system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
using namespace std;
__global__ void sum(float* input)
{
int tid = threadIdx.x;
float number_of_threads = blockDim.x;
int step_size = 1;
while(number_of_threads > 0){
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *= 2;
number_of_threads = number_of_threads!=1 ? (int)ceil(number_of_threads/2) : 0;
}
}
int main(int argc, char const *argv[])
{
// User input
int count;
cout << "Enter size : ";
cin >> count;
// Host array
float hostArray[count];
for (int i = 0; i < count; i++)
hostArray[i] = rand()%count+1;
// Device array
float *deviceArray;
cudaMalloc(&deviceArray, count*sizeof(float));
cudaMemcpy(deviceArray, hostArray, count*sizeof(float), cudaMemcpyHostToDevice);
// Cuda code
sum<<<1, (count/2)+1>>>(deviceArray);
float mean;
cudaMemcpy(&mean, deviceArray, sizeof(float), cudaMemcpyDeviceToHost);
mean = (float)mean/count;
cout << "Elements : ";
for(int i = 0; i < count; i++)
cout << hostArray[i] << " ";
cout << "\nArithmetic mean: " << mean << endl;
// Recalculation
for(int i = 0; i < count; i++)
hostArray[i] = (hostArray[i]-mean)*(hostArray[i]-mean);
cudaMemcpy(deviceArray, hostArray, count*sizeof(float), cudaMemcpyHostToDevice);
sum<<<1, (count/2)+1>>>(deviceArray);
float variance;
cudaMemcpy(&variance, deviceArray, sizeof(float), cudaMemcpyDeviceToHost);
variance = (float)variance/count;
cout << "Standard deviation : " << sqrt(variance) << endl;
}
/*
Enter size : 3
Elements : 2 2 1
Arithmetic mean: 1.66667
Standard deviation : 0.471404
*/ | code for sm_80
Function : _Z3sumPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fda0003f05270 */
/*0020*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0040*/ I2F.U32 R7, c[0x0][0x0] ; /* 0x0000000000077b06 */
/* 0x000e620000201000 */
/*0050*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fca0000000a00 */
/*0070*/ I2F R0, R2 ; /* 0x0000000200007306 */
/* 0x0010a20000201400 */
/*0080*/ IMAD.SHL.U32 R6, R2, 0x2, RZ ; /* 0x0000000202067824 */
/* 0x002fce00078e00ff */
/*0090*/ FSETP.GT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720b */
/* 0x004fda0003f04000 */
/*00a0*/ @P0 IMAD R4, R6, UR4, RZ ; /* 0x0000000406040c24 */
/* 0x000fe2000f8e02ff */
/*00b0*/ @P0 MOV R3, 0x4 ; /* 0x0000000400030802 */
/* 0x000fc80000000f00 */
/*00c0*/ @P0 IADD3 R2, R4.reuse, UR4, RZ ; /* 0x0000000404020c10 */
/* 0x041fe2000fffe0ff */
/*00d0*/ @P0 IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004040625 */
/* 0x000fc800078e0203 */
/*00e0*/ @P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002020625 */
/* 0x000fe200078e0203 */
/*00f0*/ @P0 LDG.E R8, [R4.64] ; /* 0x0000000604080981 */
/* 0x000eaa000c1e1900 */
/*0100*/ @P0 LDG.E R3, [R2.64] ; /* 0x0000000602030981 */
/* 0x000ea2000c1e1900 */
/*0110*/ FSETP.NEU.AND P1, PT, R7, 1, PT ; /* 0x3f8000000700780b */
/* 0x000fe20003f2d000 */
/*0120*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0130*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fd6000800063f */
/*0140*/ @P1 FMUL R11, R7, 0.5 ; /* 0x3f000000070b1820 */
/* 0x000fc80000400000 */
/*0150*/ @P1 F2I.CEIL.NTZ R10, R11 ; /* 0x0000000b000a1305 */
/* 0x000e30000020b100 */
/*0160*/ I2F R7, R10 ; /* 0x0000000a00077306 */
/* 0x0010620000201400 */
/*0170*/ @P0 FADD R9, R8, R3 ; /* 0x0000000308090221 */
/* 0x004fca0000000000 */
/*0180*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e2000c101906 */
/*0190*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f04270 */
/*01a0*/ @P0 BRA 0x90 ; /* 0xfffffee000000947 */
/* 0x003fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <math.h>
using namespace std;
__global__ void sum(float* input)
{
int tid = threadIdx.x;
float number_of_threads = blockDim.x;
int step_size = 1;
while(number_of_threads > 0){
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *= 2;
number_of_threads = number_of_threads!=1 ? (int)ceil(number_of_threads/2) : 0;
}
}
int main(int argc, char const *argv[])
{
// User input
int count;
cout << "Enter size : ";
cin >> count;
// Host array
float hostArray[count];
for (int i = 0; i < count; i++)
hostArray[i] = rand()%count+1;
// Device array
float *deviceArray;
cudaMalloc(&deviceArray, count*sizeof(float));
cudaMemcpy(deviceArray, hostArray, count*sizeof(float), cudaMemcpyHostToDevice);
// Cuda code
sum<<<1, (count/2)+1>>>(deviceArray);
float mean;
cudaMemcpy(&mean, deviceArray, sizeof(float), cudaMemcpyDeviceToHost);
mean = (float)mean/count;
cout << "Elements : ";
for(int i = 0; i < count; i++)
cout << hostArray[i] << " ";
cout << "\nArithmetic mean: " << mean << endl;
// Recalculation
for(int i = 0; i < count; i++)
hostArray[i] = (hostArray[i]-mean)*(hostArray[i]-mean);
cudaMemcpy(deviceArray, hostArray, count*sizeof(float), cudaMemcpyHostToDevice);
sum<<<1, (count/2)+1>>>(deviceArray);
float variance;
cudaMemcpy(&variance, deviceArray, sizeof(float), cudaMemcpyDeviceToHost);
variance = (float)variance/count;
cout << "Standard deviation : " << sqrt(variance) << endl;
}
/*
Enter size : 3
Elements : 2 2 1
Arithmetic mean: 1.66667
Standard deviation : 0.471404
*/ | .file "tmpxft_0011c936_00000000-6_mean_and_stddev.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3sumPfPf
.type _Z22__device_stub__Z3sumPfPf, @function
_Z22__device_stub__Z3sumPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z3sumPfPf, .-_Z22__device_stub__Z3sumPfPf
.globl _Z3sumPf
.type _Z3sumPf, @function
_Z3sumPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3sumPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3sumPf, .-_Z3sumPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter size : "
.LC1:
.string "Elements : "
.LC2:
.string " "
.LC3:
.string "\nArithmetic mean: "
.LC4:
.string "Standard deviation : "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $48, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -80(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl -80(%rbp), %esi
movslq %esi, %rax
leaq 15(,%rax,4), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
testl %esi, %esi
jle .L15
movl $0, %r12d
.L16:
call rand@PLT
movl -80(%rbp), %esi
cltd
idivl %esi
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%r12,4)
addq $1, %r12
cmpl %r12d, %esi
jg .L16
.L15:
movslq %esi, %rsi
salq $2, %rsi
leaq -72(%rbp), %rdi
call cudaMalloc@PLT
movslq -80(%rbp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
movl -80(%rbp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl $1, %eax
movl %eax, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L17:
leaq -76(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -72(%rbp), %rsi
call cudaMemcpy@PLT
pxor %xmm1, %xmm1
cvtsi2ssl -80(%rbp), %xmm1
movss -76(%rbp), %xmm0
divss %xmm1, %xmm0
movss %xmm0, -76(%rbp)
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -80(%rbp)
jle .L18
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC2(%rip), %r13
.L19:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, -80(%rbp)
jg .L19
.L18:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -76(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -80(%rbp), %edx
testl %edx, %edx
jle .L20
movss -76(%rbp), %xmm1
movq %rbx, %rax
movslq %edx, %rcx
leaq (%rbx,%rcx,4), %rcx
.L21:
movss (%rax), %xmm0
subss %xmm1, %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rcx
jne .L21
.L20:
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
movl -80(%rbp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl $1, %eax
movl %eax, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L22:
leaq -52(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -72(%rbp), %rsi
call cudaMemcpy@PLT
pxor %xmm1, %xmm1
cvtsi2ssl -80(%rbp), %xmm1
movss -52(%rbp), %xmm0
divss %xmm1, %xmm0
movss %xmm0, -52(%rbp)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movss -52(%rbp), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L31
sqrtss %xmm0, %xmm0
.L25:
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L33:
.cfi_restore_state
movq -72(%rbp), %rdi
call _Z22__device_stub__Z3sumPfPf
jmp .L17
.L34:
movq -72(%rbp), %rdi
call _Z22__device_stub__Z3sumPfPf
jmp .L22
.L31:
call sqrtf@PLT
jmp .L25
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3sumPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <math.h>
using namespace std;
__global__ void sum(float* input)
{
int tid = threadIdx.x;
float number_of_threads = blockDim.x;
int step_size = 1;
while(number_of_threads > 0){
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *= 2;
number_of_threads = number_of_threads!=1 ? (int)ceil(number_of_threads/2) : 0;
}
}
int main(int argc, char const *argv[])
{
// User input
int count;
cout << "Enter size : ";
cin >> count;
// Host array
float hostArray[count];
for (int i = 0; i < count; i++)
hostArray[i] = rand()%count+1;
// Device array
float *deviceArray;
cudaMalloc(&deviceArray, count*sizeof(float));
cudaMemcpy(deviceArray, hostArray, count*sizeof(float), cudaMemcpyHostToDevice);
// Cuda code
sum<<<1, (count/2)+1>>>(deviceArray);
float mean;
cudaMemcpy(&mean, deviceArray, sizeof(float), cudaMemcpyDeviceToHost);
mean = (float)mean/count;
cout << "Elements : ";
for(int i = 0; i < count; i++)
cout << hostArray[i] << " ";
cout << "\nArithmetic mean: " << mean << endl;
// Recalculation
for(int i = 0; i < count; i++)
hostArray[i] = (hostArray[i]-mean)*(hostArray[i]-mean);
cudaMemcpy(deviceArray, hostArray, count*sizeof(float), cudaMemcpyHostToDevice);
sum<<<1, (count/2)+1>>>(deviceArray);
float variance;
cudaMemcpy(&variance, deviceArray, sizeof(float), cudaMemcpyDeviceToHost);
variance = (float)variance/count;
cout << "Standard deviation : " << sqrt(variance) << endl;
}
/*
Enter size : 3
Elements : 2 2 1
Arithmetic mean: 1.66667
Standard deviation : 0.471404
*/ | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
using namespace std;
__global__ void sum(float* input)
{
int tid = threadIdx.x;
float number_of_threads = blockDim.x;
int step_size = 1;
while(number_of_threads > 0){
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *= 2;
number_of_threads = number_of_threads!=1 ? (int)ceil(number_of_threads/2) : 0;
}
}
int main(int argc, char const *argv[])
{
// User input
int count;
cout << "Enter size : ";
cin >> count;
// Host array
float hostArray[count];
for (int i = 0; i < count; i++)
hostArray[i] = rand()%count+1;
// Device array
float *deviceArray;
hipMalloc(&deviceArray, count*sizeof(float));
hipMemcpy(deviceArray, hostArray, count*sizeof(float), hipMemcpyHostToDevice);
// Cuda code
sum<<<1, (count/2)+1>>>(deviceArray);
float mean;
hipMemcpy(&mean, deviceArray, sizeof(float), hipMemcpyDeviceToHost);
mean = (float)mean/count;
cout << "Elements : ";
for(int i = 0; i < count; i++)
cout << hostArray[i] << " ";
cout << "\nArithmetic mean: " << mean << endl;
// Recalculation
for(int i = 0; i < count; i++)
hostArray[i] = (hostArray[i]-mean)*(hostArray[i]-mean);
hipMemcpy(deviceArray, hostArray, count*sizeof(float), hipMemcpyHostToDevice);
sum<<<1, (count/2)+1>>>(deviceArray);
float variance;
hipMemcpy(&variance, deviceArray, sizeof(float), hipMemcpyDeviceToHost);
variance = (float)variance/count;
cout << "Standard deviation : " << sqrt(variance) << endl;
}
/*
Enter size : 3
Elements : 2 2 1
Arithmetic mean: 1.66667
Standard deviation : 0.471404
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
using namespace std;
__global__ void sum(float* input)
{
int tid = threadIdx.x;
float number_of_threads = blockDim.x;
int step_size = 1;
while(number_of_threads > 0){
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *= 2;
number_of_threads = number_of_threads!=1 ? (int)ceil(number_of_threads/2) : 0;
}
}
int main(int argc, char const *argv[])
{
// User input
int count;
cout << "Enter size : ";
cin >> count;
// Host array
float hostArray[count];
for (int i = 0; i < count; i++)
hostArray[i] = rand()%count+1;
// Device array
float *deviceArray;
hipMalloc(&deviceArray, count*sizeof(float));
hipMemcpy(deviceArray, hostArray, count*sizeof(float), hipMemcpyHostToDevice);
// Cuda code
sum<<<1, (count/2)+1>>>(deviceArray);
float mean;
hipMemcpy(&mean, deviceArray, sizeof(float), hipMemcpyDeviceToHost);
mean = (float)mean/count;
cout << "Elements : ";
for(int i = 0; i < count; i++)
cout << hostArray[i] << " ";
cout << "\nArithmetic mean: " << mean << endl;
// Recalculation
for(int i = 0; i < count; i++)
hostArray[i] = (hostArray[i]-mean)*(hostArray[i]-mean);
hipMemcpy(deviceArray, hostArray, count*sizeof(float), hipMemcpyHostToDevice);
sum<<<1, (count/2)+1>>>(deviceArray);
float variance;
hipMemcpy(&variance, deviceArray, sizeof(float), hipMemcpyDeviceToHost);
variance = (float)variance/count;
cout << "Standard deviation : " << sqrt(variance) << endl;
}
/*
Enter size : 3
Elements : 2 2 1
Arithmetic mean: 1.66667
Standard deviation : 0.471404
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPf
.globl _Z3sumPf
.p2align 8
.type _Z3sumPf,@function
_Z3sumPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
s_and_b32 s2, 0xffff, s2
v_cvt_f32_i32_e32 v1, v0
v_cvt_f32_u32_e32 v2, s2
v_lshlrev_b32_e32 v0, 1, v0
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_mul_f32_e32 v3, 0.5, v2
v_cmp_neq_f32_e32 vcc_lo, 1.0, v2
s_lshl_b32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ceil_f32_e32 v3, v3
v_cvt_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, v3
v_cndmask_b32_e32 v2, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, 0, v2
s_cbranch_vccz .LBB0_5
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_gt_f32_e32 v2, v1
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v3, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s2, v3
v_mov_b32_e32 v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPf, .Lfunc_end0-_Z3sumPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPf
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z3sumPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <math.h>
using namespace std;
__global__ void sum(float* input)
{
int tid = threadIdx.x;
float number_of_threads = blockDim.x;
int step_size = 1;
while(number_of_threads > 0){
if(tid < number_of_threads)
{
int first = tid*step_size*2;
int second = first + step_size;
input[first] += input[second];
}
step_size *= 2;
number_of_threads = number_of_threads!=1 ? (int)ceil(number_of_threads/2) : 0;
}
}
int main(int argc, char const *argv[])
{
// User input
int count;
cout << "Enter size : ";
cin >> count;
// Host array
float hostArray[count];
for (int i = 0; i < count; i++)
hostArray[i] = rand()%count+1;
// Device array
float *deviceArray;
hipMalloc(&deviceArray, count*sizeof(float));
hipMemcpy(deviceArray, hostArray, count*sizeof(float), hipMemcpyHostToDevice);
// Cuda code
sum<<<1, (count/2)+1>>>(deviceArray);
float mean;
hipMemcpy(&mean, deviceArray, sizeof(float), hipMemcpyDeviceToHost);
mean = (float)mean/count;
cout << "Elements : ";
for(int i = 0; i < count; i++)
cout << hostArray[i] << " ";
cout << "\nArithmetic mean: " << mean << endl;
// Recalculation
for(int i = 0; i < count; i++)
hostArray[i] = (hostArray[i]-mean)*(hostArray[i]-mean);
hipMemcpy(deviceArray, hostArray, count*sizeof(float), hipMemcpyHostToDevice);
sum<<<1, (count/2)+1>>>(deviceArray);
float variance;
hipMemcpy(&variance, deviceArray, sizeof(float), hipMemcpyDeviceToHost);
variance = (float)variance/count;
cout << "Standard deviation : " << sqrt(variance) << endl;
}
/*
Enter size : 3
Elements : 2 2 1
Arithmetic mean: 1.66667
Standard deviation : 0.471404
*/ | .text
.file "mean_and_stddev.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__sumPf # -- Begin function _Z18__device_stub__sumPf
.p2align 4, 0x90
.type _Z18__device_stub__sumPf,@function
_Z18__device_stub__sumPf: # @_Z18__device_stub__sumPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3sumPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPf, .Lfunc_end0-_Z18__device_stub__sumPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq -44(%rbp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq %rsp, %r12
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl -44(%rbp)
incl %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
movslq -44(%rbp), %rax
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movabsq $4294967296, %r14 # imm = 0x100000000
movslq %eax, %rsi
shlq $2, %rsi
leaq -56(%rbp), %rdi
callq hipMalloc
movq -56(%rbp), %rdi
movslq -44(%rbp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl -44(%rbp), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
incl %edx
orq %r14, %rdx
leaq 1(%r14), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq -56(%rbp), %rax
movq %rax, -120(%rbp)
leaq -120(%rbp), %rax
movq %rax, -80(%rbp)
leaq -72(%rbp), %rdi
leaq -112(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -72(%rbp), %rsi
movl -64(%rbp), %edx
movq -112(%rbp), %rcx
movl -104(%rbp), %r8d
leaq -80(%rbp), %r9
movl $_Z3sumPf, %edi
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_5:
movq -56(%rbp), %rsi
leaq -48(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
movss -48(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, -48(%rbp)
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, -44(%rbp)
jle .LBB1_8
# %bb.6: # %.lr.ph46.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.lr.ph46
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
movslq -44(%rbp), %rax
cmpq %rax, %r15
jl .LBB1_7
.LBB1_8: # %._crit_edge47
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -48(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_25
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r15, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_15
# %bb.13: # %.lr.ph49
movss -48(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss %xmm1, %xmm1
movss %xmm1, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_14
.LBB1_15: # %._crit_edge50
movq -56(%rbp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl -44(%rbp), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
incl %edx
orq %r14, %rdx
incq %r14
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16:
movq -56(%rbp), %rax
movq %rax, -120(%rbp)
leaq -120(%rbp), %rax
movq %rax, -80(%rbp)
leaq -72(%rbp), %rdi
leaq -112(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -72(%rbp), %rsi
movl -64(%rbp), %edx
movq -112(%rbp), %rcx
movl -104(%rbp), %r8d
leaq -80(%rbp), %r9
movl $_Z3sumPf, %edi
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_17:
movq -56(%rbp), %rsi
leaq -72(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
movss -72(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, -72(%rbp)
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -72(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB1_19
# %bb.18:
sqrtss %xmm0, %xmm0
jmp .LBB1_20
.LBB1_19: # %call.sqrt
callq sqrtf
.LBB1_20: # %.split
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_25
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%rbx)
je .LBB1_23
# %bb.22:
movzbl 67(%rbx), %ecx
jmp .LBB1_24
.LBB1_23:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r12, %rsp
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_25:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPf,@object # @_Z3sumPf
.section .rodata,"a",@progbits
.globl _Z3sumPf
.p2align 3, 0x0
_Z3sumPf:
.quad _Z18__device_stub__sumPf
.size _Z3sumPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter size : "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elements : "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nArithmetic mean: "
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Standard deviation : "
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPf"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPf
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fda0003f05270 */
/*0020*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0040*/ I2F.U32 R7, c[0x0][0x0] ; /* 0x0000000000077b06 */
/* 0x000e620000201000 */
/*0050*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fca0000000a00 */
/*0070*/ I2F R0, R2 ; /* 0x0000000200007306 */
/* 0x0010a20000201400 */
/*0080*/ IMAD.SHL.U32 R6, R2, 0x2, RZ ; /* 0x0000000202067824 */
/* 0x002fce00078e00ff */
/*0090*/ FSETP.GT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720b */
/* 0x004fda0003f04000 */
/*00a0*/ @P0 IMAD R4, R6, UR4, RZ ; /* 0x0000000406040c24 */
/* 0x000fe2000f8e02ff */
/*00b0*/ @P0 MOV R3, 0x4 ; /* 0x0000000400030802 */
/* 0x000fc80000000f00 */
/*00c0*/ @P0 IADD3 R2, R4.reuse, UR4, RZ ; /* 0x0000000404020c10 */
/* 0x041fe2000fffe0ff */
/*00d0*/ @P0 IMAD.WIDE R4, R4, R3, c[0x0][0x160] ; /* 0x0000580004040625 */
/* 0x000fc800078e0203 */
/*00e0*/ @P0 IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002020625 */
/* 0x000fe200078e0203 */
/*00f0*/ @P0 LDG.E R8, [R4.64] ; /* 0x0000000604080981 */
/* 0x000eaa000c1e1900 */
/*0100*/ @P0 LDG.E R3, [R2.64] ; /* 0x0000000602030981 */
/* 0x000ea2000c1e1900 */
/*0110*/ FSETP.NEU.AND P1, PT, R7, 1, PT ; /* 0x3f8000000700780b */
/* 0x000fe20003f2d000 */
/*0120*/ HFMA2.MMA R10, -RZ, RZ, 0, 0 ; /* 0x00000000ff0a7435 */
/* 0x000fe200000001ff */
/*0130*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fd6000800063f */
/*0140*/ @P1 FMUL R11, R7, 0.5 ; /* 0x3f000000070b1820 */
/* 0x000fc80000400000 */
/*0150*/ @P1 F2I.CEIL.NTZ R10, R11 ; /* 0x0000000b000a1305 */
/* 0x000e30000020b100 */
/*0160*/ I2F R7, R10 ; /* 0x0000000a00077306 */
/* 0x0010620000201400 */
/*0170*/ @P0 FADD R9, R8, R3 ; /* 0x0000000308090221 */
/* 0x004fca0000000000 */
/*0180*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e2000c101906 */
/*0190*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f04270 */
/*01a0*/ @P0 BRA 0x90 ; /* 0xfffffee000000947 */
/* 0x003fea000383ffff */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPf
.globl _Z3sumPf
.p2align 8
.type _Z3sumPf,@function
_Z3sumPf:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s3, s2, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
s_and_b32 s2, 0xffff, s2
v_cvt_f32_i32_e32 v1, v0
v_cvt_f32_u32_e32 v2, s2
v_lshlrev_b32_e32 v0, 1, v0
s_mov_b32 s2, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_mul_f32_e32 v3, 0.5, v2
v_cmp_neq_f32_e32 vcc_lo, 1.0, v2
s_lshl_b32 s2, s2, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ceil_f32_e32 v3, v3
v_cvt_i32_f32_e32 v3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v3, v3
v_cndmask_b32_e32 v2, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f32_e32 vcc_lo, 0, v2
s_cbranch_vccz .LBB0_5
.LBB0_3:
s_mov_b32 s3, exec_lo
v_cmpx_gt_f32_e32 v2, v1
s_cbranch_execz .LBB0_2
v_mul_lo_u32 v3, v0, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v5, s2, v3
v_mov_b32_e32 v4, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_clause 0x1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_b32 v[3:4], v5, off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPf, .Lfunc_end0-_Z3sumPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPf
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z3sumPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011c936_00000000-6_mean_and_stddev.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3sumPfPf
.type _Z22__device_stub__Z3sumPfPf, @function
_Z22__device_stub__Z3sumPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z3sumPfPf, .-_Z22__device_stub__Z3sumPfPf
.globl _Z3sumPf
.type _Z3sumPf, @function
_Z3sumPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3sumPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3sumPf, .-_Z3sumPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter size : "
.LC1:
.string "Elements : "
.LC2:
.string " "
.LC3:
.string "\nArithmetic mean: "
.LC4:
.string "Standard deviation : "
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $48, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq -80(%rbp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl -80(%rbp), %esi
movslq %esi, %rax
leaq 15(,%rax,4), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L12:
cmpq %rdx, %rsp
je .L13
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L12
.L13:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L14
orq $0, -8(%rsp,%rax)
.L14:
movq %rsp, %rbx
testl %esi, %esi
jle .L15
movl $0, %r12d
.L16:
call rand@PLT
movl -80(%rbp), %esi
cltd
idivl %esi
addl $1, %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%r12,4)
addq $1, %r12
cmpl %r12d, %esi
jg .L16
.L15:
movslq %esi, %rsi
salq $2, %rsi
leaq -72(%rbp), %rdi
call cudaMalloc@PLT
movslq -80(%rbp), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
movl -80(%rbp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl $1, %eax
movl %eax, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L17:
leaq -76(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -72(%rbp), %rsi
call cudaMemcpy@PLT
pxor %xmm1, %xmm1
cvtsi2ssl -80(%rbp), %xmm1
movss -76(%rbp), %xmm0
divss %xmm1, %xmm0
movss %xmm0, -76(%rbp)
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
cmpl $0, -80(%rbp)
jle .L18
movl $0, %r12d
leaq _ZSt4cout(%rip), %r14
leaq .LC2(%rip), %r13
.L19:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12,4), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %r12
cmpl %r12d, -80(%rbp)
jg .L19
.L18:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd -76(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl -80(%rbp), %edx
testl %edx, %edx
jle .L20
movss -76(%rbp), %xmm1
movq %rbx, %rax
movslq %edx, %rcx
leaq (%rbx,%rcx,4), %rcx
.L21:
movss (%rax), %xmm0
subss %xmm1, %xmm0
mulss %xmm0, %xmm0
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rax, %rcx
jne .L21
.L20:
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq -72(%rbp), %rdi
call cudaMemcpy@PLT
movl -80(%rbp), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
addl $1, %eax
movl %eax, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $1, -64(%rbp)
movl $1, -60(%rbp)
movl $1, -56(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L22:
leaq -52(%rbp), %rdi
movl $2, %ecx
movl $4, %edx
movq -72(%rbp), %rsi
call cudaMemcpy@PLT
pxor %xmm1, %xmm1
cvtsi2ssl -80(%rbp), %xmm1
movss -52(%rbp), %xmm0
divss %xmm1, %xmm0
movss %xmm0, -52(%rbp)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movss -52(%rbp), %xmm0
pxor %xmm1, %xmm1
ucomiss %xmm0, %xmm1
ja .L31
sqrtss %xmm0, %xmm0
.L25:
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L33:
.cfi_restore_state
movq -72(%rbp), %rdi
call _Z22__device_stub__Z3sumPfPf
jmp .L17
.L34:
movq -72(%rbp), %rdi
call _Z22__device_stub__Z3sumPfPf
jmp .L22
.L31:
call sqrtf@PLT
jmp .L25
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z3sumPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mean_and_stddev.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__sumPf # -- Begin function _Z18__device_stub__sumPf
.p2align 4, 0x90
.type _Z18__device_stub__sumPf,@function
_Z18__device_stub__sumPf: # @_Z18__device_stub__sumPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3sumPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPf, .Lfunc_end0-_Z18__device_stub__sumPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq -44(%rbp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movq %rsp, %r12
movl -44(%rbp), %eax
movq %rsp, %rbx
leaq 15(,%rax,4), %rax
andq $-16, %rax
subq %rax, %rbx
movq %rbx, %rsp
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl -44(%rbp)
incl %edx
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
movslq -44(%rbp), %rax
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
movabsq $4294967296, %r14 # imm = 0x100000000
movslq %eax, %rsi
shlq $2, %rsi
leaq -56(%rbp), %rdi
callq hipMalloc
movq -56(%rbp), %rdi
movslq -44(%rbp), %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl -44(%rbp), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
incl %edx
orq %r14, %rdx
leaq 1(%r14), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq -56(%rbp), %rax
movq %rax, -120(%rbp)
leaq -120(%rbp), %rax
movq %rax, -80(%rbp)
leaq -72(%rbp), %rdi
leaq -112(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -72(%rbp), %rsi
movl -64(%rbp), %edx
movq -112(%rbp), %rcx
movl -104(%rbp), %r8d
leaq -80(%rbp), %r9
movl $_Z3sumPf, %edi
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_5:
movq -56(%rbp), %rsi
leaq -48(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
movss -48(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, -48(%rbp)
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
cmpl $0, -44(%rbp)
jle .LBB1_8
# %bb.6: # %.lr.ph46.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # %.lr.ph46
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
movslq -44(%rbp), %rax
cmpq %rax, %r15
jl .LBB1_7
.LBB1_8: # %._crit_edge47
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -48(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_25
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_11
# %bb.10:
movzbl 67(%r15), %ecx
jmp .LBB1_12
.LBB1_11:
movq %r15, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl -44(%rbp), %eax
testl %eax, %eax
jle .LBB1_15
# %bb.13: # %.lr.ph49
movss -48(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_14: # =>This Inner Loop Header: Depth=1
movss (%rbx,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
subss %xmm0, %xmm1
mulss %xmm1, %xmm1
movss %xmm1, (%rbx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_14
.LBB1_15: # %._crit_edge50
movq -56(%rbp), %rdi
movslq %eax, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl -44(%rbp), %eax
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
incl %edx
orq %r14, %rdx
incq %r14
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_17
# %bb.16:
movq -56(%rbp), %rax
movq %rax, -120(%rbp)
leaq -120(%rbp), %rax
movq %rax, -80(%rbp)
leaq -72(%rbp), %rdi
leaq -112(%rbp), %rsi
leaq -96(%rbp), %rdx
leaq -88(%rbp), %rcx
callq __hipPopCallConfiguration
movq -72(%rbp), %rsi
movl -64(%rbp), %edx
movq -112(%rbp), %rcx
movl -104(%rbp), %r8d
leaq -80(%rbp), %r9
movl $_Z3sumPf, %edi
pushq -88(%rbp)
pushq -96(%rbp)
callq hipLaunchKernel
addq $16, %rsp
.LBB1_17:
movq -56(%rbp), %rsi
leaq -72(%rbp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
xorps %xmm0, %xmm0
cvtsi2ssl -44(%rbp), %xmm0
movss -72(%rbp), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
movss %xmm1, -72(%rbp)
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss -72(%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
ucomiss %xmm1, %xmm0
jb .LBB1_19
# %bb.18:
sqrtss %xmm0, %xmm0
jmp .LBB1_20
.LBB1_19: # %call.sqrt
callq sqrtf
.LBB1_20: # %.split
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_25
# %bb.21: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i29
cmpb $0, 56(%rbx)
je .LBB1_23
# %bb.22:
movzbl 67(%rbx), %ecx
jmp .LBB1_24
.LBB1_23:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_24: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit32
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r12, %rsp
xorl %eax, %eax
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB1_25:
.cfi_def_cfa %rbp, 16
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPf,@object # @_Z3sumPf
.section .rodata,"a",@progbits
.globl _Z3sumPf
.p2align 3, 0x0
_Z3sumPf:
.quad _Z18__device_stub__sumPf
.size _Z3sumPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter size : "
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Elements : "
.size .L.str.1, 12
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " "
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nArithmetic mean: "
.size .L.str.3, 19
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Standard deviation : "
.size .L.str.4, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3sumPf"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPf
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
__global__ void gSumVector(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
__global__ void gScalarMultVect(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
printf("Device does not support overlapping\n");
return 0;
}
float time1, time2, time3, time4;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *host_a, *host_b, *host_c;
cudaHostAlloc((void**) &host_a, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
cudaHostAlloc((void**) &host_b, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
cudaHostAlloc((void**) &host_c, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**) &dev_a, N * sizeof(int));
cudaMalloc((void**) &dev_b, N * sizeof(int));
cudaMalloc((void**) &dev_c, N * sizeof(int));
int *dev_a0, *dev_a1, *dev_b0, *dev_b1, *dev_c0, *dev_c1;
cudaMalloc((void**) &dev_a0, N * sizeof(int));
cudaMalloc((void**) &dev_a1, N * sizeof(int));
cudaMalloc((void**) &dev_b0, N * sizeof(int));
cudaMalloc((void**) &dev_b1, N * sizeof(int));
cudaMalloc((void**) &dev_c0, N * sizeof(int));
cudaMalloc((void**) &dev_c1, N * sizeof(int));
cudaStream_t stream, stream0, stream1;
cudaStreamCreate(&stream);
cudaStreamCreate(&stream0);
cudaStreamCreate(&stream1);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpyAsync(dev_a, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(dev_b, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
kernel<<<N / 256, 256, 0, stream>>>(dev_a, dev_b, dev_c);
cudaMemcpyAsync(host_c + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost, stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time1, start, stop);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
cudaMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
cudaMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
cudaMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
cudaMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time2, start, stop);
cudaEventRecord(start,0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
cudaMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
cudaMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
cudaMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time3, start, stop);
int *host_a1, *host_b1, *host_c1;
host_a1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_b1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_c1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpy(dev_a, host_a1 + i, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b1 + i, N * sizeof(int), cudaMemcpyHostToDevice);
kernel<<<N / 256, 256>>>(dev_a, dev_b, dev_c);
cudaMemcpy(host_c1 + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time4, start, stop);
printf("%.4f ms\n", time1);
printf("%.4f ms\n", time2);
printf("%.4f ms\n", time3);
printf("%.4f ms\n", time4);
free(host_a1);
free(host_b1);
free(host_c1);
cudaStreamDestroy(stream);
cudaStreamDestroy(stream0);
cudaStreamDestroy(stream1);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
cudaFree(dev_a0);
cudaFree(dev_a1);
cudaFree(dev_b0);
cudaFree(dev_b1);
cudaFree(dev_c0);
cudaFree(dev_c1);
cudaFreeHost(host_a);
cudaFreeHost(host_b);
cudaFreeHost(host_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | code for sm_80
Function : _Z15gScalarMultVectPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xfffff, PT ; /* 0x000fffff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10gSumVectorPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0xfffff, PT ; /* 0x000fffff0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6kernelPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xfffff, PT ; /* 0x000fffff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R3, R0.reuse, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0080*/ IADD3 R4, R0, 0x2, RZ ; /* 0x0000000200047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ SHF.R.S32.HI R2, RZ, 0x1f, R3 ; /* 0x0000001fff027819 */
/* 0x000fe40000011403 */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*00c0*/ LEA.HI R2, R2, R3, RZ, 0x8 ; /* 0x0000000302027211 */
/* 0x000fe400078f40ff */
/*00d0*/ LEA.HI R5, R5, R4, RZ, 0x8 ; /* 0x0000000405057211 */
/* 0x000fc400078f40ff */
/*00e0*/ LOP3.LUT R2, R2, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0002027812 */
/* 0x000fe400078ec0ff */
/*00f0*/ LOP3.LUT R5, R5, 0xffffff00, RZ, 0xc0, !PT ; /* 0xffffff0005057812 */
/* 0x000fc600078ec0ff */
/*0100*/ IMAD.IADD R3, R3, 0x1, -R2 ; /* 0x0000000103037824 */
/* 0x000fe400078e0a02 */
/*0110*/ IMAD.IADD R2, R4, 0x1, -R5 ; /* 0x0000000104027824 */
/* 0x000fe400078e0a05 */
/*0120*/ IMAD.WIDE R4, R0, R9, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0209 */
/*0130*/ IMAD.WIDE R6, R3, R9.reuse, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x080fe400078e0209 */
/*0140*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0150*/ IMAD.WIDE R8, R2, R9, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x000fe400078e0209 */
/*0160*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0c7424 */
/* 0x000fc400078e00ff */
/*0190*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*01a0*/ FFMA R11, R12, -R13, 1 ; /* 0x3f8000000c0b7423 */
/* 0x000fc8000000080d */
/*01b0*/ FFMA R11, R11, R12, 0.3333333432674407959 ; /* 0x3eaaaaab0b0b7423 */
/* 0x000fe2000000000c */
/*01c0*/ BSSY B0, 0x280 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*01d0*/ IADD3 R10, R8, R6, R5 ; /* 0x00000006080a7210 */
/* 0x004fcc0007ffe005 */
/*01e0*/ I2F R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e300000201400 */
/*01f0*/ FCHK P0, R10, 3 ; /* 0x404000000a007902 */
/* 0x001e220000000000 */
/*0200*/ FFMA R12, R10, R11, RZ ; /* 0x0000000b0a0c7223 */
/* 0x000fc800000000ff */
/*0210*/ FFMA R4, R12, -3, R10 ; /* 0xc04000000c047823 */
/* 0x000fc8000000000a */
/*0220*/ FFMA R4, R11, R4, R12 ; /* 0x000000040b047223 */
/* 0x000fe2000000000c */
/*0230*/ @!P0 BRA 0x270 ; /* 0x0000003000008947 */
/* 0x001fea0003800000 */
/*0240*/ MOV R6, 0x260 ; /* 0x0000026000067802 */
/* 0x000fe40000000f00 */
/*0250*/ CALL.REL.NOINC 0x470 ; /* 0x0000021000007944 */
/* 0x000fea0003c00000 */
/*0260*/ IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff047224 */
/* 0x001fe400078e0005 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0290*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fc800078e0205 */
/*02a0*/ IMAD.WIDE R6, R0, R5.reuse, c[0x0][0x168] ; /* 0x00005a0000067625 */
/* 0x080fe400078e0205 */
/*02b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0205 */
/*02d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea8000c1e1900 */
/*02e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3eaaaaab ; /* 0x3eaaaaabff0a7424 */
/* 0x000fc400078e00ff */
/*0300*/ IMAD.MOV.U32 R13, RZ, RZ, 0x40400000 ; /* 0x40400000ff0d7424 */
/* 0x000fc800078e00ff */
/*0310*/ FFMA R11, R10, -R13, 1 ; /* 0x3f8000000a0b7423 */
/* 0x000fc8000000080d */
/*0320*/ FFMA R12, R11, R10, 0.3333333432674407959 ; /* 0x3eaaaaab0b0c7423 */
/* 0x000fe2000000000a */
/*0330*/ BSSY B0, 0x400 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R5, R2, R8, R7 ; /* 0x0000000802057210 */
/* 0x004fcc0007ffe007 */
/*0350*/ I2F R5, R5 ; /* 0x0000000500057306 */
/* 0x000e300000201400 */
/*0360*/ FCHK P0, R5, 3 ; /* 0x4040000005007902 */
/* 0x001e220000000000 */
/*0370*/ FFMA R10, R12, R5, RZ ; /* 0x000000050c0a7223 */
/* 0x000fc800000000ff */
/*0380*/ FFMA R9, R10, -3, R5 ; /* 0xc04000000a097823 */
/* 0x000fc80000000005 */
/*0390*/ FFMA R9, R12, R9, R10 ; /* 0x000000090c097223 */
/* 0x000fe2000000000a */
/*03a0*/ @!P0 BRA 0x3f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*03b0*/ IMAD.MOV.U32 R10, RZ, RZ, R5 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0005 */
/*03c0*/ MOV R6, 0x3e0 ; /* 0x000003e000067802 */
/* 0x000fe40000000f00 */
/*03d0*/ CALL.REL.NOINC 0x470 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x001fe400078e0005 */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ FADD R4, R9, R4 ; /* 0x0000000409047221 */
/* 0x000fe40000000000 */
/*0410*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0420*/ FMUL R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000400000 */
/*0430*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fe400078e0203 */
/*0440*/ F2I.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000e26000020f100 */
/*0450*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0460*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0470*/ SHF.R.U32.HI R7, RZ, 0x17, R13.reuse ; /* 0x00000017ff077819 */
/* 0x100fe2000001160d */
/*0480*/ BSSY B1, 0xad0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0490*/ SHF.R.U32.HI R5, RZ, 0x17, R10 ; /* 0x00000017ff057819 */
/* 0x000fe2000001160a */
/*04a0*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000d */
/*04b0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fc400078ec0ff */
/*04c0*/ LOP3.LUT R14, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050e7812 */
/* 0x000fe200078ec0ff */
/*04d0*/ IMAD.MOV.U32 R5, RZ, RZ, R10 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000a */
/*04e0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ IADD3 R12, R14, -0x1, RZ ; /* 0xffffffff0e0c7810 */
/* 0x000fe40007ffe0ff */
/*0500*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0510*/ ISETP.GT.U32.OR P0, PT, R12, 0xfd, P0 ; /* 0x000000fd0c00780c */
/* 0x000fda0000704470 */
/*0520*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0530*/ @!P0 BRA 0x6b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0540*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fe40003f1c200 */
/*0550*/ FSETP.GTU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fc80003f3c200 */
/*0560*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0570*/ @P0 BRA 0xab0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0580*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c805 */
/*0590*/ @!P0 BRA 0xa90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.NEU.FTZ.AND P2, PT, |R10|.reuse, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x040fe40003f5d200 */
/*05b0*/ FSETP.NEU.FTZ.AND P1, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f3d200 */
/*05c0*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fd60003f1d200 */
/*05d0*/ @!P1 BRA !P2, 0xa90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*05e0*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*05f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0600*/ @P1 BRA 0xa70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0610*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0620*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0630*/ @P0 BRA 0xa40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe40003f06270 */
/*0650*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0660*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0670*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0680*/ @!P0 FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a058823 */
/* 0x000fe400000000ff */
/*0690*/ @!P1 FFMA R8, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d089823 */
/* 0x000fe200000000ff */
/*06a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*06b0*/ LEA R11, R7, 0xc0800000, 0x17 ; /* 0xc0800000070b7811 */
/* 0x000fe200078eb8ff */
/*06c0*/ BSSY B2, 0xa30 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*06d0*/ IMAD.IADD R11, R8, 0x1, -R11 ; /* 0x00000001080b7824 */
/* 0x000fe200078e0a0b */
/*06e0*/ IADD3 R8, R14, -0x7f, RZ ; /* 0xffffff810e087810 */
/* 0x000fc60007ffe0ff */
/*06f0*/ MUFU.RCP R10, R11 ; /* 0x0000000b000a7308 */
/* 0x000e220000001000 */
/*0700*/ FADD.FTZ R12, -R11, -RZ ; /* 0x800000ff0b0c7221 */
/* 0x000fe40000010100 */
/*0710*/ IMAD R5, R8.reuse, -0x800000, R5 ; /* 0xff80000008057824 */
/* 0x040fe200078e0205 */
/*0720*/ IADD3 R8, R8, 0x7f, -R7 ; /* 0x0000007f08087810 */
/* 0x000fca0007ffe807 */
/*0730*/ IMAD.IADD R8, R8, 0x1, R9 ; /* 0x0000000108087824 */
/* 0x000fe400078e0209 */
/*0740*/ FFMA R13, R10, R12, 1 ; /* 0x3f8000000a0d7423 */
/* 0x001fc8000000000c */
/*0750*/ FFMA R14, R10, R13, R10 ; /* 0x0000000d0a0e7223 */
/* 0x000fc8000000000a */
/*0760*/ FFMA R10, R5, R14, RZ ; /* 0x0000000e050a7223 */
/* 0x000fc800000000ff */
/*0770*/ FFMA R13, R12, R10, R5 ; /* 0x0000000a0c0d7223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R13, R14, R13, R10 ; /* 0x0000000d0e0d7223 */
/* 0x000fc8000000000a */
/*0790*/ FFMA R12, R12, R13, R5 ; /* 0x0000000d0c0c7223 */
/* 0x000fc80000000005 */
/*07a0*/ FFMA R5, R14, R12, R13 ; /* 0x0000000c0e057223 */
/* 0x000fca000000000d */
/*07b0*/ SHF.R.U32.HI R7, RZ, 0x17, R5 ; /* 0x00000017ff077819 */
/* 0x000fc80000011605 */
/*07c0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fca00078ec0ff */
/*07d0*/ IMAD.IADD R11, R7, 0x1, R8 ; /* 0x00000001070b7824 */
/* 0x000fca00078e0208 */
/*07e0*/ IADD3 R7, R11, -0x1, RZ ; /* 0xffffffff0b077810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R7, 0xfe, PT ; /* 0x000000fe0700780c */
/* 0x000fda0003f06070 */
/*0800*/ @!P0 BRA 0xa10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0810*/ ISETP.GT.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f04270 */
/*0820*/ @P0 BRA 0x9e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0830*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fda0003f06270 */
/*0840*/ @P0 BRA 0xa20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0850*/ ISETP.GE.AND P0, PT, R11, -0x18, PT ; /* 0xffffffe80b00780c */
/* 0x000fe40003f06270 */
/*0860*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fd600078ec0ff */
/*0870*/ @!P0 BRA 0xa20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0880*/ FFMA.RZ R7, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e077223 */
/* 0x1c0fe2000000c00d */
/*0890*/ IADD3 R10, R11.reuse, 0x20, RZ ; /* 0x000000200b0a7810 */
/* 0x040fe20007ffe0ff */
/*08a0*/ FFMA.RM R8, R14.reuse, R12.reuse, R13.reuse ; /* 0x0000000c0e087223 */
/* 0x1c0fe2000000400d */
/*08b0*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f45270 */
/*08c0*/ LOP3.LUT R9, R7, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff07097812 */
/* 0x000fe200078ec0ff */
/*08d0*/ FFMA.RP R7, R14, R12, R13 ; /* 0x0000000c0e077223 */
/* 0x000fe2000000800d */
/*08e0*/ ISETP.NE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f25270 */
/*08f0*/ IMAD.MOV R11, RZ, RZ, -R11 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a0b */
/*0900*/ LOP3.LUT R9, R9, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000009097812 */
/* 0x000fe400078efcff */
/*0910*/ FSETP.NEU.FTZ.AND P0, PT, R7, R8, PT ; /* 0x000000080700720b */
/* 0x000fc40003f1d000 */
/*0920*/ SHF.L.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7219 */
/* 0x000fe400000006ff */
/*0930*/ SEL R8, R11, RZ, P2 ; /* 0x000000ff0b087207 */
/* 0x000fe40001000000 */
/*0940*/ ISETP.NE.AND P1, PT, R10, RZ, P1 ; /* 0x000000ff0a00720c */
/* 0x000fe40000f25270 */
/*0950*/ SHF.R.U32.HI R8, RZ, R8, R9 ; /* 0x00000008ff087219 */
/* 0x000fe40000011609 */
/*0960*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0970*/ SHF.R.U32.HI R10, RZ, 0x1, R8 ; /* 0x00000001ff0a7819 */
/* 0x000fc40000011608 */
/*0980*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc80004000000 */
/*0990*/ LOP3.LUT R7, R7, 0x1, R10, 0xf8, !PT ; /* 0x0000000107077812 */
/* 0x000fc800078ef80a */
/*09a0*/ LOP3.LUT R7, R7, R8, RZ, 0xc0, !PT ; /* 0x0000000807077212 */
/* 0x000fca00078ec0ff */
/*09b0*/ IMAD.IADD R10, R10, 0x1, R7 ; /* 0x000000010a0a7824 */
/* 0x000fca00078e0207 */
/*09c0*/ LOP3.LUT R5, R10, R5, RZ, 0xfc, !PT ; /* 0x000000050a057212 */
/* 0x000fe200078efcff */
/*09d0*/ BRA 0xa20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT R5, R5, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000005057812 */
/* 0x000fc800078ec0ff */
/*09f0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a00*/ BRA 0xa20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0a10*/ IMAD R5, R8, 0x800000, R5 ; /* 0x0080000008057824 */
/* 0x000fe400078e0205 */
/*0a20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0a30*/ BRA 0xac0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0a40*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fc800078e4805 */
/*0a50*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000005057812 */
/* 0x000fe200078efcff */
/*0a60*/ BRA 0xac0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0a70*/ LOP3.LUT R5, R8, 0x80000000, R5, 0x48, !PT ; /* 0x8000000008057812 */
/* 0x000fe200078e4805 */
/*0a80*/ BRA 0xac0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0a90*/ MUFU.RSQ R5, -QNAN ; /* 0xffc0000000057908 */
/* 0x000e220000001400 */
/*0aa0*/ BRA 0xac0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0ab0*/ FADD.FTZ R5, R10, R13 ; /* 0x0000000d0a057221 */
/* 0x000fe40000010000 */
/*0ac0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x0 ; /* 0x00000000ff077424 */
/* 0x000fc800078e00ff */
/*0ae0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff51006007950 */
/* 0x000fea0003c3ffff */
/*0af0*/ BRA 0xaf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
__global__ void gSumVector(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
__global__ void gScalarMultVect(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
printf("Device does not support overlapping\n");
return 0;
}
float time1, time2, time3, time4;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *host_a, *host_b, *host_c;
cudaHostAlloc((void**) &host_a, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
cudaHostAlloc((void**) &host_b, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
cudaHostAlloc((void**) &host_c, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**) &dev_a, N * sizeof(int));
cudaMalloc((void**) &dev_b, N * sizeof(int));
cudaMalloc((void**) &dev_c, N * sizeof(int));
int *dev_a0, *dev_a1, *dev_b0, *dev_b1, *dev_c0, *dev_c1;
cudaMalloc((void**) &dev_a0, N * sizeof(int));
cudaMalloc((void**) &dev_a1, N * sizeof(int));
cudaMalloc((void**) &dev_b0, N * sizeof(int));
cudaMalloc((void**) &dev_b1, N * sizeof(int));
cudaMalloc((void**) &dev_c0, N * sizeof(int));
cudaMalloc((void**) &dev_c1, N * sizeof(int));
cudaStream_t stream, stream0, stream1;
cudaStreamCreate(&stream);
cudaStreamCreate(&stream0);
cudaStreamCreate(&stream1);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpyAsync(dev_a, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(dev_b, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
kernel<<<N / 256, 256, 0, stream>>>(dev_a, dev_b, dev_c);
cudaMemcpyAsync(host_c + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost, stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time1, start, stop);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
cudaMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
cudaMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
cudaMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
cudaMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time2, start, stop);
cudaEventRecord(start,0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
cudaMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
cudaMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
cudaMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time3, start, stop);
int *host_a1, *host_b1, *host_c1;
host_a1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_b1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_c1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpy(dev_a, host_a1 + i, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b1 + i, N * sizeof(int), cudaMemcpyHostToDevice);
kernel<<<N / 256, 256>>>(dev_a, dev_b, dev_c);
cudaMemcpy(host_c1 + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time4, start, stop);
printf("%.4f ms\n", time1);
printf("%.4f ms\n", time2);
printf("%.4f ms\n", time3);
printf("%.4f ms\n", time4);
free(host_a1);
free(host_b1);
free(host_c1);
cudaStreamDestroy(stream);
cudaStreamDestroy(stream0);
cudaStreamDestroy(stream1);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
cudaFree(dev_a0);
cudaFree(dev_a1);
cudaFree(dev_b0);
cudaFree(dev_b1);
cudaFree(dev_c0);
cudaFree(dev_c1);
cudaFreeHost(host_a);
cudaFreeHost(host_b);
cudaFreeHost(host_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | .file "tmpxft_00168526_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6kernelPiS_S_PiS_S_
.type _Z29__device_stub__Z6kernelPiS_S_PiS_S_, @function
_Z29__device_stub__Z6kernelPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6kernelPiS_S_PiS_S_, .-_Z29__device_stub__Z6kernelPiS_S_PiS_S_
.globl _Z6kernelPiS_S_
.type _Z6kernelPiS_S_, @function
_Z6kernelPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPiS_S_, .-_Z6kernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device does not support overlapping\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%.4f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1224, %rsp
.cfi_def_cfa_offset 1264
movq %fs:40, %rax
movq %rax, 1208(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaGetDevice@PLT
leaq 176(%rsp), %rdi
movl (%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 560(%rsp)
je .L30
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 48(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 56(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 136(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 144(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L15
.L30:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L14:
movq %rbx, %rdi
addq 48(%rsp), %rdi
movq 128(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 72(%rsp), %rsi
call cudaMemcpyAsync@PLT
addq $4194304, %rbx
cmpq $83886080, %rbx
je .L31
.L15:
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq 128(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 56(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq 128(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 64(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 128(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L14
.L31:
movq 128(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L18
.L33:
movq 112(%rsp), %rdx
movq 96(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L16
.L17:
movq %rbp, %rdi
addq 48(%rsp), %rdi
movq 144(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 120(%rsp), %rsi
call cudaMemcpyAsync@PLT
addq $8388608, %rbx
cmpq $83886080, %rbx
je .L32
.L18:
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq 136(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 80(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq 136(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 96(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 136(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L16:
movq %rbx, %rdi
addq 48(%rsp), %rdi
movq 136(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 112(%rsp), %rsi
call cudaMemcpyAsync@PLT
leaq 4194304(%rbx), %rbp
movq %rbp, %rsi
addq 32(%rsp), %rsi
movq 144(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 88(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbp, %rsi
addq 40(%rsp), %rsi
movq 144(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 104(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 144(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L17
.L32:
movq 136(%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 144(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L21
.L35:
movq 112(%rsp), %rdx
movq 96(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L19
.L20:
movq %rbx, %rdi
addq 48(%rsp), %rdi
movq 136(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 112(%rsp), %rsi
call cudaMemcpyAsync@PLT
movq %rbp, %rdi
addq 48(%rsp), %rdi
movq 144(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 120(%rsp), %rsi
call cudaMemcpyAsync@PLT
addq $8388608, %rbx
cmpq $83886080, %rbx
je .L34
.L21:
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq 136(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 80(%rsp), %rdi
call cudaMemcpyAsync@PLT
leaq 4194304(%rbx), %rbp
movq %rbp, %rsi
addq 32(%rsp), %rsi
movq 144(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 88(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq 136(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 96(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbp, %rsi
addq 40(%rsp), %rsi
movq 144(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 104(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 136(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L19:
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 144(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L20
.L34:
movq 136(%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 144(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $4, %esi
movl $20971520, %edi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movl $20971520, %edi
call calloc@PLT
movq %rax, %r12
movl $4, %esi
movl $20971520, %edi
call calloc@PLT
movq %rax, %rbp
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L23
.L22:
leaq 0(%rbp,%rbx), %rdi
movl $2, %ecx
movl $4194304, %edx
movq 72(%rsp), %rsi
call cudaMemcpy@PLT
addq $4194304, %rbx
cmpq $83886080, %rbx
je .L36
.L23:
leaq 0(%r13,%rbx), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq (%r12,%rbx), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L22
.L36:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 164(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 164(%rsp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 128(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 136(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 144(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
.L13:
movq 1208(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $1224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_
.type _Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_, @function
_Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10gSumVectorPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_, .-_Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_
.globl _Z10gSumVectorPiS_S_
.type _Z10gSumVectorPiS_S_, @function
_Z10gSumVectorPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10gSumVectorPiS_S_, .-_Z10gSumVectorPiS_S_
.globl _Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_
.type _Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_, @function
_Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gScalarMultVectPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_, .-_Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_
.globl _Z15gScalarMultVectPiS_S_
.type _Z15gScalarMultVectPiS_S_, @function
_Z15gScalarMultVectPiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15gScalarMultVectPiS_S_, .-_Z15gScalarMultVectPiS_S_
.section .rodata.str1.1
.LC2:
.string "_Z15gScalarMultVectPiS_S_"
.LC3:
.string "_Z10gSumVectorPiS_S_"
.LC4:
.string "_Z6kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gScalarMultVectPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gSumVectorPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
__global__ void gSumVector(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
__global__ void gScalarMultVect(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
int main()
{
cudaDeviceProp prop;
int whichDevice;
cudaGetDevice(&whichDevice);
cudaGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
printf("Device does not support overlapping\n");
return 0;
}
float time1, time2, time3, time4;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int *host_a, *host_b, *host_c;
cudaHostAlloc((void**) &host_a, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
cudaHostAlloc((void**) &host_b, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
cudaHostAlloc((void**) &host_c, FULL_DATA_SIZE * sizeof(int),
cudaHostAllocDefault);
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**) &dev_a, N * sizeof(int));
cudaMalloc((void**) &dev_b, N * sizeof(int));
cudaMalloc((void**) &dev_c, N * sizeof(int));
int *dev_a0, *dev_a1, *dev_b0, *dev_b1, *dev_c0, *dev_c1;
cudaMalloc((void**) &dev_a0, N * sizeof(int));
cudaMalloc((void**) &dev_a1, N * sizeof(int));
cudaMalloc((void**) &dev_b0, N * sizeof(int));
cudaMalloc((void**) &dev_b1, N * sizeof(int));
cudaMalloc((void**) &dev_c0, N * sizeof(int));
cudaMalloc((void**) &dev_c1, N * sizeof(int));
cudaStream_t stream, stream0, stream1;
cudaStreamCreate(&stream);
cudaStreamCreate(&stream0);
cudaStreamCreate(&stream1);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpyAsync(dev_a, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
cudaMemcpyAsync(dev_b, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream);
kernel<<<N / 256, 256, 0, stream>>>(dev_a, dev_b, dev_c);
cudaMemcpyAsync(host_c + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost, stream);
}
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time1, start, stop);
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
cudaMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
cudaMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
cudaMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
cudaMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time2, start, stop);
cudaEventRecord(start,0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
cudaMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
cudaMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), cudaMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
cudaMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), cudaMemcpyDeviceToHost, stream0);
cudaMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), cudaMemcpyDeviceToHost, stream1);
}
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time3, start, stop);
int *host_a1, *host_b1, *host_c1;
host_a1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_b1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_c1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
cudaEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
cudaMemcpy(dev_a, host_a1 + i, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, host_b1 + i, N * sizeof(int), cudaMemcpyHostToDevice);
kernel<<<N / 256, 256>>>(dev_a, dev_b, dev_c);
cudaMemcpy(host_c1 + i, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
}
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&time4, start, stop);
printf("%.4f ms\n", time1);
printf("%.4f ms\n", time2);
printf("%.4f ms\n", time3);
printf("%.4f ms\n", time4);
free(host_a1);
free(host_b1);
free(host_c1);
cudaStreamDestroy(stream);
cudaStreamDestroy(stream0);
cudaStreamDestroy(stream1);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
cudaFree(dev_a0);
cudaFree(dev_a1);
cudaFree(dev_b0);
cudaFree(dev_b1);
cudaFree(dev_c0);
cudaFree(dev_c1);
cudaFreeHost(host_a);
cudaFreeHost(host_b);
cudaFreeHost(host_c);
cudaEventDestroy(start);
cudaEventDestroy(stop);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
__global__ void gSumVector(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
__global__ void gScalarMultVect(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
printf("Device does not support overlapping\n");
return 0;
}
float time1, time2, time3, time4;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *host_a, *host_b, *host_c;
hipHostAlloc((void**) &host_a, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
hipHostAlloc((void**) &host_b, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
hipHostAlloc((void**) &host_c, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**) &dev_a, N * sizeof(int));
hipMalloc((void**) &dev_b, N * sizeof(int));
hipMalloc((void**) &dev_c, N * sizeof(int));
int *dev_a0, *dev_a1, *dev_b0, *dev_b1, *dev_c0, *dev_c1;
hipMalloc((void**) &dev_a0, N * sizeof(int));
hipMalloc((void**) &dev_a1, N * sizeof(int));
hipMalloc((void**) &dev_b0, N * sizeof(int));
hipMalloc((void**) &dev_b1, N * sizeof(int));
hipMalloc((void**) &dev_c0, N * sizeof(int));
hipMalloc((void**) &dev_c1, N * sizeof(int));
hipStream_t stream, stream0, stream1;
hipStreamCreate(&stream);
hipStreamCreate(&stream0);
hipStreamCreate(&stream1);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpyAsync(dev_a, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(dev_b, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
kernel<<<N / 256, 256, 0, stream>>>(dev_a, dev_b, dev_c);
hipMemcpyAsync(host_c + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time1, start, stop);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
hipMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
hipMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
hipMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
hipMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time2, start, stop);
hipEventRecord(start,0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
hipMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
hipMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
hipMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time3, start, stop);
int *host_a1, *host_b1, *host_c1;
host_a1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_b1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_c1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpy(dev_a, host_a1 + i, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b1 + i, N * sizeof(int), hipMemcpyHostToDevice);
kernel<<<N / 256, 256>>>(dev_a, dev_b, dev_c);
hipMemcpy(host_c1 + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time4, start, stop);
printf("%.4f ms\n", time1);
printf("%.4f ms\n", time2);
printf("%.4f ms\n", time3);
printf("%.4f ms\n", time4);
free(host_a1);
free(host_b1);
free(host_c1);
hipStreamDestroy(stream);
hipStreamDestroy(stream0);
hipStreamDestroy(stream1);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
hipFree(dev_a0);
hipFree(dev_a1);
hipFree(dev_b0);
hipFree(dev_b1);
hipFree(dev_c0);
hipFree(dev_c1);
hipHostFree(host_a);
hipHostFree(host_b);
hipHostFree(host_c);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
__global__ void gSumVector(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
__global__ void gScalarMultVect(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
printf("Device does not support overlapping\n");
return 0;
}
float time1, time2, time3, time4;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *host_a, *host_b, *host_c;
hipHostAlloc((void**) &host_a, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
hipHostAlloc((void**) &host_b, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
hipHostAlloc((void**) &host_c, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**) &dev_a, N * sizeof(int));
hipMalloc((void**) &dev_b, N * sizeof(int));
hipMalloc((void**) &dev_c, N * sizeof(int));
int *dev_a0, *dev_a1, *dev_b0, *dev_b1, *dev_c0, *dev_c1;
hipMalloc((void**) &dev_a0, N * sizeof(int));
hipMalloc((void**) &dev_a1, N * sizeof(int));
hipMalloc((void**) &dev_b0, N * sizeof(int));
hipMalloc((void**) &dev_b1, N * sizeof(int));
hipMalloc((void**) &dev_c0, N * sizeof(int));
hipMalloc((void**) &dev_c1, N * sizeof(int));
hipStream_t stream, stream0, stream1;
hipStreamCreate(&stream);
hipStreamCreate(&stream0);
hipStreamCreate(&stream1);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpyAsync(dev_a, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(dev_b, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
kernel<<<N / 256, 256, 0, stream>>>(dev_a, dev_b, dev_c);
hipMemcpyAsync(host_c + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time1, start, stop);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
hipMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
hipMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
hipMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
hipMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time2, start, stop);
hipEventRecord(start,0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
hipMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
hipMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
hipMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time3, start, stop);
int *host_a1, *host_b1, *host_c1;
host_a1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_b1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_c1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpy(dev_a, host_a1 + i, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b1 + i, N * sizeof(int), hipMemcpyHostToDevice);
kernel<<<N / 256, 256>>>(dev_a, dev_b, dev_c);
hipMemcpy(host_c1 + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time4, start, stop);
printf("%.4f ms\n", time1);
printf("%.4f ms\n", time2);
printf("%.4f ms\n", time3);
printf("%.4f ms\n", time4);
free(host_a1);
free(host_b1);
free(host_c1);
hipStreamDestroy(stream);
hipStreamDestroy(stream0);
hipStreamDestroy(stream1);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
hipFree(dev_a0);
hipFree(dev_a1);
hipFree(dev_b0);
hipFree(dev_b1);
hipFree(dev_c0);
hipFree(dev_c1);
hipHostFree(host_a);
hipHostFree(host_b);
hipHostFree(host_c);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPiS_S_
.globl _Z6kernelPiS_S_
.p2align 8
.type _Z6kernelPiS_S_,@function
_Z6kernelPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v0, 1, v1
v_add_nc_u32_e32 v4, 2, v1
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v0
v_ashrrev_i32_e32 v3, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v2, 24, v2
v_lshrrev_b32_e32 v3, 24, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v0, v2
v_add_nc_u32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xffffff00, v2
v_and_b32_e32 v6, 0xffffff00, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v0, v0, v5
v_sub_nc_u32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
s_clause 0x2
global_load_b32 v6, v[6:7], off
global_load_b32 v7, v[10:11], off
global_load_b32 v10, v[12:13], off
s_clause 0x2
global_load_b32 v8, v[8:9], off
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[4:5], off
s_waitcnt vmcnt(3)
v_add3_u32 v4, v7, v6, v10
s_waitcnt vmcnt(0)
v_add3_u32 v0, v0, v8, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v4
v_cvt_f32_i32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v4, null, 0x40400000, 0x40400000, v1
v_div_scale_f32 v10, vcc_lo, v1, 0x40400000, v1
v_div_scale_f32 v5, null, 0x40400000, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
v_rcp_f32_e32 v7, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v4, v6, 1.0
v_fma_f32 v9, -v5, v7, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v6, v8, v6
v_div_scale_f32 v8, s0, v0, 0x40400000, v0
v_fmac_f32_e32 v7, v9, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v9, v10, v6
v_mul_f32_e32 v11, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v4, v9, v10
v_fma_f32 v13, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, v12, v6
v_fmac_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v9, v10
v_fma_f32 v5, -v5, v11, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v6, v9
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v5, v5, v7, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v1, v4, 0x40400000, v1
v_div_fixup_f32 v0, v5, 0x40400000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v0, v1, v0
v_mul_f32_e32 v0, 0.5, v0
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v4, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPiS_S_, .Lfunc_end0-_Z6kernelPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10gSumVectorPiS_S_
.globl _Z10gSumVectorPiS_S_
.p2align 8
.type _Z10gSumVectorPiS_S_,@function
_Z10gSumVectorPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10gSumVectorPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10gSumVectorPiS_S_, .Lfunc_end1-_Z10gSumVectorPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15gScalarMultVectPiS_S_
.globl _Z15gScalarMultVectPiS_S_
.p2align 8
.type _Z15gScalarMultVectPiS_S_,@function
_Z15gScalarMultVectPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x100000, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15gScalarMultVectPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15gScalarMultVectPiS_S_, .Lfunc_end2-_Z15gScalarMultVectPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10gSumVectorPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10gSumVectorPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15gScalarMultVectPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15gScalarMultVectPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N (1024 * 1024)
#define FULL_DATA_SIZE (N * 20)
__global__ void kernel(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N) {
int idx1 = (idx + 1) % 256;
int idx2 = (idx + 2) % 256;
float as = (a[idx] + a[idx1] + a[idx2]) / 3.0f;
float bs = (b[idx] + b[idx1] + b[idx2]) / 3.0f;
c[idx] = (as + bs) / 2;
}
}
__global__ void gSumVector(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
__global__ void gScalarMultVect(int *a, int *b, int *c)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < N)
c[idx] = a[idx] * b[idx];
}
int main()
{
hipDeviceProp_t prop;
int whichDevice;
hipGetDevice(&whichDevice);
hipGetDeviceProperties(&prop, whichDevice);
if (!prop.deviceOverlap) {
printf("Device does not support overlapping\n");
return 0;
}
float time1, time2, time3, time4;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int *host_a, *host_b, *host_c;
hipHostAlloc((void**) &host_a, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
hipHostAlloc((void**) &host_b, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
hipHostAlloc((void**) &host_c, FULL_DATA_SIZE * sizeof(int),
hipHostMallocDefault);
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**) &dev_a, N * sizeof(int));
hipMalloc((void**) &dev_b, N * sizeof(int));
hipMalloc((void**) &dev_c, N * sizeof(int));
int *dev_a0, *dev_a1, *dev_b0, *dev_b1, *dev_c0, *dev_c1;
hipMalloc((void**) &dev_a0, N * sizeof(int));
hipMalloc((void**) &dev_a1, N * sizeof(int));
hipMalloc((void**) &dev_b0, N * sizeof(int));
hipMalloc((void**) &dev_b1, N * sizeof(int));
hipMalloc((void**) &dev_c0, N * sizeof(int));
hipMalloc((void**) &dev_c1, N * sizeof(int));
hipStream_t stream, stream0, stream1;
hipStreamCreate(&stream);
hipStreamCreate(&stream0);
hipStreamCreate(&stream1);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpyAsync(dev_a, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
hipMemcpyAsync(dev_b, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream);
kernel<<<N / 256, 256, 0, stream>>>(dev_a, dev_b, dev_c);
hipMemcpyAsync(host_c + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost, stream);
}
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time1, start, stop);
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
hipMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
hipMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
hipMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
hipMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time2, start, stop);
hipEventRecord(start,0);
for (int i = 0; i < FULL_DATA_SIZE; i += N * 2) {
hipMemcpyAsync(dev_a0, host_a + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_a1, host_a + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
hipMemcpyAsync(dev_b0, host_b + i, N * sizeof(int), hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(dev_b1, host_b + i + N, N * sizeof(int), hipMemcpyHostToDevice, stream1);
kernel<<<N / 256, 256, 0, stream0>>>(dev_a0, dev_b0, dev_c0);
kernel<<<N / 256, 256, 0, stream1>>>(dev_a1, dev_b1, dev_c1);
hipMemcpyAsync(host_c + i, dev_c0, N * sizeof(int), hipMemcpyDeviceToHost, stream0);
hipMemcpyAsync(host_c + i + N, dev_c1, N * sizeof(int), hipMemcpyDeviceToHost, stream1);
}
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time3, start, stop);
int *host_a1, *host_b1, *host_c1;
host_a1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_b1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
host_c1 = (int*) calloc(FULL_DATA_SIZE, sizeof(int));
hipEventRecord(start, 0);
for (int i = 0; i < FULL_DATA_SIZE; i += N) {
hipMemcpy(dev_a, host_a1 + i, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_b, host_b1 + i, N * sizeof(int), hipMemcpyHostToDevice);
kernel<<<N / 256, 256>>>(dev_a, dev_b, dev_c);
hipMemcpy(host_c1 + i, dev_c, N * sizeof(int), hipMemcpyDeviceToHost);
}
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&time4, start, stop);
printf("%.4f ms\n", time1);
printf("%.4f ms\n", time2);
printf("%.4f ms\n", time3);
printf("%.4f ms\n", time4);
free(host_a1);
free(host_b1);
free(host_c1);
hipStreamDestroy(stream);
hipStreamDestroy(stream0);
hipStreamDestroy(stream1);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
hipFree(dev_a0);
hipFree(dev_a1);
hipFree(dev_b0);
hipFree(dev_b1);
hipFree(dev_c0);
hipFree(dev_c1);
hipHostFree(host_a);
hipHostFree(host_b);
hipHostFree(host_c);
hipEventDestroy(start);
hipEventDestroy(stop);
return 0;
} | .text
.file "main.hip"
.globl _Z21__device_stub__kernelPiS_S_ # -- Begin function _Z21__device_stub__kernelPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_S_,@function
_Z21__device_stub__kernelPiS_S_: # @_Z21__device_stub__kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_S_, .Lfunc_end0-_Z21__device_stub__kernelPiS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__gSumVectorPiS_S_ # -- Begin function _Z25__device_stub__gSumVectorPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__gSumVectorPiS_S_,@function
_Z25__device_stub__gSumVectorPiS_S_: # @_Z25__device_stub__gSumVectorPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10gSumVectorPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__gSumVectorPiS_S_, .Lfunc_end1-_Z25__device_stub__gSumVectorPiS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gScalarMultVectPiS_S_ # -- Begin function _Z30__device_stub__gScalarMultVectPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__gScalarMultVectPiS_S_,@function
_Z30__device_stub__gScalarMultVectPiS_S_: # @_Z30__device_stub__gScalarMultVectPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gScalarMultVectPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__gScalarMultVectPiS_S_, .Lfunc_end2-_Z30__device_stub__gScalarMultVectPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1752, %rsp # imm = 0x6D8
.cfi_def_cfa_offset 1808
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 252(%rsp), %rdi
callq hipGetDevice
movl 252(%rsp), %esi
leaq 280(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 664(%rsp)
je .LBB3_1
# %bb.2:
movabsq $4294967552, %rbx # imm = 0x100000100
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 160(%rsp), %rdi
xorl %r12d, %r12d
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 152(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 144(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 232(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 224(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 216(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 208(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 200(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 192(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 184(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 176(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 168(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 136(%rsp), %rdi
callq hipStreamCreate
leaq 24(%rsp), %rdi
callq hipStreamCreate
leaq 16(%rsp), %rdi
callq hipStreamCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-1048576, %r13 # imm = 0xFFF00000
leaq 3840(%rbx), %r14
leaq 104(%rsp), %rbp
leaq 112(%rsp), %r15
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
movq 144(%rsp), %rdi
addq %r12, %rdi
movq 216(%rsp), %rsi
movq 136(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
addq $1048576, %r13 # imm = 0x100000
addq $4194304, %r12 # imm = 0x400000
cmpq $19922944, %r13 # imm = 0x1300000
jae .LBB3_6
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq 232(%rsp), %rdi
movq 160(%rsp), %rsi
addq %r12, %rsi
movq 136(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 224(%rsp), %rdi
movq 152(%rsp), %rsi
addq %r12, %rsi
movq 136(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 136(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movq 216(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_5
.LBB3_6:
movq 136(%rsp), %rdi
callq hipStreamSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 248(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-2097152, %r12 # imm = 0xFFE00000
movl $4194304, %r13d # imm = 0x400000
leaq 104(%rsp), %rbp
leaq 112(%rsp), %r15
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_7 Depth=1
movq 144(%rsp), %rdi
addq %r13, %rdi
movq 168(%rsp), %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
addq $2097152, %r12 # imm = 0x200000
addq $8388608, %r13 # imm = 0x800000
cmpq $18874368, %r12 # imm = 0x1200000
jae .LBB3_12
.LBB3_7: # =>This Inner Loop Header: Depth=1
movq 208(%rsp), %rdi
movq 160(%rsp), %rax
leaq (%rax,%r13), %rsi
addq $-4194304, %rsi # imm = 0xFFC00000
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 192(%rsp), %rdi
movq 152(%rsp), %rax
leaq (%rax,%r13), %rsi
addq $-4194304, %rsi # imm = 0xFFC00000
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 24(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movq 208(%rsp), %rax
movq 192(%rsp), %rcx
movq 176(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
movq 144(%rsp), %rax
leaq (%rax,%r13), %rdi
addq $-4194304, %rdi # imm = 0xFFC00000
movq 176(%rsp), %rsi
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
movq 200(%rsp), %rdi
movq 160(%rsp), %rsi
addq %r13, %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 184(%rsp), %rdi
movq 152(%rsp), %rsi
addq %r13, %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_7 Depth=1
movq 200(%rsp), %rax
movq 184(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
movq 24(%rsp), %rdi
callq hipStreamSynchronize
movq 16(%rsp), %rdi
callq hipStreamSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 244(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-2097152, %r12 # imm = 0xFFE00000
movl $4194304, %r13d # imm = 0x400000
leaq 104(%rsp), %rbp
leaq 112(%rsp), %r15
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_13 Depth=1
movq 144(%rsp), %rax
leaq (%rax,%r13), %rdi
addq $-4194304, %rdi # imm = 0xFFC00000
movq 176(%rsp), %rsi
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
movq 144(%rsp), %rdi
addq %r13, %rdi
movq 168(%rsp), %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
addq $2097152, %r12 # imm = 0x200000
addq $8388608, %r13 # imm = 0x800000
cmpq $18874368, %r12 # imm = 0x1200000
jae .LBB3_18
.LBB3_13: # =>This Inner Loop Header: Depth=1
movq 208(%rsp), %rdi
movq 160(%rsp), %rax
leaq (%rax,%r13), %rsi
addq $-4194304, %rsi # imm = 0xFFC00000
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 200(%rsp), %rdi
movq 160(%rsp), %rsi
addq %r13, %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 192(%rsp), %rdi
movq 152(%rsp), %rax
leaq (%rax,%r13), %rsi
addq $-4194304, %rsi # imm = 0xFFC00000
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 184(%rsp), %rdi
movq 152(%rsp), %rsi
addq %r13, %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 24(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_13 Depth=1
movq 208(%rsp), %rax
movq 192(%rsp), %rcx
movq 176(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15: # in Loop: Header=BB3_13 Depth=1
movq 16(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_13 Depth=1
movq 200(%rsp), %rax
movq 184(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_17
.LBB3_18:
movq 24(%rsp), %rdi
callq hipStreamSynchronize
movq 16(%rsp), %rdi
callq hipStreamSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
movl $20971520, %edi # imm = 0x1400000
movl $4, %esi
callq calloc
movq %rax, %r15
movl $20971520, %edi # imm = 0x1400000
movl $4, %esi
callq calloc
movq %rax, %r12
movl $20971520, %edi # imm = 0x1400000
movl $4, %esi
callq calloc
movq %rax, %r13
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-1048576, %rbp # imm = 0xFFF00000
movq %r15, 272(%rsp) # 8-byte Spill
movq %r12, 264(%rsp) # 8-byte Spill
movq %r13, 256(%rsp) # 8-byte Spill
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_21: # in Loop: Header=BB3_19 Depth=1
movq 216(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
addq $1048576, %rbp # imm = 0x100000
addq $4194304, %r13 # imm = 0x400000
addq $4194304, %r12 # imm = 0x400000
addq $4194304, %r15 # imm = 0x400000
cmpq $19922944, %rbp # imm = 0x1300000
jae .LBB3_22
.LBB3_19: # =>This Inner Loop Header: Depth=1
movq 232(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 224(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_21
# %bb.20: # in Loop: Header=BB3_19 Depth=1
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movq 216(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
leaq 112(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_21
.LBB3_22:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movss 248(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 244(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 272(%rsp), %rdi # 8-byte Reload
callq free
movq 264(%rsp), %rdi # 8-byte Reload
callq free
movq 256(%rsp), %rdi # 8-byte Reload
callq free
movq 136(%rsp), %rdi
callq hipStreamDestroy
movq 24(%rsp), %rdi
callq hipStreamDestroy
movq 16(%rsp), %rdi
callq hipStreamDestroy
movq 232(%rsp), %rdi
callq hipFree
movq 224(%rsp), %rdi
callq hipFree
movq 216(%rsp), %rdi
callq hipFree
movq 208(%rsp), %rdi
callq hipFree
movq 200(%rsp), %rdi
callq hipFree
movq 192(%rsp), %rdi
callq hipFree
movq 184(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipHostFree
movq 152(%rsp), %rdi
callq hipHostFree
movq 144(%rsp), %rdi
callq hipHostFree
movq 96(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
jmp .LBB3_23
.LBB3_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_23:
xorl %eax, %eax
addq $1752, %rsp # imm = 0x6D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gSumVectorPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gScalarMultVectPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_S_,@object # @_Z6kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_S_
.p2align 3, 0x0
_Z6kernelPiS_S_:
.quad _Z21__device_stub__kernelPiS_S_
.size _Z6kernelPiS_S_, 8
.type _Z10gSumVectorPiS_S_,@object # @_Z10gSumVectorPiS_S_
.globl _Z10gSumVectorPiS_S_
.p2align 3, 0x0
_Z10gSumVectorPiS_S_:
.quad _Z25__device_stub__gSumVectorPiS_S_
.size _Z10gSumVectorPiS_S_, 8
.type _Z15gScalarMultVectPiS_S_,@object # @_Z15gScalarMultVectPiS_S_
.globl _Z15gScalarMultVectPiS_S_
.p2align 3, 0x0
_Z15gScalarMultVectPiS_S_:
.quad _Z30__device_stub__gScalarMultVectPiS_S_
.size _Z15gScalarMultVectPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.4f ms\n"
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_S_"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10gSumVectorPiS_S_"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15gScalarMultVectPiS_S_"
.size .L__unnamed_3, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Device does not support overlapping"
.size .Lstr, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_S_
.addrsig_sym _Z25__device_stub__gSumVectorPiS_S_
.addrsig_sym _Z30__device_stub__gScalarMultVectPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_S_
.addrsig_sym _Z10gSumVectorPiS_S_
.addrsig_sym _Z15gScalarMultVectPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00168526_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6kernelPiS_S_PiS_S_
.type _Z29__device_stub__Z6kernelPiS_S_PiS_S_, @function
_Z29__device_stub__Z6kernelPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6kernelPiS_S_PiS_S_, .-_Z29__device_stub__Z6kernelPiS_S_PiS_S_
.globl _Z6kernelPiS_S_
.type _Z6kernelPiS_S_, @function
_Z6kernelPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6kernelPiS_S_, .-_Z6kernelPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Device does not support overlapping\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%.4f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1224, %rsp
.cfi_def_cfa_offset 1264
movq %fs:40, %rax
movq %rax, 1208(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaGetDevice@PLT
leaq 176(%rsp), %rdi
movl (%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
cmpl $0, 560(%rsp)
je .L30
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 48(%rsp), %rdi
movl $0, %edx
movl $83886080, %esi
call cudaHostAlloc@PLT
leaq 56(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 104(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 112(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 120(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 128(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 136(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 144(%rsp), %rdi
call cudaStreamCreate@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L15
.L30:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L14:
movq %rbx, %rdi
addq 48(%rsp), %rdi
movq 128(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 72(%rsp), %rsi
call cudaMemcpyAsync@PLT
addq $4194304, %rbx
cmpq $83886080, %rbx
je .L31
.L15:
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq 128(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 56(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq 128(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 64(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 128(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L14
.L31:
movq 128(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L18
.L33:
movq 112(%rsp), %rdx
movq 96(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L16
.L17:
movq %rbp, %rdi
addq 48(%rsp), %rdi
movq 144(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 120(%rsp), %rsi
call cudaMemcpyAsync@PLT
addq $8388608, %rbx
cmpq $83886080, %rbx
je .L32
.L18:
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq 136(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 80(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq 136(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 96(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 136(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L16:
movq %rbx, %rdi
addq 48(%rsp), %rdi
movq 136(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 112(%rsp), %rsi
call cudaMemcpyAsync@PLT
leaq 4194304(%rbx), %rbp
movq %rbp, %rsi
addq 32(%rsp), %rsi
movq 144(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 88(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbp, %rsi
addq 40(%rsp), %rsi
movq 144(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 104(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 144(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L17
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L17
.L32:
movq 136(%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 144(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L21
.L35:
movq 112(%rsp), %rdx
movq 96(%rsp), %rsi
movq 80(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L19
.L20:
movq %rbx, %rdi
addq 48(%rsp), %rdi
movq 136(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 112(%rsp), %rsi
call cudaMemcpyAsync@PLT
movq %rbp, %rdi
addq 48(%rsp), %rdi
movq 144(%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 120(%rsp), %rsi
call cudaMemcpyAsync@PLT
addq $8388608, %rbx
cmpq $83886080, %rbx
je .L34
.L21:
movq %rbx, %rsi
addq 32(%rsp), %rsi
movq 136(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 80(%rsp), %rdi
call cudaMemcpyAsync@PLT
leaq 4194304(%rbx), %rbp
movq %rbp, %rsi
addq 32(%rsp), %rsi
movq 144(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 88(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbx, %rsi
addq 40(%rsp), %rsi
movq 136(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 96(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq %rbp, %rsi
addq 40(%rsp), %rsi
movq 144(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 104(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 136(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L19:
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movq 144(%rsp), %r9
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
movq 120(%rsp), %rdx
movq 104(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L20
.L34:
movq 136(%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 144(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $4, %esi
movl $20971520, %edi
call calloc@PLT
movq %rax, %r13
movl $4, %esi
movl $20971520, %edi
call calloc@PLT
movq %rax, %r12
movl $4, %esi
movl $20971520, %edi
call calloc@PLT
movq %rax, %rbp
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %ebx
jmp .L23
.L22:
leaq 0(%rbp,%rbx), %rdi
movl $2, %ecx
movl $4194304, %edx
movq 72(%rsp), %rsi
call cudaMemcpy@PLT
addq $4194304, %rbx
cmpq $83886080, %rbx
je .L36
.L23:
leaq 0(%r13,%rbx), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq (%r12,%rbx), %rsi
movl $1, %ecx
movl $4194304, %edx
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 164(%rsp)
movl $1, 168(%rsp)
movl $1, 172(%rsp)
movl $4096, 152(%rsp)
movl $1, 156(%rsp)
movl $1, 160(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 164(%rsp), %rdx
movl $1, %ecx
movq 152(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z29__device_stub__Z6kernelPiS_S_PiS_S_
jmp .L22
.L36:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 164(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 164(%rsp), %xmm0
movq %rbx, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 128(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 136(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 144(%rsp), %rdi
call cudaStreamDestroy@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 96(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 112(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
.L13:
movq 1208(%rsp), %rax
subq %fs:40, %rax
jne .L37
movl $0, %eax
addq $1224, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_
.type _Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_, @function
_Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10gSumVectorPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_, .-_Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_
.globl _Z10gSumVectorPiS_S_
.type _Z10gSumVectorPiS_S_, @function
_Z10gSumVectorPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10gSumVectorPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10gSumVectorPiS_S_, .-_Z10gSumVectorPiS_S_
.globl _Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_
.type _Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_, @function
_Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15gScalarMultVectPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_, .-_Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_
.globl _Z15gScalarMultVectPiS_S_
.type _Z15gScalarMultVectPiS_S_, @function
_Z15gScalarMultVectPiS_S_:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z15gScalarMultVectPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z15gScalarMultVectPiS_S_, .-_Z15gScalarMultVectPiS_S_
.section .rodata.str1.1
.LC2:
.string "_Z15gScalarMultVectPiS_S_"
.LC3:
.string "_Z10gSumVectorPiS_S_"
.LC4:
.string "_Z6kernelPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15gScalarMultVectPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10gSumVectorPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z21__device_stub__kernelPiS_S_ # -- Begin function _Z21__device_stub__kernelPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__kernelPiS_S_,@function
_Z21__device_stub__kernelPiS_S_: # @_Z21__device_stub__kernelPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPiS_S_, .Lfunc_end0-_Z21__device_stub__kernelPiS_S_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__gSumVectorPiS_S_ # -- Begin function _Z25__device_stub__gSumVectorPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__gSumVectorPiS_S_,@function
_Z25__device_stub__gSumVectorPiS_S_: # @_Z25__device_stub__gSumVectorPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10gSumVectorPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__gSumVectorPiS_S_, .Lfunc_end1-_Z25__device_stub__gSumVectorPiS_S_
.cfi_endproc
# -- End function
.globl _Z30__device_stub__gScalarMultVectPiS_S_ # -- Begin function _Z30__device_stub__gScalarMultVectPiS_S_
.p2align 4, 0x90
.type _Z30__device_stub__gScalarMultVectPiS_S_,@function
_Z30__device_stub__gScalarMultVectPiS_S_: # @_Z30__device_stub__gScalarMultVectPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15gScalarMultVectPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z30__device_stub__gScalarMultVectPiS_S_, .Lfunc_end2-_Z30__device_stub__gScalarMultVectPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1752, %rsp # imm = 0x6D8
.cfi_def_cfa_offset 1808
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 252(%rsp), %rdi
callq hipGetDevice
movl 252(%rsp), %esi
leaq 280(%rsp), %rdi
callq hipGetDevicePropertiesR0600
cmpl $0, 664(%rsp)
je .LBB3_1
# %bb.2:
movabsq $4294967552, %rbx # imm = 0x100000100
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
leaq 160(%rsp), %rdi
xorl %r12d, %r12d
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 152(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 144(%rsp), %rdi
movl $83886080, %esi # imm = 0x5000000
xorl %edx, %edx
callq hipHostAlloc
leaq 232(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 224(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 216(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 208(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 200(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 192(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 184(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 176(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 168(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 136(%rsp), %rdi
callq hipStreamCreate
leaq 24(%rsp), %rdi
callq hipStreamCreate
leaq 16(%rsp), %rdi
callq hipStreamCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-1048576, %r13 # imm = 0xFFF00000
leaq 3840(%rbx), %r14
leaq 104(%rsp), %rbp
leaq 112(%rsp), %r15
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_5: # in Loop: Header=BB3_3 Depth=1
movq 144(%rsp), %rdi
addq %r12, %rdi
movq 216(%rsp), %rsi
movq 136(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
addq $1048576, %r13 # imm = 0x100000
addq $4194304, %r12 # imm = 0x400000
cmpq $19922944, %r13 # imm = 0x1300000
jae .LBB3_6
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq 232(%rsp), %rdi
movq 160(%rsp), %rsi
addq %r12, %rsi
movq 136(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 224(%rsp), %rdi
movq 152(%rsp), %rsi
addq %r12, %rsi
movq 136(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 136(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4: # in Loop: Header=BB3_3 Depth=1
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movq 216(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_5
.LBB3_6:
movq 136(%rsp), %rdi
callq hipStreamSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 248(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-2097152, %r12 # imm = 0xFFE00000
movl $4194304, %r13d # imm = 0x400000
leaq 104(%rsp), %rbp
leaq 112(%rsp), %r15
jmp .LBB3_7
.p2align 4, 0x90
.LBB3_11: # in Loop: Header=BB3_7 Depth=1
movq 144(%rsp), %rdi
addq %r13, %rdi
movq 168(%rsp), %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
addq $2097152, %r12 # imm = 0x200000
addq $8388608, %r13 # imm = 0x800000
cmpq $18874368, %r12 # imm = 0x1200000
jae .LBB3_12
.LBB3_7: # =>This Inner Loop Header: Depth=1
movq 208(%rsp), %rdi
movq 160(%rsp), %rax
leaq (%rax,%r13), %rsi
addq $-4194304, %rsi # imm = 0xFFC00000
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 192(%rsp), %rdi
movq 152(%rsp), %rax
leaq (%rax,%r13), %rsi
addq $-4194304, %rsi # imm = 0xFFC00000
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 24(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_9
# %bb.8: # in Loop: Header=BB3_7 Depth=1
movq 208(%rsp), %rax
movq 192(%rsp), %rcx
movq 176(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_9: # in Loop: Header=BB3_7 Depth=1
movq 144(%rsp), %rax
leaq (%rax,%r13), %rdi
addq $-4194304, %rdi # imm = 0xFFC00000
movq 176(%rsp), %rsi
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
movq 200(%rsp), %rdi
movq 160(%rsp), %rsi
addq %r13, %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 184(%rsp), %rdi
movq 152(%rsp), %rsi
addq %r13, %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 16(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_11
# %bb.10: # in Loop: Header=BB3_7 Depth=1
movq 200(%rsp), %rax
movq 184(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_11
.LBB3_12:
movq 24(%rsp), %rdi
callq hipStreamSynchronize
movq 16(%rsp), %rdi
callq hipStreamSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 244(%rsp), %rdi
callq hipEventElapsedTime
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-2097152, %r12 # imm = 0xFFE00000
movl $4194304, %r13d # imm = 0x400000
leaq 104(%rsp), %rbp
leaq 112(%rsp), %r15
jmp .LBB3_13
.p2align 4, 0x90
.LBB3_17: # in Loop: Header=BB3_13 Depth=1
movq 144(%rsp), %rax
leaq (%rax,%r13), %rdi
addq $-4194304, %rdi # imm = 0xFFC00000
movq 176(%rsp), %rsi
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
movq 144(%rsp), %rdi
addq %r13, %rdi
movq 168(%rsp), %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
addq $2097152, %r12 # imm = 0x200000
addq $8388608, %r13 # imm = 0x800000
cmpq $18874368, %r12 # imm = 0x1200000
jae .LBB3_18
.LBB3_13: # =>This Inner Loop Header: Depth=1
movq 208(%rsp), %rdi
movq 160(%rsp), %rax
leaq (%rax,%r13), %rsi
addq $-4194304, %rsi # imm = 0xFFC00000
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 200(%rsp), %rdi
movq 160(%rsp), %rsi
addq %r13, %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 192(%rsp), %rdi
movq 152(%rsp), %rax
leaq (%rax,%r13), %rsi
addq $-4194304, %rsi # imm = 0xFFC00000
movq 24(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 184(%rsp), %rdi
movq 152(%rsp), %rsi
addq %r13, %rsi
movq 16(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 24(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14: # in Loop: Header=BB3_13 Depth=1
movq 208(%rsp), %rax
movq 192(%rsp), %rcx
movq 176(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15: # in Loop: Header=BB3_13 Depth=1
movq 16(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_17
# %bb.16: # in Loop: Header=BB3_13 Depth=1
movq 200(%rsp), %rax
movq 184(%rsp), %rcx
movq 168(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
movq %r15, %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_17
.LBB3_18:
movq 24(%rsp), %rdi
callq hipStreamSynchronize
movq 16(%rsp), %rdi
callq hipStreamSynchronize
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 240(%rsp), %rdi
callq hipEventElapsedTime
movl $20971520, %edi # imm = 0x1400000
movl $4, %esi
callq calloc
movq %rax, %r15
movl $20971520, %edi # imm = 0x1400000
movl $4, %esi
callq calloc
movq %rax, %r12
movl $20971520, %edi # imm = 0x1400000
movl $4, %esi
callq calloc
movq %rax, %r13
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq $-1048576, %rbp # imm = 0xFFF00000
movq %r15, 272(%rsp) # 8-byte Spill
movq %r12, 264(%rsp) # 8-byte Spill
movq %r13, 256(%rsp) # 8-byte Spill
jmp .LBB3_19
.p2align 4, 0x90
.LBB3_21: # in Loop: Header=BB3_19 Depth=1
movq 216(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r13, %rdi
movl $2, %ecx
callq hipMemcpy
addq $1048576, %rbp # imm = 0x100000
addq $4194304, %r13 # imm = 0x400000
addq $4194304, %r12 # imm = 0x400000
addq $4194304, %r15 # imm = 0x400000
cmpq $19922944, %rbp # imm = 0x1300000
jae .LBB3_22
.LBB3_19: # =>This Inner Loop Header: Depth=1
movq 232(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 224(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_21
# %bb.20: # in Loop: Header=BB3_19 Depth=1
movq 232(%rsp), %rax
movq 224(%rsp), %rcx
movq 216(%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z6kernelPiS_S_, %edi
leaq 112(%rsp), %r9
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB3_21
.LBB3_22:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movss 248(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 244(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 240(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movss 112(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 272(%rsp), %rdi # 8-byte Reload
callq free
movq 264(%rsp), %rdi # 8-byte Reload
callq free
movq 256(%rsp), %rdi # 8-byte Reload
callq free
movq 136(%rsp), %rdi
callq hipStreamDestroy
movq 24(%rsp), %rdi
callq hipStreamDestroy
movq 16(%rsp), %rdi
callq hipStreamDestroy
movq 232(%rsp), %rdi
callq hipFree
movq 224(%rsp), %rdi
callq hipFree
movq 216(%rsp), %rdi
callq hipFree
movq 208(%rsp), %rdi
callq hipFree
movq 200(%rsp), %rdi
callq hipFree
movq 192(%rsp), %rdi
callq hipFree
movq 184(%rsp), %rdi
callq hipFree
movq 176(%rsp), %rdi
callq hipFree
movq 168(%rsp), %rdi
callq hipFree
movq 160(%rsp), %rdi
callq hipHostFree
movq 152(%rsp), %rdi
callq hipHostFree
movq 144(%rsp), %rdi
callq hipHostFree
movq 96(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
jmp .LBB3_23
.LBB3_1:
movl $.Lstr, %edi
callq puts@PLT
.LBB3_23:
xorl %eax, %eax
addq $1752, %rsp # imm = 0x6D8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10gSumVectorPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15gScalarMultVectPiS_S_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPiS_S_,@object # @_Z6kernelPiS_S_
.section .rodata,"a",@progbits
.globl _Z6kernelPiS_S_
.p2align 3, 0x0
_Z6kernelPiS_S_:
.quad _Z21__device_stub__kernelPiS_S_
.size _Z6kernelPiS_S_, 8
.type _Z10gSumVectorPiS_S_,@object # @_Z10gSumVectorPiS_S_
.globl _Z10gSumVectorPiS_S_
.p2align 3, 0x0
_Z10gSumVectorPiS_S_:
.quad _Z25__device_stub__gSumVectorPiS_S_
.size _Z10gSumVectorPiS_S_, 8
.type _Z15gScalarMultVectPiS_S_,@object # @_Z15gScalarMultVectPiS_S_
.globl _Z15gScalarMultVectPiS_S_
.p2align 3, 0x0
_Z15gScalarMultVectPiS_S_:
.quad _Z30__device_stub__gScalarMultVectPiS_S_
.size _Z15gScalarMultVectPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.4f ms\n"
.size .L.str.1, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPiS_S_"
.size .L__unnamed_1, 16
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10gSumVectorPiS_S_"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15gScalarMultVectPiS_S_"
.size .L__unnamed_3, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Device does not support overlapping"
.size .Lstr, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPiS_S_
.addrsig_sym _Z25__device_stub__gSumVectorPiS_S_
.addrsig_sym _Z30__device_stub__gScalarMultVectPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelPiS_S_
.addrsig_sym _Z10gSumVectorPiS_S_
.addrsig_sym _Z15gScalarMultVectPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "k_indices.cuh"
namespace timemachine {
// Takes a source and destination array.
// The value of the src is used as the index and the value in the destination array. Allows combining
// a series of indices to get a unique set of values.
void __global__ k_unique_indices(
const int N, // Number of values in src
const int K, // Number of values in dest
const unsigned int *__restrict__ src,
unsigned int *__restrict__ dest) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= N) {
return;
}
const unsigned int val = src[idx];
if (val >= K) {
return;
}
dest[val] = val;
}
// Any value that is >=N becomes the idx and any value that is an idx becomes N
void __global__ k_invert_indices(const int N, unsigned int *__restrict__ arr) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= N) {
return;
}
arr[idx] = arr[idx] >= N ? idx : N;
}
void __global__ k_arange(const int N, unsigned int *__restrict__ arr, unsigned int offset) {
const int atom_idx = blockIdx.x * blockDim.x + threadIdx.x;
if (atom_idx >= N) {
return;
}
arr[atom_idx] = atom_idx + offset;
}
void __global__ k_arange(const int N, int *__restrict__ arr, int offset) {
const int atom_idx = blockIdx.x * blockDim.x + threadIdx.x;
if (atom_idx >= N) {
return;
}
arr[atom_idx] = atom_idx + offset;
}
} // namespace timemachine | code for sm_80
Function : _ZN11timemachine8k_arangeEiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ IADD3 R5, R2, c[0x0][0x170], RZ ; /* 0x00005c0002057a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN11timemachine8k_arangeEiPjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ IADD3 R5, R2, c[0x0][0x170], RZ ; /* 0x00005c0002057a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN11timemachine16k_invert_indicesEiPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x004fc80003f06070 */
/*00b0*/ SEL R5, R0, c[0x0][0x160], P0 ; /* 0x0000580000057a07 */
/* 0x000fca0000000000 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN11timemachine16k_unique_indicesEiiPKjPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R0, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0200 */
/*0090*/ LDG.E.CONSTANT R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e9900 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x004fda0003f06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.WIDE.U32 R2, R5, R0, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fca00078e0000 */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "k_indices.cuh"
namespace timemachine {
// Takes a source and destination array.
// The value of the src is used as the index and the value in the destination array. Allows combining
// a series of indices to get a unique set of values.
void __global__ k_unique_indices(
const int N, // Number of values in src
const int K, // Number of values in dest
const unsigned int *__restrict__ src,
unsigned int *__restrict__ dest) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= N) {
return;
}
const unsigned int val = src[idx];
if (val >= K) {
return;
}
dest[val] = val;
}
// Any value that is >=N becomes the idx and any value that is an idx becomes N
void __global__ k_invert_indices(const int N, unsigned int *__restrict__ arr) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= N) {
return;
}
arr[idx] = arr[idx] >= N ? idx : N;
}
void __global__ k_arange(const int N, unsigned int *__restrict__ arr, unsigned int offset) {
const int atom_idx = blockIdx.x * blockDim.x + threadIdx.x;
if (atom_idx >= N) {
return;
}
arr[atom_idx] = atom_idx + offset;
}
void __global__ k_arange(const int N, int *__restrict__ arr, int offset) {
const int atom_idx = blockIdx.x * blockDim.x + threadIdx.x;
if (atom_idx >= N) {
return;
}
arr[atom_idx] = atom_idx + offset;
}
} // namespace timemachine | .file "tmpxft_0015271f_00000000-6_k_indices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj
.type _Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj, @function
_Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
movq %rdx, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
movq %rcx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11timemachine16k_unique_indicesEiiPKjPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj, .-_Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj
.globl _ZN11timemachine16k_unique_indicesEiiPKjPj
.type _ZN11timemachine16k_unique_indicesEiiPKjPj, @function
_ZN11timemachine16k_unique_indicesEiiPKjPj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN11timemachine16k_unique_indicesEiiPKjPj, .-_ZN11timemachine16k_unique_indicesEiiPKjPj
.globl _Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj
.type _Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj, @function
_Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11timemachine16k_invert_indicesEiPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj, .-_Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj
.globl _ZN11timemachine16k_invert_indicesEiPj
.type _ZN11timemachine16k_invert_indicesEiPj, @function
_ZN11timemachine16k_invert_indicesEiPj:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZN11timemachine16k_invert_indicesEiPj, .-_ZN11timemachine16k_invert_indicesEiPj
.globl _Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj
.type _Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj, @function
_Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11timemachine8k_arangeEiPjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj, .-_Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj
.globl _ZN11timemachine8k_arangeEiPjj
.type _ZN11timemachine8k_arangeEiPjj, @function
_ZN11timemachine8k_arangeEiPjj:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZN11timemachine8k_arangeEiPjj, .-_ZN11timemachine8k_arangeEiPjj
.globl _Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii
.type _Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii, @function
_Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii:
.LFB2057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11timemachine8k_arangeEiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii, .-_Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii
.globl _ZN11timemachine8k_arangeEiPii
.type _ZN11timemachine8k_arangeEiPii, @function
_ZN11timemachine8k_arangeEiPii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZN11timemachine8k_arangeEiPii, .-_ZN11timemachine8k_arangeEiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN11timemachine8k_arangeEiPii"
.align 8
.LC1:
.string "_ZN11timemachine8k_arangeEiPjj"
.align 8
.LC2:
.string "_ZN11timemachine16k_invert_indicesEiPj"
.align 8
.LC3:
.string "_ZN11timemachine16k_unique_indicesEiiPKjPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine8k_arangeEiPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine8k_arangeEiPjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine16k_invert_indicesEiPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine16k_unique_indicesEiiPKjPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "k_indices.cuh"
namespace timemachine {
// Takes a source and destination array.
// The value of the src is used as the index and the value in the destination array. Allows combining
// a series of indices to get a unique set of values.
void __global__ k_unique_indices(
const int N, // Number of values in src
const int K, // Number of values in dest
const unsigned int *__restrict__ src,
unsigned int *__restrict__ dest) {
const int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= N) {
return;
}
const unsigned int val = src[idx];
if (val >= K) {
return;
}
dest[val] = val;
}
// Any value that is >=N becomes the idx and any value that is an idx becomes N
void __global__ k_invert_indices(const int N, unsigned int *__restrict__ arr) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx >= N) {
return;
}
arr[idx] = arr[idx] >= N ? idx : N;
}
void __global__ k_arange(const int N, unsigned int *__restrict__ arr, unsigned int offset) {
const int atom_idx = blockIdx.x * blockDim.x + threadIdx.x;
if (atom_idx >= N) {
return;
}
arr[atom_idx] = atom_idx + offset;
}
void __global__ k_arange(const int N, int *__restrict__ arr, int offset) {
const int atom_idx = blockIdx.x * blockDim.x + threadIdx.x;
if (atom_idx >= N) {
return;
}
arr[atom_idx] = atom_idx + offset;
}
} // namespace timemachine | #pragma once
#include <hip/hip_runtime.h>
namespace timemachine {
// Takes a source and destination array. Assumes K <= N with values in the src are less than or equal
// to K. The value of the src is used as the indice and the value in the destination array. Allows combining
// a series of indices to get a unique set of values.
void __global__ k_unique_indices(
const int N, // Number of values in src
const int K, // Number of values in dest
const unsigned int *__restrict__ src,
unsigned int *__restrict__ dest);
// Any value that is >=N becomes the idx and any value that is an idx becomes N. Assumes
// that the array is made up of indice values that correspond to their index in the array,
// otherwise the inversion may contain values that were in the input.
void __global__ k_invert_indices(const int N, unsigned int *__restrict__ arr);
void __global__ k_arange(const int N, unsigned int *__restrict__ arr, unsigned int offset = 0);
void __global__ k_arange(const int N, int *__restrict__ arr, int offset = 0);
} // namespace timemachine |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
namespace timemachine {
// Takes a source and destination array. Assumes K <= N with values in the src are less than or equal
// to K. The value of the src is used as the indice and the value in the destination array. Allows combining
// a series of indices to get a unique set of values.
void __global__ k_unique_indices(
const int N, // Number of values in src
const int K, // Number of values in dest
const unsigned int *__restrict__ src,
unsigned int *__restrict__ dest);
// Any value that is >=N becomes the idx and any value that is an idx becomes N. Assumes
// that the array is made up of indice values that correspond to their index in the array,
// otherwise the inversion may contain values that were in the input.
void __global__ k_invert_indices(const int N, unsigned int *__restrict__ arr);
void __global__ k_arange(const int N, unsigned int *__restrict__ arr, unsigned int offset = 0);
void __global__ k_arange(const int N, int *__restrict__ arr, int offset = 0);
} // namespace timemachine | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
namespace timemachine {
// Takes a source and destination array. Assumes K <= N with values in the src are less than or equal
// to K. The value of the src is used as the indice and the value in the destination array. Allows combining
// a series of indices to get a unique set of values.
void __global__ k_unique_indices(
const int N, // Number of values in src
const int K, // Number of values in dest
const unsigned int *__restrict__ src,
unsigned int *__restrict__ dest);
// Any value that is >=N becomes the idx and any value that is an idx becomes N. Assumes
// that the array is made up of indice values that correspond to their index in the array,
// otherwise the inversion may contain values that were in the input.
void __global__ k_invert_indices(const int N, unsigned int *__restrict__ arr);
void __global__ k_arange(const int N, unsigned int *__restrict__ arr, unsigned int offset = 0);
void __global__ k_arange(const int N, int *__restrict__ arr, int offset = 0);
} // namespace timemachine | .text
.file "k_indices.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN11timemachine8k_arangeEiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ IADD3 R5, R2, c[0x0][0x170], RZ ; /* 0x00005c0002057a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN11timemachine8k_arangeEiPjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ IADD3 R5, R2, c[0x0][0x170], RZ ; /* 0x00005c0002057a10 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN11timemachine16k_invert_indicesEiPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x004fc80003f06070 */
/*00b0*/ SEL R5, R0, c[0x0][0x160], P0 ; /* 0x0000580000057a07 */
/* 0x000fca0000000000 */
/*00c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN11timemachine16k_unique_indicesEiiPKjPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R0, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff007435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R0, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0200 */
/*0090*/ LDG.E.CONSTANT R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea4000c1e9900 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x164], PT ; /* 0x0000590005007a0c */
/* 0x004fda0003f06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.WIDE.U32 R2, R5, R0, c[0x0][0x170] ; /* 0x00005c0005027625 */
/* 0x000fca00078e0000 */
/*00d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015271f_00000000-6_k_indices.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj
.type _Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj, @function
_Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
movq %rdx, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
movq %rcx, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11timemachine16k_unique_indicesEiiPKjPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj, .-_Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj
.globl _ZN11timemachine16k_unique_indicesEiiPKjPj
.type _ZN11timemachine16k_unique_indicesEiiPKjPj, @function
_ZN11timemachine16k_unique_indicesEiiPKjPj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z56__device_stub__ZN11timemachine16k_unique_indicesEiiPKjPjiiPKjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZN11timemachine16k_unique_indicesEiiPKjPj, .-_ZN11timemachine16k_unique_indicesEiiPKjPj
.globl _Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj
.type _Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj, @function
_Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11timemachine16k_invert_indicesEiPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj, .-_Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj
.globl _ZN11timemachine16k_invert_indicesEiPj
.type _ZN11timemachine16k_invert_indicesEiPj, @function
_ZN11timemachine16k_invert_indicesEiPj:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__ZN11timemachine16k_invert_indicesEiPjiPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZN11timemachine16k_invert_indicesEiPj, .-_ZN11timemachine16k_invert_indicesEiPj
.globl _Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj
.type _Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj, @function
_Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj:
.LFB2055:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11timemachine8k_arangeEiPjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj, .-_Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj
.globl _ZN11timemachine8k_arangeEiPjj
.type _ZN11timemachine8k_arangeEiPjj, @function
_ZN11timemachine8k_arangeEiPjj:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__ZN11timemachine8k_arangeEiPjjiPjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZN11timemachine8k_arangeEiPjj, .-_ZN11timemachine8k_arangeEiPjj
.globl _Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii
.type _Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii, @function
_Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii:
.LFB2057:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN11timemachine8k_arangeEiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii, .-_Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii
.globl _ZN11timemachine8k_arangeEiPii
.type _ZN11timemachine8k_arangeEiPii, @function
_ZN11timemachine8k_arangeEiPii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__ZN11timemachine8k_arangeEiPiiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZN11timemachine8k_arangeEiPii, .-_ZN11timemachine8k_arangeEiPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN11timemachine8k_arangeEiPii"
.align 8
.LC1:
.string "_ZN11timemachine8k_arangeEiPjj"
.align 8
.LC2:
.string "_ZN11timemachine16k_invert_indicesEiPj"
.align 8
.LC3:
.string "_ZN11timemachine16k_unique_indicesEiiPKjPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine8k_arangeEiPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine8k_arangeEiPjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine16k_invert_indicesEiPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZN11timemachine16k_unique_indicesEiiPKjPj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "k_indices.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void _reluforw(int n, float *y) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (y[i] < 0) y[i] = 0;
i += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z9_reluforwiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ FSETP.GEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x004fda0003f0e000 */
/*00d0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101904 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0x70 ; /* 0xffffff7000008947 */
/* 0x001fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void _reluforw(int n, float *y) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (y[i] < 0) y[i] = 0;
i += blockDim.x * gridDim.x;
}
} | .file "tmpxft_000d83df_00000000-6__reluforw.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9_reluforwiPfiPf
.type _Z29__device_stub__Z9_reluforwiPfiPf, @function
_Z29__device_stub__Z9_reluforwiPfiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9_reluforwiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z9_reluforwiPfiPf, .-_Z29__device_stub__Z9_reluforwiPfiPf
.globl _Z9_reluforwiPf
.type _Z9_reluforwiPf, @function
_Z9_reluforwiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9_reluforwiPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9_reluforwiPf, .-_Z9_reluforwiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9_reluforwiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9_reluforwiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void _reluforw(int n, float *y) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (y[i] < 0) y[i] = 0;
i += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _reluforw(int n, float *y) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (y[i] < 0) y[i] = 0;
i += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _reluforw(int n, float *y) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (y[i] < 0) y[i] = 0;
i += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9_reluforwiPf
.globl _Z9_reluforwiPf
.p2align 8
.type _Z9_reluforwiPf,@function
_Z9_reluforwiPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s5
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_gt_f32_e32 0, v4
s_cbranch_execz .LBB0_2
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9_reluforwiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9_reluforwiPf, .Lfunc_end0-_Z9_reluforwiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9_reluforwiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9_reluforwiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void _reluforw(int n, float *y) {
int i = threadIdx.x + blockIdx.x * blockDim.x;
while (i < n) {
if (y[i] < 0) y[i] = 0;
i += blockDim.x * gridDim.x;
}
} | .text
.file "_reluforw.hip"
.globl _Z24__device_stub___reluforwiPf # -- Begin function _Z24__device_stub___reluforwiPf
.p2align 4, 0x90
.type _Z24__device_stub___reluforwiPf,@function
_Z24__device_stub___reluforwiPf: # @_Z24__device_stub___reluforwiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9_reluforwiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub___reluforwiPf, .Lfunc_end0-_Z24__device_stub___reluforwiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9_reluforwiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9_reluforwiPf,@object # @_Z9_reluforwiPf
.section .rodata,"a",@progbits
.globl _Z9_reluforwiPf
.p2align 3, 0x0
_Z9_reluforwiPf:
.quad _Z24__device_stub___reluforwiPf
.size _Z9_reluforwiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9_reluforwiPf"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub___reluforwiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9_reluforwiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9_reluforwiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD R0, R5, c[0x0][0xc], R0 ; /* 0x0000030005007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ FSETP.GEU.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x004fda0003f0e000 */
/*00d0*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0001e2000c101904 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0x70 ; /* 0xffffff7000008947 */
/* 0x001fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9_reluforwiPf
.globl _Z9_reluforwiPf
.p2align 8
.type _Z9_reluforwiPf,@function
_Z9_reluforwiPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_5
s_load_b32 s2, s[2:3], 0x0
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s5
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
v_add_nc_u32_e32 v1, s2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_5
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_gt_f32_e32 0, v4
s_cbranch_execz .LBB0_2
global_store_b32 v[2:3], v0, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9_reluforwiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9_reluforwiPf, .Lfunc_end0-_Z9_reluforwiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9_reluforwiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9_reluforwiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d83df_00000000-6__reluforw.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9_reluforwiPfiPf
.type _Z29__device_stub__Z9_reluforwiPfiPf, @function
_Z29__device_stub__Z9_reluforwiPfiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9_reluforwiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z9_reluforwiPfiPf, .-_Z29__device_stub__Z9_reluforwiPfiPf
.globl _Z9_reluforwiPf
.type _Z9_reluforwiPf, @function
_Z9_reluforwiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9_reluforwiPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9_reluforwiPf, .-_Z9_reluforwiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9_reluforwiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9_reluforwiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "_reluforw.hip"
.globl _Z24__device_stub___reluforwiPf # -- Begin function _Z24__device_stub___reluforwiPf
.p2align 4, 0x90
.type _Z24__device_stub___reluforwiPf,@function
_Z24__device_stub___reluforwiPf: # @_Z24__device_stub___reluforwiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9_reluforwiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub___reluforwiPf, .Lfunc_end0-_Z24__device_stub___reluforwiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9_reluforwiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9_reluforwiPf,@object # @_Z9_reluforwiPf
.section .rodata,"a",@progbits
.globl _Z9_reluforwiPf
.p2align 3, 0x0
_Z9_reluforwiPf:
.quad _Z24__device_stub___reluforwiPf
.size _Z9_reluforwiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9_reluforwiPf"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub___reluforwiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9_reluforwiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<fstream>
#include <ctime>
#define M_PI 3.14276
#define c 299792458
#define mu0 M_PI*4e-7
#define eta0 c*mu0
double** declare_array2D(int, int);
using namespace std;
int main() {
std::clock_t start = std::clock();
int NX = 900;
int NY = 900;
int NT = 1000;
double dl = 1;
double dt = dl / (sqrt(2.) * c);
//2D mesh variables
double tempV = 0, E0 = 0, V = 0;
double** V1 = declare_array2D(NX, NY);
double** V2 = declare_array2D(NX, NY);
double** V3 = declare_array2D(NX, NY);
double** V4 = declare_array2D(NX, NY);
double Z = eta0 / sqrt(2.);
//boundary coefficients
double rXmin = -1;
double rXmax = -1;
double rYmin = -1;
double rYmax = -1;
//input / output
double width = 20 * dt * sqrt(2.);
double delay = 100 * dt * sqrt(2.);
int Ein[] = { 10,10 };
int Eout[] = { 15,15 };
ofstream output("CPU.csv");
for (int n = 0; n < NT; n++) {
//source
E0 = (1 / sqrt(2.)) * exp(-(n * dt - delay) * (n * dt - delay) / (width * width));
V1[Ein[0]][Ein[1]] = V1[Ein[0]][Ein[1]] + E0;
V2[Ein[0]][Ein[1]] = V2[Ein[0]][Ein[1]] - E0;
V3[Ein[0]][Ein[1]] = V3[Ein[0]][Ein[1]] - E0;
V4[Ein[0]][Ein[1]] = V4[Ein[0]][Ein[1]] + E0;
//*/
// original scatter
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double I = (2 * V1[x][y] + 2 * V4[x][y] - 2 * V2[x][y] - 2 * V3[x][y]) / (4 * Z);
V = 2 * V1[x][y] - I * Z; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + I * Z; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + I * Z; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - I * Z; //port4
V4[x][y] = V - V4[x][y];
}
}
/*/
// scatter without Z
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double IZ = ((V1[x][y] + V4[x][y] - V2[x][y] - V3[x][y]) / 2);
V = 2 * V1[x][y] - IZ; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + IZ; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + IZ; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - IZ; //port4
V4[x][y] = V - V4[x][y];
}
}
//*/
//connect
for (int x = 1; x < NX; x++) {
for (int y = 0; y < NY; y++) {
tempV = V2[x][y];
V2[x][y] = V4[x - 1][y];
V4[x - 1][y] = tempV;
}
}
for (int x = 0; x < NX; x++) {
for (int y = 1; y < NY; y++) {
tempV = V1[x][y];
V1[x][y] = V3[x][y - 1];
V3[x][y - 1] = tempV;
}
}
//boundary
for (int x = 0; x < NX; x++) {
V3[x][NY - 1] = rYmax * V3[x][NY - 1];
V1[x][0] = rYmin * V1[x][0];
}
for (int y = 0; y < NY; y++) {
V4[NX - 1][y] = rXmax * V4[NX - 1][y];
V2[0][y] = rXmin * V2[0][y];
}
output << n * dt << "," << V2[Eout[0]][Eout[1]] + V4[Eout[0]][Eout[1]] << endl;
if (n % 100 == 0)
cout << n << endl;
}
output.close();
cout << "Done";
std::cout << ((std::clock() - start) / (double)CLOCKS_PER_SEC) << '\n';
cin.get();
}
double** declare_array2D(int NX, int NY) {
double** V = new double* [NX];
for (int x = 0; x < NX; x++) {
V[x] = new double[NY];
}
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
V[x][y] = 0;
}
}
return V;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<fstream>
#include <ctime>
#define M_PI 3.14276
#define c 299792458
#define mu0 M_PI*4e-7
#define eta0 c*mu0
double** declare_array2D(int, int);
using namespace std;
int main() {
std::clock_t start = std::clock();
int NX = 900;
int NY = 900;
int NT = 1000;
double dl = 1;
double dt = dl / (sqrt(2.) * c);
//2D mesh variables
double tempV = 0, E0 = 0, V = 0;
double** V1 = declare_array2D(NX, NY);
double** V2 = declare_array2D(NX, NY);
double** V3 = declare_array2D(NX, NY);
double** V4 = declare_array2D(NX, NY);
double Z = eta0 / sqrt(2.);
//boundary coefficients
double rXmin = -1;
double rXmax = -1;
double rYmin = -1;
double rYmax = -1;
//input / output
double width = 20 * dt * sqrt(2.);
double delay = 100 * dt * sqrt(2.);
int Ein[] = { 10,10 };
int Eout[] = { 15,15 };
ofstream output("CPU.csv");
for (int n = 0; n < NT; n++) {
//source
E0 = (1 / sqrt(2.)) * exp(-(n * dt - delay) * (n * dt - delay) / (width * width));
V1[Ein[0]][Ein[1]] = V1[Ein[0]][Ein[1]] + E0;
V2[Ein[0]][Ein[1]] = V2[Ein[0]][Ein[1]] - E0;
V3[Ein[0]][Ein[1]] = V3[Ein[0]][Ein[1]] - E0;
V4[Ein[0]][Ein[1]] = V4[Ein[0]][Ein[1]] + E0;
//*/
// original scatter
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double I = (2 * V1[x][y] + 2 * V4[x][y] - 2 * V2[x][y] - 2 * V3[x][y]) / (4 * Z);
V = 2 * V1[x][y] - I * Z; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + I * Z; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + I * Z; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - I * Z; //port4
V4[x][y] = V - V4[x][y];
}
}
/*/
// scatter without Z
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double IZ = ((V1[x][y] + V4[x][y] - V2[x][y] - V3[x][y]) / 2);
V = 2 * V1[x][y] - IZ; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + IZ; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + IZ; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - IZ; //port4
V4[x][y] = V - V4[x][y];
}
}
//*/
//connect
for (int x = 1; x < NX; x++) {
for (int y = 0; y < NY; y++) {
tempV = V2[x][y];
V2[x][y] = V4[x - 1][y];
V4[x - 1][y] = tempV;
}
}
for (int x = 0; x < NX; x++) {
for (int y = 1; y < NY; y++) {
tempV = V1[x][y];
V1[x][y] = V3[x][y - 1];
V3[x][y - 1] = tempV;
}
}
//boundary
for (int x = 0; x < NX; x++) {
V3[x][NY - 1] = rYmax * V3[x][NY - 1];
V1[x][0] = rYmin * V1[x][0];
}
for (int y = 0; y < NY; y++) {
V4[NX - 1][y] = rXmax * V4[NX - 1][y];
V2[0][y] = rXmin * V2[0][y];
}
output << n * dt << "," << V2[Eout[0]][Eout[1]] + V4[Eout[0]][Eout[1]] << endl;
if (n % 100 == 0)
cout << n << endl;
}
output.close();
cout << "Done";
std::cout << ((std::clock() - start) / (double)CLOCKS_PER_SEC) << '\n';
cin.get();
}
double** declare_array2D(int NX, int NY) {
double** V = new double* [NX];
for (int x = 0; x < NX; x++) {
V[x] = new double[NY];
}
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
V[x][y] = 0;
}
}
return V;
} | .file "tmpxft_000edeea_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3804:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3804:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15declare_array2Dii
.type _Z15declare_array2Dii, @function
_Z15declare_array2Dii:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movslq %edi, %rbp
movq %rbp, %rax
shrq $60, %rax
jne .L4
movl %edi, %ebx
movl %esi, %r13d
salq $3, %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L3
movslq %r13d, %r12
movq %r12, %rax
shrq $60, %rax
jne .L18
salq $3, %r12
movq %r14, %rbx
addq %r14, %rbp
movq %r14, %r15
.L7:
movq %r12, %rdi
call _Znam@PLT
movq %rax, (%r15)
addq $8, %r15
cmpq %rbp, %r15
jne .L7
jmp .L8
.L4:
call __cxa_throw_bad_array_new_length@PLT
.L18:
call __cxa_throw_bad_array_new_length@PLT
.L12:
movq (%rbx), %rax
leaq (%r12,%rax), %rdx
.L11:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L11
.L13:
addq $8, %rbx
cmpq %rbp, %rbx
je .L3
.L8:
testl %r13d, %r13d
jg .L12
jmp .L13
.L3:
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _Z15declare_array2Dii, .-_Z15declare_array2Dii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3827:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3827:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CPU.csv"
.LC9:
.string ","
.LC10:
.string "Done"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, 24(%rsp)
movl $900, %esi
movl $900, %edi
.LEHB0:
call _Z15declare_array2Dii
movq %rax, %r13
movl $900, %esi
movl $900, %edi
call _Z15declare_array2Dii
movq %rax, %rbp
movl $900, %esi
movl $900, %edi
call _Z15declare_array2Dii
movq %rax, %r12
movl $900, %esi
movl $900, %edi
call _Z15declare_array2Dii
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $16, %edx
leaq .LC1(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movl $0, 20(%rsp)
jmp .L40
.L55:
movq 8(%rsp), %rdx
addq $8, %r10
addq $8, %rsi
addq $8, %r8
addq $8, %rdi
cmpq %r11, %rsi
je .L24
.L22:
movl $0, %eax
movq %rdx, 8(%rsp)
.L23:
movq %rax, %r15
addq (%r10), %r15
movsd (%r15), %xmm5
movapd %xmm5, %xmm1
addsd %xmm5, %xmm1
movq (%rsi), %rdx
movsd (%rdx,%rax), %xmm0
addsd %xmm0, %xmm0
addsd %xmm1, %xmm0
movq (%r8), %rdx
movsd (%rdx,%rax), %xmm4
addsd %xmm4, %xmm4
subsd %xmm4, %xmm0
movq (%rdi), %rdx
movsd (%rdx,%rax), %xmm4
addsd %xmm4, %xmm4
subsd %xmm4, %xmm0
divsd %xmm3, %xmm0
mulsd %xmm2, %xmm0
subsd %xmm0, %xmm1
subsd %xmm5, %xmm1
movsd %xmm1, (%r15)
movq %rax, %r15
addq (%r8), %r15
movsd (%r15), %xmm4
movapd %xmm4, %xmm1
addsd %xmm4, %xmm1
addsd %xmm0, %xmm1
subsd %xmm4, %xmm1
movsd %xmm1, (%r15)
movq %rax, %r15
addq (%rdi), %r15
movsd (%r15), %xmm4
movapd %xmm4, %xmm1
addsd %xmm4, %xmm1
addsd %xmm0, %xmm1
subsd %xmm4, %xmm1
movsd %xmm1, (%r15)
movq %rax, %r15
addq (%rsi), %r15
movsd (%r15), %xmm4
movapd %xmm4, %xmm1
addsd %xmm4, %xmm1
subsd %xmm0, %xmm1
subsd %xmm4, %xmm1
movsd %xmm1, (%r15)
addq $8, %rax
cmpq $7200, %rax
jne .L23
jmp .L55
.L57:
addq $8, %rdi
addq $8, %rcx
cmpq %r8, %rcx
je .L56
.L26:
movl $0, %eax
.L25:
movq %rax, %rsi
addq (%rdi), %rsi
movsd (%rsi), %xmm0
movq (%rcx), %r10
movsd (%r10,%rax), %xmm1
movsd %xmm1, (%rsi)
movq (%rcx), %rsi
movsd %xmm0, (%rsi,%rax)
addq $8, %rax
cmpq $7200, %rax
jne .L25
jmp .L57
.L56:
leaq 7200(%r12), %rdi
jmp .L27
.L24:
leaq 8(%rbp), %rdi
leaq 7192(%rbx), %r8
jmp .L26
.L58:
addq $8, %r9
addq $8, %rdx
cmpq %rdi, %rdx
je .L44
.L27:
movl $8, %eax
.L28:
movq %rax, %rcx
addq (%r9), %rcx
movsd (%rcx), %xmm0
movq (%rdx), %rsi
movsd -8(%rsi,%rax), %xmm1
movsd %xmm1, (%rcx)
movq (%rdx), %rcx
movsd %xmm0, -8(%rcx,%rax)
addq $8, %rax
cmpq $7200, %rax
jne .L28
jmp .L58
.L44:
movl $0, %eax
.L29:
movq (%r12,%rax), %rdx
movsd 7192(%rdx), %xmm0
xorpd .LC4(%rip), %xmm0
movsd %xmm0, 7192(%rdx)
movq 0(%r13,%rax), %rdx
movsd (%rdx), %xmm0
xorpd .LC4(%rip), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq $7200, %rax
jne .L29
movl $0, %eax
.L30:
movq %rax, %rdx
addq 7192(%rbx), %rdx
movsd (%rdx), %xmm0
xorpd .LC4(%rip), %xmm0
movsd %xmm0, (%rdx)
movq %rax, %rdx
addq 0(%rbp), %rdx
movsd (%rdx), %xmm0
xorpd .LC4(%rip), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq $7200, %rax
jne .L30
leaq 32(%rsp), %rdi
movq %r14, %xmm0
.LEHB1:
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r14
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 120(%rbp), %rdx
movq 120(%rbx), %rax
movsd 120(%rdx), %xmm0
addsd 120(%rax), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .L59
cmpb $0, 56(%r14)
je .L33
movzbl 67(%r14), %eax
.L34:
movsbl %al, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
jmp .L60
.L59:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L61
call _ZSt16__throw_bad_castv@PLT
.L45:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L61:
call __stack_chk_fail@PLT
.L33:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L34
.L60:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl 20(%rsp), %edi
movslq %edi, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edi, %edx
sarl $31, %edx
subl %edx, %eax
imull $100, %eax, %eax
cmpl %eax, %edi
je .L62
.L35:
addl $1, 20(%rsp)
movl 20(%rsp), %eax
cmpl $1000, %eax
je .L63
.L40:
pxor %xmm0, %xmm0
cvtsi2sdl 20(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
movq %xmm0, %r14
movapd %xmm0, %xmm1
subsd .LC3(%rip), %xmm1
movapd %xmm1, %xmm0
xorpd .LC4(%rip), %xmm0
mulsd %xmm1, %xmm0
divsd .LC5(%rip), %xmm0
call exp@PLT
mulsd .LC6(%rip), %xmm0
movq 80(%r13), %rax
movapd %xmm0, %xmm1
addsd 80(%rax), %xmm1
movsd %xmm1, 80(%rax)
movq 80(%rbp), %rax
movsd 80(%rax), %xmm1
subsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 80(%r12), %rax
movsd 80(%rax), %xmm1
subsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 80(%rbx), %rax
addsd 80(%rax), %xmm0
movsd %xmm0, 80(%rax)
movq %r13, %r9
movq %rbx, %rcx
movq %rbp, %r8
movq %r12, %rdx
leaq 7200(%rbx), %r11
movq %r12, %rdi
movq %rbx, %rsi
movq %r13, %r10
movsd .LC7(%rip), %xmm3
movsd .LC8(%rip), %xmm2
jmp .L22
.L62:
movl %edi, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .L64
cmpb $0, 56(%r14)
je .L38
movzbl 67(%r14), %eax
.L39:
movsbl %al, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
jmp .L65
.L64:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L66:
call __stack_chk_fail@PLT
.L38:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L39
.L65:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L35
.L63:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq 24(%rsp), %rbx
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC11(%rip), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq _ZSt3cin(%rip), %rdi
call _ZNSi3getEv@PLT
.LEHE1:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3800:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 1498987438
.long 1042563772
.align 8
.LC3:
.long 1739959091
.long 1050043030
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC5:
.long 1430085210
.long 1022626609
.align 8
.LC6:
.long 1719614412
.long 1072079006
.align 8
.LC7:
.long -94971825
.long 1083221964
.align 8
.LC8:
.long -94971825
.long 1081124812
.align 8
.LC11:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<fstream>
#include <ctime>
#define M_PI 3.14276
#define c 299792458
#define mu0 M_PI*4e-7
#define eta0 c*mu0
double** declare_array2D(int, int);
using namespace std;
int main() {
std::clock_t start = std::clock();
int NX = 900;
int NY = 900;
int NT = 1000;
double dl = 1;
double dt = dl / (sqrt(2.) * c);
//2D mesh variables
double tempV = 0, E0 = 0, V = 0;
double** V1 = declare_array2D(NX, NY);
double** V2 = declare_array2D(NX, NY);
double** V3 = declare_array2D(NX, NY);
double** V4 = declare_array2D(NX, NY);
double Z = eta0 / sqrt(2.);
//boundary coefficients
double rXmin = -1;
double rXmax = -1;
double rYmin = -1;
double rYmax = -1;
//input / output
double width = 20 * dt * sqrt(2.);
double delay = 100 * dt * sqrt(2.);
int Ein[] = { 10,10 };
int Eout[] = { 15,15 };
ofstream output("CPU.csv");
for (int n = 0; n < NT; n++) {
//source
E0 = (1 / sqrt(2.)) * exp(-(n * dt - delay) * (n * dt - delay) / (width * width));
V1[Ein[0]][Ein[1]] = V1[Ein[0]][Ein[1]] + E0;
V2[Ein[0]][Ein[1]] = V2[Ein[0]][Ein[1]] - E0;
V3[Ein[0]][Ein[1]] = V3[Ein[0]][Ein[1]] - E0;
V4[Ein[0]][Ein[1]] = V4[Ein[0]][Ein[1]] + E0;
//*/
// original scatter
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double I = (2 * V1[x][y] + 2 * V4[x][y] - 2 * V2[x][y] - 2 * V3[x][y]) / (4 * Z);
V = 2 * V1[x][y] - I * Z; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + I * Z; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + I * Z; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - I * Z; //port4
V4[x][y] = V - V4[x][y];
}
}
/*/
// scatter without Z
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double IZ = ((V1[x][y] + V4[x][y] - V2[x][y] - V3[x][y]) / 2);
V = 2 * V1[x][y] - IZ; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + IZ; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + IZ; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - IZ; //port4
V4[x][y] = V - V4[x][y];
}
}
//*/
//connect
for (int x = 1; x < NX; x++) {
for (int y = 0; y < NY; y++) {
tempV = V2[x][y];
V2[x][y] = V4[x - 1][y];
V4[x - 1][y] = tempV;
}
}
for (int x = 0; x < NX; x++) {
for (int y = 1; y < NY; y++) {
tempV = V1[x][y];
V1[x][y] = V3[x][y - 1];
V3[x][y - 1] = tempV;
}
}
//boundary
for (int x = 0; x < NX; x++) {
V3[x][NY - 1] = rYmax * V3[x][NY - 1];
V1[x][0] = rYmin * V1[x][0];
}
for (int y = 0; y < NY; y++) {
V4[NX - 1][y] = rXmax * V4[NX - 1][y];
V2[0][y] = rXmin * V2[0][y];
}
output << n * dt << "," << V2[Eout[0]][Eout[1]] + V4[Eout[0]][Eout[1]] << endl;
if (n % 100 == 0)
cout << n << endl;
}
output.close();
cout << "Done";
std::cout << ((std::clock() - start) / (double)CLOCKS_PER_SEC) << '\n';
cin.get();
}
double** declare_array2D(int NX, int NY) {
double** V = new double* [NX];
for (int x = 0; x < NX; x++) {
V[x] = new double[NY];
}
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
V[x][y] = 0;
}
}
return V;
} | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<fstream>
#include <ctime>
#define M_PI 3.14276
#define c 299792458
#define mu0 M_PI*4e-7
#define eta0 c*mu0
double** declare_array2D(int, int);
using namespace std;
int main() {
std::clock_t start = std::clock();
int NX = 900;
int NY = 900;
int NT = 1000;
double dl = 1;
double dt = dl / (sqrt(2.) * c);
//2D mesh variables
double tempV = 0, E0 = 0, V = 0;
double** V1 = declare_array2D(NX, NY);
double** V2 = declare_array2D(NX, NY);
double** V3 = declare_array2D(NX, NY);
double** V4 = declare_array2D(NX, NY);
double Z = eta0 / sqrt(2.);
//boundary coefficients
double rXmin = -1;
double rXmax = -1;
double rYmin = -1;
double rYmax = -1;
//input / output
double width = 20 * dt * sqrt(2.);
double delay = 100 * dt * sqrt(2.);
int Ein[] = { 10,10 };
int Eout[] = { 15,15 };
ofstream output("CPU.csv");
for (int n = 0; n < NT; n++) {
//source
E0 = (1 / sqrt(2.)) * exp(-(n * dt - delay) * (n * dt - delay) / (width * width));
V1[Ein[0]][Ein[1]] = V1[Ein[0]][Ein[1]] + E0;
V2[Ein[0]][Ein[1]] = V2[Ein[0]][Ein[1]] - E0;
V3[Ein[0]][Ein[1]] = V3[Ein[0]][Ein[1]] - E0;
V4[Ein[0]][Ein[1]] = V4[Ein[0]][Ein[1]] + E0;
//*/
// original scatter
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double I = (2 * V1[x][y] + 2 * V4[x][y] - 2 * V2[x][y] - 2 * V3[x][y]) / (4 * Z);
V = 2 * V1[x][y] - I * Z; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + I * Z; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + I * Z; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - I * Z; //port4
V4[x][y] = V - V4[x][y];
}
}
/*/
// scatter without Z
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double IZ = ((V1[x][y] + V4[x][y] - V2[x][y] - V3[x][y]) / 2);
V = 2 * V1[x][y] - IZ; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + IZ; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + IZ; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - IZ; //port4
V4[x][y] = V - V4[x][y];
}
}
//*/
//connect
for (int x = 1; x < NX; x++) {
for (int y = 0; y < NY; y++) {
tempV = V2[x][y];
V2[x][y] = V4[x - 1][y];
V4[x - 1][y] = tempV;
}
}
for (int x = 0; x < NX; x++) {
for (int y = 1; y < NY; y++) {
tempV = V1[x][y];
V1[x][y] = V3[x][y - 1];
V3[x][y - 1] = tempV;
}
}
//boundary
for (int x = 0; x < NX; x++) {
V3[x][NY - 1] = rYmax * V3[x][NY - 1];
V1[x][0] = rYmin * V1[x][0];
}
for (int y = 0; y < NY; y++) {
V4[NX - 1][y] = rXmax * V4[NX - 1][y];
V2[0][y] = rXmin * V2[0][y];
}
output << n * dt << "," << V2[Eout[0]][Eout[1]] + V4[Eout[0]][Eout[1]] << endl;
if (n % 100 == 0)
cout << n << endl;
}
output.close();
cout << "Done";
std::cout << ((std::clock() - start) / (double)CLOCKS_PER_SEC) << '\n';
cin.get();
}
double** declare_array2D(int NX, int NY) {
double** V = new double* [NX];
for (int x = 0; x < NX; x++) {
V[x] = new double[NY];
}
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
V[x][y] = 0;
}
}
return V;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<fstream>
#include <ctime>
#define M_PI 3.14276
#define c 299792458
#define mu0 M_PI*4e-7
#define eta0 c*mu0
double** declare_array2D(int, int);
using namespace std;
int main() {
std::clock_t start = std::clock();
int NX = 900;
int NY = 900;
int NT = 1000;
double dl = 1;
double dt = dl / (sqrt(2.) * c);
//2D mesh variables
double tempV = 0, E0 = 0, V = 0;
double** V1 = declare_array2D(NX, NY);
double** V2 = declare_array2D(NX, NY);
double** V3 = declare_array2D(NX, NY);
double** V4 = declare_array2D(NX, NY);
double Z = eta0 / sqrt(2.);
//boundary coefficients
double rXmin = -1;
double rXmax = -1;
double rYmin = -1;
double rYmax = -1;
//input / output
double width = 20 * dt * sqrt(2.);
double delay = 100 * dt * sqrt(2.);
int Ein[] = { 10,10 };
int Eout[] = { 15,15 };
ofstream output("CPU.csv");
for (int n = 0; n < NT; n++) {
//source
E0 = (1 / sqrt(2.)) * exp(-(n * dt - delay) * (n * dt - delay) / (width * width));
V1[Ein[0]][Ein[1]] = V1[Ein[0]][Ein[1]] + E0;
V2[Ein[0]][Ein[1]] = V2[Ein[0]][Ein[1]] - E0;
V3[Ein[0]][Ein[1]] = V3[Ein[0]][Ein[1]] - E0;
V4[Ein[0]][Ein[1]] = V4[Ein[0]][Ein[1]] + E0;
//*/
// original scatter
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double I = (2 * V1[x][y] + 2 * V4[x][y] - 2 * V2[x][y] - 2 * V3[x][y]) / (4 * Z);
V = 2 * V1[x][y] - I * Z; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + I * Z; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + I * Z; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - I * Z; //port4
V4[x][y] = V - V4[x][y];
}
}
/*/
// scatter without Z
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double IZ = ((V1[x][y] + V4[x][y] - V2[x][y] - V3[x][y]) / 2);
V = 2 * V1[x][y] - IZ; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + IZ; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + IZ; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - IZ; //port4
V4[x][y] = V - V4[x][y];
}
}
//*/
//connect
for (int x = 1; x < NX; x++) {
for (int y = 0; y < NY; y++) {
tempV = V2[x][y];
V2[x][y] = V4[x - 1][y];
V4[x - 1][y] = tempV;
}
}
for (int x = 0; x < NX; x++) {
for (int y = 1; y < NY; y++) {
tempV = V1[x][y];
V1[x][y] = V3[x][y - 1];
V3[x][y - 1] = tempV;
}
}
//boundary
for (int x = 0; x < NX; x++) {
V3[x][NY - 1] = rYmax * V3[x][NY - 1];
V1[x][0] = rYmin * V1[x][0];
}
for (int y = 0; y < NY; y++) {
V4[NX - 1][y] = rXmax * V4[NX - 1][y];
V2[0][y] = rXmin * V2[0][y];
}
output << n * dt << "," << V2[Eout[0]][Eout[1]] + V4[Eout[0]][Eout[1]] << endl;
if (n % 100 == 0)
cout << n << endl;
}
output.close();
cout << "Done";
std::cout << ((std::clock() - start) / (double)CLOCKS_PER_SEC) << '\n';
cin.get();
}
double** declare_array2D(int NX, int NY) {
double** V = new double* [NX];
for (int x = 0; x < NX; x++) {
V[x] = new double[NY];
}
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
V[x][y] = 0;
}
}
return V;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdlib.h>
#include<stdio.h>
#include<iostream>
#include<fstream>
#include <ctime>
#define M_PI 3.14276
#define c 299792458
#define mu0 M_PI*4e-7
#define eta0 c*mu0
double** declare_array2D(int, int);
using namespace std;
int main() {
std::clock_t start = std::clock();
int NX = 900;
int NY = 900;
int NT = 1000;
double dl = 1;
double dt = dl / (sqrt(2.) * c);
//2D mesh variables
double tempV = 0, E0 = 0, V = 0;
double** V1 = declare_array2D(NX, NY);
double** V2 = declare_array2D(NX, NY);
double** V3 = declare_array2D(NX, NY);
double** V4 = declare_array2D(NX, NY);
double Z = eta0 / sqrt(2.);
//boundary coefficients
double rXmin = -1;
double rXmax = -1;
double rYmin = -1;
double rYmax = -1;
//input / output
double width = 20 * dt * sqrt(2.);
double delay = 100 * dt * sqrt(2.);
int Ein[] = { 10,10 };
int Eout[] = { 15,15 };
ofstream output("CPU.csv");
for (int n = 0; n < NT; n++) {
//source
E0 = (1 / sqrt(2.)) * exp(-(n * dt - delay) * (n * dt - delay) / (width * width));
V1[Ein[0]][Ein[1]] = V1[Ein[0]][Ein[1]] + E0;
V2[Ein[0]][Ein[1]] = V2[Ein[0]][Ein[1]] - E0;
V3[Ein[0]][Ein[1]] = V3[Ein[0]][Ein[1]] - E0;
V4[Ein[0]][Ein[1]] = V4[Ein[0]][Ein[1]] + E0;
//*/
// original scatter
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double I = (2 * V1[x][y] + 2 * V4[x][y] - 2 * V2[x][y] - 2 * V3[x][y]) / (4 * Z);
V = 2 * V1[x][y] - I * Z; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + I * Z; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + I * Z; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - I * Z; //port4
V4[x][y] = V - V4[x][y];
}
}
/*/
// scatter without Z
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
double IZ = ((V1[x][y] + V4[x][y] - V2[x][y] - V3[x][y]) / 2);
V = 2 * V1[x][y] - IZ; //port1
V1[x][y] = V - V1[x][y];
V = 2 * V2[x][y] + IZ; //port2
V2[x][y] = V - V2[x][y];
V = 2 * V3[x][y] + IZ; //port3
V3[x][y] = V - V3[x][y];
V = 2 * V4[x][y] - IZ; //port4
V4[x][y] = V - V4[x][y];
}
}
//*/
//connect
for (int x = 1; x < NX; x++) {
for (int y = 0; y < NY; y++) {
tempV = V2[x][y];
V2[x][y] = V4[x - 1][y];
V4[x - 1][y] = tempV;
}
}
for (int x = 0; x < NX; x++) {
for (int y = 1; y < NY; y++) {
tempV = V1[x][y];
V1[x][y] = V3[x][y - 1];
V3[x][y - 1] = tempV;
}
}
//boundary
for (int x = 0; x < NX; x++) {
V3[x][NY - 1] = rYmax * V3[x][NY - 1];
V1[x][0] = rYmin * V1[x][0];
}
for (int y = 0; y < NY; y++) {
V4[NX - 1][y] = rXmax * V4[NX - 1][y];
V2[0][y] = rXmin * V2[0][y];
}
output << n * dt << "," << V2[Eout[0]][Eout[1]] + V4[Eout[0]][Eout[1]] << endl;
if (n % 100 == 0)
cout << n << endl;
}
output.close();
cout << "Done";
std::cout << ((std::clock() - start) / (double)CLOCKS_PER_SEC) << '\n';
cin.get();
}
double** declare_array2D(int NX, int NY) {
double** V = new double* [NX];
for (int x = 0; x < NX; x++) {
V[x] = new double[NY];
}
for (int x = 0; x < NX; x++) {
for (int y = 0; y < NY; y++) {
V[x][y] = 0;
}
}
return V;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e2442bc5958bbae # double 2.3586543367496838E-9
.LCPI0_1:
.quad 0xbe96629667b5ab33 # double -3.3356409519815204E-7
.LCPI0_2:
.quad 0xbcf40b31553d5e5a # double -4.4506002242144737E-15
.LCPI0_3:
.quad 0x3fe6a09e667f3bcc # double 0.70710678118654746
.LCPI0_4:
.quad 0x4090a7ccfa56d84f # double 1065.9501737184071
.LCPI0_5:
.quad 0x4070a7ccfa56d84f # double 266.48754342960177
.LCPI0_7:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_6:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 640
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, (%r14,%rbx,8)
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_1
# %bb.2: # %.preheader.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_3: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq (%r14,%rbx,8), %rdi
movl $7200, %edx # imm = 0x1C20
xorl %esi, %esi
callq memset@PLT
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_3
# %bb.4: # %_Z15declare_array2Dii.exit
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, (%r13,%rbx,8)
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_5
# %bb.6: # %.preheader.i210.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_7: # %.preheader.i210
# =>This Inner Loop Header: Depth=1
movq (%r13,%rbx,8), %rdi
movl $7200, %edx # imm = 0x1C20
xorl %esi, %esi
callq memset@PLT
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_7
# %bb.8: # %_Z15declare_array2Dii.exit214
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, (%r12,%rbx,8)
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_9
# %bb.10: # %.preheader.i219.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_11: # %.preheader.i219
# =>This Inner Loop Header: Depth=1
movq (%r12,%rbx,8), %rdi
movl $7200, %edx # imm = 0x1C20
xorl %esi, %esi
callq memset@PLT
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_11
# %bb.12: # %_Z15declare_array2Dii.exit223
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_13: # =>This Inner Loop Header: Depth=1
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, (%r15,%rbx,8)
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_13
# %bb.14: # %.preheader.i228.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_15: # %.preheader.i228
# =>This Inner Loop Header: Depth=1
movq (%r15,%rbx,8), %rdi
movl $7200, %edx # imm = 0x1C20
xorl %esi, %esi
callq memset@PLT
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_15
# %bb.16: # %_Z15declare_array2Dii.exit232
leaq 72(%rsp), %rdi
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq 80(%r14), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movq (%r13), %rbp
movq %r15, %rcx
movq %r13, %r15
movq 80(%r13), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movq 80(%r12), %rax
movq %rax, 48(%rsp) # 8-byte Spill
movq 80(%rcx), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movq %rcx, %r13
movq %rcx, %rax
movq 7192(%rcx), %rbx
xorl %eax, %eax
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_61: # %_ZNSolsEPFRSoS_E.exit240
# in Loop: Header=BB0_17 Depth=1
movq 24(%rsp), %rax # 8-byte Reload
incl %eax
cmpl $1000, %eax # imm = 0x3E8
je .LBB0_38
.LBB0_17: # =>This Loop Header: Depth=1
# Child Loop BB0_18 Depth 2
# Child Loop BB0_19 Depth 3
# Child Loop BB0_22 Depth 2
# Child Loop BB0_23 Depth 3
# Child Loop BB0_26 Depth 2
# Child Loop BB0_27 Depth 3
# Child Loop BB0_30 Depth 2
# Child Loop BB0_32 Depth 2
movq %rax, 24(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
addsd .LCPI0_1(%rip), %xmm0
mulsd %xmm0, %xmm0
divsd .LCPI0_2(%rip), %xmm0
callq exp
mulsd .LCPI0_3(%rip), %xmm0
movq 64(%rsp), %rax # 8-byte Reload
movsd 80(%rax), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 56(%rsp), %rax # 8-byte Reload
movsd 80(%rax), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 48(%rsp), %rax # 8-byte Reload
movsd 80(%rax), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 40(%rsp), %rax # 8-byte Reload
addsd 80(%rax), %xmm0
movsd %xmm0, 80(%rax)
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_18: # %.preheader265
# Parent Loop BB0_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_19 Depth 3
movq (%r14,%rax,8), %rcx
movq (%r13,%rax,8), %rdx
movq (%r15,%rax,8), %rsi
movq (%r12,%rax,8), %rdi
xorl %r8d, %r8d
movsd .LCPI0_4(%rip), %xmm4 # xmm4 = mem[0],zero
movsd .LCPI0_5(%rip), %xmm5 # xmm5 = mem[0],zero
.p2align 4, 0x90
.LBB0_19: # Parent Loop BB0_17 Depth=1
# Parent Loop BB0_18 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rcx,%r8,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
addsd %xmm1, %xmm2
movsd (%rdx,%r8,8), %xmm0 # xmm0 = mem[0],zero
addsd %xmm0, %xmm0
addsd %xmm2, %xmm0
movsd (%rsi,%r8,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm3, %xmm3
subsd %xmm3, %xmm0
movsd (%rdi,%r8,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm3, %xmm3
subsd %xmm3, %xmm0
divsd %xmm4, %xmm0
mulsd %xmm5, %xmm0
subsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rcx,%r8,8)
movsd (%rsi,%r8,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
addsd %xmm1, %xmm2
addsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rsi,%r8,8)
movsd (%rdi,%r8,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
addsd %xmm1, %xmm2
addsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rdi,%r8,8)
movsd (%rdx,%r8,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
addsd %xmm1, %xmm2
subsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rdx,%r8,8)
incq %r8
cmpq $900, %r8 # imm = 0x384
jne .LBB0_19
# %bb.20: # in Loop: Header=BB0_18 Depth=2
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_18
# %bb.21: # %.preheader264.preheader
# in Loop: Header=BB0_17 Depth=1
movl $1, %eax
.p2align 4, 0x90
.LBB0_22: # %.preheader264
# Parent Loop BB0_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_23 Depth 3
movq (%r15,%rax,8), %rcx
movq -8(%r13,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_23: # Parent Loop BB0_17 Depth=1
# Parent Loop BB0_22 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rcx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
movsd (%rdx,%rsi,8), %xmm1 # xmm1 = mem[0],zero
movsd %xmm1, (%rcx,%rsi,8)
movsd %xmm0, (%rdx,%rsi,8)
incq %rsi
cmpq $900, %rsi # imm = 0x384
jne .LBB0_23
# %bb.24: # in Loop: Header=BB0_22 Depth=2
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_22
# %bb.25: # %.preheader.preheader
# in Loop: Header=BB0_17 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_26: # %.preheader
# Parent Loop BB0_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_27 Depth 3
movq (%r14,%rax,8), %rcx
movq (%r12,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_27: # Parent Loop BB0_17 Depth=1
# Parent Loop BB0_26 Depth=2
# => This Inner Loop Header: Depth=3
movsd 8(%rcx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
movsd (%rdx,%rsi,8), %xmm1 # xmm1 = mem[0],zero
movsd %xmm1, 8(%rcx,%rsi,8)
movsd %xmm0, (%rdx,%rsi,8)
incq %rsi
cmpq $899, %rsi # imm = 0x383
jne .LBB0_27
# %bb.28: # in Loop: Header=BB0_26 Depth=2
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_26
# %bb.29: # %.preheader267.preheader
# in Loop: Header=BB0_17 Depth=1
xorl %eax, %eax
movapd .LCPI0_6(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0]
.p2align 4, 0x90
.LBB0_30: # %.preheader267
# Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12,%rax,8), %rcx
movsd 7192(%rcx), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm0
movlpd %xmm0, 7192(%rcx)
movq (%r14,%rax,8), %rcx
movsd (%rcx), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm0
movlpd %xmm0, (%rcx)
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_30
# %bb.31: # %.preheader266.preheader
# in Loop: Header=BB0_17 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_32: # %.preheader266
# Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm0
movlpd %xmm0, (%rbx,%rax,8)
movsd (%rbp,%rax,8), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm0
movlpd %xmm0, (%rbp,%rax,8)
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_32
# %bb.33: # in Loop: Header=BB0_17 Depth=1
.Ltmp0:
leaq 72(%rsp), %rdi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp1:
# %bb.34: # %_ZNSolsEd.exit
# in Loop: Header=BB0_17 Depth=1
.Ltmp2:
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, 8(%rsp) # 8-byte Spill
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rdi # 8-byte Reload
.Ltmp3:
# %bb.35: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB0_17 Depth=1
movq 120(%r15), %rax
movsd 120(%rax), %xmm0 # xmm0 = mem[0],zero
movq 120(%r13), %rax
addsd 120(%rax), %xmm0
.Ltmp4:
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, 8(%rsp) # 8-byte Spill
.Ltmp5:
# %bb.36: # %_ZNSolsEd.exit237
# in Loop: Header=BB0_17 Depth=1
movq 8(%rsp), %rcx # 8-byte Reload
movq (%rcx), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %rdi
testq %rdi, %rdi
je .LBB0_37
# %bb.46: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_17 Depth=1
cmpb $0, 56(%rdi)
je .LBB0_48
# %bb.47: # in Loop: Header=BB0_17 Depth=1
movzbl 67(%rdi), %eax
jmp .LBB0_50
.p2align 4, 0x90
.LBB0_48: # in Loop: Header=BB0_17 Depth=1
.Ltmp6:
movq %rdi, 16(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp7:
# %bb.49: # %.noexc249
# in Loop: Header=BB0_17 Depth=1
movq 16(%rsp), %rdi # 8-byte Reload
movq (%rdi), %rax
.Ltmp8:
movl $10, %esi
callq *48(%rax)
.Ltmp9:
.LBB0_50: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB0_17 Depth=1
.Ltmp10:
movsbl %al, %esi
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZNSo3putEc
.Ltmp11:
# %bb.51: # %.noexc251
# in Loop: Header=BB0_17 Depth=1
.Ltmp12:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp13:
# %bb.52: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB0_17 Depth=1
imull $-1030792151, 24(%rsp), %eax # 4-byte Folded Reload
# imm = 0xC28F5C29
rorl $2, %eax
cmpl $42949672, %eax # imm = 0x28F5C28
ja .LBB0_61
# %bb.53: # in Loop: Header=BB0_17 Depth=1
.Ltmp14:
movl $_ZSt4cout, %edi
movq 24(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, 8(%rsp) # 8-byte Spill
.Ltmp15:
# %bb.54: # in Loop: Header=BB0_17 Depth=1
movq 8(%rsp), %rcx # 8-byte Reload
movq (%rcx), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %rdi
testq %rdi, %rdi
je .LBB0_37
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i254
# in Loop: Header=BB0_17 Depth=1
cmpb $0, 56(%rdi)
je .LBB0_57
# %bb.56: # in Loop: Header=BB0_17 Depth=1
movzbl 67(%rdi), %eax
jmp .LBB0_59
.LBB0_57: # in Loop: Header=BB0_17 Depth=1
.Ltmp16:
movq %rdi, 16(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp17:
# %bb.58: # %.noexc259
# in Loop: Header=BB0_17 Depth=1
movq 16(%rsp), %rdi # 8-byte Reload
movq (%rdi), %rax
.Ltmp18:
movl $10, %esi
callq *48(%rax)
.Ltmp19:
.LBB0_59: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i256
# in Loop: Header=BB0_17 Depth=1
.Ltmp20:
movsbl %al, %esi
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZNSo3putEc
.Ltmp21:
# %bb.60: # %.noexc261
# in Loop: Header=BB0_17 Depth=1
.Ltmp22:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp23:
jmp .LBB0_61
.LBB0_38:
leaq 80(%rsp), %rdi
.Ltmp25:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp26:
# %bb.39: # %.noexc
testq %rax, %rax
jne .LBB0_41
# %bb.40:
movq 72(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $72, %rdi
movl 104(%rsp,%rax), %esi
orl $4, %esi
.Ltmp27:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp28:
.LBB0_41: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp29:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp30:
# %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit242
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_7(%rip), %xmm0
.Ltmp31:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp32:
# %bb.43: # %_ZNSolsEd.exit244
movb $10, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_64
# %bb.44:
.Ltmp33:
leaq 7(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp34:
jmp .LBB0_65
.LBB0_64:
.Ltmp35:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp36:
.LBB0_65: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
.Ltmp37:
movl $_ZSt3cin, %edi
callq _ZNSi3getEv
.Ltmp38:
# %bb.66:
leaq 72(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_37: # %.invoke
.cfi_def_cfa_offset 640
.Ltmp40:
callq _ZSt16__throw_bad_castv
.Ltmp41:
# %bb.45: # %.cont
.LBB0_67:
.Ltmp39:
jmp .LBB0_68
.LBB0_63: # %.loopexit.split-lp
.Ltmp42:
jmp .LBB0_68
.LBB0_62: # %.loopexit
.Ltmp24:
.LBB0_68:
movq %rax, %rbx
leaq 72(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp23-.Ltmp0 # Call between .Ltmp0 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp38-.Ltmp25 # Call between .Ltmp25 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp41 # Call between .Ltmp41 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z15declare_array2Dii # -- Begin function _Z15declare_array2Dii
.p2align 4, 0x90
.type _Z15declare_array2Dii,@function
_Z15declare_array2Dii: # @_Z15declare_array2Dii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,8), %rdi
testl %r15d, %r15d
movq $-1, %r13
cmovsq %r13, %rdi
callq _Znam
movq %rax, %r14
movl %ebp, %r12d
testl %r15d, %r15d
jle .LBB1_3
# %bb.1: # %.lr.ph
movslq %ebx, %rax
leaq (,%rax,8), %r15
testl %eax, %eax
cmovsq %r13, %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq _Znam
movq %rax, (%r14,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB1_2
.LBB1_3: # %.preheader19
testl %ebp, %ebp
jle .LBB1_8
# %bb.4: # %.preheader.lr.ph
movl %ebx, %r15d
shlq $3, %r15
xorl %r13d, %r13d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %r13
cmpq %r13, %r12
je .LBB1_8
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
testl %ebx, %ebx
jle .LBB1_7
# %bb.6: # %.lr.ph22
# in Loop: Header=BB1_5 Depth=1
movq (%r14,%r13,8), %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
jmp .LBB1_7
.LBB1_8: # %._crit_edge24
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15declare_array2Dii, .Lfunc_end1-_Z15declare_array2Dii
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU.csv"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ","
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Done"
.size .L.str.2, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000edeea_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3804:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3804:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15declare_array2Dii
.type _Z15declare_array2Dii, @function
_Z15declare_array2Dii:
.LFB3801:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movslq %edi, %rbp
movq %rbp, %rax
shrq $60, %rax
jne .L4
movl %edi, %ebx
movl %esi, %r13d
salq $3, %rbp
movq %rbp, %rdi
call _Znam@PLT
movq %rax, %r14
testl %ebx, %ebx
jle .L3
movslq %r13d, %r12
movq %r12, %rax
shrq $60, %rax
jne .L18
salq $3, %r12
movq %r14, %rbx
addq %r14, %rbp
movq %r14, %r15
.L7:
movq %r12, %rdi
call _Znam@PLT
movq %rax, (%r15)
addq $8, %r15
cmpq %rbp, %r15
jne .L7
jmp .L8
.L4:
call __cxa_throw_bad_array_new_length@PLT
.L18:
call __cxa_throw_bad_array_new_length@PLT
.L12:
movq (%rbx), %rax
leaq (%r12,%rax), %rdx
.L11:
movq $0x000000000, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L11
.L13:
addq $8, %rbx
cmpq %rbp, %rbx
je .L3
.L8:
testl %r13d, %r13d
jg .L12
jmp .L13
.L3:
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _Z15declare_array2Dii, .-_Z15declare_array2Dii
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3827:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3827:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "CPU.csv"
.LC9:
.string ","
.LC10:
.string "Done"
.text
.globl main
.type main, @function
main:
.LFB3800:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3800
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $568, %rsp
.cfi_def_cfa_offset 624
movq %fs:40, %rax
movq %rax, 552(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, 24(%rsp)
movl $900, %esi
movl $900, %edi
.LEHB0:
call _Z15declare_array2Dii
movq %rax, %r13
movl $900, %esi
movl $900, %edi
call _Z15declare_array2Dii
movq %rax, %rbp
movl $900, %esi
movl $900, %edi
call _Z15declare_array2Dii
movq %rax, %r12
movl $900, %esi
movl $900, %edi
call _Z15declare_array2Dii
movq %rax, %rbx
leaq 32(%rsp), %rdi
movl $16, %edx
leaq .LC1(%rip), %rsi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE0:
movl $0, 20(%rsp)
jmp .L40
.L55:
movq 8(%rsp), %rdx
addq $8, %r10
addq $8, %rsi
addq $8, %r8
addq $8, %rdi
cmpq %r11, %rsi
je .L24
.L22:
movl $0, %eax
movq %rdx, 8(%rsp)
.L23:
movq %rax, %r15
addq (%r10), %r15
movsd (%r15), %xmm5
movapd %xmm5, %xmm1
addsd %xmm5, %xmm1
movq (%rsi), %rdx
movsd (%rdx,%rax), %xmm0
addsd %xmm0, %xmm0
addsd %xmm1, %xmm0
movq (%r8), %rdx
movsd (%rdx,%rax), %xmm4
addsd %xmm4, %xmm4
subsd %xmm4, %xmm0
movq (%rdi), %rdx
movsd (%rdx,%rax), %xmm4
addsd %xmm4, %xmm4
subsd %xmm4, %xmm0
divsd %xmm3, %xmm0
mulsd %xmm2, %xmm0
subsd %xmm0, %xmm1
subsd %xmm5, %xmm1
movsd %xmm1, (%r15)
movq %rax, %r15
addq (%r8), %r15
movsd (%r15), %xmm4
movapd %xmm4, %xmm1
addsd %xmm4, %xmm1
addsd %xmm0, %xmm1
subsd %xmm4, %xmm1
movsd %xmm1, (%r15)
movq %rax, %r15
addq (%rdi), %r15
movsd (%r15), %xmm4
movapd %xmm4, %xmm1
addsd %xmm4, %xmm1
addsd %xmm0, %xmm1
subsd %xmm4, %xmm1
movsd %xmm1, (%r15)
movq %rax, %r15
addq (%rsi), %r15
movsd (%r15), %xmm4
movapd %xmm4, %xmm1
addsd %xmm4, %xmm1
subsd %xmm0, %xmm1
subsd %xmm4, %xmm1
movsd %xmm1, (%r15)
addq $8, %rax
cmpq $7200, %rax
jne .L23
jmp .L55
.L57:
addq $8, %rdi
addq $8, %rcx
cmpq %r8, %rcx
je .L56
.L26:
movl $0, %eax
.L25:
movq %rax, %rsi
addq (%rdi), %rsi
movsd (%rsi), %xmm0
movq (%rcx), %r10
movsd (%r10,%rax), %xmm1
movsd %xmm1, (%rsi)
movq (%rcx), %rsi
movsd %xmm0, (%rsi,%rax)
addq $8, %rax
cmpq $7200, %rax
jne .L25
jmp .L57
.L56:
leaq 7200(%r12), %rdi
jmp .L27
.L24:
leaq 8(%rbp), %rdi
leaq 7192(%rbx), %r8
jmp .L26
.L58:
addq $8, %r9
addq $8, %rdx
cmpq %rdi, %rdx
je .L44
.L27:
movl $8, %eax
.L28:
movq %rax, %rcx
addq (%r9), %rcx
movsd (%rcx), %xmm0
movq (%rdx), %rsi
movsd -8(%rsi,%rax), %xmm1
movsd %xmm1, (%rcx)
movq (%rdx), %rcx
movsd %xmm0, -8(%rcx,%rax)
addq $8, %rax
cmpq $7200, %rax
jne .L28
jmp .L58
.L44:
movl $0, %eax
.L29:
movq (%r12,%rax), %rdx
movsd 7192(%rdx), %xmm0
xorpd .LC4(%rip), %xmm0
movsd %xmm0, 7192(%rdx)
movq 0(%r13,%rax), %rdx
movsd (%rdx), %xmm0
xorpd .LC4(%rip), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq $7200, %rax
jne .L29
movl $0, %eax
.L30:
movq %rax, %rdx
addq 7192(%rbx), %rdx
movsd (%rdx), %xmm0
xorpd .LC4(%rip), %xmm0
movsd %xmm0, (%rdx)
movq %rax, %rdx
addq 0(%rbp), %rdx
movsd (%rdx), %xmm0
xorpd .LC4(%rip), %xmm0
movsd %xmm0, (%rdx)
addq $8, %rax
cmpq $7200, %rax
jne .L30
leaq 32(%rsp), %rdi
movq %r14, %xmm0
.LEHB1:
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r14
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 120(%rbp), %rdx
movq 120(%rbx), %rax
movsd 120(%rdx), %xmm0
addsd 120(%rax), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .L59
cmpb $0, 56(%r14)
je .L33
movzbl 67(%r14), %eax
.L34:
movsbl %al, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
jmp .L60
.L59:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L61
call _ZSt16__throw_bad_castv@PLT
.L45:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L61:
call __stack_chk_fail@PLT
.L33:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L34
.L60:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl 20(%rsp), %edi
movslq %edi, %rax
imulq $1374389535, %rax, %rax
sarq $37, %rax
movl %edi, %edx
sarl $31, %edx
subl %edx, %eax
imull $100, %eax, %eax
cmpl %eax, %edi
je .L62
.L35:
addl $1, 20(%rsp)
movl 20(%rsp), %eax
cmpl $1000, %eax
je .L63
.L40:
pxor %xmm0, %xmm0
cvtsi2sdl 20(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
movq %xmm0, %r14
movapd %xmm0, %xmm1
subsd .LC3(%rip), %xmm1
movapd %xmm1, %xmm0
xorpd .LC4(%rip), %xmm0
mulsd %xmm1, %xmm0
divsd .LC5(%rip), %xmm0
call exp@PLT
mulsd .LC6(%rip), %xmm0
movq 80(%r13), %rax
movapd %xmm0, %xmm1
addsd 80(%rax), %xmm1
movsd %xmm1, 80(%rax)
movq 80(%rbp), %rax
movsd 80(%rax), %xmm1
subsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 80(%r12), %rax
movsd 80(%rax), %xmm1
subsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 80(%rbx), %rax
addsd 80(%rax), %xmm0
movsd %xmm0, 80(%rax)
movq %r13, %r9
movq %rbx, %rcx
movq %rbp, %r8
movq %r12, %rdx
leaq 7200(%rbx), %r11
movq %r12, %rdi
movq %rbx, %rsi
movq %r13, %r10
movsd .LC7(%rip), %xmm3
movsd .LC8(%rip), %xmm2
jmp .L22
.L62:
movl %edi, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .L64
cmpb $0, 56(%r14)
je .L38
movzbl 67(%r14), %eax
.L39:
movsbl %al, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
jmp .L65
.L64:
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L66
call _ZSt16__throw_bad_castv@PLT
.L66:
call __stack_chk_fail@PLT
.L38:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L39
.L65:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L35
.L63:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq 24(%rsp), %rbx
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC11(%rip), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
leaq _ZSt3cin(%rip), %rdi
call _ZNSi3getEv@PLT
.LEHE1:
leaq 32(%rsp), %rdi
call _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev@PLT
movq 552(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $568, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3800:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3800-.LLSDACSB3800
.LLSDACSB3800:
.uleb128 .LEHB0-.LFB3800
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3800
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB3800
.uleb128 0
.uleb128 .LEHB2-.LFB3800
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE3800:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 1498987438
.long 1042563772
.align 8
.LC3:
.long 1739959091
.long 1050043030
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 0
.long -2147483648
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC5:
.long 1430085210
.long 1022626609
.align 8
.LC6:
.long 1719614412
.long 1072079006
.align 8
.LC7:
.long -94971825
.long 1083221964
.align 8
.LC8:
.long -94971825
.long 1081124812
.align 8
.LC11:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e2442bc5958bbae # double 2.3586543367496838E-9
.LCPI0_1:
.quad 0xbe96629667b5ab33 # double -3.3356409519815204E-7
.LCPI0_2:
.quad 0xbcf40b31553d5e5a # double -4.4506002242144737E-15
.LCPI0_3:
.quad 0x3fe6a09e667f3bcc # double 0.70710678118654746
.LCPI0_4:
.quad 0x4090a7ccfa56d84f # double 1065.9501737184071
.LCPI0_5:
.quad 0x4070a7ccfa56d84f # double 266.48754342960177
.LCPI0_7:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_6:
.quad 0x8000000000000000 # double -0
.quad 0x8000000000000000 # double -0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 640
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
callq clock
movq %rax, 32(%rsp) # 8-byte Spill
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, (%r14,%rbx,8)
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_1
# %bb.2: # %.preheader.i.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_3: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq (%r14,%rbx,8), %rdi
movl $7200, %edx # imm = 0x1C20
xorl %esi, %esi
callq memset@PLT
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_3
# %bb.4: # %_Z15declare_array2Dii.exit
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, %r13
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, (%r13,%rbx,8)
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_5
# %bb.6: # %.preheader.i210.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_7: # %.preheader.i210
# =>This Inner Loop Header: Depth=1
movq (%r13,%rbx,8), %rdi
movl $7200, %edx # imm = 0x1C20
xorl %esi, %esi
callq memset@PLT
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_7
# %bb.8: # %_Z15declare_array2Dii.exit214
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, %r12
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_9: # =>This Inner Loop Header: Depth=1
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, (%r12,%rbx,8)
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_9
# %bb.10: # %.preheader.i219.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_11: # %.preheader.i219
# =>This Inner Loop Header: Depth=1
movq (%r12,%rbx,8), %rdi
movl $7200, %edx # imm = 0x1C20
xorl %esi, %esi
callq memset@PLT
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_11
# %bb.12: # %_Z15declare_array2Dii.exit223
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, %r15
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_13: # =>This Inner Loop Header: Depth=1
movl $7200, %edi # imm = 0x1C20
callq _Znam
movq %rax, (%r15,%rbx,8)
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_13
# %bb.14: # %.preheader.i228.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_15: # %.preheader.i228
# =>This Inner Loop Header: Depth=1
movq (%r15,%rbx,8), %rdi
movl $7200, %edx # imm = 0x1C20
xorl %esi, %esi
callq memset@PLT
incq %rbx
cmpq $900, %rbx # imm = 0x384
jne .LBB0_15
# %bb.16: # %_Z15declare_array2Dii.exit232
leaq 72(%rsp), %rdi
movl $.L.str, %esi
movl $16, %edx
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode
movq 80(%r14), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movq (%r13), %rbp
movq %r15, %rcx
movq %r13, %r15
movq 80(%r13), %rax
movq %rax, 56(%rsp) # 8-byte Spill
movq 80(%r12), %rax
movq %rax, 48(%rsp) # 8-byte Spill
movq 80(%rcx), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movq %rcx, %r13
movq %rcx, %rax
movq 7192(%rcx), %rbx
xorl %eax, %eax
jmp .LBB0_17
.p2align 4, 0x90
.LBB0_61: # %_ZNSolsEPFRSoS_E.exit240
# in Loop: Header=BB0_17 Depth=1
movq 24(%rsp), %rax # 8-byte Reload
incl %eax
cmpl $1000, %eax # imm = 0x3E8
je .LBB0_38
.LBB0_17: # =>This Loop Header: Depth=1
# Child Loop BB0_18 Depth 2
# Child Loop BB0_19 Depth 3
# Child Loop BB0_22 Depth 2
# Child Loop BB0_23 Depth 3
# Child Loop BB0_26 Depth 2
# Child Loop BB0_27 Depth 3
# Child Loop BB0_30 Depth 2
# Child Loop BB0_32 Depth 2
movq %rax, 24(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
addsd .LCPI0_1(%rip), %xmm0
mulsd %xmm0, %xmm0
divsd .LCPI0_2(%rip), %xmm0
callq exp
mulsd .LCPI0_3(%rip), %xmm0
movq 64(%rsp), %rax # 8-byte Reload
movsd 80(%rax), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 56(%rsp), %rax # 8-byte Reload
movsd 80(%rax), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 48(%rsp), %rax # 8-byte Reload
movsd 80(%rax), %xmm1 # xmm1 = mem[0],zero
subsd %xmm0, %xmm1
movsd %xmm1, 80(%rax)
movq 40(%rsp), %rax # 8-byte Reload
addsd 80(%rax), %xmm0
movsd %xmm0, 80(%rax)
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_18: # %.preheader265
# Parent Loop BB0_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_19 Depth 3
movq (%r14,%rax,8), %rcx
movq (%r13,%rax,8), %rdx
movq (%r15,%rax,8), %rsi
movq (%r12,%rax,8), %rdi
xorl %r8d, %r8d
movsd .LCPI0_4(%rip), %xmm4 # xmm4 = mem[0],zero
movsd .LCPI0_5(%rip), %xmm5 # xmm5 = mem[0],zero
.p2align 4, 0x90
.LBB0_19: # Parent Loop BB0_17 Depth=1
# Parent Loop BB0_18 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rcx,%r8,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
addsd %xmm1, %xmm2
movsd (%rdx,%r8,8), %xmm0 # xmm0 = mem[0],zero
addsd %xmm0, %xmm0
addsd %xmm2, %xmm0
movsd (%rsi,%r8,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm3, %xmm3
subsd %xmm3, %xmm0
movsd (%rdi,%r8,8), %xmm3 # xmm3 = mem[0],zero
addsd %xmm3, %xmm3
subsd %xmm3, %xmm0
divsd %xmm4, %xmm0
mulsd %xmm5, %xmm0
subsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rcx,%r8,8)
movsd (%rsi,%r8,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
addsd %xmm1, %xmm2
addsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rsi,%r8,8)
movsd (%rdi,%r8,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
addsd %xmm1, %xmm2
addsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rdi,%r8,8)
movsd (%rdx,%r8,8), %xmm1 # xmm1 = mem[0],zero
movapd %xmm1, %xmm2
addsd %xmm1, %xmm2
subsd %xmm0, %xmm2
subsd %xmm1, %xmm2
movsd %xmm2, (%rdx,%r8,8)
incq %r8
cmpq $900, %r8 # imm = 0x384
jne .LBB0_19
# %bb.20: # in Loop: Header=BB0_18 Depth=2
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_18
# %bb.21: # %.preheader264.preheader
# in Loop: Header=BB0_17 Depth=1
movl $1, %eax
.p2align 4, 0x90
.LBB0_22: # %.preheader264
# Parent Loop BB0_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_23 Depth 3
movq (%r15,%rax,8), %rcx
movq -8(%r13,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_23: # Parent Loop BB0_17 Depth=1
# Parent Loop BB0_22 Depth=2
# => This Inner Loop Header: Depth=3
movsd (%rcx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
movsd (%rdx,%rsi,8), %xmm1 # xmm1 = mem[0],zero
movsd %xmm1, (%rcx,%rsi,8)
movsd %xmm0, (%rdx,%rsi,8)
incq %rsi
cmpq $900, %rsi # imm = 0x384
jne .LBB0_23
# %bb.24: # in Loop: Header=BB0_22 Depth=2
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_22
# %bb.25: # %.preheader.preheader
# in Loop: Header=BB0_17 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_26: # %.preheader
# Parent Loop BB0_17 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_27 Depth 3
movq (%r14,%rax,8), %rcx
movq (%r12,%rax,8), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB0_27: # Parent Loop BB0_17 Depth=1
# Parent Loop BB0_26 Depth=2
# => This Inner Loop Header: Depth=3
movsd 8(%rcx,%rsi,8), %xmm0 # xmm0 = mem[0],zero
movsd (%rdx,%rsi,8), %xmm1 # xmm1 = mem[0],zero
movsd %xmm1, 8(%rcx,%rsi,8)
movsd %xmm0, (%rdx,%rsi,8)
incq %rsi
cmpq $899, %rsi # imm = 0x383
jne .LBB0_27
# %bb.28: # in Loop: Header=BB0_26 Depth=2
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_26
# %bb.29: # %.preheader267.preheader
# in Loop: Header=BB0_17 Depth=1
xorl %eax, %eax
movapd .LCPI0_6(%rip), %xmm1 # xmm1 = [-0.0E+0,-0.0E+0]
.p2align 4, 0x90
.LBB0_30: # %.preheader267
# Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movq (%r12,%rax,8), %rcx
movsd 7192(%rcx), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm0
movlpd %xmm0, 7192(%rcx)
movq (%r14,%rax,8), %rcx
movsd (%rcx), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm0
movlpd %xmm0, (%rcx)
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_30
# %bb.31: # %.preheader266.preheader
# in Loop: Header=BB0_17 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_32: # %.preheader266
# Parent Loop BB0_17 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%rbx,%rax,8), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm0
movlpd %xmm0, (%rbx,%rax,8)
movsd (%rbp,%rax,8), %xmm0 # xmm0 = mem[0],zero
xorpd %xmm1, %xmm0
movlpd %xmm0, (%rbp,%rax,8)
incq %rax
cmpq $900, %rax # imm = 0x384
jne .LBB0_32
# %bb.33: # in Loop: Header=BB0_17 Depth=1
.Ltmp0:
leaq 72(%rsp), %rdi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp1:
# %bb.34: # %_ZNSolsEd.exit
# in Loop: Header=BB0_17 Depth=1
.Ltmp2:
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, 8(%rsp) # 8-byte Spill
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rdi # 8-byte Reload
.Ltmp3:
# %bb.35: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB0_17 Depth=1
movq 120(%r15), %rax
movsd 120(%rax), %xmm0 # xmm0 = mem[0],zero
movq 120(%r13), %rax
addsd 120(%rax), %xmm0
.Ltmp4:
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, 8(%rsp) # 8-byte Spill
.Ltmp5:
# %bb.36: # %_ZNSolsEd.exit237
# in Loop: Header=BB0_17 Depth=1
movq 8(%rsp), %rcx # 8-byte Reload
movq (%rcx), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %rdi
testq %rdi, %rdi
je .LBB0_37
# %bb.46: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_17 Depth=1
cmpb $0, 56(%rdi)
je .LBB0_48
# %bb.47: # in Loop: Header=BB0_17 Depth=1
movzbl 67(%rdi), %eax
jmp .LBB0_50
.p2align 4, 0x90
.LBB0_48: # in Loop: Header=BB0_17 Depth=1
.Ltmp6:
movq %rdi, 16(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp7:
# %bb.49: # %.noexc249
# in Loop: Header=BB0_17 Depth=1
movq 16(%rsp), %rdi # 8-byte Reload
movq (%rdi), %rax
.Ltmp8:
movl $10, %esi
callq *48(%rax)
.Ltmp9:
.LBB0_50: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
# in Loop: Header=BB0_17 Depth=1
.Ltmp10:
movsbl %al, %esi
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZNSo3putEc
.Ltmp11:
# %bb.51: # %.noexc251
# in Loop: Header=BB0_17 Depth=1
.Ltmp12:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp13:
# %bb.52: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB0_17 Depth=1
imull $-1030792151, 24(%rsp), %eax # 4-byte Folded Reload
# imm = 0xC28F5C29
rorl $2, %eax
cmpl $42949672, %eax # imm = 0x28F5C28
ja .LBB0_61
# %bb.53: # in Loop: Header=BB0_17 Depth=1
.Ltmp14:
movl $_ZSt4cout, %edi
movq 24(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movq %rax, 8(%rsp) # 8-byte Spill
.Ltmp15:
# %bb.54: # in Loop: Header=BB0_17 Depth=1
movq 8(%rsp), %rcx # 8-byte Reload
movq (%rcx), %rax
movq -24(%rax), %rax
movq 240(%rcx,%rax), %rdi
testq %rdi, %rdi
je .LBB0_37
# %bb.55: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i254
# in Loop: Header=BB0_17 Depth=1
cmpb $0, 56(%rdi)
je .LBB0_57
# %bb.56: # in Loop: Header=BB0_17 Depth=1
movzbl 67(%rdi), %eax
jmp .LBB0_59
.LBB0_57: # in Loop: Header=BB0_17 Depth=1
.Ltmp16:
movq %rdi, 16(%rsp) # 8-byte Spill
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp17:
# %bb.58: # %.noexc259
# in Loop: Header=BB0_17 Depth=1
movq 16(%rsp), %rdi # 8-byte Reload
movq (%rdi), %rax
.Ltmp18:
movl $10, %esi
callq *48(%rax)
.Ltmp19:
.LBB0_59: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i256
# in Loop: Header=BB0_17 Depth=1
.Ltmp20:
movsbl %al, %esi
movq 8(%rsp), %rdi # 8-byte Reload
callq _ZNSo3putEc
.Ltmp21:
# %bb.60: # %.noexc261
# in Loop: Header=BB0_17 Depth=1
.Ltmp22:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp23:
jmp .LBB0_61
.LBB0_38:
leaq 80(%rsp), %rdi
.Ltmp25:
callq _ZNSt13basic_filebufIcSt11char_traitsIcEE5closeEv
.Ltmp26:
# %bb.39: # %.noexc
testq %rax, %rax
jne .LBB0_41
# %bb.40:
movq 72(%rsp), %rax
movq -24(%rax), %rax
leaq (%rsp,%rax), %rdi
addq $72, %rdi
movl 104(%rsp,%rax), %esi
orl $4, %esi
.Ltmp27:
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.Ltmp28:
.LBB0_41: # %_ZNSt14basic_ofstreamIcSt11char_traitsIcEE5closeEv.exit
.Ltmp29:
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $4, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp30:
# %bb.42: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit242
callq clock
subq 32(%rsp), %rax # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI0_7(%rip), %xmm0
.Ltmp31:
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp32:
# %bb.43: # %_ZNSolsEd.exit244
movb $10, 7(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB0_64
# %bb.44:
.Ltmp33:
leaq 7(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp34:
jmp .LBB0_65
.LBB0_64:
.Ltmp35:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp36:
.LBB0_65: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
.Ltmp37:
movl $_ZSt3cin, %edi
callq _ZNSi3getEv
.Ltmp38:
# %bb.66:
leaq 72(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
xorl %eax, %eax
addq $584, %rsp # imm = 0x248
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_37: # %.invoke
.cfi_def_cfa_offset 640
.Ltmp40:
callq _ZSt16__throw_bad_castv
.Ltmp41:
# %bb.45: # %.cont
.LBB0_67:
.Ltmp39:
jmp .LBB0_68
.LBB0_63: # %.loopexit.split-lp
.Ltmp42:
jmp .LBB0_68
.LBB0_62: # %.loopexit
.Ltmp24:
.LBB0_68:
movq %rax, %rbx
leaq 72(%rsp), %rdi
callq _ZNSt14basic_ofstreamIcSt11char_traitsIcEED1Ev
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp23-.Ltmp0 # Call between .Ltmp0 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp38-.Ltmp25 # Call between .Ltmp25 and .Ltmp38
.uleb128 .Ltmp39-.Lfunc_begin0 # jumps to .Ltmp39
.byte 0 # On action: cleanup
.uleb128 .Ltmp40-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp41-.Ltmp40 # Call between .Ltmp40 and .Ltmp41
.uleb128 .Ltmp42-.Lfunc_begin0 # jumps to .Ltmp42
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Lfunc_end0-.Ltmp41 # Call between .Ltmp41 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.globl _Z15declare_array2Dii # -- Begin function _Z15declare_array2Dii
.p2align 4, 0x90
.type _Z15declare_array2Dii,@function
_Z15declare_array2Dii: # @_Z15declare_array2Dii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebx
movl %edi, %ebp
movslq %edi, %r15
leaq (,%r15,8), %rdi
testl %r15d, %r15d
movq $-1, %r13
cmovsq %r13, %rdi
callq _Znam
movq %rax, %r14
movl %ebp, %r12d
testl %r15d, %r15d
jle .LBB1_3
# %bb.1: # %.lr.ph
movslq %ebx, %rax
leaq (,%rax,8), %r15
testl %eax, %eax
cmovsq %r13, %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
callq _Znam
movq %rax, (%r14,%r13,8)
incq %r13
cmpq %r13, %r12
jne .LBB1_2
.LBB1_3: # %.preheader19
testl %ebp, %ebp
jle .LBB1_8
# %bb.4: # %.preheader.lr.ph
movl %ebx, %r15d
shlq $3, %r15
xorl %r13d, %r13d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_5 Depth=1
incq %r13
cmpq %r13, %r12
je .LBB1_8
.LBB1_5: # %.preheader
# =>This Inner Loop Header: Depth=1
testl %ebx, %ebx
jle .LBB1_7
# %bb.6: # %.lr.ph22
# in Loop: Header=BB1_5 Depth=1
movq (%r14,%r13,8), %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
jmp .LBB1_7
.LBB1_8: # %._crit_edge24
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z15declare_array2Dii, .Lfunc_end1-_Z15declare_array2Dii
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CPU.csv"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ","
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Done"
.size .L.str.2, 5
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void call_kALACSearch(int16_t * mCoefsU, int16_t * mCoefsV, int32_t kALACMaxCoefs)
{
int x = blockIdx.x;
int y = threadIdx.x;
int index = x * 16 * 16 + y * 16;
int32_t k;
int32_t den = 1 << DENSHIFT_DEFAULT;
mCoefsU[index + 0] = (AINIT * den) >> 4;
mCoefsU[index + 1] = (BINIT * den) >> 4;
mCoefsU[index + 2] = (CINIT * den) >> 4;
mCoefsV[index + 0] = (AINIT * den) >> 4;
mCoefsV[index + 1] = (BINIT * den) >> 4;
mCoefsV[index + 2] = (CINIT * den) >> 4;
for (k = 3; k < kALACMaxCoefs; k++)
{
mCoefsU[index + k] = 0;
mCoefsV[index + k] = 0;
}
} | code for sm_80
Function : _Z16call_kALACSearchPsS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff097624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4c0 ; /* 0x000004c0ff027424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0xfc60 ; /* 0x0000fc60ff077424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, 0xffc0 ; /* 0x0000ffc0ff087424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R0, R0, 0x10, R3 ; /* 0x0000001000007824 */
/* 0x001fc800078e0203 */
/*00b0*/ IMAD.SHL.U32 R6, R0, 0x10, RZ ; /* 0x0000001000067824 */
/* 0x000fe200078e00ff */
/*00c0*/ PRMT R0, R2, 0x7610, R0 ; /* 0x0000761002007816 */
/* 0x000fc60000000000 */
/*00d0*/ IMAD.WIDE R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0205 */
/*00e0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe200078e0205 */
/*00f0*/ STG.E.U16 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001e8000c101504 */
/*0100*/ STG.E.U16 [R2.64+0x2], R7 ; /* 0x0000020702007986 */
/* 0x0001e8000c101504 */
/*0110*/ STG.E.U16 [R2.64+0x4], R8 ; /* 0x0000040802007986 */
/* 0x0001e8000c101504 */
/*0120*/ STG.E.U16 [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x0001e8000c101504 */
/*0130*/ STG.E.U16 [R4.64+0x2], R7 ; /* 0x0000020704007986 */
/* 0x0001e8000c101504 */
/*0140*/ STG.E.U16 [R4.64+0x4], R8 ; /* 0x0000040804007986 */
/* 0x0001e2000c101504 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R0, R9, -0x4, RZ ; /* 0xfffffffc09007810 */
/* 0x001fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fc600078e00ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0190*/ IADD3 R0, R9, -0x3, RZ ; /* 0xfffffffd09007810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fe40000011406 */
/*01b0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fce00078ec0ff */
/*01c0*/ @!P0 BRA 0x8c0 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*01d0*/ LEA R4, P0, R6, 0xc, 0x1 ; /* 0x0000000c06047811 */
/* 0x000fe200078008ff */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R8, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000087a10 */
/* 0x000fe40007ffe1ff */
/*0200*/ LEA.HI.X R5, R6, RZ, R9, 0x1, P0 ; /* 0x000000ff06057211 */
/* 0x000fe400000f0c09 */
/*0210*/ ISETP.GT.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe40003f04270 */
/*0220*/ IADD3 R2, P1, R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x040fe40007f3e0ff */
/*0230*/ IADD3 R4, P2, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc40007f5e0ff */
/*0240*/ IADD3.X R3, R5.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005037a10 */
/* 0x040fe40000ffe4ff */
/*0250*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005057a10 */
/* 0x000fca00017fe4ff */
/*0260*/ @!P0 BRA 0x780 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R10, R8, -0x3, RZ ; /* 0xfffffffd080a7810 */
/* 0x000fe40007ffe0ff */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0290*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fda0003f24270 */
/*02a0*/ @!P1 BRA 0x580 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*02b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02c0*/ STG.E.U16 [R2.64+-0x6], RZ ; /* 0xfffffaff02007986 */
/* 0x000fe2000c101504 */
/*02d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R12, P2, R2, 0x20, RZ ; /* 0x00000020020c7810 */
/* 0x000fe20007f5e0ff */
/*02f0*/ STG.E.U16 [R4.64+-0x6], RZ ; /* 0xfffffaff04007986 */
/* 0x000fe2000c101504 */
/*0300*/ ISETP.GT.AND P1, PT, R8, 0xf, PT ; /* 0x0000000f0800780c */
/* 0x000fe40003f24270 */
/*0310*/ IADD3 R10, P3, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fe20007f7e0ff */
/*0320*/ STG.E.U16 [R2.64+-0x4], RZ ; /* 0xfffffcff02007986 */
/* 0x000fe2000c101504 */
/*0330*/ IMAD.X R13, RZ, RZ, R3, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0603 */
/*0340*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc40007ffe0ff */
/*0350*/ STG.E.U16 [R4.64+-0x4], RZ ; /* 0xfffffcff04007986 */
/* 0x000fe2000c101504 */
/*0360*/ IMAD.X R11, RZ, RZ, R5, P3 ; /* 0x000000ffff0b7224 */
/* 0x000fc600018e0605 */
/*0370*/ STG.E.U16 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe8000c101504 */
/*0380*/ STG.E.U16 [R4.64+-0x2], RZ ; /* 0xfffffeff04007986 */
/* 0x000fe8000c101504 */
/*0390*/ STG.E.U16 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101504 */
/*03a0*/ STG.E.U16 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101504 */
/*03b0*/ STG.E.U16 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe8000c101504 */
/*03c0*/ STG.E.U16 [R4.64+0x2], RZ ; /* 0x000002ff04007986 */
/* 0x000fe8000c101504 */
/*03d0*/ STG.E.U16 [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101504 */
/*03e0*/ STG.E.U16 [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x000fe8000c101504 */
/*03f0*/ STG.E.U16 [R2.64+0x6], RZ ; /* 0x000006ff02007986 */
/* 0x000fe8000c101504 */
/*0400*/ STG.E.U16 [R4.64+0x6], RZ ; /* 0x000006ff04007986 */
/* 0x000fe8000c101504 */
/*0410*/ STG.E.U16 [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101504 */
/*0420*/ STG.E.U16 [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x000fe8000c101504 */
/*0430*/ STG.E.U16 [R2.64+0xa], RZ ; /* 0x00000aff02007986 */
/* 0x000fe8000c101504 */
/*0440*/ STG.E.U16 [R4.64+0xa], RZ ; /* 0x00000aff04007986 */
/* 0x000fe8000c101504 */
/*0450*/ STG.E.U16 [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101504 */
/*0460*/ STG.E.U16 [R4.64+0xc], RZ ; /* 0x00000cff04007986 */
/* 0x000fe8000c101504 */
/*0470*/ STG.E.U16 [R2.64+0xe], RZ ; /* 0x00000eff02007986 */
/* 0x000fe8000c101504 */
/*0480*/ STG.E.U16 [R4.64+0xe], RZ ; /* 0x00000eff04007986 */
/* 0x000fe8000c101504 */
/*0490*/ STG.E.U16 [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101504 */
/*04a0*/ STG.E.U16 [R4.64+0x10], RZ ; /* 0x000010ff04007986 */
/* 0x000fe8000c101504 */
/*04b0*/ STG.E.U16 [R2.64+0x12], RZ ; /* 0x000012ff02007986 */
/* 0x000fe8000c101504 */
/*04c0*/ STG.E.U16 [R4.64+0x12], RZ ; /* 0x000012ff04007986 */
/* 0x000fe8000c101504 */
/*04d0*/ STG.E.U16 [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101504 */
/*04e0*/ STG.E.U16 [R4.64+0x14], RZ ; /* 0x000014ff04007986 */
/* 0x000fe8000c101504 */
/*04f0*/ STG.E.U16 [R2.64+0x16], RZ ; /* 0x000016ff02007986 */
/* 0x000fe8000c101504 */
/*0500*/ STG.E.U16 [R4.64+0x16], RZ ; /* 0x000016ff04007986 */
/* 0x000fe8000c101504 */
/*0510*/ STG.E.U16 [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x0001e8000c101504 */
/*0520*/ STG.E.U16 [R4.64+0x18], RZ ; /* 0x000018ff04007986 */
/* 0x0003e2000c101504 */
/*0530*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fc400078e000c */
/*0540*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe400078e000a */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0570*/ @P1 BRA 0x2c0 ; /* 0xfffffd4000001947 */
/* 0x000fea000383ffff */
/*0580*/ IADD3 R10, R8, -0x3, RZ ; /* 0xfffffffd080a7810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*05a0*/ @!P1 BRA 0x760 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*05b0*/ STG.E.U16 [R2.64+-0x6], RZ ; /* 0xfffffaff02007986 */
/* 0x000fe2000c101504 */
/*05c0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05d0*/ IADD3 R10, P2, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fe20007f5e0ff */
/*05e0*/ STG.E.U16 [R4.64+-0x6], RZ ; /* 0xfffffaff04007986 */
/* 0x000fe2000c101504 */
/*05f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0600*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0603 */
/*0610*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*0620*/ STG.E.U16 [R2.64+-0x4], RZ ; /* 0xfffffcff02007986 */
/* 0x000fe2000c101504 */
/*0630*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e0605 */
/*0640*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fc40007ffe0ff */
/*0650*/ STG.E.U16 [R4.64+-0x4], RZ ; /* 0xfffffcff04007986 */
/* 0x000fe8000c101504 */
/*0660*/ STG.E.U16 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe8000c101504 */
/*0670*/ STG.E.U16 [R4.64+-0x2], RZ ; /* 0xfffffeff04007986 */
/* 0x000fe8000c101504 */
/*0680*/ STG.E.U16 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101504 */
/*0690*/ STG.E.U16 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101504 */
/*06a0*/ STG.E.U16 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe8000c101504 */
/*06b0*/ STG.E.U16 [R4.64+0x2], RZ ; /* 0x000002ff04007986 */
/* 0x000fe8000c101504 */
/*06c0*/ STG.E.U16 [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101504 */
/*06d0*/ STG.E.U16 [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x000fe8000c101504 */
/*06e0*/ STG.E.U16 [R2.64+0x6], RZ ; /* 0x000006ff02007986 */
/* 0x000fe8000c101504 */
/*06f0*/ STG.E.U16 [R4.64+0x6], RZ ; /* 0x000006ff04007986 */
/* 0x000fe8000c101504 */
/*0700*/ STG.E.U16 [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x0001e8000c101504 */
/*0710*/ STG.E.U16 [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x0003e2000c101504 */
/*0720*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fc400078e000c */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe400078e000a */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*0760*/ ISETP.NE.OR P0, PT, R8, 0x3, P0 ; /* 0x000000030800780c */
/* 0x000fda0000705670 */
/*0770*/ @!P0 BRA 0x8c0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0790*/ STG.E.U16 [R2.64+-0x6], RZ ; /* 0xfffffaff02007986 */
/* 0x000fe2000c101504 */
/*07a0*/ IADD3 R12, P1, R2, 0x8, RZ ; /* 0x00000008020c7810 */
/* 0x000fe40007f3e0ff */
/*07b0*/ ISETP.NE.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f05270 */
/*07c0*/ STG.E.U16 [R4.64+-0x6], RZ ; /* 0xfffffaff04007986 */
/* 0x000fe2000c101504 */
/*07d0*/ IADD3 R10, P2, R4, 0x8, RZ ; /* 0x00000008040a7810 */
/* 0x000fe20007f5e0ff */
/*07e0*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0603 */
/*07f0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0800*/ STG.E.U16 [R2.64+-0x4], RZ ; /* 0xfffffcff02007986 */
/* 0x000fe4000c101504 */
/*0810*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fc400010e0605 */
/*0820*/ STG.E.U16 [R4.64+-0x4], RZ ; /* 0xfffffcff04007986 */
/* 0x000fe8000c101504 */
/*0830*/ STG.E.U16 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe8000c101504 */
/*0840*/ STG.E.U16 [R4.64+-0x2], RZ ; /* 0xfffffeff04007986 */
/* 0x000fe8000c101504 */
/*0850*/ STG.E.U16 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101504 */
/*0860*/ STG.E.U16 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0003e2000c101504 */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fc400078e000c */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0890*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe400078e000a */
/*08a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*08b0*/ @P0 BRA 0x780 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*08c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R3, P0, R6, R7, RZ ; /* 0x0000000706037210 */
/* 0x000fc80007f1e0ff */
/*08f0*/ LEA.HI.X.SX32 R6, R7, R9, 0x1, P0 ; /* 0x0000000907067211 */
/* 0x000fe200000f0eff */
/*0900*/ IMAD.SHL.U32 R2, R3, 0x2, RZ ; /* 0x0000000203027824 */
/* 0x000fc600078e00ff */
/*0910*/ SHF.L.U64.HI R3, R3, 0x1, R6 ; /* 0x0000000103037819 */
/* 0x000fe40000010206 */
/*0920*/ IADD3 R4, P0, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f1e0ff */
/*0930*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe40007f3e0ff */
/*0940*/ IADD3.X R5, R3.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003057a10 */
/* 0x040fe400007fe4ff */
/*0950*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003037a10 */
/* 0x000fc80000ffe4ff */
/*0960*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0970*/ STG.E.U16 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c101504 */
/*0980*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0990*/ STG.E.U16 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0003e2000c101504 */
/*09a0*/ IADD3 R2, P2, R2, 0x2, RZ ; /* 0x0000000202027810 */
/* 0x001fc40007f5e0ff */
/*09b0*/ IADD3 R4, P1, R4, 0x2, RZ ; /* 0x0000000204047810 */
/* 0x002fc60007f3e0ff */
/*09c0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*09d0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0605 */
/*09e0*/ @P0 BRA 0x960 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void call_kALACSearch(int16_t * mCoefsU, int16_t * mCoefsV, int32_t kALACMaxCoefs)
{
int x = blockIdx.x;
int y = threadIdx.x;
int index = x * 16 * 16 + y * 16;
int32_t k;
int32_t den = 1 << DENSHIFT_DEFAULT;
mCoefsU[index + 0] = (AINIT * den) >> 4;
mCoefsU[index + 1] = (BINIT * den) >> 4;
mCoefsU[index + 2] = (CINIT * den) >> 4;
mCoefsV[index + 0] = (AINIT * den) >> 4;
mCoefsV[index + 1] = (BINIT * den) >> 4;
mCoefsV[index + 2] = (CINIT * den) >> 4;
for (k = 3; k < kALACMaxCoefs; k++)
{
mCoefsU[index + k] = 0;
mCoefsV[index + k] = 0;
}
} | .file "tmpxft_00190137_00000000-6_call_kALACSearch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i
.type _Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i, @function
_Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16call_kALACSearchPsS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i, .-_Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i
.globl _Z16call_kALACSearchPsS_i
.type _Z16call_kALACSearchPsS_i, @function
_Z16call_kALACSearchPsS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16call_kALACSearchPsS_i, .-_Z16call_kALACSearchPsS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16call_kALACSearchPsS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16call_kALACSearchPsS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void call_kALACSearch(int16_t * mCoefsU, int16_t * mCoefsV, int32_t kALACMaxCoefs)
{
int x = blockIdx.x;
int y = threadIdx.x;
int index = x * 16 * 16 + y * 16;
int32_t k;
int32_t den = 1 << DENSHIFT_DEFAULT;
mCoefsU[index + 0] = (AINIT * den) >> 4;
mCoefsU[index + 1] = (BINIT * den) >> 4;
mCoefsU[index + 2] = (CINIT * den) >> 4;
mCoefsV[index + 0] = (AINIT * den) >> 4;
mCoefsV[index + 1] = (BINIT * den) >> 4;
mCoefsV[index + 2] = (CINIT * den) >> 4;
for (k = 3; k < kALACMaxCoefs; k++)
{
mCoefsU[index + k] = 0;
mCoefsV[index + k] = 0;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void call_kALACSearch(int16_t * mCoefsU, int16_t * mCoefsV, int32_t kALACMaxCoefs)
{
int x = blockIdx.x;
int y = threadIdx.x;
int index = x * 16 * 16 + y * 16;
int32_t k;
int32_t den = 1 << DENSHIFT_DEFAULT;
mCoefsU[index + 0] = (AINIT * den) >> 4;
mCoefsU[index + 1] = (BINIT * den) >> 4;
mCoefsU[index + 2] = (CINIT * den) >> 4;
mCoefsV[index + 0] = (AINIT * den) >> 4;
mCoefsV[index + 1] = (BINIT * den) >> 4;
mCoefsV[index + 2] = (CINIT * den) >> 4;
for (k = 3; k < kALACMaxCoefs; k++)
{
mCoefsU[index + k] = 0;
mCoefsV[index + k] = 0;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void call_kALACSearch(int16_t * mCoefsU, int16_t * mCoefsV, int32_t kALACMaxCoefs)
{
int x = blockIdx.x;
int y = threadIdx.x;
int index = x * 16 * 16 + y * 16;
int32_t k;
int32_t den = 1 << DENSHIFT_DEFAULT;
mCoefsU[index + 0] = (AINIT * den) >> 4;
mCoefsU[index + 1] = (BINIT * den) >> 4;
mCoefsU[index + 2] = (CINIT * den) >> 4;
mCoefsV[index + 0] = (AINIT * den) >> 4;
mCoefsV[index + 1] = (BINIT * den) >> 4;
mCoefsV[index + 2] = (CINIT * den) >> 4;
for (k = 3; k < kALACMaxCoefs; k++)
{
mCoefsU[index + k] = 0;
mCoefsV[index + k] = 0;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16call_kALACSearchPsS_i
.globl _Z16call_kALACSearchPsS_i
.p2align 8
.type _Z16call_kALACSearchPsS_i,@function
_Z16call_kALACSearchPsS_i:
v_dual_mov_b32 v13, 0x4c0 :: v_dual_lshlrev_b32 v0, 4, v0
s_lshl_b32 s2, s15, 8
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
v_dual_mov_b32 v14, 0xfffffc60 :: v_dual_add_nc_u32 v1, s2, v0
v_mov_b32_e32 v15, 0xffffffc0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v3, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
v_or_b32_e32 v5, 2, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_cmp_lt_i32 s0, 4
s_clause 0x2
global_store_b16 v[7:8], v13, off
global_store_b16 v[9:10], v14, off
global_store_b16 v[11:12], v15, off
s_clause 0x2
global_store_b16 v[1:2], v13, off
global_store_b16 v[3:4], v14, off
global_store_b16 v[5:6], v15, off
s_cbranch_scc1 .LBB0_3
v_add3_u32 v0, s2, v0, 3
v_mov_b32_e32 v2, 0
s_add_i32 s0, s0, -3
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_cmp_lg_u32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 1, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_store_b16 v[5:6], v2, off
global_store_b16 v[3:4], v2, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16call_kALACSearchPsS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16call_kALACSearchPsS_i, .Lfunc_end0-_Z16call_kALACSearchPsS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16call_kALACSearchPsS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16call_kALACSearchPsS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void call_kALACSearch(int16_t * mCoefsU, int16_t * mCoefsV, int32_t kALACMaxCoefs)
{
int x = blockIdx.x;
int y = threadIdx.x;
int index = x * 16 * 16 + y * 16;
int32_t k;
int32_t den = 1 << DENSHIFT_DEFAULT;
mCoefsU[index + 0] = (AINIT * den) >> 4;
mCoefsU[index + 1] = (BINIT * den) >> 4;
mCoefsU[index + 2] = (CINIT * den) >> 4;
mCoefsV[index + 0] = (AINIT * den) >> 4;
mCoefsV[index + 1] = (BINIT * den) >> 4;
mCoefsV[index + 2] = (CINIT * den) >> 4;
for (k = 3; k < kALACMaxCoefs; k++)
{
mCoefsU[index + k] = 0;
mCoefsV[index + k] = 0;
}
} | .text
.file "call_kALACSearch.hip"
.globl _Z31__device_stub__call_kALACSearchPsS_i # -- Begin function _Z31__device_stub__call_kALACSearchPsS_i
.p2align 4, 0x90
.type _Z31__device_stub__call_kALACSearchPsS_i,@function
_Z31__device_stub__call_kALACSearchPsS_i: # @_Z31__device_stub__call_kALACSearchPsS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16call_kALACSearchPsS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__call_kALACSearchPsS_i, .Lfunc_end0-_Z31__device_stub__call_kALACSearchPsS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16call_kALACSearchPsS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16call_kALACSearchPsS_i,@object # @_Z16call_kALACSearchPsS_i
.section .rodata,"a",@progbits
.globl _Z16call_kALACSearchPsS_i
.p2align 3, 0x0
_Z16call_kALACSearchPsS_i:
.quad _Z31__device_stub__call_kALACSearchPsS_i
.size _Z16call_kALACSearchPsS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16call_kALACSearchPsS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__call_kALACSearchPsS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16call_kALACSearchPsS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16call_kALACSearchPsS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff097624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4c0 ; /* 0x000004c0ff027424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2 ; /* 0x00000002ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ISETP.GE.AND P0, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, 0xfc60 ; /* 0x0000fc60ff077424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, 0xffc0 ; /* 0x0000ffc0ff087424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R0, R0, 0x10, R3 ; /* 0x0000001000007824 */
/* 0x001fc800078e0203 */
/*00b0*/ IMAD.SHL.U32 R6, R0, 0x10, RZ ; /* 0x0000001000067824 */
/* 0x000fe200078e00ff */
/*00c0*/ PRMT R0, R2, 0x7610, R0 ; /* 0x0000761002007816 */
/* 0x000fc60000000000 */
/*00d0*/ IMAD.WIDE R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc800078e0205 */
/*00e0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe200078e0205 */
/*00f0*/ STG.E.U16 [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x0001e8000c101504 */
/*0100*/ STG.E.U16 [R2.64+0x2], R7 ; /* 0x0000020702007986 */
/* 0x0001e8000c101504 */
/*0110*/ STG.E.U16 [R2.64+0x4], R8 ; /* 0x0000040802007986 */
/* 0x0001e8000c101504 */
/*0120*/ STG.E.U16 [R4.64], R0 ; /* 0x0000000004007986 */
/* 0x0001e8000c101504 */
/*0130*/ STG.E.U16 [R4.64+0x2], R7 ; /* 0x0000020704007986 */
/* 0x0001e8000c101504 */
/*0140*/ STG.E.U16 [R4.64+0x4], R8 ; /* 0x0000040804007986 */
/* 0x0001e2000c101504 */
/*0150*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R0, R9, -0x4, RZ ; /* 0xfffffffc09007810 */
/* 0x001fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fc600078e00ff */
/*0180*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe40003f06070 */
/*0190*/ IADD3 R0, R9, -0x3, RZ ; /* 0xfffffffd09007810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ SHF.R.S32.HI R9, RZ, 0x1f, R6 ; /* 0x0000001fff097819 */
/* 0x000fe40000011406 */
/*01b0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fce00078ec0ff */
/*01c0*/ @!P0 BRA 0x8c0 ; /* 0x000006f000008947 */
/* 0x000fea0003800000 */
/*01d0*/ LEA R4, P0, R6, 0xc, 0x1 ; /* 0x0000000c06047811 */
/* 0x000fe200078008ff */
/*01e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fe200078e00ff */
/*01f0*/ IADD3 R8, -R0, c[0x0][0x170], RZ ; /* 0x00005c0000087a10 */
/* 0x000fe40007ffe1ff */
/*0200*/ LEA.HI.X R5, R6, RZ, R9, 0x1, P0 ; /* 0x000000ff06057211 */
/* 0x000fe400000f0c09 */
/*0210*/ ISETP.GT.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe40003f04270 */
/*0220*/ IADD3 R2, P1, R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x040fe40007f3e0ff */
/*0230*/ IADD3 R4, P2, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc40007f5e0ff */
/*0240*/ IADD3.X R3, R5.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005037a10 */
/* 0x040fe40000ffe4ff */
/*0250*/ IADD3.X R5, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005057a10 */
/* 0x000fca00017fe4ff */
/*0260*/ @!P0 BRA 0x780 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R10, R8, -0x3, RZ ; /* 0xfffffffd080a7810 */
/* 0x000fe40007ffe0ff */
/*0280*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0290*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fda0003f24270 */
/*02a0*/ @!P1 BRA 0x580 ; /* 0x000002d000009947 */
/* 0x000fea0003800000 */
/*02b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*02c0*/ STG.E.U16 [R2.64+-0x6], RZ ; /* 0xfffffaff02007986 */
/* 0x000fe2000c101504 */
/*02d0*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe40007ffe0ff */
/*02e0*/ IADD3 R12, P2, R2, 0x20, RZ ; /* 0x00000020020c7810 */
/* 0x000fe20007f5e0ff */
/*02f0*/ STG.E.U16 [R4.64+-0x6], RZ ; /* 0xfffffaff04007986 */
/* 0x000fe2000c101504 */
/*0300*/ ISETP.GT.AND P1, PT, R8, 0xf, PT ; /* 0x0000000f0800780c */
/* 0x000fe40003f24270 */
/*0310*/ IADD3 R10, P3, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fe20007f7e0ff */
/*0320*/ STG.E.U16 [R2.64+-0x4], RZ ; /* 0xfffffcff02007986 */
/* 0x000fe2000c101504 */
/*0330*/ IMAD.X R13, RZ, RZ, R3, P2 ; /* 0x000000ffff0d7224 */
/* 0x000fe200010e0603 */
/*0340*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc40007ffe0ff */
/*0350*/ STG.E.U16 [R4.64+-0x4], RZ ; /* 0xfffffcff04007986 */
/* 0x000fe2000c101504 */
/*0360*/ IMAD.X R11, RZ, RZ, R5, P3 ; /* 0x000000ffff0b7224 */
/* 0x000fc600018e0605 */
/*0370*/ STG.E.U16 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe8000c101504 */
/*0380*/ STG.E.U16 [R4.64+-0x2], RZ ; /* 0xfffffeff04007986 */
/* 0x000fe8000c101504 */
/*0390*/ STG.E.U16 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101504 */
/*03a0*/ STG.E.U16 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101504 */
/*03b0*/ STG.E.U16 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe8000c101504 */
/*03c0*/ STG.E.U16 [R4.64+0x2], RZ ; /* 0x000002ff04007986 */
/* 0x000fe8000c101504 */
/*03d0*/ STG.E.U16 [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101504 */
/*03e0*/ STG.E.U16 [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x000fe8000c101504 */
/*03f0*/ STG.E.U16 [R2.64+0x6], RZ ; /* 0x000006ff02007986 */
/* 0x000fe8000c101504 */
/*0400*/ STG.E.U16 [R4.64+0x6], RZ ; /* 0x000006ff04007986 */
/* 0x000fe8000c101504 */
/*0410*/ STG.E.U16 [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe8000c101504 */
/*0420*/ STG.E.U16 [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x000fe8000c101504 */
/*0430*/ STG.E.U16 [R2.64+0xa], RZ ; /* 0x00000aff02007986 */
/* 0x000fe8000c101504 */
/*0440*/ STG.E.U16 [R4.64+0xa], RZ ; /* 0x00000aff04007986 */
/* 0x000fe8000c101504 */
/*0450*/ STG.E.U16 [R2.64+0xc], RZ ; /* 0x00000cff02007986 */
/* 0x000fe8000c101504 */
/*0460*/ STG.E.U16 [R4.64+0xc], RZ ; /* 0x00000cff04007986 */
/* 0x000fe8000c101504 */
/*0470*/ STG.E.U16 [R2.64+0xe], RZ ; /* 0x00000eff02007986 */
/* 0x000fe8000c101504 */
/*0480*/ STG.E.U16 [R4.64+0xe], RZ ; /* 0x00000eff04007986 */
/* 0x000fe8000c101504 */
/*0490*/ STG.E.U16 [R2.64+0x10], RZ ; /* 0x000010ff02007986 */
/* 0x000fe8000c101504 */
/*04a0*/ STG.E.U16 [R4.64+0x10], RZ ; /* 0x000010ff04007986 */
/* 0x000fe8000c101504 */
/*04b0*/ STG.E.U16 [R2.64+0x12], RZ ; /* 0x000012ff02007986 */
/* 0x000fe8000c101504 */
/*04c0*/ STG.E.U16 [R4.64+0x12], RZ ; /* 0x000012ff04007986 */
/* 0x000fe8000c101504 */
/*04d0*/ STG.E.U16 [R2.64+0x14], RZ ; /* 0x000014ff02007986 */
/* 0x000fe8000c101504 */
/*04e0*/ STG.E.U16 [R4.64+0x14], RZ ; /* 0x000014ff04007986 */
/* 0x000fe8000c101504 */
/*04f0*/ STG.E.U16 [R2.64+0x16], RZ ; /* 0x000016ff02007986 */
/* 0x000fe8000c101504 */
/*0500*/ STG.E.U16 [R4.64+0x16], RZ ; /* 0x000016ff04007986 */
/* 0x000fe8000c101504 */
/*0510*/ STG.E.U16 [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x0001e8000c101504 */
/*0520*/ STG.E.U16 [R4.64+0x18], RZ ; /* 0x000018ff04007986 */
/* 0x0003e2000c101504 */
/*0530*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fc400078e000c */
/*0540*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0550*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe400078e000a */
/*0560*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0570*/ @P1 BRA 0x2c0 ; /* 0xfffffd4000001947 */
/* 0x000fea000383ffff */
/*0580*/ IADD3 R10, R8, -0x3, RZ ; /* 0xfffffffd080a7810 */
/* 0x000fc80007ffe0ff */
/*0590*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*05a0*/ @!P1 BRA 0x760 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*05b0*/ STG.E.U16 [R2.64+-0x6], RZ ; /* 0xfffffaff02007986 */
/* 0x000fe2000c101504 */
/*05c0*/ IADD3 R12, P1, R2, 0x10, RZ ; /* 0x00000010020c7810 */
/* 0x000fe40007f3e0ff */
/*05d0*/ IADD3 R10, P2, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fe20007f5e0ff */
/*05e0*/ STG.E.U16 [R4.64+-0x6], RZ ; /* 0xfffffaff04007986 */
/* 0x000fe2000c101504 */
/*05f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0600*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0603 */
/*0610*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*0620*/ STG.E.U16 [R2.64+-0x4], RZ ; /* 0xfffffcff02007986 */
/* 0x000fe2000c101504 */
/*0630*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe200010e0605 */
/*0640*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fc40007ffe0ff */
/*0650*/ STG.E.U16 [R4.64+-0x4], RZ ; /* 0xfffffcff04007986 */
/* 0x000fe8000c101504 */
/*0660*/ STG.E.U16 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe8000c101504 */
/*0670*/ STG.E.U16 [R4.64+-0x2], RZ ; /* 0xfffffeff04007986 */
/* 0x000fe8000c101504 */
/*0680*/ STG.E.U16 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101504 */
/*0690*/ STG.E.U16 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101504 */
/*06a0*/ STG.E.U16 [R2.64+0x2], RZ ; /* 0x000002ff02007986 */
/* 0x000fe8000c101504 */
/*06b0*/ STG.E.U16 [R4.64+0x2], RZ ; /* 0x000002ff04007986 */
/* 0x000fe8000c101504 */
/*06c0*/ STG.E.U16 [R2.64+0x4], RZ ; /* 0x000004ff02007986 */
/* 0x000fe8000c101504 */
/*06d0*/ STG.E.U16 [R4.64+0x4], RZ ; /* 0x000004ff04007986 */
/* 0x000fe8000c101504 */
/*06e0*/ STG.E.U16 [R2.64+0x6], RZ ; /* 0x000006ff02007986 */
/* 0x000fe8000c101504 */
/*06f0*/ STG.E.U16 [R4.64+0x6], RZ ; /* 0x000006ff04007986 */
/* 0x000fe8000c101504 */
/*0700*/ STG.E.U16 [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x0001e8000c101504 */
/*0710*/ STG.E.U16 [R4.64+0x8], RZ ; /* 0x000008ff04007986 */
/* 0x0003e2000c101504 */
/*0720*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fc400078e000c */
/*0730*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe400078e000a */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000b */
/*0760*/ ISETP.NE.OR P0, PT, R8, 0x3, P0 ; /* 0x000000030800780c */
/* 0x000fda0000705670 */
/*0770*/ @!P0 BRA 0x8c0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0790*/ STG.E.U16 [R2.64+-0x6], RZ ; /* 0xfffffaff02007986 */
/* 0x000fe2000c101504 */
/*07a0*/ IADD3 R12, P1, R2, 0x8, RZ ; /* 0x00000008020c7810 */
/* 0x000fe40007f3e0ff */
/*07b0*/ ISETP.NE.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fe20003f05270 */
/*07c0*/ STG.E.U16 [R4.64+-0x6], RZ ; /* 0xfffffaff04007986 */
/* 0x000fe2000c101504 */
/*07d0*/ IADD3 R10, P2, R4, 0x8, RZ ; /* 0x00000008040a7810 */
/* 0x000fe20007f5e0ff */
/*07e0*/ IMAD.X R13, RZ, RZ, R3, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0603 */
/*07f0*/ IADD3 R7, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fe20007ffe0ff */
/*0800*/ STG.E.U16 [R2.64+-0x4], RZ ; /* 0xfffffcff02007986 */
/* 0x000fe4000c101504 */
/*0810*/ IMAD.X R11, RZ, RZ, R5, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fc400010e0605 */
/*0820*/ STG.E.U16 [R4.64+-0x4], RZ ; /* 0xfffffcff04007986 */
/* 0x000fe8000c101504 */
/*0830*/ STG.E.U16 [R2.64+-0x2], RZ ; /* 0xfffffeff02007986 */
/* 0x000fe8000c101504 */
/*0840*/ STG.E.U16 [R4.64+-0x2], RZ ; /* 0xfffffeff04007986 */
/* 0x000fe8000c101504 */
/*0850*/ STG.E.U16 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e8000c101504 */
/*0860*/ STG.E.U16 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0003e2000c101504 */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fc400078e000c */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*0890*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x002fe400078e000a */
/*08a0*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*08b0*/ @P0 BRA 0x780 ; /* 0xfffffec000000947 */
/* 0x000fea000383ffff */
/*08c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*08d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R3, P0, R6, R7, RZ ; /* 0x0000000706037210 */
/* 0x000fc80007f1e0ff */
/*08f0*/ LEA.HI.X.SX32 R6, R7, R9, 0x1, P0 ; /* 0x0000000907067211 */
/* 0x000fe200000f0eff */
/*0900*/ IMAD.SHL.U32 R2, R3, 0x2, RZ ; /* 0x0000000203027824 */
/* 0x000fc600078e00ff */
/*0910*/ SHF.L.U64.HI R3, R3, 0x1, R6 ; /* 0x0000000103037819 */
/* 0x000fe40000010206 */
/*0920*/ IADD3 R4, P0, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f1e0ff */
/*0930*/ IADD3 R2, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002027a10 */
/* 0x000fe40007f3e0ff */
/*0940*/ IADD3.X R5, R3.reuse, c[0x0][0x16c], RZ, P0, !PT ; /* 0x00005b0003057a10 */
/* 0x040fe400007fe4ff */
/*0950*/ IADD3.X R3, R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003037a10 */
/* 0x000fc80000ffe4ff */
/*0960*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0970*/ STG.E.U16 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c101504 */
/*0980*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0990*/ STG.E.U16 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0003e2000c101504 */
/*09a0*/ IADD3 R2, P2, R2, 0x2, RZ ; /* 0x0000000202027810 */
/* 0x001fc40007f5e0ff */
/*09b0*/ IADD3 R4, P1, R4, 0x2, RZ ; /* 0x0000000204047810 */
/* 0x002fc60007f3e0ff */
/*09c0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*09d0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0605 */
/*09e0*/ @P0 BRA 0x960 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16call_kALACSearchPsS_i
.globl _Z16call_kALACSearchPsS_i
.p2align 8
.type _Z16call_kALACSearchPsS_i,@function
_Z16call_kALACSearchPsS_i:
v_dual_mov_b32 v13, 0x4c0 :: v_dual_lshlrev_b32 v0, 4, v0
s_lshl_b32 s2, s15, 8
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
v_dual_mov_b32 v14, 0xfffffc60 :: v_dual_add_nc_u32 v1, s2, v0
v_mov_b32_e32 v15, 0xffffffc0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_or_b32_e32 v3, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
v_or_b32_e32 v5, 2, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 1, v[3:4]
v_lshlrev_b64 v[5:6], 1, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
s_cmp_lt_i32 s0, 4
s_clause 0x2
global_store_b16 v[7:8], v13, off
global_store_b16 v[9:10], v14, off
global_store_b16 v[11:12], v15, off
s_clause 0x2
global_store_b16 v[1:2], v13, off
global_store_b16 v[3:4], v14, off
global_store_b16 v[5:6], v15, off
s_cbranch_scc1 .LBB0_3
v_add3_u32 v0, s2, v0, 3
v_mov_b32_e32 v2, 0
s_add_i32 s0, s0, -3
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_cmp_lg_u32 s0, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 1, v[0:1]
v_add_nc_u32_e32 v0, 1, v0
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_store_b16 v[5:6], v2, off
global_store_b16 v[3:4], v2, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16call_kALACSearchPsS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16call_kALACSearchPsS_i, .Lfunc_end0-_Z16call_kALACSearchPsS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16call_kALACSearchPsS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16call_kALACSearchPsS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00190137_00000000-6_call_kALACSearch.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i
.type _Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i, @function
_Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16call_kALACSearchPsS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i, .-_Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i
.globl _Z16call_kALACSearchPsS_i
.type _Z16call_kALACSearchPsS_i, @function
_Z16call_kALACSearchPsS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z16call_kALACSearchPsS_iPsS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16call_kALACSearchPsS_i, .-_Z16call_kALACSearchPsS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16call_kALACSearchPsS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16call_kALACSearchPsS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "call_kALACSearch.hip"
.globl _Z31__device_stub__call_kALACSearchPsS_i # -- Begin function _Z31__device_stub__call_kALACSearchPsS_i
.p2align 4, 0x90
.type _Z31__device_stub__call_kALACSearchPsS_i,@function
_Z31__device_stub__call_kALACSearchPsS_i: # @_Z31__device_stub__call_kALACSearchPsS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16call_kALACSearchPsS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z31__device_stub__call_kALACSearchPsS_i, .Lfunc_end0-_Z31__device_stub__call_kALACSearchPsS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16call_kALACSearchPsS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16call_kALACSearchPsS_i,@object # @_Z16call_kALACSearchPsS_i
.section .rodata,"a",@progbits
.globl _Z16call_kALACSearchPsS_i
.p2align 3, 0x0
_Z16call_kALACSearchPsS_i:
.quad _Z31__device_stub__call_kALACSearchPsS_i
.size _Z16call_kALACSearchPsS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16call_kALACSearchPsS_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__call_kALACSearchPsS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16call_kALACSearchPsS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define MATRIX_SIZE 10000
#define RANGE_NUMBERS 10
#define DIM_THREADS 32
__host__ __device__ inline void setAt(int *m, int i, int j, int v) {
*(m + i*MATRIX_SIZE + j) = v;
}
__host__ __device__ inline int getAt(int *m, int i, int j) {
return *(m + i*MATRIX_SIZE + j);
}
/*__global__ void matrix_mult_shared_mem(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
__shared__ int shared_a[MATRIX_SIZE*MATRIX_SIZE];
__shared__ int shared_b[MATRIX_SIZE*MATRIX_SIZE];
for(int aux = 0; aux < MATRIX_SIZE; aux++) {
setAt(shared_a, i, aux, getAt(a, i, aux));
setAt(shared_b, i, aux, getAt(b, i, aux));
}
__syncthreads();
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(shared_a, i, it) * getAt(shared_b, it, j)) % 50;
}
setAt(c, i, j, sum);
}*/
__global__ void matrix_mult(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(a, i, it) * getAt(b, it, j)) % 50;
}
setAt(c, i, j, sum);
}
int main(int argc, char **argv) {
printf("Starting\n");
srand(time(0));
float etime;
struct timespec t_start, t_end;
size_t size = sizeof(int) * MATRIX_SIZE * MATRIX_SIZE;
int * a, * b, * c;
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// fill matrices
for(int i = 0; i < MATRIX_SIZE; i++) {
for(int j = 0; j < MATRIX_SIZE; j++){
setAt(a, i, j, rand() % RANGE_NUMBERS);
setAt(b, i, j, rand() % RANGE_NUMBERS);
}
}
int * d_a, * d_b, * d_c;
// alloc memory in device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
for(int dim_threads = DIM_THREADS; dim_threads >= 1; dim_threads >>= 1) {
clock_gettime(CLOCK_REALTIME, &t_start);
// copy matrices do device memory
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(dim_threads, dim_threads);
dim3 numBlocks(MATRIX_SIZE / threadsPerBlock.x, MATRIX_SIZE / threadsPerBlock.y);
// call function in device
matrix_mult<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c);
// get data from device memory
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t_end);
etime = (t_end.tv_sec + t_end.tv_nsec / 1000000000.) -
(t_start.tv_sec + t_start.tv_nsec / 1000000000.);
printf("\nNum threads per block: %dx%d Time spent: %lf\n", dim_threads,dim_threads, etime);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
printf("CUDA Error: %s\n",cudaGetErrorString(err));
}
}
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z11matrix_multPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0200 */
/*00a0*/ IMAD R7, R7, 0x2710, RZ ; /* 0x0000271007077824 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R0, R2, c[0x0][0x4], R3 ; /* 0x0000010002007a24 */
/* 0x002fc800078e0203 */
/*00c0*/ IMAD.WIDE R2, R0, R4, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0204 */
/*00d0*/ SHF.R.S32.HI R6, RZ, 0x1f, R0 ; /* 0x0000001fff067819 */
/* 0x000fc60000011400 */
/*00e0*/ IMAD.WIDE R4, R7, R4, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fe200078e0204 */
/*00f0*/ IADD3 R10, P0, R2, 0x27100, RZ ; /* 0x00027100020a7810 */
/* 0x000fc80007f1e0ff */
/*0100*/ IADD3 R2, P1, R4, 0x10, RZ ; /* 0x0000001004027810 */
/* 0x000fe20007f3e0ff */
/*0110*/ IMAD.X R11, RZ, RZ, R3, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fc600000e0603 */
/*0120*/ IADD3.X R3, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff037210 */
/* 0x000fc60000ffe4ff */
/*0130*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0150*/ LDG.E R20, [R2.64+-0x10] ; /* 0xfffff00402147981 */
/* 0x0000a8000c1e1900 */
/*0160*/ LDG.E R19, [R4.64+-0x27100] ; /* 0xfd8f000404137981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R21, [R4.64+-0x1d4c0] ; /* 0xfe2b400404157981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R22, [R2.64+-0xc] ; /* 0xfffff40402167981 */
/* 0x0000e8000c1e1900 */
/*0190*/ LDG.E R24, [R4.64+-0x13880] ; /* 0xfec7800404187981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R25, [R2.64+-0x8] ; /* 0xfffff80402197981 */
/* 0x000128000c1e1900 */
/*01b0*/ LDG.E R17, [R4.64+-0x9c40] ; /* 0xff63c00404117981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R18, [R2.64+-0x4] ; /* 0xfffffc0402127981 */
/* 0x000168000c1e1900 */
/*01d0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000168000c1e1900 */
/*01f0*/ LDG.E R13, [R4.64+0x9c40] ; /* 0x009c4004040d7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000168000c1e1900 */
/*0210*/ LDG.E R10, [R4.64+0x13880] ; /* 0x01388004040a7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000168000c1e1900 */
/*0230*/ LDG.E R8, [R4.64+0x1d4c0] ; /* 0x01d4c00404087981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0402097981 */
/* 0x000162000c1e1900 */
/*0250*/ IADD3 R23, R23, 0x8, RZ ; /* 0x0000000817177810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.NE.AND P0, PT, R23, 0x2710, PT ; /* 0x000027101700780c */
/* 0x000fe40003f05270 */
/*0270*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fca0007f5e0ff */
/*0280*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0290*/ IMAD R19, R19, R20, RZ ; /* 0x0000001413137224 */
/* 0x004fe400078e02ff */
/*02a0*/ IMAD R21, R21, R22, RZ ; /* 0x0000001615157224 */
/* 0x008fe400078e02ff */
/*02b0*/ IMAD.HI R22, R19, 0x51eb851f, RZ ; /* 0x51eb851f13167827 */
/* 0x000fc800078e02ff */
/*02c0*/ IMAD.HI R26, R21, 0x51eb851f, RZ ; /* 0x51eb851f151a7827 */
/* 0x000fc800078e02ff */
/*02d0*/ IMAD R20, R24, R25, RZ ; /* 0x0000001918147224 */
/* 0x010fe200078e02ff */
/*02e0*/ SHF.R.U32.HI R25, RZ, 0x1f, R22 ; /* 0x0000001fff197819 */
/* 0x000fe40000011616 */
/*02f0*/ SHF.R.U32.HI R27, RZ, 0x1f, R26 ; /* 0x0000001fff1b7819 */
/* 0x000fe2000001161a */
/*0300*/ IMAD R17, R17, R18, RZ ; /* 0x0000001211117224 */
/* 0x020fe200078e02ff */
/*0310*/ LEA.HI.SX32 R24, R22, R25, 0x1c ; /* 0x0000001916187211 */
/* 0x000fe200078fe2ff */
/*0320*/ IMAD.HI R22, R20, 0x51eb851f, RZ ; /* 0x51eb851f14167827 */
/* 0x000fe200078e02ff */
/*0330*/ LEA.HI.SX32 R26, R26, R27, 0x1c ; /* 0x0000001b1a1a7211 */
/* 0x000fc600078fe2ff */
/*0340*/ IMAD.HI R18, R17, 0x51eb851f, RZ ; /* 0x51eb851f11127827 */
/* 0x000fe200078e02ff */
/*0350*/ SHF.R.U32.HI R25, RZ, 0x1f, R22 ; /* 0x0000001fff197819 */
/* 0x000fc60000011616 */
/*0360*/ IMAD R26, R26, -0x32, R21 ; /* 0xffffffce1a1a7824 */
/* 0x000fe200078e0215 */
/*0370*/ SHF.R.U32.HI R21, RZ, 0x1f, R18 ; /* 0x0000001fff157819 */
/* 0x000fe20000011612 */
/*0380*/ IMAD R15, R16, R15, RZ ; /* 0x0000000f100f7224 */
/* 0x000fe200078e02ff */
/*0390*/ LEA.HI.SX32 R25, R22, R25, 0x1c ; /* 0x0000001916197211 */
/* 0x000fe200078fe2ff */
/*03a0*/ IMAD R19, R24, -0x32, R19 ; /* 0xffffffce18137824 */
/* 0x000fe400078e0213 */
/*03b0*/ IMAD R12, R13, R12, RZ ; /* 0x0000000c0d0c7224 */
/* 0x000fe200078e02ff */
/*03c0*/ LEA.HI.SX32 R18, R18, R21, 0x1c ; /* 0x0000001512127211 */
/* 0x000fe400078fe2ff */
/*03d0*/ IADD3 R14, R26, R19, R14 ; /* 0x000000131a0e7210 */
/* 0x000fe20007ffe00e */
/*03e0*/ IMAD R19, R25, -0x32, R20 ; /* 0xffffffce19137824 */
/* 0x000fc400078e0214 */
/*03f0*/ IMAD R10, R10, R11, RZ ; /* 0x0000000b0a0a7224 */
/* 0x000fe400078e02ff */
/*0400*/ IMAD.HI R11, R15, 0x51eb851f, RZ ; /* 0x51eb851f0f0b7827 */
/* 0x000fc800078e02ff */
/*0410*/ IMAD R8, R8, R9, RZ ; /* 0x0000000908087224 */
/* 0x000fe400078e02ff */
/*0420*/ IMAD.HI R9, R12, 0x51eb851f, RZ ; /* 0x51eb851f0c097827 */
/* 0x000fe200078e02ff */
/*0430*/ SHF.R.U32.HI R16, RZ, 0x1f, R11 ; /* 0x0000001fff107819 */
/* 0x000fc6000001160b */
/*0440*/ IMAD R18, R18, -0x32, R17 ; /* 0xffffffce12127824 */
/* 0x000fe200078e0211 */
/*0450*/ SHF.R.U32.HI R20, RZ, 0x1f, R9 ; /* 0x0000001fff147819 */
/* 0x000fe20000011609 */
/*0460*/ IMAD.HI R13, R10, 0x51eb851f, RZ ; /* 0x51eb851f0a0d7827 */
/* 0x000fc800078e02ff */
/*0470*/ IMAD.HI R17, R8, 0x51eb851f, RZ ; /* 0x51eb851f08117827 */
/* 0x000fe200078e02ff */
/*0480*/ IADD3 R14, R18, R19, R14 ; /* 0x00000013120e7210 */
/* 0x000fe40007ffe00e */
/*0490*/ SHF.R.U32.HI R22, RZ, 0x1f, R13 ; /* 0x0000001fff167819 */
/* 0x000fe4000001160d */
/*04a0*/ LEA.HI.SX32 R16, R11, R16, 0x1c ; /* 0x000000100b107211 */
/* 0x000fe400078fe2ff */
/*04b0*/ LEA.HI.SX32 R9, R9, R20, 0x1c ; /* 0x0000001409097211 */
/* 0x000fe400078fe2ff */
/*04c0*/ SHF.R.U32.HI R18, RZ, 0x1f, R17 ; /* 0x0000001fff127819 */
/* 0x000fe20000011611 */
/*04d0*/ IMAD R15, R16, -0x32, R15 ; /* 0xffffffce100f7824 */
/* 0x000fe200078e020f */
/*04e0*/ LEA.HI.SX32 R13, R13, R22, 0x1c ; /* 0x000000160d0d7211 */
/* 0x000fe200078fe2ff */
/*04f0*/ IMAD R9, R9, -0x32, R12 ; /* 0xffffffce09097824 */
/* 0x000fe200078e020c */
/*0500*/ LEA.HI.SX32 R17, R17, R18, 0x1c ; /* 0x0000001211117211 */
/* 0x000fc600078fe2ff */
/*0510*/ IMAD R13, R13, -0x32, R10 ; /* 0xffffffce0d0d7824 */
/* 0x000fe200078e020a */
/*0520*/ IADD3 R10, P1, R4, 0x4e200, RZ ; /* 0x0004e200040a7810 */
/* 0x000fe20007f3e0ff */
/*0530*/ IMAD R17, R17, -0x32, R8 ; /* 0xffffffce11117824 */
/* 0x000fe200078e0208 */
/*0540*/ IADD3 R14, R9, R15, R14 ; /* 0x0000000f090e7210 */
/* 0x000fe40007ffe00e */
/*0550*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0b7210 */
/* 0x000fe40000ffe4ff */
/*0560*/ IADD3 R14, R17, R13, R14 ; /* 0x0000000d110e7210 */
/* 0x000fe20007ffe00e */
/*0570*/ @P0 BRA 0x130 ; /* 0xfffffbb000000947 */
/* 0x000fea000383ffff */
/*0580*/ IADD3 R0, P0, R0, R7, RZ ; /* 0x0000000700007210 */
/* 0x000fc80007f1e0ff */
/*0590*/ LEA.HI.X.SX32 R7, R7, R6, 0x1, P0 ; /* 0x0000000607077211 */
/* 0x000fe400000f0eff */
/*05a0*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*05b0*/ LEA.HI.X R3, R0, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1407 */
/*05c0*/ STG.E [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x000fe2000c101904 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define MATRIX_SIZE 10000
#define RANGE_NUMBERS 10
#define DIM_THREADS 32
__host__ __device__ inline void setAt(int *m, int i, int j, int v) {
*(m + i*MATRIX_SIZE + j) = v;
}
__host__ __device__ inline int getAt(int *m, int i, int j) {
return *(m + i*MATRIX_SIZE + j);
}
/*__global__ void matrix_mult_shared_mem(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
__shared__ int shared_a[MATRIX_SIZE*MATRIX_SIZE];
__shared__ int shared_b[MATRIX_SIZE*MATRIX_SIZE];
for(int aux = 0; aux < MATRIX_SIZE; aux++) {
setAt(shared_a, i, aux, getAt(a, i, aux));
setAt(shared_b, i, aux, getAt(b, i, aux));
}
__syncthreads();
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(shared_a, i, it) * getAt(shared_b, it, j)) % 50;
}
setAt(c, i, j, sum);
}*/
__global__ void matrix_mult(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(a, i, it) * getAt(b, it, j)) % 50;
}
setAt(c, i, j, sum);
}
int main(int argc, char **argv) {
printf("Starting\n");
srand(time(0));
float etime;
struct timespec t_start, t_end;
size_t size = sizeof(int) * MATRIX_SIZE * MATRIX_SIZE;
int * a, * b, * c;
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// fill matrices
for(int i = 0; i < MATRIX_SIZE; i++) {
for(int j = 0; j < MATRIX_SIZE; j++){
setAt(a, i, j, rand() % RANGE_NUMBERS);
setAt(b, i, j, rand() % RANGE_NUMBERS);
}
}
int * d_a, * d_b, * d_c;
// alloc memory in device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
for(int dim_threads = DIM_THREADS; dim_threads >= 1; dim_threads >>= 1) {
clock_gettime(CLOCK_REALTIME, &t_start);
// copy matrices do device memory
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(dim_threads, dim_threads);
dim3 numBlocks(MATRIX_SIZE / threadsPerBlock.x, MATRIX_SIZE / threadsPerBlock.y);
// call function in device
matrix_mult<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c);
// get data from device memory
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t_end);
etime = (t_end.tv_sec + t_end.tv_nsec / 1000000000.) -
(t_start.tv_sec + t_start.tv_nsec / 1000000000.);
printf("\nNum threads per block: %dx%d Time spent: %lf\n", dim_threads,dim_threads, etime);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
printf("CUDA Error: %s\n",cudaGetErrorString(err));
}
}
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | .file "tmpxft_00121d83_00000000-6_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_
.type _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_, @function
_Z35__device_stub__Z11matrix_multPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11matrix_multPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_, .-_Z35__device_stub__Z11matrix_multPiS_S_PiS_S_
.globl _Z11matrix_multPiS_S_
.type _Z11matrix_multPiS_S_, @function
_Z11matrix_multPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11matrix_multPiS_S_, .-_Z11matrix_multPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Starting\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nNum threads per block: %dx%d Time spent: %lf\n"
.section .rodata.str1.1
.LC3:
.string "CUDA Error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, (%rsp)
movl $400000000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbp, %r12
leaq 400000000(%rbp), %r14
.L12:
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
addq $4, %rbx
cmpq $40000, %rbx
jne .L13
addq $40000, %r12
addq $40000, %r13
cmpq %r14, %r12
jne .L12
leaq 16(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $6, %r12d
movl $32, %ebx
leaq 64(%rsp), %r15
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
jmp .L17
.L23:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_
jmp .L15
.L16:
sarl %ebx
subl $1, %r12d
je .L22
.L17:
movq %r15, %rsi
movl $0, %edi
call clock_gettime@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $10000, %eax
movl $0, %edx
divl %ebx
movl %eax, 52(%rsp)
movl %eax, 56(%rsp)
movl %ebx, 40(%rsp)
movl %ebx, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $400000000, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 80(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
divsd .LC1(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
je .L16
call cudaGetErrorString@PLT
movq %rax, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L22:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11matrix_multPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_multPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define MATRIX_SIZE 10000
#define RANGE_NUMBERS 10
#define DIM_THREADS 32
__host__ __device__ inline void setAt(int *m, int i, int j, int v) {
*(m + i*MATRIX_SIZE + j) = v;
}
__host__ __device__ inline int getAt(int *m, int i, int j) {
return *(m + i*MATRIX_SIZE + j);
}
/*__global__ void matrix_mult_shared_mem(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
__shared__ int shared_a[MATRIX_SIZE*MATRIX_SIZE];
__shared__ int shared_b[MATRIX_SIZE*MATRIX_SIZE];
for(int aux = 0; aux < MATRIX_SIZE; aux++) {
setAt(shared_a, i, aux, getAt(a, i, aux));
setAt(shared_b, i, aux, getAt(b, i, aux));
}
__syncthreads();
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(shared_a, i, it) * getAt(shared_b, it, j)) % 50;
}
setAt(c, i, j, sum);
}*/
__global__ void matrix_mult(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(a, i, it) * getAt(b, it, j)) % 50;
}
setAt(c, i, j, sum);
}
int main(int argc, char **argv) {
printf("Starting\n");
srand(time(0));
float etime;
struct timespec t_start, t_end;
size_t size = sizeof(int) * MATRIX_SIZE * MATRIX_SIZE;
int * a, * b, * c;
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// fill matrices
for(int i = 0; i < MATRIX_SIZE; i++) {
for(int j = 0; j < MATRIX_SIZE; j++){
setAt(a, i, j, rand() % RANGE_NUMBERS);
setAt(b, i, j, rand() % RANGE_NUMBERS);
}
}
int * d_a, * d_b, * d_c;
// alloc memory in device
cudaMalloc((void **) &d_a, size);
cudaMalloc((void **) &d_b, size);
cudaMalloc((void **) &d_c, size);
for(int dim_threads = DIM_THREADS; dim_threads >= 1; dim_threads >>= 1) {
clock_gettime(CLOCK_REALTIME, &t_start);
// copy matrices do device memory
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
dim3 threadsPerBlock(dim_threads, dim_threads);
dim3 numBlocks(MATRIX_SIZE / threadsPerBlock.x, MATRIX_SIZE / threadsPerBlock.y);
// call function in device
matrix_mult<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c);
// get data from device memory
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t_end);
etime = (t_end.tv_sec + t_end.tv_nsec / 1000000000.) -
(t_start.tv_sec + t_start.tv_nsec / 1000000000.);
printf("\nNum threads per block: %dx%d Time spent: %lf\n", dim_threads,dim_threads, etime);
cudaError_t err = cudaGetLastError();
if (err != cudaSuccess) {
printf("CUDA Error: %s\n",cudaGetErrorString(err));
}
}
cudaFree(d_a); cudaFree(d_b); cudaFree(d_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define MATRIX_SIZE 10000
#define RANGE_NUMBERS 10
#define DIM_THREADS 32
__host__ __device__ inline void setAt(int *m, int i, int j, int v) {
*(m + i*MATRIX_SIZE + j) = v;
}
__host__ __device__ inline int getAt(int *m, int i, int j) {
return *(m + i*MATRIX_SIZE + j);
}
/*__global__ void matrix_mult_shared_mem(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
__shared__ int shared_a[MATRIX_SIZE*MATRIX_SIZE];
__shared__ int shared_b[MATRIX_SIZE*MATRIX_SIZE];
for(int aux = 0; aux < MATRIX_SIZE; aux++) {
setAt(shared_a, i, aux, getAt(a, i, aux));
setAt(shared_b, i, aux, getAt(b, i, aux));
}
__syncthreads();
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(shared_a, i, it) * getAt(shared_b, it, j)) % 50;
}
setAt(c, i, j, sum);
}*/
__global__ void matrix_mult(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(a, i, it) * getAt(b, it, j)) % 50;
}
setAt(c, i, j, sum);
}
int main(int argc, char **argv) {
printf("Starting\n");
srand(time(0));
float etime;
struct timespec t_start, t_end;
size_t size = sizeof(int) * MATRIX_SIZE * MATRIX_SIZE;
int * a, * b, * c;
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// fill matrices
for(int i = 0; i < MATRIX_SIZE; i++) {
for(int j = 0; j < MATRIX_SIZE; j++){
setAt(a, i, j, rand() % RANGE_NUMBERS);
setAt(b, i, j, rand() % RANGE_NUMBERS);
}
}
int * d_a, * d_b, * d_c;
// alloc memory in device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
for(int dim_threads = DIM_THREADS; dim_threads >= 1; dim_threads >>= 1) {
clock_gettime(CLOCK_REALTIME, &t_start);
// copy matrices do device memory
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
dim3 threadsPerBlock(dim_threads, dim_threads);
dim3 numBlocks(MATRIX_SIZE / threadsPerBlock.x, MATRIX_SIZE / threadsPerBlock.y);
// call function in device
matrix_mult<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c);
// get data from device memory
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t_end);
etime = (t_end.tv_sec + t_end.tv_nsec / 1000000000.) -
(t_start.tv_sec + t_start.tv_nsec / 1000000000.);
printf("\nNum threads per block: %dx%d Time spent: %lf\n", dim_threads,dim_threads, etime);
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
printf("CUDA Error: %s\n",hipGetErrorString(err));
}
}
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define MATRIX_SIZE 10000
#define RANGE_NUMBERS 10
#define DIM_THREADS 32
__host__ __device__ inline void setAt(int *m, int i, int j, int v) {
*(m + i*MATRIX_SIZE + j) = v;
}
__host__ __device__ inline int getAt(int *m, int i, int j) {
return *(m + i*MATRIX_SIZE + j);
}
/*__global__ void matrix_mult_shared_mem(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
__shared__ int shared_a[MATRIX_SIZE*MATRIX_SIZE];
__shared__ int shared_b[MATRIX_SIZE*MATRIX_SIZE];
for(int aux = 0; aux < MATRIX_SIZE; aux++) {
setAt(shared_a, i, aux, getAt(a, i, aux));
setAt(shared_b, i, aux, getAt(b, i, aux));
}
__syncthreads();
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(shared_a, i, it) * getAt(shared_b, it, j)) % 50;
}
setAt(c, i, j, sum);
}*/
__global__ void matrix_mult(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(a, i, it) * getAt(b, it, j)) % 50;
}
setAt(c, i, j, sum);
}
int main(int argc, char **argv) {
printf("Starting\n");
srand(time(0));
float etime;
struct timespec t_start, t_end;
size_t size = sizeof(int) * MATRIX_SIZE * MATRIX_SIZE;
int * a, * b, * c;
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// fill matrices
for(int i = 0; i < MATRIX_SIZE; i++) {
for(int j = 0; j < MATRIX_SIZE; j++){
setAt(a, i, j, rand() % RANGE_NUMBERS);
setAt(b, i, j, rand() % RANGE_NUMBERS);
}
}
int * d_a, * d_b, * d_c;
// alloc memory in device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
for(int dim_threads = DIM_THREADS; dim_threads >= 1; dim_threads >>= 1) {
clock_gettime(CLOCK_REALTIME, &t_start);
// copy matrices do device memory
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
dim3 threadsPerBlock(dim_threads, dim_threads);
dim3 numBlocks(MATRIX_SIZE / threadsPerBlock.x, MATRIX_SIZE / threadsPerBlock.y);
// call function in device
matrix_mult<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c);
// get data from device memory
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t_end);
etime = (t_end.tv_sec + t_end.tv_nsec / 1000000000.) -
(t_start.tv_sec + t_start.tv_nsec / 1000000000.);
printf("\nNum threads per block: %dx%d Time spent: %lf\n", dim_threads,dim_threads, etime);
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
printf("CUDA Error: %s\n",hipGetErrorString(err));
}
}
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matrix_multPiS_S_
.globl _Z11matrix_multPiS_S_
.p2align 8
.type _Z11matrix_multPiS_S_,@function
_Z11matrix_multPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v2, 0x2710
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_mov_b32_e32 v5, 0
v_add_co_u32 v6, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v8, vcc_lo
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, s2
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
global_load_b32 v10, v[3:4], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 0x9c40
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_cmpk_eq_u32 s2, 0x9c40
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v9, v8, 0x51eb851f
v_lshrrev_b32_e32 v10, 31, v9
v_ashrrev_i32_e32 v9, 4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v9, v10
v_mul_lo_u32 v9, v9, 50
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v8, v9
v_add_nc_u32_e32 v5, v8, v5
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v2, v2, 0x2710
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_multPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matrix_multPiS_S_, .Lfunc_end0-_Z11matrix_multPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_multPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matrix_multPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#define MATRIX_SIZE 10000
#define RANGE_NUMBERS 10
#define DIM_THREADS 32
__host__ __device__ inline void setAt(int *m, int i, int j, int v) {
*(m + i*MATRIX_SIZE + j) = v;
}
__host__ __device__ inline int getAt(int *m, int i, int j) {
return *(m + i*MATRIX_SIZE + j);
}
/*__global__ void matrix_mult_shared_mem(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
__shared__ int shared_a[MATRIX_SIZE*MATRIX_SIZE];
__shared__ int shared_b[MATRIX_SIZE*MATRIX_SIZE];
for(int aux = 0; aux < MATRIX_SIZE; aux++) {
setAt(shared_a, i, aux, getAt(a, i, aux));
setAt(shared_b, i, aux, getAt(b, i, aux));
}
__syncthreads();
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(shared_a, i, it) * getAt(shared_b, it, j)) % 50;
}
setAt(c, i, j, sum);
}*/
__global__ void matrix_mult(int *a, int *b, int *c) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int sum = 0;
for(int it = 0; it < MATRIX_SIZE; it++) {
sum += (getAt(a, i, it) * getAt(b, it, j)) % 50;
}
setAt(c, i, j, sum);
}
int main(int argc, char **argv) {
printf("Starting\n");
srand(time(0));
float etime;
struct timespec t_start, t_end;
size_t size = sizeof(int) * MATRIX_SIZE * MATRIX_SIZE;
int * a, * b, * c;
a = (int *) malloc(size);
b = (int *) malloc(size);
c = (int *) malloc(size);
// fill matrices
for(int i = 0; i < MATRIX_SIZE; i++) {
for(int j = 0; j < MATRIX_SIZE; j++){
setAt(a, i, j, rand() % RANGE_NUMBERS);
setAt(b, i, j, rand() % RANGE_NUMBERS);
}
}
int * d_a, * d_b, * d_c;
// alloc memory in device
hipMalloc((void **) &d_a, size);
hipMalloc((void **) &d_b, size);
hipMalloc((void **) &d_c, size);
for(int dim_threads = DIM_THREADS; dim_threads >= 1; dim_threads >>= 1) {
clock_gettime(CLOCK_REALTIME, &t_start);
// copy matrices do device memory
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
dim3 threadsPerBlock(dim_threads, dim_threads);
dim3 numBlocks(MATRIX_SIZE / threadsPerBlock.x, MATRIX_SIZE / threadsPerBlock.y);
// call function in device
matrix_mult<<<numBlocks,threadsPerBlock>>>(d_a, d_b, d_c);
// get data from device memory
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
hipDeviceSynchronize();
clock_gettime(CLOCK_REALTIME, &t_end);
etime = (t_end.tv_sec + t_end.tv_nsec / 1000000000.) -
(t_start.tv_sec + t_start.tv_nsec / 1000000000.);
printf("\nNum threads per block: %dx%d Time spent: %lf\n", dim_threads,dim_threads, etime);
hipError_t err = hipGetLastError();
if (err != hipSuccess) {
printf("CUDA Error: %s\n",hipGetErrorString(err));
}
}
hipFree(d_a); hipFree(d_b); hipFree(d_c);
return 0;
} | .text
.file "matrix_mult.hip"
.globl _Z26__device_stub__matrix_multPiS_S_ # -- Begin function _Z26__device_stub__matrix_multPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__matrix_multPiS_S_,@function
_Z26__device_stub__matrix_multPiS_S_: # @_Z26__device_stub__matrix_multPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matrix_multPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__matrix_multPiS_S_, .Lfunc_end0-_Z26__device_stub__matrix_multPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r13
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r15
movq %r13, 32(%rsp) # 8-byte Spill
movq %r14, %rbp
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbx,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbp,%rbx,4)
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $40000, %rbp # imm = 0x9C40
addq $40000, %r13 # imm = 0x9C40
cmpq $10000, %r12 # imm = 0x2710
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $32, %ebp
leaq 128(%rsp), %r12
leaq 112(%rsp), %r13
movq 32(%rsp), %rbx # 8-byte Reload
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_5 Depth=1
movl %ebp, %eax
shrl %eax
cmpl $2, %ebp
movl %eax, %ebp
jb .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorl %edi, %edi
movq %r12, %rsi
callq clock_gettime
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
movq %rax, %rcx
shlq $32, %rcx
orq %rax, %rcx
movl $10000, %eax # imm = 0x2710
xorl %edx, %edx
divl %ebp
# kill: def $eax killed $eax def $rax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z11matrix_multPiS_S_, %edi
leaq 144(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
movq 8(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %edi, %edi
movq %r13, %rsi
callq clock_gettime
xorps %xmm0, %xmm0
cvtsi2sdq 112(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 120(%rsp), %xmm1
movsd .LCPI1_0(%rip), %xmm3 # xmm3 = mem[0],zero
divsd %xmm3, %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 128(%rsp), %xmm0
cvtsi2sdq 136(%rsp), %xmm2
divsd %xmm3, %xmm2
addsd %xmm0, %xmm2
subsd %xmm2, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebp, %esi
movl %ebp, %edx
movb $1, %al
callq printf
callq hipGetLastError
testl %eax, %eax
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_5 Depth=1
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
jmp .LBB1_9
.LBB1_10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_multPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11matrix_multPiS_S_,@object # @_Z11matrix_multPiS_S_
.section .rodata,"a",@progbits
.globl _Z11matrix_multPiS_S_
.p2align 3, 0x0
_Z11matrix_multPiS_S_:
.quad _Z26__device_stub__matrix_multPiS_S_
.size _Z11matrix_multPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\nNum threads per block: %dx%d Time spent: %lf\n"
.size .L.str.1, 47
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA Error: %s\n"
.size .L.str.2, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11matrix_multPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Starting"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matrix_multPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matrix_multPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11matrix_multPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ HFMA2.MMA R23, -RZ, RZ, 0, 0 ; /* 0x00000000ff177435 */
/* 0x000fe200000001ff */
/*0040*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0070*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0080*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x001fc800078e0200 */
/*00a0*/ IMAD R7, R7, 0x2710, RZ ; /* 0x0000271007077824 */
/* 0x000fe400078e02ff */
/*00b0*/ IMAD R0, R2, c[0x0][0x4], R3 ; /* 0x0000010002007a24 */
/* 0x002fc800078e0203 */
/*00c0*/ IMAD.WIDE R2, R0, R4, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0204 */
/*00d0*/ SHF.R.S32.HI R6, RZ, 0x1f, R0 ; /* 0x0000001fff067819 */
/* 0x000fc60000011400 */
/*00e0*/ IMAD.WIDE R4, R7, R4, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fe200078e0204 */
/*00f0*/ IADD3 R10, P0, R2, 0x27100, RZ ; /* 0x00027100020a7810 */
/* 0x000fc80007f1e0ff */
/*0100*/ IADD3 R2, P1, R4, 0x10, RZ ; /* 0x0000001004027810 */
/* 0x000fe20007f3e0ff */
/*0110*/ IMAD.X R11, RZ, RZ, R3, P0 ; /* 0x000000ffff0b7224 */
/* 0x000fc600000e0603 */
/*0120*/ IADD3.X R3, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff037210 */
/* 0x000fc60000ffe4ff */
/*0130*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe20000000f00 */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, R11 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000b */
/*0150*/ LDG.E R20, [R2.64+-0x10] ; /* 0xfffff00402147981 */
/* 0x0000a8000c1e1900 */
/*0160*/ LDG.E R19, [R4.64+-0x27100] ; /* 0xfd8f000404137981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R21, [R4.64+-0x1d4c0] ; /* 0xfe2b400404157981 */
/* 0x000ee8000c1e1900 */
/*0180*/ LDG.E R22, [R2.64+-0xc] ; /* 0xfffff40402167981 */
/* 0x0000e8000c1e1900 */
/*0190*/ LDG.E R24, [R4.64+-0x13880] ; /* 0xfec7800404187981 */
/* 0x000f28000c1e1900 */
/*01a0*/ LDG.E R25, [R2.64+-0x8] ; /* 0xfffff80402197981 */
/* 0x000128000c1e1900 */
/*01b0*/ LDG.E R17, [R4.64+-0x9c40] ; /* 0xff63c00404117981 */
/* 0x000f68000c1e1900 */
/*01c0*/ LDG.E R18, [R2.64+-0x4] ; /* 0xfffffc0402127981 */
/* 0x000168000c1e1900 */
/*01d0*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000168000c1e1900 */
/*01f0*/ LDG.E R13, [R4.64+0x9c40] ; /* 0x009c4004040d7981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R12, [R2.64+0x4] ; /* 0x00000404020c7981 */
/* 0x000168000c1e1900 */
/*0210*/ LDG.E R10, [R4.64+0x13880] ; /* 0x01388004040a7981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x000168000c1e1900 */
/*0230*/ LDG.E R8, [R4.64+0x1d4c0] ; /* 0x01d4c00404087981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R9, [R2.64+0xc] ; /* 0x00000c0402097981 */
/* 0x000162000c1e1900 */
/*0250*/ IADD3 R23, R23, 0x8, RZ ; /* 0x0000000817177810 */
/* 0x000fc80007ffe0ff */
/*0260*/ ISETP.NE.AND P0, PT, R23, 0x2710, PT ; /* 0x000027101700780c */
/* 0x000fe40003f05270 */
/*0270*/ IADD3 R2, P2, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x001fca0007f5e0ff */
/*0280*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*0290*/ IMAD R19, R19, R20, RZ ; /* 0x0000001413137224 */
/* 0x004fe400078e02ff */
/*02a0*/ IMAD R21, R21, R22, RZ ; /* 0x0000001615157224 */
/* 0x008fe400078e02ff */
/*02b0*/ IMAD.HI R22, R19, 0x51eb851f, RZ ; /* 0x51eb851f13167827 */
/* 0x000fc800078e02ff */
/*02c0*/ IMAD.HI R26, R21, 0x51eb851f, RZ ; /* 0x51eb851f151a7827 */
/* 0x000fc800078e02ff */
/*02d0*/ IMAD R20, R24, R25, RZ ; /* 0x0000001918147224 */
/* 0x010fe200078e02ff */
/*02e0*/ SHF.R.U32.HI R25, RZ, 0x1f, R22 ; /* 0x0000001fff197819 */
/* 0x000fe40000011616 */
/*02f0*/ SHF.R.U32.HI R27, RZ, 0x1f, R26 ; /* 0x0000001fff1b7819 */
/* 0x000fe2000001161a */
/*0300*/ IMAD R17, R17, R18, RZ ; /* 0x0000001211117224 */
/* 0x020fe200078e02ff */
/*0310*/ LEA.HI.SX32 R24, R22, R25, 0x1c ; /* 0x0000001916187211 */
/* 0x000fe200078fe2ff */
/*0320*/ IMAD.HI R22, R20, 0x51eb851f, RZ ; /* 0x51eb851f14167827 */
/* 0x000fe200078e02ff */
/*0330*/ LEA.HI.SX32 R26, R26, R27, 0x1c ; /* 0x0000001b1a1a7211 */
/* 0x000fc600078fe2ff */
/*0340*/ IMAD.HI R18, R17, 0x51eb851f, RZ ; /* 0x51eb851f11127827 */
/* 0x000fe200078e02ff */
/*0350*/ SHF.R.U32.HI R25, RZ, 0x1f, R22 ; /* 0x0000001fff197819 */
/* 0x000fc60000011616 */
/*0360*/ IMAD R26, R26, -0x32, R21 ; /* 0xffffffce1a1a7824 */
/* 0x000fe200078e0215 */
/*0370*/ SHF.R.U32.HI R21, RZ, 0x1f, R18 ; /* 0x0000001fff157819 */
/* 0x000fe20000011612 */
/*0380*/ IMAD R15, R16, R15, RZ ; /* 0x0000000f100f7224 */
/* 0x000fe200078e02ff */
/*0390*/ LEA.HI.SX32 R25, R22, R25, 0x1c ; /* 0x0000001916197211 */
/* 0x000fe200078fe2ff */
/*03a0*/ IMAD R19, R24, -0x32, R19 ; /* 0xffffffce18137824 */
/* 0x000fe400078e0213 */
/*03b0*/ IMAD R12, R13, R12, RZ ; /* 0x0000000c0d0c7224 */
/* 0x000fe200078e02ff */
/*03c0*/ LEA.HI.SX32 R18, R18, R21, 0x1c ; /* 0x0000001512127211 */
/* 0x000fe400078fe2ff */
/*03d0*/ IADD3 R14, R26, R19, R14 ; /* 0x000000131a0e7210 */
/* 0x000fe20007ffe00e */
/*03e0*/ IMAD R19, R25, -0x32, R20 ; /* 0xffffffce19137824 */
/* 0x000fc400078e0214 */
/*03f0*/ IMAD R10, R10, R11, RZ ; /* 0x0000000b0a0a7224 */
/* 0x000fe400078e02ff */
/*0400*/ IMAD.HI R11, R15, 0x51eb851f, RZ ; /* 0x51eb851f0f0b7827 */
/* 0x000fc800078e02ff */
/*0410*/ IMAD R8, R8, R9, RZ ; /* 0x0000000908087224 */
/* 0x000fe400078e02ff */
/*0420*/ IMAD.HI R9, R12, 0x51eb851f, RZ ; /* 0x51eb851f0c097827 */
/* 0x000fe200078e02ff */
/*0430*/ SHF.R.U32.HI R16, RZ, 0x1f, R11 ; /* 0x0000001fff107819 */
/* 0x000fc6000001160b */
/*0440*/ IMAD R18, R18, -0x32, R17 ; /* 0xffffffce12127824 */
/* 0x000fe200078e0211 */
/*0450*/ SHF.R.U32.HI R20, RZ, 0x1f, R9 ; /* 0x0000001fff147819 */
/* 0x000fe20000011609 */
/*0460*/ IMAD.HI R13, R10, 0x51eb851f, RZ ; /* 0x51eb851f0a0d7827 */
/* 0x000fc800078e02ff */
/*0470*/ IMAD.HI R17, R8, 0x51eb851f, RZ ; /* 0x51eb851f08117827 */
/* 0x000fe200078e02ff */
/*0480*/ IADD3 R14, R18, R19, R14 ; /* 0x00000013120e7210 */
/* 0x000fe40007ffe00e */
/*0490*/ SHF.R.U32.HI R22, RZ, 0x1f, R13 ; /* 0x0000001fff167819 */
/* 0x000fe4000001160d */
/*04a0*/ LEA.HI.SX32 R16, R11, R16, 0x1c ; /* 0x000000100b107211 */
/* 0x000fe400078fe2ff */
/*04b0*/ LEA.HI.SX32 R9, R9, R20, 0x1c ; /* 0x0000001409097211 */
/* 0x000fe400078fe2ff */
/*04c0*/ SHF.R.U32.HI R18, RZ, 0x1f, R17 ; /* 0x0000001fff127819 */
/* 0x000fe20000011611 */
/*04d0*/ IMAD R15, R16, -0x32, R15 ; /* 0xffffffce100f7824 */
/* 0x000fe200078e020f */
/*04e0*/ LEA.HI.SX32 R13, R13, R22, 0x1c ; /* 0x000000160d0d7211 */
/* 0x000fe200078fe2ff */
/*04f0*/ IMAD R9, R9, -0x32, R12 ; /* 0xffffffce09097824 */
/* 0x000fe200078e020c */
/*0500*/ LEA.HI.SX32 R17, R17, R18, 0x1c ; /* 0x0000001211117211 */
/* 0x000fc600078fe2ff */
/*0510*/ IMAD R13, R13, -0x32, R10 ; /* 0xffffffce0d0d7824 */
/* 0x000fe200078e020a */
/*0520*/ IADD3 R10, P1, R4, 0x4e200, RZ ; /* 0x0004e200040a7810 */
/* 0x000fe20007f3e0ff */
/*0530*/ IMAD R17, R17, -0x32, R8 ; /* 0xffffffce11117824 */
/* 0x000fe200078e0208 */
/*0540*/ IADD3 R14, R9, R15, R14 ; /* 0x0000000f090e7210 */
/* 0x000fe40007ffe00e */
/*0550*/ IADD3.X R11, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff0b7210 */
/* 0x000fe40000ffe4ff */
/*0560*/ IADD3 R14, R17, R13, R14 ; /* 0x0000000d110e7210 */
/* 0x000fe20007ffe00e */
/*0570*/ @P0 BRA 0x130 ; /* 0xfffffbb000000947 */
/* 0x000fea000383ffff */
/*0580*/ IADD3 R0, P0, R0, R7, RZ ; /* 0x0000000700007210 */
/* 0x000fc80007f1e0ff */
/*0590*/ LEA.HI.X.SX32 R7, R7, R6, 0x1, P0 ; /* 0x0000000607077211 */
/* 0x000fe400000f0eff */
/*05a0*/ LEA R2, P0, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000027a11 */
/* 0x000fc800078010ff */
/*05b0*/ LEA.HI.X R3, R0, c[0x0][0x174], R7, 0x2, P0 ; /* 0x00005d0000037a11 */
/* 0x000fca00000f1407 */
/*05c0*/ STG.E [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x000fe2000c101904 */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matrix_multPiS_S_
.globl _Z11matrix_multPiS_S_
.p2align 8
.type _Z11matrix_multPiS_S_,@function
_Z11matrix_multPiS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v2, 0x2710
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
v_mov_b32_e32 v5, 0
v_add_co_u32 v6, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v8, vcc_lo
.p2align 6
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, v6, s2
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
global_load_b32 v10, v[3:4], off
global_load_b32 v8, v[8:9], off
v_add_co_u32 v3, vcc_lo, v3, 0x9c40
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_cmpk_eq_u32 s2, 0x9c40
s_waitcnt vmcnt(0)
v_mul_lo_u32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_i32 v9, v8, 0x51eb851f
v_lshrrev_b32_e32 v10, 31, v9
v_ashrrev_i32_e32 v9, 4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v9, v10
v_mul_lo_u32 v9, v9, 50
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v8, v8, v9
v_add_nc_u32_e32 v5, v8, v5
s_cbranch_scc0 .LBB0_1
s_load_b64 s[0:1], s[0:1], 0x10
v_mul_lo_u32 v2, v2, 0x2710
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_store_b32 v[0:1], v5, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matrix_multPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matrix_multPiS_S_, .Lfunc_end0-_Z11matrix_multPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matrix_multPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matrix_multPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00121d83_00000000-6_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_
.type _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_, @function
_Z35__device_stub__Z11matrix_multPiS_S_PiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11matrix_multPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_, .-_Z35__device_stub__Z11matrix_multPiS_S_PiS_S_
.globl _Z11matrix_multPiS_S_
.type _Z11matrix_multPiS_S_, @function
_Z11matrix_multPiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11matrix_multPiS_S_, .-_Z11matrix_multPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Starting\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nNum threads per block: %dx%d Time spent: %lf\n"
.section .rodata.str1.1
.LC3:
.string "CUDA Error: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $400000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000000, %edi
call malloc@PLT
movq %rax, %r13
movq %rax, (%rsp)
movl $400000000, %edi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbp, %r12
leaq 400000000(%rbp), %r14
.L12:
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx)
addq $4, %rbx
cmpq $40000, %rbx
jne .L13
addq $40000, %r12
addq $40000, %r13
cmpq %r14, %r12
jne .L12
leaq 16(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000000, %esi
call cudaMalloc@PLT
movl $6, %r12d
movl $32, %ebx
leaq 64(%rsp), %r15
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
jmp .L17
.L23:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11matrix_multPiS_S_PiS_S_
jmp .L15
.L16:
sarl %ebx
subl $1, %r12d
je .L22
.L17:
movq %r15, %rsi
movl $0, %edi
call clock_gettime@PLT
movl $1, %ecx
movl $400000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000000, %edx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $10000, %eax
movl $0, %edx
divl %ebx
movl %eax, 52(%rsp)
movl %eax, 56(%rsp)
movl %ebx, 40(%rsp)
movl %ebx, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
movl $2, %ecx
movl $400000000, %edx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
leaq 80(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 88(%rsp), %xmm0
divsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 80(%rsp), %xmm1
addsd %xmm1, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 72(%rsp), %xmm1
divsd .LC1(%rip), %xmm1
pxor %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2
addsd %xmm2, %xmm1
subsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
je .L16
call cudaGetErrorString@PLT
movq %rax, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L22:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11matrix_multPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matrix_multPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1104006501
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mult.hip"
.globl _Z26__device_stub__matrix_multPiS_S_ # -- Begin function _Z26__device_stub__matrix_multPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__matrix_multPiS_S_,@function
_Z26__device_stub__matrix_multPiS_S_: # @_Z26__device_stub__matrix_multPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matrix_multPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__matrix_multPiS_S_, .Lfunc_end0-_Z26__device_stub__matrix_multPiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r13
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r14
movl $400000000, %edi # imm = 0x17D78400
callq malloc
movq %rax, %r15
movq %r13, 32(%rsp) # 8-byte Spill
movq %r14, %rbp
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbx,4)
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbp,%rbx,4)
incq %rbx
cmpq $10000, %rbx # imm = 0x2710
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $40000, %rbp # imm = 0x9C40
addq $40000, %r13 # imm = 0x9C40
cmpq $10000, %r12 # imm = 0x2710
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 16(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
leaq 8(%rsp), %rdi
movl $400000000, %esi # imm = 0x17D78400
callq hipMalloc
movl $32, %ebp
leaq 128(%rsp), %r12
leaq 112(%rsp), %r13
movq 32(%rsp), %rbx # 8-byte Reload
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_5 Depth=1
movl %ebp, %eax
shrl %eax
cmpl $2, %ebp
movl %eax, %ebp
jb .LBB1_10
.LBB1_5: # =>This Inner Loop Header: Depth=1
xorl %edi, %edi
movq %r12, %rsi
callq clock_gettime
movq 24(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $400000000, %edx # imm = 0x17D78400
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl %ebp, %eax
movq %rax, %rcx
shlq $32, %rcx
orq %rax, %rcx
movl $10000, %eax # imm = 0x2710
xorl %edx, %edx
divl %ebp
# kill: def $eax killed $eax def $rax
movq %rax, %rdi
shlq $32, %rdi
orq %rax, %rdi
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z11matrix_multPiS_S_, %edi
leaq 144(%rsp), %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
movq 8(%rsp), %rsi
movl $400000000, %edx # imm = 0x17D78400
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
xorl %edi, %edi
movq %r13, %rsi
callq clock_gettime
xorps %xmm0, %xmm0
cvtsi2sdq 112(%rsp), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 120(%rsp), %xmm1
movsd .LCPI1_0(%rip), %xmm3 # xmm3 = mem[0],zero
divsd %xmm3, %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 128(%rsp), %xmm0
cvtsi2sdq 136(%rsp), %xmm2
divsd %xmm3, %xmm2
addsd %xmm0, %xmm2
subsd %xmm2, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebp, %esi
movl %ebp, %edx
movb $1, %al
callq printf
callq hipGetLastError
testl %eax, %eax
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_5 Depth=1
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
jmp .LBB1_9
.LBB1_10:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matrix_multPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11matrix_multPiS_S_,@object # @_Z11matrix_multPiS_S_
.section .rodata,"a",@progbits
.globl _Z11matrix_multPiS_S_
.p2align 3, 0x0
_Z11matrix_multPiS_S_:
.quad _Z26__device_stub__matrix_multPiS_S_
.size _Z11matrix_multPiS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "\nNum threads per block: %dx%d Time spent: %lf\n"
.size .L.str.1, 47
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA Error: %s\n"
.size .L.str.2, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11matrix_multPiS_S_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Starting"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matrix_multPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matrix_multPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketSort(int *key, int *bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j=0, k=0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main() {
const int n = 50;
const int m = 64;
int range = 5;
int *key;
cudaMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
int *bucket;
cudaMallocManaged(&bucket, range*sizeof(int));
for (int i=0; i<range; i++) {
bucket[i] = 0;
}
bucketSort<<<(n+m-1)/m, m>>>(key, bucket, n);
cudaDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ",key[i]);
}
printf("\n");
} | code for sm_80
Function : _Z10bucketSortPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020b */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x004fca00078e020b */
/*00d0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e8000c10e184 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0120*/ IMAD.WIDE R4, R7.reuse, R11, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x040fe200078e020b */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ea000c101904 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc40007ffe0ff */
/*0160*/ IADD3 R9, R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x004fc80007ffe0ff */
/*0170*/ ISETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04270 */
/*0180*/ @!P0 BRA 0x120 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketSort(int *key, int *bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j=0, k=0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main() {
const int n = 50;
const int m = 64;
int range = 5;
int *key;
cudaMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
int *bucket;
cudaMallocManaged(&bucket, range*sizeof(int));
for (int i=0; i<range; i++) {
bucket[i] = 0;
}
bucketSort<<<(n+m-1)/m, m>>>(key, bucket, n);
cudaDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ",key[i]);
}
printf("\n");
} | .file "tmpxft_0008e2bb_00000000-6_12_bucket_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10bucketSortPiS_iPiS_i
.type _Z33__device_stub__Z10bucketSortPiS_iPiS_i, @function
_Z33__device_stub__Z10bucketSortPiS_iPiS_i:
.LFB2951:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10bucketSortPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2951:
.size _Z33__device_stub__Z10bucketSortPiS_iPiS_i, .-_Z33__device_stub__Z10bucketSortPiS_iPiS_i
.globl _Z10bucketSortPiS_i
.type _Z10bucketSortPiS_i, @function
_Z10bucketSortPiS_i:
.LFB2952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10bucketSortPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2952:
.size _Z10bucketSortPiS_i, .-_Z10bucketSortPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2926:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $200, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
movq (%rsp), %rdx
movl %eax, (%rdx,%rbx)
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $20, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L13:
movq 8(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $20, %rax
jne .L13
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L15:
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L15
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $50, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z10bucketSortPiS_iPiS_i
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2926:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10bucketSortPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bucketSortPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2954:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketSort(int *key, int *bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j=0, k=0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main() {
const int n = 50;
const int m = 64;
int range = 5;
int *key;
cudaMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
int *bucket;
cudaMallocManaged(&bucket, range*sizeof(int));
for (int i=0; i<range; i++) {
bucket[i] = 0;
}
bucketSort<<<(n+m-1)/m, m>>>(key, bucket, n);
cudaDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ",key[i]);
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketSort(int *key, int *bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j=0, k=0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main() {
const int n = 50;
const int m = 64;
int range = 5;
int *key;
hipMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
int *bucket;
hipMallocManaged(&bucket, range*sizeof(int));
for (int i=0; i<range; i++) {
bucket[i] = 0;
}
bucketSort<<<(n+m-1)/m, m>>>(key, bucket, n);
hipDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ",key[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketSort(int *key, int *bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j=0, k=0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main() {
const int n = 50;
const int m = 64;
int range = 5;
int *key;
hipMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
int *bucket;
hipMallocManaged(&bucket, range*sizeof(int));
for (int i=0; i<range; i++) {
bucket[i] = 0;
}
bucketSort<<<(n+m-1)/m, m>>>(key, bucket, n);
hipDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ",key[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bucketSortPiS_i
.globl _Z10bucketSortPiS_i
.p2align 8
.type _Z10bucketSortPiS_i,@function
_Z10bucketSortPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v1
global_atomic_add_u32 v[4:5], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
s_mov_b32 s1, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s1
s_add_i32 s1, s1, 1
global_store_b32 v[2:3], v5, off
global_load_b32 v5, v4, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, v0, v1
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bucketSortPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bucketSortPiS_i, .Lfunc_end0-_Z10bucketSortPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bucketSortPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10bucketSortPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <vector>
__global__ void bucketSort(int *key, int *bucket, int n) {
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n) return;
atomicAdd(&bucket[key[i]], 1);
__syncthreads();
for (int j=0, k=0; j <= i; k++) {
key[i] = k;
j += bucket[k];
}
}
int main() {
const int n = 50;
const int m = 64;
int range = 5;
int *key;
hipMallocManaged(&key, n*sizeof(int));
for (int i=0; i<n; i++) {
key[i] = rand() % range;
printf("%d ",key[i]);
}
printf("\n");
int *bucket;
hipMallocManaged(&bucket, range*sizeof(int));
for (int i=0; i<range; i++) {
bucket[i] = 0;
}
bucketSort<<<(n+m-1)/m, m>>>(key, bucket, n);
hipDeviceSynchronize();
for (int i=0; i<n; i++) {
printf("%d ",key[i]);
}
printf("\n");
} | .text
.file "12_bucket_sort.hip"
.globl _Z25__device_stub__bucketSortPiS_i # -- Begin function _Z25__device_stub__bucketSortPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__bucketSortPiS_i,@function
_Z25__device_stub__bucketSortPiS_i: # @_Z25__device_stub__bucketSortPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10bucketSortPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__bucketSortPiS_i, .Lfunc_end0-_Z25__device_stub__bucketSortPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $200, %esi
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $33, %rax
addl %ecx, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movq 8(%rsp), %rax
movl %esi, (%rax,%rbx,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movl $0, 16(%rax)
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $50, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10bucketSortPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bucketSortPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bucketSortPiS_i,@object # @_Z10bucketSortPiS_i
.section .rodata,"a",@progbits
.globl _Z10bucketSortPiS_i
.p2align 3, 0x0
_Z10bucketSortPiS_i:
.quad _Z25__device_stub__bucketSortPiS_i
.size _Z10bucketSortPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bucketSortPiS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bucketSortPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bucketSortPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10bucketSortPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R11, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e020b */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f06270 */
/*00c0*/ IMAD.WIDE R4, R4, R11, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x004fca00078e020b */
/*00d0*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e8000c10e184 */
/*00e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fc60000000f00 */
/*0120*/ IMAD.WIDE R4, R7.reuse, R11, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x040fe200078e020b */
/*0130*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001ea000c101904 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x001fc40007ffe0ff */
/*0160*/ IADD3 R9, R4, R9, RZ ; /* 0x0000000904097210 */
/* 0x004fc80007ffe0ff */
/*0170*/ ISETP.GT.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04270 */
/*0180*/ @!P0 BRA 0x120 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10bucketSortPiS_i
.globl _Z10bucketSortPiS_i
.p2align 8
.type _Z10bucketSortPiS_i,@function
_Z10bucketSortPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, -1, v1
global_atomic_add_u32 v[4:5], v0, off
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s0, 0
s_mov_b32 s1, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s1
s_add_i32 s1, s1, 1
global_store_b32 v[2:3], v5, off
global_load_b32 v5, v4, s[2:3]
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, v0, v1
s_or_b32 s0, vcc_lo, s0
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10bucketSortPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10bucketSortPiS_i, .Lfunc_end0-_Z10bucketSortPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10bucketSortPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10bucketSortPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008e2bb_00000000-6_12_bucket_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2929:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2929:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10bucketSortPiS_iPiS_i
.type _Z33__device_stub__Z10bucketSortPiS_iPiS_i, @function
_Z33__device_stub__Z10bucketSortPiS_iPiS_i:
.LFB2951:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10bucketSortPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2951:
.size _Z33__device_stub__Z10bucketSortPiS_iPiS_i, .-_Z33__device_stub__Z10bucketSortPiS_iPiS_i
.globl _Z10bucketSortPiS_i
.type _Z10bucketSortPiS_i, @function
_Z10bucketSortPiS_i:
.LFB2952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10bucketSortPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2952:
.size _Z10bucketSortPiS_i, .-_Z10bucketSortPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2926:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $1, %edx
movl $200, %esi
call cudaMallocManaged@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
subl %edx, %eax
movq (%rsp), %rdx
movl %eax, (%rdx,%rbx)
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $20, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L13:
movq 8(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $20, %rax
jne .L13
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
call cudaDeviceSynchronize@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L15:
movq (%rsp), %rax
movl (%rax,%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $200, %rbx
jne .L15
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $50, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z33__device_stub__Z10bucketSortPiS_iPiS_i
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2926:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10bucketSortPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2954:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10bucketSortPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2954:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "12_bucket_sort.hip"
.globl _Z25__device_stub__bucketSortPiS_i # -- Begin function _Z25__device_stub__bucketSortPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__bucketSortPiS_i,@function
_Z25__device_stub__bucketSortPiS_i: # @_Z25__device_stub__bucketSortPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10bucketSortPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__bucketSortPiS_i, .Lfunc_end0-_Z25__device_stub__bucketSortPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $200, %esi
movl $1, %edx
callq hipMallocManaged
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $33, %rax
addl %ecx, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movq 8(%rsp), %rax
movl %esi, (%rax,%rbx,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
leaq 24(%rsp), %rdi
movl $20, %esi
movl $1, %edx
callq hipMallocManaged
movq 24(%rsp), %rax
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movl $0, 16(%rax)
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 63(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $50, 20(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10bucketSortPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movl (%rax,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $50, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10bucketSortPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10bucketSortPiS_i,@object # @_Z10bucketSortPiS_i
.section .rodata,"a",@progbits
.globl _Z10bucketSortPiS_i
.p2align 3, 0x0
_Z10bucketSortPiS_i:
.quad _Z25__device_stub__bucketSortPiS_i
.size _Z10bucketSortPiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10bucketSortPiS_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__bucketSortPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10bucketSortPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <math.h>
#include <iostream>
#include <vector>
static const size_t N = 102400;
__global__ void kernel(const float* A, const float* B, float* C, int N)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < N) {
C[tid] = A[tid] + B[tid];
}
}
int main() {
std::vector<float> h_A, h_B, h_C;
h_A.resize(N);
h_B.resize(N);
h_C.resize(N);
for (int i = 0; i < N; i++) {
h_A[i] = i;
h_B[i] = 0.5f * i - 2;
}
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, sizeof(float) * N);
cudaMalloc(&d_B, sizeof(float) * N);
cudaMalloc(&d_C, sizeof(float) * N);
cudaMemcpy(d_A, &h_A[0], sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, &h_B[0], sizeof(float) * N, cudaMemcpyHostToDevice);
kernel<<<ceil(double(N) / 512), 512>>>(d_A, d_B, d_C, N);
cudaMemcpy(&h_C[0], d_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
double err = 0;
for (int i = 0; i < N; i++) {
err += (h_A[i] + h_B[i]) - h_C[i];
}
std::cout << "Cum error: " << sqrt(err) << std::endl;
return 0;
} | code for sm_80
Function : _Z6kernelPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <math.h>
#include <iostream>
#include <vector>
static const size_t N = 102400;
__global__ void kernel(const float* A, const float* B, float* C, int N)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < N) {
C[tid] = A[tid] + B[tid];
}
}
int main() {
std::vector<float> h_A, h_B, h_C;
h_A.resize(N);
h_B.resize(N);
h_C.resize(N);
for (int i = 0; i < N; i++) {
h_A[i] = i;
h_B[i] = 0.5f * i - 2;
}
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, sizeof(float) * N);
cudaMalloc(&d_B, sizeof(float) * N);
cudaMalloc(&d_C, sizeof(float) * N);
cudaMemcpy(d_A, &h_A[0], sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, &h_B[0], sizeof(float) * N, cudaMemcpyHostToDevice);
kernel<<<ceil(double(N) / 512), 512>>>(d_A, d_B, d_C, N);
cudaMemcpy(&h_C[0], d_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
double err = 0;
for (int i = 0; i < N; i++) {
err += (h_A[i] + h_B[i]) - h_C[i];
}
std::cout << "Cum error: " << sqrt(err) << std::endl;
return 0;
} | .file "tmpxft_0007d521_00000000-6_sumvec.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4045:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4045:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi
.type _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi, @function
_Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi:
.LFB4067:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi, .-_Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi
.globl _Z6kernelPKfS0_Pfi
.type _Z6kernelPKfS0_Pfi, @function
_Z6kernelPKfS0_Pfi:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z6kernelPKfS0_Pfi, .-_Z6kernelPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4380:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4380:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata._ZNSt6vectorIfSaIfEE17_M_default_appendEm.str1.1,"aMS",@progbits,1
.LC2:
.string "vector::_M_default_append"
.section .text._ZNSt6vectorIfSaIfEE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorIfSaIfEE17_M_default_appendEm,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.type _ZNSt6vectorIfSaIfEE17_M_default_appendEm, @function
_ZNSt6vectorIfSaIfEE17_M_default_appendEm:
.LFB4542:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L33
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %rbx
movq 8(%rdi), %rdx
movq (%rdi), %r15
movq %rdx, %r14
subq %r15, %r14
movq %r14, %r13
sarq $2, %r13
movabsq $2305843009213693951, %rax
subq %r13, %rax
movq %rax, %rcx
movq 16(%rdi), %rax
subq %rdx, %rax
sarq $2, %rax
cmpq %rsi, %rax
jb .L21
movl $0x00000000, (%rdx)
leaq 4(%rdx), %rsi
subq $1, %rbx
je .L22
leaq (%rsi,%rbx,4), %rcx
movq %rsi, %rax
.L23:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rcx
jne .L23
subq %rdx, %rcx
leaq -4(%rsi,%rcx), %rsi
.L22:
movq %rsi, 8(%rbp)
.L19:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
cmpq %rsi, %rcx
jb .L36
cmpq %r13, %rsi
movq %r13, %rax
cmovnb %rsi, %rax
addq %r13, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
cmova %rdx, %rax
salq $2, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call _Znwm@PLT
movq %rax, %r12
leaq (%rax,%r14), %rax
movl $0x00000000, (%rax)
movq %rbx, %rdx
subq $1, %rdx
je .L25
addq $4, %rax
leaq (%rax,%rdx,4), %rdx
.L26:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L26
.L25:
testq %r14, %r14
jg .L37
testq %r15, %r15
je .L29
movq 16(%rbp), %rsi
subq %r15, %rsi
jmp .L28
.L36:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L37:
movq %r14, %rdx
movq %r15, %rsi
movq %r12, %rdi
call memmove@PLT
movq 16(%rbp), %rsi
subq %r15, %rsi
.L28:
movq %r15, %rdi
call _ZdlPvm@PLT
.L29:
movq %r12, 0(%rbp)
addq %r13, %rbx
leaq (%r12,%rbx,4), %rax
movq %rax, 8(%rbp)
movq 8(%rsp), %rax
addq %rax, %r12
movq %r12, 16(%rbp)
jmp .L19
.L33:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE4542:
.size _ZNSt6vectorIfSaIfEE17_M_default_appendEm, .-_ZNSt6vectorIfSaIfEE17_M_default_appendEm
.section .text._ZNSt6vectorIfSaIfEE6resizeEm,"axG",@progbits,_ZNSt6vectorIfSaIfEE6resizeEm,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEE6resizeEm
.type _ZNSt6vectorIfSaIfEE6resizeEm, @function
_ZNSt6vectorIfSaIfEE6resizeEm:
.LFB4382:
.cfi_startproc
endbr64
movq 8(%rdi), %rdx
movq (%rdi), %rcx
movq %rdx, %rax
subq %rcx, %rax
sarq $2, %rax
cmpq %rsi, %rax
jb .L45
cmpq %rax, %rsi
jnb .L42
leaq (%rcx,%rsi,4), %rax
cmpq %rdx, %rax
je .L42
movq %rax, 8(%rdi)
ret
.L45:
subq $8, %rsp
.cfi_def_cfa_offset 16
subq %rax, %rsi
call _ZNSt6vectorIfSaIfEE17_M_default_appendEm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L42:
ret
.cfi_endproc
.LFE4382:
.size _ZNSt6vectorIfSaIfEE6resizeEm, .-_ZNSt6vectorIfSaIfEE6resizeEm
.section .rodata.str1.1
.LC6:
.string "Cum error: "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $160, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
leaq 64(%rsp), %rdi
movl $102400, %esi
.LEHB0:
call _ZNSt6vectorIfSaIfEE6resizeEm
leaq 96(%rsp), %rdi
movl $102400, %esi
call _ZNSt6vectorIfSaIfEE6resizeEm
leaq 128(%rsp), %rdi
movl $102400, %esi
call _ZNSt6vectorIfSaIfEE6resizeEm
movq 64(%rsp), %rbx
movq 96(%rsp), %rbp
movl $0, %eax
movss .LC4(%rip), %xmm2
movss .LC5(%rip), %xmm1
.L47:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
mulss %xmm2, %xmm0
subss %xmm1, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $102400, %rax
jne .L47
leaq 16(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $409600, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $409600, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $200, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movl $102400, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi
.L48:
movq 128(%rsp), %r12
movl $2, %ecx
movl $409600, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
movq $0x000000000, 8(%rsp)
.L49:
movss (%rbx,%rax), %xmm0
addss 0(%rbp,%rax), %xmm0
subss (%r12,%rax), %xmm0
cvtss2sd %xmm0, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $4, %rax
cmpq $409600, %rax
jne .L49
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
pxor %xmm0, %xmm0
movsd 8(%rsp), %xmm4
ucomisd %xmm4, %xmm0
ja .L60
sqrtsd %xmm4, %xmm4
movapd %xmm4, %xmm0
.L52:
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L63
.L60:
movsd 8(%rsp), %xmm0
call sqrt@PLT
jmp .L52
.L63:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE0:
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 .L56-.LFB4032
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1056964608
.align 4
.LC5:
.long 1073741824
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <math.h>
#include <iostream>
#include <vector>
static const size_t N = 102400;
__global__ void kernel(const float* A, const float* B, float* C, int N)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < N) {
C[tid] = A[tid] + B[tid];
}
}
int main() {
std::vector<float> h_A, h_B, h_C;
h_A.resize(N);
h_B.resize(N);
h_C.resize(N);
for (int i = 0; i < N; i++) {
h_A[i] = i;
h_B[i] = 0.5f * i - 2;
}
float *d_A, *d_B, *d_C;
cudaMalloc(&d_A, sizeof(float) * N);
cudaMalloc(&d_B, sizeof(float) * N);
cudaMalloc(&d_C, sizeof(float) * N);
cudaMemcpy(d_A, &h_A[0], sizeof(float) * N, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, &h_B[0], sizeof(float) * N, cudaMemcpyHostToDevice);
kernel<<<ceil(double(N) / 512), 512>>>(d_A, d_B, d_C, N);
cudaMemcpy(&h_C[0], d_C, sizeof(float) * N, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
double err = 0;
for (int i = 0; i < N; i++) {
err += (h_A[i] + h_B[i]) - h_C[i];
}
std::cout << "Cum error: " << sqrt(err) << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <math.h>
#include <iostream>
#include <vector>
static const size_t N = 102400;
__global__ void kernel(const float* A, const float* B, float* C, int N)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < N) {
C[tid] = A[tid] + B[tid];
}
}
int main() {
std::vector<float> h_A, h_B, h_C;
h_A.resize(N);
h_B.resize(N);
h_C.resize(N);
for (int i = 0; i < N; i++) {
h_A[i] = i;
h_B[i] = 0.5f * i - 2;
}
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, sizeof(float) * N);
hipMalloc(&d_B, sizeof(float) * N);
hipMalloc(&d_C, sizeof(float) * N);
hipMemcpy(d_A, &h_A[0], sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(d_B, &h_B[0], sizeof(float) * N, hipMemcpyHostToDevice);
kernel<<<ceil(double(N) / 512), 512>>>(d_A, d_B, d_C, N);
hipMemcpy(&h_C[0], d_C, sizeof(float) * N, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
double err = 0;
for (int i = 0; i < N; i++) {
err += (h_A[i] + h_B[i]) - h_C[i];
}
std::cout << "Cum error: " << sqrt(err) << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <iostream>
#include <vector>
static const size_t N = 102400;
__global__ void kernel(const float* A, const float* B, float* C, int N)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < N) {
C[tid] = A[tid] + B[tid];
}
}
int main() {
std::vector<float> h_A, h_B, h_C;
h_A.resize(N);
h_B.resize(N);
h_C.resize(N);
for (int i = 0; i < N; i++) {
h_A[i] = i;
h_B[i] = 0.5f * i - 2;
}
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, sizeof(float) * N);
hipMalloc(&d_B, sizeof(float) * N);
hipMalloc(&d_C, sizeof(float) * N);
hipMemcpy(d_A, &h_A[0], sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(d_B, &h_B[0], sizeof(float) * N, hipMemcpyHostToDevice);
kernel<<<ceil(double(N) / 512), 512>>>(d_A, d_B, d_C, N);
hipMemcpy(&h_C[0], d_C, sizeof(float) * N, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
double err = 0;
for (int i = 0; i < N; i++) {
err += (h_A[i] + h_B[i]) - h_C[i];
}
std::cout << "Cum error: " << sqrt(err) << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPKfS0_Pfi
.globl _Z6kernelPKfS0_Pfi
.p2align 8
.type _Z6kernelPKfS0_Pfi,@function
_Z6kernelPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPKfS0_Pfi, .Lfunc_end0-_Z6kernelPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <math.h>
#include <iostream>
#include <vector>
static const size_t N = 102400;
__global__ void kernel(const float* A, const float* B, float* C, int N)
{
int tid = blockDim.x * blockIdx.x + threadIdx.x;
if (tid < N) {
C[tid] = A[tid] + B[tid];
}
}
int main() {
std::vector<float> h_A, h_B, h_C;
h_A.resize(N);
h_B.resize(N);
h_C.resize(N);
for (int i = 0; i < N; i++) {
h_A[i] = i;
h_B[i] = 0.5f * i - 2;
}
float *d_A, *d_B, *d_C;
hipMalloc(&d_A, sizeof(float) * N);
hipMalloc(&d_B, sizeof(float) * N);
hipMalloc(&d_C, sizeof(float) * N);
hipMemcpy(d_A, &h_A[0], sizeof(float) * N, hipMemcpyHostToDevice);
hipMemcpy(d_B, &h_B[0], sizeof(float) * N, hipMemcpyHostToDevice);
kernel<<<ceil(double(N) / 512), 512>>>(d_A, d_B, d_C, N);
hipMemcpy(&h_C[0], d_C, sizeof(float) * N, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
double err = 0;
for (int i = 0; i < N; i++) {
err += (h_A[i] + h_B[i]) - h_C[i];
}
std::cout << "Cum error: " << sqrt(err) << std::endl;
return 0;
} | .text
.file "sumvec.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPKfS0_Pfi # -- Begin function _Z21__device_stub__kernelPKfS0_Pfi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPKfS0_Pfi,@function
_Z21__device_stub__kernelPKfS0_Pfi: # @_Z21__device_stub__kernelPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPKfS0_Pfi, .Lfunc_end0-_Z21__device_stub__kernelPKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f000000 # float 0.5
.LCPI1_1:
.long 0xc0000000 # float -2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $248, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
movaps %xmm0, 96(%rsp)
movq $0, 112(%rsp)
movq 64(%rsp), %rax
movq 72(%rsp), %rcx
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, %rdi
sarq $2, %rdi
cmpq $102399, %rdi # imm = 0x18FFF
ja .LBB1_2
# %bb.1:
movl $102400, %esi # imm = 0x19000
subq %rdi, %rsi
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.Ltmp1:
jmp .LBB1_5
.LBB1_2:
cmpq $409600, %rdx # imm = 0x64000
je .LBB1_5
# %bb.3:
addq $409600, %rax # imm = 0x64000
cmpq %rax, %rcx
je .LBB1_5
# %bb.4:
movq %rax, 72(%rsp)
.LBB1_5: # %_ZNSt6vectorIfSaIfEE6resizeEm.exit
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, %rdi
sarq $2, %rdi
cmpq $102399, %rdi # imm = 0x18FFF
ja .LBB1_7
# %bb.6:
movl $102400, %esi # imm = 0x19000
subq %rdi, %rsi
.Ltmp2:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.Ltmp3:
jmp .LBB1_10
.LBB1_7:
cmpq $409600, %rdx # imm = 0x64000
je .LBB1_10
# %bb.8:
addq $409600, %rax # imm = 0x64000
cmpq %rax, %rcx
je .LBB1_10
# %bb.9:
movq %rax, 40(%rsp)
.LBB1_10: # %_ZNSt6vectorIfSaIfEE6resizeEm.exit28
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, %rdi
sarq $2, %rdi
cmpq $102399, %rdi # imm = 0x18FFF
ja .LBB1_12
# %bb.11:
movl $102400, %esi # imm = 0x19000
subq %rdi, %rsi
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.Ltmp5:
jmp .LBB1_15
.LBB1_12:
cmpq $409600, %rdx # imm = 0x64000
je .LBB1_15
# %bb.13:
addq $409600, %rax # imm = 0x64000
cmpq %rax, %rcx
je .LBB1_15
# %bb.14:
movq %rax, 104(%rsp)
.LBB1_15: # %_ZNSt6vectorIfSaIfEE6resizeEm.exit31
movq 64(%rsp), %rax
movq 32(%rsp), %rcx
xorl %edx, %edx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
movss %xmm2, (%rax,%rdx,4)
mulss %xmm0, %xmm2
addss %xmm1, %xmm2
movss %xmm2, (%rcx,%rdx,4)
incq %rdx
cmpq $102400, %rdx # imm = 0x19000
jne .LBB1_16
# %bb.17:
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
.Ltmp8:
# %bb.18: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
.Ltmp10:
# %bb.19: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit34
.Ltmp11:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
.Ltmp12:
# %bb.20: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit36
movq 16(%rsp), %rdi
movq 64(%rsp), %rsi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $409600, %edx # imm = 0x64000
movl $1, %ecx
callq hipMemcpy
.Ltmp14:
# %bb.21:
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi
.Ltmp15:
.cfi_escape 0x2e, 0x00
movl $409600, %edx # imm = 0x64000
movl $1, %ecx
callq hipMemcpy
.Ltmp16:
# %bb.22:
.Ltmp17:
.cfi_escape 0x2e, 0x00
movabsq $4294967496, %rdi # imm = 0x1000000C8
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp18:
# %bb.23:
testl %eax, %eax
jne .LBB1_26
# %bb.24:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movl $102400, 28(%rsp) # imm = 0x19000
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 28(%rsp), %rax
movq %rax, 232(%rsp)
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp20:
# %bb.25: # %.noexc37
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
.Ltmp21:
.cfi_escape 0x2e, 0x10
leaq 208(%rsp), %r9
movl $_Z6kernelPKfS0_Pfi, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp22:
.LBB1_26:
movq 96(%rsp), %rdi
movq (%rsp), %rsi
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $409600, %edx # imm = 0x64000
movl $2, %ecx
callq hipMemcpy
.Ltmp24:
# %bb.27:
movq 16(%rsp), %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp26:
# %bb.28:
movq 8(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp28:
# %bb.29:
movq (%rsp), %rdi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp30:
# %bb.30: # %.preheader
movq 64(%rsp), %rax
movq 32(%rsp), %rcx
xorps %xmm1, %xmm1
movq 96(%rsp), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_31: # =>This Inner Loop Header: Depth=1
movss (%rax,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rcx,%rsi,4), %xmm0
subss (%rdx,%rsi,4), %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
incq %rsi
cmpq $102400, %rsi # imm = 0x19000
jne .LBB1_31
# %bb.32:
.Ltmp32:
movsd %xmm1, 128(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
xorpd %xmm1, %xmm1
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
jb .LBB1_35
# %bb.34:
sqrtsd %xmm0, %xmm0
jmp .LBB1_36
.LBB1_35: # %call.sqrt
.cfi_escape 0x2e, 0x00
callq sqrt
.LBB1_36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit.split
.Ltmp34:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp35:
# %bb.37: # %_ZNSolsEd.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_38
# %bb.40: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_42
# %bb.41:
movzbl 67(%r14), %eax
jmp .LBB1_44
.LBB1_42:
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp37:
# %bb.43: # %.noexc54
movq (%r14), %rax
.Ltmp38:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp39:
.LBB1_44: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp40:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp41:
# %bb.45: # %.noexc56
.Ltmp42:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp43:
# %bb.46: # %_ZNSolsEPFRSoS_E.exit
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_48
# %bb.47:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_48: # %_ZNSt6vectorIfSaIfEED2Ev.exit
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_50
# %bb.49:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_50: # %_ZNSt6vectorIfSaIfEED2Ev.exit43
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_52
# %bb.51:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_52: # %_ZNSt6vectorIfSaIfEED2Ev.exit45
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_38:
.cfi_def_cfa_offset 272
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp45:
# %bb.39: # %.noexc53
.LBB1_61:
.Ltmp6:
jmp .LBB1_54
.LBB1_53:
.Ltmp46:
jmp .LBB1_54
.LBB1_62:
.Ltmp31:
.LBB1_54:
movq %rax, %rbx
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_56
# %bb.55:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_56: # %_ZNSt6vectorIfSaIfEED2Ev.exit47
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_58
# %bb.57:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_58: # %_ZNSt6vectorIfSaIfEED2Ev.exit49
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_60
# %bb.59:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_60: # %_ZNSt6vectorIfSaIfEED2Ev.exit51
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp30-.Ltmp7 # Call between .Ltmp7 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp45-.Ltmp32 # Call between .Ltmp32 and .Ltmp45
.uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end1-.Ltmp45 # Call between .Ltmp45 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt6vectorIfSaIfEE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorIfSaIfEE17_M_default_appendEm,comdat
.weak _ZNSt6vectorIfSaIfEE17_M_default_appendEm # -- Begin function _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.p2align 4, 0x90
.type _ZNSt6vectorIfSaIfEE17_M_default_appendEm,@function
_ZNSt6vectorIfSaIfEE17_M_default_appendEm: # @_ZNSt6vectorIfSaIfEE17_M_default_appendEm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testq %rsi, %rsi
je .LBB2_16
# %bb.1:
movq %rsi, %r14
movq %rdi, %rbx
movq 8(%rdi), %r12
movq 16(%rdi), %rax
subq %r12, %rax
sarq $2, %rax
cmpq %rsi, %rax
jae .LBB2_2
# %bb.5:
movabsq $2305843009213693951, %rax # imm = 0x1FFFFFFFFFFFFFFF
movq (%rbx), %rcx
movq %rcx, 16(%rsp) # 8-byte Spill
subq %rcx, %r12
movq %r12, %r15
sarq $2, %r15
movq %r15, %rcx
xorq %rax, %rcx
cmpq %r14, %rcx
jb .LBB2_17
# %bb.6: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit
cmpq %r14, %r15
movq %r14, %rcx
cmovaq %r15, %rcx
leaq (%rcx,%r15), %rbp
cmpq %rax, %rbp
cmovaeq %rax, %rbp
addq %r15, %rcx
cmovbq %rax, %rbp
testq %rbp, %rbp
je .LBB2_7
# %bb.8:
leaq (,%rbp,4), %rdi
callq _Znwm
movq %rax, %r13
jmp .LBB2_9
.LBB2_2:
movl $0, (%r12)
leaq 4(%r12), %rdi
cmpq $1, %r14
je .LBB2_4
# %bb.3: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i
leaq -4(,%r14,4), %rdx
xorl %esi, %esi
callq memset@PLT
leaq (%r12,%r14,4), %rdi
.LBB2_4: # %_ZSt27__uninitialized_default_n_aIPfmfET_S1_T0_RSaIT1_E.exit
movq %rdi, 8(%rbx)
jmp .LBB2_16
.LBB2_7:
xorl %r13d, %r13d
.LBB2_9: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit
leaq (,%r15,4), %rax
addq %r13, %rax
movq %rax, 8(%rsp) # 8-byte Spill
movl $0, (%r13,%r15,4)
cmpq $1, %r14
je .LBB2_11
# %bb.10: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i30
movq 8(%rsp), %rax # 8-byte Reload
leaq 4(%rax), %rdi
leaq -4(,%r14,4), %rdx
xorl %esi, %esi
callq memset@PLT
.LBB2_11: # %_ZSt27__uninitialized_default_n_aIPfmfET_S1_T0_RSaIT1_E.exit32
testq %r12, %r12
movq 16(%rsp), %r15 # 8-byte Reload
jle .LBB2_13
# %bb.12:
movq %r13, %rdi
movq %r15, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB2_13: # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit
testq %r15, %r15
je .LBB2_15
# %bb.14:
movq %r15, %rdi
callq _ZdlPv
.LBB2_15: # %_ZNSt12_Vector_baseIfSaIfEE13_M_deallocateEPfm.exit35
movq %r13, (%rbx)
movq 8(%rsp), %rax # 8-byte Reload
leaq (%rax,%r14,4), %rax
movq %rax, 8(%rbx)
leaq (,%rbp,4), %rax
addq %r13, %rax
movq %rax, 16(%rbx)
.LBB2_16:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 80
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end2:
.size _ZNSt6vectorIfSaIfEE17_M_default_appendEm, .Lfunc_end2-_ZNSt6vectorIfSaIfEE17_M_default_appendEm
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPKfS0_Pfi,@object # @_Z6kernelPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z6kernelPKfS0_Pfi
.p2align 3, 0x0
_Z6kernelPKfS0_Pfi:
.quad _Z21__device_stub__kernelPKfS0_Pfi
.size _Z6kernelPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cum error: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "vector::_M_default_append"
.size .L.str.1, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPKfS0_Pfi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPKfS0_Pfi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelPKfS0_Pfi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelPKfS0_Pfi
.globl _Z6kernelPKfS0_Pfi
.p2align 8
.type _Z6kernelPKfS0_Pfi,@function
_Z6kernelPKfS0_Pfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelPKfS0_Pfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelPKfS0_Pfi, .Lfunc_end0-_Z6kernelPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007d521_00000000-6_sumvec.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4045:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4045:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi
.type _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi, @function
_Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi:
.LFB4067:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi, .-_Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi
.globl _Z6kernelPKfS0_Pfi
.type _Z6kernelPKfS0_Pfi, @function
_Z6kernelPKfS0_Pfi:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z6kernelPKfS0_Pfi, .-_Z6kernelPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6kernelPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4380:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L16
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L16:
ret
.cfi_endproc
.LFE4380:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata._ZNSt6vectorIfSaIfEE17_M_default_appendEm.str1.1,"aMS",@progbits,1
.LC2:
.string "vector::_M_default_append"
.section .text._ZNSt6vectorIfSaIfEE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorIfSaIfEE17_M_default_appendEm,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.type _ZNSt6vectorIfSaIfEE17_M_default_appendEm, @function
_ZNSt6vectorIfSaIfEE17_M_default_appendEm:
.LFB4542:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L33
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %rbx
movq 8(%rdi), %rdx
movq (%rdi), %r15
movq %rdx, %r14
subq %r15, %r14
movq %r14, %r13
sarq $2, %r13
movabsq $2305843009213693951, %rax
subq %r13, %rax
movq %rax, %rcx
movq 16(%rdi), %rax
subq %rdx, %rax
sarq $2, %rax
cmpq %rsi, %rax
jb .L21
movl $0x00000000, (%rdx)
leaq 4(%rdx), %rsi
subq $1, %rbx
je .L22
leaq (%rsi,%rbx,4), %rcx
movq %rsi, %rax
.L23:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rcx
jne .L23
subq %rdx, %rcx
leaq -4(%rsi,%rcx), %rsi
.L22:
movq %rsi, 8(%rbp)
.L19:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
cmpq %rsi, %rcx
jb .L36
cmpq %r13, %rsi
movq %r13, %rax
cmovnb %rsi, %rax
addq %r13, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
cmova %rdx, %rax
salq $2, %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call _Znwm@PLT
movq %rax, %r12
leaq (%rax,%r14), %rax
movl $0x00000000, (%rax)
movq %rbx, %rdx
subq $1, %rdx
je .L25
addq $4, %rax
leaq (%rax,%rdx,4), %rdx
.L26:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L26
.L25:
testq %r14, %r14
jg .L37
testq %r15, %r15
je .L29
movq 16(%rbp), %rsi
subq %r15, %rsi
jmp .L28
.L36:
leaq .LC2(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L37:
movq %r14, %rdx
movq %r15, %rsi
movq %r12, %rdi
call memmove@PLT
movq 16(%rbp), %rsi
subq %r15, %rsi
.L28:
movq %r15, %rdi
call _ZdlPvm@PLT
.L29:
movq %r12, 0(%rbp)
addq %r13, %rbx
leaq (%r12,%rbx,4), %rax
movq %rax, 8(%rbp)
movq 8(%rsp), %rax
addq %rax, %r12
movq %r12, 16(%rbp)
jmp .L19
.L33:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE4542:
.size _ZNSt6vectorIfSaIfEE17_M_default_appendEm, .-_ZNSt6vectorIfSaIfEE17_M_default_appendEm
.section .text._ZNSt6vectorIfSaIfEE6resizeEm,"axG",@progbits,_ZNSt6vectorIfSaIfEE6resizeEm,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEE6resizeEm
.type _ZNSt6vectorIfSaIfEE6resizeEm, @function
_ZNSt6vectorIfSaIfEE6resizeEm:
.LFB4382:
.cfi_startproc
endbr64
movq 8(%rdi), %rdx
movq (%rdi), %rcx
movq %rdx, %rax
subq %rcx, %rax
sarq $2, %rax
cmpq %rsi, %rax
jb .L45
cmpq %rax, %rsi
jnb .L42
leaq (%rcx,%rsi,4), %rax
cmpq %rdx, %rax
je .L42
movq %rax, 8(%rdi)
ret
.L45:
subq $8, %rsp
.cfi_def_cfa_offset 16
subq %rax, %rsi
call _ZNSt6vectorIfSaIfEE17_M_default_appendEm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L42:
ret
.cfi_endproc
.LFE4382:
.size _ZNSt6vectorIfSaIfEE6resizeEm, .-_ZNSt6vectorIfSaIfEE6resizeEm
.section .rodata.str1.1
.LC6:
.string "Cum error: "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $160, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
leaq 64(%rsp), %rdi
movl $102400, %esi
.LEHB0:
call _ZNSt6vectorIfSaIfEE6resizeEm
leaq 96(%rsp), %rdi
movl $102400, %esi
call _ZNSt6vectorIfSaIfEE6resizeEm
leaq 128(%rsp), %rdi
movl $102400, %esi
call _ZNSt6vectorIfSaIfEE6resizeEm
movq 64(%rsp), %rbx
movq 96(%rsp), %rbp
movl $0, %eax
movss .LC4(%rip), %xmm2
movss .LC5(%rip), %xmm1
.L47:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
mulss %xmm2, %xmm0
subss %xmm1, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $102400, %rax
jne .L47
leaq 16(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $409600, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $409600, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $409600, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $200, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L48
movl $102400, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z6kernelPKfS0_PfiPKfS0_Pfi
.L48:
movq 128(%rsp), %r12
movl $2, %ecx
movl $409600, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movl $0, %eax
movq $0x000000000, 8(%rsp)
.L49:
movss (%rbx,%rax), %xmm0
addss 0(%rbp,%rax), %xmm0
subss (%r12,%rax), %xmm0
cvtss2sd %xmm0, %xmm0
addsd 8(%rsp), %xmm0
movsd %xmm0, 8(%rsp)
addq $4, %rax
cmpq $409600, %rax
jne .L49
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
pxor %xmm0, %xmm0
movsd 8(%rsp), %xmm4
ucomisd %xmm4, %xmm0
ja .L60
sqrtsd %xmm4, %xmm4
movapd %xmm4, %xmm0
.L52:
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
jmp .L63
.L60:
movsd 8(%rsp), %xmm0
call sqrt@PLT
jmp .L52
.L63:
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE0:
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 152(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 .L56-.LFB4032
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1056964608
.align 4
.LC5:
.long 1073741824
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumvec.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelPKfS0_Pfi # -- Begin function _Z21__device_stub__kernelPKfS0_Pfi
.p2align 4, 0x90
.type _Z21__device_stub__kernelPKfS0_Pfi,@function
_Z21__device_stub__kernelPKfS0_Pfi: # @_Z21__device_stub__kernelPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelPKfS0_Pfi, .Lfunc_end0-_Z21__device_stub__kernelPKfS0_Pfi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3f000000 # float 0.5
.LCPI1_1:
.long 0xc0000000 # float -2
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $248, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorps %xmm0, %xmm0
movaps %xmm0, 64(%rsp)
movq $0, 80(%rsp)
movaps %xmm0, 32(%rsp)
movq $0, 48(%rsp)
movaps %xmm0, 96(%rsp)
movq $0, 112(%rsp)
movq 64(%rsp), %rax
movq 72(%rsp), %rcx
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, %rdi
sarq $2, %rdi
cmpq $102399, %rdi # imm = 0x18FFF
ja .LBB1_2
# %bb.1:
movl $102400, %esi # imm = 0x19000
subq %rdi, %rsi
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
callq _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.Ltmp1:
jmp .LBB1_5
.LBB1_2:
cmpq $409600, %rdx # imm = 0x64000
je .LBB1_5
# %bb.3:
addq $409600, %rax # imm = 0x64000
cmpq %rax, %rcx
je .LBB1_5
# %bb.4:
movq %rax, 72(%rsp)
.LBB1_5: # %_ZNSt6vectorIfSaIfEE6resizeEm.exit
movq 32(%rsp), %rax
movq 40(%rsp), %rcx
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, %rdi
sarq $2, %rdi
cmpq $102399, %rdi # imm = 0x18FFF
ja .LBB1_7
# %bb.6:
movl $102400, %esi # imm = 0x19000
subq %rdi, %rsi
.Ltmp2:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
callq _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.Ltmp3:
jmp .LBB1_10
.LBB1_7:
cmpq $409600, %rdx # imm = 0x64000
je .LBB1_10
# %bb.8:
addq $409600, %rax # imm = 0x64000
cmpq %rax, %rcx
je .LBB1_10
# %bb.9:
movq %rax, 40(%rsp)
.LBB1_10: # %_ZNSt6vectorIfSaIfEE6resizeEm.exit28
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, %rdi
sarq $2, %rdi
cmpq $102399, %rdi # imm = 0x18FFF
ja .LBB1_12
# %bb.11:
movl $102400, %esi # imm = 0x19000
subq %rdi, %rsi
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
callq _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.Ltmp5:
jmp .LBB1_15
.LBB1_12:
cmpq $409600, %rdx # imm = 0x64000
je .LBB1_15
# %bb.13:
addq $409600, %rax # imm = 0x64000
cmpq %rax, %rcx
je .LBB1_15
# %bb.14:
movq %rax, 104(%rsp)
.LBB1_15: # %_ZNSt6vectorIfSaIfEE6resizeEm.exit31
movq 64(%rsp), %rax
movq 32(%rsp), %rcx
xorl %edx, %edx
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_16: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %edx, %xmm2
movss %xmm2, (%rax,%rdx,4)
mulss %xmm0, %xmm2
addss %xmm1, %xmm2
movss %xmm2, (%rcx,%rdx,4)
incq %rdx
cmpq $102400, %rdx # imm = 0x19000
jne .LBB1_16
# %bb.17:
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
.Ltmp8:
# %bb.18: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
.Ltmp10:
# %bb.19: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit34
.Ltmp11:
.cfi_escape 0x2e, 0x00
movq %rsp, %rdi
movl $409600, %esi # imm = 0x64000
callq hipMalloc
.Ltmp12:
# %bb.20: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit36
movq 16(%rsp), %rdi
movq 64(%rsp), %rsi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $409600, %edx # imm = 0x64000
movl $1, %ecx
callq hipMemcpy
.Ltmp14:
# %bb.21:
movq 8(%rsp), %rdi
movq 32(%rsp), %rsi
.Ltmp15:
.cfi_escape 0x2e, 0x00
movl $409600, %edx # imm = 0x64000
movl $1, %ecx
callq hipMemcpy
.Ltmp16:
# %bb.22:
.Ltmp17:
.cfi_escape 0x2e, 0x00
movabsq $4294967496, %rdi # imm = 0x1000000C8
movabsq $4294967808, %rdx # imm = 0x100000200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp18:
# %bb.23:
testl %eax, %eax
jne .LBB1_26
# %bb.24:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 200(%rsp)
movq %rcx, 192(%rsp)
movq %rdx, 184(%rsp)
movl $102400, 28(%rsp) # imm = 0x19000
leaq 200(%rsp), %rax
movq %rax, 208(%rsp)
leaq 192(%rsp), %rax
movq %rax, 216(%rsp)
leaq 184(%rsp), %rax
movq %rax, 224(%rsp)
leaq 28(%rsp), %rax
movq %rax, 232(%rsp)
.Ltmp19:
.cfi_escape 0x2e, 0x00
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp20:
# %bb.25: # %.noexc37
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
.Ltmp21:
.cfi_escape 0x2e, 0x10
leaq 208(%rsp), %r9
movl $_Z6kernelPKfS0_Pfi, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp22:
.LBB1_26:
movq 96(%rsp), %rdi
movq (%rsp), %rsi
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $409600, %edx # imm = 0x64000
movl $2, %ecx
callq hipMemcpy
.Ltmp24:
# %bb.27:
movq 16(%rsp), %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp26:
# %bb.28:
movq 8(%rsp), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp28:
# %bb.29:
movq (%rsp), %rdi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp30:
# %bb.30: # %.preheader
movq 64(%rsp), %rax
movq 32(%rsp), %rcx
xorps %xmm1, %xmm1
movq 96(%rsp), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_31: # =>This Inner Loop Header: Depth=1
movss (%rax,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
addss (%rcx,%rsi,4), %xmm0
subss (%rdx,%rsi,4), %xmm0
cvtss2sd %xmm0, %xmm0
addsd %xmm0, %xmm1
incq %rsi
cmpq $102400, %rsi # imm = 0x19000
jne .LBB1_31
# %bb.32:
.Ltmp32:
movsd %xmm1, 128(%rsp) # 8-byte Spill
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.33: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
xorpd %xmm1, %xmm1
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
ucomisd %xmm1, %xmm0
jb .LBB1_35
# %bb.34:
sqrtsd %xmm0, %xmm0
jmp .LBB1_36
.LBB1_35: # %call.sqrt
.cfi_escape 0x2e, 0x00
callq sqrt
.LBB1_36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit.split
.Ltmp34:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp35:
# %bb.37: # %_ZNSolsEd.exit
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB1_38
# %bb.40: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_42
# %bb.41:
movzbl 67(%r14), %eax
jmp .LBB1_44
.LBB1_42:
.Ltmp36:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp37:
# %bb.43: # %.noexc54
movq (%r14), %rax
.Ltmp38:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp39:
.LBB1_44: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp40:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
.Ltmp41:
# %bb.45: # %.noexc56
.Ltmp42:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp43:
# %bb.46: # %_ZNSolsEPFRSoS_E.exit
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_48
# %bb.47:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_48: # %_ZNSt6vectorIfSaIfEED2Ev.exit
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_50
# %bb.49:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_50: # %_ZNSt6vectorIfSaIfEED2Ev.exit43
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_52
# %bb.51:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_52: # %_ZNSt6vectorIfSaIfEED2Ev.exit45
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_38:
.cfi_def_cfa_offset 272
.Ltmp44:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp45:
# %bb.39: # %.noexc53
.LBB1_61:
.Ltmp6:
jmp .LBB1_54
.LBB1_53:
.Ltmp46:
jmp .LBB1_54
.LBB1_62:
.Ltmp31:
.LBB1_54:
movq %rax, %rbx
movq 96(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_56
# %bb.55:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_56: # %_ZNSt6vectorIfSaIfEED2Ev.exit47
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_58
# %bb.57:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_58: # %_ZNSt6vectorIfSaIfEED2Ev.exit49
movq 64(%rsp), %rdi
testq %rdi, %rdi
je .LBB1_60
# %bb.59:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_60: # %_ZNSt6vectorIfSaIfEED2Ev.exit51
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp5-.Ltmp0 # Call between .Ltmp0 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp30-.Ltmp7 # Call between .Ltmp7 and .Ltmp30
.uleb128 .Ltmp31-.Lfunc_begin0 # jumps to .Ltmp31
.byte 0 # On action: cleanup
.uleb128 .Ltmp32-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp45-.Ltmp32 # Call between .Ltmp32 and .Ltmp45
.uleb128 .Ltmp46-.Lfunc_begin0 # jumps to .Ltmp46
.byte 0 # On action: cleanup
.uleb128 .Ltmp45-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end1-.Ltmp45 # Call between .Ltmp45 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt6vectorIfSaIfEE17_M_default_appendEm,"axG",@progbits,_ZNSt6vectorIfSaIfEE17_M_default_appendEm,comdat
.weak _ZNSt6vectorIfSaIfEE17_M_default_appendEm # -- Begin function _ZNSt6vectorIfSaIfEE17_M_default_appendEm
.p2align 4, 0x90
.type _ZNSt6vectorIfSaIfEE17_M_default_appendEm,@function
_ZNSt6vectorIfSaIfEE17_M_default_appendEm: # @_ZNSt6vectorIfSaIfEE17_M_default_appendEm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
testq %rsi, %rsi
je .LBB2_16
# %bb.1:
movq %rsi, %r14
movq %rdi, %rbx
movq 8(%rdi), %r12
movq 16(%rdi), %rax
subq %r12, %rax
sarq $2, %rax
cmpq %rsi, %rax
jae .LBB2_2
# %bb.5:
movabsq $2305843009213693951, %rax # imm = 0x1FFFFFFFFFFFFFFF
movq (%rbx), %rcx
movq %rcx, 16(%rsp) # 8-byte Spill
subq %rcx, %r12
movq %r12, %r15
sarq $2, %r15
movq %r15, %rcx
xorq %rax, %rcx
cmpq %r14, %rcx
jb .LBB2_17
# %bb.6: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit
cmpq %r14, %r15
movq %r14, %rcx
cmovaq %r15, %rcx
leaq (%rcx,%r15), %rbp
cmpq %rax, %rbp
cmovaeq %rax, %rbp
addq %r15, %rcx
cmovbq %rax, %rbp
testq %rbp, %rbp
je .LBB2_7
# %bb.8:
leaq (,%rbp,4), %rdi
callq _Znwm
movq %rax, %r13
jmp .LBB2_9
.LBB2_2:
movl $0, (%r12)
leaq 4(%r12), %rdi
cmpq $1, %r14
je .LBB2_4
# %bb.3: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i
leaq -4(,%r14,4), %rdx
xorl %esi, %esi
callq memset@PLT
leaq (%r12,%r14,4), %rdi
.LBB2_4: # %_ZSt27__uninitialized_default_n_aIPfmfET_S1_T0_RSaIT1_E.exit
movq %rdi, 8(%rbx)
jmp .LBB2_16
.LBB2_7:
xorl %r13d, %r13d
.LBB2_9: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit
leaq (,%r15,4), %rax
addq %r13, %rax
movq %rax, 8(%rsp) # 8-byte Spill
movl $0, (%r13,%r15,4)
cmpq $1, %r14
je .LBB2_11
# %bb.10: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i30
movq 8(%rsp), %rax # 8-byte Reload
leaq 4(%rax), %rdi
leaq -4(,%r14,4), %rdx
xorl %esi, %esi
callq memset@PLT
.LBB2_11: # %_ZSt27__uninitialized_default_n_aIPfmfET_S1_T0_RSaIT1_E.exit32
testq %r12, %r12
movq 16(%rsp), %r15 # 8-byte Reload
jle .LBB2_13
# %bb.12:
movq %r13, %rdi
movq %r15, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB2_13: # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit
testq %r15, %r15
je .LBB2_15
# %bb.14:
movq %r15, %rdi
callq _ZdlPv
.LBB2_15: # %_ZNSt12_Vector_baseIfSaIfEE13_M_deallocateEPfm.exit35
movq %r13, (%rbx)
movq 8(%rsp), %rax # 8-byte Reload
leaq (%rax,%r14,4), %rax
movq %rax, 8(%rbx)
leaq (,%rbp,4), %rax
addq %r13, %rax
movq %rax, 16(%rbx)
.LBB2_16:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_17:
.cfi_def_cfa_offset 80
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end2:
.size _ZNSt6vectorIfSaIfEE17_M_default_appendEm, .Lfunc_end2-_ZNSt6vectorIfSaIfEE17_M_default_appendEm
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelPKfS0_Pfi,@object # @_Z6kernelPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z6kernelPKfS0_Pfi
.p2align 3, 0x0
_Z6kernelPKfS0_Pfi:
.quad _Z21__device_stub__kernelPKfS0_Pfi
.size _Z6kernelPKfS0_Pfi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cum error: "
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "vector::_M_default_append"
.size .L.str.1, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelPKfS0_Pfi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelPKfS0_Pfi
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z6kernelPKfS0_Pfi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
inline void check_cuda_errors(const char *filename, const int line_number){
#ifdef DEBUG
cudaThreadSynchronize();
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess){
printf("CUDA error at %s:%i: %s\n", filename, line_number, cudaGetErrorString(error));
exit(-1);
}
#endif
}
__global__ void foo(int *ptr){
*ptr = 7;
}
int main(){
foo<<<1,1>>>(0);
check_cuda_errors(__FILE__, __LINE__);
return 0;
} | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x7 ; /* 0x00000007ff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
inline void check_cuda_errors(const char *filename, const int line_number){
#ifdef DEBUG
cudaThreadSynchronize();
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess){
printf("CUDA error at %s:%i: %s\n", filename, line_number, cudaGetErrorString(error));
exit(-1);
}
#endif
}
__global__ void foo(int *ptr){
*ptr = 7;
}
int main(){
foo<<<1,1>>>(0);
check_cuda_errors(__FILE__, __LINE__);
return 0;
} | .file "tmpxft_00104849_00000000-6_debug_errors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3fooPi, .-_Z3fooPi
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl $0, %edi
call _Z22__device_stub__Z3fooPiPi
jmp .L12
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
inline void check_cuda_errors(const char *filename, const int line_number){
#ifdef DEBUG
cudaThreadSynchronize();
cudaError_t error = cudaGetLastError();
if(error != cudaSuccess){
printf("CUDA error at %s:%i: %s\n", filename, line_number, cudaGetErrorString(error));
exit(-1);
}
#endif
}
__global__ void foo(int *ptr){
*ptr = 7;
}
int main(){
foo<<<1,1>>>(0);
check_cuda_errors(__FILE__, __LINE__);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
inline void check_cuda_errors(const char *filename, const int line_number){
#ifdef DEBUG
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if(error != hipSuccess){
printf("CUDA error at %s:%i: %s\n", filename, line_number, hipGetErrorString(error));
exit(-1);
}
#endif
}
__global__ void foo(int *ptr){
*ptr = 7;
}
int main(){
foo<<<1,1>>>(0);
check_cuda_errors(__FILE__, __LINE__);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
inline void check_cuda_errors(const char *filename, const int line_number){
#ifdef DEBUG
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if(error != hipSuccess){
printf("CUDA error at %s:%i: %s\n", filename, line_number, hipGetErrorString(error));
exit(-1);
}
#endif
}
__global__ void foo(int *ptr){
*ptr = 7;
}
int main(){
foo<<<1,1>>>(0);
check_cuda_errors(__FILE__, __LINE__);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 7
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
inline void check_cuda_errors(const char *filename, const int line_number){
#ifdef DEBUG
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if(error != hipSuccess){
printf("CUDA error at %s:%i: %s\n", filename, line_number, hipGetErrorString(error));
exit(-1);
}
#endif
}
__global__ void foo(int *ptr){
*ptr = 7;
}
int main(){
foo<<<1,1>>>(0);
check_cuda_errors(__FILE__, __LINE__);
return 0;
} | .text
.file "debug_errors.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq $0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3fooPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x7 ; /* 0x00000007ff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3fooPi
.globl _Z3fooPi
.p2align 8
.type _Z3fooPi,@function
_Z3fooPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 7
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3fooPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3fooPi, .Lfunc_end0-_Z3fooPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3fooPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z3fooPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00104849_00000000-6_debug_errors.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3fooPiPi
.type _Z22__device_stub__Z3fooPiPi, @function
_Z22__device_stub__Z3fooPiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3fooPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z22__device_stub__Z3fooPiPi, .-_Z22__device_stub__Z3fooPiPi
.globl _Z3fooPi
.type _Z3fooPi, @function
_Z3fooPi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3fooPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3fooPi, .-_Z3fooPi
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl $0, %edi
call _Z22__device_stub__Z3fooPiPi
jmp .L12
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3fooPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3fooPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "debug_errors.hip"
.globl _Z18__device_stub__fooPi # -- Begin function _Z18__device_stub__fooPi
.p2align 4, 0x90
.type _Z18__device_stub__fooPi,@function
_Z18__device_stub__fooPi: # @_Z18__device_stub__fooPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__fooPi, .Lfunc_end0-_Z18__device_stub__fooPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq $0, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3fooPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3fooPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3fooPi,@object # @_Z3fooPi
.section .rodata,"a",@progbits
.globl _Z3fooPi
.p2align 3, 0x0
_Z3fooPi:
.quad _Z18__device_stub__fooPi
.size _Z3fooPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3fooPi"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__fooPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3fooPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <set>
#include <algorithm>
#include <assert.h>
#include "cuda_runtime.h"
using namespace std;
#define ITERATION_FINEGRAINED (1)
#define KB (1024/sizeof(int))
#define MB (KB*1024)
#define MAX_NUM_THREADS (1024) // a block has maximal thread size
//kernel function
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help); //used to benchmark the TLB structure
__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index); //obsolete: use to attain average cycle and pages visited
void TLB_latency(int N, int stride);
void TLB_benchmarking(int beginSize, int endSize, int stride);
void generate_strided(unsigned *arr, int length, int stride);
void generate_strided_onepass(unsigned *arr, int length, int stride);
//global variables
int numThreadsGlobal;
int numBlocksGlobal;
int dataSizeGlobal; //in MB
int pageSizeGlobal; //in KB
/*
* TLB benchmarking: ./tlb_GPU pageSize_KB dataSize_begin_MB dataSize_end_MB
*
* blockSize=1 and gridSize=1 for TLB benchmarking;
*/
int main(int argc, char* argv[]){
if (argc < 4) {
cerr<<"Shall provide the blockSize, gridSize used and page size."<<endl;
cerr<<"Eg.: ./tlb_GPU bSize gSize dataSize_MB pageSize_KB"<<endl;
exit(0);
}
numThreadsGlobal = 1;
numBlocksGlobal = 1;
pageSizeGlobal = atoi(argv[1]) * KB;
int dataSize_begin = atoi(argv[2]) * MB;
int dataSize_end = atoi(argv[3]) * MB;
cudaSetDevice(0);
TLB_benchmarking(dataSize_begin, dataSize_end,pageSizeGlobal);
cudaDeviceReset();
return 0;
}
void TLB_benchmarking(int beginSize, int endSize, int stride) {
for (int ds = beginSize; ds <= endSize; ds += stride) {
cout << "Struc: Data size: " << (float)ds / MB << "MB\t" << "Stride: " << stride / MB << "MB\t";
cudaDeviceReset();
cudaError_t error_id;
unsigned *h_a, *d_a;
unsigned *h_timeinfo, *d_timeinfo;
double *help;
h_a = (unsigned*)malloc(sizeof(unsigned)*ds);
error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*ds);
if (error_id != cudaSuccess) cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
/* initialize array elements on CPU with pointers into d_a. */
generate_strided_onepass(h_a,ds,stride);
/* copy array elements from CPU to GPU */
error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*ds, cudaMemcpyHostToDevice);
if (error_id != cudaSuccess) cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
if (error_id != cudaSuccess) cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
if (error_id != cudaSuccess) cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
cudaThreadSynchronize();
/* launch kernel*/
dim3 Db = dim3(numThreadsGlobal);
dim3 Dg = dim3(numBlocksGlobal);
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, false, NULL, NULL); //warp up
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, true, d_timeinfo, help); //formal
cudaThreadSynchronize();
error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
cerr << "Error kernel is " << cudaGetErrorString(error_id) << endl;
}
/* copy results from GPU to CPU */
cudaThreadSynchronize();
error_id = cudaMemcpy((void *) h_timeinfo, (void *) d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) cerr << "Error 2.2 is " << cudaGetErrorString(error_id) << endl;
double total = 0; //here we use double, otherwise it will overflow
for (int i = 0; i < numThreadsGlobal * numBlocksGlobal; i++) {
total += h_timeinfo[i];
}
total /= (numThreadsGlobal * numBlocksGlobal);
cout << "cycle: " << total << endl;
cudaThreadSynchronize();
/* free memory on GPU */
cudaFree(help);
cudaFree(d_a);
cudaFree(d_timeinfo);
/*free memory on CPU */
free(h_a);
free(h_timeinfo);
cudaDeviceReset();
}
}
//used for TLB benchmarking
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help) {
unsigned long start, end;
unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
unsigned curIdx = 0;
double anc = 0;
double total = 0;
int myIteration = 0;
//traverse the data array once
while (curIdx < length) {
start = clock64();
curIdx = arr[curIdx];
anc += curIdx; //to ensure the curIdx has been read, this instruction is 16-cycle long on K40m
end = clock64();
total += (end-start-16);
myIteration++;
}
if (record) {
duration[gid] = (total/myIteration);
help[gid] = anc;
}
}
void generate_strided_onepass(unsigned *arr, int length, int stride) {
for (int i = 0 ; i < length; i++) {
arr[i] = i+stride;
}
}
//void measure_global() {
//
// int stride = pageSizeGlobal*KB; //2MB stride
// set<int> missPages; //recording the overall missing pages in each case
//
// //begin and end size in MBs
// /* To test the TLB structures the beginSize and endSize is different;
// * To test the latency of multi-thread, beginSize and endSize should set as the data size tested */
// int beginSize = dataSizeGlobal * MB;
// int endSize = dataSizeGlobal * MB;
//
// //1. The L1 TLB has 16 entries. Test with N_min=28 *1024*256, N_max>32*1024*256
// //2. The L2 TLB has 65 entries. Test with N_min=128*1024*256, N_max=160*1024*256
// for (int dataSize = beginSize; dataSize <= endSize; dataSize += (128*KB)) {
//// cout<<"Data size: "<<(float)dataSize/MB<<"MB\t"<<"Stride: "<< stride/MB <<"MB"<<endl;
// cout<<"Data size: "<<(float)dataSize/MB<<"MB\tbsize: "<<numThreadsGlobal<<"\tgsize: "<<numBlocksGlobal<<'\t';
// parametric_measure_global(dataSize, false, stride, missPages); //not finegrained
// }
//}
//void TLB_finegrained(int N, bool finegrained, int stride, set<int> & lastMissPages) {
// cudaDeviceReset();
// cudaError_t error_id;
// int i;
// unsigned *h_a, *d_a;
// h_a = (unsigned*)malloc(sizeof(unsigned)*N);
// error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*N);
//
// if (error_id != cudaSuccess)
// cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
//
// /* initialize array elements on CPU with pointers into d_a. */
// generate_strided(h_a,N,stride);
// //generate_strided_onepass(h_a,N,(mul)*stride);
//
// /* copy array elements from CPU to GPU */
// error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*N, cudaMemcpyHostToDevice);
// if (error_id != cudaSuccess) {
// cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// unsigned *h_index, *h_timeinfo, *d_timeinfo, *d_index;
// double *help;
//
// if (finegrained) {
// h_index = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
//
// //recording time and visited locations
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
// }
//
// error_id = cudaMalloc((void **) &d_index, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal *ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
// }
// }
// else {
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.4 is " << cudaGetErrorString(error_id) << endl;
// }
// error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.5 is " << cudaGetErrorString(error_id) << endl;
// }
// }
//
// cudaThreadSynchronize ();
// /* launch kernel*/
// dim3 Db = dim3(numThreadsGlobal);
// dim3 Dg = dim3(numBlocksGlobal);
// if (finegrained) {
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, NULL, NULL);
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, d_timeinfo, d_index);
// }
// else {
// strided_access<<<Dg, Db>>>(d_a, N, stride, false, NULL, NULL); //warp up
// strided_access<<<Dg, Db>>>(d_a, N, stride, true, d_timeinfo, help); //formal
// }
//
// cudaThreadSynchronize();
//
// error_id = cudaGetLastError();
// if (error_id != cudaSuccess) {
// cerr<<"Error kernel is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// /* copy results from GPU to CPU */
// cudaThreadSynchronize ();
//
// if (finegrained) {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.0 is "<<cudaGetErrorString(error_id)<<endl;
// }
// error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// //statistics
// int count_less_300 = 0, count_300_400 = 0, count_400_500 = 0, count_500_600 = 0, count_larger_600 = 0;
// double total = 0;
//
// int loop = 0; //how many times the array is looped
//
// set<int> curMissPages;
// for(i=0 ;i<ITERATION;i++) {
// int curPage = h_index[i]/stride;
// if ( (h_timeinfo[i] > 400) && (h_timeinfo[i] < 510)) {
// curMissPages.insert(curPage);
// }
// cout<<curPage<<'\t'<<h_index[i]<<'\t'<<h_timeinfo[i]<<endl;
//
// if (h_index[i]<stride) loop ++;
// if (h_timeinfo[i] < 300) count_less_300++;
// else if (h_timeinfo[i] < 400) count_300_400 ++;
// else if (h_timeinfo[i] < 500) count_400_500 ++;
// else if (h_timeinfo[i] < 600) count_500_600++;
// else count_larger_600++;
// total += h_timeinfo[i];
// }
// set<int> diffSet;
// set_difference(curMissPages.begin(), curMissPages.end(),lastMissPages.begin(), lastMissPages.end(), inserter(diffSet,diffSet.end()));
//
// //to check that pages missed in last dataset will be hit in this dataset
// set<int> checkSet;
// set_difference(lastMissPages.begin(), lastMissPages.end(), curMissPages.begin(), curMissPages.end(), inserter(checkSet,checkSet.end()));
// assert(checkSet.size() == 0);
//
// int totalPages = N /512 / 1024;
// cout<<"Pages: "<<totalPages<<", misses: "<<count_400_500<<", loops: "<<loop<<", new miss pages: ";
// for (set<int>::iterator it = diffSet.begin(); it != diffSet.end(); ++it) {
// cout<<*it<<' ';
// }
// cout<<endl;
//
// // lastMissPages = curMissPages;
//
// total = total / ITERATION;
// cout<<"Average: "<<total<<endl;
// // cout<<"Statistics:"<<endl;
// // cout<<"Data size: "<<N / 1024 / 256<<" MB."<<endl;
//
// // cout<<"less than 300: "<<count_less_300<<endl;
// // cout<<"300 - 400: "<<count_300_400<<endl;
// // cout<<"400 - 500: "<<count_400_500<<endl;
// // cout<<"500 - 600: "<<count_500_600<<endl;
// // cout<<"larger than 600: "<<count_larger_600<<endl;
// // cout<<"Average cycles: "<<total<<" in "<<ITERATION<<" iterations."<<endl;
// }
// else {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.2 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// double total = 0; //here we use double, otherwise it will overflow
// for(int i = 0; i < numThreadsGlobal*numBlocksGlobal; i++) {
// total += h_timeinfo[i];
// }
// total /= (numThreadsGlobal*numBlocksGlobal);
// cout<<"cycle: "<<total<<endl;
// }
// cudaThreadSynchronize();
//
// /* free memory on GPU */
// if (finegrained) {
// cudaFree(d_index);
// free(h_index);
// }
// else {
// cudaFree(help);
// }
//
// cudaFree(d_a);
// cudaFree(d_timeinfo);
//
// /*free memory on CPU */
// free(h_a);
// free(h_timeinfo);
//
// cudaDeviceReset();
//}
//obsolete: to record the page number and study the cache replacement policy
//__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index) {
//
// unsigned timestamp;
// unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
// unsigned gsize = blockDim.x * gridDim.x;
// unsigned curIdx = (blockDim.x * threadIdx.x + blockIdx.x) % length;
//
// __shared__ unsigned int s_tvalue[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
// __shared__ unsigned int s_index[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
//
// unsigned it = gid;
// while (it < ITERATION_FINEGRAINED * MAX_NUM_THREADS) {
// s_index[it] = 0;
// s_tvalue[it] = 0;
// it += gsize;
// }
// __syncthreads();
//
// it = gid;
// for (int k = 0; k < ITERATION_FINEGRAINED; k++) {
// timestamp = clock();
// curIdx = arr[curIdx];
// s_index[it]= curIdx;
// timestamp = clock() - timestamp;
// s_tvalue[it] = timestamp;
// it += ITERATION_FINEGRAINED;
// }
//
// if (record) {
// it = threadIdx.x;
// while (it < blockDim.x * ITERATION_FINEGRAINED) {
// duration[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_tvalue[it];
// index[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_index[it];
// it += blockDim.x;
// }
// }
//} | code for sm_80
Function : _Z22strided_access_onepassPjiibS_Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0040*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0050*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fd2000001ff00 */
/*0060*/ @!P0 BRA 0x1a0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0080*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0090*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*00a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*00b0*/ CS2R R10, SR_CLOCKLO ; /* 0x00000000000a7805 */
/* 0x00ffc80000015000 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fca00078e0007 */
/*00e0*/ LDG.E R0, [R6.64] ; /* 0x0000000606007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ I2F.F64.U32 R8, R0 ; /* 0x0000000000087312 */
/* 0x004e240000201800 */
/*0100*/ DADD R2, R8, R2 ; /* 0x0000000008027229 */
/* 0x00104c0000000002 */
/*0110*/ CS2R R6, SR_CLOCKLO ; /* 0x0000000000067805 */
/* 0x000fcc0000015000 */
/*0120*/ IADD3 R6, P0, P1, R6, -0x10, -R10 ; /* 0xfffffff006067810 */
/* 0x000fe2000791e80a */
/*0130*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000fffe03f */
/*0140*/ IADD3.X R7, R7, -0x1, ~R11, P0, P1 ; /* 0xffffffff07077810 */
/* 0x000fe400007e2c0b */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0160*/ I2F.F64.U64 R6, R6 ; /* 0x0000000600067312 */
/* 0x000ea40000301800 */
/*0170*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0044ce0000000004 */
/*0180*/ @!P0 BRA 0xb0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0190*/ I2F.F64 R6, UR4 ; /* 0x0000000400067d12 */
/* 0x004ea40008201c00 */
/*01a0*/ ULDC.S8 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000200 */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*01c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01d0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x005e220000001800 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*01f0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x008fca0003f2e200 */
/*0200*/ DFMA R10, R8, -R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000806 */
/*0210*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0220*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0230*/ DFMA R8, R10, -R6, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c0000000806 */
/*0240*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*0250*/ DMUL R10, R8, R4 ; /* 0x00000004080a7228 */
/* 0x001e0c0000000000 */
/*0260*/ DFMA R12, R10, -R6, R4 ; /* 0x800000060a0c722b */
/* 0x001e0c0000000004 */
/*0270*/ DFMA R8, R8, R12, R10 ; /* 0x0000000c0808722b */
/* 0x001e14000000000a */
/*0280*/ FFMA R0, RZ, R7, R9 ; /* 0x00000007ff007223 */
/* 0x001fca0000000009 */
/*0290*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*02a0*/ @P0 BRA P1, 0x310 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*02b0*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*02c0*/ MOV R0, 0x310 ; /* 0x0000031000007802 */
/* 0x000fe20000000f00 */
/*02d0*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0005 */
/*02e0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*02f0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0300*/ CALL.REL.NOINC 0x3c0 ; /* 0x000000b000007944 */
/* 0x002fea0003c00000 */
/*0310*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0320*/ F2I.U32.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */
/* 0x000ea2000030d000 */
/*0330*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*0340*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0350*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc400078e00ff */
/*0360*/ IMAD R6, R6, c[0x0][0x0], R5 ; /* 0x0000000006067a24 */
/* 0x001fc800078e0205 */
/*0370*/ IMAD.WIDE.U32 R4, R6, R11, c[0x0][0x178] ; /* 0x00005e0006047625 */
/* 0x000fc800078e000b */
/*0380*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0007 */
/*0390*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe8000c101906 */
/*03a0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x002fe2000c101b06 */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*03d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*03e0*/ LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x040fe400078ec0ff */
/*03f0*/ LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009107812 */
/* 0x000fc400078ec0ff */
/*0400*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fcc00078e0008 */
/*0420*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e0c0000000000 */
/*0430*/ MUFU.RCP64H R11, R7 ; /* 0x00000007000b7308 */
/* 0x001e240000001800 */
/*0440*/ DFMA R4, R10, -R6, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c0000000806 */
/*0450*/ DFMA R12, R4, R4, R4 ; /* 0x00000004040c722b */
/* 0x0010640000000004 */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x001fe400078e000f */
/*0470*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0480*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0490*/ LOP3.LUT R15, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050f7812 */
/* 0x000fe200078ec0ff */
/*04a0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x002e06000000000a */
/*04b0*/ ISETP.GE.U32.AND P1, PT, R15, R16, PT ; /* 0x000000100f00720c */
/* 0x000fe40003f26070 */
/*04c0*/ @!P0 LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007108812 */
/* 0x000fe200078ec0ff */
/*04d0*/ DFMA R10, R12, -R6, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e220000000806 */
/*04e0*/ SEL R17, R14, 0x63400000, !P1 ; /* 0x634000000e117807 */
/* 0x000fe40004800000 */
/*04f0*/ FSETP.GEU.AND P1, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x000fc60003f2e200 */
/*0500*/ DFMA R12, R12, R10, R12 ; /* 0x0000000a0c0c722b */
/* 0x001064000000000c */
/*0510*/ LOP3.LUT R11, R17, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff110b7812 */
/* 0x001fe200078ef805 */
/*0520*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000f */
/*0530*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0004 */
/*0540*/ @P1 BRA 0x5d0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0550*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x002fc800078ec0ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R15, R18, PT ; /* 0x000000120f00720c */
/* 0x000fe20003f06070 */
/*0570*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*0580*/ SEL R17, R14, 0x63400000, !P0 ; /* 0x634000000e117807 */
/* 0x000fc80004000000 */
/*0590*/ LOP3.LUT R17, R17, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000011117812 */
/* 0x000fc800078ef805 */
/*05a0*/ LOP3.LUT R19, R17, 0x100000, RZ, 0xfc, !PT ; /* 0x0010000011137812 */
/* 0x000fcc00078efcff */
/*05b0*/ DFMA R10, R10, 2, -R18 ; /* 0x400000000a0a782b */
/* 0x000e140000000812 */
/*05c0*/ LOP3.LUT R17, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b117812 */
/* 0x001fc800078ec0ff */
/*05d0*/ IADD3 R20, R17, -0x1, RZ ; /* 0xffffffff11147810 */
/* 0x002fe20007ffe0ff */
/*05e0*/ DMUL R18, R12, R10 ; /* 0x0000000a0c127228 */
/* 0x000e220000000000 */
/*05f0*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0600*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0610*/ DFMA R20, R18, -R6, R10 ; /* 0x800000061214722b */
/* 0x001e22000000000a */
/*0620*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0630*/ DFMA R12, R12, R20, R18 ; /* 0x000000140c0c722b */
/* 0x0010500000000012 */
/*0640*/ @P0 BRA 0x810 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0650*/ LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009107812 */
/* 0x003fc800078ec0ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R15.reuse, R16, PT ; /* 0x000000100f00720c */
/* 0x040fe20003f06070 */
/*0670*/ IMAD.IADD R4, R15, 0x1, -R16 ; /* 0x000000010f047824 */
/* 0x000fc600078e0a10 */
/*0680*/ SEL R5, R14, 0x63400000, !P0 ; /* 0x634000000e057807 */
/* 0x000fe40004000000 */
/*0690*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*06a0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*06b0*/ IMAD.IADD R16, R4, 0x1, -R5 ; /* 0x0000000104107824 */
/* 0x000fe400078e0a05 */
/*06c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*06d0*/ IADD3 R5, R16, 0x7fe00000, RZ ; /* 0x7fe0000010057810 */
/* 0x000fcc0007ffe0ff */
/*06e0*/ DMUL R14, R12, R4 ; /* 0x000000040c0e7228 */
/* 0x000e140000000000 */
/*06f0*/ FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x001fda0003f0c200 */
/*0700*/ @P0 BRA 0x960 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0710*/ DFMA R6, R12, -R6, R10 ; /* 0x800000060c06722b */
/* 0x000e22000000000a */
/*0720*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0730*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0740*/ LOP3.LUT R9, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007097812 */
/* 0x000fc800078e4809 */
/*0750*/ LOP3.LUT R5, R9, R5, RZ, 0xfc, !PT ; /* 0x0000000509057212 */
/* 0x000fce00078efcff */
/*0760*/ @!P0 BRA 0x960 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD.MOV R7, RZ, RZ, -R16 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a10 */
/*0780*/ DMUL.RP R4, R12, R4 ; /* 0x000000040c047228 */
/* 0x000e220000008000 */
/*0790*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*07a0*/ DFMA R6, R14, -R6, R12 ; /* 0x800000060e06722b */
/* 0x000e46000000000c */
/*07b0*/ LOP3.LUT R9, R5, R9, RZ, 0x3c, !PT ; /* 0x0000000905097212 */
/* 0x001fc600078e3cff */
/*07c0*/ IADD3 R6, -R16, -0x43300000, RZ ; /* 0xbcd0000010067810 */
/* 0x002fc80007ffe1ff */
/*07d0*/ FSETP.NEU.AND P0, PT, |R7|, R6, PT ; /* 0x000000060700720b */
/* 0x000fc80003f0d200 */
/*07e0*/ FSEL R14, R4, R14, !P0 ; /* 0x0000000e040e7208 */
/* 0x000fe40004000000 */
/*07f0*/ FSEL R15, R9, R15, !P0 ; /* 0x0000000f090f7208 */
/* 0x000fe20004000000 */
/*0800*/ BRA 0x960 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0810*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x003e1c0003f08000 */
/*0820*/ @P0 BRA 0x940 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0830*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0840*/ @P0 BRA 0x910 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0850*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0860*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*0870*/ IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; /* 0xfff80000ff0f7424 */
/* 0x000fd400078e00ff */
/*0880*/ @!P0 BRA 0x960 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0890*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*08a0*/ LOP3.LUT R15, R5, 0x80000000, R9, 0x48, !PT ; /* 0x80000000050f7812 */
/* 0x000fe400078e4809 */
/*08b0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*08c0*/ @P0 LOP3.LUT R4, R15, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000f040812 */
/* 0x000fe200078efcff */
/*08d0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe400078e00ff */
/*08e0*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*08f0*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, R4 ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e0004 */
/*0900*/ BRA 0x960 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0910*/ LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090f7812 */
/* 0x000fe200078efcff */
/*0920*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0930*/ BRA 0x960 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R15, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050f7812 */
/* 0x000fe200078efcff */
/*0950*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0004 */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0970*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc400078e00ff */
/*0980*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000e */
/*0990*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000f */
/*09a0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff65004007950 */
/* 0x000fec0003c3ffff */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <set>
#include <algorithm>
#include <assert.h>
#include "cuda_runtime.h"
using namespace std;
#define ITERATION_FINEGRAINED (1)
#define KB (1024/sizeof(int))
#define MB (KB*1024)
#define MAX_NUM_THREADS (1024) // a block has maximal thread size
//kernel function
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help); //used to benchmark the TLB structure
__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index); //obsolete: use to attain average cycle and pages visited
void TLB_latency(int N, int stride);
void TLB_benchmarking(int beginSize, int endSize, int stride);
void generate_strided(unsigned *arr, int length, int stride);
void generate_strided_onepass(unsigned *arr, int length, int stride);
//global variables
int numThreadsGlobal;
int numBlocksGlobal;
int dataSizeGlobal; //in MB
int pageSizeGlobal; //in KB
/*
* TLB benchmarking: ./tlb_GPU pageSize_KB dataSize_begin_MB dataSize_end_MB
*
* blockSize=1 and gridSize=1 for TLB benchmarking;
*/
int main(int argc, char* argv[]){
if (argc < 4) {
cerr<<"Shall provide the blockSize, gridSize used and page size."<<endl;
cerr<<"Eg.: ./tlb_GPU bSize gSize dataSize_MB pageSize_KB"<<endl;
exit(0);
}
numThreadsGlobal = 1;
numBlocksGlobal = 1;
pageSizeGlobal = atoi(argv[1]) * KB;
int dataSize_begin = atoi(argv[2]) * MB;
int dataSize_end = atoi(argv[3]) * MB;
cudaSetDevice(0);
TLB_benchmarking(dataSize_begin, dataSize_end,pageSizeGlobal);
cudaDeviceReset();
return 0;
}
void TLB_benchmarking(int beginSize, int endSize, int stride) {
for (int ds = beginSize; ds <= endSize; ds += stride) {
cout << "Struc: Data size: " << (float)ds / MB << "MB\t" << "Stride: " << stride / MB << "MB\t";
cudaDeviceReset();
cudaError_t error_id;
unsigned *h_a, *d_a;
unsigned *h_timeinfo, *d_timeinfo;
double *help;
h_a = (unsigned*)malloc(sizeof(unsigned)*ds);
error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*ds);
if (error_id != cudaSuccess) cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
/* initialize array elements on CPU with pointers into d_a. */
generate_strided_onepass(h_a,ds,stride);
/* copy array elements from CPU to GPU */
error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*ds, cudaMemcpyHostToDevice);
if (error_id != cudaSuccess) cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
if (error_id != cudaSuccess) cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
if (error_id != cudaSuccess) cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
cudaThreadSynchronize();
/* launch kernel*/
dim3 Db = dim3(numThreadsGlobal);
dim3 Dg = dim3(numBlocksGlobal);
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, false, NULL, NULL); //warp up
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, true, d_timeinfo, help); //formal
cudaThreadSynchronize();
error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
cerr << "Error kernel is " << cudaGetErrorString(error_id) << endl;
}
/* copy results from GPU to CPU */
cudaThreadSynchronize();
error_id = cudaMemcpy((void *) h_timeinfo, (void *) d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) cerr << "Error 2.2 is " << cudaGetErrorString(error_id) << endl;
double total = 0; //here we use double, otherwise it will overflow
for (int i = 0; i < numThreadsGlobal * numBlocksGlobal; i++) {
total += h_timeinfo[i];
}
total /= (numThreadsGlobal * numBlocksGlobal);
cout << "cycle: " << total << endl;
cudaThreadSynchronize();
/* free memory on GPU */
cudaFree(help);
cudaFree(d_a);
cudaFree(d_timeinfo);
/*free memory on CPU */
free(h_a);
free(h_timeinfo);
cudaDeviceReset();
}
}
//used for TLB benchmarking
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help) {
unsigned long start, end;
unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
unsigned curIdx = 0;
double anc = 0;
double total = 0;
int myIteration = 0;
//traverse the data array once
while (curIdx < length) {
start = clock64();
curIdx = arr[curIdx];
anc += curIdx; //to ensure the curIdx has been read, this instruction is 16-cycle long on K40m
end = clock64();
total += (end-start-16);
myIteration++;
}
if (record) {
duration[gid] = (total/myIteration);
help[gid] = anc;
}
}
void generate_strided_onepass(unsigned *arr, int length, int stride) {
for (int i = 0 ; i < length; i++) {
arr[i] = i+stride;
}
}
//void measure_global() {
//
// int stride = pageSizeGlobal*KB; //2MB stride
// set<int> missPages; //recording the overall missing pages in each case
//
// //begin and end size in MBs
// /* To test the TLB structures the beginSize and endSize is different;
// * To test the latency of multi-thread, beginSize and endSize should set as the data size tested */
// int beginSize = dataSizeGlobal * MB;
// int endSize = dataSizeGlobal * MB;
//
// //1. The L1 TLB has 16 entries. Test with N_min=28 *1024*256, N_max>32*1024*256
// //2. The L2 TLB has 65 entries. Test with N_min=128*1024*256, N_max=160*1024*256
// for (int dataSize = beginSize; dataSize <= endSize; dataSize += (128*KB)) {
//// cout<<"Data size: "<<(float)dataSize/MB<<"MB\t"<<"Stride: "<< stride/MB <<"MB"<<endl;
// cout<<"Data size: "<<(float)dataSize/MB<<"MB\tbsize: "<<numThreadsGlobal<<"\tgsize: "<<numBlocksGlobal<<'\t';
// parametric_measure_global(dataSize, false, stride, missPages); //not finegrained
// }
//}
//void TLB_finegrained(int N, bool finegrained, int stride, set<int> & lastMissPages) {
// cudaDeviceReset();
// cudaError_t error_id;
// int i;
// unsigned *h_a, *d_a;
// h_a = (unsigned*)malloc(sizeof(unsigned)*N);
// error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*N);
//
// if (error_id != cudaSuccess)
// cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
//
// /* initialize array elements on CPU with pointers into d_a. */
// generate_strided(h_a,N,stride);
// //generate_strided_onepass(h_a,N,(mul)*stride);
//
// /* copy array elements from CPU to GPU */
// error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*N, cudaMemcpyHostToDevice);
// if (error_id != cudaSuccess) {
// cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// unsigned *h_index, *h_timeinfo, *d_timeinfo, *d_index;
// double *help;
//
// if (finegrained) {
// h_index = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
//
// //recording time and visited locations
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
// }
//
// error_id = cudaMalloc((void **) &d_index, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal *ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
// }
// }
// else {
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.4 is " << cudaGetErrorString(error_id) << endl;
// }
// error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.5 is " << cudaGetErrorString(error_id) << endl;
// }
// }
//
// cudaThreadSynchronize ();
// /* launch kernel*/
// dim3 Db = dim3(numThreadsGlobal);
// dim3 Dg = dim3(numBlocksGlobal);
// if (finegrained) {
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, NULL, NULL);
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, d_timeinfo, d_index);
// }
// else {
// strided_access<<<Dg, Db>>>(d_a, N, stride, false, NULL, NULL); //warp up
// strided_access<<<Dg, Db>>>(d_a, N, stride, true, d_timeinfo, help); //formal
// }
//
// cudaThreadSynchronize();
//
// error_id = cudaGetLastError();
// if (error_id != cudaSuccess) {
// cerr<<"Error kernel is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// /* copy results from GPU to CPU */
// cudaThreadSynchronize ();
//
// if (finegrained) {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.0 is "<<cudaGetErrorString(error_id)<<endl;
// }
// error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// //statistics
// int count_less_300 = 0, count_300_400 = 0, count_400_500 = 0, count_500_600 = 0, count_larger_600 = 0;
// double total = 0;
//
// int loop = 0; //how many times the array is looped
//
// set<int> curMissPages;
// for(i=0 ;i<ITERATION;i++) {
// int curPage = h_index[i]/stride;
// if ( (h_timeinfo[i] > 400) && (h_timeinfo[i] < 510)) {
// curMissPages.insert(curPage);
// }
// cout<<curPage<<'\t'<<h_index[i]<<'\t'<<h_timeinfo[i]<<endl;
//
// if (h_index[i]<stride) loop ++;
// if (h_timeinfo[i] < 300) count_less_300++;
// else if (h_timeinfo[i] < 400) count_300_400 ++;
// else if (h_timeinfo[i] < 500) count_400_500 ++;
// else if (h_timeinfo[i] < 600) count_500_600++;
// else count_larger_600++;
// total += h_timeinfo[i];
// }
// set<int> diffSet;
// set_difference(curMissPages.begin(), curMissPages.end(),lastMissPages.begin(), lastMissPages.end(), inserter(diffSet,diffSet.end()));
//
// //to check that pages missed in last dataset will be hit in this dataset
// set<int> checkSet;
// set_difference(lastMissPages.begin(), lastMissPages.end(), curMissPages.begin(), curMissPages.end(), inserter(checkSet,checkSet.end()));
// assert(checkSet.size() == 0);
//
// int totalPages = N /512 / 1024;
// cout<<"Pages: "<<totalPages<<", misses: "<<count_400_500<<", loops: "<<loop<<", new miss pages: ";
// for (set<int>::iterator it = diffSet.begin(); it != diffSet.end(); ++it) {
// cout<<*it<<' ';
// }
// cout<<endl;
//
// // lastMissPages = curMissPages;
//
// total = total / ITERATION;
// cout<<"Average: "<<total<<endl;
// // cout<<"Statistics:"<<endl;
// // cout<<"Data size: "<<N / 1024 / 256<<" MB."<<endl;
//
// // cout<<"less than 300: "<<count_less_300<<endl;
// // cout<<"300 - 400: "<<count_300_400<<endl;
// // cout<<"400 - 500: "<<count_400_500<<endl;
// // cout<<"500 - 600: "<<count_500_600<<endl;
// // cout<<"larger than 600: "<<count_larger_600<<endl;
// // cout<<"Average cycles: "<<total<<" in "<<ITERATION<<" iterations."<<endl;
// }
// else {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.2 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// double total = 0; //here we use double, otherwise it will overflow
// for(int i = 0; i < numThreadsGlobal*numBlocksGlobal; i++) {
// total += h_timeinfo[i];
// }
// total /= (numThreadsGlobal*numBlocksGlobal);
// cout<<"cycle: "<<total<<endl;
// }
// cudaThreadSynchronize();
//
// /* free memory on GPU */
// if (finegrained) {
// cudaFree(d_index);
// free(h_index);
// }
// else {
// cudaFree(help);
// }
//
// cudaFree(d_a);
// cudaFree(d_timeinfo);
//
// /*free memory on CPU */
// free(h_a);
// free(h_timeinfo);
//
// cudaDeviceReset();
//}
//obsolete: to record the page number and study the cache replacement policy
//__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index) {
//
// unsigned timestamp;
// unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
// unsigned gsize = blockDim.x * gridDim.x;
// unsigned curIdx = (blockDim.x * threadIdx.x + blockIdx.x) % length;
//
// __shared__ unsigned int s_tvalue[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
// __shared__ unsigned int s_index[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
//
// unsigned it = gid;
// while (it < ITERATION_FINEGRAINED * MAX_NUM_THREADS) {
// s_index[it] = 0;
// s_tvalue[it] = 0;
// it += gsize;
// }
// __syncthreads();
//
// it = gid;
// for (int k = 0; k < ITERATION_FINEGRAINED; k++) {
// timestamp = clock();
// curIdx = arr[curIdx];
// s_index[it]= curIdx;
// timestamp = clock() - timestamp;
// s_tvalue[it] = timestamp;
// it += ITERATION_FINEGRAINED;
// }
//
// if (record) {
// it = threadIdx.x;
// while (it < blockDim.x * ITERATION_FINEGRAINED) {
// duration[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_tvalue[it];
// index[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_index[it];
// it += blockDim.x;
// }
// }
//} | .file "tmpxft_000f3dd2_00000000-6_tlb_benchmark.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4302:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4302:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24generate_strided_onepassPjii
.type _Z24generate_strided_onepassPjii, @function
_Z24generate_strided_onepassPjii:
.LFB4299:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movl %edx, %eax
addl %edx, %esi
.L5:
movl %eax, (%rdi)
addl $1, %eax
addq $4, %rdi
cmpl %esi, %eax
jne .L5
.L3:
ret
.cfi_endproc
.LFE4299:
.size _Z24generate_strided_onepassPjii, .-_Z24generate_strided_onepassPjii
.globl _Z49__device_stub__Z22strided_access_onepassPjiibS_PdPjiibS_Pd
.type _Z49__device_stub__Z22strided_access_onepassPjiibS_PdPjiibS_Pd, @function
_Z49__device_stub__Z22strided_access_onepassPjiibS_PdPjiibS_Pd:
.LFB4324:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movb %cl, 28(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z22strided_access_onepassPjiibS_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4324:
.size _Z49__device_stub__Z22strided_access_onepassPjiibS_PdPjiibS_Pd, .-_Z49__device_stub__Z22strided_access_onepassPjiibS_PdPjiibS_Pd
.globl _Z22strided_access_onepassPjiibS_Pd
.type _Z22strided_access_onepassPjiibS_Pd, @function
_Z22strided_access_onepassPjiibS_Pd:
.LFB4325:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %cl, %ecx
call _Z49__device_stub__Z22strided_access_onepassPjiibS_PdPjiibS_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4325:
.size _Z22strided_access_onepassPjiibS_Pd, .-_Z22strided_access_onepassPjiibS_Pd
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Struc: Data size: "
.LC3:
.string "MB\t"
.LC4:
.string "Stride: "
.LC5:
.string "Error 1.0 is "
.LC6:
.string "Error 1.1 is "
.LC7:
.string "Error 1.2 is "
.LC8:
.string "Error 1.3 is "
.LC9:
.string "Error kernel is "
.LC10:
.string "Error 2.2 is "
.LC11:
.string "cycle: "
.text
.globl _Z16TLB_benchmarkingiii
.type _Z16TLB_benchmarkingiii, @function
_Z16TLB_benchmarkingiii:
.LFB4298:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl %esi, %edi
jg .L15
movl %edi, %ebp
movl %edx, %r15d
movslq %edx, %rax
movq %rax, %rcx
shrq $18, %rcx
movq %rcx, 8(%rsp)
salq $2, %rax
movq %rax, 16(%rsp)
movslq %edi, %r13
salq $2, %r13
movl %esi, 28(%rsp)
jmp .L69
.L94:
movl $13, %edx
leaq .LC5(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L75
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L19:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L76
cmpb $0, 56(%rbx)
je .L22
movzbl 67(%rbx), %esi
.L23:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L17
.L75:
leaq _ZSt4cerr(%rip), %rdi
movq _ZSt4cerr(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L19
.L76:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L77
call _ZSt16__throw_bad_castv@PLT
.L77:
call __stack_chk_fail@PLT
.L22:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L23
.L95:
movl $13, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rbx
testq %rax, %rax
je .L78
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L26:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L79
cmpb $0, 56(%rbx)
je .L29
movzbl 67(%rbx), %esi
.L30:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L24
.L78:
leaq _ZSt4cerr(%rip), %rdi
movq _ZSt4cerr(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L26
.L79:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L80
call _ZSt16__throw_bad_castv@PLT
.L80:
call __stack_chk_fail@PLT
.L29:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L96:
movl $13, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r12
testq %rax, %rax
je .L81
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L33:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rip), %rdx
movq 240(%rdx,%rax), %r12
testq %r12, %r12
je .L82
cmpb $0, 56(%r12)
je .L36
movzbl 67(%r12), %esi
.L37:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L31
.L81:
leaq _ZSt4cerr(%rip), %rdi
movq _ZSt4cerr(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L33
.L82:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L83
call _ZSt16__throw_bad_castv@PLT
.L83:
call __stack_chk_fail@PLT
.L36:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L37
.L97:
movl $13, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r12
testq %rax, %rax
je .L84
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L40:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rip), %rdx
movq 240(%rdx,%rax), %r12
testq %r12, %r12
je .L85
cmpb $0, 56(%r12)
je .L43
movzbl 67(%r12), %esi
.L44:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L38
.L84:
leaq _ZSt4cerr(%rip), %rdi
movq _ZSt4cerr(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L40
.L85:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L86
call _ZSt16__throw_bad_castv@PLT
.L86:
call __stack_chk_fail@PLT
.L43:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L44
.L98:
movl $0, %r9d
movl $0, %r8d
movl $0, %ecx
movl %r15d, %edx
movl %ebp, %esi
movq 40(%rsp), %rdi
call _Z49__device_stub__Z22strided_access_onepassPjiibS_PdPjiibS_Pd
jmp .L45
.L99:
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movl $1, %ecx
movl %r15d, %edx
movl %ebp, %esi
movq 40(%rsp), %rdi
call _Z49__device_stub__Z22strided_access_onepassPjiibS_PdPjiibS_Pd
jmp .L46
.L100:
movl $16, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r12
testq %rax, %rax
je .L87
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L49:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rip), %rdx
movq 240(%rdx,%rax), %r12
testq %r12, %r12
je .L88
cmpb $0, 56(%r12)
je .L52
movzbl 67(%r12), %esi
.L53:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L47
.L87:
leaq _ZSt4cerr(%rip), %rdi
movq _ZSt4cerr(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L49
.L88:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L89
call _ZSt16__throw_bad_castv@PLT
.L89:
call __stack_chk_fail@PLT
.L52:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L53
.L101:
movl $13, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r12
testq %rax, %rax
je .L90
movq %rax, %rdi
call strlen@PLT
movq %rax, %rdx
movq %r12, %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L56:
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rip), %rdx
movq 240(%rdx,%rax), %r12
testq %r12, %r12
je .L91
cmpb $0, 56(%r12)
je .L59
movzbl 67(%r12), %esi
.L60:
movsbl %sil, %esi
leaq _ZSt4cerr(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L54
.L90:
leaq _ZSt4cerr(%rip), %rdi
movq _ZSt4cerr(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L56
.L91:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L92
call _ZSt16__throw_bad_castv@PLT
.L92:
call __stack_chk_fail@PLT
.L59:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L60
.L71:
pxor %xmm0, %xmm0
jmp .L61
.L102:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L93
call _ZSt16__throw_bad_castv@PLT
.L93:
call __stack_chk_fail@PLT
.L67:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L68:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
call cudaThreadSynchronize@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq (%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
addl %r15d, %ebp
movq 16(%rsp), %rax
addq %rax, %r13
cmpl %ebp, 28(%rsp)
jl .L15
.L69:
movl $18, %edx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
mulss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $3, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $8, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
movl $3, %edx
leaq .LC3(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call cudaDeviceReset@PLT
movq %r13, %rdi
call malloc@PLT
movq %rax, (%rsp)
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L94
.L17:
movl %r15d, %edx
movl %ebp, %esi
movq (%rsp), %rbx
movq %rbx, %rdi
call _Z24generate_strided_onepassPjii
movl $1, %ecx
movq %r13, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L95
.L24:
movslq numThreadsGlobal(%rip), %r12
movslq numBlocksGlobal(%rip), %rax
imulq %rax, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L96
.L31:
movslq numThreadsGlobal(%rip), %rsi
movslq numBlocksGlobal(%rip), %rax
imulq %rax, %rsi
salq $3, %rsi
leaq 56(%rsp), %rdi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L97
.L38:
call cudaThreadSynchronize@PLT
movl numThreadsGlobal(%rip), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl numBlocksGlobal(%rip), %eax
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 76(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L98
.L45:
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L99
.L46:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L100
.L47:
call cudaThreadSynchronize@PLT
movslq numThreadsGlobal(%rip), %rdx
movslq numBlocksGlobal(%rip), %rax
imulq %rax, %rdx
salq $2, %rdx
movl $2, %ecx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L101
.L54:
movl numThreadsGlobal(%rip), %esi
imull numBlocksGlobal(%rip), %esi
testl %esi, %esi
jle .L71
movq %rbx, %rax
movslq %esi, %rdx
leaq (%rbx,%rdx,4), %rcx
pxor %xmm0, %xmm0
.L64:
movl (%rax), %edx
pxor %xmm1, %xmm1
cvtsi2sdq %rdx, %xmm1
addsd %xmm1, %xmm0
addq $4, %rax
cmpq %rax, %rcx
jne .L64
.L61:
pxor %xmm1, %xmm1
cvtsi2sdl %esi, %xmm1
divsd %xmm1, %xmm0
movq %xmm0, %r12
movl $7, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .L102
cmpb $0, 56(%r14)
je .L67
movzbl 67(%r14), %esi
jmp .L68
.L15:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L103:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4298:
.size _Z16TLB_benchmarkingiii, .-_Z16TLB_benchmarkingiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC12:
.string "Shall provide the blockSize, gridSize used and page size."
.align 8
.LC13:
.string "Eg.: ./tlb_GPU bSize gSize dataSize_MB pageSize_KB"
.text
.globl main
.type main, @function
main:
.LFB4297:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
cmpl $3, %edi
jg .L105
leaq .LC12(%rip), %rsi
leaq _ZSt4cerr(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %edi
call exit@PLT
.L105:
movq %rsi, %rbx
movl $1, numThreadsGlobal(%rip)
movl $1, numBlocksGlobal(%rip)
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
sall $8, %eax
movl %eax, pageSizeGlobal(%rip)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl $0, %edi
call cudaSetDevice@PLT
movl %ebx, %esi
sall $18, %esi
movl %ebp, %edi
sall $18, %edi
movl pageSizeGlobal(%rip), %edx
call _Z16TLB_benchmarkingiii
call cudaDeviceReset@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4297:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC14:
.string "_Z22strided_access_onepassPjiibS_Pd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4327:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z22strided_access_onepassPjiibS_Pd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4327:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl pageSizeGlobal
.bss
.align 4
.type pageSizeGlobal, @object
.size pageSizeGlobal, 4
pageSizeGlobal:
.zero 4
.globl dataSizeGlobal
.align 4
.type dataSizeGlobal, @object
.size dataSizeGlobal, 4
dataSizeGlobal:
.zero 4
.globl numBlocksGlobal
.align 4
.type numBlocksGlobal, @object
.size numBlocksGlobal, 4
numBlocksGlobal:
.zero 4
.globl numThreadsGlobal
.align 4
.type numThreadsGlobal, @object
.size numThreadsGlobal, 4
numThreadsGlobal:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 914358272
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <set>
#include <algorithm>
#include <assert.h>
#include "cuda_runtime.h"
using namespace std;
#define ITERATION_FINEGRAINED (1)
#define KB (1024/sizeof(int))
#define MB (KB*1024)
#define MAX_NUM_THREADS (1024) // a block has maximal thread size
//kernel function
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help); //used to benchmark the TLB structure
__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index); //obsolete: use to attain average cycle and pages visited
void TLB_latency(int N, int stride);
void TLB_benchmarking(int beginSize, int endSize, int stride);
void generate_strided(unsigned *arr, int length, int stride);
void generate_strided_onepass(unsigned *arr, int length, int stride);
//global variables
int numThreadsGlobal;
int numBlocksGlobal;
int dataSizeGlobal; //in MB
int pageSizeGlobal; //in KB
/*
* TLB benchmarking: ./tlb_GPU pageSize_KB dataSize_begin_MB dataSize_end_MB
*
* blockSize=1 and gridSize=1 for TLB benchmarking;
*/
int main(int argc, char* argv[]){
if (argc < 4) {
cerr<<"Shall provide the blockSize, gridSize used and page size."<<endl;
cerr<<"Eg.: ./tlb_GPU bSize gSize dataSize_MB pageSize_KB"<<endl;
exit(0);
}
numThreadsGlobal = 1;
numBlocksGlobal = 1;
pageSizeGlobal = atoi(argv[1]) * KB;
int dataSize_begin = atoi(argv[2]) * MB;
int dataSize_end = atoi(argv[3]) * MB;
cudaSetDevice(0);
TLB_benchmarking(dataSize_begin, dataSize_end,pageSizeGlobal);
cudaDeviceReset();
return 0;
}
void TLB_benchmarking(int beginSize, int endSize, int stride) {
for (int ds = beginSize; ds <= endSize; ds += stride) {
cout << "Struc: Data size: " << (float)ds / MB << "MB\t" << "Stride: " << stride / MB << "MB\t";
cudaDeviceReset();
cudaError_t error_id;
unsigned *h_a, *d_a;
unsigned *h_timeinfo, *d_timeinfo;
double *help;
h_a = (unsigned*)malloc(sizeof(unsigned)*ds);
error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*ds);
if (error_id != cudaSuccess) cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
/* initialize array elements on CPU with pointers into d_a. */
generate_strided_onepass(h_a,ds,stride);
/* copy array elements from CPU to GPU */
error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*ds, cudaMemcpyHostToDevice);
if (error_id != cudaSuccess) cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
if (error_id != cudaSuccess) cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
if (error_id != cudaSuccess) cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
cudaThreadSynchronize();
/* launch kernel*/
dim3 Db = dim3(numThreadsGlobal);
dim3 Dg = dim3(numBlocksGlobal);
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, false, NULL, NULL); //warp up
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, true, d_timeinfo, help); //formal
cudaThreadSynchronize();
error_id = cudaGetLastError();
if (error_id != cudaSuccess) {
cerr << "Error kernel is " << cudaGetErrorString(error_id) << endl;
}
/* copy results from GPU to CPU */
cudaThreadSynchronize();
error_id = cudaMemcpy((void *) h_timeinfo, (void *) d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
if (error_id != cudaSuccess) cerr << "Error 2.2 is " << cudaGetErrorString(error_id) << endl;
double total = 0; //here we use double, otherwise it will overflow
for (int i = 0; i < numThreadsGlobal * numBlocksGlobal; i++) {
total += h_timeinfo[i];
}
total /= (numThreadsGlobal * numBlocksGlobal);
cout << "cycle: " << total << endl;
cudaThreadSynchronize();
/* free memory on GPU */
cudaFree(help);
cudaFree(d_a);
cudaFree(d_timeinfo);
/*free memory on CPU */
free(h_a);
free(h_timeinfo);
cudaDeviceReset();
}
}
//used for TLB benchmarking
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help) {
unsigned long start, end;
unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
unsigned curIdx = 0;
double anc = 0;
double total = 0;
int myIteration = 0;
//traverse the data array once
while (curIdx < length) {
start = clock64();
curIdx = arr[curIdx];
anc += curIdx; //to ensure the curIdx has been read, this instruction is 16-cycle long on K40m
end = clock64();
total += (end-start-16);
myIteration++;
}
if (record) {
duration[gid] = (total/myIteration);
help[gid] = anc;
}
}
void generate_strided_onepass(unsigned *arr, int length, int stride) {
for (int i = 0 ; i < length; i++) {
arr[i] = i+stride;
}
}
//void measure_global() {
//
// int stride = pageSizeGlobal*KB; //2MB stride
// set<int> missPages; //recording the overall missing pages in each case
//
// //begin and end size in MBs
// /* To test the TLB structures the beginSize and endSize is different;
// * To test the latency of multi-thread, beginSize and endSize should set as the data size tested */
// int beginSize = dataSizeGlobal * MB;
// int endSize = dataSizeGlobal * MB;
//
// //1. The L1 TLB has 16 entries. Test with N_min=28 *1024*256, N_max>32*1024*256
// //2. The L2 TLB has 65 entries. Test with N_min=128*1024*256, N_max=160*1024*256
// for (int dataSize = beginSize; dataSize <= endSize; dataSize += (128*KB)) {
//// cout<<"Data size: "<<(float)dataSize/MB<<"MB\t"<<"Stride: "<< stride/MB <<"MB"<<endl;
// cout<<"Data size: "<<(float)dataSize/MB<<"MB\tbsize: "<<numThreadsGlobal<<"\tgsize: "<<numBlocksGlobal<<'\t';
// parametric_measure_global(dataSize, false, stride, missPages); //not finegrained
// }
//}
//void TLB_finegrained(int N, bool finegrained, int stride, set<int> & lastMissPages) {
// cudaDeviceReset();
// cudaError_t error_id;
// int i;
// unsigned *h_a, *d_a;
// h_a = (unsigned*)malloc(sizeof(unsigned)*N);
// error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*N);
//
// if (error_id != cudaSuccess)
// cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
//
// /* initialize array elements on CPU with pointers into d_a. */
// generate_strided(h_a,N,stride);
// //generate_strided_onepass(h_a,N,(mul)*stride);
//
// /* copy array elements from CPU to GPU */
// error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*N, cudaMemcpyHostToDevice);
// if (error_id != cudaSuccess) {
// cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// unsigned *h_index, *h_timeinfo, *d_timeinfo, *d_index;
// double *help;
//
// if (finegrained) {
// h_index = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
//
// //recording time and visited locations
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
// }
//
// error_id = cudaMalloc((void **) &d_index, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal *ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
// }
// }
// else {
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.4 is " << cudaGetErrorString(error_id) << endl;
// }
// error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.5 is " << cudaGetErrorString(error_id) << endl;
// }
// }
//
// cudaThreadSynchronize ();
// /* launch kernel*/
// dim3 Db = dim3(numThreadsGlobal);
// dim3 Dg = dim3(numBlocksGlobal);
// if (finegrained) {
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, NULL, NULL);
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, d_timeinfo, d_index);
// }
// else {
// strided_access<<<Dg, Db>>>(d_a, N, stride, false, NULL, NULL); //warp up
// strided_access<<<Dg, Db>>>(d_a, N, stride, true, d_timeinfo, help); //formal
// }
//
// cudaThreadSynchronize();
//
// error_id = cudaGetLastError();
// if (error_id != cudaSuccess) {
// cerr<<"Error kernel is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// /* copy results from GPU to CPU */
// cudaThreadSynchronize ();
//
// if (finegrained) {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.0 is "<<cudaGetErrorString(error_id)<<endl;
// }
// error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// //statistics
// int count_less_300 = 0, count_300_400 = 0, count_400_500 = 0, count_500_600 = 0, count_larger_600 = 0;
// double total = 0;
//
// int loop = 0; //how many times the array is looped
//
// set<int> curMissPages;
// for(i=0 ;i<ITERATION;i++) {
// int curPage = h_index[i]/stride;
// if ( (h_timeinfo[i] > 400) && (h_timeinfo[i] < 510)) {
// curMissPages.insert(curPage);
// }
// cout<<curPage<<'\t'<<h_index[i]<<'\t'<<h_timeinfo[i]<<endl;
//
// if (h_index[i]<stride) loop ++;
// if (h_timeinfo[i] < 300) count_less_300++;
// else if (h_timeinfo[i] < 400) count_300_400 ++;
// else if (h_timeinfo[i] < 500) count_400_500 ++;
// else if (h_timeinfo[i] < 600) count_500_600++;
// else count_larger_600++;
// total += h_timeinfo[i];
// }
// set<int> diffSet;
// set_difference(curMissPages.begin(), curMissPages.end(),lastMissPages.begin(), lastMissPages.end(), inserter(diffSet,diffSet.end()));
//
// //to check that pages missed in last dataset will be hit in this dataset
// set<int> checkSet;
// set_difference(lastMissPages.begin(), lastMissPages.end(), curMissPages.begin(), curMissPages.end(), inserter(checkSet,checkSet.end()));
// assert(checkSet.size() == 0);
//
// int totalPages = N /512 / 1024;
// cout<<"Pages: "<<totalPages<<", misses: "<<count_400_500<<", loops: "<<loop<<", new miss pages: ";
// for (set<int>::iterator it = diffSet.begin(); it != diffSet.end(); ++it) {
// cout<<*it<<' ';
// }
// cout<<endl;
//
// // lastMissPages = curMissPages;
//
// total = total / ITERATION;
// cout<<"Average: "<<total<<endl;
// // cout<<"Statistics:"<<endl;
// // cout<<"Data size: "<<N / 1024 / 256<<" MB."<<endl;
//
// // cout<<"less than 300: "<<count_less_300<<endl;
// // cout<<"300 - 400: "<<count_300_400<<endl;
// // cout<<"400 - 500: "<<count_400_500<<endl;
// // cout<<"500 - 600: "<<count_500_600<<endl;
// // cout<<"larger than 600: "<<count_larger_600<<endl;
// // cout<<"Average cycles: "<<total<<" in "<<ITERATION<<" iterations."<<endl;
// }
// else {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.2 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// double total = 0; //here we use double, otherwise it will overflow
// for(int i = 0; i < numThreadsGlobal*numBlocksGlobal; i++) {
// total += h_timeinfo[i];
// }
// total /= (numThreadsGlobal*numBlocksGlobal);
// cout<<"cycle: "<<total<<endl;
// }
// cudaThreadSynchronize();
//
// /* free memory on GPU */
// if (finegrained) {
// cudaFree(d_index);
// free(h_index);
// }
// else {
// cudaFree(help);
// }
//
// cudaFree(d_a);
// cudaFree(d_timeinfo);
//
// /*free memory on CPU */
// free(h_a);
// free(h_timeinfo);
//
// cudaDeviceReset();
//}
//obsolete: to record the page number and study the cache replacement policy
//__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index) {
//
// unsigned timestamp;
// unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
// unsigned gsize = blockDim.x * gridDim.x;
// unsigned curIdx = (blockDim.x * threadIdx.x + blockIdx.x) % length;
//
// __shared__ unsigned int s_tvalue[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
// __shared__ unsigned int s_index[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
//
// unsigned it = gid;
// while (it < ITERATION_FINEGRAINED * MAX_NUM_THREADS) {
// s_index[it] = 0;
// s_tvalue[it] = 0;
// it += gsize;
// }
// __syncthreads();
//
// it = gid;
// for (int k = 0; k < ITERATION_FINEGRAINED; k++) {
// timestamp = clock();
// curIdx = arr[curIdx];
// s_index[it]= curIdx;
// timestamp = clock() - timestamp;
// s_tvalue[it] = timestamp;
// it += ITERATION_FINEGRAINED;
// }
//
// if (record) {
// it = threadIdx.x;
// while (it < blockDim.x * ITERATION_FINEGRAINED) {
// duration[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_tvalue[it];
// index[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_index[it];
// it += blockDim.x;
// }
// }
//} | #include <iostream>
#include <set>
#include <algorithm>
#include <assert.h>
#include "hip/hip_runtime.h"
using namespace std;
#define ITERATION_FINEGRAINED (1)
#define KB (1024/sizeof(int))
#define MB (KB*1024)
#define MAX_NUM_THREADS (1024) // a block has maximal thread size
//kernel function
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help); //used to benchmark the TLB structure
__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index); //obsolete: use to attain average cycle and pages visited
void TLB_latency(int N, int stride);
void TLB_benchmarking(int beginSize, int endSize, int stride);
void generate_strided(unsigned *arr, int length, int stride);
void generate_strided_onepass(unsigned *arr, int length, int stride);
//global variables
int numThreadsGlobal;
int numBlocksGlobal;
int dataSizeGlobal; //in MB
int pageSizeGlobal; //in KB
/*
* TLB benchmarking: ./tlb_GPU pageSize_KB dataSize_begin_MB dataSize_end_MB
*
* blockSize=1 and gridSize=1 for TLB benchmarking;
*/
int main(int argc, char* argv[]){
if (argc < 4) {
cerr<<"Shall provide the blockSize, gridSize used and page size."<<endl;
cerr<<"Eg.: ./tlb_GPU bSize gSize dataSize_MB pageSize_KB"<<endl;
exit(0);
}
numThreadsGlobal = 1;
numBlocksGlobal = 1;
pageSizeGlobal = atoi(argv[1]) * KB;
int dataSize_begin = atoi(argv[2]) * MB;
int dataSize_end = atoi(argv[3]) * MB;
hipSetDevice(0);
TLB_benchmarking(dataSize_begin, dataSize_end,pageSizeGlobal);
hipDeviceReset();
return 0;
}
void TLB_benchmarking(int beginSize, int endSize, int stride) {
for (int ds = beginSize; ds <= endSize; ds += stride) {
cout << "Struc: Data size: " << (float)ds / MB << "MB\t" << "Stride: " << stride / MB << "MB\t";
hipDeviceReset();
hipError_t error_id;
unsigned *h_a, *d_a;
unsigned *h_timeinfo, *d_timeinfo;
double *help;
h_a = (unsigned*)malloc(sizeof(unsigned)*ds);
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned)*ds);
if (error_id != hipSuccess) cerr<<"Error 1.0 is "<<hipGetErrorString(error_id)<<endl;
/* initialize array elements on CPU with pointers into d_a. */
generate_strided_onepass(h_a,ds,stride);
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned)*ds, hipMemcpyHostToDevice);
if (error_id != hipSuccess) cerr<<"Error 1.1 is "<<hipGetErrorString(error_id)<<endl;
h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
error_id = hipMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
if (error_id != hipSuccess) cerr << "Error 1.2 is " << hipGetErrorString(error_id) << endl;
error_id = hipMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
if (error_id != hipSuccess) cerr << "Error 1.3 is " << hipGetErrorString(error_id) << endl;
hipDeviceSynchronize();
/* launch kernel*/
dim3 Db = dim3(numThreadsGlobal);
dim3 Dg = dim3(numBlocksGlobal);
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, false, NULL, NULL); //warp up
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, true, d_timeinfo, help); //formal
hipDeviceSynchronize();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
cerr << "Error kernel is " << hipGetErrorString(error_id) << endl;
}
/* copy results from GPU to CPU */
hipDeviceSynchronize();
error_id = hipMemcpy((void *) h_timeinfo, (void *) d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) cerr << "Error 2.2 is " << hipGetErrorString(error_id) << endl;
double total = 0; //here we use double, otherwise it will overflow
for (int i = 0; i < numThreadsGlobal * numBlocksGlobal; i++) {
total += h_timeinfo[i];
}
total /= (numThreadsGlobal * numBlocksGlobal);
cout << "cycle: " << total << endl;
hipDeviceSynchronize();
/* free memory on GPU */
hipFree(help);
hipFree(d_a);
hipFree(d_timeinfo);
/*free memory on CPU */
free(h_a);
free(h_timeinfo);
hipDeviceReset();
}
}
//used for TLB benchmarking
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help) {
unsigned long start, end;
unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
unsigned curIdx = 0;
double anc = 0;
double total = 0;
int myIteration = 0;
//traverse the data array once
while (curIdx < length) {
start = clock64();
curIdx = arr[curIdx];
anc += curIdx; //to ensure the curIdx has been read, this instruction is 16-cycle long on K40m
end = clock64();
total += (end-start-16);
myIteration++;
}
if (record) {
duration[gid] = (total/myIteration);
help[gid] = anc;
}
}
void generate_strided_onepass(unsigned *arr, int length, int stride) {
for (int i = 0 ; i < length; i++) {
arr[i] = i+stride;
}
}
//void measure_global() {
//
// int stride = pageSizeGlobal*KB; //2MB stride
// set<int> missPages; //recording the overall missing pages in each case
//
// //begin and end size in MBs
// /* To test the TLB structures the beginSize and endSize is different;
// * To test the latency of multi-thread, beginSize and endSize should set as the data size tested */
// int beginSize = dataSizeGlobal * MB;
// int endSize = dataSizeGlobal * MB;
//
// //1. The L1 TLB has 16 entries. Test with N_min=28 *1024*256, N_max>32*1024*256
// //2. The L2 TLB has 65 entries. Test with N_min=128*1024*256, N_max=160*1024*256
// for (int dataSize = beginSize; dataSize <= endSize; dataSize += (128*KB)) {
//// cout<<"Data size: "<<(float)dataSize/MB<<"MB\t"<<"Stride: "<< stride/MB <<"MB"<<endl;
// cout<<"Data size: "<<(float)dataSize/MB<<"MB\tbsize: "<<numThreadsGlobal<<"\tgsize: "<<numBlocksGlobal<<'\t';
// parametric_measure_global(dataSize, false, stride, missPages); //not finegrained
// }
//}
//void TLB_finegrained(int N, bool finegrained, int stride, set<int> & lastMissPages) {
// cudaDeviceReset();
// cudaError_t error_id;
// int i;
// unsigned *h_a, *d_a;
// h_a = (unsigned*)malloc(sizeof(unsigned)*N);
// error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*N);
//
// if (error_id != cudaSuccess)
// cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
//
// /* initialize array elements on CPU with pointers into d_a. */
// generate_strided(h_a,N,stride);
// //generate_strided_onepass(h_a,N,(mul)*stride);
//
// /* copy array elements from CPU to GPU */
// error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*N, cudaMemcpyHostToDevice);
// if (error_id != cudaSuccess) {
// cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// unsigned *h_index, *h_timeinfo, *d_timeinfo, *d_index;
// double *help;
//
// if (finegrained) {
// h_index = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
//
// //recording time and visited locations
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
// }
//
// error_id = cudaMalloc((void **) &d_index, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal *ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
// }
// }
// else {
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.4 is " << cudaGetErrorString(error_id) << endl;
// }
// error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.5 is " << cudaGetErrorString(error_id) << endl;
// }
// }
//
// cudaThreadSynchronize ();
// /* launch kernel*/
// dim3 Db = dim3(numThreadsGlobal);
// dim3 Dg = dim3(numBlocksGlobal);
// if (finegrained) {
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, NULL, NULL);
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, d_timeinfo, d_index);
// }
// else {
// strided_access<<<Dg, Db>>>(d_a, N, stride, false, NULL, NULL); //warp up
// strided_access<<<Dg, Db>>>(d_a, N, stride, true, d_timeinfo, help); //formal
// }
//
// cudaThreadSynchronize();
//
// error_id = cudaGetLastError();
// if (error_id != cudaSuccess) {
// cerr<<"Error kernel is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// /* copy results from GPU to CPU */
// cudaThreadSynchronize ();
//
// if (finegrained) {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.0 is "<<cudaGetErrorString(error_id)<<endl;
// }
// error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// //statistics
// int count_less_300 = 0, count_300_400 = 0, count_400_500 = 0, count_500_600 = 0, count_larger_600 = 0;
// double total = 0;
//
// int loop = 0; //how many times the array is looped
//
// set<int> curMissPages;
// for(i=0 ;i<ITERATION;i++) {
// int curPage = h_index[i]/stride;
// if ( (h_timeinfo[i] > 400) && (h_timeinfo[i] < 510)) {
// curMissPages.insert(curPage);
// }
// cout<<curPage<<'\t'<<h_index[i]<<'\t'<<h_timeinfo[i]<<endl;
//
// if (h_index[i]<stride) loop ++;
// if (h_timeinfo[i] < 300) count_less_300++;
// else if (h_timeinfo[i] < 400) count_300_400 ++;
// else if (h_timeinfo[i] < 500) count_400_500 ++;
// else if (h_timeinfo[i] < 600) count_500_600++;
// else count_larger_600++;
// total += h_timeinfo[i];
// }
// set<int> diffSet;
// set_difference(curMissPages.begin(), curMissPages.end(),lastMissPages.begin(), lastMissPages.end(), inserter(diffSet,diffSet.end()));
//
// //to check that pages missed in last dataset will be hit in this dataset
// set<int> checkSet;
// set_difference(lastMissPages.begin(), lastMissPages.end(), curMissPages.begin(), curMissPages.end(), inserter(checkSet,checkSet.end()));
// assert(checkSet.size() == 0);
//
// int totalPages = N /512 / 1024;
// cout<<"Pages: "<<totalPages<<", misses: "<<count_400_500<<", loops: "<<loop<<", new miss pages: ";
// for (set<int>::iterator it = diffSet.begin(); it != diffSet.end(); ++it) {
// cout<<*it<<' ';
// }
// cout<<endl;
//
// // lastMissPages = curMissPages;
//
// total = total / ITERATION;
// cout<<"Average: "<<total<<endl;
// // cout<<"Statistics:"<<endl;
// // cout<<"Data size: "<<N / 1024 / 256<<" MB."<<endl;
//
// // cout<<"less than 300: "<<count_less_300<<endl;
// // cout<<"300 - 400: "<<count_300_400<<endl;
// // cout<<"400 - 500: "<<count_400_500<<endl;
// // cout<<"500 - 600: "<<count_500_600<<endl;
// // cout<<"larger than 600: "<<count_larger_600<<endl;
// // cout<<"Average cycles: "<<total<<" in "<<ITERATION<<" iterations."<<endl;
// }
// else {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.2 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// double total = 0; //here we use double, otherwise it will overflow
// for(int i = 0; i < numThreadsGlobal*numBlocksGlobal; i++) {
// total += h_timeinfo[i];
// }
// total /= (numThreadsGlobal*numBlocksGlobal);
// cout<<"cycle: "<<total<<endl;
// }
// cudaThreadSynchronize();
//
// /* free memory on GPU */
// if (finegrained) {
// cudaFree(d_index);
// free(h_index);
// }
// else {
// cudaFree(help);
// }
//
// cudaFree(d_a);
// cudaFree(d_timeinfo);
//
// /*free memory on CPU */
// free(h_a);
// free(h_timeinfo);
//
// cudaDeviceReset();
//}
//obsolete: to record the page number and study the cache replacement policy
//__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index) {
//
// unsigned timestamp;
// unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
// unsigned gsize = blockDim.x * gridDim.x;
// unsigned curIdx = (blockDim.x * threadIdx.x + blockIdx.x) % length;
//
// __shared__ unsigned int s_tvalue[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
// __shared__ unsigned int s_index[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
//
// unsigned it = gid;
// while (it < ITERATION_FINEGRAINED * MAX_NUM_THREADS) {
// s_index[it] = 0;
// s_tvalue[it] = 0;
// it += gsize;
// }
// __syncthreads();
//
// it = gid;
// for (int k = 0; k < ITERATION_FINEGRAINED; k++) {
// timestamp = clock();
// curIdx = arr[curIdx];
// s_index[it]= curIdx;
// timestamp = clock() - timestamp;
// s_tvalue[it] = timestamp;
// it += ITERATION_FINEGRAINED;
// }
//
// if (record) {
// it = threadIdx.x;
// while (it < blockDim.x * ITERATION_FINEGRAINED) {
// duration[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_tvalue[it];
// index[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_index[it];
// it += blockDim.x;
// }
// }
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <set>
#include <algorithm>
#include <assert.h>
#include "hip/hip_runtime.h"
using namespace std;
#define ITERATION_FINEGRAINED (1)
#define KB (1024/sizeof(int))
#define MB (KB*1024)
#define MAX_NUM_THREADS (1024) // a block has maximal thread size
//kernel function
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help); //used to benchmark the TLB structure
__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index); //obsolete: use to attain average cycle and pages visited
void TLB_latency(int N, int stride);
void TLB_benchmarking(int beginSize, int endSize, int stride);
void generate_strided(unsigned *arr, int length, int stride);
void generate_strided_onepass(unsigned *arr, int length, int stride);
//global variables
int numThreadsGlobal;
int numBlocksGlobal;
int dataSizeGlobal; //in MB
int pageSizeGlobal; //in KB
/*
* TLB benchmarking: ./tlb_GPU pageSize_KB dataSize_begin_MB dataSize_end_MB
*
* blockSize=1 and gridSize=1 for TLB benchmarking;
*/
int main(int argc, char* argv[]){
if (argc < 4) {
cerr<<"Shall provide the blockSize, gridSize used and page size."<<endl;
cerr<<"Eg.: ./tlb_GPU bSize gSize dataSize_MB pageSize_KB"<<endl;
exit(0);
}
numThreadsGlobal = 1;
numBlocksGlobal = 1;
pageSizeGlobal = atoi(argv[1]) * KB;
int dataSize_begin = atoi(argv[2]) * MB;
int dataSize_end = atoi(argv[3]) * MB;
hipSetDevice(0);
TLB_benchmarking(dataSize_begin, dataSize_end,pageSizeGlobal);
hipDeviceReset();
return 0;
}
void TLB_benchmarking(int beginSize, int endSize, int stride) {
for (int ds = beginSize; ds <= endSize; ds += stride) {
cout << "Struc: Data size: " << (float)ds / MB << "MB\t" << "Stride: " << stride / MB << "MB\t";
hipDeviceReset();
hipError_t error_id;
unsigned *h_a, *d_a;
unsigned *h_timeinfo, *d_timeinfo;
double *help;
h_a = (unsigned*)malloc(sizeof(unsigned)*ds);
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned)*ds);
if (error_id != hipSuccess) cerr<<"Error 1.0 is "<<hipGetErrorString(error_id)<<endl;
/* initialize array elements on CPU with pointers into d_a. */
generate_strided_onepass(h_a,ds,stride);
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned)*ds, hipMemcpyHostToDevice);
if (error_id != hipSuccess) cerr<<"Error 1.1 is "<<hipGetErrorString(error_id)<<endl;
h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
error_id = hipMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
if (error_id != hipSuccess) cerr << "Error 1.2 is " << hipGetErrorString(error_id) << endl;
error_id = hipMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
if (error_id != hipSuccess) cerr << "Error 1.3 is " << hipGetErrorString(error_id) << endl;
hipDeviceSynchronize();
/* launch kernel*/
dim3 Db = dim3(numThreadsGlobal);
dim3 Dg = dim3(numBlocksGlobal);
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, false, NULL, NULL); //warp up
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, true, d_timeinfo, help); //formal
hipDeviceSynchronize();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
cerr << "Error kernel is " << hipGetErrorString(error_id) << endl;
}
/* copy results from GPU to CPU */
hipDeviceSynchronize();
error_id = hipMemcpy((void *) h_timeinfo, (void *) d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) cerr << "Error 2.2 is " << hipGetErrorString(error_id) << endl;
double total = 0; //here we use double, otherwise it will overflow
for (int i = 0; i < numThreadsGlobal * numBlocksGlobal; i++) {
total += h_timeinfo[i];
}
total /= (numThreadsGlobal * numBlocksGlobal);
cout << "cycle: " << total << endl;
hipDeviceSynchronize();
/* free memory on GPU */
hipFree(help);
hipFree(d_a);
hipFree(d_timeinfo);
/*free memory on CPU */
free(h_a);
free(h_timeinfo);
hipDeviceReset();
}
}
//used for TLB benchmarking
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help) {
unsigned long start, end;
unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
unsigned curIdx = 0;
double anc = 0;
double total = 0;
int myIteration = 0;
//traverse the data array once
while (curIdx < length) {
start = clock64();
curIdx = arr[curIdx];
anc += curIdx; //to ensure the curIdx has been read, this instruction is 16-cycle long on K40m
end = clock64();
total += (end-start-16);
myIteration++;
}
if (record) {
duration[gid] = (total/myIteration);
help[gid] = anc;
}
}
void generate_strided_onepass(unsigned *arr, int length, int stride) {
for (int i = 0 ; i < length; i++) {
arr[i] = i+stride;
}
}
//void measure_global() {
//
// int stride = pageSizeGlobal*KB; //2MB stride
// set<int> missPages; //recording the overall missing pages in each case
//
// //begin and end size in MBs
// /* To test the TLB structures the beginSize and endSize is different;
// * To test the latency of multi-thread, beginSize and endSize should set as the data size tested */
// int beginSize = dataSizeGlobal * MB;
// int endSize = dataSizeGlobal * MB;
//
// //1. The L1 TLB has 16 entries. Test with N_min=28 *1024*256, N_max>32*1024*256
// //2. The L2 TLB has 65 entries. Test with N_min=128*1024*256, N_max=160*1024*256
// for (int dataSize = beginSize; dataSize <= endSize; dataSize += (128*KB)) {
//// cout<<"Data size: "<<(float)dataSize/MB<<"MB\t"<<"Stride: "<< stride/MB <<"MB"<<endl;
// cout<<"Data size: "<<(float)dataSize/MB<<"MB\tbsize: "<<numThreadsGlobal<<"\tgsize: "<<numBlocksGlobal<<'\t';
// parametric_measure_global(dataSize, false, stride, missPages); //not finegrained
// }
//}
//void TLB_finegrained(int N, bool finegrained, int stride, set<int> & lastMissPages) {
// cudaDeviceReset();
// cudaError_t error_id;
// int i;
// unsigned *h_a, *d_a;
// h_a = (unsigned*)malloc(sizeof(unsigned)*N);
// error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*N);
//
// if (error_id != cudaSuccess)
// cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
//
// /* initialize array elements on CPU with pointers into d_a. */
// generate_strided(h_a,N,stride);
// //generate_strided_onepass(h_a,N,(mul)*stride);
//
// /* copy array elements from CPU to GPU */
// error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*N, cudaMemcpyHostToDevice);
// if (error_id != cudaSuccess) {
// cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// unsigned *h_index, *h_timeinfo, *d_timeinfo, *d_index;
// double *help;
//
// if (finegrained) {
// h_index = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
//
// //recording time and visited locations
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
// }
//
// error_id = cudaMalloc((void **) &d_index, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal *ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
// }
// }
// else {
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.4 is " << cudaGetErrorString(error_id) << endl;
// }
// error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.5 is " << cudaGetErrorString(error_id) << endl;
// }
// }
//
// cudaThreadSynchronize ();
// /* launch kernel*/
// dim3 Db = dim3(numThreadsGlobal);
// dim3 Dg = dim3(numBlocksGlobal);
// if (finegrained) {
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, NULL, NULL);
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, d_timeinfo, d_index);
// }
// else {
// strided_access<<<Dg, Db>>>(d_a, N, stride, false, NULL, NULL); //warp up
// strided_access<<<Dg, Db>>>(d_a, N, stride, true, d_timeinfo, help); //formal
// }
//
// cudaThreadSynchronize();
//
// error_id = cudaGetLastError();
// if (error_id != cudaSuccess) {
// cerr<<"Error kernel is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// /* copy results from GPU to CPU */
// cudaThreadSynchronize ();
//
// if (finegrained) {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.0 is "<<cudaGetErrorString(error_id)<<endl;
// }
// error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// //statistics
// int count_less_300 = 0, count_300_400 = 0, count_400_500 = 0, count_500_600 = 0, count_larger_600 = 0;
// double total = 0;
//
// int loop = 0; //how many times the array is looped
//
// set<int> curMissPages;
// for(i=0 ;i<ITERATION;i++) {
// int curPage = h_index[i]/stride;
// if ( (h_timeinfo[i] > 400) && (h_timeinfo[i] < 510)) {
// curMissPages.insert(curPage);
// }
// cout<<curPage<<'\t'<<h_index[i]<<'\t'<<h_timeinfo[i]<<endl;
//
// if (h_index[i]<stride) loop ++;
// if (h_timeinfo[i] < 300) count_less_300++;
// else if (h_timeinfo[i] < 400) count_300_400 ++;
// else if (h_timeinfo[i] < 500) count_400_500 ++;
// else if (h_timeinfo[i] < 600) count_500_600++;
// else count_larger_600++;
// total += h_timeinfo[i];
// }
// set<int> diffSet;
// set_difference(curMissPages.begin(), curMissPages.end(),lastMissPages.begin(), lastMissPages.end(), inserter(diffSet,diffSet.end()));
//
// //to check that pages missed in last dataset will be hit in this dataset
// set<int> checkSet;
// set_difference(lastMissPages.begin(), lastMissPages.end(), curMissPages.begin(), curMissPages.end(), inserter(checkSet,checkSet.end()));
// assert(checkSet.size() == 0);
//
// int totalPages = N /512 / 1024;
// cout<<"Pages: "<<totalPages<<", misses: "<<count_400_500<<", loops: "<<loop<<", new miss pages: ";
// for (set<int>::iterator it = diffSet.begin(); it != diffSet.end(); ++it) {
// cout<<*it<<' ';
// }
// cout<<endl;
//
// // lastMissPages = curMissPages;
//
// total = total / ITERATION;
// cout<<"Average: "<<total<<endl;
// // cout<<"Statistics:"<<endl;
// // cout<<"Data size: "<<N / 1024 / 256<<" MB."<<endl;
//
// // cout<<"less than 300: "<<count_less_300<<endl;
// // cout<<"300 - 400: "<<count_300_400<<endl;
// // cout<<"400 - 500: "<<count_400_500<<endl;
// // cout<<"500 - 600: "<<count_500_600<<endl;
// // cout<<"larger than 600: "<<count_larger_600<<endl;
// // cout<<"Average cycles: "<<total<<" in "<<ITERATION<<" iterations."<<endl;
// }
// else {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.2 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// double total = 0; //here we use double, otherwise it will overflow
// for(int i = 0; i < numThreadsGlobal*numBlocksGlobal; i++) {
// total += h_timeinfo[i];
// }
// total /= (numThreadsGlobal*numBlocksGlobal);
// cout<<"cycle: "<<total<<endl;
// }
// cudaThreadSynchronize();
//
// /* free memory on GPU */
// if (finegrained) {
// cudaFree(d_index);
// free(h_index);
// }
// else {
// cudaFree(help);
// }
//
// cudaFree(d_a);
// cudaFree(d_timeinfo);
//
// /*free memory on CPU */
// free(h_a);
// free(h_timeinfo);
//
// cudaDeviceReset();
//}
//obsolete: to record the page number and study the cache replacement policy
//__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index) {
//
// unsigned timestamp;
// unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
// unsigned gsize = blockDim.x * gridDim.x;
// unsigned curIdx = (blockDim.x * threadIdx.x + blockIdx.x) % length;
//
// __shared__ unsigned int s_tvalue[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
// __shared__ unsigned int s_index[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
//
// unsigned it = gid;
// while (it < ITERATION_FINEGRAINED * MAX_NUM_THREADS) {
// s_index[it] = 0;
// s_tvalue[it] = 0;
// it += gsize;
// }
// __syncthreads();
//
// it = gid;
// for (int k = 0; k < ITERATION_FINEGRAINED; k++) {
// timestamp = clock();
// curIdx = arr[curIdx];
// s_index[it]= curIdx;
// timestamp = clock() - timestamp;
// s_tvalue[it] = timestamp;
// it += ITERATION_FINEGRAINED;
// }
//
// if (record) {
// it = threadIdx.x;
// while (it < blockDim.x * ITERATION_FINEGRAINED) {
// duration[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_tvalue[it];
// index[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_index[it];
// it += blockDim.x;
// }
// }
//} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22strided_access_onepassPjiibS_Pd
.globl _Z22strided_access_onepassPjiibS_Pd
.p2align 8
.type _Z22strided_access_onepassPjiibS_Pd,@function
_Z22strided_access_onepassPjiibS_Pd:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x34
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, 0
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, v6
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_getreg_b32 s7, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v5, v[7:8], off
s_getreg_b32 s8, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_sub_u32 s7, s8, s7
s_subb_u32 s8, 0, 0
s_add_u32 s7, s7, -16
s_addc_u32 s8, s8, -1
v_cvt_f64_u32_e32 v[9:10], s7
v_cvt_f64_u32_e32 v[7:8], s8
s_add_i32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[7:8], 32
v_add_f64 v[7:8], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[3:4], v[7:8]
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[9:10], v5
v_cmp_gt_u32_e32 vcc_lo, s5, v5
v_add_f64 v[1:2], v[1:2], v[9:10]
s_cbranch_vccnz .LBB0_2
v_cvt_f64_i32_e32 v[5:6], s6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s2, 0
s_cbranch_scc1 .LBB0_7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[3:4]
v_div_scale_f64 v[13:14], vcc_lo, v[3:4], v[5:6], v[3:4]
s_load_b128 s[0:3], s[0:1], 0x18
s_and_b32 s4, 0xffff, s4
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[3:4], v[7:8], v[5:6], v[3:4]
v_cvt_u32_f64_e32 v7, v[3:4]
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[5:6], v7, off
global_store_b64 v[3:4], v[1:2], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22strided_access_onepassPjiibS_Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22strided_access_onepassPjiibS_Pd, .Lfunc_end0-_Z22strided_access_onepassPjiibS_Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 1
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22strided_access_onepassPjiibS_Pd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22strided_access_onepassPjiibS_Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <set>
#include <algorithm>
#include <assert.h>
#include "hip/hip_runtime.h"
using namespace std;
#define ITERATION_FINEGRAINED (1)
#define KB (1024/sizeof(int))
#define MB (KB*1024)
#define MAX_NUM_THREADS (1024) // a block has maximal thread size
//kernel function
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help); //used to benchmark the TLB structure
__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index); //obsolete: use to attain average cycle and pages visited
void TLB_latency(int N, int stride);
void TLB_benchmarking(int beginSize, int endSize, int stride);
void generate_strided(unsigned *arr, int length, int stride);
void generate_strided_onepass(unsigned *arr, int length, int stride);
//global variables
int numThreadsGlobal;
int numBlocksGlobal;
int dataSizeGlobal; //in MB
int pageSizeGlobal; //in KB
/*
* TLB benchmarking: ./tlb_GPU pageSize_KB dataSize_begin_MB dataSize_end_MB
*
* blockSize=1 and gridSize=1 for TLB benchmarking;
*/
int main(int argc, char* argv[]){
if (argc < 4) {
cerr<<"Shall provide the blockSize, gridSize used and page size."<<endl;
cerr<<"Eg.: ./tlb_GPU bSize gSize dataSize_MB pageSize_KB"<<endl;
exit(0);
}
numThreadsGlobal = 1;
numBlocksGlobal = 1;
pageSizeGlobal = atoi(argv[1]) * KB;
int dataSize_begin = atoi(argv[2]) * MB;
int dataSize_end = atoi(argv[3]) * MB;
hipSetDevice(0);
TLB_benchmarking(dataSize_begin, dataSize_end,pageSizeGlobal);
hipDeviceReset();
return 0;
}
void TLB_benchmarking(int beginSize, int endSize, int stride) {
for (int ds = beginSize; ds <= endSize; ds += stride) {
cout << "Struc: Data size: " << (float)ds / MB << "MB\t" << "Stride: " << stride / MB << "MB\t";
hipDeviceReset();
hipError_t error_id;
unsigned *h_a, *d_a;
unsigned *h_timeinfo, *d_timeinfo;
double *help;
h_a = (unsigned*)malloc(sizeof(unsigned)*ds);
error_id = hipMalloc ((void **) &d_a, sizeof(unsigned)*ds);
if (error_id != hipSuccess) cerr<<"Error 1.0 is "<<hipGetErrorString(error_id)<<endl;
/* initialize array elements on CPU with pointers into d_a. */
generate_strided_onepass(h_a,ds,stride);
/* copy array elements from CPU to GPU */
error_id = hipMemcpy(d_a, h_a, sizeof(unsigned)*ds, hipMemcpyHostToDevice);
if (error_id != hipSuccess) cerr<<"Error 1.1 is "<<hipGetErrorString(error_id)<<endl;
h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
error_id = hipMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
if (error_id != hipSuccess) cerr << "Error 1.2 is " << hipGetErrorString(error_id) << endl;
error_id = hipMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
if (error_id != hipSuccess) cerr << "Error 1.3 is " << hipGetErrorString(error_id) << endl;
hipDeviceSynchronize();
/* launch kernel*/
dim3 Db = dim3(numThreadsGlobal);
dim3 Dg = dim3(numBlocksGlobal);
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, false, NULL, NULL); //warp up
strided_access_onepass<<< Dg, Db >>> (d_a, ds, stride, true, d_timeinfo, help); //formal
hipDeviceSynchronize();
error_id = hipGetLastError();
if (error_id != hipSuccess) {
cerr << "Error kernel is " << hipGetErrorString(error_id) << endl;
}
/* copy results from GPU to CPU */
hipDeviceSynchronize();
error_id = hipMemcpy((void *) h_timeinfo, (void *) d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal, hipMemcpyDeviceToHost);
if (error_id != hipSuccess) cerr << "Error 2.2 is " << hipGetErrorString(error_id) << endl;
double total = 0; //here we use double, otherwise it will overflow
for (int i = 0; i < numThreadsGlobal * numBlocksGlobal; i++) {
total += h_timeinfo[i];
}
total /= (numThreadsGlobal * numBlocksGlobal);
cout << "cycle: " << total << endl;
hipDeviceSynchronize();
/* free memory on GPU */
hipFree(help);
hipFree(d_a);
hipFree(d_timeinfo);
/*free memory on CPU */
free(h_a);
free(h_timeinfo);
hipDeviceReset();
}
}
//used for TLB benchmarking
__global__ void strided_access_onepass(unsigned *arr, int length, int stride, bool record, unsigned *duration, double *help) {
unsigned long start, end;
unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
unsigned curIdx = 0;
double anc = 0;
double total = 0;
int myIteration = 0;
//traverse the data array once
while (curIdx < length) {
start = clock64();
curIdx = arr[curIdx];
anc += curIdx; //to ensure the curIdx has been read, this instruction is 16-cycle long on K40m
end = clock64();
total += (end-start-16);
myIteration++;
}
if (record) {
duration[gid] = (total/myIteration);
help[gid] = anc;
}
}
void generate_strided_onepass(unsigned *arr, int length, int stride) {
for (int i = 0 ; i < length; i++) {
arr[i] = i+stride;
}
}
//void measure_global() {
//
// int stride = pageSizeGlobal*KB; //2MB stride
// set<int> missPages; //recording the overall missing pages in each case
//
// //begin and end size in MBs
// /* To test the TLB structures the beginSize and endSize is different;
// * To test the latency of multi-thread, beginSize and endSize should set as the data size tested */
// int beginSize = dataSizeGlobal * MB;
// int endSize = dataSizeGlobal * MB;
//
// //1. The L1 TLB has 16 entries. Test with N_min=28 *1024*256, N_max>32*1024*256
// //2. The L2 TLB has 65 entries. Test with N_min=128*1024*256, N_max=160*1024*256
// for (int dataSize = beginSize; dataSize <= endSize; dataSize += (128*KB)) {
//// cout<<"Data size: "<<(float)dataSize/MB<<"MB\t"<<"Stride: "<< stride/MB <<"MB"<<endl;
// cout<<"Data size: "<<(float)dataSize/MB<<"MB\tbsize: "<<numThreadsGlobal<<"\tgsize: "<<numBlocksGlobal<<'\t';
// parametric_measure_global(dataSize, false, stride, missPages); //not finegrained
// }
//}
//void TLB_finegrained(int N, bool finegrained, int stride, set<int> & lastMissPages) {
// cudaDeviceReset();
// cudaError_t error_id;
// int i;
// unsigned *h_a, *d_a;
// h_a = (unsigned*)malloc(sizeof(unsigned)*N);
// error_id = cudaMalloc ((void **) &d_a, sizeof(unsigned)*N);
//
// if (error_id != cudaSuccess)
// cerr<<"Error 1.0 is "<<cudaGetErrorString(error_id)<<endl;
//
// /* initialize array elements on CPU with pointers into d_a. */
// generate_strided(h_a,N,stride);
// //generate_strided_onepass(h_a,N,(mul)*stride);
//
// /* copy array elements from CPU to GPU */
// error_id = cudaMemcpy(d_a, h_a, sizeof(unsigned)*N, cudaMemcpyHostToDevice);
// if (error_id != cudaSuccess) {
// cerr<<"Error 1.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// unsigned *h_index, *h_timeinfo, *d_timeinfo, *d_index;
// double *help;
//
// if (finegrained) {
// h_index = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
//
// //recording time and visited locations
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal * ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.2 is " << cudaGetErrorString(error_id) << endl;
// }
//
// error_id = cudaMalloc((void **) &d_index, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal *ITERATION);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.3 is " << cudaGetErrorString(error_id) << endl;
// }
// }
// else {
// h_timeinfo = (unsigned *) malloc(sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// error_id = cudaMalloc((void **) &d_timeinfo, sizeof(unsigned) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.4 is " << cudaGetErrorString(error_id) << endl;
// }
// error_id = cudaMalloc((void **) &help, sizeof(double) * numThreadsGlobal * numBlocksGlobal);
// if (error_id != cudaSuccess) {
// cerr << "Error 1.5 is " << cudaGetErrorString(error_id) << endl;
// }
// }
//
// cudaThreadSynchronize ();
// /* launch kernel*/
// dim3 Db = dim3(numThreadsGlobal);
// dim3 Dg = dim3(numBlocksGlobal);
// if (finegrained) {
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, NULL, NULL);
// strided_access_finegrained<<<Dg, Db>>>(d_a, N, false, d_timeinfo, d_index);
// }
// else {
// strided_access<<<Dg, Db>>>(d_a, N, stride, false, NULL, NULL); //warp up
// strided_access<<<Dg, Db>>>(d_a, N, stride, true, d_timeinfo, help); //formal
// }
//
// cudaThreadSynchronize();
//
// error_id = cudaGetLastError();
// if (error_id != cudaSuccess) {
// cerr<<"Error kernel is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// /* copy results from GPU to CPU */
// cudaThreadSynchronize ();
//
// if (finegrained) {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.0 is "<<cudaGetErrorString(error_id)<<endl;
// }
// error_id = cudaMemcpy((void *)h_index, (void *)d_index, sizeof(unsigned)*ITERATION*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.1 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// //statistics
// int count_less_300 = 0, count_300_400 = 0, count_400_500 = 0, count_500_600 = 0, count_larger_600 = 0;
// double total = 0;
//
// int loop = 0; //how many times the array is looped
//
// set<int> curMissPages;
// for(i=0 ;i<ITERATION;i++) {
// int curPage = h_index[i]/stride;
// if ( (h_timeinfo[i] > 400) && (h_timeinfo[i] < 510)) {
// curMissPages.insert(curPage);
// }
// cout<<curPage<<'\t'<<h_index[i]<<'\t'<<h_timeinfo[i]<<endl;
//
// if (h_index[i]<stride) loop ++;
// if (h_timeinfo[i] < 300) count_less_300++;
// else if (h_timeinfo[i] < 400) count_300_400 ++;
// else if (h_timeinfo[i] < 500) count_400_500 ++;
// else if (h_timeinfo[i] < 600) count_500_600++;
// else count_larger_600++;
// total += h_timeinfo[i];
// }
// set<int> diffSet;
// set_difference(curMissPages.begin(), curMissPages.end(),lastMissPages.begin(), lastMissPages.end(), inserter(diffSet,diffSet.end()));
//
// //to check that pages missed in last dataset will be hit in this dataset
// set<int> checkSet;
// set_difference(lastMissPages.begin(), lastMissPages.end(), curMissPages.begin(), curMissPages.end(), inserter(checkSet,checkSet.end()));
// assert(checkSet.size() == 0);
//
// int totalPages = N /512 / 1024;
// cout<<"Pages: "<<totalPages<<", misses: "<<count_400_500<<", loops: "<<loop<<", new miss pages: ";
// for (set<int>::iterator it = diffSet.begin(); it != diffSet.end(); ++it) {
// cout<<*it<<' ';
// }
// cout<<endl;
//
// // lastMissPages = curMissPages;
//
// total = total / ITERATION;
// cout<<"Average: "<<total<<endl;
// // cout<<"Statistics:"<<endl;
// // cout<<"Data size: "<<N / 1024 / 256<<" MB."<<endl;
//
// // cout<<"less than 300: "<<count_less_300<<endl;
// // cout<<"300 - 400: "<<count_300_400<<endl;
// // cout<<"400 - 500: "<<count_400_500<<endl;
// // cout<<"500 - 600: "<<count_500_600<<endl;
// // cout<<"larger than 600: "<<count_larger_600<<endl;
// // cout<<"Average cycles: "<<total<<" in "<<ITERATION<<" iterations."<<endl;
// }
// else {
// error_id = cudaMemcpy((void *)h_timeinfo, (void *)d_timeinfo, sizeof(unsigned)*numThreadsGlobal * numBlocksGlobal, cudaMemcpyDeviceToHost);
// if (error_id != cudaSuccess) {
// cerr<<"Error 2.2 is "<<cudaGetErrorString(error_id)<<endl;
// }
//
// double total = 0; //here we use double, otherwise it will overflow
// for(int i = 0; i < numThreadsGlobal*numBlocksGlobal; i++) {
// total += h_timeinfo[i];
// }
// total /= (numThreadsGlobal*numBlocksGlobal);
// cout<<"cycle: "<<total<<endl;
// }
// cudaThreadSynchronize();
//
// /* free memory on GPU */
// if (finegrained) {
// cudaFree(d_index);
// free(h_index);
// }
// else {
// cudaFree(help);
// }
//
// cudaFree(d_a);
// cudaFree(d_timeinfo);
//
// /*free memory on CPU */
// free(h_a);
// free(h_timeinfo);
//
// cudaDeviceReset();
//}
//obsolete: to record the page number and study the cache replacement policy
//__global__ void strided_access_finegrained(unsigned *arr, int length, bool record, unsigned *duration, unsigned *index) {
//
// unsigned timestamp;
// unsigned gid = blockDim.x * blockIdx.x + threadIdx.x;
// unsigned gsize = blockDim.x * gridDim.x;
// unsigned curIdx = (blockDim.x * threadIdx.x + blockIdx.x) % length;
//
// __shared__ unsigned int s_tvalue[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
// __shared__ unsigned int s_index[ITERATION_FINEGRAINED*MAX_NUM_THREADS];
//
// unsigned it = gid;
// while (it < ITERATION_FINEGRAINED * MAX_NUM_THREADS) {
// s_index[it] = 0;
// s_tvalue[it] = 0;
// it += gsize;
// }
// __syncthreads();
//
// it = gid;
// for (int k = 0; k < ITERATION_FINEGRAINED; k++) {
// timestamp = clock();
// curIdx = arr[curIdx];
// s_index[it]= curIdx;
// timestamp = clock() - timestamp;
// s_tvalue[it] = timestamp;
// it += ITERATION_FINEGRAINED;
// }
//
// if (record) {
// it = threadIdx.x;
// while (it < blockDim.x * ITERATION_FINEGRAINED) {
// duration[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_tvalue[it];
// index[it + blockIdx.x*blockDim.x*ITERATION_FINEGRAINED] = s_index[it];
// it += blockDim.x;
// }
// }
//} | .text
.file "tlb_benchmark.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
cmpl $3, %edi
jle .LBB0_2
# %bb.1:
movq %rsi, %rbx
movl $1, numThreadsGlobal(%rip)
movl $1, numBlocksGlobal(%rip)
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
shll $8, %eax
movl %eax, pageSizeGlobal(%rip)
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
shll $18, %r14d
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
shll $18, %ebx
xorl %edi, %edi
callq hipSetDevice
movl pageSizeGlobal(%rip), %edx
movl %r14d, %edi
movl %ebx, %esi
callq _Z16TLB_benchmarkingiii
callq hipDeviceReset
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $_ZSt4cerr, %edi
movl $.L.str.1, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z16TLB_benchmarkingiii
.LCPI1_0:
.long 0x36800000 # float 3.81469727E-6
.text
.globl _Z16TLB_benchmarkingiii
.p2align 4, 0x90
.type _Z16TLB_benchmarkingiii,@function
_Z16TLB_benchmarkingiii: # @_Z16TLB_benchmarkingiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, 4(%rsp) # 4-byte Spill
cmpl %esi, %edi
jle .LBB1_1
.LBB1_70: # %._crit_edge134
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1: # %.lr.ph133
.cfi_def_cfa_offset 256
movslq 4(%rsp), %rax # 4-byte Folded Reload
movq %rax, %rcx
shrq $18, %rcx
movq %rcx, 184(%rsp) # 8-byte Spill
movslq %edi, %rbx
movslq %esi, %rcx
movq %rcx, 168(%rsp) # 8-byte Spill
movq %rax, 176(%rsp) # 8-byte Spill
movl %eax, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_68: # in Loop: Header=BB1_2 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_69: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit115
# in Loop: Header=BB1_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq hipDeviceSynchronize
movq 104(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq %rbp, %rdi
callq free
movq %r15, %rdi
callq free
callq hipDeviceReset
addq 176(%rsp), %rbx # 8-byte Folded Reload
cmpq 168(%rsp), %rbx # 8-byte Folded Reload
jg .LBB1_70
.LBB1_2: # =>This Loop Header: Depth=1
# Child Loop BB1_13 Depth 2
# Child Loop BB1_72 Depth 2
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
mulss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.4, %esi
movl $8, %edx
movq %r15, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
movq 184(%rsp), %rsi # 8-byte Reload
callq _ZNSo9_M_insertImEERSoT_
movl $.L.str.3, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq hipDeviceReset
leaq (,%rbx,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbp
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_11
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movl %eax, %r12d
movl $_ZSt4cerr, %edi
movl $.L.str.5, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r12d, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_4
# %bb.5: # in Loop: Header=BB1_2 Depth=1
movq %rax, %rdi
movq %rax, %r12
callq strlen
movl $_ZSt4cerr, %edi
movq %r12, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_73
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r12)
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_11: # in Loop: Header=BB1_2 Depth=1
testq %rbx, %rbx
jle .LBB1_14
# %bb.12: # %.lr.ph.i.preheader
# in Loop: Header=BB1_2 Depth=1
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_13: # %.lr.ph.i
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%r14,%rax), %ecx
movl %ecx, (%rbp,%rax,4)
incq %rax
cmpq %rax, %rbx
jne .LBB1_13
.LBB1_14: # %_Z24generate_strided_onepassPjii.exit
# in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_23
# %bb.15: # in Loop: Header=BB1_2 Depth=1
movl %eax, %r15d
movl $_ZSt4cerr, %edi
movl $.L.str.6, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r15d, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_16
# %bb.17: # in Loop: Header=BB1_2 Depth=1
movq %rax, %rdi
movq %rax, %r15
callq strlen
movl $_ZSt4cerr, %edi
movq %r15, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_18
.p2align 4, 0x90
.LBB1_16: # in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_18: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit71
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r15
testq %r15, %r15
je .LBB1_73
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i87
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_21
# %bb.20: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_22
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit90
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_23: # in Loop: Header=BB1_2 Depth=1
movslq numThreadsGlobal(%rip), %rax
movslq numBlocksGlobal(%rip), %r12
imulq %rax, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
testl %eax, %eax
je .LBB1_32
# %bb.24: # in Loop: Header=BB1_2 Depth=1
movl %eax, %r12d
movl $_ZSt4cerr, %edi
movl $.L.str.7, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r12d, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_25
# %bb.26: # in Loop: Header=BB1_2 Depth=1
movq %rax, %rdi
movq %rax, %r12
callq strlen
movl $_ZSt4cerr, %edi
movq %r12, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_27
.p2align 4, 0x90
.LBB1_25: # in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_27: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit73
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_73
# %bb.28: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i92
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r12)
je .LBB1_30
# %bb.29: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_31
.p2align 4, 0x90
.LBB1_30: # in Loop: Header=BB1_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_31: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit95
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_32: # in Loop: Header=BB1_2 Depth=1
movslq numThreadsGlobal(%rip), %rax
movslq numBlocksGlobal(%rip), %rsi
imulq %rax, %rsi
shlq $3, %rsi
leaq 104(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB1_41
# %bb.33: # in Loop: Header=BB1_2 Depth=1
movl %eax, %r12d
movl $_ZSt4cerr, %edi
movl $.L.str.8, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r12d, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_34
# %bb.35: # in Loop: Header=BB1_2 Depth=1
movq %rax, %rdi
movq %rax, %r12
callq strlen
movl $_ZSt4cerr, %edi
movq %r12, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_36
.p2align 4, 0x90
.LBB1_34: # in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_36: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit75
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_73
# %bb.37: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i97
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r12)
je .LBB1_39
# %bb.38: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_40
.p2align 4, 0x90
.LBB1_39: # in Loop: Header=BB1_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_40: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit100
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_41: # in Loop: Header=BB1_2 Depth=1
callq hipDeviceSynchronize
movl numThreadsGlobal(%rip), %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movl numBlocksGlobal(%rip), %r13d
orq %rax, %r13
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_43
# %bb.42: # in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %rax
movq %rax, 96(%rsp)
movl %ebx, 12(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movb $0, 3(%rsp)
movq $0, 88(%rsp)
movq $0, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 3(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z22strided_access_onepassPjiibS_Pd, %edi
leaq 112(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_43: # in Loop: Header=BB1_2 Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_45
# %bb.44: # in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq 104(%rsp), %rdx
movq %rax, 96(%rsp)
movl %ebx, 12(%rsp)
movl 4(%rsp), %eax # 4-byte Reload
movl %eax, 8(%rsp)
movb $1, 3(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 3(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z22strided_access_onepassPjiibS_Pd, %edi
leaq 112(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_45: # in Loop: Header=BB1_2 Depth=1
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_54
# %bb.46: # in Loop: Header=BB1_2 Depth=1
movl %eax, %r12d
movl $_ZSt4cerr, %edi
movl $.L.str.9, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r12d, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_47
# %bb.48: # in Loop: Header=BB1_2 Depth=1
movq %rax, %rdi
movq %rax, %r12
callq strlen
movl $_ZSt4cerr, %edi
movq %r12, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_49
.p2align 4, 0x90
.LBB1_47: # in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit83
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_73
# %bb.50: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i102
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r12)
je .LBB1_52
# %bb.51: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_53
.p2align 4, 0x90
.LBB1_52: # in Loop: Header=BB1_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_53: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit105
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_54: # in Loop: Header=BB1_2 Depth=1
callq hipDeviceSynchronize
movq 24(%rsp), %rsi
movslq numThreadsGlobal(%rip), %rax
movslq numBlocksGlobal(%rip), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_63
# %bb.55: # in Loop: Header=BB1_2 Depth=1
movl %eax, %r12d
movl $_ZSt4cerr, %edi
movl $.L.str.10, %esi
movl $13, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl %r12d, %edi
callq hipGetErrorString
testq %rax, %rax
je .LBB1_56
# %bb.57: # in Loop: Header=BB1_2 Depth=1
movq %rax, %rdi
movq %rax, %r12
callq strlen
movl $_ZSt4cerr, %edi
movq %r12, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_58
.p2align 4, 0x90
.LBB1_56: # in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cerr(%rax), %rdi
movl _ZSt4cerr+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_58: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit85
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cerr(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cerr+240(%rax), %r12
testq %r12, %r12
je .LBB1_73
# %bb.59: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i107
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r12)
je .LBB1_61
# %bb.60: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_62
.p2align 4, 0x90
.LBB1_61: # in Loop: Header=BB1_2 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_62: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit110
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cerr, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_63: # in Loop: Header=BB1_2 Depth=1
movl numBlocksGlobal(%rip), %eax
imull numThreadsGlobal(%rip), %eax
testl %eax, %eax
jle .LBB1_64
# %bb.71: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movl %eax, %ecx
xorpd %xmm1, %xmm1
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_72: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%rdx,4), %esi
xorps %xmm0, %xmm0
cvtsi2sd %rsi, %xmm0
addsd %xmm0, %xmm1
incq %rdx
cmpq %rdx, %rcx
jne .LBB1_72
jmp .LBB1_65
.p2align 4, 0x90
.LBB1_64: # in Loop: Header=BB1_2 Depth=1
xorpd %xmm1, %xmm1
.LBB1_65: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
divsd %xmm0, %xmm1
movsd %xmm1, 192(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.11, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_73
# %bb.66: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i112
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r12)
je .LBB1_68
# %bb.67: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_69
.LBB1_73:
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z16TLB_benchmarkingiii, .Lfunc_end1-_Z16TLB_benchmarkingiii
.cfi_endproc
# -- End function
.globl _Z24generate_strided_onepassPjii # -- Begin function _Z24generate_strided_onepassPjii
.p2align 4, 0x90
.type _Z24generate_strided_onepassPjii,@function
_Z24generate_strided_onepassPjii: # @_Z24generate_strided_onepassPjii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
movl %edx, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal (%rcx,%rdx), %esi
movl %esi, (%rdi,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z24generate_strided_onepassPjii, .Lfunc_end2-_Z24generate_strided_onepassPjii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__strided_access_onepassPjiibS_Pd # -- Begin function _Z37__device_stub__strided_access_onepassPjiibS_Pd
.p2align 4, 0x90
.type _Z37__device_stub__strided_access_onepassPjiibS_Pd,@function
_Z37__device_stub__strided_access_onepassPjiibS_Pd: # @_Z37__device_stub__strided_access_onepassPjiibS_Pd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movb %cl, 15(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 15(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z22strided_access_onepassPjiibS_Pd, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z37__device_stub__strided_access_onepassPjiibS_Pd, .Lfunc_end3-_Z37__device_stub__strided_access_onepassPjiibS_Pd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22strided_access_onepassPjiibS_Pd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type numThreadsGlobal,@object # @numThreadsGlobal
.bss
.globl numThreadsGlobal
.p2align 2, 0x0
numThreadsGlobal:
.long 0 # 0x0
.size numThreadsGlobal, 4
.type numBlocksGlobal,@object # @numBlocksGlobal
.globl numBlocksGlobal
.p2align 2, 0x0
numBlocksGlobal:
.long 0 # 0x0
.size numBlocksGlobal, 4
.type dataSizeGlobal,@object # @dataSizeGlobal
.globl dataSizeGlobal
.p2align 2, 0x0
dataSizeGlobal:
.long 0 # 0x0
.size dataSizeGlobal, 4
.type pageSizeGlobal,@object # @pageSizeGlobal
.globl pageSizeGlobal
.p2align 2, 0x0
pageSizeGlobal:
.long 0 # 0x0
.size pageSizeGlobal, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Shall provide the blockSize, gridSize used and page size."
.size .L.str, 58
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Eg.: ./tlb_GPU bSize gSize dataSize_MB pageSize_KB"
.size .L.str.1, 51
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Struc: Data size: "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "MB\t"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Stride: "
.size .L.str.4, 9
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error 1.0 is "
.size .L.str.5, 14
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error 1.1 is "
.size .L.str.6, 14
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error 1.2 is "
.size .L.str.7, 14
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error 1.3 is "
.size .L.str.8, 14
.type _Z22strided_access_onepassPjiibS_Pd,@object # @_Z22strided_access_onepassPjiibS_Pd
.section .rodata,"a",@progbits
.globl _Z22strided_access_onepassPjiibS_Pd
.p2align 3, 0x0
_Z22strided_access_onepassPjiibS_Pd:
.quad _Z37__device_stub__strided_access_onepassPjiibS_Pd
.size _Z22strided_access_onepassPjiibS_Pd, 8
.type .L.str.9,@object # @.str.9
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.9:
.asciz "Error kernel is "
.size .L.str.9, 17
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Error 2.2 is "
.size .L.str.10, 14
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "cycle: "
.size .L.str.11, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22strided_access_onepassPjiibS_Pd"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__strided_access_onepassPjiibS_Pd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym _Z22strided_access_onepassPjiibS_Pd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22strided_access_onepassPjiibS_Pd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe20003f05270 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0040*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0050*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fd2000001ff00 */
/*0060*/ @!P0 BRA 0x1a0 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0080*/ CS2R R4, SRZ ; /* 0x0000000000047805 */
/* 0x000fe2000001ff00 */
/*0090*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*00a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*00b0*/ CS2R R10, SR_CLOCKLO ; /* 0x00000000000a7805 */
/* 0x00ffc80000015000 */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc800078e00ff */
/*00d0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fca00078e0007 */
/*00e0*/ LDG.E R0, [R6.64] ; /* 0x0000000606007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ I2F.F64.U32 R8, R0 ; /* 0x0000000000087312 */
/* 0x004e240000201800 */
/*0100*/ DADD R2, R8, R2 ; /* 0x0000000008027229 */
/* 0x00104c0000000002 */
/*0110*/ CS2R R6, SR_CLOCKLO ; /* 0x0000000000067805 */
/* 0x000fcc0000015000 */
/*0120*/ IADD3 R6, P0, P1, R6, -0x10, -R10 ; /* 0xfffffff006067810 */
/* 0x000fe2000791e80a */
/*0130*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fc6000fffe03f */
/*0140*/ IADD3.X R7, R7, -0x1, ~R11, P0, P1 ; /* 0xffffffff07077810 */
/* 0x000fe400007e2c0b */
/*0150*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0160*/ I2F.F64.U64 R6, R6 ; /* 0x0000000600067312 */
/* 0x000ea40000301800 */
/*0170*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x0044ce0000000004 */
/*0180*/ @!P0 BRA 0xb0 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0190*/ I2F.F64 R6, UR4 ; /* 0x0000000400067d12 */
/* 0x004ea40008201c00 */
/*01a0*/ ULDC.S8 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000200 */
/*01b0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05270 */
/*01c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01d0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x005e220000001800 */
/*01e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*01f0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x008fca0003f2e200 */
/*0200*/ DFMA R10, R8, -R6, 1 ; /* 0x3ff00000080a742b */
/* 0x001e0c0000000806 */
/*0210*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0220*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0230*/ DFMA R8, R10, -R6, 1 ; /* 0x3ff000000a08742b */
/* 0x001e0c0000000806 */
/*0240*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*0250*/ DMUL R10, R8, R4 ; /* 0x00000004080a7228 */
/* 0x001e0c0000000000 */
/*0260*/ DFMA R12, R10, -R6, R4 ; /* 0x800000060a0c722b */
/* 0x001e0c0000000004 */
/*0270*/ DFMA R8, R8, R12, R10 ; /* 0x0000000c0808722b */
/* 0x001e14000000000a */
/*0280*/ FFMA R0, RZ, R7, R9 ; /* 0x00000007ff007223 */
/* 0x001fca0000000009 */
/*0290*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*02a0*/ @P0 BRA P1, 0x310 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*02b0*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0004 */
/*02c0*/ MOV R0, 0x310 ; /* 0x0000031000007802 */
/* 0x000fe20000000f00 */
/*02d0*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0005 */
/*02e0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*02f0*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*0300*/ CALL.REL.NOINC 0x3c0 ; /* 0x000000b000007944 */
/* 0x002fea0003c00000 */
/*0310*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0320*/ F2I.U32.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */
/* 0x000ea2000030d000 */
/*0330*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe400078e00ff */
/*0340*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0350*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fc400078e00ff */
/*0360*/ IMAD R6, R6, c[0x0][0x0], R5 ; /* 0x0000000006067a24 */
/* 0x001fc800078e0205 */
/*0370*/ IMAD.WIDE.U32 R4, R6, R11, c[0x0][0x178] ; /* 0x00005e0006047625 */
/* 0x000fc800078e000b */
/*0380*/ IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fe200078e0007 */
/*0390*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe8000c101906 */
/*03a0*/ STG.E.64 [R6.64], R2 ; /* 0x0000000206007986 */
/* 0x002fe2000c101b06 */
/*03b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03c0*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*03d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*03e0*/ LOP3.LUT R6, R9.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x040fe400078ec0ff */
/*03f0*/ LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009107812 */
/* 0x000fc400078ec0ff */
/*0400*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0410*/ IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff067224 */
/* 0x000fcc00078e0008 */
/*0420*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e0c0000000000 */
/*0430*/ MUFU.RCP64H R11, R7 ; /* 0x00000007000b7308 */
/* 0x001e240000001800 */
/*0440*/ DFMA R4, R10, -R6, 1 ; /* 0x3ff000000a04742b */
/* 0x001e0c0000000806 */
/*0450*/ DFMA R12, R4, R4, R4 ; /* 0x00000004040c722b */
/* 0x0010640000000004 */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x001fe400078e000f */
/*0470*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000e */
/*0480*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0e7424 */
/* 0x000fe200078e00ff */
/*0490*/ LOP3.LUT R15, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050f7812 */
/* 0x000fe200078ec0ff */
/*04a0*/ DFMA R12, R10, R12, R10 ; /* 0x0000000c0a0c722b */
/* 0x002e06000000000a */
/*04b0*/ ISETP.GE.U32.AND P1, PT, R15, R16, PT ; /* 0x000000100f00720c */
/* 0x000fe40003f26070 */
/*04c0*/ @!P0 LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007108812 */
/* 0x000fe200078ec0ff */
/*04d0*/ DFMA R10, R12, -R6, 1 ; /* 0x3ff000000c0a742b */
/* 0x001e220000000806 */
/*04e0*/ SEL R17, R14, 0x63400000, !P1 ; /* 0x634000000e117807 */
/* 0x000fe40004800000 */
/*04f0*/ FSETP.GEU.AND P1, PT, |R5|, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x000fc60003f2e200 */
/*0500*/ DFMA R12, R12, R10, R12 ; /* 0x0000000a0c0c722b */
/* 0x001064000000000c */
/*0510*/ LOP3.LUT R11, R17, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff110b7812 */
/* 0x001fe200078ef805 */
/*0520*/ IMAD.MOV.U32 R17, RZ, RZ, R15 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000f */
/*0530*/ IMAD.MOV.U32 R10, RZ, RZ, R4 ; /* 0x000000ffff0a7224 */
/* 0x000fca00078e0004 */
/*0540*/ @P1 BRA 0x5d0 ; /* 0x0000008000001947 */
/* 0x000fea0003800000 */
/*0550*/ LOP3.LUT R18, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009127812 */
/* 0x002fc800078ec0ff */
/*0560*/ ISETP.GE.U32.AND P0, PT, R15, R18, PT ; /* 0x000000120f00720c */
/* 0x000fe20003f06070 */
/*0570*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fc600078e00ff */
/*0580*/ SEL R17, R14, 0x63400000, !P0 ; /* 0x634000000e117807 */
/* 0x000fc80004000000 */
/*0590*/ LOP3.LUT R17, R17, 0x80000000, R5, 0xf8, !PT ; /* 0x8000000011117812 */
/* 0x000fc800078ef805 */
/*05a0*/ LOP3.LUT R19, R17, 0x100000, RZ, 0xfc, !PT ; /* 0x0010000011137812 */
/* 0x000fcc00078efcff */
/*05b0*/ DFMA R10, R10, 2, -R18 ; /* 0x400000000a0a782b */
/* 0x000e140000000812 */
/*05c0*/ LOP3.LUT R17, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b117812 */
/* 0x001fc800078ec0ff */
/*05d0*/ IADD3 R20, R17, -0x1, RZ ; /* 0xffffffff11147810 */
/* 0x002fe20007ffe0ff */
/*05e0*/ DMUL R18, R12, R10 ; /* 0x0000000a0c127228 */
/* 0x000e220000000000 */
/*05f0*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0600*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc60003f04070 */
/*0610*/ DFMA R20, R18, -R6, R10 ; /* 0x800000061214722b */
/* 0x001e22000000000a */
/*0620*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0630*/ DFMA R12, R12, R20, R18 ; /* 0x000000140c0c722b */
/* 0x0010500000000012 */
/*0640*/ @P0 BRA 0x810 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0650*/ LOP3.LUT R16, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009107812 */
/* 0x003fc800078ec0ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R15.reuse, R16, PT ; /* 0x000000100f00720c */
/* 0x040fe20003f06070 */
/*0670*/ IMAD.IADD R4, R15, 0x1, -R16 ; /* 0x000000010f047824 */
/* 0x000fc600078e0a10 */
/*0680*/ SEL R5, R14, 0x63400000, !P0 ; /* 0x634000000e057807 */
/* 0x000fe40004000000 */
/*0690*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*06a0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*06b0*/ IMAD.IADD R16, R4, 0x1, -R5 ; /* 0x0000000104107824 */
/* 0x000fe400078e0a05 */
/*06c0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*06d0*/ IADD3 R5, R16, 0x7fe00000, RZ ; /* 0x7fe0000010057810 */
/* 0x000fcc0007ffe0ff */
/*06e0*/ DMUL R14, R12, R4 ; /* 0x000000040c0e7228 */
/* 0x000e140000000000 */
/*06f0*/ FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x001fda0003f0c200 */
/*0700*/ @P0 BRA 0x960 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0710*/ DFMA R6, R12, -R6, R10 ; /* 0x800000060c06722b */
/* 0x000e22000000000a */
/*0720*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0730*/ FSETP.NEU.AND P0, PT, R7.reuse, RZ, PT ; /* 0x000000ff0700720b */
/* 0x041fe40003f0d000 */
/*0740*/ LOP3.LUT R9, R7, 0x80000000, R9, 0x48, !PT ; /* 0x8000000007097812 */
/* 0x000fc800078e4809 */
/*0750*/ LOP3.LUT R5, R9, R5, RZ, 0xfc, !PT ; /* 0x0000000509057212 */
/* 0x000fce00078efcff */
/*0760*/ @!P0 BRA 0x960 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0770*/ IMAD.MOV R7, RZ, RZ, -R16 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a10 */
/*0780*/ DMUL.RP R4, R12, R4 ; /* 0x000000040c047228 */
/* 0x000e220000008000 */
/*0790*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fcc00078e00ff */
/*07a0*/ DFMA R6, R14, -R6, R12 ; /* 0x800000060e06722b */
/* 0x000e46000000000c */
/*07b0*/ LOP3.LUT R9, R5, R9, RZ, 0x3c, !PT ; /* 0x0000000905097212 */
/* 0x001fc600078e3cff */
/*07c0*/ IADD3 R6, -R16, -0x43300000, RZ ; /* 0xbcd0000010067810 */
/* 0x002fc80007ffe1ff */
/*07d0*/ FSETP.NEU.AND P0, PT, |R7|, R6, PT ; /* 0x000000060700720b */
/* 0x000fc80003f0d200 */
/*07e0*/ FSEL R14, R4, R14, !P0 ; /* 0x0000000e040e7208 */
/* 0x000fe40004000000 */
/*07f0*/ FSEL R15, R9, R15, !P0 ; /* 0x0000000f090f7208 */
/* 0x000fe20004000000 */
/*0800*/ BRA 0x960 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0810*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x003e1c0003f08000 */
/*0820*/ @P0 BRA 0x940 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0830*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0840*/ @P0 BRA 0x910 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0850*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0860*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*0870*/ IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; /* 0xfff80000ff0f7424 */
/* 0x000fd400078e00ff */
/*0880*/ @!P0 BRA 0x960 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0890*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*08a0*/ LOP3.LUT R15, R5, 0x80000000, R9, 0x48, !PT ; /* 0x80000000050f7812 */
/* 0x000fe400078e4809 */
/*08b0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*08c0*/ @P0 LOP3.LUT R4, R15, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000f040812 */
/* 0x000fe200078efcff */
/*08d0*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe400078e00ff */
/*08e0*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*08f0*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, R4 ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e0004 */
/*0900*/ BRA 0x960 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0910*/ LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090f7812 */
/* 0x000fe200078efcff */
/*0920*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0930*/ BRA 0x960 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R15, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050f7812 */
/* 0x000fe200078efcff */
/*0950*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0004 */
/*0960*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0970*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc400078e00ff */
/*0980*/ IMAD.MOV.U32 R8, RZ, RZ, R14 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000e */
/*0990*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe200078e000f */
/*09a0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff65004007950 */
/* 0x000fec0003c3ffff */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22strided_access_onepassPjiibS_Pd
.globl _Z22strided_access_onepassPjiibS_Pd
.p2align 8
.type _Z22strided_access_onepassPjiibS_Pd,@function
_Z22strided_access_onepassPjiibS_Pd:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x34
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, 0
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, v6
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[5:6]
s_getreg_b32 s7, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v5, v[7:8], off
s_getreg_b32 s8, hwreg(HW_REG_SHADER_CYCLES, 0, 20)
s_sub_u32 s7, s8, s7
s_subb_u32 s8, 0, 0
s_add_u32 s7, s7, -16
s_addc_u32 s8, s8, -1
v_cvt_f64_u32_e32 v[9:10], s7
v_cvt_f64_u32_e32 v[7:8], s8
s_add_i32 s6, s6, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[7:8], 32
v_add_f64 v[7:8], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[3:4], v[7:8]
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[9:10], v5
v_cmp_gt_u32_e32 vcc_lo, s5, v5
v_add_f64 v[1:2], v[1:2], v[9:10]
s_cbranch_vccnz .LBB0_2
v_cvt_f64_i32_e32 v[5:6], s6
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v5, 0
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v3, 0
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v4, 0
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s2, 0
s_cbranch_scc1 .LBB0_7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], v[3:4]
v_div_scale_f64 v[13:14], vcc_lo, v[3:4], v[5:6], v[3:4]
s_load_b128 s[0:3], s[0:1], 0x18
s_and_b32 s4, 0xffff, s4
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[3:4], v[7:8], v[5:6], v[3:4]
v_cvt_u32_f64_e32 v7, v[3:4]
v_mad_u64_u32 v[3:4], null, s15, s4, v[0:1]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[3:4]
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b32 v[5:6], v7, off
global_store_b64 v[3:4], v[1:2], off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22strided_access_onepassPjiibS_Pd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22strided_access_onepassPjiibS_Pd, .Lfunc_end0-_Z22strided_access_onepassPjiibS_Pd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 1
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22strided_access_onepassPjiibS_Pd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22strided_access_onepassPjiibS_Pd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void addScannedBlockSums(float *input, float *aux, int len) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int i = 2 * bx * dx + tx;
if (bx > 0) {
if (i < len)
aux[i] += input[bx-1];
if (i + dx < len)
aux[i + dx] += input[blockIdx.x - 1];
}
} | code for sm_80
Function : _Z19addScannedBlockSumsPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GE.AND P0, PT, R8.reuse, 0x1, PT ; /* 0x000000010800780c */
/* 0x041fe40003f06270 */
/*0040*/ SHF.L.U32 R0, R8, 0x1, RZ ; /* 0x0000000108007819 */
/* 0x000fca00000006ff */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fcc00078e0203 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GE.AND P0, PT, R0.reuse, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x040fe20003f06270 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R6, R0, c[0x0][0x0], RZ ; /* 0x0000000000067a10 */
/* 0x000fe20007ffe0ff */
/*00a0*/ BSSY B0, 0x160 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*00b0*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fce0003f26270 */
/*00c0*/ @P0 BRA 0x150 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00e0*/ IADD3 R2, R8, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x000fd20007ffe0ff */
/*00f0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0130*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R2, R8, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x000fe40007ffe0ff */
/*0180*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x001fca0000000f00 */
/*0190*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0005 */
/*01a0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0205 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*01e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void addScannedBlockSums(float *input, float *aux, int len) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int i = 2 * bx * dx + tx;
if (bx > 0) {
if (i < len)
aux[i] += input[bx-1];
if (i + dx < len)
aux[i + dx] += input[blockIdx.x - 1];
}
} | .file "tmpxft_00070dc1_00000000-6_addScannedBlockSums.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i
.type _Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i, @function
_Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19addScannedBlockSumsPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i, .-_Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i
.globl _Z19addScannedBlockSumsPfS_i
.type _Z19addScannedBlockSumsPfS_i, @function
_Z19addScannedBlockSumsPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19addScannedBlockSumsPfS_i, .-_Z19addScannedBlockSumsPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19addScannedBlockSumsPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19addScannedBlockSumsPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void addScannedBlockSums(float *input, float *aux, int len) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int i = 2 * bx * dx + tx;
if (bx > 0) {
if (i < len)
aux[i] += input[bx-1];
if (i + dx < len)
aux[i + dx] += input[blockIdx.x - 1];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addScannedBlockSums(float *input, float *aux, int len) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int i = 2 * bx * dx + tx;
if (bx > 0) {
if (i < len)
aux[i] += input[bx-1];
if (i + dx < len)
aux[i + dx] += input[blockIdx.x - 1];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addScannedBlockSums(float *input, float *aux, int len) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int i = 2 * bx * dx + tx;
if (bx > 0) {
if (i < len)
aux[i] += input[bx-1];
if (i + dx < len)
aux[i + dx] += input[blockIdx.x - 1];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19addScannedBlockSumsPfS_i
.globl _Z19addScannedBlockSumsPfS_i
.p2align 8
.type _Z19addScannedBlockSumsPfS_i,@function
_Z19addScannedBlockSumsPfS_i:
s_cmp_lt_i32 s15, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s15, s7
v_lshl_add_u32 v0, s5, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 2
s_add_u32 s5, s0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_addc_u32 s9, s1, s11
s_add_u32 s10, s5, -4
s_addc_u32 s11, s9, -1
s_load_b32 s5, s[10:11], 0x0
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, s5, v3
global_store_b32 v[1:2], v3, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v0, s7, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
s_add_i32 s4, s4, -1
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[4:5], s[4:5], 2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v2, s[0:1]
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19addScannedBlockSumsPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19addScannedBlockSumsPfS_i, .Lfunc_end0-_Z19addScannedBlockSumsPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19addScannedBlockSumsPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19addScannedBlockSumsPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void addScannedBlockSums(float *input, float *aux, int len) {
int tx = threadIdx.x;
int bx = blockIdx.x;
int dx = blockDim.x;
int i = 2 * bx * dx + tx;
if (bx > 0) {
if (i < len)
aux[i] += input[bx-1];
if (i + dx < len)
aux[i + dx] += input[blockIdx.x - 1];
}
} | .text
.file "addScannedBlockSums.hip"
.globl _Z34__device_stub__addScannedBlockSumsPfS_i # -- Begin function _Z34__device_stub__addScannedBlockSumsPfS_i
.p2align 4, 0x90
.type _Z34__device_stub__addScannedBlockSumsPfS_i,@function
_Z34__device_stub__addScannedBlockSumsPfS_i: # @_Z34__device_stub__addScannedBlockSumsPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19addScannedBlockSumsPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__addScannedBlockSumsPfS_i, .Lfunc_end0-_Z34__device_stub__addScannedBlockSumsPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19addScannedBlockSumsPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19addScannedBlockSumsPfS_i,@object # @_Z19addScannedBlockSumsPfS_i
.section .rodata,"a",@progbits
.globl _Z19addScannedBlockSumsPfS_i
.p2align 3, 0x0
_Z19addScannedBlockSumsPfS_i:
.quad _Z34__device_stub__addScannedBlockSumsPfS_i
.size _Z19addScannedBlockSumsPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19addScannedBlockSumsPfS_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__addScannedBlockSumsPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19addScannedBlockSumsPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19addScannedBlockSumsPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0030*/ ISETP.GE.AND P0, PT, R8.reuse, 0x1, PT ; /* 0x000000010800780c */
/* 0x041fe40003f06270 */
/*0040*/ SHF.L.U32 R0, R8, 0x1, RZ ; /* 0x0000000108007819 */
/* 0x000fca00000006ff */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x002fcc00078e0203 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ ISETP.GE.AND P0, PT, R0.reuse, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x040fe20003f06270 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R6, R0, c[0x0][0x0], RZ ; /* 0x0000000000067a10 */
/* 0x000fe20007ffe0ff */
/*00a0*/ BSSY B0, 0x160 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*00b0*/ ISETP.GE.AND P1, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fce0003f26270 */
/*00c0*/ @P0 BRA 0x150 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00d0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00e0*/ IADD3 R2, R8, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x000fd20007ffe0ff */
/*00f0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*0100*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fe400078e0205 */
/*0110*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0130*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*0140*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0170*/ IADD3 R2, R8, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x000fe40007ffe0ff */
/*0180*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x001fca0000000f00 */
/*0190*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0005 */
/*01a0*/ IMAD.WIDE R4, R6, R5, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0205 */
/*01b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*01d0*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*01e0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19addScannedBlockSumsPfS_i
.globl _Z19addScannedBlockSumsPfS_i
.p2align 8
.type _Z19addScannedBlockSumsPfS_i,@function
_Z19addScannedBlockSumsPfS_i:
s_cmp_lt_i32 s15, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x2
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s15, s7
v_lshl_add_u32 v0, s5, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v1, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 2
s_add_u32 s5, s0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_addc_u32 s9, s1, s11
s_add_u32 s10, s5, -4
s_addc_u32 s11, s9, -1
s_load_b32 s5, s[10:11], 0x0
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v3, s5, v3
global_store_b32 v[1:2], v3, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v0, s7, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
s_add_i32 s4, s4, -1
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[4:5], s[4:5], 2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v2, s[0:1]
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19addScannedBlockSumsPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19addScannedBlockSumsPfS_i, .Lfunc_end0-_Z19addScannedBlockSumsPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19addScannedBlockSumsPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z19addScannedBlockSumsPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00070dc1_00000000-6_addScannedBlockSums.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i
.type _Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i, @function
_Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19addScannedBlockSumsPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i, .-_Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i
.globl _Z19addScannedBlockSumsPfS_i
.type _Z19addScannedBlockSumsPfS_i, @function
_Z19addScannedBlockSumsPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z19addScannedBlockSumsPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19addScannedBlockSumsPfS_i, .-_Z19addScannedBlockSumsPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19addScannedBlockSumsPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19addScannedBlockSumsPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addScannedBlockSums.hip"
.globl _Z34__device_stub__addScannedBlockSumsPfS_i # -- Begin function _Z34__device_stub__addScannedBlockSumsPfS_i
.p2align 4, 0x90
.type _Z34__device_stub__addScannedBlockSumsPfS_i,@function
_Z34__device_stub__addScannedBlockSumsPfS_i: # @_Z34__device_stub__addScannedBlockSumsPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19addScannedBlockSumsPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z34__device_stub__addScannedBlockSumsPfS_i, .Lfunc_end0-_Z34__device_stub__addScannedBlockSumsPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19addScannedBlockSumsPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19addScannedBlockSumsPfS_i,@object # @_Z19addScannedBlockSumsPfS_i
.section .rodata,"a",@progbits
.globl _Z19addScannedBlockSumsPfS_i
.p2align 3, 0x0
_Z19addScannedBlockSumsPfS_i:
.quad _Z34__device_stub__addScannedBlockSumsPfS_i
.size _Z19addScannedBlockSumsPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19addScannedBlockSumsPfS_i"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__addScannedBlockSumsPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19addScannedBlockSumsPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mDivergence_TwoDim(float *div, float *u_dimX, float *u_dimY, float r_sStep) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) return;
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int Left = Idx - 1;
int Right = Idx + 1;
int Top = Idx + blockDim.x;
int Bottom = Idx - blockDim.x;
div[Idx] = ((u_dimX[Right]-u_dimX[Left])+(u_dimY[Top]-u_dimY[Bottom]))*r_sStep;
} | code for sm_80
Function : _Z18mDivergence_TwoDimPfS_S_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e6a0000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x001fc8000bf05270 */
/*0060*/ ISETP.EQ.OR P0, PT, R8, RZ, !P0 ; /* 0x000000ff0800720c */
/* 0x000fc80004702670 */
/*0070*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x002fc80000702670 */
/*0080*/ ISETP.EQ.OR P0, PT, R3, 0x1df, P0 ; /* 0x000001df0300780c */
/* 0x000fda0000702670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */
/* 0x000fe200078e0208 */
/*00b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IADD3 R6, R8.reuse, -c[0x0][0x0], RZ ; /* 0x8000000008067a10 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R4, R8, c[0x0][0x0], RZ ; /* 0x0000000008047a10 */
/* 0x000fc80007ffe0ff */
/*00f0*/ IMAD.WIDE R2, R8, R11, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fc800078e020b */
/*0100*/ IMAD.WIDE R6, R6, R11.reuse, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x080fe200078e020b */
/*0110*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0402007981 */
/* 0x000ea6000c1e1900 */
/*0120*/ IMAD.WIDE R4, R4, R11, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e020b */
/*0130*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee2000c1e1900 */
/*0160*/ FADD R0, -R0, R9 ; /* 0x0000000900007221 */
/* 0x004fc40000000100 */
/*0170*/ FADD R9, -R6, R5 ; /* 0x0000000506097221 */
/* 0x008fc80000000100 */
/*0180*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x000fe40000000000 */
/*0190*/ IMAD.WIDE R8, R8, R11, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e020b */
/*01a0*/ FMUL R11, R0, c[0x0][0x178] ; /* 0x00005e00000b7a20 */
/* 0x000fca0000400000 */
/*01b0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mDivergence_TwoDim(float *div, float *u_dimX, float *u_dimY, float r_sStep) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) return;
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int Left = Idx - 1;
int Right = Idx + 1;
int Top = Idx + blockDim.x;
int Bottom = Idx - blockDim.x;
div[Idx] = ((u_dimX[Right]-u_dimX[Left])+(u_dimY[Top]-u_dimY[Bottom]))*r_sStep;
} | .file "tmpxft_0004c475_00000000-6_mDivergence_TwoDim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13checkBoundaryiii
.type _Z13checkBoundaryiii, @function
_Z13checkBoundaryiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13checkBoundaryiii, .-_Z13checkBoundaryiii
.globl _Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f
.type _Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f, @function
_Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18mDivergence_TwoDimPfS_S_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f, .-_Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f
.globl _Z18mDivergence_TwoDimPfS_S_f
.type _Z18mDivergence_TwoDimPfS_S_f, @function
_Z18mDivergence_TwoDimPfS_S_f:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18mDivergence_TwoDimPfS_S_f, .-_Z18mDivergence_TwoDimPfS_S_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18mDivergence_TwoDimPfS_S_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18mDivergence_TwoDimPfS_S_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mDivergence_TwoDim(float *div, float *u_dimX, float *u_dimY, float r_sStep) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) return;
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int Left = Idx - 1;
int Right = Idx + 1;
int Top = Idx + blockDim.x;
int Bottom = Idx - blockDim.x;
div[Idx] = ((u_dimX[Right]-u_dimX[Left])+(u_dimY[Top]-u_dimY[Bottom]))*r_sStep;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mDivergence_TwoDim(float *div, float *u_dimX, float *u_dimY, float r_sStep) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) return;
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int Left = Idx - 1;
int Right = Idx + 1;
int Top = Idx + blockDim.x;
int Bottom = Idx - blockDim.x;
div[Idx] = ((u_dimX[Right]-u_dimX[Left])+(u_dimY[Top]-u_dimY[Bottom]))*r_sStep;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mDivergence_TwoDim(float *div, float *u_dimX, float *u_dimY, float r_sStep) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) return;
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int Left = Idx - 1;
int Right = Idx + 1;
int Top = Idx + blockDim.x;
int Bottom = Idx - blockDim.x;
div[Idx] = ((u_dimX[Right]-u_dimX[Left])+(u_dimY[Top]-u_dimY[Bottom]))*r_sStep;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18mDivergence_TwoDimPfS_S_f
.globl _Z18mDivergence_TwoDimPfS_S_f
.p2align 8
.type _Z18mDivergence_TwoDimPfS_S_f,@function
_Z18mDivergence_TwoDimPfS_S_f:
s_load_b32 s2, s[0:1], 0x2c
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s3, -1
v_cmp_ne_u32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_7
s_cmpk_lt_i32 s15, 0x1df
s_cbranch_scc1 .LBB0_3
s_cmpk_lg_i32 s15, 0x1df
s_cselect_b32 s2, -1, 0
s_cbranch_execz .LBB0_4
s_branch .LBB0_5
.LBB0_3:
s_mov_b32 s2, 0
.LBB0_4:
s_cmp_lg_u32 s15, 0
s_cselect_b32 s2, -1, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v5, s3, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_clause 0x1
global_load_b32 v8, v[6:7], off offset:4
global_load_b32 v6, v[6:7], off offset:-4
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(2)
v_sub_f32_e32 v4, v8, v6
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v4, v2
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18mDivergence_TwoDimPfS_S_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18mDivergence_TwoDimPfS_S_f, .Lfunc_end0-_Z18mDivergence_TwoDimPfS_S_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18mDivergence_TwoDimPfS_S_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18mDivergence_TwoDimPfS_S_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ bool checkBoundary(int blockIdx, int blockDim, int threadIdx){
int x = threadIdx;
int y = blockIdx;
return (x == 0 || x == (blockDim-1) || y == 0 || y == 479);
}
__global__ void mDivergence_TwoDim(float *div, float *u_dimX, float *u_dimY, float r_sStep) {
if(checkBoundary(blockIdx.x, blockDim.x, threadIdx.x)) return;
int Idx = blockIdx.x * blockDim.x + threadIdx.x;
int Left = Idx - 1;
int Right = Idx + 1;
int Top = Idx + blockDim.x;
int Bottom = Idx - blockDim.x;
div[Idx] = ((u_dimX[Right]-u_dimX[Left])+(u_dimY[Top]-u_dimY[Bottom]))*r_sStep;
} | .text
.file "mDivergence_TwoDim.hip"
.globl _Z33__device_stub__mDivergence_TwoDimPfS_S_f # -- Begin function _Z33__device_stub__mDivergence_TwoDimPfS_S_f
.p2align 4, 0x90
.type _Z33__device_stub__mDivergence_TwoDimPfS_S_f,@function
_Z33__device_stub__mDivergence_TwoDimPfS_S_f: # @_Z33__device_stub__mDivergence_TwoDimPfS_S_f
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18mDivergence_TwoDimPfS_S_f, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__mDivergence_TwoDimPfS_S_f, .Lfunc_end0-_Z33__device_stub__mDivergence_TwoDimPfS_S_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18mDivergence_TwoDimPfS_S_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18mDivergence_TwoDimPfS_S_f,@object # @_Z18mDivergence_TwoDimPfS_S_f
.section .rodata,"a",@progbits
.globl _Z18mDivergence_TwoDimPfS_S_f
.p2align 3, 0x0
_Z18mDivergence_TwoDimPfS_S_f:
.quad _Z33__device_stub__mDivergence_TwoDimPfS_S_f
.size _Z18mDivergence_TwoDimPfS_S_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18mDivergence_TwoDimPfS_S_f"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__mDivergence_TwoDimPfS_S_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18mDivergence_TwoDimPfS_S_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18mDivergence_TwoDimPfS_S_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e6a0000002500 */
/*0050*/ ISETP.NE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x001fc8000bf05270 */
/*0060*/ ISETP.EQ.OR P0, PT, R8, RZ, !P0 ; /* 0x000000ff0800720c */
/* 0x000fc80004702670 */
/*0070*/ ISETP.EQ.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x002fc80000702670 */
/*0080*/ ISETP.EQ.OR P0, PT, R3, 0x1df, P0 ; /* 0x000001df0300780c */
/* 0x000fda0000702670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD R8, R3, c[0x0][0x0], R8 ; /* 0x0000000003087a24 */
/* 0x000fe200078e0208 */
/*00b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IADD3 R6, R8.reuse, -c[0x0][0x0], RZ ; /* 0x8000000008067a10 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R4, R8, c[0x0][0x0], RZ ; /* 0x0000000008047a10 */
/* 0x000fc80007ffe0ff */
/*00f0*/ IMAD.WIDE R2, R8, R11, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fc800078e020b */
/*0100*/ IMAD.WIDE R6, R6, R11.reuse, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x080fe200078e020b */
/*0110*/ LDG.E R0, [R2.64+-0x4] ; /* 0xfffffc0402007981 */
/* 0x000ea6000c1e1900 */
/*0120*/ IMAD.WIDE R4, R4, R11, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e020b */
/*0130*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee2000c1e1900 */
/*0160*/ FADD R0, -R0, R9 ; /* 0x0000000900007221 */
/* 0x004fc40000000100 */
/*0170*/ FADD R9, -R6, R5 ; /* 0x0000000506097221 */
/* 0x008fc80000000100 */
/*0180*/ FADD R0, R0, R9 ; /* 0x0000000900007221 */
/* 0x000fe40000000000 */
/*0190*/ IMAD.WIDE R8, R8, R11, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e020b */
/*01a0*/ FMUL R11, R0, c[0x0][0x178] ; /* 0x00005e00000b7a20 */
/* 0x000fca0000400000 */
/*01b0*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ BRA 0x1d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18mDivergence_TwoDimPfS_S_f
.globl _Z18mDivergence_TwoDimPfS_S_f
.p2align 8
.type _Z18mDivergence_TwoDimPfS_S_f,@function
_Z18mDivergence_TwoDimPfS_S_f:
s_load_b32 s2, s[0:1], 0x2c
v_cmp_ne_u32_e32 vcc_lo, 0, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s3, -1
v_cmp_ne_u32_e64 s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_7
s_cmpk_lt_i32 s15, 0x1df
s_cbranch_scc1 .LBB0_3
s_cmpk_lg_i32 s15, 0x1df
s_cselect_b32 s2, -1, 0
s_cbranch_execz .LBB0_4
s_branch .LBB0_5
.LBB0_3:
s_mov_b32 s2, 0
.LBB0_4:
s_cmp_lg_u32 s15, 0
s_cselect_b32 s2, -1, 0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_7
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
v_subrev_nc_u32_e32 v5, s3, v1
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[3:4]
v_lshlrev_b64 v[4:5], 2, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
s_clause 0x1
global_load_b32 v8, v[6:7], off offset:4
global_load_b32 v6, v[6:7], off offset:-4
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(2)
v_sub_f32_e32 v4, v8, v6
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v4, v2
v_mul_f32_e32 v2, s0, v2
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18mDivergence_TwoDimPfS_S_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18mDivergence_TwoDimPfS_S_f, .Lfunc_end0-_Z18mDivergence_TwoDimPfS_S_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18mDivergence_TwoDimPfS_S_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18mDivergence_TwoDimPfS_S_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004c475_00000000-6_mDivergence_TwoDim.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13checkBoundaryiii
.type _Z13checkBoundaryiii, @function
_Z13checkBoundaryiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z13checkBoundaryiii, .-_Z13checkBoundaryiii
.globl _Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f
.type _Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f, @function
_Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18mDivergence_TwoDimPfS_S_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f, .-_Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f
.globl _Z18mDivergence_TwoDimPfS_S_f
.type _Z18mDivergence_TwoDimPfS_S_f, @function
_Z18mDivergence_TwoDimPfS_S_f:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18mDivergence_TwoDimPfS_S_fPfS_S_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z18mDivergence_TwoDimPfS_S_f, .-_Z18mDivergence_TwoDimPfS_S_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18mDivergence_TwoDimPfS_S_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18mDivergence_TwoDimPfS_S_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mDivergence_TwoDim.hip"
.globl _Z33__device_stub__mDivergence_TwoDimPfS_S_f # -- Begin function _Z33__device_stub__mDivergence_TwoDimPfS_S_f
.p2align 4, 0x90
.type _Z33__device_stub__mDivergence_TwoDimPfS_S_f,@function
_Z33__device_stub__mDivergence_TwoDimPfS_S_f: # @_Z33__device_stub__mDivergence_TwoDimPfS_S_f
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18mDivergence_TwoDimPfS_S_f, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__mDivergence_TwoDimPfS_S_f, .Lfunc_end0-_Z33__device_stub__mDivergence_TwoDimPfS_S_f
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18mDivergence_TwoDimPfS_S_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18mDivergence_TwoDimPfS_S_f,@object # @_Z18mDivergence_TwoDimPfS_S_f
.section .rodata,"a",@progbits
.globl _Z18mDivergence_TwoDimPfS_S_f
.p2align 3, 0x0
_Z18mDivergence_TwoDimPfS_S_f:
.quad _Z33__device_stub__mDivergence_TwoDimPfS_S_f
.size _Z18mDivergence_TwoDimPfS_S_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18mDivergence_TwoDimPfS_S_f"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__mDivergence_TwoDimPfS_S_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18mDivergence_TwoDimPfS_S_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
template<class DType>
__global__ void block_sum(const DType *input,
DType *per_block_results,
const size_t n)
{
extern __shared__ DType sdata[];
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
// Ò»¸öÏ̸߳ºÔð°ÑÒ»¸öÔªËØ´ÓÈ«¾ÖÄÚ´æÔØÈëµ½¹²ÏíÄÚ´æ
DType x = 0;
if(i < n){
x = input[i];
}
sdata[threadIdx.x] = x;
__syncthreads();//µÈ´ýËùÓÐḬ̈߳Ñ×Ô¼º¸ºÔðµÄÔªËØÔØÈëµ½¹²ÏíÄÚ´æ
// ¿éÄÚ½øÐкϲ¢²Ù×÷£¬Ã¿´ÎºÏ²¢±äΪһ°ë.×¢ÒâthreadIdx.xÊÇ¿éÄÚµÄÆ«ÒÆ£¬ÉÏÃæËã³öµÄiÊÇÈ«¾ÖµÄÆ«ÒÆ¡£
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(threadIdx.x < offset)//¿ØÖÆÖ»ÓÐijЩÏ̲߳ŽøÐвÙ×÷¡£
{
sdata[threadIdx.x] += sdata[threadIdx.x + offset];
}
__syncthreads();
}
//ÿ¸ö¿éµÄÏß³Ì0¸ºÔð´æ·Å¿éÄÚÇóºÍµÄ½á¹û
if(threadIdx.x == 0)
{
per_block_results[blockIdx.x] = sdata[0];
}
}
int main()
{
const int num_elements=1024; //ÉèÖÃÊý×鳤¶È
//·ÖÅäÄÚ´æ
float h_input[num_elements];
for (int i = 0; i < num_elements; i++){
h_input[i]=1.0f;
}
float *d_input = 0;
cudaMalloc((void**)&d_input, sizeof(float) * num_elements);
cudaMemcpy(d_input, &h_input, sizeof(float) * num_elements, cudaMemcpyHostToDevice);
const size_t block_size = 512;//Ï߳̿éµÄ´óС¡£Ä¿Ç°ÓÐЩgpuµÄÏ߳̿é×î´óΪ512£¬ÓÐЩΪ1024.
const size_t num_blocks = (num_elements/block_size) + ((num_elements%block_size) ? 1 : 0);
float *d_partial_sums_and_total = 0;//Ò»¸öÏ߳̿éÒ»¸öºÍ£¬ÁíÍâ¼ÓÒ»¸öÔªËØ£¬´æ·ÅËùÓÐÏ߳̿éµÄºÍ¡£
cudaMalloc((void**)&d_partial_sums_and_total, sizeof(float) * (num_blocks + 1));
//°Ñÿ¸öÏ߳̿éµÄºÍÇó³öÀ´
block_sum<<<num_blocks,block_size,block_size *sizeof(float)>>>(d_input, d_partial_sums_and_total, num_elements);
//ÔÙ´ÎÓÃÒ»¸öÏ߳̿é°ÑÉÏÒ»²½µÄ½á¹ûÇóºÍ¡£
//×¢ÒâÕâÀïÓиöÏÞÖÆ£¬ÉÏÒ»²½Ï߳̿éµÄÊýÁ¿£¬±ØÐë²»´óÓÚÒ»¸öÏ߳̿éÏ̵߳Ä×î´óÊýÁ¿£¬ÒòΪÕâÒ»²½µÃ°ÑÉÏÒ»²½µÄ½á¹û·ÅÔÚÒ»¸öÏ߳̿é²Ù×÷¡£
//¼´num_blocks²»ÄÜ´óÓÚÏ߳̿éµÄ×î´óÏß³ÌÊýÁ¿¡£
block_sum<<<1,num_blocks,num_blocks * sizeof(float)>>>(d_partial_sums_and_total, d_partial_sums_and_total + num_blocks, num_blocks);
float device_result = 0;
cudaMemcpy(&device_result, d_partial_sums_and_total + num_blocks, sizeof(float), cudaMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// ÊÍ·ÅÏÔ´æÈÝÁ¿
cudaFree(d_input);
cudaFree(d_partial_sums_and_total);
return 0;
} | code for sm_80
Function : _Z9block_sumIfEvPKT_PS0_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @!P0 LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000028a11 */
/* 0x000fc800078210ff */
/*0080*/ @!P0 LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P1 ; /* 0x0000590000038a11 */
/* 0x000fe200008f14ff */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fcc00078e00ff */
/*00a0*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00f0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0110*/ @!P1 BRA 0x1e0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0150*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0160*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0170*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0180*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0190*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*01a0*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01d0*/ @P1 BRA 0x140 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
template<class DType>
__global__ void block_sum(const DType *input,
DType *per_block_results,
const size_t n)
{
extern __shared__ DType sdata[];
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
// Ò»¸öÏ̸߳ºÔð°ÑÒ»¸öÔªËØ´ÓÈ«¾ÖÄÚ´æÔØÈëµ½¹²ÏíÄÚ´æ
DType x = 0;
if(i < n){
x = input[i];
}
sdata[threadIdx.x] = x;
__syncthreads();//µÈ´ýËùÓÐḬ̈߳Ñ×Ô¼º¸ºÔðµÄÔªËØÔØÈëµ½¹²ÏíÄÚ´æ
// ¿éÄÚ½øÐкϲ¢²Ù×÷£¬Ã¿´ÎºÏ²¢±äΪһ°ë.×¢ÒâthreadIdx.xÊÇ¿éÄÚµÄÆ«ÒÆ£¬ÉÏÃæËã³öµÄiÊÇÈ«¾ÖµÄÆ«ÒÆ¡£
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(threadIdx.x < offset)//¿ØÖÆÖ»ÓÐijЩÏ̲߳ŽøÐвÙ×÷¡£
{
sdata[threadIdx.x] += sdata[threadIdx.x + offset];
}
__syncthreads();
}
//ÿ¸ö¿éµÄÏß³Ì0¸ºÔð´æ·Å¿éÄÚÇóºÍµÄ½á¹û
if(threadIdx.x == 0)
{
per_block_results[blockIdx.x] = sdata[0];
}
}
int main()
{
const int num_elements=1024; //ÉèÖÃÊý×鳤¶È
//·ÖÅäÄÚ´æ
float h_input[num_elements];
for (int i = 0; i < num_elements; i++){
h_input[i]=1.0f;
}
float *d_input = 0;
cudaMalloc((void**)&d_input, sizeof(float) * num_elements);
cudaMemcpy(d_input, &h_input, sizeof(float) * num_elements, cudaMemcpyHostToDevice);
const size_t block_size = 512;//Ï߳̿éµÄ´óС¡£Ä¿Ç°ÓÐЩgpuµÄÏ߳̿é×î´óΪ512£¬ÓÐЩΪ1024.
const size_t num_blocks = (num_elements/block_size) + ((num_elements%block_size) ? 1 : 0);
float *d_partial_sums_and_total = 0;//Ò»¸öÏ߳̿éÒ»¸öºÍ£¬ÁíÍâ¼ÓÒ»¸öÔªËØ£¬´æ·ÅËùÓÐÏ߳̿éµÄºÍ¡£
cudaMalloc((void**)&d_partial_sums_and_total, sizeof(float) * (num_blocks + 1));
//°Ñÿ¸öÏ߳̿éµÄºÍÇó³öÀ´
block_sum<<<num_blocks,block_size,block_size *sizeof(float)>>>(d_input, d_partial_sums_and_total, num_elements);
//ÔÙ´ÎÓÃÒ»¸öÏ߳̿é°ÑÉÏÒ»²½µÄ½á¹ûÇóºÍ¡£
//×¢ÒâÕâÀïÓиöÏÞÖÆ£¬ÉÏÒ»²½Ï߳̿éµÄÊýÁ¿£¬±ØÐë²»´óÓÚÒ»¸öÏ߳̿éÏ̵߳Ä×î´óÊýÁ¿£¬ÒòΪÕâÒ»²½µÃ°ÑÉÏÒ»²½µÄ½á¹û·ÅÔÚÒ»¸öÏ߳̿é²Ù×÷¡£
//¼´num_blocks²»ÄÜ´óÓÚÏ߳̿éµÄ×î´óÏß³ÌÊýÁ¿¡£
block_sum<<<1,num_blocks,num_blocks * sizeof(float)>>>(d_partial_sums_and_total, d_partial_sums_and_total + num_blocks, num_blocks);
float device_result = 0;
cudaMemcpy(&device_result, d_partial_sums_and_total + num_blocks, sizeof(float), cudaMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// ÊÍ·ÅÏÔ´æÈÝÁ¿
cudaFree(d_input);
cudaFree(d_partial_sums_and_total);
return 0;
} | .file "tmpxft_000b8101_00000000-6_kernel0.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z9block_sumIfEvPKT_PS0_m,"axG",@progbits,_Z9block_sumIfEvPKT_PS0_m,comdat
.weak _Z9block_sumIfEvPKT_PS0_m
.type _Z9block_sumIfEvPKT_PS0_m, @function
_Z9block_sumIfEvPKT_PS0_m:
.LFB3999:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9block_sumIfEvPKT_PS0_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3999:
.size _Z9block_sumIfEvPKT_PS0_m, .-_Z9block_sumIfEvPKT_PS0_m
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Device sum: "
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $72, %rsp
.cfi_def_cfa_offset 4176
movq %fs:40, %rax
movq %rax, 4152(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rax
leaq 4144(%rsp), %rdx
movss .LC0(%rip), %xmm0
.L10:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L10
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $2048, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L11:
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $8, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $0x00000000, 36(%rsp)
movq 16(%rsp), %rax
leaq 8(%rax), %rsi
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4152(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $4168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $1024, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z9block_sumIfEvPKT_PS0_m
jmp .L11
.L17:
movq 16(%rsp), %rdi
leaq 8(%rdi), %rsi
movl $2, %edx
call _Z9block_sumIfEvPKT_PS0_m
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9block_sumIfEvPKT_PS0_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9block_sumIfEvPKT_PS0_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
template<class DType>
__global__ void block_sum(const DType *input,
DType *per_block_results,
const size_t n)
{
extern __shared__ DType sdata[];
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
// Ò»¸öÏ̸߳ºÔð°ÑÒ»¸öÔªËØ´ÓÈ«¾ÖÄÚ´æÔØÈëµ½¹²ÏíÄÚ´æ
DType x = 0;
if(i < n){
x = input[i];
}
sdata[threadIdx.x] = x;
__syncthreads();//µÈ´ýËùÓÐḬ̈߳Ñ×Ô¼º¸ºÔðµÄÔªËØÔØÈëµ½¹²ÏíÄÚ´æ
// ¿éÄÚ½øÐкϲ¢²Ù×÷£¬Ã¿´ÎºÏ²¢±äΪһ°ë.×¢ÒâthreadIdx.xÊÇ¿éÄÚµÄÆ«ÒÆ£¬ÉÏÃæËã³öµÄiÊÇÈ«¾ÖµÄÆ«ÒÆ¡£
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(threadIdx.x < offset)//¿ØÖÆÖ»ÓÐijЩÏ̲߳ŽøÐвÙ×÷¡£
{
sdata[threadIdx.x] += sdata[threadIdx.x + offset];
}
__syncthreads();
}
//ÿ¸ö¿éµÄÏß³Ì0¸ºÔð´æ·Å¿éÄÚÇóºÍµÄ½á¹û
if(threadIdx.x == 0)
{
per_block_results[blockIdx.x] = sdata[0];
}
}
int main()
{
const int num_elements=1024; //ÉèÖÃÊý×鳤¶È
//·ÖÅäÄÚ´æ
float h_input[num_elements];
for (int i = 0; i < num_elements; i++){
h_input[i]=1.0f;
}
float *d_input = 0;
cudaMalloc((void**)&d_input, sizeof(float) * num_elements);
cudaMemcpy(d_input, &h_input, sizeof(float) * num_elements, cudaMemcpyHostToDevice);
const size_t block_size = 512;//Ï߳̿éµÄ´óС¡£Ä¿Ç°ÓÐЩgpuµÄÏ߳̿é×î´óΪ512£¬ÓÐЩΪ1024.
const size_t num_blocks = (num_elements/block_size) + ((num_elements%block_size) ? 1 : 0);
float *d_partial_sums_and_total = 0;//Ò»¸öÏ߳̿éÒ»¸öºÍ£¬ÁíÍâ¼ÓÒ»¸öÔªËØ£¬´æ·ÅËùÓÐÏ߳̿éµÄºÍ¡£
cudaMalloc((void**)&d_partial_sums_and_total, sizeof(float) * (num_blocks + 1));
//°Ñÿ¸öÏ߳̿éµÄºÍÇó³öÀ´
block_sum<<<num_blocks,block_size,block_size *sizeof(float)>>>(d_input, d_partial_sums_and_total, num_elements);
//ÔÙ´ÎÓÃÒ»¸öÏ߳̿é°ÑÉÏÒ»²½µÄ½á¹ûÇóºÍ¡£
//×¢ÒâÕâÀïÓиöÏÞÖÆ£¬ÉÏÒ»²½Ï߳̿éµÄÊýÁ¿£¬±ØÐë²»´óÓÚÒ»¸öÏ߳̿éÏ̵߳Ä×î´óÊýÁ¿£¬ÒòΪÕâÒ»²½µÃ°ÑÉÏÒ»²½µÄ½á¹û·ÅÔÚÒ»¸öÏ߳̿é²Ù×÷¡£
//¼´num_blocks²»ÄÜ´óÓÚÏ߳̿éµÄ×î´óÏß³ÌÊýÁ¿¡£
block_sum<<<1,num_blocks,num_blocks * sizeof(float)>>>(d_partial_sums_and_total, d_partial_sums_and_total + num_blocks, num_blocks);
float device_result = 0;
cudaMemcpy(&device_result, d_partial_sums_and_total + num_blocks, sizeof(float), cudaMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// ÊÍ·ÅÏÔ´æÈÝÁ¿
cudaFree(d_input);
cudaFree(d_partial_sums_and_total);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
template<class DType>
__global__ void block_sum(const DType *input,
DType *per_block_results,
const size_t n)
{
extern __shared__ DType sdata[];
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
// Ò»¸öÏ̸߳ºÔð°ÑÒ»¸öÔªËØ´ÓÈ«¾ÖÄÚ´æÔØÈëµ½¹²ÏíÄÚ´æ
DType x = 0;
if(i < n){
x = input[i];
}
sdata[threadIdx.x] = x;
__syncthreads();//µÈ´ýËùÓÐḬ̈߳Ñ×Ô¼º¸ºÔðµÄÔªËØÔØÈëµ½¹²ÏíÄÚ´æ
// ¿éÄÚ½øÐкϲ¢²Ù×÷£¬Ã¿´ÎºÏ²¢±äΪһ°ë.×¢ÒâthreadIdx.xÊÇ¿éÄÚµÄÆ«ÒÆ£¬ÉÏÃæËã³öµÄiÊÇÈ«¾ÖµÄÆ«ÒÆ¡£
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(threadIdx.x < offset)//¿ØÖÆÖ»ÓÐijЩÏ̲߳ŽøÐвÙ×÷¡£
{
sdata[threadIdx.x] += sdata[threadIdx.x + offset];
}
__syncthreads();
}
//ÿ¸ö¿éµÄÏß³Ì0¸ºÔð´æ·Å¿éÄÚÇóºÍµÄ½á¹û
if(threadIdx.x == 0)
{
per_block_results[blockIdx.x] = sdata[0];
}
}
int main()
{
const int num_elements=1024; //ÉèÖÃÊý×鳤¶È
//·ÖÅäÄÚ´æ
float h_input[num_elements];
for (int i = 0; i < num_elements; i++){
h_input[i]=1.0f;
}
float *d_input = 0;
hipMalloc((void**)&d_input, sizeof(float) * num_elements);
hipMemcpy(d_input, &h_input, sizeof(float) * num_elements, hipMemcpyHostToDevice);
const size_t block_size = 512;//Ï߳̿éµÄ´óС¡£Ä¿Ç°ÓÐЩgpuµÄÏ߳̿é×î´óΪ512£¬ÓÐЩΪ1024.
const size_t num_blocks = (num_elements/block_size) + ((num_elements%block_size) ? 1 : 0);
float *d_partial_sums_and_total = 0;//Ò»¸öÏ߳̿éÒ»¸öºÍ£¬ÁíÍâ¼ÓÒ»¸öÔªËØ£¬´æ·ÅËùÓÐÏ߳̿éµÄºÍ¡£
hipMalloc((void**)&d_partial_sums_and_total, sizeof(float) * (num_blocks + 1));
//°Ñÿ¸öÏ߳̿éµÄºÍÇó³öÀ´
block_sum<<<num_blocks,block_size,block_size *sizeof(float)>>>(d_input, d_partial_sums_and_total, num_elements);
//ÔÙ´ÎÓÃÒ»¸öÏ߳̿é°ÑÉÏÒ»²½µÄ½á¹ûÇóºÍ¡£
//×¢ÒâÕâÀïÓиöÏÞÖÆ£¬ÉÏÒ»²½Ï߳̿éµÄÊýÁ¿£¬±ØÐë²»´óÓÚÒ»¸öÏ߳̿éÏ̵߳Ä×î´óÊýÁ¿£¬ÒòΪÕâÒ»²½µÃ°ÑÉÏÒ»²½µÄ½á¹û·ÅÔÚÒ»¸öÏ߳̿é²Ù×÷¡£
//¼´num_blocks²»ÄÜ´óÓÚÏ߳̿éµÄ×î´óÏß³ÌÊýÁ¿¡£
block_sum<<<1,num_blocks,num_blocks * sizeof(float)>>>(d_partial_sums_and_total, d_partial_sums_and_total + num_blocks, num_blocks);
float device_result = 0;
hipMemcpy(&device_result, d_partial_sums_and_total + num_blocks, sizeof(float), hipMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// ÊÍ·ÅÏÔ´æÈÝÁ¿
hipFree(d_input);
hipFree(d_partial_sums_and_total);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
template<class DType>
__global__ void block_sum(const DType *input,
DType *per_block_results,
const size_t n)
{
extern __shared__ DType sdata[];
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
// Ò»¸öÏ̸߳ºÔð°ÑÒ»¸öÔªËØ´ÓÈ«¾ÖÄÚ´æÔØÈëµ½¹²ÏíÄÚ´æ
DType x = 0;
if(i < n){
x = input[i];
}
sdata[threadIdx.x] = x;
__syncthreads();//µÈ´ýËùÓÐḬ̈߳Ñ×Ô¼º¸ºÔðµÄÔªËØÔØÈëµ½¹²ÏíÄÚ´æ
// ¿éÄÚ½øÐкϲ¢²Ù×÷£¬Ã¿´ÎºÏ²¢±äΪһ°ë.×¢ÒâthreadIdx.xÊÇ¿éÄÚµÄÆ«ÒÆ£¬ÉÏÃæËã³öµÄiÊÇÈ«¾ÖµÄÆ«ÒÆ¡£
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(threadIdx.x < offset)//¿ØÖÆÖ»ÓÐijЩÏ̲߳ŽøÐвÙ×÷¡£
{
sdata[threadIdx.x] += sdata[threadIdx.x + offset];
}
__syncthreads();
}
//ÿ¸ö¿éµÄÏß³Ì0¸ºÔð´æ·Å¿éÄÚÇóºÍµÄ½á¹û
if(threadIdx.x == 0)
{
per_block_results[blockIdx.x] = sdata[0];
}
}
int main()
{
const int num_elements=1024; //ÉèÖÃÊý×鳤¶È
//·ÖÅäÄÚ´æ
float h_input[num_elements];
for (int i = 0; i < num_elements; i++){
h_input[i]=1.0f;
}
float *d_input = 0;
hipMalloc((void**)&d_input, sizeof(float) * num_elements);
hipMemcpy(d_input, &h_input, sizeof(float) * num_elements, hipMemcpyHostToDevice);
const size_t block_size = 512;//Ï߳̿éµÄ´óС¡£Ä¿Ç°ÓÐЩgpuµÄÏ߳̿é×î´óΪ512£¬ÓÐЩΪ1024.
const size_t num_blocks = (num_elements/block_size) + ((num_elements%block_size) ? 1 : 0);
float *d_partial_sums_and_total = 0;//Ò»¸öÏ߳̿éÒ»¸öºÍ£¬ÁíÍâ¼ÓÒ»¸öÔªËØ£¬´æ·ÅËùÓÐÏ߳̿éµÄºÍ¡£
hipMalloc((void**)&d_partial_sums_and_total, sizeof(float) * (num_blocks + 1));
//°Ñÿ¸öÏ߳̿éµÄºÍÇó³öÀ´
block_sum<<<num_blocks,block_size,block_size *sizeof(float)>>>(d_input, d_partial_sums_and_total, num_elements);
//ÔÙ´ÎÓÃÒ»¸öÏ߳̿é°ÑÉÏÒ»²½µÄ½á¹ûÇóºÍ¡£
//×¢ÒâÕâÀïÓиöÏÞÖÆ£¬ÉÏÒ»²½Ï߳̿éµÄÊýÁ¿£¬±ØÐë²»´óÓÚÒ»¸öÏ߳̿éÏ̵߳Ä×î´óÊýÁ¿£¬ÒòΪÕâÒ»²½µÃ°ÑÉÏÒ»²½µÄ½á¹û·ÅÔÚÒ»¸öÏ߳̿é²Ù×÷¡£
//¼´num_blocks²»ÄÜ´óÓÚÏ߳̿éµÄ×î´óÏß³ÌÊýÁ¿¡£
block_sum<<<1,num_blocks,num_blocks * sizeof(float)>>>(d_partial_sums_and_total, d_partial_sums_and_total + num_blocks, num_blocks);
float device_result = 0;
hipMemcpy(&device_result, d_partial_sums_and_total + num_blocks, sizeof(float), hipMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// ÊÍ·ÅÏÔ´æÈÝÁ¿
hipFree(d_input);
hipFree(d_partial_sums_and_total);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z9block_sumIfEvPKT_PS0_m,"axG",@progbits,_Z9block_sumIfEvPKT_PS0_m,comdat
.protected _Z9block_sumIfEvPKT_PS0_m
.globl _Z9block_sumIfEvPKT_PS0_m
.p2align 8
.type _Z9block_sumIfEvPKT_PS0_m,@function
_Z9block_sumIfEvPKT_PS0_m:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_4:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_3
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9block_sumIfEvPKT_PS0_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9block_sumIfEvPKT_PS0_m,"axG",@progbits,_Z9block_sumIfEvPKT_PS0_m,comdat
.Lfunc_end0:
.size _Z9block_sumIfEvPKT_PS0_m, .Lfunc_end0-_Z9block_sumIfEvPKT_PS0_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9block_sumIfEvPKT_PS0_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9block_sumIfEvPKT_PS0_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
template<class DType>
__global__ void block_sum(const DType *input,
DType *per_block_results,
const size_t n)
{
extern __shared__ DType sdata[];
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
// Ò»¸öÏ̸߳ºÔð°ÑÒ»¸öÔªËØ´ÓÈ«¾ÖÄÚ´æÔØÈëµ½¹²ÏíÄÚ´æ
DType x = 0;
if(i < n){
x = input[i];
}
sdata[threadIdx.x] = x;
__syncthreads();//µÈ´ýËùÓÐḬ̈߳Ñ×Ô¼º¸ºÔðµÄÔªËØÔØÈëµ½¹²ÏíÄÚ´æ
// ¿éÄÚ½øÐкϲ¢²Ù×÷£¬Ã¿´ÎºÏ²¢±äΪһ°ë.×¢ÒâthreadIdx.xÊÇ¿éÄÚµÄÆ«ÒÆ£¬ÉÏÃæËã³öµÄiÊÇÈ«¾ÖµÄÆ«ÒÆ¡£
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(threadIdx.x < offset)//¿ØÖÆÖ»ÓÐijЩÏ̲߳ŽøÐвÙ×÷¡£
{
sdata[threadIdx.x] += sdata[threadIdx.x + offset];
}
__syncthreads();
}
//ÿ¸ö¿éµÄÏß³Ì0¸ºÔð´æ·Å¿éÄÚÇóºÍµÄ½á¹û
if(threadIdx.x == 0)
{
per_block_results[blockIdx.x] = sdata[0];
}
}
int main()
{
const int num_elements=1024; //ÉèÖÃÊý×鳤¶È
//·ÖÅäÄÚ´æ
float h_input[num_elements];
for (int i = 0; i < num_elements; i++){
h_input[i]=1.0f;
}
float *d_input = 0;
hipMalloc((void**)&d_input, sizeof(float) * num_elements);
hipMemcpy(d_input, &h_input, sizeof(float) * num_elements, hipMemcpyHostToDevice);
const size_t block_size = 512;//Ï߳̿éµÄ´óС¡£Ä¿Ç°ÓÐЩgpuµÄÏ߳̿é×î´óΪ512£¬ÓÐЩΪ1024.
const size_t num_blocks = (num_elements/block_size) + ((num_elements%block_size) ? 1 : 0);
float *d_partial_sums_and_total = 0;//Ò»¸öÏ߳̿éÒ»¸öºÍ£¬ÁíÍâ¼ÓÒ»¸öÔªËØ£¬´æ·ÅËùÓÐÏ߳̿éµÄºÍ¡£
hipMalloc((void**)&d_partial_sums_and_total, sizeof(float) * (num_blocks + 1));
//°Ñÿ¸öÏ߳̿éµÄºÍÇó³öÀ´
block_sum<<<num_blocks,block_size,block_size *sizeof(float)>>>(d_input, d_partial_sums_and_total, num_elements);
//ÔÙ´ÎÓÃÒ»¸öÏ߳̿é°ÑÉÏÒ»²½µÄ½á¹ûÇóºÍ¡£
//×¢ÒâÕâÀïÓиöÏÞÖÆ£¬ÉÏÒ»²½Ï߳̿éµÄÊýÁ¿£¬±ØÐë²»´óÓÚÒ»¸öÏ߳̿éÏ̵߳Ä×î´óÊýÁ¿£¬ÒòΪÕâÒ»²½µÃ°ÑÉÏÒ»²½µÄ½á¹û·ÅÔÚÒ»¸öÏ߳̿é²Ù×÷¡£
//¼´num_blocks²»ÄÜ´óÓÚÏ߳̿éµÄ×î´óÏß³ÌÊýÁ¿¡£
block_sum<<<1,num_blocks,num_blocks * sizeof(float)>>>(d_partial_sums_and_total, d_partial_sums_and_total + num_blocks, num_blocks);
float device_result = 0;
hipMemcpy(&device_result, d_partial_sums_and_total + num_blocks, sizeof(float), hipMemcpyDeviceToHost);
std::cout << "Device sum: " << device_result << std::endl;
// ÊÍ·ÅÏÔ´æÈÝÁ¿
hipFree(d_input);
hipFree(d_partial_sums_and_total);
return 0;
} | .text
.file "kernel0.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $4232, %rsp # imm = 0x1088
.cfi_def_cfa_offset 4256
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, 128(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB0_1
# %bb.2:
movabsq $4294967298, %rbx # imm = 0x100000002
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $12, %esi
callq hipMalloc
leaq 510(%rbx), %rdx
movl $2048, %r8d # imm = 0x800
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $1024, 72(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9block_sumIfEvPKT_PS0_m, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
leaq -1(%rbx), %rdi
movl $8, %r8d
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
addq $8, %rax
movq %rax, 80(%rsp)
movq $2, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9block_sumIfEvPKT_PS0_m, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movl $0, 96(%rsp)
movq 8(%rsp), %rsi
addq $8, %rsi
leaq 96(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4232, %rsp # imm = 0x1088
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 4256
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__block_sumIfEvPKT_PS0_m,"axG",@progbits,_Z24__device_stub__block_sumIfEvPKT_PS0_m,comdat
.weak _Z24__device_stub__block_sumIfEvPKT_PS0_m # -- Begin function _Z24__device_stub__block_sumIfEvPKT_PS0_m
.p2align 4, 0x90
.type _Z24__device_stub__block_sumIfEvPKT_PS0_m,@function
_Z24__device_stub__block_sumIfEvPKT_PS0_m: # @_Z24__device_stub__block_sumIfEvPKT_PS0_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_sumIfEvPKT_PS0_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__block_sumIfEvPKT_PS0_m, .Lfunc_end1-_Z24__device_stub__block_sumIfEvPKT_PS0_m
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9block_sumIfEvPKT_PS0_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9block_sumIfEvPKT_PS0_m,@object # @_Z9block_sumIfEvPKT_PS0_m
.section .rodata._Z9block_sumIfEvPKT_PS0_m,"aG",@progbits,_Z9block_sumIfEvPKT_PS0_m,comdat
.weak _Z9block_sumIfEvPKT_PS0_m
.p2align 3, 0x0
_Z9block_sumIfEvPKT_PS0_m:
.quad _Z24__device_stub__block_sumIfEvPKT_PS0_m
.size _Z9block_sumIfEvPKT_PS0_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device sum: "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9block_sumIfEvPKT_PS0_m"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__block_sumIfEvPKT_PS0_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9block_sumIfEvPKT_PS0_m
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9block_sumIfEvPKT_PS0_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R6, c[0x0][0x0], R7 ; /* 0x0000000006007a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @!P0 LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000028a11 */
/* 0x000fc800078210ff */
/*0080*/ @!P0 LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P1 ; /* 0x0000590000038a11 */
/* 0x000fe200008f14ff */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fcc00078e00ff */
/*00a0*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*00c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00f0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0041e80000004800 */
/*0100*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0110*/ @!P1 BRA 0x1e0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26070 */
/*0150*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x000fe200078e0200 */
/*0160*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0170*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0180*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0190*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fca0000000000 */
/*01a0*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*01b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01c0*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*01d0*/ @P1 BRA 0x140 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*01f0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fca00078e0003 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z9block_sumIfEvPKT_PS0_m,"axG",@progbits,_Z9block_sumIfEvPKT_PS0_m,comdat
.protected _Z9block_sumIfEvPKT_PS0_m
.globl _Z9block_sumIfEvPKT_PS0_m
.p2align 8
.type _Z9block_sumIfEvPKT_PS0_m,@function
_Z9block_sumIfEvPKT_PS0_m:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_mov_b32_e32 v2, 0
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v2, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
.LBB0_4:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_3
.LBB0_7:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9block_sumIfEvPKT_PS0_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z9block_sumIfEvPKT_PS0_m,"axG",@progbits,_Z9block_sumIfEvPKT_PS0_m,comdat
.Lfunc_end0:
.size _Z9block_sumIfEvPKT_PS0_m, .Lfunc_end0-_Z9block_sumIfEvPKT_PS0_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9block_sumIfEvPKT_PS0_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9block_sumIfEvPKT_PS0_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b8101_00000000-6_kernel0.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z9block_sumIfEvPKT_PS0_m,"axG",@progbits,_Z9block_sumIfEvPKT_PS0_m,comdat
.weak _Z9block_sumIfEvPKT_PS0_m
.type _Z9block_sumIfEvPKT_PS0_m, @function
_Z9block_sumIfEvPKT_PS0_m:
.LFB3999:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9block_sumIfEvPKT_PS0_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3999:
.size _Z9block_sumIfEvPKT_PS0_m, .-_Z9block_sumIfEvPKT_PS0_m
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Device sum: "
.text
.globl main
.type main, @function
main:
.LFB3671:
.cfi_startproc
endbr64
subq $4096, %rsp
.cfi_def_cfa_offset 4104
orq $0, (%rsp)
subq $72, %rsp
.cfi_def_cfa_offset 4176
movq %fs:40, %rax
movq %rax, 4152(%rsp)
xorl %eax, %eax
leaq 48(%rsp), %rax
leaq 4144(%rsp), %rdx
movss .LC0(%rip), %xmm0
.L10:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L10
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $4096, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl $512, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $2, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $2048, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L11:
movl $2, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $8, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $0x00000000, 36(%rsp)
movq 16(%rsp), %rax
leaq 8(%rax), %rsi
leaq 36(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4152(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $4168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl $1024, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z9block_sumIfEvPKT_PS0_m
jmp .L11
.L17:
movq 16(%rsp), %rdi
leaq 8(%rdi), %rsi
movl $2, %edx
call _Z9block_sumIfEvPKT_PS0_m
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9block_sumIfEvPKT_PS0_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9block_sumIfEvPKT_PS0_m(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel0.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $4232, %rsp # imm = 0x1088
.cfi_def_cfa_offset 4256
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, 128(%rsp,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1024, %rax # imm = 0x400
jne .LBB0_1
# %bb.2:
movabsq $4294967298, %rbx # imm = 0x100000002
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movq 16(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movl $1, %ecx
callq hipMemcpy
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $12, %esi
callq hipMalloc
leaq 510(%rbx), %rdx
movl $2048, %r8d # imm = 0x800
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq $1024, 72(%rsp) # imm = 0x400
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9block_sumIfEvPKT_PS0_m, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
leaq -1(%rbx), %rdi
movl $8, %r8d
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_6
# %bb.5:
movq 8(%rsp), %rax
movq %rax, 88(%rsp)
addq $8, %rax
movq %rax, 80(%rsp)
movq $2, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9block_sumIfEvPKT_PS0_m, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_6:
movl $0, 96(%rsp)
movq 8(%rsp), %rsi
addq $8, %rsi
leaq 96(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 96(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $4232, %rsp # imm = 0x1088
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 4256
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .text._Z24__device_stub__block_sumIfEvPKT_PS0_m,"axG",@progbits,_Z24__device_stub__block_sumIfEvPKT_PS0_m,comdat
.weak _Z24__device_stub__block_sumIfEvPKT_PS0_m # -- Begin function _Z24__device_stub__block_sumIfEvPKT_PS0_m
.p2align 4, 0x90
.type _Z24__device_stub__block_sumIfEvPKT_PS0_m,@function
_Z24__device_stub__block_sumIfEvPKT_PS0_m: # @_Z24__device_stub__block_sumIfEvPKT_PS0_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_sumIfEvPKT_PS0_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z24__device_stub__block_sumIfEvPKT_PS0_m, .Lfunc_end1-_Z24__device_stub__block_sumIfEvPKT_PS0_m
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9block_sumIfEvPKT_PS0_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9block_sumIfEvPKT_PS0_m,@object # @_Z9block_sumIfEvPKT_PS0_m
.section .rodata._Z9block_sumIfEvPKT_PS0_m,"aG",@progbits,_Z9block_sumIfEvPKT_PS0_m,comdat
.weak _Z9block_sumIfEvPKT_PS0_m
.p2align 3, 0x0
_Z9block_sumIfEvPKT_PS0_m:
.quad _Z24__device_stub__block_sumIfEvPKT_PS0_m
.size _Z9block_sumIfEvPKT_PS0_m, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device sum: "
.size .L.str, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9block_sumIfEvPKT_PS0_m"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__block_sumIfEvPKT_PS0_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9block_sumIfEvPKT_PS0_m
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void IntDataPointIdentity(int *size, const int *inputX, const int *inputY, int *outputX, int *outputY, int *length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
// copy int array
const int *inArrayBody = &inputX[ix* *length];
int *outArrayBody = &outputX[ix* *length];
for (long i = 0; i < *length; i++) {
outArrayBody[i] = inArrayBody[i];
}
// copy int scalar value
outputY[ix] = inputY[ix];
}
} | code for sm_80
Function : _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0070*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e240000002500 */
/*0080*/ IMAD.WIDE.U32 R8, R9, c[0x0][0x0], R2 ; /* 0x0000000009087a25 */
/* 0x001fe200078e0002 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R5 ; /* 0x0000001fff037819 */
/* 0x004fc80000011405 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fc80003f06070 */
/*00b0*/ ISETP.GE.AND.EX P0, PT, R9, R3, PT, P0 ; /* 0x000000030900720c */
/* 0x000fda0003f06300 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff047624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fca00078e00ff */
/*00f0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.SHL.U32 R6, R8.reuse, 0x4, RZ ; /* 0x0000000408067824 */
/* 0x040fe200078e00ff */
/*0110*/ SHF.L.U64.HI R0, R8, 0x2, R9 ; /* 0x0000000208007819 */
/* 0x000fc80000010209 */
/*0120*/ IADD3 R2, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006027a10 */
/* 0x000fc80007f3e0ff */
/*0130*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000037a10 */
/* 0x000fe40000ffe4ff */
/*0140*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x004fda0003f06270 */
/*0150*/ @!P0 BRA 0x350 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0160*/ SHF.R.S32.HI R7, RZ, 0x1f, R11 ; /* 0x0000001fff077819 */
/* 0x000fe2000001140b */
/*0170*/ IMAD R9, R9, R11.reuse, RZ ; /* 0x0000000b09097224 */
/* 0x080fe200078e02ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ IMAD.WIDE.U32 R10, R8, R11, RZ ; /* 0x0000000b080a7225 */
/* 0x000fe200078e00ff */
/*01a0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc60008000000 */
/*01b0*/ IMAD R9, R8, R7, R9 ; /* 0x0000000708097224 */
/* 0x000fe400078e0209 */
/*01c0*/ IMAD.SHL.U32 R7, R10, 0x4, RZ ; /* 0x000000040a077824 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.IADD R9, R11, 0x1, R9 ; /* 0x000000010b097824 */
/* 0x000fc600078e0209 */
/*01e0*/ IADD3 R13, P0, R7.reuse, c[0x0][0x178], RZ ; /* 0x00005e00070d7a10 */
/* 0x040fe40007f1e0ff */
/*01f0*/ IADD3 R11, P1, R7, c[0x0][0x168], RZ ; /* 0x00005a00070b7a10 */
/* 0x000fe40007f3e0ff */
/*0200*/ SHF.L.U64.HI R10, R10, 0x2, R9 ; /* 0x000000020a0a7819 */
/* 0x000fc80000010209 */
/*0210*/ IADD3.X R14, R10.reuse, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a0e7a10 */
/* 0x040fe400007fe4ff */
/*0220*/ IADD3.X R12, R10, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000a0c7a10 */
/* 0x000fc60000ffe4ff */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000b */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R12 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000c */
/*0250*/ LDG.E R7, [R8.64] ; /* 0x0000000608077981 */
/* 0x0000a4000c1e1900 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x001fe400078e000d */
/*0270*/ IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000e */
/*0280*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0041e8000c101906 */
/*0290*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*02b0*/ IADD3 R13, P1, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe40007f3e0ff */
/*02c0*/ IADD3 R11, P2, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe20007f5e0ff */
/*02d0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*02e0*/ IMAD.X R14, RZ, RZ, R14, P1 ; /* 0x000000ffff0e7224 */
/* 0x000fc400008e060e */
/*02f0*/ IMAD.X R12, RZ, RZ, R12, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400010e060c */
/*0300*/ IMAD.U32 R15, RZ, RZ, UR5 ; /* 0x00000005ff0f7e24 */
/* 0x000fe2000f8e00ff */
/*0310*/ ISETP.LE.U32.AND P0, PT, R10, UR4, PT ; /* 0x000000040a007c0c */
/* 0x004fe4000bf03070 */
/*0320*/ SHF.R.S32.HI R10, RZ, 0x1f, R10 ; /* 0x0000001fff0a7819 */
/* 0x000fc8000001140a */
/*0330*/ ISETP.GE.AND.EX P0, PT, R15, R10, PT, P0 ; /* 0x0000000a0f00720c */
/* 0x000fda0003f06300 */
/*0340*/ @!P0 BRA 0x230 ; /* 0xfffffee000008947 */
/* 0x001fea000383ffff */
/*0350*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IADD3 R6, P0, R6, c[0x0][0x180], RZ ; /* 0x0000600006067a10 */
/* 0x000fc80007f1e0ff */
/*0370*/ IADD3.X R7, R0, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610000077a10 */
/* 0x000fca00007fe4ff */
/*0380*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x004fe2000c101906 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void IntDataPointIdentity(int *size, const int *inputX, const int *inputY, int *outputX, int *outputY, int *length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
// copy int array
const int *inArrayBody = &inputX[ix* *length];
int *outArrayBody = &outputX[ix* *length];
for (long i = 0; i < *length; i++) {
outArrayBody[i] = inArrayBody[i];
}
// copy int scalar value
outputY[ix] = inputY[ix];
}
} | .file "tmpxft_00036ff5_00000000-6_IntDataPointIdentity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_
.type _Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_, @function
_Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20IntDataPointIdentityPiPKiS1_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_, .-_Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_
.globl _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.type _Z20IntDataPointIdentityPiPKiS1_S_S_S_, @function
_Z20IntDataPointIdentityPiPKiS1_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20IntDataPointIdentityPiPKiS1_S_S_S_, .-_Z20IntDataPointIdentityPiPKiS1_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20IntDataPointIdentityPiPKiS1_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20IntDataPointIdentityPiPKiS1_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void IntDataPointIdentity(int *size, const int *inputX, const int *inputY, int *outputX, int *outputY, int *length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
// copy int array
const int *inArrayBody = &inputX[ix* *length];
int *outArrayBody = &outputX[ix* *length];
for (long i = 0; i < *length; i++) {
outArrayBody[i] = inArrayBody[i];
}
// copy int scalar value
outputY[ix] = inputY[ix];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IntDataPointIdentity(int *size, const int *inputX, const int *inputY, int *outputX, int *outputY, int *length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
// copy int array
const int *inArrayBody = &inputX[ix* *length];
int *outArrayBody = &outputX[ix* *length];
for (long i = 0; i < *length; i++) {
outArrayBody[i] = inArrayBody[i];
}
// copy int scalar value
outputY[ix] = inputY[ix];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IntDataPointIdentity(int *size, const int *inputX, const int *inputY, int *outputX, int *outputY, int *length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
// copy int array
const int *inArrayBody = &inputX[ix* *length];
int *outArrayBody = &outputX[ix* *length];
for (long i = 0; i < *length; i++) {
outArrayBody[i] = inArrayBody[i];
}
// copy int scalar value
outputY[ix] = inputY[ix];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.globl _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.p2align 8
.type _Z20IntDataPointIdentityPiPKiS1_S_S_S_,@function
_Z20IntDataPointIdentityPiPKiS1_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x3c
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s15, v[0:1]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s3, s2, 31
s_load_b64 s[6:7], s[0:1], 0x8
v_mul_lo_u32 v4, v3, s2
v_mul_lo_u32 v5, v2, s3
v_mad_u64_u32 v[0:1], null, v2, s2, 0
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v1, v5, v4
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_mov_b64 s[6:7], 0
.p2align 6
.LBB0_3:
global_load_b32 v7, v[0:1], off
s_add_u32 s6, s6, 1
v_add_co_u32 v0, vcc_lo, v0, 4
s_addc_u32 s7, s7, 0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v7, off
global_load_b32 v7, v6, s[4:5]
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i64_e64 s2, s[6:7], v[7:8]
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB0_3
.LBB0_4:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20IntDataPointIdentityPiPKiS1_S_S_S_, .Lfunc_end0-_Z20IntDataPointIdentityPiPKiS1_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20IntDataPointIdentityPiPKiS1_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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