system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void IntDataPointIdentity(int *size, const int *inputX, const int *inputY, int *outputX, int *outputY, int *length) {
const long ix = threadIdx.x + blockIdx.x * (long)blockDim.x;
if (ix < *size) {
// copy int array
const int *inArrayBody = &inputX[ix* *length];
int *outArrayBody = &outputX[ix* *length];
for (long i = 0; i < *length; i++) {
outArrayBody[i] = inArrayBody[i];
}
// copy int scalar value
outputY[ix] = inputY[ix];
}
} | .text
.file "IntDataPointIdentity.hip"
.globl _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_ # -- Begin function _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.p2align 4, 0x90
.type _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_,@function
_Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_: # @_Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20IntDataPointIdentityPiPKiS1_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_, .Lfunc_end0-_Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20IntDataPointIdentityPiPKiS1_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20IntDataPointIdentityPiPKiS1_S_S_S_,@object # @_Z20IntDataPointIdentityPiPKiS1_S_S_S_
.section .rodata,"a",@progbits
.globl _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.p2align 3, 0x0
_Z20IntDataPointIdentityPiPKiS1_S_S_S_:
.quad _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.size _Z20IntDataPointIdentityPiPKiS1_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20IntDataPointIdentityPiPKiS1_S_S_S_"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0070*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e240000002500 */
/*0080*/ IMAD.WIDE.U32 R8, R9, c[0x0][0x0], R2 ; /* 0x0000000009087a25 */
/* 0x001fe200078e0002 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R5 ; /* 0x0000001fff037819 */
/* 0x004fc80000011405 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fc80003f06070 */
/*00b0*/ ISETP.GE.AND.EX P0, PT, R9, R3, PT, P0 ; /* 0x000000030900720c */
/* 0x000fda0003f06300 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff047624 */
/* 0x000fe400078e00ff */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff057624 */
/* 0x000fca00078e00ff */
/*00f0*/ LDG.E R11, [R4.64] ; /* 0x00000006040b7981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.SHL.U32 R6, R8.reuse, 0x4, RZ ; /* 0x0000000408067824 */
/* 0x040fe200078e00ff */
/*0110*/ SHF.L.U64.HI R0, R8, 0x2, R9 ; /* 0x0000000208007819 */
/* 0x000fc80000010209 */
/*0120*/ IADD3 R2, P1, R6, c[0x0][0x170], RZ ; /* 0x00005c0006027a10 */
/* 0x000fc80007f3e0ff */
/*0130*/ IADD3.X R3, R0, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0000037a10 */
/* 0x000fe40000ffe4ff */
/*0140*/ ISETP.GE.AND P0, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x004fda0003f06270 */
/*0150*/ @!P0 BRA 0x350 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0160*/ SHF.R.S32.HI R7, RZ, 0x1f, R11 ; /* 0x0000001fff077819 */
/* 0x000fe2000001140b */
/*0170*/ IMAD R9, R9, R11.reuse, RZ ; /* 0x0000000b09097224 */
/* 0x080fe200078e02ff */
/*0180*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0190*/ IMAD.WIDE.U32 R10, R8, R11, RZ ; /* 0x0000000b080a7225 */
/* 0x000fe200078e00ff */
/*01a0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fc60008000000 */
/*01b0*/ IMAD R9, R8, R7, R9 ; /* 0x0000000708097224 */
/* 0x000fe400078e0209 */
/*01c0*/ IMAD.SHL.U32 R7, R10, 0x4, RZ ; /* 0x000000040a077824 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.IADD R9, R11, 0x1, R9 ; /* 0x000000010b097824 */
/* 0x000fc600078e0209 */
/*01e0*/ IADD3 R13, P0, R7.reuse, c[0x0][0x178], RZ ; /* 0x00005e00070d7a10 */
/* 0x040fe40007f1e0ff */
/*01f0*/ IADD3 R11, P1, R7, c[0x0][0x168], RZ ; /* 0x00005a00070b7a10 */
/* 0x000fe40007f3e0ff */
/*0200*/ SHF.L.U64.HI R10, R10, 0x2, R9 ; /* 0x000000020a0a7819 */
/* 0x000fc80000010209 */
/*0210*/ IADD3.X R14, R10.reuse, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f000a0e7a10 */
/* 0x040fe400007fe4ff */
/*0220*/ IADD3.X R12, R10, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b000a0c7a10 */
/* 0x000fc60000ffe4ff */
/*0230*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000b */
/*0240*/ IMAD.MOV.U32 R9, RZ, RZ, R12 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000c */
/*0250*/ LDG.E R7, [R8.64] ; /* 0x0000000608077981 */
/* 0x0000a4000c1e1900 */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, R13 ; /* 0x000000ffff087224 */
/* 0x001fe400078e000d */
/*0270*/ IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff097224 */
/* 0x000fca00078e000e */
/*0280*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0041e8000c101906 */
/*0290*/ LDG.E R10, [R4.64] ; /* 0x00000006040a7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*02b0*/ IADD3 R13, P1, R13, 0x4, RZ ; /* 0x000000040d0d7810 */
/* 0x000fe40007f3e0ff */
/*02c0*/ IADD3 R11, P2, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fe20007f5e0ff */
/*02d0*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe400087fe43f */
/*02e0*/ IMAD.X R14, RZ, RZ, R14, P1 ; /* 0x000000ffff0e7224 */
/* 0x000fc400008e060e */
/*02f0*/ IMAD.X R12, RZ, RZ, R12, P2 ; /* 0x000000ffff0c7224 */
/* 0x000fe400010e060c */
/*0300*/ IMAD.U32 R15, RZ, RZ, UR5 ; /* 0x00000005ff0f7e24 */
/* 0x000fe2000f8e00ff */
/*0310*/ ISETP.LE.U32.AND P0, PT, R10, UR4, PT ; /* 0x000000040a007c0c */
/* 0x004fe4000bf03070 */
/*0320*/ SHF.R.S32.HI R10, RZ, 0x1f, R10 ; /* 0x0000001fff0a7819 */
/* 0x000fc8000001140a */
/*0330*/ ISETP.GE.AND.EX P0, PT, R15, R10, PT, P0 ; /* 0x0000000a0f00720c */
/* 0x000fda0003f06300 */
/*0340*/ @!P0 BRA 0x230 ; /* 0xfffffee000008947 */
/* 0x001fea000383ffff */
/*0350*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IADD3 R6, P0, R6, c[0x0][0x180], RZ ; /* 0x0000600006067a10 */
/* 0x000fc80007f1e0ff */
/*0370*/ IADD3.X R7, R0, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610000077a10 */
/* 0x000fca00007fe4ff */
/*0380*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x004fe2000c101906 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ BRA 0x3a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.globl _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.p2align 8
.type _Z20IntDataPointIdentityPiPKiS1_S_S_S_,@function
_Z20IntDataPointIdentityPiPKiS1_S_S_S_:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x3c
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_and_b32 s3, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s3, s15, v[0:1]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b64 s[4:5], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_ashr_i32 s3, s2, 31
s_load_b64 s[6:7], s[0:1], 0x8
v_mul_lo_u32 v4, v3, s2
v_mul_lo_u32 v5, v2, s3
v_mad_u64_u32 v[0:1], null, v2, s2, 0
s_load_b64 s[2:3], s[0:1], 0x18
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v1, v1, v5, v4
v_lshlrev_b64 v[4:5], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_mov_b64 s[6:7], 0
.p2align 6
.LBB0_3:
global_load_b32 v7, v[0:1], off
s_add_u32 s6, s6, 1
v_add_co_u32 v0, vcc_lo, v0, 4
s_addc_u32 s7, s7, 0
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v7, off
global_load_b32 v7, v6, s[4:5]
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i64_e64 s2, s[6:7], v[7:8]
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccz .LBB0_3
.LBB0_4:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_load_b64 s[0:1], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20IntDataPointIdentityPiPKiS1_S_S_S_, .Lfunc_end0-_Z20IntDataPointIdentityPiPKiS1_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20IntDataPointIdentityPiPKiS1_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00036ff5_00000000-6_IntDataPointIdentity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_
.type _Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_, @function
_Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20IntDataPointIdentityPiPKiS1_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_, .-_Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_
.globl _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.type _Z20IntDataPointIdentityPiPKiS1_S_S_S_, @function
_Z20IntDataPointIdentityPiPKiS1_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z52__device_stub__Z20IntDataPointIdentityPiPKiS1_S_S_S_PiPKiS1_S_S_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20IntDataPointIdentityPiPKiS1_S_S_S_, .-_Z20IntDataPointIdentityPiPKiS1_S_S_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20IntDataPointIdentityPiPKiS1_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20IntDataPointIdentityPiPKiS1_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "IntDataPointIdentity.hip"
.globl _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_ # -- Begin function _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.p2align 4, 0x90
.type _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_,@function
_Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_: # @_Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20IntDataPointIdentityPiPKiS1_S_S_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_, .Lfunc_end0-_Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20IntDataPointIdentityPiPKiS1_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20IntDataPointIdentityPiPKiS1_S_S_S_,@object # @_Z20IntDataPointIdentityPiPKiS1_S_S_S_
.section .rodata,"a",@progbits
.globl _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.p2align 3, 0x0
_Z20IntDataPointIdentityPiPKiS1_S_S_S_:
.quad _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.size _Z20IntDataPointIdentityPiPKiS1_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20IntDataPointIdentityPiPKiS1_S_S_S_"
.size .L__unnamed_1, 39
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__IntDataPointIdentityPiPKiS1_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20IntDataPointIdentityPiPKiS1_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void A_for_lightning_estimation(float* rho, float* N, int npix, float* A) {
int i = blockIdx.x*blockDim.x + threadIdx.x; // pixel index
int c = blockIdx.y*blockDim.y + threadIdx.y; // channel index
int h = blockIdx.z*blockDim.z + threadIdx.z; // harmonic index
if (i < npix) {
A[c*npix * 4 + h*npix + i] = rho[c*npix + i] * N[h*npix + i];
}
} | code for sm_80
Function : _Z26A_for_lightning_estimationPfS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*00a0*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e680000002300 */
/*00b0*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e620000002700 */
/*00c0*/ IMAD R2, R3, c[0x0][0x4], R2 ; /* 0x0000010003027a24 */
/* 0x001fc800078e0202 */
/*00d0*/ IMAD R7, R2, c[0x0][0x170], RZ ; /* 0x00005c0002077a24 */
/* 0x000fe400078e02ff */
/*00e0*/ IMAD R3, R5, c[0x0][0x8], R4 ; /* 0x0000020005037a24 */
/* 0x002fc600078e0204 */
/*00f0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD R6, R3, c[0x0][0x170], R0 ; /* 0x00005c0003067a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.WIDE R4, R6, R9, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0209 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ LEA R6, R7, R6, 0x2 ; /* 0x0000000607067211 */
/* 0x000fca00078e10ff */
/*0160*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0209 */
/*0170*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0180*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void A_for_lightning_estimation(float* rho, float* N, int npix, float* A) {
int i = blockIdx.x*blockDim.x + threadIdx.x; // pixel index
int c = blockIdx.y*blockDim.y + threadIdx.y; // channel index
int h = blockIdx.z*blockDim.z + threadIdx.z; // harmonic index
if (i < npix) {
A[c*npix * 4 + h*npix + i] = rho[c*npix + i] * N[h*npix + i];
}
} | .file "tmpxft_000d30cd_00000000-6_A_for_lightning_estimation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_
.type _Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_, @function
_Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26A_for_lightning_estimationPfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_, .-_Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_
.globl _Z26A_for_lightning_estimationPfS_iS_
.type _Z26A_for_lightning_estimationPfS_iS_, @function
_Z26A_for_lightning_estimationPfS_iS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26A_for_lightning_estimationPfS_iS_, .-_Z26A_for_lightning_estimationPfS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26A_for_lightning_estimationPfS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26A_for_lightning_estimationPfS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void A_for_lightning_estimation(float* rho, float* N, int npix, float* A) {
int i = blockIdx.x*blockDim.x + threadIdx.x; // pixel index
int c = blockIdx.y*blockDim.y + threadIdx.y; // channel index
int h = blockIdx.z*blockDim.z + threadIdx.z; // harmonic index
if (i < npix) {
A[c*npix * 4 + h*npix + i] = rho[c*npix + i] * N[h*npix + i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void A_for_lightning_estimation(float* rho, float* N, int npix, float* A) {
int i = blockIdx.x*blockDim.x + threadIdx.x; // pixel index
int c = blockIdx.y*blockDim.y + threadIdx.y; // channel index
int h = blockIdx.z*blockDim.z + threadIdx.z; // harmonic index
if (i < npix) {
A[c*npix * 4 + h*npix + i] = rho[c*npix + i] * N[h*npix + i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void A_for_lightning_estimation(float* rho, float* N, int npix, float* A) {
int i = blockIdx.x*blockDim.x + threadIdx.x; // pixel index
int c = blockIdx.y*blockDim.y + threadIdx.y; // channel index
int h = blockIdx.z*blockDim.z + threadIdx.z; // harmonic index
if (i < npix) {
A[c*npix * 4 + h*npix + i] = rho[c*npix + i] * N[h*npix + i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26A_for_lightning_estimationPfS_iS_
.globl _Z26A_for_lightning_estimationPfS_iS_
.p2align 8
.type _Z26A_for_lightning_estimationPfS_iS_,@function
_Z26A_for_lightning_estimationPfS_iS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s13, s5, v[3:4]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[2:3], 0xc
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s14, s2, v[2:3]
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v3, s4
v_mad_u64_u32 v[2:3], null, v4, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v5, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[0:1], off
v_lshl_add_u32 v0, v5, 2, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v4, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26A_for_lightning_estimationPfS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26A_for_lightning_estimationPfS_iS_, .Lfunc_end0-_Z26A_for_lightning_estimationPfS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26A_for_lightning_estimationPfS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26A_for_lightning_estimationPfS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void A_for_lightning_estimation(float* rho, float* N, int npix, float* A) {
int i = blockIdx.x*blockDim.x + threadIdx.x; // pixel index
int c = blockIdx.y*blockDim.y + threadIdx.y; // channel index
int h = blockIdx.z*blockDim.z + threadIdx.z; // harmonic index
if (i < npix) {
A[c*npix * 4 + h*npix + i] = rho[c*npix + i] * N[h*npix + i];
}
} | .text
.file "A_for_lightning_estimation.hip"
.globl _Z41__device_stub__A_for_lightning_estimationPfS_iS_ # -- Begin function _Z41__device_stub__A_for_lightning_estimationPfS_iS_
.p2align 4, 0x90
.type _Z41__device_stub__A_for_lightning_estimationPfS_iS_,@function
_Z41__device_stub__A_for_lightning_estimationPfS_iS_: # @_Z41__device_stub__A_for_lightning_estimationPfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26A_for_lightning_estimationPfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__A_for_lightning_estimationPfS_iS_, .Lfunc_end0-_Z41__device_stub__A_for_lightning_estimationPfS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26A_for_lightning_estimationPfS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26A_for_lightning_estimationPfS_iS_,@object # @_Z26A_for_lightning_estimationPfS_iS_
.section .rodata,"a",@progbits
.globl _Z26A_for_lightning_estimationPfS_iS_
.p2align 3, 0x0
_Z26A_for_lightning_estimationPfS_iS_:
.quad _Z41__device_stub__A_for_lightning_estimationPfS_iS_
.size _Z26A_for_lightning_estimationPfS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26A_for_lightning_estimationPfS_iS_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__A_for_lightning_estimationPfS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26A_for_lightning_estimationPfS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26A_for_lightning_estimationPfS_iS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0090*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*00a0*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e680000002300 */
/*00b0*/ S2R R5, SR_CTAID.Z ; /* 0x0000000000057919 */
/* 0x000e620000002700 */
/*00c0*/ IMAD R2, R3, c[0x0][0x4], R2 ; /* 0x0000010003027a24 */
/* 0x001fc800078e0202 */
/*00d0*/ IMAD R7, R2, c[0x0][0x170], RZ ; /* 0x00005c0002077a24 */
/* 0x000fe400078e02ff */
/*00e0*/ IMAD R3, R5, c[0x0][0x8], R4 ; /* 0x0000020005037a24 */
/* 0x002fc600078e0204 */
/*00f0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD R6, R3, c[0x0][0x170], R0 ; /* 0x00005c0003067a24 */
/* 0x000fc800078e0200 */
/*0110*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0209 */
/*0120*/ IMAD.WIDE R4, R6, R9, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe400078e0209 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ LEA R6, R7, R6, 0x2 ; /* 0x0000000607067211 */
/* 0x000fca00078e10ff */
/*0160*/ IMAD.WIDE R6, R6, R9, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0209 */
/*0170*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0180*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26A_for_lightning_estimationPfS_iS_
.globl _Z26A_for_lightning_estimationPfS_iS_
.p2align 8
.type _Z26A_for_lightning_estimationPfS_iS_,@function
_Z26A_for_lightning_estimationPfS_iS_:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s13, s5, v[3:4]
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[2:3], 0xc
v_bfe_u32 v2, v0, 10, 10
v_bfe_u32 v0, v0, 20, 10
s_clause 0x1
s_load_b128 s[8:11], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s14, s2, v[2:3]
s_and_b32 s2, s3, 0xffff
v_mad_u64_u32 v[4:5], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v5, v3, s4
v_mad_u64_u32 v[2:3], null, v4, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v0, v5, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[0:1], off
v_lshl_add_u32 v0, v5, 2, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v4, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26A_for_lightning_estimationPfS_iS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26A_for_lightning_estimationPfS_iS_, .Lfunc_end0-_Z26A_for_lightning_estimationPfS_iS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26A_for_lightning_estimationPfS_iS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26A_for_lightning_estimationPfS_iS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d30cd_00000000-6_A_for_lightning_estimation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_
.type _Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_, @function
_Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26A_for_lightning_estimationPfS_iS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_, .-_Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_
.globl _Z26A_for_lightning_estimationPfS_iS_
.type _Z26A_for_lightning_estimationPfS_iS_, @function
_Z26A_for_lightning_estimationPfS_iS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z26A_for_lightning_estimationPfS_iS_PfS_iS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26A_for_lightning_estimationPfS_iS_, .-_Z26A_for_lightning_estimationPfS_iS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26A_for_lightning_estimationPfS_iS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26A_for_lightning_estimationPfS_iS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "A_for_lightning_estimation.hip"
.globl _Z41__device_stub__A_for_lightning_estimationPfS_iS_ # -- Begin function _Z41__device_stub__A_for_lightning_estimationPfS_iS_
.p2align 4, 0x90
.type _Z41__device_stub__A_for_lightning_estimationPfS_iS_,@function
_Z41__device_stub__A_for_lightning_estimationPfS_iS_: # @_Z41__device_stub__A_for_lightning_estimationPfS_iS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26A_for_lightning_estimationPfS_iS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z41__device_stub__A_for_lightning_estimationPfS_iS_, .Lfunc_end0-_Z41__device_stub__A_for_lightning_estimationPfS_iS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26A_for_lightning_estimationPfS_iS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26A_for_lightning_estimationPfS_iS_,@object # @_Z26A_for_lightning_estimationPfS_iS_
.section .rodata,"a",@progbits
.globl _Z26A_for_lightning_estimationPfS_iS_
.p2align 3, 0x0
_Z26A_for_lightning_estimationPfS_iS_:
.quad _Z41__device_stub__A_for_lightning_estimationPfS_iS_
.size _Z26A_for_lightning_estimationPfS_iS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26A_for_lightning_estimationPfS_iS_"
.size .L__unnamed_1, 38
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__A_for_lightning_estimationPfS_iS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26A_for_lightning_estimationPfS_iS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
============================================================================
Filename : algorithm.c
Author : Gabioud Pierre, Jérémie Rossetti
SCIPER : 247 216, 270 015
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__ void GPU_processing(double *input, double *output, int length) {
int x = (blockIdx.x*blockDim.x) + threadIdx.x;
int y = (blockIdx.y*blockDim.y) + threadIdx.y;
int element_id = (y*length) + x;
int element_id2 = ((length - y - 1) * length) + x;
int element_id3 = (y*length) + length - x - 1;
int element_id4 = ((length - y - 1) * length) + length - x - 1;
double res = 0;
if (x >= length || y >= length || x%(length-1) == 0 || y%(length-1) == 0 ||
(x==length/2 - 1 && (y==length/2 || y==length/2-1)) ||
(x==length/2 && (y==length/2 || y==length/2-1))) return;
res = (input[(y-1)*(length)+(x-1)] +
input[(y-1)*(length)+(x)] +
input[(y-1)*(length)+(x+1)] +
input[(y)*(length)+(x-1)] +
input[(y)*(length)+(x)] +
input[(y)*(length)+(x+1)] +
input[(y+1)*(length)+(x-1)] +
input[(y+1)*(length)+(x)] +
input[(y+1)*(length)+(x+1)] ) / 9;
output[element_id] = res;
output[element_id2] = res;
output[element_id3] = res;
output[element_id4] = res;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
double* gpu_output;
cudaMalloc((void**)&gpu_output, length*length*sizeof(double));
double* gpu_input;
cudaMalloc((void**)&gpu_input, length*length*sizeof(double));
double* temp;
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cudaMemcpy((void*)gpu_input, (void*)input, length*length*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy((void*)gpu_output, (void*)output, length*length*sizeof(double), cudaMemcpyHostToDevice);
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
int nbTPB = 256;//256 threads par blocks max
while(nbTPB > length*length/60){
nbTPB = nbTPB/4;
}
int sizeTB = ceil(sqrt(nbTPB));
dim3 thrsPerBlock(sizeTB, sizeTB);
int nbTB = ceil(sqrt((length/2)*(length/2)/nbTPB));
dim3 nBlks(nbTB, nbTB);
for(int i = 0; i < iterations; i++) {
GPU_processing<<< nBlks, thrsPerBlock>>>(gpu_input, gpu_output, length);
cudaThreadSynchronize();
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cudaMemcpy((void*)output, (void*)gpu_input, length*length*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree(gpu_input);
cudaFree(gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | code for sm_80
Function : _Z14GPU_processingPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*00c0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f26270 */
/*00d0*/ IADD3 R6, R2, -0x1, RZ ; /* 0xffffffff02067810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ IABS R8, R6.reuse ; /* 0x0000000600087213 */
/* 0x080fe40000000000 */
/*00f0*/ IABS R11, R6 ; /* 0x00000006000b7213 */
/* 0x000fe40000000000 */
/*0100*/ I2F.RP R7, R8 ; /* 0x0000000800077306 */
/* 0x000e300000209400 */
/*0110*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fc40007ffe0ff */
/*0130*/ LOP3.LUT R7, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff077212 */
/* 0x000fc800078e33ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*0170*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fc800078e0004 */
/*0190*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0b */
/*01a0*/ IMAD.HI.U32 R4, R5, R10, RZ ; /* 0x0000000a05047227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD R4, R4, R9, R10 ; /* 0x0000000904047224 */
/* 0x000fca00078e020a */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R8, R4, PT ; /* 0x000000040800720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R8 ; /* 0x0000000104048824 */
/* 0x000fca00078e0a08 */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R8, R4, PT ; /* 0x000000040800720c */
/* 0x000fda0003f04070 */
/*01f0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R8 ; /* 0x0000000104048824 */
/* 0x000fe200078e0a08 */
/*0200*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0210*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fca00078e0a04 */
/*0220*/ SEL R4, R7, R4, !P0 ; /* 0x0000000407047207 */
/* 0x000fc80004000000 */
/*0230*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f25270 */
/*0240*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0250*/ IABS R4, R3 ; /* 0x0000000300047213 */
/* 0x000fe40000000000 */
/*0260*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc60003f46270 */
/*0270*/ IMAD.HI.U32 R5, R5, R4, RZ ; /* 0x0000000405057227 */
/* 0x000fc800078e00ff */
/*0280*/ IMAD R5, R5, R9, R4 ; /* 0x0000000905057224 */
/* 0x000fca00078e0204 */
/*0290*/ ISETP.GT.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f24070 */
/*02a0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105059824 */
/* 0x000fca00078e0a08 */
/*02b0*/ ISETP.GT.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f24070 */
/*02c0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105059824 */
/* 0x000fc800078e0a08 */
/*02d0*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fca00078e0a05 */
/*02e0*/ SEL R5, R7, R5, !P0 ; /* 0x0000000507057207 */
/* 0x000fc80004000000 */
/*02f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0300*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0310*/ LEA.HI R4, R2, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0002047a11 */
/* 0x000fe200078f08ff */
/*0320*/ BSSY B0, 0x3b0 ; /* 0x0000008000007945 */
/* 0x000fe60003800000 */
/*0330*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011404 */
/*0340*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.NE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fda0003f05270 */
/*0360*/ @P0 BRA 0x3a0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fc80003f05270 */
/*0380*/ ISETP.EQ.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x000fda0004702670 */
/*0390*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.NE.AND P0, PT, R0, R4, PT ; /* 0x000000040000720c */
/* 0x000fe20003f05270 */
/*03c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*03d0*/ BSSY B0, 0x430 ; /* 0x0000005000007945 */
/* 0x000ff60003800000 */
/*03e0*/ @P0 BRA 0x420 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fc80003f05270 */
/*0400*/ ISETP.EQ.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x000fda0004702670 */
/*0410*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ IMAD R5, R3, R2, -c[0x0][0x170] ; /* 0x80005c0003057624 */
/* 0x000fe400078e0202 */
/*0440*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe400078e00ff */
/*0450*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x000fc800078e0205 */
/*0460*/ IMAD.WIDE R12, R5, R11, c[0x0][0x160] ; /* 0x00005800050c7625 */
/* 0x000fca00078e020b */
/*0470*/ LDG.E.64 R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x0000a8000c1e1b00 */
/*0480*/ LDG.E.64 R18, [R12.64+-0x8] ; /* 0xfffff8040c127981 */
/* 0x0000a2000c1e1b00 */
/*0490*/ IMAD.WIDE R22, R2, 0x8, R12 ; /* 0x0000000802167825 */
/* 0x000fe200078e020c */
/*04a0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ LDG.E.64 R6, [R12.64+0x8] ; /* 0x000008040c067981 */
/* 0x0000e6000c1e1b00 */
/*04c0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e020b */
/*04d0*/ LDG.E.64 R4, [R22.64+-0x8] ; /* 0xfffff80416047981 */
/* 0x000f28000c1e1b00 */
/*04e0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000f62000c1e1b00 */
/*04f0*/ IMAD.WIDE R14, R2, 0x8, R10 ; /* 0x00000008020e7825 */
/* 0x000fc600078e020a */
/*0500*/ LDG.E.64 R10, [R22.64+0x8] ; /* 0x00000804160a7981 */
/* 0x000f66000c1e1b00 */
/*0510*/ IMAD.WIDE R24, R2, 0x8, R14 ; /* 0x0000000802187825 */
/* 0x000fca00078e020e */
/*0520*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000f68000c1e1b00 */
/*0530*/ LDG.E.64 R14, [R24.64+0x8] ; /* 0x00000804180e7981 */
/* 0x000f68000c1e1b00 */
/*0540*/ LDG.E.64 R12, [R24.64+0x10] ; /* 0x00001004180c7981 */
/* 0x001f62000c1e1b00 */
/*0550*/ BSSY B0, 0x770 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0560*/ DADD R20, R20, R18 ; /* 0x0000000014147229 */
/* 0x0040c40000000012 */
/*0570*/ MUFU.RCP64H R19, 9 ; /* 0x4022000000137908 */
/* 0x001e220000001800 */
/*0580*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fc600078e00ff */
/*0590*/ DADD R20, R20, R6 ; /* 0x0000000014147229 */
/* 0x0083240000000006 */
/*05a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x002fe400078e00ff */
/*05b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x40220000 ; /* 0x40220000ff077424 */
/* 0x000fe400078e00ff */
/*05c0*/ DADD R4, R20, R4 ; /* 0x0000000014047229 */
/* 0x010f480000000004 */
/*05d0*/ DFMA R20, R18, -R6, 1 ; /* 0x3ff000001214742b */
/* 0x001e080000000806 */
/*05e0*/ DADD R4, R4, R8 ; /* 0x0000000004047229 */
/* 0x020e480000000008 */
/*05f0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e080000000014 */
/*0600*/ DADD R4, R4, R10 ; /* 0x0000000004047229 */
/* 0x0022a4000000000a */
/*0610*/ LOP3.LUT R11, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff0b7212 */
/* 0x002fe400078e33ff */
/*0620*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x001e240000000012 */
/*0630*/ IADD3 R11, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0b7a10 */
/* 0x000fe40007ffe0ff */
/*0640*/ DADD R4, R4, R16 ; /* 0x0000000004047229 */
/* 0x004e480000000010 */
/*0650*/ DFMA R6, R20, -R6, 1 ; /* 0x3ff000001406742b */
/* 0x001e080000000806 */
/*0660*/ DADD R4, R4, R14 ; /* 0x0000000004047229 */
/* 0x002e48000000000e */
/*0670*/ DFMA R6, R20, R6, R20 ; /* 0x000000061406722b */
/* 0x001fc80000000014 */
/*0680*/ DADD R12, R4, R12 ; /* 0x00000000040c7229 */
/* 0x002e0c000000000c */
/*0690*/ DMUL R4, R12, R6 ; /* 0x000000060c047228 */
/* 0x001e080000000000 */
/*06a0*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f2e200 */
/*06b0*/ DFMA R8, R4, -9, R12 ; /* 0xc02200000408782b */
/* 0x001e0c000000000c */
/*06c0*/ DFMA R4, R6, R8, R4 ; /* 0x000000080604722b */
/* 0x001e140000000004 */
/*06d0*/ FFMA R2, RZ, 2.53125, R5 ; /* 0x40220000ff027823 */
/* 0x001fca0000000005 */
/*06e0*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fe40003f04200 */
/*06f0*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fc800078e33ff */
/*0700*/ IADD3 R2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fce0007ffe0ff */
/*0710*/ @P0 BRA P1, 0x760 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0720*/ MOV R10, 0x740 ; /* 0x00000740000a7802 */
/* 0x000fe40000000f00 */
/*0730*/ CALL.REL.NOINC 0x850 ; /* 0x0000011000007944 */
/* 0x000fea0003c00000 */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0760*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0770*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; /* 0x00000008ff0a7424 */
/* 0x000fe400078e00ff */
/*0780*/ IMAD R6, R3, c[0x0][0x170], R0.reuse ; /* 0x00005c0003067a24 */
/* 0x100fe400078e0200 */
/*0790*/ IMAD R7, R11, c[0x0][0x170], R0 ; /* 0x00005c000b077a24 */
/* 0x000fe400078e0200 */
/*07a0*/ IMAD R8, R3, c[0x0][0x170], R2.reuse ; /* 0x00005c0003087a24 */
/* 0x100fe400078e0202 */
/*07b0*/ IMAD R11, R11, c[0x0][0x170], R2 ; /* 0x00005c000b0b7a24 */
/* 0x000fc400078e0202 */
/*07c0*/ IMAD.WIDE R2, R6, R10, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e020a */
/*07d0*/ IMAD.WIDE R6, R7, R10.reuse, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x080fe200078e020a */
/*07e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe6000c101b04 */
/*07f0*/ IMAD.WIDE R8, R8, R10.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe200078e020a */
/*0800*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x000fe6000c101b04 */
/*0810*/ IMAD.WIDE R10, R11, R10, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe200078e020a */
/*0820*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x000fe8000c101b04 */
/*0830*/ STG.E.64 [R10.64], R4 ; /* 0x000000040a007986 */
/* 0x000fe2000c101b04 */
/*0840*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff20000 ; /* 0x3ff20000ff057424 */
/* 0x000fe200078e00ff */
/*0860*/ BSSY B1, 0xd30 ; /* 0x000004c000017945 */
/* 0x000fe20003800000 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fc400078e000d */
/*0880*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x000e220000001800 */
/*0890*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*08a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*08b0*/ FSETP.GEU.AND P1, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f2e200 */
/*08c0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*08d0*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*08e0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe400078e00ff */
/*08f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x40200000 ; /* 0x40200000ff157424 */
/* 0x000fe200078e00ff */
/*0900*/ ISETP.GE.U32.AND P0, PT, R12, 0x40200000, PT ; /* 0x402000000c00780c */
/* 0x000fe20003f06070 */
/*0910*/ IMAD.MOV.U32 R20, RZ, RZ, R12 ; /* 0x000000ffff147224 */
/* 0x000fc600078e000c */
/*0920*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe20004000000 */
/*0930*/ DFMA R14, R8, -R4, 1 ; /* 0x3ff00000080e742b */
/* 0x001e220000000804 */
/*0940*/ IADD3 R23, R21, -0x1, RZ ; /* 0xffffffff15177810 */
/* 0x000fe40007ffe0ff */
/*0950*/ @!P1 LOP3.LUT R18, R13, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000d129812 */
/* 0x000fc600078ef807 */
/*0960*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*0970*/ DFMA R16, R8, R14, R8 ; /* 0x0000000e0810722b */
/* 0x0010640000000008 */
/*0980*/ LOP3.LUT R9, R13, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0d097812 */
/* 0x001fe200078ef807 */
/*0990*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*09a0*/ @!P1 LOP3.LUT R15, R18, 0x100000, RZ, 0xfc, !PT ; /* 0x00100000120f9812 */
/* 0x000fe200078efcff */
/*09b0*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e00ff */
/*09c0*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x002e0a0000000804 */
/*09d0*/ @!P1 DFMA R8, R8, 2, -R14 ; /* 0x400000000808982b */
/* 0x000e48000000080e */
/*09e0*/ DFMA R14, R16, R18, R16 ; /* 0x00000012100e722b */
/* 0x001e0c0000000010 */
/*09f0*/ @!P1 LOP3.LUT R20, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009149812 */
/* 0x002fe200078ec0ff */
/*0a00*/ DMUL R16, R14, R8 ; /* 0x000000080e107228 */
/* 0x001e060000000000 */
/*0a10*/ IADD3 R22, R20, -0x1, RZ ; /* 0xffffffff14167810 */
/* 0x000fc60007ffe0ff */
/*0a20*/ DFMA R18, R16, -R4, R8 ; /* 0x800000041012722b */
/* 0x001e220000000008 */
/*0a30*/ ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; /* 0x7feffffe1600780c */
/* 0x000fc80003f04070 */
/*0a40*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fe20000704470 */
/*0a50*/ DFMA R14, R14, R18, R16 ; /* 0x000000120e0e722b */
/* 0x0010580000000010 */
/*0a60*/ @P0 BRA 0xc10 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R12, R12, -0x40200000, RZ ; /* 0xbfe000000c0c7810 */
/* 0x003fe20007ffe0ff */
/*0a80*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0a90*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*0aa0*/ IMNMX R12, R12, 0x46a00000, PT ; /* 0x46a000000c0c7817 */
/* 0x000fca0003800200 */
/*0ab0*/ IMAD.IADD R16, R12, 0x1, -R13 ; /* 0x000000010c107824 */
/* 0x000fca00078e0a0d */
/*0ac0*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*0ad0*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*0ae0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0af0*/ @P0 BRA 0xd20 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*0b00*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e220000000008 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0b20*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0b30*/ LOP3.LUT R4, R5, 0x40220000, RZ, 0x3c, !PT ; /* 0x4022000005047812 */
/* 0x000fc800078e3cff */
/*0b40*/ LOP3.LUT R9, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004097812 */
/* 0x000fc800078ec0ff */
/*0b50*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fc600078efcff */
/*0b60*/ @!P0 BRA 0xd20 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0b80*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0b90*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0ba0*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*0bb0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*0bc0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*0bd0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0be0*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*0bf0*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0c00*/ BRA 0xd20 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0c10*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0c20*/ @P0 BRA 0xd00 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0c30*/ ISETP.NE.AND P0, PT, R20, R21, PT ; /* 0x000000151400720c */
/* 0x000fe20003f05270 */
/*0c40*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0c50*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0c60*/ @!P0 BRA 0xd20 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0c80*/ LOP3.LUT R6, R7, 0x40220000, RZ, 0x3c, !PT ; /* 0x4022000007067812 */
/* 0x000fe400078e3cff */
/*0c90*/ ISETP.EQ.OR P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fe40004702670 */
/*0ca0*/ LOP3.LUT R13, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000060d7812 */
/* 0x000fd600078ec0ff */
/*0cb0*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*0cc0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0cd0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0ce0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*0cf0*/ BRA 0xd20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d00*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0d10*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0d20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d30*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*0d40*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0d50*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2a004007950 */
/* 0x000fea0003c3ffff */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
============================================================================
Filename : algorithm.c
Author : Gabioud Pierre, Jérémie Rossetti
SCIPER : 247 216, 270 015
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__ void GPU_processing(double *input, double *output, int length) {
int x = (blockIdx.x*blockDim.x) + threadIdx.x;
int y = (blockIdx.y*blockDim.y) + threadIdx.y;
int element_id = (y*length) + x;
int element_id2 = ((length - y - 1) * length) + x;
int element_id3 = (y*length) + length - x - 1;
int element_id4 = ((length - y - 1) * length) + length - x - 1;
double res = 0;
if (x >= length || y >= length || x%(length-1) == 0 || y%(length-1) == 0 ||
(x==length/2 - 1 && (y==length/2 || y==length/2-1)) ||
(x==length/2 && (y==length/2 || y==length/2-1))) return;
res = (input[(y-1)*(length)+(x-1)] +
input[(y-1)*(length)+(x)] +
input[(y-1)*(length)+(x+1)] +
input[(y)*(length)+(x-1)] +
input[(y)*(length)+(x)] +
input[(y)*(length)+(x+1)] +
input[(y+1)*(length)+(x-1)] +
input[(y+1)*(length)+(x)] +
input[(y+1)*(length)+(x+1)] ) / 9;
output[element_id] = res;
output[element_id2] = res;
output[element_id3] = res;
output[element_id4] = res;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
double* gpu_output;
cudaMalloc((void**)&gpu_output, length*length*sizeof(double));
double* gpu_input;
cudaMalloc((void**)&gpu_input, length*length*sizeof(double));
double* temp;
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cudaMemcpy((void*)gpu_input, (void*)input, length*length*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy((void*)gpu_output, (void*)output, length*length*sizeof(double), cudaMemcpyHostToDevice);
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
int nbTPB = 256;//256 threads par blocks max
while(nbTPB > length*length/60){
nbTPB = nbTPB/4;
}
int sizeTB = ceil(sqrt(nbTPB));
dim3 thrsPerBlock(sizeTB, sizeTB);
int nbTB = ceil(sqrt((length/2)*(length/2)/nbTPB));
dim3 nBlks(nbTB, nbTB);
for(int i = 0; i < iterations; i++) {
GPU_processing<<< nBlks, thrsPerBlock>>>(gpu_input, gpu_output, length);
cudaThreadSynchronize();
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cudaMemcpy((void*)output, (void*)gpu_input, length*length*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree(gpu_input);
cudaFree(gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | .file "tmpxft_000f17ea_00000000-6_implementation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13array_processPdS_ii
.type _Z13array_processPdS_ii, @function
_Z13array_processPdS_ii:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %ecx, -28(%rsp)
testl %ecx, %ecx
jle .L3
movq %rsi, %r8
movl %edx, %r10d
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal -1(%rax), %ecx
movl %ecx, %edx
imull %r10d, %edx
leal (%rcx,%rdx), %r13d
movslq %r13d, %r13
salq $3, %r13
leal (%rdx,%r10), %esi
addl %esi, %ecx
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r14
addl %eax, %edx
movslq %edx, %rdx
leaq 0(,%rdx,8), %r15
addl %esi, %eax
cltq
salq $3, %rax
movq %rax, -40(%rsp)
movslq %r10d, %rbp
leaq 0(,%rbp,8), %r11
leal -3(%r10), %eax
salq $4, %rbp
movl $0, %edx
leaq 8(,%rax,8), %rax
movq %rax, -8(%rsp)
leal -1(%r10), %r12d
movsd .LC0(%rip), %xmm1
movsd .LC1(%rip), %xmm2
movq %r13, -24(%rsp)
movq %r14, -16(%rsp)
movl %r10d, %ebx
jmp .L5
.L8:
leaq (%rax,%rbp), %r14
leaq (%rax,%r13), %rcx
movq %r14, %rsi
.L6:
movsd (%rax), %xmm0
addsd 8(%rax), %xmm0
addsd 16(%rax), %xmm0
addsd (%rdi,%rcx), %xmm0
addsd 8(%rdi,%rcx), %xmm0
addsd 16(%rdi,%rcx), %xmm0
addsd (%rsi), %xmm0
addsd 8(%rsi), %xmm0
addsd 16(%rsi), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%r8,%rcx)
addq $8, %rax
addq $8, %rsi
addq $8, %rcx
cmpq %r9, %rax
jne .L6
addl $1, %r10d
movq %r14, %rax
subq %r11, %rax
addq %r11, %r9
cmpl %r12d, %r10d
jne .L8
.L7:
movq -24(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movq -16(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movsd %xmm2, (%r8,%r15)
movq -40(%rsp), %rax
movsd %xmm2, (%r8,%rax)
addl $1, %edx
movq %r8, %rax
movq %rdi, %r8
cmpl %edx, -28(%rsp)
je .L3
movq %rax, %rdi
.L5:
cmpl $2, %ebx
jle .L7
movq %rdi, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rdi), %r9
movq %r11, %r13
subq %rdi, %r13
movl $1, %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z13array_processPdS_ii, .-_Z13array_processPdS_ii
.globl _Z37__device_stub__Z14GPU_processingPdS_iPdS_i
.type _Z37__device_stub__Z14GPU_processingPdS_iPdS_i, @function
_Z37__device_stub__Z14GPU_processingPdS_iPdS_i:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14GPU_processingPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z37__device_stub__Z14GPU_processingPdS_iPdS_i, .-_Z37__device_stub__Z14GPU_processingPdS_iPdS_i
.globl _Z14GPU_processingPdS_i
.type _Z14GPU_processingPdS_i, @function
_Z14GPU_processingPdS_i:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14GPU_processingPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z14GPU_processingPdS_i, .-_Z14GPU_processingPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "Host to Device MemCpy takes "
.LC9:
.string "s"
.LC10:
.string "Computation takes "
.LC11:
.string "Device to Host MemCpy takes "
.text
.globl _Z17GPU_array_processPdS_ii
.type _Z17GPU_array_processPdS_ii, @function
_Z17GPU_array_processPdS_ii:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 8(%rsp)
movq %rsi, %r14
movl %edx, %r12d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl %r12d, %r15d
imull %r12d, %r15d
movslq %r15d, %rbx
leaq 0(,%rbx,8), %r13
leaq 80(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
imulq $-2004318071, %rbx, %rdx
shrq $32, %rdx
addl %r15d, %edx
sarl $5, %edx
movl %r15d, %eax
sarl $31, %eax
subl %eax, %edx
cmpl $15359, %r15d
jg .L47
movl $256, %ebx
.L22:
leal 3(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $2, %eax
movl %eax, %ebx
cmpl %edx, %eax
jg .L22
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L54
.L21:
sqrtsd %xmm0, %xmm0
.L25:
movapd %xmm0, %xmm3
movsd .LC12(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L26
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L26:
cvttsd2sil %xmm3, %eax
movl %eax, 96(%rsp)
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl %r12d, %eax
shrl $31, %eax
addl %r12d, %eax
sarl %eax
imull %eax, %eax
cltd
idivl %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L52
sqrtsd %xmm0, %xmm0
.L29:
movapd %xmm0, %xmm3
movsd .LC12(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L30
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L30:
cvttsd2sil %xmm3, %eax
movl %eax, 108(%rsp)
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
testl %ebp, %ebp
jle .L31
movl $0, %ebx
jmp .L33
.L47:
movl $256, %ebx
movsd .LC2(%rip), %xmm0
jmp .L21
.L54:
call sqrt@PLT
jmp .L25
.L52:
call sqrt@PLT
jmp .L29
.L32:
call cudaThreadSynchronize@PLT
movq 88(%rsp), %rax
movq 80(%rsp), %rdx
movq %rdx, 88(%rsp)
movq %rax, 80(%rsp)
addl $1, %ebx
cmpl %ebx, %ebp
je .L31
.L33:
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movl %r12d, %edx
movq 80(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z37__device_stub__Z14GPU_processingPdS_iPdS_i
jmp .L32
.L31:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r13, %rdx
movq 88(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
leaq 28(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 28(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L55
cmpb $0, 56(%rbp)
je .L36
movzbl 67(%rbp), %esi
.L37:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $18, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 28(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L56
cmpb $0, 56(%rbp)
je .L40
movzbl 67(%rbp), %esi
.L41:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 28(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 28(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L57
cmpb $0, 56(%rbp)
je .L44
movzbl 67(%rbp), %esi
.L45:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L59
call _ZSt16__throw_bad_castv@PLT
.L59:
call __stack_chk_fail@PLT
.L36:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L37
.L56:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L60
call _ZSt16__throw_bad_castv@PLT
.L60:
call __stack_chk_fail@PLT
.L40:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L41
.L57:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L61
call _ZSt16__throw_bad_castv@PLT
.L61:
call __stack_chk_fail@PLT
.L44:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L45
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z17GPU_array_processPdS_ii, .-_Z17GPU_array_processPdS_ii
.section .rodata.str1.1
.LC13:
.string "_Z14GPU_processingPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z14GPU_processingPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1075970048
.align 8
.LC1:
.long 0
.long 1083129856
.align 8
.LC2:
.long 0
.long 1081081856
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1148846080
.section .rodata.cst8
.align 8
.LC12:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
============================================================================
Filename : algorithm.c
Author : Gabioud Pierre, Jérémie Rossetti
SCIPER : 247 216, 270 015
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__ void GPU_processing(double *input, double *output, int length) {
int x = (blockIdx.x*blockDim.x) + threadIdx.x;
int y = (blockIdx.y*blockDim.y) + threadIdx.y;
int element_id = (y*length) + x;
int element_id2 = ((length - y - 1) * length) + x;
int element_id3 = (y*length) + length - x - 1;
int element_id4 = ((length - y - 1) * length) + length - x - 1;
double res = 0;
if (x >= length || y >= length || x%(length-1) == 0 || y%(length-1) == 0 ||
(x==length/2 - 1 && (y==length/2 || y==length/2-1)) ||
(x==length/2 && (y==length/2 || y==length/2-1))) return;
res = (input[(y-1)*(length)+(x-1)] +
input[(y-1)*(length)+(x)] +
input[(y-1)*(length)+(x+1)] +
input[(y)*(length)+(x-1)] +
input[(y)*(length)+(x)] +
input[(y)*(length)+(x+1)] +
input[(y+1)*(length)+(x-1)] +
input[(y+1)*(length)+(x)] +
input[(y+1)*(length)+(x+1)] ) / 9;
output[element_id] = res;
output[element_id2] = res;
output[element_id3] = res;
output[element_id4] = res;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
cudaEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
cudaEventCreate(&cpy_H2D_start);
cudaEventCreate(&cpy_H2D_end);
cudaEventCreate(&cpy_D2H_start);
cudaEventCreate(&cpy_D2H_end);
cudaEventCreate(&comp_start);
cudaEventCreate(&comp_end);
/* Preprocessing goes here */
double* gpu_output;
cudaMalloc((void**)&gpu_output, length*length*sizeof(double));
double* gpu_input;
cudaMalloc((void**)&gpu_input, length*length*sizeof(double));
double* temp;
cudaEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
cudaMemcpy((void*)gpu_input, (void*)input, length*length*sizeof(double), cudaMemcpyHostToDevice);
cudaMemcpy((void*)gpu_output, (void*)output, length*length*sizeof(double), cudaMemcpyHostToDevice);
cudaEventRecord(cpy_H2D_end);
cudaEventSynchronize(cpy_H2D_end);
//Copy array from host to device
cudaEventRecord(comp_start);
/* GPU calculation goes here */
int nbTPB = 256;//256 threads par blocks max
while(nbTPB > length*length/60){
nbTPB = nbTPB/4;
}
int sizeTB = ceil(sqrt(nbTPB));
dim3 thrsPerBlock(sizeTB, sizeTB);
int nbTB = ceil(sqrt((length/2)*(length/2)/nbTPB));
dim3 nBlks(nbTB, nbTB);
for(int i = 0; i < iterations; i++) {
GPU_processing<<< nBlks, thrsPerBlock>>>(gpu_input, gpu_output, length);
cudaThreadSynchronize();
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
cudaEventRecord(comp_end);
cudaEventSynchronize(comp_end);
cudaEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
cudaMemcpy((void*)output, (void*)gpu_input, length*length*sizeof(double), cudaMemcpyDeviceToHost);
cudaEventRecord(cpy_D2H_end);
cudaEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
cudaFree(gpu_input);
cudaFree(gpu_output);
float time;
cudaEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
cudaEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | /*
============================================================================
Filename : algorithm.c
Author : Gabioud Pierre, Jérémie Rossetti
SCIPER : 247 216, 270 015
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__ void GPU_processing(double *input, double *output, int length) {
int x = (blockIdx.x*blockDim.x) + threadIdx.x;
int y = (blockIdx.y*blockDim.y) + threadIdx.y;
int element_id = (y*length) + x;
int element_id2 = ((length - y - 1) * length) + x;
int element_id3 = (y*length) + length - x - 1;
int element_id4 = ((length - y - 1) * length) + length - x - 1;
double res = 0;
if (x >= length || y >= length || x%(length-1) == 0 || y%(length-1) == 0 ||
(x==length/2 - 1 && (y==length/2 || y==length/2-1)) ||
(x==length/2 && (y==length/2 || y==length/2-1))) return;
res = (input[(y-1)*(length)+(x-1)] +
input[(y-1)*(length)+(x)] +
input[(y-1)*(length)+(x+1)] +
input[(y)*(length)+(x-1)] +
input[(y)*(length)+(x)] +
input[(y)*(length)+(x+1)] +
input[(y+1)*(length)+(x-1)] +
input[(y+1)*(length)+(x)] +
input[(y+1)*(length)+(x+1)] ) / 9;
output[element_id] = res;
output[element_id2] = res;
output[element_id3] = res;
output[element_id4] = res;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
double* gpu_output;
hipMalloc((void**)&gpu_output, length*length*sizeof(double));
double* gpu_input;
hipMalloc((void**)&gpu_input, length*length*sizeof(double));
double* temp;
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
hipMemcpy((void*)gpu_input, (void*)input, length*length*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy((void*)gpu_output, (void*)output, length*length*sizeof(double), hipMemcpyHostToDevice);
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
int nbTPB = 256;//256 threads par blocks max
while(nbTPB > length*length/60){
nbTPB = nbTPB/4;
}
int sizeTB = ceil(sqrt(nbTPB));
dim3 thrsPerBlock(sizeTB, sizeTB);
int nbTB = ceil(sqrt((length/2)*(length/2)/nbTPB));
dim3 nBlks(nbTB, nbTB);
for(int i = 0; i < iterations; i++) {
GPU_processing<<< nBlks, thrsPerBlock>>>(gpu_input, gpu_output, length);
hipDeviceSynchronize();
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
hipMemcpy((void*)output, (void*)gpu_input, length*length*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree(gpu_input);
hipFree(gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
============================================================================
Filename : algorithm.c
Author : Gabioud Pierre, Jérémie Rossetti
SCIPER : 247 216, 270 015
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__ void GPU_processing(double *input, double *output, int length) {
int x = (blockIdx.x*blockDim.x) + threadIdx.x;
int y = (blockIdx.y*blockDim.y) + threadIdx.y;
int element_id = (y*length) + x;
int element_id2 = ((length - y - 1) * length) + x;
int element_id3 = (y*length) + length - x - 1;
int element_id4 = ((length - y - 1) * length) + length - x - 1;
double res = 0;
if (x >= length || y >= length || x%(length-1) == 0 || y%(length-1) == 0 ||
(x==length/2 - 1 && (y==length/2 || y==length/2-1)) ||
(x==length/2 && (y==length/2 || y==length/2-1))) return;
res = (input[(y-1)*(length)+(x-1)] +
input[(y-1)*(length)+(x)] +
input[(y-1)*(length)+(x+1)] +
input[(y)*(length)+(x-1)] +
input[(y)*(length)+(x)] +
input[(y)*(length)+(x+1)] +
input[(y+1)*(length)+(x-1)] +
input[(y+1)*(length)+(x)] +
input[(y+1)*(length)+(x+1)] ) / 9;
output[element_id] = res;
output[element_id2] = res;
output[element_id3] = res;
output[element_id4] = res;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
double* gpu_output;
hipMalloc((void**)&gpu_output, length*length*sizeof(double));
double* gpu_input;
hipMalloc((void**)&gpu_input, length*length*sizeof(double));
double* temp;
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
hipMemcpy((void*)gpu_input, (void*)input, length*length*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy((void*)gpu_output, (void*)output, length*length*sizeof(double), hipMemcpyHostToDevice);
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
int nbTPB = 256;//256 threads par blocks max
while(nbTPB > length*length/60){
nbTPB = nbTPB/4;
}
int sizeTB = ceil(sqrt(nbTPB));
dim3 thrsPerBlock(sizeTB, sizeTB);
int nbTB = ceil(sqrt((length/2)*(length/2)/nbTPB));
dim3 nBlks(nbTB, nbTB);
for(int i = 0; i < iterations; i++) {
GPU_processing<<< nBlks, thrsPerBlock>>>(gpu_input, gpu_output, length);
hipDeviceSynchronize();
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
hipMemcpy((void*)output, (void*)gpu_input, length*length*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree(gpu_input);
hipFree(gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14GPU_processingPdS_i
.globl _Z14GPU_processingPdS_i
.p2align 8
.type _Z14GPU_processingPdS_i,@function
_Z14GPU_processingPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_10
s_add_i32 s2, s4, -1
v_ashrrev_i32_e32 v4, 31, v0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_xor_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v0, v4
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s3, 0, s2
v_xor_b32_e32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s3, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v3, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s2
v_sub_nc_u32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v4
v_sub_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v4, v2
v_mul_lo_u32 v2, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_xor_b32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
s_lshr_b32 s2, s4, 31
s_mov_b32 s7, exec_lo
s_add_i32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 1
s_add_i32 s5, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e64 s6, s5, v0
v_cmpx_eq_u32_e64 s5, v0
v_cmp_ne_u32_e32 vcc_lo, s3, v1
v_cmp_ne_u32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s6, s6, s2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_10
v_cmp_ne_u32_e64 s6, s3, v0
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e64 s3, v0
v_cmp_ne_u32_e32 vcc_lo, s3, v1
v_cmp_ne_u32_e64 s2, s5, v1
s_and_not1_b32 s3, s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s3, s2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v2, -1, v1
v_add_nc_u32_e32 v16, -1, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v20, 1, v0
v_mul_lo_u32 v22, v1, s4
v_mul_lo_u32 v6, v2, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v22, v16
v_add_nc_u32_e32 v2, v6, v16
v_add_nc_u32_e32 v4, v6, v0
v_add_nc_u32_e32 v6, v6, v20
v_add_nc_u32_e32 v10, v22, v0
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_add_nc_u32_e32 v14, v22, v20
v_add_nc_u32_e32 v21, s4, v22
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v12, vcc_lo, s0, v10
global_load_b64 v[8:9], v[8:9], off
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v11, vcc_lo
v_ashrrev_i32_e32 v15, 31, v14
v_add_nc_u32_e32 v16, v21, v16
v_add_nc_u32_e32 v18, v21, v0
global_load_b64 v[12:13], v[12:13], off
v_add_nc_u32_e32 v20, v21, v20
v_lshlrev_b64 v[14:15], 3, v[14:15]
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v19, 31, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_u32 v14, vcc_lo, s0, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo
v_lshlrev_b64 v[16:17], 3, v[16:17]
v_lshlrev_b64 v[18:19], 3, v[18:19]
v_lshlrev_b64 v[20:21], 3, v[20:21]
global_load_b64 v[14:15], v[14:15], off
v_add_co_u32 v16, vcc_lo, s0, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
v_add_co_u32 v18, vcc_lo, s0, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s1, v19, vcc_lo
global_load_b64 v[16:17], v[16:17], off
v_add_co_u32 v20, vcc_lo, s0, v20
global_load_b64 v[18:19], v[18:19], off
v_add_co_ci_u32_e32 v21, vcc_lo, s1, v21, vcc_lo
global_load_b64 v[20:21], v[20:21], off
s_waitcnt vmcnt(7)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_waitcnt vmcnt(5)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[12:13]
s_waitcnt vmcnt(3)
v_add_f64 v[2:3], v[2:3], v[14:15]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[16:17]
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], v[18:19]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[20:21]
v_div_scale_f64 v[4:5], null, 0x40220000, 0x40220000, v[2:3]
v_div_scale_f64 v[12:13], vcc_lo, v[2:3], 0x40220000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[12:13], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
v_xad_u32 v6, v1, -1, s4
v_add_co_u32 v9, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v11, vcc_lo
v_div_fixup_f64 v[1:2], v[4:5], 0x40220000, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v6, s4
v_xad_u32 v6, v0, -1, s4
v_add_nc_u32_e32 v3, v6, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, v4, v0
v_add_nc_u32_e32 v7, v6, v4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x3
global_store_b64 v[9:10], v[1:2], off
global_store_b64 v[5:6], v[1:2], off
global_store_b64 v[3:4], v[1:2], off
global_store_b64 v[7:8], v[1:2], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14GPU_processingPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14GPU_processingPdS_i, .Lfunc_end0-_Z14GPU_processingPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14GPU_processingPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14GPU_processingPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
============================================================================
Filename : algorithm.c
Author : Gabioud Pierre, Jérémie Rossetti
SCIPER : 247 216, 270 015
============================================================================
*/
#include <iostream>
#include <iomanip>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <math.h>
using namespace std;
// CPU Baseline
void array_process(double *input, double *output, int length, int iterations)
{
double *temp;
for(int n=0; n<(int) iterations; n++)
{
for(int i=1; i<length-1; i++)
{
for(int j=1; j<length-1; j++)
{
output[(i)*(length)+(j)] = (input[(i-1)*(length)+(j-1)] +
input[(i-1)*(length)+(j)] +
input[(i-1)*(length)+(j+1)] +
input[(i)*(length)+(j-1)] +
input[(i)*(length)+(j)] +
input[(i)*(length)+(j+1)] +
input[(i+1)*(length)+(j-1)] +
input[(i+1)*(length)+(j)] +
input[(i+1)*(length)+(j+1)] ) / 9;
}
}
output[(length/2-1)*length+(length/2-1)] = 1000;
output[(length/2)*length+(length/2-1)] = 1000;
output[(length/2-1)*length+(length/2)] = 1000;
output[(length/2)*length+(length/2)] = 1000;
temp = input;
input = output;
output = temp;
}
}
__global__ void GPU_processing(double *input, double *output, int length) {
int x = (blockIdx.x*blockDim.x) + threadIdx.x;
int y = (blockIdx.y*blockDim.y) + threadIdx.y;
int element_id = (y*length) + x;
int element_id2 = ((length - y - 1) * length) + x;
int element_id3 = (y*length) + length - x - 1;
int element_id4 = ((length - y - 1) * length) + length - x - 1;
double res = 0;
if (x >= length || y >= length || x%(length-1) == 0 || y%(length-1) == 0 ||
(x==length/2 - 1 && (y==length/2 || y==length/2-1)) ||
(x==length/2 && (y==length/2 || y==length/2-1))) return;
res = (input[(y-1)*(length)+(x-1)] +
input[(y-1)*(length)+(x)] +
input[(y-1)*(length)+(x+1)] +
input[(y)*(length)+(x-1)] +
input[(y)*(length)+(x)] +
input[(y)*(length)+(x+1)] +
input[(y+1)*(length)+(x-1)] +
input[(y+1)*(length)+(x)] +
input[(y+1)*(length)+(x+1)] ) / 9;
output[element_id] = res;
output[element_id2] = res;
output[element_id3] = res;
output[element_id4] = res;
}
// GPU Optimized function
void GPU_array_process(double *input, double *output, int length, int iterations)
{
//Cuda events for calculating elapsed time
hipEvent_t cpy_H2D_start, cpy_H2D_end, comp_start, comp_end, cpy_D2H_start, cpy_D2H_end;
hipEventCreate(&cpy_H2D_start);
hipEventCreate(&cpy_H2D_end);
hipEventCreate(&cpy_D2H_start);
hipEventCreate(&cpy_D2H_end);
hipEventCreate(&comp_start);
hipEventCreate(&comp_end);
/* Preprocessing goes here */
double* gpu_output;
hipMalloc((void**)&gpu_output, length*length*sizeof(double));
double* gpu_input;
hipMalloc((void**)&gpu_input, length*length*sizeof(double));
double* temp;
hipEventRecord(cpy_H2D_start);
/* Copying array from host to device goes here */
hipMemcpy((void*)gpu_input, (void*)input, length*length*sizeof(double), hipMemcpyHostToDevice);
hipMemcpy((void*)gpu_output, (void*)output, length*length*sizeof(double), hipMemcpyHostToDevice);
hipEventRecord(cpy_H2D_end);
hipEventSynchronize(cpy_H2D_end);
//Copy array from host to device
hipEventRecord(comp_start);
/* GPU calculation goes here */
int nbTPB = 256;//256 threads par blocks max
while(nbTPB > length*length/60){
nbTPB = nbTPB/4;
}
int sizeTB = ceil(sqrt(nbTPB));
dim3 thrsPerBlock(sizeTB, sizeTB);
int nbTB = ceil(sqrt((length/2)*(length/2)/nbTPB));
dim3 nBlks(nbTB, nbTB);
for(int i = 0; i < iterations; i++) {
GPU_processing<<< nBlks, thrsPerBlock>>>(gpu_input, gpu_output, length);
hipDeviceSynchronize();
temp = gpu_input;
gpu_input = gpu_output;
gpu_output = temp;
}
hipEventRecord(comp_end);
hipEventSynchronize(comp_end);
hipEventRecord(cpy_D2H_start);
/* Copying array from device to host goes here */
hipMemcpy((void*)output, (void*)gpu_input, length*length*sizeof(double), hipMemcpyDeviceToHost);
hipEventRecord(cpy_D2H_end);
hipEventSynchronize(cpy_D2H_end);
/* Postprocessing goes here */
hipFree(gpu_input);
hipFree(gpu_output);
float time;
hipEventElapsedTime(&time, cpy_H2D_start, cpy_H2D_end);
cout<<"Host to Device MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, comp_start, comp_end);
cout<<"Computation takes "<<setprecision(4)<<time/1000<<"s"<<endl;
hipEventElapsedTime(&time, cpy_D2H_start, cpy_D2H_end);
cout<<"Device to Host MemCpy takes "<<setprecision(4)<<time/1000<<"s"<<endl;
} | .text
.file "implementation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13array_processPdS_ii
.LCPI0_0:
.quad 0x4022000000000000 # double 9
.text
.globl _Z13array_processPdS_ii
.p2align 4, 0x90
.type _Z13array_processPdS_ii,@function
_Z13array_processPdS_ii: # @_Z13array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdx, -48(%rsp) # 8-byte Spill
movl %ecx, -52(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader72.lr.ph
movq -48(%rsp), %r10 # 8-byte Reload
leal -1(%r10), %eax
movl %r10d, %ecx
shrl $31, %ecx
addl %r10d, %ecx
sarl %ecx
leal -1(%rcx), %edx
imull %r10d, %edx
leal (%rdx,%rcx), %r8d
decl %r8d
movslq %r8d, %r8
movq %r8, -8(%rsp) # 8-byte Spill
movl %ecx, %r8d
imull %r10d, %r8d
leal (%r8,%rcx), %r9d
decl %r9d
movslq %r9d, %r9
movq %r9, -16(%rsp) # 8-byte Spill
addl %ecx, %edx
movslq %edx, %rdx
addl %ecx, %r8d
movslq %r8d, %r11
movslq %r10d, %rcx
leaq (,%rcx,8), %rbx
leaq 8(,%rcx,8), %r8
movq %r8, -24(%rsp) # 8-byte Spill
leaq 16(,%rcx,8), %r8
movq %r8, -32(%rsp) # 8-byte Spill
shlq $4, %rcx
addq $16, %rcx
movq %rcx, -40(%rsp) # 8-byte Spill
leaq -8(,%rax,8), %r13
xorl %ebp, %ebp
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movabsq $4652007308841189376, %r14 # imm = 0x408F400000000000
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %._crit_edge75
# in Loop: Header=BB0_2 Depth=1
movq -8(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq -16(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq %r14, (%rsi,%rdx,8)
movq %r14, (%rsi,%r11,8)
incl %ebp
movq %rsi, %rdi
movq %r15, %rsi
cmpl -52(%rsp), %ebp # 4-byte Folded Reload
je .LBB0_8
.LBB0_2: # %.preheader72
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_5 Depth 3
movq %rdi, %r15
cmpl $3, -48(%rsp) # 4-byte Folded Reload
jl .LBB0_7
# %bb.3: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
movq -40(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %rdi
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rsi,%rcx), %r12
movq -32(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %r8
leaq 16(%r15), %rcx
movl $1, %r9d
.p2align 4, 0x90
.LBB0_4: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_5 Depth 3
incq %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_5: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movsd -16(%rcx,%r10), %xmm1 # xmm1 = mem[0],zero
addsd -8(%rcx,%r10), %xmm1
addsd (%rcx,%r10), %xmm1
addsd -16(%r8,%r10), %xmm1
addsd -8(%r8,%r10), %xmm1
addsd (%r8,%r10), %xmm1
addsd -16(%rdi,%r10), %xmm1
addsd -8(%rdi,%r10), %xmm1
addsd (%rdi,%r10), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%r12,%r10)
addq $8, %r10
cmpq %r10, %r13
jne .LBB0_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
addq %rbx, %rdi
addq %rbx, %r12
addq %rbx, %r8
addq %rbx, %rcx
cmpq %rax, %r9
jne .LBB0_4
jmp .LBB0_7
.LBB0_8: # %._crit_edge79
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13array_processPdS_ii, .Lfunc_end0-_Z13array_processPdS_ii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__GPU_processingPdS_i # -- Begin function _Z29__device_stub__GPU_processingPdS_i
.p2align 4, 0x90
.type _Z29__device_stub__GPU_processingPdS_i,@function
_Z29__device_stub__GPU_processingPdS_i: # @_Z29__device_stub__GPU_processingPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14GPU_processingPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z29__device_stub__GPU_processingPdS_i, .Lfunc_end1-_Z29__device_stub__GPU_processingPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17GPU_array_processPdS_ii
.LCPI2_0:
.long 0x447a0000 # float 1000
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x0000000000000000 # double 0
.text
.globl _Z17GPU_array_processPdS_ii
.p2align 4, 0x90
.type _Z17GPU_array_processPdS_ii,@function
_Z17GPU_array_processPdS_ii: # @_Z17GPU_array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r14d
movq %rsi, %r15
movq %rdi, %rbx
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movl %r14d, 28(%rsp) # 4-byte Spill
# kill: def $r14d killed $r14d def $r14
imull %r14d, %r14d
leaq (,%r14,8), %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, 128(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %r12, 120(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $256, %ebx # imm = 0x100
cmpl $15359, %r14d # imm = 0x3BFF
ja .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl $2290649225, %eax # imm = 0x88888889
imulq %r14, %rax
shrq $37, %rax
movl $256, %ecx # imm = 0x100
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal 3(%rcx), %ebx
testl %ecx, %ecx
cmovnsl %ecx, %ebx
sarl $2, %ebx
movl %ebx, %ecx
cmpl %eax, %ebx
jg .LBB2_2
.LBB2_3: # %._crit_edge
cvtsi2sd %ebx, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB2_6
.LBB2_5: # %call.sqrt
callq sqrt
.LBB2_6: # %._crit_edge.split
callq ceil@PLT
movsd %xmm0, 112(%rsp) # 8-byte Spill
movl 28(%rsp), %ecx # 4-byte Reload
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
imull %eax, %eax
cltd
idivl %ebx
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
ucomisd .LCPI2_1(%rip), %xmm0
jb .LBB2_8
# %bb.7:
sqrtsd %xmm0, %xmm0
jmp .LBB2_9
.LBB2_8: # %call.sqrt56
callq sqrt
.LBB2_9: # %._crit_edge.split.split
callq ceil@PLT
testl %ebp, %ebp
jle .LBB2_14
# %bb.10:
cvttsd2si 112(%rsp), %r12d # 8-byte Folded Reload
movabsq $4294967297, %rax # imm = 0x100000001
imulq %rax, %r12
cvttsd2si %xmm0, %r13d
imulq %rax, %r13
leaq 144(%rsp), %r14
leaq 136(%rsp), %rbx
leaq 64(%rsp), %r15
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_11 Depth=1
callq hipDeviceSynchronize
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
decl %ebp
je .LBB2_14
.LBB2_11: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 60(%rsp), %rax
movq %rax, 80(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
movq %r14, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
movl $_Z14GPU_processingPdS_i, %edi
movq %r15, %r9
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_13
.LBB2_14: # %._crit_edge55
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movq 128(%rsp), %rdi # 8-byte Reload
movq 120(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_27
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB2_18
.LBB2_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 96(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_27
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
cmpb $0, 56(%r14)
je .LBB2_21
# %bb.20:
movzbl 67(%r14), %eax
jmp .LBB2_22
.LBB2_21:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 88(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_27
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
cmpb $0, 56(%r14)
je .LBB2_25
# %bb.24:
movzbl 67(%r14), %eax
jmp .LBB2_26
.LBB2_25:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z17GPU_array_processPdS_ii, .Lfunc_end2-_Z17GPU_array_processPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14GPU_processingPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14GPU_processingPdS_i,@object # @_Z14GPU_processingPdS_i
.section .rodata,"a",@progbits
.globl _Z14GPU_processingPdS_i
.p2align 3, 0x0
_Z14GPU_processingPdS_i:
.quad _Z29__device_stub__GPU_processingPdS_i
.size _Z14GPU_processingPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host to Device MemCpy takes "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "s"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computation takes "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device to Host MemCpy takes "
.size .L.str.3, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14GPU_processingPdS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__GPU_processingPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14GPU_processingPdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14GPU_processingPdS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x170], P0 ; /* 0x00005c0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ IABS R10, R0 ; /* 0x00000000000a7213 */
/* 0x000fe40000000000 */
/*00c0*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f26270 */
/*00d0*/ IADD3 R6, R2, -0x1, RZ ; /* 0xffffffff02067810 */
/* 0x000fc80007ffe0ff */
/*00e0*/ IABS R8, R6.reuse ; /* 0x0000000600087213 */
/* 0x080fe40000000000 */
/*00f0*/ IABS R11, R6 ; /* 0x00000006000b7213 */
/* 0x000fe40000000000 */
/*0100*/ I2F.RP R7, R8 ; /* 0x0000000800077306 */
/* 0x000e300000209400 */
/*0110*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R4, R7, 0xffffffe, RZ ; /* 0x0ffffffe07047810 */
/* 0x001fc40007ffe0ff */
/*0130*/ LOP3.LUT R7, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff077212 */
/* 0x000fc800078e33ff */
/*0140*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0150*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0160*/ IMAD.MOV R9, RZ, RZ, -R5 ; /* 0x000000ffff097224 */
/* 0x002fc800078e0a05 */
/*0170*/ IMAD R9, R9, R8, RZ ; /* 0x0000000809097224 */
/* 0x000fc800078e02ff */
/*0180*/ IMAD.HI.U32 R5, R5, R9, R4 ; /* 0x0000000905057227 */
/* 0x000fc800078e0004 */
/*0190*/ IMAD.MOV R9, RZ, RZ, -R11 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0a0b */
/*01a0*/ IMAD.HI.U32 R4, R5, R10, RZ ; /* 0x0000000a05047227 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD R4, R4, R9, R10 ; /* 0x0000000904047224 */
/* 0x000fca00078e020a */
/*01c0*/ ISETP.GT.U32.AND P0, PT, R8, R4, PT ; /* 0x000000040800720c */
/* 0x000fda0003f04070 */
/*01d0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R8 ; /* 0x0000000104048824 */
/* 0x000fca00078e0a08 */
/*01e0*/ ISETP.GT.U32.AND P0, PT, R8, R4, PT ; /* 0x000000040800720c */
/* 0x000fda0003f04070 */
/*01f0*/ @!P0 IMAD.IADD R4, R4, 0x1, -R8 ; /* 0x0000000104048824 */
/* 0x000fe200078e0a08 */
/*0200*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc60003f05270 */
/*0210*/ @!P1 IMAD.MOV R4, RZ, RZ, -R4 ; /* 0x000000ffff049224 */
/* 0x000fca00078e0a04 */
/*0220*/ SEL R4, R7, R4, !P0 ; /* 0x0000000407047207 */
/* 0x000fc80004000000 */
/*0230*/ ISETP.NE.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f25270 */
/*0240*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0250*/ IABS R4, R3 ; /* 0x0000000300047213 */
/* 0x000fe40000000000 */
/*0260*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fc60003f46270 */
/*0270*/ IMAD.HI.U32 R5, R5, R4, RZ ; /* 0x0000000405057227 */
/* 0x000fc800078e00ff */
/*0280*/ IMAD R5, R5, R9, R4 ; /* 0x0000000905057224 */
/* 0x000fca00078e0204 */
/*0290*/ ISETP.GT.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f24070 */
/*02a0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105059824 */
/* 0x000fca00078e0a08 */
/*02b0*/ ISETP.GT.U32.AND P1, PT, R8, R5, PT ; /* 0x000000050800720c */
/* 0x000fda0003f24070 */
/*02c0*/ @!P1 IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105059824 */
/* 0x000fc800078e0a08 */
/*02d0*/ @!P2 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff05a224 */
/* 0x000fca00078e0a05 */
/*02e0*/ SEL R5, R7, R5, !P0 ; /* 0x0000000507057207 */
/* 0x000fc80004000000 */
/*02f0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0300*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0310*/ LEA.HI R4, R2, c[0x0][0x170], RZ, 0x1 ; /* 0x00005c0002047a11 */
/* 0x000fe200078f08ff */
/*0320*/ BSSY B0, 0x3b0 ; /* 0x0000008000007945 */
/* 0x000fe60003800000 */
/*0330*/ SHF.R.S32.HI R4, RZ, 0x1, R4 ; /* 0x00000001ff047819 */
/* 0x000fc80000011404 */
/*0340*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fc80007ffe0ff */
/*0350*/ ISETP.NE.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fda0003f05270 */
/*0360*/ @P0 BRA 0x3a0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0370*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fc80003f05270 */
/*0380*/ ISETP.EQ.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x000fda0004702670 */
/*0390*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ ISETP.NE.AND P0, PT, R0, R4, PT ; /* 0x000000040000720c */
/* 0x000fe20003f05270 */
/*03c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*03d0*/ BSSY B0, 0x430 ; /* 0x0000005000007945 */
/* 0x000ff60003800000 */
/*03e0*/ @P0 BRA 0x420 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*03f0*/ ISETP.NE.AND P0, PT, R3, R5, PT ; /* 0x000000050300720c */
/* 0x000fc80003f05270 */
/*0400*/ ISETP.EQ.OR P0, PT, R3, R0, !P0 ; /* 0x000000000300720c */
/* 0x000fda0004702670 */
/*0410*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ IMAD R5, R3, R2, -c[0x0][0x170] ; /* 0x80005c0003057624 */
/* 0x000fe400078e0202 */
/*0440*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe400078e00ff */
/*0450*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x000fc800078e0205 */
/*0460*/ IMAD.WIDE R12, R5, R11, c[0x0][0x160] ; /* 0x00005800050c7625 */
/* 0x000fca00078e020b */
/*0470*/ LDG.E.64 R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x0000a8000c1e1b00 */
/*0480*/ LDG.E.64 R18, [R12.64+-0x8] ; /* 0xfffff8040c127981 */
/* 0x0000a2000c1e1b00 */
/*0490*/ IMAD.WIDE R22, R2, 0x8, R12 ; /* 0x0000000802167825 */
/* 0x000fe200078e020c */
/*04a0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fe40007ffe0ff */
/*04b0*/ LDG.E.64 R6, [R12.64+0x8] ; /* 0x000008040c067981 */
/* 0x0000e6000c1e1b00 */
/*04c0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e020b */
/*04d0*/ LDG.E.64 R4, [R22.64+-0x8] ; /* 0xfffff80416047981 */
/* 0x000f28000c1e1b00 */
/*04e0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000f62000c1e1b00 */
/*04f0*/ IMAD.WIDE R14, R2, 0x8, R10 ; /* 0x00000008020e7825 */
/* 0x000fc600078e020a */
/*0500*/ LDG.E.64 R10, [R22.64+0x8] ; /* 0x00000804160a7981 */
/* 0x000f66000c1e1b00 */
/*0510*/ IMAD.WIDE R24, R2, 0x8, R14 ; /* 0x0000000802187825 */
/* 0x000fca00078e020e */
/*0520*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x000f68000c1e1b00 */
/*0530*/ LDG.E.64 R14, [R24.64+0x8] ; /* 0x00000804180e7981 */
/* 0x000f68000c1e1b00 */
/*0540*/ LDG.E.64 R12, [R24.64+0x10] ; /* 0x00001004180c7981 */
/* 0x001f62000c1e1b00 */
/*0550*/ BSSY B0, 0x770 ; /* 0x0000021000007945 */
/* 0x000fe20003800000 */
/*0560*/ DADD R20, R20, R18 ; /* 0x0000000014147229 */
/* 0x0040c40000000012 */
/*0570*/ MUFU.RCP64H R19, 9 ; /* 0x4022000000137908 */
/* 0x001e220000001800 */
/*0580*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fc600078e00ff */
/*0590*/ DADD R20, R20, R6 ; /* 0x0000000014147229 */
/* 0x0083240000000006 */
/*05a0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x0 ; /* 0x00000000ff067424 */
/* 0x002fe400078e00ff */
/*05b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x40220000 ; /* 0x40220000ff077424 */
/* 0x000fe400078e00ff */
/*05c0*/ DADD R4, R20, R4 ; /* 0x0000000014047229 */
/* 0x010f480000000004 */
/*05d0*/ DFMA R20, R18, -R6, 1 ; /* 0x3ff000001214742b */
/* 0x001e080000000806 */
/*05e0*/ DADD R4, R4, R8 ; /* 0x0000000004047229 */
/* 0x020e480000000008 */
/*05f0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e080000000014 */
/*0600*/ DADD R4, R4, R10 ; /* 0x0000000004047229 */
/* 0x0022a4000000000a */
/*0610*/ LOP3.LUT R11, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff0b7212 */
/* 0x002fe400078e33ff */
/*0620*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x001e240000000012 */
/*0630*/ IADD3 R11, R11, c[0x0][0x170], RZ ; /* 0x00005c000b0b7a10 */
/* 0x000fe40007ffe0ff */
/*0640*/ DADD R4, R4, R16 ; /* 0x0000000004047229 */
/* 0x004e480000000010 */
/*0650*/ DFMA R6, R20, -R6, 1 ; /* 0x3ff000001406742b */
/* 0x001e080000000806 */
/*0660*/ DADD R4, R4, R14 ; /* 0x0000000004047229 */
/* 0x002e48000000000e */
/*0670*/ DFMA R6, R20, R6, R20 ; /* 0x000000061406722b */
/* 0x001fc80000000014 */
/*0680*/ DADD R12, R4, R12 ; /* 0x00000000040c7229 */
/* 0x002e0c000000000c */
/*0690*/ DMUL R4, R12, R6 ; /* 0x000000060c047228 */
/* 0x001e080000000000 */
/*06a0*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f2e200 */
/*06b0*/ DFMA R8, R4, -9, R12 ; /* 0xc02200000408782b */
/* 0x001e0c000000000c */
/*06c0*/ DFMA R4, R6, R8, R4 ; /* 0x000000080604722b */
/* 0x001e140000000004 */
/*06d0*/ FFMA R2, RZ, 2.53125, R5 ; /* 0x40220000ff027823 */
/* 0x001fca0000000005 */
/*06e0*/ FSETP.GT.AND P0, PT, |R2|, 1.469367938527859385e-39, PT ; /* 0x001000000200780b */
/* 0x000fe40003f04200 */
/*06f0*/ LOP3.LUT R2, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff027212 */
/* 0x000fc800078e33ff */
/*0700*/ IADD3 R2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fce0007ffe0ff */
/*0710*/ @P0 BRA P1, 0x760 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0720*/ MOV R10, 0x740 ; /* 0x00000740000a7802 */
/* 0x000fe40000000f00 */
/*0730*/ CALL.REL.NOINC 0x850 ; /* 0x0000011000007944 */
/* 0x000fea0003c00000 */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, R13 ; /* 0x000000ffff057224 */
/* 0x000fe400078e000d */
/*0760*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0770*/ IMAD.MOV.U32 R10, RZ, RZ, 0x8 ; /* 0x00000008ff0a7424 */
/* 0x000fe400078e00ff */
/*0780*/ IMAD R6, R3, c[0x0][0x170], R0.reuse ; /* 0x00005c0003067a24 */
/* 0x100fe400078e0200 */
/*0790*/ IMAD R7, R11, c[0x0][0x170], R0 ; /* 0x00005c000b077a24 */
/* 0x000fe400078e0200 */
/*07a0*/ IMAD R8, R3, c[0x0][0x170], R2.reuse ; /* 0x00005c0003087a24 */
/* 0x100fe400078e0202 */
/*07b0*/ IMAD R11, R11, c[0x0][0x170], R2 ; /* 0x00005c000b0b7a24 */
/* 0x000fc400078e0202 */
/*07c0*/ IMAD.WIDE R2, R6, R10, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e020a */
/*07d0*/ IMAD.WIDE R6, R7, R10.reuse, c[0x0][0x168] ; /* 0x00005a0007067625 */
/* 0x080fe200078e020a */
/*07e0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe6000c101b04 */
/*07f0*/ IMAD.WIDE R8, R8, R10.reuse, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x080fe200078e020a */
/*0800*/ STG.E.64 [R6.64], R4 ; /* 0x0000000406007986 */
/* 0x000fe6000c101b04 */
/*0810*/ IMAD.WIDE R10, R11, R10, c[0x0][0x168] ; /* 0x00005a000b0a7625 */
/* 0x000fe200078e020a */
/*0820*/ STG.E.64 [R8.64], R4 ; /* 0x0000000408007986 */
/* 0x000fe8000c101b04 */
/*0830*/ STG.E.64 [R10.64], R4 ; /* 0x000000040a007986 */
/* 0x000fe2000c101b04 */
/*0840*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3ff20000 ; /* 0x3ff20000ff057424 */
/* 0x000fe200078e00ff */
/*0860*/ BSSY B1, 0xd30 ; /* 0x000004c000017945 */
/* 0x000fe20003800000 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fc400078e000d */
/*0880*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x000e220000001800 */
/*0890*/ IMAD.MOV.U32 R4, RZ, RZ, 0x0 ; /* 0x00000000ff047424 */
/* 0x000fe400078e00ff */
/*08a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*08b0*/ FSETP.GEU.AND P1, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f2e200 */
/*08c0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe200078e000c */
/*08d0*/ LOP3.LUT R12, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000070c7812 */
/* 0x000fe200078ec0ff */
/*08e0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0d7424 */
/* 0x000fe400078e00ff */
/*08f0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x40200000 ; /* 0x40200000ff157424 */
/* 0x000fe200078e00ff */
/*0900*/ ISETP.GE.U32.AND P0, PT, R12, 0x40200000, PT ; /* 0x402000000c00780c */
/* 0x000fe20003f06070 */
/*0910*/ IMAD.MOV.U32 R20, RZ, RZ, R12 ; /* 0x000000ffff147224 */
/* 0x000fc600078e000c */
/*0920*/ SEL R13, R13, 0x63400000, !P0 ; /* 0x634000000d0d7807 */
/* 0x000fe20004000000 */
/*0930*/ DFMA R14, R8, -R4, 1 ; /* 0x3ff00000080e742b */
/* 0x001e220000000804 */
/*0940*/ IADD3 R23, R21, -0x1, RZ ; /* 0xffffffff15177810 */
/* 0x000fe40007ffe0ff */
/*0950*/ @!P1 LOP3.LUT R18, R13, 0x80000000, R7, 0xf8, !PT ; /* 0x800000000d129812 */
/* 0x000fc600078ef807 */
/*0960*/ DFMA R14, R14, R14, R14 ; /* 0x0000000e0e0e722b */
/* 0x001e0c000000000e */
/*0970*/ DFMA R16, R8, R14, R8 ; /* 0x0000000e0810722b */
/* 0x0010640000000008 */
/*0980*/ LOP3.LUT R9, R13, 0x800fffff, R7, 0xf8, !PT ; /* 0x800fffff0d097812 */
/* 0x001fe200078ef807 */
/*0990*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0006 */
/*09a0*/ @!P1 LOP3.LUT R15, R18, 0x100000, RZ, 0xfc, !PT ; /* 0x00100000120f9812 */
/* 0x000fe200078efcff */
/*09b0*/ @!P1 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e9224 */
/* 0x000fe200078e00ff */
/*09c0*/ DFMA R18, R16, -R4, 1 ; /* 0x3ff000001012742b */
/* 0x002e0a0000000804 */
/*09d0*/ @!P1 DFMA R8, R8, 2, -R14 ; /* 0x400000000808982b */
/* 0x000e48000000080e */
/*09e0*/ DFMA R14, R16, R18, R16 ; /* 0x00000012100e722b */
/* 0x001e0c0000000010 */
/*09f0*/ @!P1 LOP3.LUT R20, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009149812 */
/* 0x002fe200078ec0ff */
/*0a00*/ DMUL R16, R14, R8 ; /* 0x000000080e107228 */
/* 0x001e060000000000 */
/*0a10*/ IADD3 R22, R20, -0x1, RZ ; /* 0xffffffff14167810 */
/* 0x000fc60007ffe0ff */
/*0a20*/ DFMA R18, R16, -R4, R8 ; /* 0x800000041012722b */
/* 0x001e220000000008 */
/*0a30*/ ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; /* 0x7feffffe1600780c */
/* 0x000fc80003f04070 */
/*0a40*/ ISETP.GT.U32.OR P0, PT, R23, 0x7feffffe, P0 ; /* 0x7feffffe1700780c */
/* 0x000fe20000704470 */
/*0a50*/ DFMA R14, R14, R18, R16 ; /* 0x000000120e0e722b */
/* 0x0010580000000010 */
/*0a60*/ @P0 BRA 0xc10 ; /* 0x000001a000000947 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R12, R12, -0x40200000, RZ ; /* 0xbfe000000c0c7810 */
/* 0x003fe20007ffe0ff */
/*0a80*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*0a90*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fc80007800200 */
/*0aa0*/ IMNMX R12, R12, 0x46a00000, PT ; /* 0x46a000000c0c7817 */
/* 0x000fca0003800200 */
/*0ab0*/ IMAD.IADD R16, R12, 0x1, -R13 ; /* 0x000000010c107824 */
/* 0x000fca00078e0a0d */
/*0ac0*/ IADD3 R7, R16, 0x7fe00000, RZ ; /* 0x7fe0000010077810 */
/* 0x000fcc0007ffe0ff */
/*0ad0*/ DMUL R12, R14, R6 ; /* 0x000000060e0c7228 */
/* 0x000e140000000000 */
/*0ae0*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x001fda0003f0c200 */
/*0af0*/ @P0 BRA 0xd20 ; /* 0x0000022000000947 */
/* 0x000fea0003800000 */
/*0b00*/ DFMA R4, R14, -R4, R8 ; /* 0x800000040e04722b */
/* 0x000e220000000008 */
/*0b10*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fd200078e00ff */
/*0b20*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0b30*/ LOP3.LUT R4, R5, 0x40220000, RZ, 0x3c, !PT ; /* 0x4022000005047812 */
/* 0x000fc800078e3cff */
/*0b40*/ LOP3.LUT R9, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004097812 */
/* 0x000fc800078ec0ff */
/*0b50*/ LOP3.LUT R7, R9, R7, RZ, 0xfc, !PT ; /* 0x0000000709077212 */
/* 0x000fc600078efcff */
/*0b60*/ @!P0 BRA 0xd20 ; /* 0x000001b000008947 */
/* 0x000fea0003800000 */
/*0b70*/ IMAD.MOV R5, RZ, RZ, -R16 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a10 */
/*0b80*/ DMUL.RP R6, R14, R6 ; /* 0x000000060e067228 */
/* 0x000e220000008000 */
/*0b90*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0ba0*/ DFMA R4, R12, -R4, R14 ; /* 0x800000040c04722b */
/* 0x000e46000000000e */
/*0bb0*/ LOP3.LUT R9, R7, R9, RZ, 0x3c, !PT ; /* 0x0000000907097212 */
/* 0x001fc600078e3cff */
/*0bc0*/ IADD3 R4, -R16, -0x43300000, RZ ; /* 0xbcd0000010047810 */
/* 0x002fc80007ffe1ff */
/*0bd0*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0be0*/ FSEL R12, R6, R12, !P0 ; /* 0x0000000c060c7208 */
/* 0x000fe40004000000 */
/*0bf0*/ FSEL R13, R9, R13, !P0 ; /* 0x0000000d090d7208 */
/* 0x000fe20004000000 */
/*0c00*/ BRA 0xd20 ; /* 0x0000011000007947 */
/* 0x000fea0003800000 */
/*0c10*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x003e1c0003f08000 */
/*0c20*/ @P0 BRA 0xd00 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*0c30*/ ISETP.NE.AND P0, PT, R20, R21, PT ; /* 0x000000151400720c */
/* 0x000fe20003f05270 */
/*0c40*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0c50*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0c60*/ @!P0 BRA 0xd20 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0c70*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0c80*/ LOP3.LUT R6, R7, 0x40220000, RZ, 0x3c, !PT ; /* 0x4022000007067812 */
/* 0x000fe400078e3cff */
/*0c90*/ ISETP.EQ.OR P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fe40004702670 */
/*0ca0*/ LOP3.LUT R13, R6, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000060d7812 */
/* 0x000fd600078ec0ff */
/*0cb0*/ @P0 LOP3.LUT R4, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d040812 */
/* 0x000fe200078efcff */
/*0cc0*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0cd0*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0ce0*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R4 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0004 */
/*0cf0*/ BRA 0xd20 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0d00*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0d10*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0006 */
/*0d20*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0d30*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000a */
/*0d40*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0d50*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2a004007950 */
/* 0x000fea0003c3ffff */
/*0d60*/ BRA 0xd60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14GPU_processingPdS_i
.globl _Z14GPU_processingPdS_i
.p2align 8
.type _Z14GPU_processingPdS_i,@function
_Z14GPU_processingPdS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_10
s_add_i32 s2, s4, -1
v_ashrrev_i32_e32 v4, 31, v0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s3
s_xor_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, v0, v4
v_cvt_f32_u32_e32 v2, s2
s_sub_i32 s3, 0, s2
v_xor_b32_e32 v5, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, s3, v2
v_mul_hi_u32 v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v2, v3
v_mul_hi_u32 v3, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v3, s2
v_sub_nc_u32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s2, v3
v_cmp_le_u32_e32 vcc_lo, s2, v3
v_cndmask_b32_e32 v3, v3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v3, v4
v_sub_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v3
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v4, v2
v_mul_lo_u32 v2, v2, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s2, v2
v_cmp_le_u32_e32 vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_xor_b32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v2, v3
v_cmp_ne_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_10
s_lshr_b32 s2, s4, 31
s_mov_b32 s7, exec_lo
s_add_i32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 1
s_add_i32 s5, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e64 s6, s5, v0
v_cmpx_eq_u32_e64 s5, v0
v_cmp_ne_u32_e32 vcc_lo, s3, v1
v_cmp_ne_u32_e64 s2, s5, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_not1_b32 s6, s6, exec_lo
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s6, s6, s2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_10
v_cmp_ne_u32_e64 s6, s3, v0
s_mov_b32 s7, exec_lo
v_cmpx_eq_u32_e64 s3, v0
v_cmp_ne_u32_e32 vcc_lo, s3, v1
v_cmp_ne_u32_e64 s2, s5, v1
s_and_not1_b32 s3, s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s6, s3, s2
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_10
v_add_nc_u32_e32 v2, -1, v1
v_add_nc_u32_e32 v16, -1, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v20, 1, v0
v_mul_lo_u32 v22, v1, s4
v_mul_lo_u32 v6, v2, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v8, v22, v16
v_add_nc_u32_e32 v2, v6, v16
v_add_nc_u32_e32 v4, v6, v0
v_add_nc_u32_e32 v6, v6, v20
v_add_nc_u32_e32 v10, v22, v0
v_ashrrev_i32_e32 v9, 31, v8
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
v_ashrrev_i32_e32 v7, 31, v6
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_lshlrev_b64 v[10:11], 3, v[10:11]
v_add_nc_u32_e32 v14, v22, v20
v_add_nc_u32_e32 v21, s4, v22
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, s0, v6
s_clause 0x1
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_add_co_u32 v8, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v12, vcc_lo, s0, v10
global_load_b64 v[8:9], v[8:9], off
v_add_co_ci_u32_e32 v13, vcc_lo, s1, v11, vcc_lo
v_ashrrev_i32_e32 v15, 31, v14
v_add_nc_u32_e32 v16, v21, v16
v_add_nc_u32_e32 v18, v21, v0
global_load_b64 v[12:13], v[12:13], off
v_add_nc_u32_e32 v20, v21, v20
v_lshlrev_b64 v[14:15], 3, v[14:15]
v_ashrrev_i32_e32 v17, 31, v16
v_ashrrev_i32_e32 v19, 31, v18
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v21, 31, v20
v_add_co_u32 v14, vcc_lo, s0, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s1, v15, vcc_lo
v_lshlrev_b64 v[16:17], 3, v[16:17]
v_lshlrev_b64 v[18:19], 3, v[18:19]
v_lshlrev_b64 v[20:21], 3, v[20:21]
global_load_b64 v[14:15], v[14:15], off
v_add_co_u32 v16, vcc_lo, s0, v16
v_add_co_ci_u32_e32 v17, vcc_lo, s1, v17, vcc_lo
v_add_co_u32 v18, vcc_lo, s0, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s1, v19, vcc_lo
global_load_b64 v[16:17], v[16:17], off
v_add_co_u32 v20, vcc_lo, s0, v20
global_load_b64 v[18:19], v[18:19], off
v_add_co_ci_u32_e32 v21, vcc_lo, s1, v21, vcc_lo
global_load_b64 v[20:21], v[20:21], off
s_waitcnt vmcnt(7)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(6)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_waitcnt vmcnt(5)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_waitcnt vmcnt(4)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[12:13]
s_waitcnt vmcnt(3)
v_add_f64 v[2:3], v[2:3], v[14:15]
s_waitcnt vmcnt(2)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[16:17]
s_waitcnt vmcnt(1)
v_add_f64 v[2:3], v[2:3], v[18:19]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[20:21]
v_div_scale_f64 v[4:5], null, 0x40220000, 0x40220000, v[2:3]
v_div_scale_f64 v[12:13], vcc_lo, v[2:3], 0x40220000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[12:13], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
v_xad_u32 v6, v1, -1, s4
v_add_co_u32 v9, vcc_lo, s2, v10
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v11, vcc_lo
v_div_fixup_f64 v[1:2], v[4:5], 0x40220000, v[2:3]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v6, s4
v_xad_u32 v6, v0, -1, s4
v_add_nc_u32_e32 v3, v6, v22
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, v4, v0
v_add_nc_u32_e32 v7, v6, v4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_lshlrev_b64 v[5:6], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x3
global_store_b64 v[9:10], v[1:2], off
global_store_b64 v[5:6], v[1:2], off
global_store_b64 v[3:4], v[1:2], off
global_store_b64 v[7:8], v[1:2], off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14GPU_processingPdS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14GPU_processingPdS_i, .Lfunc_end0-_Z14GPU_processingPdS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14GPU_processingPdS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14GPU_processingPdS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f17ea_00000000-6_implementation.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13array_processPdS_ii
.type _Z13array_processPdS_ii, @function
_Z13array_processPdS_ii:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movl %ecx, -28(%rsp)
testl %ecx, %ecx
jle .L3
movq %rsi, %r8
movl %edx, %r10d
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
leal -1(%rax), %ecx
movl %ecx, %edx
imull %r10d, %edx
leal (%rcx,%rdx), %r13d
movslq %r13d, %r13
salq $3, %r13
leal (%rdx,%r10), %esi
addl %esi, %ecx
movslq %ecx, %rcx
leaq 0(,%rcx,8), %r14
addl %eax, %edx
movslq %edx, %rdx
leaq 0(,%rdx,8), %r15
addl %esi, %eax
cltq
salq $3, %rax
movq %rax, -40(%rsp)
movslq %r10d, %rbp
leaq 0(,%rbp,8), %r11
leal -3(%r10), %eax
salq $4, %rbp
movl $0, %edx
leaq 8(,%rax,8), %rax
movq %rax, -8(%rsp)
leal -1(%r10), %r12d
movsd .LC0(%rip), %xmm1
movsd .LC1(%rip), %xmm2
movq %r13, -24(%rsp)
movq %r14, -16(%rsp)
movl %r10d, %ebx
jmp .L5
.L8:
leaq (%rax,%rbp), %r14
leaq (%rax,%r13), %rcx
movq %r14, %rsi
.L6:
movsd (%rax), %xmm0
addsd 8(%rax), %xmm0
addsd 16(%rax), %xmm0
addsd (%rdi,%rcx), %xmm0
addsd 8(%rdi,%rcx), %xmm0
addsd 16(%rdi,%rcx), %xmm0
addsd (%rsi), %xmm0
addsd 8(%rsi), %xmm0
addsd 16(%rsi), %xmm0
divsd %xmm1, %xmm0
movsd %xmm0, 8(%r8,%rcx)
addq $8, %rax
addq $8, %rsi
addq $8, %rcx
cmpq %r9, %rax
jne .L6
addl $1, %r10d
movq %r14, %rax
subq %r11, %rax
addq %r11, %r9
cmpl %r12d, %r10d
jne .L8
.L7:
movq -24(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movq -16(%rsp), %rax
movsd %xmm2, (%r8,%rax)
movsd %xmm2, (%r8,%r15)
movq -40(%rsp), %rax
movsd %xmm2, (%r8,%rax)
addl $1, %edx
movq %r8, %rax
movq %rdi, %r8
cmpl %edx, -28(%rsp)
je .L3
movq %rax, %rdi
.L5:
cmpl $2, %ebx
jle .L7
movq %rdi, %rax
movq -8(%rsp), %rsi
leaq (%rsi,%rdi), %r9
movq %r11, %r13
subq %rdi, %r13
movl $1, %r10d
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z13array_processPdS_ii, .-_Z13array_processPdS_ii
.globl _Z37__device_stub__Z14GPU_processingPdS_iPdS_i
.type _Z37__device_stub__Z14GPU_processingPdS_iPdS_i, @function
_Z37__device_stub__Z14GPU_processingPdS_iPdS_i:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14GPU_processingPdS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z37__device_stub__Z14GPU_processingPdS_iPdS_i, .-_Z37__device_stub__Z14GPU_processingPdS_iPdS_i
.globl _Z14GPU_processingPdS_i
.type _Z14GPU_processingPdS_i, @function
_Z14GPU_processingPdS_i:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14GPU_processingPdS_iPdS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z14GPU_processingPdS_i, .-_Z14GPU_processingPdS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC7:
.string "Host to Device MemCpy takes "
.LC9:
.string "s"
.LC10:
.string "Computation takes "
.LC11:
.string "Device to Host MemCpy takes "
.text
.globl _Z17GPU_array_processPdS_ii
.type _Z17GPU_array_processPdS_ii, @function
_Z17GPU_array_processPdS_ii:
.LFB3950:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 8(%rsp)
movq %rsi, %r14
movl %edx, %r12d
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl %r12d, %r15d
imull %r12d, %r15d
movslq %r15d, %rbx
leaq 0(,%rbx,8), %r13
leaq 80(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
imulq $-2004318071, %rbx, %rdx
shrq $32, %rdx
addl %r15d, %edx
sarl $5, %edx
movl %r15d, %eax
sarl $31, %eax
subl %eax, %edx
cmpl $15359, %r15d
jg .L47
movl $256, %ebx
.L22:
leal 3(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $2, %eax
movl %eax, %ebx
cmpl %edx, %eax
jg .L22
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L54
.L21:
sqrtsd %xmm0, %xmm0
.L25:
movapd %xmm0, %xmm3
movsd .LC12(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L26
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L26:
cvttsd2sil %xmm3, %eax
movl %eax, 96(%rsp)
movl %eax, 100(%rsp)
movl $1, 104(%rsp)
movl %r12d, %eax
shrl $31, %eax
addl %r12d, %eax
sarl %eax
imull %eax, %eax
cltd
idivl %ebx
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L52
sqrtsd %xmm0, %xmm0
.L29:
movapd %xmm0, %xmm3
movsd .LC12(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L30
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L30:
cvttsd2sil %xmm3, %eax
movl %eax, 108(%rsp)
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
testl %ebp, %ebp
jle .L31
movl $0, %ebx
jmp .L33
.L47:
movl $256, %ebx
movsd .LC2(%rip), %xmm0
jmp .L21
.L54:
call sqrt@PLT
jmp .L25
.L52:
call sqrt@PLT
jmp .L29
.L32:
call cudaThreadSynchronize@PLT
movq 88(%rsp), %rax
movq 80(%rsp), %rdx
movq %rdx, 88(%rsp)
movq %rax, 80(%rsp)
addl $1, %ebx
cmpl %ebx, %ebp
je .L31
.L33:
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L32
movl %r12d, %edx
movq 80(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z37__device_stub__Z14GPU_processingPdS_iPdS_i
jmp .L32
.L31:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r13, %rdx
movq 88(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
leaq 28(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 28(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L55
cmpb $0, 56(%rbp)
je .L36
movzbl 67(%rbp), %esi
.L37:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 28(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $18, %edx
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 28(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L56
cmpb $0, 56(%rbp)
je .L40
movzbl 67(%rbp), %esi
.L41:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 28(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $28, %edx
leaq .LC11(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, 8(%rbx,%rax)
movss 28(%rsp), %xmm0
divss .LC8(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC9(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L57
cmpb $0, 56(%rbp)
je .L44
movzbl 67(%rbp), %esi
.L45:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L58
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L59
call _ZSt16__throw_bad_castv@PLT
.L59:
call __stack_chk_fail@PLT
.L36:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L37
.L56:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L60
call _ZSt16__throw_bad_castv@PLT
.L60:
call __stack_chk_fail@PLT
.L40:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L41
.L57:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L61
call _ZSt16__throw_bad_castv@PLT
.L61:
call __stack_chk_fail@PLT
.L44:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L45
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3950:
.size _Z17GPU_array_processPdS_ii, .-_Z17GPU_array_processPdS_ii
.section .rodata.str1.1
.LC13:
.string "_Z14GPU_processingPdS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z14GPU_processingPdS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1075970048
.align 8
.LC1:
.long 0
.long 1083129856
.align 8
.LC2:
.long 0
.long 1081081856
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC8:
.long 1148846080
.section .rodata.cst8
.align 8
.LC12:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "implementation.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z13array_processPdS_ii
.LCPI0_0:
.quad 0x4022000000000000 # double 9
.text
.globl _Z13array_processPdS_ii
.p2align 4, 0x90
.type _Z13array_processPdS_ii,@function
_Z13array_processPdS_ii: # @_Z13array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $edx killed $edx def $rdx
movq %rdx, -48(%rsp) # 8-byte Spill
movl %ecx, -52(%rsp) # 4-byte Spill
testl %ecx, %ecx
jle .LBB0_8
# %bb.1: # %.preheader72.lr.ph
movq -48(%rsp), %r10 # 8-byte Reload
leal -1(%r10), %eax
movl %r10d, %ecx
shrl $31, %ecx
addl %r10d, %ecx
sarl %ecx
leal -1(%rcx), %edx
imull %r10d, %edx
leal (%rdx,%rcx), %r8d
decl %r8d
movslq %r8d, %r8
movq %r8, -8(%rsp) # 8-byte Spill
movl %ecx, %r8d
imull %r10d, %r8d
leal (%r8,%rcx), %r9d
decl %r9d
movslq %r9d, %r9
movq %r9, -16(%rsp) # 8-byte Spill
addl %ecx, %edx
movslq %edx, %rdx
addl %ecx, %r8d
movslq %r8d, %r11
movslq %r10d, %rcx
leaq (,%rcx,8), %rbx
leaq 8(,%rcx,8), %r8
movq %r8, -24(%rsp) # 8-byte Spill
leaq 16(,%rcx,8), %r8
movq %r8, -32(%rsp) # 8-byte Spill
shlq $4, %rcx
addq $16, %rcx
movq %rcx, -40(%rsp) # 8-byte Spill
leaq -8(,%rax,8), %r13
xorl %ebp, %ebp
movsd .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero
movabsq $4652007308841189376, %r14 # imm = 0x408F400000000000
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_7: # %._crit_edge75
# in Loop: Header=BB0_2 Depth=1
movq -8(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq -16(%rsp), %rcx # 8-byte Reload
movq %r14, (%rsi,%rcx,8)
movq %r14, (%rsi,%rdx,8)
movq %r14, (%rsi,%r11,8)
incl %ebp
movq %rsi, %rdi
movq %r15, %rsi
cmpl -52(%rsp), %ebp # 4-byte Folded Reload
je .LBB0_8
.LBB0_2: # %.preheader72
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_5 Depth 3
movq %rdi, %r15
cmpl $3, -48(%rsp) # 4-byte Folded Reload
jl .LBB0_7
# %bb.3: # %.preheader.preheader
# in Loop: Header=BB0_2 Depth=1
movq -40(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %rdi
movq -24(%rsp), %rcx # 8-byte Reload
leaq (%rsi,%rcx), %r12
movq -32(%rsp), %rcx # 8-byte Reload
leaq (%r15,%rcx), %r8
leaq 16(%r15), %rcx
movl $1, %r9d
.p2align 4, 0x90
.LBB0_4: # %.preheader
# Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_5 Depth 3
incq %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB0_5: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movsd -16(%rcx,%r10), %xmm1 # xmm1 = mem[0],zero
addsd -8(%rcx,%r10), %xmm1
addsd (%rcx,%r10), %xmm1
addsd -16(%r8,%r10), %xmm1
addsd -8(%r8,%r10), %xmm1
addsd (%r8,%r10), %xmm1
addsd -16(%rdi,%r10), %xmm1
addsd -8(%rdi,%r10), %xmm1
addsd (%rdi,%r10), %xmm1
divsd %xmm0, %xmm1
movsd %xmm1, (%r12,%r10)
addq $8, %r10
cmpq %r10, %r13
jne .LBB0_5
# %bb.6: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
addq %rbx, %rdi
addq %rbx, %r12
addq %rbx, %r8
addq %rbx, %rcx
cmpq %rax, %r9
jne .LBB0_4
jmp .LBB0_7
.LBB0_8: # %._crit_edge79
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13array_processPdS_ii, .Lfunc_end0-_Z13array_processPdS_ii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__GPU_processingPdS_i # -- Begin function _Z29__device_stub__GPU_processingPdS_i
.p2align 4, 0x90
.type _Z29__device_stub__GPU_processingPdS_i,@function
_Z29__device_stub__GPU_processingPdS_i: # @_Z29__device_stub__GPU_processingPdS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14GPU_processingPdS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z29__device_stub__GPU_processingPdS_i, .Lfunc_end1-_Z29__device_stub__GPU_processingPdS_i
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17GPU_array_processPdS_ii
.LCPI2_0:
.long 0x447a0000 # float 1000
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x0000000000000000 # double 0
.text
.globl _Z17GPU_array_processPdS_ii
.p2align 4, 0x90
.type _Z17GPU_array_processPdS_ii,@function
_Z17GPU_array_processPdS_ii: # @_Z17GPU_array_processPdS_ii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r14d
movq %rsi, %r15
movq %rdi, %rbx
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 40(%rsp), %rdi
callq hipEventCreate
movl %r14d, 28(%rsp) # 4-byte Spill
# kill: def $r14d killed $r14d def $r14
imull %r14d, %r14d
leaq (,%r14,8), %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, 128(%rsp) # 8-byte Spill
movq %r15, %rsi
movq %r12, 120(%rsp) # 8-byte Spill
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $256, %ebx # imm = 0x100
cmpl $15359, %r14d # imm = 0x3BFF
ja .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl $2290649225, %eax # imm = 0x88888889
imulq %r14, %rax
shrq $37, %rax
movl $256, %ecx # imm = 0x100
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
leal 3(%rcx), %ebx
testl %ecx, %ecx
cmovnsl %ecx, %ebx
sarl $2, %ebx
movl %ebx, %ecx
cmpl %eax, %ebx
jg .LBB2_2
.LBB2_3: # %._crit_edge
cvtsi2sd %ebx, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_5
# %bb.4:
sqrtsd %xmm0, %xmm0
jmp .LBB2_6
.LBB2_5: # %call.sqrt
callq sqrt
.LBB2_6: # %._crit_edge.split
callq ceil@PLT
movsd %xmm0, 112(%rsp) # 8-byte Spill
movl 28(%rsp), %ecx # 4-byte Reload
movl %ecx, %eax
shrl $31, %eax
addl %ecx, %eax
sarl %eax
imull %eax, %eax
cltd
idivl %ebx
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
ucomisd .LCPI2_1(%rip), %xmm0
jb .LBB2_8
# %bb.7:
sqrtsd %xmm0, %xmm0
jmp .LBB2_9
.LBB2_8: # %call.sqrt56
callq sqrt
.LBB2_9: # %._crit_edge.split.split
callq ceil@PLT
testl %ebp, %ebp
jle .LBB2_14
# %bb.10:
cvttsd2si 112(%rsp), %r12d # 8-byte Folded Reload
movabsq $4294967297, %rax # imm = 0x100000001
imulq %rax, %r12
cvttsd2si %xmm0, %r13d
imulq %rax, %r13
leaq 144(%rsp), %r14
leaq 136(%rsp), %rbx
leaq 64(%rsp), %r15
jmp .LBB2_11
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_11 Depth=1
callq hipDeviceSynchronize
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
decl %ebp
je .LBB2_14
.LBB2_11: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12: # in Loop: Header=BB2_11 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 192(%rsp)
movq %rcx, 184(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 60(%rsp)
leaq 192(%rsp), %rax
movq %rax, 64(%rsp)
leaq 184(%rsp), %rax
movq %rax, 72(%rsp)
leaq 60(%rsp), %rax
movq %rax, 80(%rsp)
leaq 168(%rsp), %rdi
leaq 152(%rsp), %rsi
movq %r14, %rdx
movq %rbx, %rcx
callq __hipPopCallConfiguration
movq 168(%rsp), %rsi
movl 176(%rsp), %edx
movq 152(%rsp), %rcx
movl 160(%rsp), %r8d
movl $_Z14GPU_processingPdS_i, %edi
movq %r15, %r9
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_13
.LBB2_14: # %._crit_edge55
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rsi
movq 128(%rsp), %rdi # 8-byte Reload
movq 120(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rdi
callq hipEventSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 104(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_27
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_17
# %bb.16:
movzbl 67(%r14), %eax
jmp .LBB2_18
.LBB2_17:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 96(%rsp), %rsi
movq 40(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_27
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i40
cmpb $0, 56(%r14)
je .LBB2_21
# %bb.20:
movzbl 67(%r14), %eax
jmp .LBB2_22
.LBB2_21:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit43
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 88(%rsp), %rsi
movq 32(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $4, _ZSt4cout+8(%rax)
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB2_27
# %bb.23: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
cmpb $0, 56(%r14)
je .LBB2_25
# %bb.24:
movzbl 67(%r14), %eax
jmp .LBB2_26
.LBB2_25:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_26: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 256
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z17GPU_array_processPdS_ii, .Lfunc_end2-_Z17GPU_array_processPdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14GPU_processingPdS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14GPU_processingPdS_i,@object # @_Z14GPU_processingPdS_i
.section .rodata,"a",@progbits
.globl _Z14GPU_processingPdS_i
.p2align 3, 0x0
_Z14GPU_processingPdS_i:
.quad _Z29__device_stub__GPU_processingPdS_i
.size _Z14GPU_processingPdS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Host to Device MemCpy takes "
.size .L.str, 29
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "s"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Computation takes "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Device to Host MemCpy takes "
.size .L.str.3, 29
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14GPU_processingPdS_i"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__GPU_processingPdS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14GPU_processingPdS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
pthread_mutex_lock(&lock);
ret = *ptr;
pthread_mutex_unlock(&lock);
return ret;
}
void set_shared_var_value(int *ptr, int val) {
pthread_mutex_lock(&lock);
(*ptr) = val;
pthread_mutex_unlock(&lock);
}
void dec_shared_var_value(int *ptr) {
pthread_mutex_lock(&lock);
(*ptr)--;
pthread_mutex_unlock(&lock);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
pthread_mutex_lock(&lock);
ret = *ptr;
pthread_mutex_unlock(&lock);
return ret;
}
void set_shared_var_value(int *ptr, int val) {
pthread_mutex_lock(&lock);
(*ptr) = val;
pthread_mutex_unlock(&lock);
}
void dec_shared_var_value(int *ptr) {
pthread_mutex_lock(&lock);
(*ptr)--;
pthread_mutex_unlock(&lock);
} | .file "tmpxft_00199400_00000000-6_atomic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20get_shared_var_valuePi
.type _Z20get_shared_var_valuePi, @function
_Z20get_shared_var_valuePi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq lock(%rip), %rbp
movq %rbp, %rdi
call pthread_mutex_lock@PLT
movl (%rbx), %ebx
movq %rbp, %rdi
call pthread_mutex_unlock@PLT
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z20get_shared_var_valuePi, .-_Z20get_shared_var_valuePi
.globl _Z20set_shared_var_valuePii
.type _Z20set_shared_var_valuePii, @function
_Z20set_shared_var_valuePii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
leaq lock(%rip), %r12
movq %r12, %rdi
call pthread_mutex_lock@PLT
movl %ebp, (%rbx)
movq %r12, %rdi
call pthread_mutex_unlock@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z20set_shared_var_valuePii, .-_Z20set_shared_var_valuePii
.globl _Z20dec_shared_var_valuePi
.type _Z20dec_shared_var_valuePi, @function
_Z20dec_shared_var_valuePi:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq lock(%rip), %rbp
movq %rbp, %rdi
call pthread_mutex_lock@PLT
subl $1, (%rbx)
movq %rbp, %rdi
call pthread_mutex_unlock@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z20dec_shared_var_valuePi, .-_Z20dec_shared_var_valuePi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
pthread_mutex_lock(&lock);
ret = *ptr;
pthread_mutex_unlock(&lock);
return ret;
}
void set_shared_var_value(int *ptr, int val) {
pthread_mutex_lock(&lock);
(*ptr) = val;
pthread_mutex_unlock(&lock);
}
void dec_shared_var_value(int *ptr) {
pthread_mutex_lock(&lock);
(*ptr)--;
pthread_mutex_unlock(&lock);
} | /*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <hip/hip_runtime.h>
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
pthread_mutex_lock(&lock);
ret = *ptr;
pthread_mutex_unlock(&lock);
return ret;
}
void set_shared_var_value(int *ptr, int val) {
pthread_mutex_lock(&lock);
(*ptr) = val;
pthread_mutex_unlock(&lock);
}
void dec_shared_var_value(int *ptr) {
pthread_mutex_lock(&lock);
(*ptr)--;
pthread_mutex_unlock(&lock);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <hip/hip_runtime.h>
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
pthread_mutex_lock(&lock);
ret = *ptr;
pthread_mutex_unlock(&lock);
return ret;
}
void set_shared_var_value(int *ptr, int val) {
pthread_mutex_lock(&lock);
(*ptr) = val;
pthread_mutex_unlock(&lock);
}
void dec_shared_var_value(int *ptr) {
pthread_mutex_lock(&lock);
(*ptr)--;
pthread_mutex_unlock(&lock);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Noopur Maheshwari : 111464061
* Rahul Rane : 111465246
*/
#include <hip/hip_runtime.h>
#include <pthread.h>
#include <iostream>
using namespace std;
extern pthread_mutex_t lock;
int get_shared_var_value(int *ptr) {
int ret;
pthread_mutex_lock(&lock);
ret = *ptr;
pthread_mutex_unlock(&lock);
return ret;
}
void set_shared_var_value(int *ptr, int val) {
pthread_mutex_lock(&lock);
(*ptr) = val;
pthread_mutex_unlock(&lock);
}
void dec_shared_var_value(int *ptr) {
pthread_mutex_lock(&lock);
(*ptr)--;
pthread_mutex_unlock(&lock);
} | .text
.file "atomic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20get_shared_var_valuePi # -- Begin function _Z20get_shared_var_valuePi
.p2align 4, 0x90
.type _Z20get_shared_var_valuePi,@function
_Z20get_shared_var_valuePi: # @_Z20get_shared_var_valuePi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $lock, %edi
callq pthread_mutex_lock
movl (%rbx), %ebx
movl $lock, %edi
callq pthread_mutex_unlock
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20get_shared_var_valuePi, .Lfunc_end0-_Z20get_shared_var_valuePi
.cfi_endproc
# -- End function
.globl _Z20set_shared_var_valuePii # -- Begin function _Z20set_shared_var_valuePii
.p2align 4, 0x90
.type _Z20set_shared_var_valuePii,@function
_Z20set_shared_var_valuePii: # @_Z20set_shared_var_valuePii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
movq %rdi, %r14
movl $lock, %edi
callq pthread_mutex_lock
movl %ebx, (%r14)
movl $lock, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp pthread_mutex_unlock # TAILCALL
.Lfunc_end1:
.size _Z20set_shared_var_valuePii, .Lfunc_end1-_Z20set_shared_var_valuePii
.cfi_endproc
# -- End function
.globl _Z20dec_shared_var_valuePi # -- Begin function _Z20dec_shared_var_valuePi
.p2align 4, 0x90
.type _Z20dec_shared_var_valuePi,@function
_Z20dec_shared_var_valuePi: # @_Z20dec_shared_var_valuePi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $lock, %edi
callq pthread_mutex_lock
decl (%rbx)
movl $lock, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp pthread_mutex_unlock # TAILCALL
.Lfunc_end2:
.size _Z20dec_shared_var_valuePi, .Lfunc_end2-_Z20dec_shared_var_valuePi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym lock
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00199400_00000000-6_atomic.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3674:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20get_shared_var_valuePi
.type _Z20get_shared_var_valuePi, @function
_Z20get_shared_var_valuePi:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq lock(%rip), %rbp
movq %rbp, %rdi
call pthread_mutex_lock@PLT
movl (%rbx), %ebx
movq %rbp, %rdi
call pthread_mutex_unlock@PLT
movl %ebx, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z20get_shared_var_valuePi, .-_Z20get_shared_var_valuePi
.globl _Z20set_shared_var_valuePii
.type _Z20set_shared_var_valuePii, @function
_Z20set_shared_var_valuePii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
leaq lock(%rip), %r12
movq %r12, %rdi
call pthread_mutex_lock@PLT
movl %ebp, (%rbx)
movq %r12, %rdi
call pthread_mutex_unlock@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z20set_shared_var_valuePii, .-_Z20set_shared_var_valuePii
.globl _Z20dec_shared_var_valuePi
.type _Z20dec_shared_var_valuePi, @function
_Z20dec_shared_var_valuePi:
.LFB3671:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
leaq lock(%rip), %rbp
movq %rbp, %rdi
call pthread_mutex_lock@PLT
subl $1, (%rbx)
movq %rbp, %rdi
call pthread_mutex_unlock@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z20dec_shared_var_valuePi, .-_Z20dec_shared_var_valuePi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "atomic.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z20get_shared_var_valuePi # -- Begin function _Z20get_shared_var_valuePi
.p2align 4, 0x90
.type _Z20get_shared_var_valuePi,@function
_Z20get_shared_var_valuePi: # @_Z20get_shared_var_valuePi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $lock, %edi
callq pthread_mutex_lock
movl (%rbx), %ebx
movl $lock, %edi
callq pthread_mutex_unlock
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z20get_shared_var_valuePi, .Lfunc_end0-_Z20get_shared_var_valuePi
.cfi_endproc
# -- End function
.globl _Z20set_shared_var_valuePii # -- Begin function _Z20set_shared_var_valuePii
.p2align 4, 0x90
.type _Z20set_shared_var_valuePii,@function
_Z20set_shared_var_valuePii: # @_Z20set_shared_var_valuePii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
movq %rdi, %r14
movl $lock, %edi
callq pthread_mutex_lock
movl %ebx, (%r14)
movl $lock, %edi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp pthread_mutex_unlock # TAILCALL
.Lfunc_end1:
.size _Z20set_shared_var_valuePii, .Lfunc_end1-_Z20set_shared_var_valuePii
.cfi_endproc
# -- End function
.globl _Z20dec_shared_var_valuePi # -- Begin function _Z20dec_shared_var_valuePi
.p2align 4, 0x90
.type _Z20dec_shared_var_valuePi,@function
_Z20dec_shared_var_valuePi: # @_Z20dec_shared_var_valuePi
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movl $lock, %edi
callq pthread_mutex_lock
decl (%rbx)
movl $lock, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp pthread_mutex_unlock # TAILCALL
.Lfunc_end2:
.size _Z20dec_shared_var_valuePi, .Lfunc_end2-_Z20dec_shared_var_valuePi
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym lock
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // includes, system
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <cuda_runtime.h>
#define N 256
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg) {
cudaError_t err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv) {
// pointers for host memory and size
int *h_a = NULL, *h_b = NULL;
// pointers for device memory
int *d_a = NULL;
h_a = (int*)malloc(sizeof(int) * N);
h_b = (int*)malloc(sizeof(int) * N);
cudaMalloc(&d_a, sizeof(int)*N);
// Initialize h_a to contain integers 0 .. N - 1
for (int i = 0; i < N; i++) {
h_a[i] = i;
}
// Zero memory for h_b
memset(h_b, 0, N * sizeof(int));
cudaMemcpy(d_a, h_a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(h_b, d_a, N * sizeof(int), cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("memcpy");
for (int i = 0; i < N; i++) {
if (h_a[i] != h_b[i]) {
printf("Test failed h_a[%d] != h_b[%d]\n", i, i);
exit(1);
}
}
free(h_b);
free(h_a);
cudaFree(d_a);
printf("Test passed!\n");
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // includes, system
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <cuda_runtime.h>
#define N 256
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg) {
cudaError_t err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv) {
// pointers for host memory and size
int *h_a = NULL, *h_b = NULL;
// pointers for device memory
int *d_a = NULL;
h_a = (int*)malloc(sizeof(int) * N);
h_b = (int*)malloc(sizeof(int) * N);
cudaMalloc(&d_a, sizeof(int)*N);
// Initialize h_a to contain integers 0 .. N - 1
for (int i = 0; i < N; i++) {
h_a[i] = i;
}
// Zero memory for h_b
memset(h_b, 0, N * sizeof(int));
cudaMemcpy(d_a, h_a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(h_b, d_a, N * sizeof(int), cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("memcpy");
for (int i = 0; i < N; i++) {
if (h_a[i] != h_b[i]) {
printf("Test failed h_a[%d] != h_b[%d]\n", i, i);
exit(1);
}
}
free(h_b);
free(h_a);
cudaFree(d_a);
printf("Test passed!\n");
return 0;
} | .file "tmpxft_001aacb1_00000000-6_data_movement.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.section .rodata.str1.1
.LC1:
.string "memcpy"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Test failed h_a[%d] != h_b[%d]\n"
.section .rodata.str1.1
.LC3:
.string "Test passed!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %rbx
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $0, %eax
.L8:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L8
movl $128, %ecx
movl $0, %eax
movq %rbp, %rdi
rep stosq
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $0, %eax
.L10:
movl 0(%rbp,%rax,4), %edx
cmpl %edx, (%rbx,%rax,4)
jne .L15
addq $1, %rax
cmpq $256, %rax
jne .L10
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %eax, %edx
movl %eax, %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // includes, system
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <cuda_runtime.h>
#define N 256
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg) {
cudaError_t err = cudaGetLastError();
if( err != cudaSuccess) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, cudaGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv) {
// pointers for host memory and size
int *h_a = NULL, *h_b = NULL;
// pointers for device memory
int *d_a = NULL;
h_a = (int*)malloc(sizeof(int) * N);
h_b = (int*)malloc(sizeof(int) * N);
cudaMalloc(&d_a, sizeof(int)*N);
// Initialize h_a to contain integers 0 .. N - 1
for (int i = 0; i < N; i++) {
h_a[i] = i;
}
// Zero memory for h_b
memset(h_b, 0, N * sizeof(int));
cudaMemcpy(d_a, h_a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(h_b, d_a, N * sizeof(int), cudaMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("memcpy");
for (int i = 0; i < N; i++) {
if (h_a[i] != h_b[i]) {
printf("Test failed h_a[%d] != h_b[%d]\n", i, i);
exit(1);
}
}
free(h_b);
free(h_a);
cudaFree(d_a);
printf("Test passed!\n");
return 0;
} | // includes, system
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 256
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg) {
hipError_t err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv) {
// pointers for host memory and size
int *h_a = NULL, *h_b = NULL;
// pointers for device memory
int *d_a = NULL;
h_a = (int*)malloc(sizeof(int) * N);
h_b = (int*)malloc(sizeof(int) * N);
hipMalloc(&d_a, sizeof(int)*N);
// Initialize h_a to contain integers 0 .. N - 1
for (int i = 0; i < N; i++) {
h_a[i] = i;
}
// Zero memory for h_b
memset(h_b, 0, N * sizeof(int));
hipMemcpy(d_a, h_a, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(h_b, d_a, N * sizeof(int), hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("memcpy");
for (int i = 0; i < N; i++) {
if (h_a[i] != h_b[i]) {
printf("Test failed h_a[%d] != h_b[%d]\n", i, i);
exit(1);
}
}
free(h_b);
free(h_a);
hipFree(d_a);
printf("Test passed!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // includes, system
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 256
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg) {
hipError_t err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv) {
// pointers for host memory and size
int *h_a = NULL, *h_b = NULL;
// pointers for device memory
int *d_a = NULL;
h_a = (int*)malloc(sizeof(int) * N);
h_b = (int*)malloc(sizeof(int) * N);
hipMalloc(&d_a, sizeof(int)*N);
// Initialize h_a to contain integers 0 .. N - 1
for (int i = 0; i < N; i++) {
h_a[i] = i;
}
// Zero memory for h_b
memset(h_b, 0, N * sizeof(int));
hipMemcpy(d_a, h_a, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(h_b, d_a, N * sizeof(int), hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("memcpy");
for (int i = 0; i < N; i++) {
if (h_a[i] != h_b[i]) {
printf("Test failed h_a[%d] != h_b[%d]\n", i, i);
exit(1);
}
}
free(h_b);
free(h_a);
hipFree(d_a);
printf("Test passed!\n");
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // includes, system
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define N 256
// Simple utility function to check for CUDA runtime errors
void checkCUDAError(const char *msg) {
hipError_t err = hipGetLastError();
if( err != hipSuccess) {
fprintf(stderr, "Cuda error: %s: %s.\n", msg, hipGetErrorString( err) );
exit(EXIT_FAILURE);
}
}
///////////////////////////////////////////////////////////////////////////////
// Program main
///////////////////////////////////////////////////////////////////////////////
int main( int argc, char** argv) {
// pointers for host memory and size
int *h_a = NULL, *h_b = NULL;
// pointers for device memory
int *d_a = NULL;
h_a = (int*)malloc(sizeof(int) * N);
h_b = (int*)malloc(sizeof(int) * N);
hipMalloc(&d_a, sizeof(int)*N);
// Initialize h_a to contain integers 0 .. N - 1
for (int i = 0; i < N; i++) {
h_a[i] = i;
}
// Zero memory for h_b
memset(h_b, 0, N * sizeof(int));
hipMemcpy(d_a, h_a, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(h_b, d_a, N * sizeof(int), hipMemcpyDeviceToHost);
// Check for any CUDA errors
checkCUDAError("memcpy");
for (int i = 0; i < N; i++) {
if (h_a[i] != h_b[i]) {
printf("Test failed h_a[%d] != h_b[%d]\n", i, i);
exit(1);
}
}
free(h_b);
free(h_a);
hipFree(d_a);
printf("Test passed!\n");
return 0;
} | .text
.file "data_movement.hip"
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKc, .Lfunc_end0-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, (%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_1
# %bb.2:
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movq (%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.3: # %_Z14checkCUDAErrorPKc.exit.preheader.preheader
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_4: # %_Z14checkCUDAErrorPKc.exit.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rdx,4), %eax
cmpl (%r14,%rdx,4), %eax
jne .LBB1_5
# %bb.7: # %_Z14checkCUDAErrorPKc.exit
# in Loop: Header=BB1_4 Depth=1
incq %rdx
cmpq $256, %rdx # imm = 0x100
jne .LBB1_4
# %bb.8:
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 32
movl $.L.str.2, %edi
movl %edx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memcpy"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Test failed h_a[%d] != h_b[%d]\n"
.size .L.str.2, 32
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test passed!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aacb1_00000000-6_data_movement.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Cuda error: %s: %s.\n"
.text
.globl _Z14checkCUDAErrorPKc
.type _Z14checkCUDAErrorPKc, @function
_Z14checkCUDAErrorPKc:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
call cudaGetLastError@PLT
testl %eax, %eax
jne .L6
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movq %rbx, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14checkCUDAErrorPKc, .-_Z14checkCUDAErrorPKc
.section .rodata.str1.1
.LC1:
.string "memcpy"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Test failed h_a[%d] != h_b[%d]\n"
.section .rodata.str1.1
.LC3:
.string "Test passed!\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movl $1024, %edi
call malloc@PLT
movq %rax, %rbx
movl $1024, %edi
call malloc@PLT
movq %rax, %rbp
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl $0, %eax
.L8:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $256, %rax
jne .L8
movl $128, %ecx
movl $0, %eax
movq %rbp, %rdi
rep stosq
movl $1, %ecx
movl $1024, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $1024, %edx
movq (%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rdi
call _Z14checkCUDAErrorPKc
movl $0, %eax
.L10:
movl 0(%rbp,%rax,4), %edx
cmpl %edx, (%rbx,%rax,4)
jne .L15
addq $1, %rax
cmpq $256, %rax
jne .L10
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %eax, %edx
movl %eax, %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "data_movement.hip"
.globl _Z14checkCUDAErrorPKc # -- Begin function _Z14checkCUDAErrorPKc
.p2align 4, 0x90
.type _Z14checkCUDAErrorPKc,@function
_Z14checkCUDAErrorPKc: # @_Z14checkCUDAErrorPKc
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
callq hipGetLastError
testl %eax, %eax
jne .LBB0_2
# %bb.1:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 32
movq stderr(%rip), %r14
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %r14, %rdi
movq %rbx, %rdx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end0:
.size _Z14checkCUDAErrorPKc, .Lfunc_end0-_Z14checkCUDAErrorPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, (%rsp)
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %rbx
movl $1024, %edi # imm = 0x400
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $256, %rax # imm = 0x100
jne .LBB1_1
# %bb.2:
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movq (%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $1024, %edx # imm = 0x400
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.3: # %_Z14checkCUDAErrorPKc.exit.preheader.preheader
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_4: # %_Z14checkCUDAErrorPKc.exit.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%rdx,4), %eax
cmpl (%r14,%rdx,4), %eax
jne .LBB1_5
# %bb.7: # %_Z14checkCUDAErrorPKc.exit
# in Loop: Header=BB1_4 Depth=1
incq %rdx
cmpq $256, %rdx # imm = 0x100
jne .LBB1_4
# %bb.8:
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 32
movl $.L.str.2, %edi
movl %edx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %edx
movq %rbx, %rdi
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda error: %s: %s.\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "memcpy"
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Test failed h_a[%d] != h_b[%d]\n"
.size .L.str.2, 32
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Test passed!"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
//#include <helper_math.h>
//#include <nvMatrix.h>
//#include "Constructor.h"
#include "cuda.h"
extern __device__ float4* d_cuda_construct_texture; | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
//#include <helper_math.h>
//#include <nvMatrix.h>
//#include "Constructor.h"
#include "cuda.h"
extern __device__ float4* d_cuda_construct_texture; | .file "tmpxft_0001fd72_00000000-6_Constructor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "d_cuda_construct_texture"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL24d_cuda_construct_texture(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL24d_cuda_construct_texture
.comm _ZL24d_cuda_construct_texture,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
//#include <helper_math.h>
//#include <nvMatrix.h>
//#include "Constructor.h"
#include "cuda.h"
extern __device__ float4* d_cuda_construct_texture; | //
//#include <helper_math.h>
//#include <nvMatrix.h>
//#include "Constructor.h"
#include "hip/hip_runtime.h"
extern __device__ float4* d_cuda_construct_texture; |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
//#include <helper_math.h>
//#include <nvMatrix.h>
//#include "Constructor.h"
#include "hip/hip_runtime.h"
extern __device__ float4* d_cuda_construct_texture; | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
//#include <helper_math.h>
//#include <nvMatrix.h>
//#include "Constructor.h"
#include "hip/hip_runtime.h"
extern __device__ float4* d_cuda_construct_texture; | .text
.file "Constructor.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001fd72_00000000-6_Constructor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "d_cuda_construct_texture"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL24d_cuda_construct_texture(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL24d_cuda_construct_texture
.comm _ZL24d_cuda_construct_texture,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Constructor.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // adaptation of Pavel's imreconstruction code for openCV
#include <thrust/device_vector.h>
#include <thrust/device_ptr.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/tuple.h>
#include <thrust/functional.h>
#include <thrust/tuple.h>
#include <thrust/iterator/permutation_iterator.h>
#include <thrust/copy.h>
#include <thrust/unique.h>
#include <thrust/sort.h>
#include <thrust/count.h>
#define MAX_THREADS 256
#define XX_THREADS 4
#define XY_THREADS 32
#define NEQ(a,b) ( (a) != (b) )
#define WARP_SIZE 32
//using namespace cv::gpu;
//using namespace cv::gpu::device;
namespace nscale { namespace gpu {
////////////////////////////////////////////////////////////////////////////////
// RECONSTRUCTION BY DILATION
////////////////////////////////////////////////////////////////////////////////
/*
* warp = 32. shared memory in banks of 32, each 32 bits (128 bytes wide) - interleave of 4 for rows? no need. compute 2 has no conflict for read/write bytes.
* global memory in partitions of 256 bytes. 1 warp at a time at 1, 2, 4, 8, or 16 bytes. width of array and threadblock = warpsize * c,
* try to remove syncthreads by making sure warps do not diverge(and use volatile)
* thread id = x + y * Dx. so this means if x and y are swapped between mem and compute steps, must have sync...
* IF 32 x 8 theads, repeat 4 times in y. read single char from global, then swap x and y to process 32 y at a time, would need to syncthread inside iterations. can use 1 warp to go through all shared mem iteratively, or have each warp compute 4 bytes 4 columns (warps are ordered)
* IF 8x4 or 4x8 threads for a warp, read 1 bytes from global (linearize the warp thread id (e.g. x + y*8 or x+y*4) to read from global sequentially, and repeat 4 or 8 times) then process the memory for this warp 4 y or 8 y iteratively, repeat for all x chunks. essentially the original algorithm. then create threadblock that is just multiplied in y to reach 192 or 256. avoids syncthreads completely.
* or alternatively, treat each warp as 4x8, and each x process columns 8 apart. each warp then do 4 bytes, (8 warps), to generate 8x8 blocks that are completed. - no synthreads needed. - no... would require more kernel iterations
for backward: thread ids should map to the data - so first thread has the last data.... ( for correctness)
for y, similar to this...
for register usage: use unsigned int where possible. maybe use 1D shared array would be better too...
*/
template <typename T>
__global__ void
iRec1DForward_X_dilation ( T* marker, const T* mask, const unsigned int sx, const unsigned int sy)
{
const unsigned int x = (threadIdx.x + threadIdx.y * XX_THREADS) % WARP_SIZE;
const unsigned int y = (threadIdx.x + threadIdx.y * XX_THREADS) / WARP_SIZE;
const unsigned int ychunk = WARP_SIZE / XX_THREADS;
const unsigned int xstop = sx - WARP_SIZE;
// printf("(tx, ty) -> (x, y) : (%d, %d)->(%d,%d)\n", threadIdx.x, threadIdx.y, x, y);
// XY_THREADS should be 32==warpSize, XX_THREADS should be 4 or 8.
// init to 0...
volatile __shared__ T s_marker[XY_THREADS][WARP_SIZE+1];
volatile __shared__ T s_mask [XY_THREADS][WARP_SIZE+1];
T s_old, s_new;
unsigned int startx;
unsigned int start;
s_marker[threadIdx.y][WARP_SIZE] = 0; // only need x=0 to be 0
// the increment allows overlap by 1 between iterations to move the data to next block.
for (startx = 0; startx < xstop; startx += WARP_SIZE) {
start = (blockIdx.x * XY_THREADS + y * ychunk) * sx + startx + x;
// printf("tx: %d, ty: %d, x: %d, y: %d, startx: %d, start: %d", threadIdx.x, threadIdx.y, x, y, startx, start);
s_marker[threadIdx.y][0] = s_marker[threadIdx.y][WARP_SIZE];
// copy part of marker and mask to shared memory. works for 1 warp at a time...
//#pragma unroll
for (unsigned int i = 0; i < ychunk && y*ychunk+i < sy; ++i) {
s_marker[y * ychunk+i][x+1] = marker[start + i*sx];
s_mask [y * ychunk+i][x+1] = mask[start + i*sx];
}
// perform iteration all X threads do the same operations, so there may be read/write hazards. but the output is the same.
// this is looping for BLOCK_SIZE times, and each iteration the final results are propagated 1 step closer to tx.
// if (threadIdx.x == 0) { // have all threads do the same work
//#pragma unroll
if (threadIdx.y + blockIdx.x * XY_THREADS < sy) { //require dimension to be perfectly padded.
for (unsigned int i = 1; i <= WARP_SIZE; ++i) {
s_old = s_marker[threadIdx.y][i];
s_new = min( max( s_marker[threadIdx.y][i-1], s_old ), s_mask[threadIdx.y][i] );
s_marker[threadIdx.y][i] = s_new;
}
}
// output result back to global memory and set up for next x chunk
//#pragma unroll
for (unsigned int i = 0; i < ychunk && y*ychunk+i < sy; ++i) {
marker[start + i*sx] = s_marker[y * ychunk+i][x+1];
}
// printf("startx: %d, change = %d\n", startx, s_change);
}
if (startx < sx) {
s_marker[threadIdx.y][0] = s_marker[threadIdx.y][sx-startx]; // getting ix-1st entry, which has been offsetted by 1 in s_marker
// shared mem copy
startx = sx - WARP_SIZE;
start = (blockIdx.x * XY_THREADS + y * ychunk) * sx + startx + x;
// printf("tx: %d, ty: %d, x: %d, y: %d, startx: %d, start: %d", threadIdx.x, threadIdx.y, x, y, startx, start);
// copy part of marker and mask to shared memory. works for 1 warp at a time...
//#pragma unroll
for (unsigned int i = 0; i < ychunk && y*ychunk+i < sy; ++i) {
s_marker[y * ychunk+i][x+1] = marker[start + i*sx];
s_mask [y * ychunk+i][x+1] = mask[start + i*sx];
}
// perform iteration all X threads do the same operations, so there may be read/write hazards. but the output is the same.
// this is looping for BLOCK_SIZE times, and each iteration the final results are propagated 1 step closer to tx.
//#pragma unroll
if (threadIdx.y + blockIdx.x * XY_THREADS < sy) { //require dimension to be perfectly padded.
for (unsigned int i = 1; i <= WARP_SIZE; ++i) {
s_old = s_marker[threadIdx.y][i];
s_new = min( max( s_marker[threadIdx.y][i-1], s_old ), s_mask[threadIdx.y][i] );
s_marker[threadIdx.y][i] = s_new;
}
}
// output result back to global memory and set up for next x chunk
//#pragma unroll
for (unsigned int i = 0; i < ychunk && y*ychunk+i < sy; ++i) {
marker[start + i*sx] = s_marker[y * ychunk+i][x+1];
}
}
}
template <typename T>
__global__ void
iRec1DBackward_X_dilation ( T* __restrict__ marker, const T* __restrict__ mask, const int sx, const int sy)
{
const unsigned int x = (threadIdx.x + threadIdx.y * XX_THREADS) % WARP_SIZE;
const unsigned int y = (threadIdx.x + threadIdx.y * XX_THREADS) / WARP_SIZE;
const unsigned int ychunk = WARP_SIZE / XX_THREADS;
const unsigned int xstop = sx - WARP_SIZE;
// printf("(tx, ty) -> (x, y) : (%d, %d)->(%d,%d)\n", threadIdx.x, threadIdx.y, x, y);
// XY_THREADS should be 32==warpSize, XX_THREADS should be 4 or 8.
// init to 0...
volatile __shared__ T s_marker[XY_THREADS][WARP_SIZE+1];
volatile __shared__ T s_mask [XY_THREADS][WARP_SIZE+1];
T s_old, s_new;
int startx;
unsigned int start;
s_marker[threadIdx.y][0] = 0; // only need x=WARPSIZE to be 0
// the increment allows overlap by 1 between iterations to move the data to next block.
for (startx = xstop; startx > 0; startx -= WARP_SIZE) {
start = (blockIdx.x * XY_THREADS + y * ychunk) * sx + startx + x;
// printf("tx: %d, ty: %d, x: %d, y: %d, startx: %d, start: %d", threadIdx.x, threadIdx.y, x, y, startx, start);
s_marker[threadIdx.y][WARP_SIZE] = s_marker[threadIdx.y][0];
// copy part of marker and mask to shared memory. works for 1 warp at a time...
//#pragma unroll
for (unsigned int i = 0; i < ychunk && y*ychunk+i < sy; ++i) {
s_marker[y * ychunk+i][x] = marker[start + i*sx];
s_mask [y * ychunk+i][x] = mask[start + i*sx];
}
// perform iteration all X threads do the same operations, so there may be read/write hazards. but the output is the same.
// this is looping for BLOCK_SIZE times, and each iteration the final results are propagated 1 step closer to tx.
// if (threadIdx.x == 0) { // have all threads do the same work
//#pragma unroll
if (threadIdx.y + blockIdx.x * XY_THREADS < sy) { //require dimension to be perfectly padded.
for (int i = WARP_SIZE - 1; i >= 0; --i) {
s_old = s_marker[threadIdx.y][i];
s_new = min( max( s_marker[threadIdx.y][i+1], s_old ), s_mask[threadIdx.y][i] );
s_marker[threadIdx.y][i] = s_new;
}
}
// output result back to global memory and set up for next x chunk
//#pragma unroll
for (unsigned int i = 0; i < ychunk && y*ychunk+i < sy; ++i) {
marker[start + i*sx] = s_marker[y * ychunk+i][x];
}
// printf("startx: %d, change = %d\n", startx, s_change);
}
if (startx <= 0) {
s_marker[threadIdx.y][WARP_SIZE] = s_marker[threadIdx.y][-startx]; // getting ix-1st entry, which has been offsetted by 1 in s_marker
// shared mem copy
startx = 0;
start = (blockIdx.x * XY_THREADS + y * ychunk) * sx + startx + x;
// printf("tx: %d, ty: %d, x: %d, y: %d, startx: %d, start: %d", threadIdx.x, threadIdx.y, x, y, startx, start);
// copy part of marker and mask to shared memory. works for 1 warp at a time...
//#pragma unroll
for (unsigned int i = 0; i < ychunk && y*ychunk+i < sy; ++i) {
s_marker[y * ychunk+i][x] = marker[start + i*sx];
s_mask [y * ychunk+i][x] = mask[start + i*sx];
}
// perform iteration all X threads do the same operations, so there may be read/write hazards. but the output is the same.
// this is looping for BLOCK_SIZE times, and each iteration the final results are propagated 1 step closer to tx.
//#pragma unroll
if (threadIdx.y + blockIdx.x * XY_THREADS < sy) { //require dimension to be perfectly padded.
for (int i = WARP_SIZE - 1; i >= 0; --i) {
s_old = s_marker[threadIdx.y][i];
s_new = min( max( s_marker[threadIdx.y][i+1], s_old ), s_mask[threadIdx.y][i] );
s_marker[threadIdx.y][i] = s_new;
}
}
// output result back to global memory and set up for next x chunk
//#pragma unroll
for (unsigned int i = 0; i < ychunk && y*ychunk+i < sy; ++i) {
marker[start + i*sx] = s_marker[y * ychunk+i][x];
}
}
}
template <typename T>
__global__ void
iRec1DForward_Y_dilation ( T* __restrict__ marker, const T* __restrict__ mask, const int sx, const int sy)
{
// parallelize along x.
const int tx = threadIdx.x;
const int bx = blockIdx.x * MAX_THREADS;
T s_old, s_new, s_prev;
if ( (bx + tx) < sx ) {
s_prev = 0;
for (int iy = 0; iy < sy; ++iy) {
// copy part of marker and mask to shared memory
s_old = marker[iy * sx + bx + tx];
// perform iteration
s_new = min( max( s_prev, s_old ), mask[iy * sx + bx + tx] );
s_prev = s_new;
// output result back to global memory
marker[iy * sx + bx + tx] = s_new;
}
}
}
template <typename T>
__global__ void
iRec1DBackward_Y_dilation ( T* __restrict__ marker, const T* __restrict__ mask, const unsigned int sx, const unsigned int sy )
{
const int tx = threadIdx.x;
const int bx = blockIdx.x * MAX_THREADS;
T s_old, s_new, s_prev;
if ( (bx + tx) < sx ) {
s_prev = 0;
for (int iy = sy - 1; iy >= 0; --iy) {
// copy part of marker and mask to shared memory
s_old = marker[iy * sx + bx + tx];
// perform iteration
s_new = min( max( s_prev, s_old ), mask[iy * sx + bx + tx] );
s_prev = s_new;
// output result back to global memory
marker[iy * sx + bx + tx] = s_new;
}
}
}
template <typename T>
__global__ void
iRec1DForward_Y_dilation_8 ( T* __restrict__ marker, const T* __restrict__ mask, const unsigned int sx, const unsigned int sy)
{
// best thing to do is to use linear arrays. each warp does a column of 32.
// parallelize along x.
const unsigned int tx = threadIdx.x;
const unsigned int bx = blockIdx.x * MAX_THREADS;
volatile __shared__ T s_marker_B[MAX_THREADS+2];
volatile T* s_marker = s_marker_B + 1;
T s_new, s_old, s_prev;
if ( bx + tx < sx ) { // make sure number of threads is a divisor of sx.
s_prev = 0;
for (int iy = 0; iy < sy; ++iy) {
// copy part of marker and mask to shared memory
if (tx == 0) {
s_marker_B[0] = (bx == 0) ? 0 : marker[iy*sx + bx - 1];
s_marker[MAX_THREADS] = (bx + MAX_THREADS >= sx) ? 0 : marker[iy*sx + bx + MAX_THREADS];
}
if (tx < WARP_SIZE) {
// first warp, get extra stuff
s_marker[tx] = marker[iy*sx + bx + tx];
}
if (tx < MAX_THREADS - WARP_SIZE) {
s_marker[tx + WARP_SIZE] = marker[iy*sx + bx + tx + WARP_SIZE];
}
__syncthreads();
// perform iteration
s_old = s_marker[tx];
s_new = min( max( s_prev, s_old ), mask[iy*sx + bx + tx]);
// output result back to global memory
s_marker[tx] = s_new;
marker[iy*sx + bx + tx] = s_new;
__syncthreads();
s_prev = max( max(s_marker[tx-1], s_marker[tx]), s_marker[tx+1]);
}
}
}
template <typename T>
__global__ void
iRec1DBackward_Y_dilation_8 ( T* __restrict__ marker, const T* __restrict__ mask, const int sx, const int sy)
{
const int tx = threadIdx.x;
const int bx = blockIdx.x * MAX_THREADS;
volatile __shared__ T s_marker_B[MAX_THREADS+2];
volatile T* s_marker = s_marker_B + 1;
T s_new, s_old, s_prev;
if ( bx + tx < sx ) { //make sure number of threads is a divisor of sx.
s_prev = 0;
for (int iy = sy - 1; iy >= 0; --iy) {
if (tx == 0) {
s_marker_B[0] = (bx == 0) ? 0 : marker[iy*sx + bx - 1];
s_marker[MAX_THREADS] = (bx + MAX_THREADS >= sx) ? 0 : marker[iy*sx + bx + MAX_THREADS];
}
if (tx < WARP_SIZE) {
// first warp, get extra stuff
s_marker[tx] = marker[iy*sx + bx + tx];
}
if (tx < MAX_THREADS - WARP_SIZE) {
s_marker[tx + WARP_SIZE] = marker[iy*sx + bx + tx + WARP_SIZE];
}
__syncthreads();
// perform iteration
s_old = s_marker[tx];
s_new = min( max( s_prev, s_old ), mask[iy*sx + bx + tx]);
// output result back to global memory
s_marker[tx] = s_new;
marker[iy*sx + bx + tx] = s_new;
__syncthreads();
s_prev = max( max(s_marker[tx-1], s_marker[tx]), s_marker[tx+1]);
}
}
}
template<typename T, typename TN>
struct InitialImageToQueue : public thrust::unary_function<TN, int>
{
__host__ __device__
int operator()(const TN& pixel) const
{
T center = thrust::get<1>(pixel);
T curr;
int id = thrust::get<0>(pixel);
curr = thrust::get<2>(pixel);
if (curr < center && curr < thrust::get<6>(pixel)) return id;
curr = thrust::get<3>(pixel);
if (curr < center && curr < thrust::get<7>(pixel)) return id;
curr = thrust::get<4>(pixel);
if (curr < center && curr < thrust::get<8>(pixel)) return id;
curr = thrust::get<5>(pixel);
if (curr < center && curr < thrust::get<9>(pixel)) return id;
return -1;
}
};
// this works
//template<typename T, typename TN>
//struct ReconPixel : public thrust::unary_function<TN, int>
//{
// __host__ __device__
// int operator()(const TN& pixel)
// {
// thrust::minimum<T> mn;
// T center = thrust::get<1>(pixel);
// int id = thrust::get<0>(pixel);
// T q = thrust::get<2>(pixel);
// T p = thrust::get<6>(pixel);
// if (q < center && p != q) {
// q = mn(center, p);
// return id - 4098;
// }
// return -1;
// }
//};
// this works too.
//template<typename T, typename TN>
//struct ReconPixel : public thrust::unary_function<TN, T>
//{
// __host__ __device__
// T operator()(const TN& pixel)
// {
// thrust::minimum<T> mn;
// int idx1 = -1;
// T center = thrust::get<1>(pixel);
// int id = thrust::get<0>(pixel);
//
// T q = thrust::get<2>(pixel);
// T p = thrust::get<3>(pixel);
// if (q < center && p != q) {
// q = mn(center, p);
// idx1 = id - 4098;
// }
// return q;
// }
//};
// this works too
//template<typename T, typename TN, typename TN2>
//struct ReconPixel : public thrust::unary_function<TN, T>
//{
// __host__ __device__
// T operator()(TN pixel)
// {
// thrust::minimum<T> mn;
// int idx1 = -1;
// T center = thrust::get<1>(pixel);
// int id = thrust::get<0>(pixel);
//
// T q = thrust::get<2>(pixel);
// T p = thrust::get<3>(pixel);
// if (q < center && p != q) {
// q = mn(center, p);
// idx1 = id - 4098;
// }
// thrust::get<2>(pixel) = q;
//// TN2 test= thrust::make_tuple(idx1, q);
// return q;
// }
//};
// DOES NOT WORK
//template<typename T, typename TN, typename TN2>
//struct ReconPixel : public thrust::unary_function<TN, TN2>
//{
// __host__ __device__
// TN2 operator()(TN pixel)
// {
// thrust::minimum<T> mn;
// int idx1 = -1;
// T center = thrust::get<1>(pixel);
// int id = thrust::get<0>(pixel);
//
// T q = thrust::get<2>(pixel);
// T p = thrust::get<3>(pixel);
// if (q < center && p != q) {
// q = mn(center, p);
// idx1 = id - 4098;
// }
//// thrust::get<2>(pixel) = q;
//// TN2 test= thrust::make_tuple(idx1, q);
// return TN2(idx1, q);
// }
//};
// DOES NOT UPDATE INPUT
//template<typename T, typename TN, typename TO>
//struct ReconPixel : public thrust::binary_function<TN, TO, bool>
//{
// int step1, step2, step3, step4;
//
// __host__ __device__
// ReconPixel(int _s1, int _s2, int _s3, int _s4) : step1(_s1), step2(_s2), step3(_s3), step4(_s4) {}
//
// __host__ __device__
// bool operator()(TN pixel, TO queue)
// {
// thrust::minimum<T> mn;
// int id = thrust::get<0>(pixel);
// T center = thrust::get<1>(pixel);
// T p, q;
// int nextId;
// bool result = false;
//
// q = thrust::get<2>(pixel);
// p = thrust::get<6>(pixel);
// nextId = -1;
// if (q < center && q != p) {
// thrust::get<2>(pixel) = mn(center, p);
// nextId = id + step1;
// result = true;
// }
// thrust::get<0>(queue) = nextId;
//
// q = thrust::get<3>(pixel);
// p = thrust::get<7>(pixel);
// nextId = -2;
// if (q < center && q != p) {
// thrust::get<3>(pixel) = mn(center, p);
// nextId = id + step2;
// result = true;
// }
// thrust::get<1>(queue) = nextId;
//
// q = thrust::get<4>(pixel);
// p = thrust::get<8>(pixel);
// nextId = -3;
// if (q < center && q != p) {
// thrust::get<4>(pixel) = mn(center, p);
// nextId = id + step3;
// result = true;
// }
// thrust::get<2>(queue) = nextId;
//
// q = thrust::get<5>(pixel);
// p = thrust::get<9>(pixel);
// nextId = -4;
// if (q < center && q != p) {
// thrust::get<5>(pixel) = mn(center, p);
// nextId = id + step4;
// result = true;
// }
// thrust::get<3>(queue) = nextId;
//
//
// return result;
// }
//};
//
template<typename T>
struct Propagate
{
volatile T *marker;
volatile T *mask;
bool *flag;
const int step;
__host__ __device__
Propagate(T* _marker, T* _mask, bool* _flag, int _step) : marker(_marker), mask(_mask), flag(_flag), step(_step) {}
__host__ __device__
void updateNeighbor(int nId, T center, thrust::minimum<T> mn) {
T q = marker[nId];
T p = mask[nId];
if (q != p && q < center) {
marker[nId] = mn(center, p);
// flag[nId] = true;
}
}
__host__ __device__
void updateAndMarkNeighbor(int nId, T center, thrust::minimum<T> mn) {
T q = marker[nId];
T p = mask[nId];
if (q != p && q < center) {
marker[nId] = mn(center, p);
flag[nId] = true;
}
}
__host__ __device__
void operator()(int id)
{
thrust::minimum<T> mn;
T center = marker[id];
int nId;
nId = id - 1; updateNeighbor(nId, center, mn);
nId = id + 1; updateNeighbor(nId, center, mn);
nId = id - step - 1; updateNeighbor(nId, center, mn);
nId = id - step; updateNeighbor(nId, center, mn);
nId = id - step + 1; updateNeighbor(nId, center, mn);
nId = id + step - 1; updateNeighbor(nId, center, mn);
nId = id + step; updateNeighbor(nId, center, mn);
nId = id + step + 1; updateNeighbor(nId, center, mn);
nId = id - 2; updateAndMarkNeighbor(nId, center, mn);
nId = id + 2; updateAndMarkNeighbor(nId, center, mn);
nId = id - 2 * step - 2; updateAndMarkNeighbor(nId, center, mn);
nId = id - 2 * step - 1; updateAndMarkNeighbor(nId, center, mn);
nId = id - 2 * step; updateAndMarkNeighbor(nId, center, mn);
nId = id - 2 * step + 1; updateAndMarkNeighbor(nId, center, mn);
nId = id - 2 * step + 2; updateAndMarkNeighbor(nId, center, mn);
nId = id - step - 2; updateAndMarkNeighbor(nId, center, mn);
nId = id - step + 2; updateAndMarkNeighbor(nId, center, mn);
nId = id + step - 2; updateAndMarkNeighbor(nId, center, mn);
nId = id + step + 2; updateAndMarkNeighbor(nId, center, mn);
nId = id + 2 * step - 2; updateAndMarkNeighbor(nId, center, mn);
nId = id + 2 * step - 1; updateAndMarkNeighbor(nId, center, mn);
nId = id + 2 * step; updateAndMarkNeighbor(nId, center, mn);
nId = id + 2 * step + 1; updateAndMarkNeighbor(nId, center, mn);
nId = id + 2 * step + 2; updateAndMarkNeighbor(nId, center, mn);
}
};
// this functor returns true if the argument is odd, and false otherwise
template <typename T>
struct GreaterThanConst : public thrust::unary_function<T,bool>
{
const T k;
__host__ __device__
GreaterThanConst(T _k) : k(_k) {}
__host__ __device__
bool operator()(T x)
{
return x > k;
}
};
// connectivity: need to have border of 0 ,and should be continuous
template <typename T>
unsigned int imreconQueueIntCaller(T* __restrict__ marker, T* __restrict__ mask, const int sx, const int sy,
const int connectivity, cudaStream_t stream) {
// printf("entering imrecon int caller with conn=%d\n", connectivity);
// setup execution parameters
dim3 threadsx( XX_THREADS, XY_THREADS );
dim3 blocksx( (sy + threadsx.y - 1) / threadsx.y );
dim3 threadsy( MAX_THREADS );
dim3 blocksy( (sx + threadsy.x - 1) / threadsy.x );
// stability detection
// dopredny pruchod pres osu X
iRec1DForward_X_dilation <<< blocksx, threadsx, 0, stream >>> ( marker, mask, sx, sy);
// dopredny pruchod pres osu Y
if (connectivity == 4) {
// dopredny pruchod pres osu Y
iRec1DForward_Y_dilation <<< blocksy, threadsy, 0, stream >>> ( marker, mask, sx, sy);
} else {
iRec1DForward_Y_dilation_8<<< blocksy, threadsy, 0, stream >>> ( marker, mask, sx, sy);
}
// zpetny pruchod pres osu X
iRec1DBackward_X_dilation<<< blocksx, threadsx, 0, stream >>> ( marker, mask, sx, sy);
// dopredny pruchod pres osu Y
if (connectivity == 4) {
// dopredny pruchod pres osu Y
iRec1DBackward_Y_dilation <<< blocksy, threadsy, 0, stream >>> ( marker, mask, sx, sy);
} else {
// zpetny pruchod pres osu Y
iRec1DBackward_Y_dilation_8<<< blocksy, threadsy, 0, stream >>> ( marker, mask, sx, sy);
}
if (stream == 0) cudaDeviceSynchronize();
else cudaStreamSynchronize(stream);
// printf("%d sync \n", iter);
// set up some types to work with
thrust::device_ptr<T> p(mask + sx + 1);
thrust::device_ptr<T> p_ym1(mask + 1);
thrust::device_ptr<T> p_yp1(mask + 2 * sx + 1);
thrust::device_ptr<T> p_xm1(mask + sx);
thrust::device_ptr<T> p_xp1(mask + sx + 2);
// conn = 8
thrust::device_ptr<T> p_ym1xm1(mask);
thrust::device_ptr<T> p_ym1xp1(mask + 2);
thrust::device_ptr<T> p_yp1xm1(mask + 2 * sx);
thrust::device_ptr<T> p_yp1xp1(mask + 2 * sx + 2);
thrust::device_ptr<T> q(marker + sx + 1);
thrust::device_ptr<T> q_ym1(marker + 1);
thrust::device_ptr<T> q_yp1(marker + 2 * sx + 1);
thrust::device_ptr<T> q_xm1(marker + sx);
thrust::device_ptr<T> q_xp1(marker + sx + 2);
// conn = 8
thrust::device_ptr<T> q_ym1xm1(marker);
thrust::device_ptr<T> q_ym1xp1(marker + 2);
thrust::device_ptr<T> q_yp1xm1(marker + 2 * sx);
thrust::device_ptr<T> q_yp1xp1(marker + 2 * sx + 2);
int area = sx * (sy - 4) - 4; // actual image area - sx and sy are padded by 1 on each side,
typedef typename thrust::device_ptr<T> PixelIterator;
// typedef typename thrust::tuple<int, T, T, T, T, T> PixelNeighborhood;
// typedef typename thrust::tuple<thrust::counting_iterator<int>, PixelIterator, PixelIterator, PixelIterator, PixelIterator, PixelIterator> WindowedImage;
// typedef typename thrust::zip_iterator<WindowedImage> WindowedPixelIterator;
typedef typename thrust::tuple<signed int, T, T, T, T, T, T, T, T, T> ReconNeighborhood;
typedef typename thrust::tuple<signed int, T, T, T> ReconNeighborhood2;
typedef typename thrust::tuple<thrust::counting_iterator<int>, PixelIterator, PixelIterator, PixelIterator, PixelIterator, PixelIterator, PixelIterator, PixelIterator, PixelIterator, PixelIterator> ReconImage;
typedef typename thrust::zip_iterator<ReconImage> ReconPixelIterator;
typedef typename thrust::device_vector<int> Queue;
typedef typename Queue::iterator QueueIterator;
typedef typename thrust::tuple<int, int, int, int> QueueElement;
thrust::counting_iterator<int> ids(0);
// WindowedImage markerImg = thrust::make_tuple(ids, q_ym1xm1, q_ym1, q_ym1xp1, q_xm1, q, q_xp1, q_yp1xm1, q_yp1, q_yp1xp1);
// WindowedImage markerImgEnd = thrust::make_tuple(ids+area, q_ym1xm1+area, q_ym1+area, q_ym1xp1+area, q_xm1+area, q+area, q_xp1+area, q_yp1xm1+area, q_yp1+area, q_yp1xp1+area);
// WindowedImage maskImg = thrust::make_tuple(ids, p_ym1xm1, p_ym1, p_ym1xp1, p_xm1, p, p_xp1, p_yp1xm1, p_yp1, p_yp1xp1);
// ReconPixelIterator mask_last = thrust::make_zip_iterator(thrust::make_tuple(p_ym1xm1+area, p_ym1+area, p_ym1xp1+area, p_xm1+area, p+area, p_xp1+area, p_yp1xm1+area, p_yp1+area, p_yp1xp1+area));
ReconImage markermaskNp = thrust::make_tuple(ids, q, q_xp1, q_yp1xm1, q_yp1, q_yp1xp1, p_xp1, p_yp1xm1, p_yp1, p_yp1xp1);
ReconImage markermaskNpEnd = thrust::make_tuple(ids+area, q+area, q_xp1+area, q_yp1xm1+area, q_yp1+area, q_yp1xp1+area, p_xp1+area, p_yp1xm1+area, p_yp1+area, p_yp1xp1+area);
ReconPixelIterator image_first = thrust::make_zip_iterator(markermaskNp);
ReconPixelIterator image_last = thrust::make_zip_iterator(markermaskNpEnd);
// put the candidates into the queue
int queueSize = area;
Queue sparseQueue(queueSize, -1);
// can change into transform_iterator to use in the copy operation. the only challenge is don't know queue size, and would still need to compact later...
// mark
thrust::transform(image_first, image_last, sparseQueue.begin(), InitialImageToQueue<T, ReconNeighborhood>());
// select
queueSize = thrust::count_if(sparseQueue.begin(), sparseQueue.end(), GreaterThanConst<int>(-1));
Queue testQueue(area, -1);
// compact the queue
Queue denseQueue(queueSize, 0);
QueueIterator denseQueue_end = thrust::copy_if(sparseQueue.begin(), sparseQueue.end(), denseQueue.begin(), GreaterThanConst<int>(-1));
QueueIterator sparseQueue_end;
thrust::device_vector<bool> dummy(area, false);
printf("number of entries in sparseQueue: %d, denseQueue: %lu \n", queueSize, denseQueue_end - denseQueue.begin());
int iterations = 0;
int total = 0;
while (queueSize > 0 && iterations < 10000) {
++iterations;
total += queueSize;
// printf("here\n");
// allocate some memory
// sparseQueue.resize(queueSize * 8); // 8 neighbors
// thrust::fill(sparseQueue.begin(), sparseQueue.end(), -1);
// also set up as 8 devPtrs
// QueueIterator ym1xm1 = sparseQueue.begin();
// QueueIterator ym1 = ym1xm1+queueSize;
// QueueIterator ym1xp1 = ym1+queueSize;
// QueueIterator xm1 = ym1xp1+queueSize;
// QueueIterator xp1 = xm1+queueSize;
// QueueIterator yp1xm1 = xp1+queueSize;
// QueueIterator yp1 = yp1xm1+queueSize;
// QueueIterator yp1xp1 = yp1+queueSize;
// printf("here3\n");
// dummy.resize(queueSize);
// sort the queue by the value
sparseQueue_end = thrust::copy(denseQueue.begin(), denseQueue.end(), sparseQueue.begin());
thrust::stable_sort_by_key(thrust::make_permutation_iterator(q, sparseQueue.begin()),
thrust::make_permutation_iterator(q, sparseQueue_end),
denseQueue.begin());
thrust::fill(dummy.begin(), dummy.end(), false);
thrust::for_each(denseQueue.begin(), denseQueue.end(), Propagate<T>(thrust::raw_pointer_cast(q),
thrust::raw_pointer_cast(p), thrust::raw_pointer_cast(&*dummy.begin()), sx));
// does not work...
// thrust::transform(thrust::make_zip_iterator(thrust::make_tuple(
// thrust::make_permutation_iterator(ids, denseQueue.begin()),
// thrust::make_permutation_iterator(q, denseQueue.begin()),
// thrust::make_permutation_iterator(q_ym1, denseQueue.begin()),
// thrust::make_permutation_iterator(q_xm1, denseQueue.begin()),
// thrust::make_permutation_iterator(q_xp1, denseQueue.begin()),
// thrust::make_permutation_iterator(q_yp1, denseQueue.begin()),
// thrust::make_permutation_iterator(p_ym1, denseQueue.begin()),
// thrust::make_permutation_iterator(p_xm1, denseQueue.begin()),
// thrust::make_permutation_iterator(p_xp1, denseQueue.begin()),
// thrust::make_permutation_iterator(p_yp1, denseQueue.begin()))),
// thrust::make_zip_iterator(thrust::make_tuple(
// thrust::make_permutation_iterator(ids, denseQueue.end()),
// thrust::make_permutation_iterator(q, denseQueue.end()),
// thrust::make_permutation_iterator(q_ym1, denseQueue.end()),
// thrust::make_permutation_iterator(q_xm1, denseQueue.end()),
// thrust::make_permutation_iterator(q_xp1, denseQueue.end()),
// thrust::make_permutation_iterator(q_yp1, denseQueue.end()),
// thrust::make_permutation_iterator(p_ym1, denseQueue.end()),
// thrust::make_permutation_iterator(p_xm1, denseQueue.end()),
// thrust::make_permutation_iterator(p_xp1, denseQueue.end()),
// thrust::make_permutation_iterator(p_yp1, denseQueue.end()))),
// thrust::make_zip_iterator(thrust::make_tuple(ym1, xm1, xp1, yp1)),
// dummy.begin(),
// ReconPixel<T, ReconNeighborhood, QueueElement>(-sx, (int)-1, (int)1, sx));
// thrust::fill(testQueue.begin(), testQueue.end(), -1);
// thrust::transform(image_first, image_last, testQueue.begin(), InitialImageToQueue<T, ReconNeighborhood>());
// printf("test queue size : %d \n", thrust::count_if(testQueue.begin(), testQueue.end(), GreaterThanConst<int>(-1)));
// does not work...
// // 8conn
// thrust::transform(thrust::make_zip_iterator(thrust::make_tuple(
// thrust::make_permutation_iterator(ids, denseQueue.begin()),
// thrust::make_permutation_iterator(q, denseQueue.begin()),
// thrust::make_permutation_iterator(q_ym1xm1, denseQueue.begin()),
// thrust::make_permutation_iterator(q_ym1xp1, denseQueue.begin()),
// thrust::make_permutation_iterator(q_yp1xm1, denseQueue.begin()),
// thrust::make_permutation_iterator(q_yp1xp1, denseQueue.begin()),
// thrust::make_permutation_iterator(p_ym1xm1, denseQueue.begin()),
// thrust::make_permutation_iterator(p_ym1xp1, denseQueue.begin()),
// thrust::make_permutation_iterator(p_yp1xm1, denseQueue.begin()),
// thrust::make_permutation_iterator(p_yp1xp1, denseQueue.begin()))),
// thrust::make_zip_iterator(thrust::make_tuple(
// thrust::make_permutation_iterator(ids, denseQueue.end()),
// thrust::make_permutation_iterator(q, denseQueue.end()),
// thrust::make_permutation_iterator(q_ym1xm1, denseQueue.end()),
// thrust::make_permutation_iterator(q_ym1xp1, denseQueue.end()),
// thrust::make_permutation_iterator(q_yp1xm1, denseQueue.end()),
// thrust::make_permutation_iterator(q_yp1xp1, denseQueue.end()),
// thrust::make_permutation_iterator(p_ym1xm1, denseQueue.end()),
// thrust::make_permutation_iterator(p_ym1xp1, denseQueue.end()),
// thrust::make_permutation_iterator(p_yp1xm1, denseQueue.end()),
// thrust::make_permutation_iterator(p_yp1xp1, denseQueue.end()))),
// thrust::make_zip_iterator(thrust::make_tuple(ym1xm1, ym1xp1, yp1xm1, yp1xp1)),
// dummy.begin(),
// ReconPixel<T, ReconNeighborhood, QueueElement>(-sx-1, -sx+1, sx-1, sx+1)); //
// thrust::fill(testQueue.begin(), testQueue.end(), -1);
// thrust::transform(image_first, image_last, testQueue.begin(), InitialImageToQueue<T, ReconNeighborhood>());
// queueSize = thrust::count_if(testQueue.begin(), testQueue.end(), GreaterThanConst<int>(-1));
// printf("test queue size : %d \n", queueSize);
// and prepare the queue for the next iterations.
//sparseQueue_end = thrust::unique(sparseQueue.begin(), sparseQueue.end());
queueSize = thrust::count_if(dummy.begin(), dummy.end(), thrust::identity<bool>());
// printf("here 7 : queueSize =%d \n", queueSize);
denseQueue.resize(queueSize);
thrust::fill(denseQueue.begin(), denseQueue.end(), -1);
denseQueue_end = thrust::copy_if(ids, ids+area, dummy.begin(), denseQueue.begin(), thrust::identity<bool>());
printf("number of entries in queue: %lu \n", denseQueue_end - denseQueue.begin());
}
if (stream == 0) cudaDeviceSynchronize();
else cudaStreamSynchronize(stream);
cudaGetLastError();
printf("iterations: %d, total: %d\n", iterations, total);
return total;
}
template unsigned int imreconQueueIntCaller<unsigned char>(unsigned char*, unsigned char*, const int, const int,
const int, cudaStream_t );
}} | #include <hip/hip_runtime.h>
/*
* kernel codes for the reconstruction by dilation (reconstruction_by_dilation_kernel)
*/
namespace nscale { namespace gpu {
template <typename T>
unsigned int imreconQueueIntCaller(T* g_marker, T* g_mask, const int sx, const int sy,
const int connectivity, hipStream_t stream );
}} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
* kernel codes for the reconstruction by dilation (reconstruction_by_dilation_kernel)
*/
namespace nscale { namespace gpu {
template <typename T>
unsigned int imreconQueueIntCaller(T* g_marker, T* g_mask, const int sx, const int sy,
const int connectivity, hipStream_t stream );
}} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* kernel codes for the reconstruction by dilation (reconstruction_by_dilation_kernel)
*/
namespace nscale { namespace gpu {
template <typename T>
unsigned int imreconQueueIntCaller(T* g_marker, T* g_mask, const int sx, const int sy,
const int connectivity, hipStream_t stream );
}} | .text
.file "imrecon_queue_int_kernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void UniformNormalDistribution(float *from, float *to, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
float tmp;
if (id < size)
{
tmp = normcdf(from[id] * sqrt((float)size));
to[id] = (tmp -0.5)*2;
}
} | code for sm_80
Function : _Z25UniformNormalDistributionPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F R2, c[0x0][0x170] ; /* 0x00005c0000027b06 */
/* 0x000e220000201400 */
/*0090*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0209 */
/*00c0*/ IADD3 R3, R2, -0xd000000, RZ ; /* 0xf300000002037810 */
/* 0x001fe20007ffe0ff */
/*00d0*/ MUFU.RSQ R5, R2 ; /* 0x0000000200057308 */
/* 0x0000660000001400 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x727fffff, PT ; /* 0x727fffff0300780c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fd60000011400 */
/*0100*/ @!P0 BRA 0x140 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0110*/ MOV R6, 0x130 ; /* 0x0000013000067802 */
/* 0x003fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0x5f0 ; /* 0x000004c000007944 */
/* 0x000fea0003c00000 */
/*0130*/ BRA 0x180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0140*/ FMUL.FTZ R7, R2, R5 ; /* 0x0000000502077220 */
/* 0x003fe40000410000 */
/*0150*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0160*/ FFMA R2, -R7, R7, R2 ; /* 0x0000000707027223 */
/* 0x000fc80000000102 */
/*0170*/ FFMA R2, R2, R5, R7 ; /* 0x0000000502027223 */
/* 0x000fe40000000007 */
/*0180*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0190*/ HFMA2.MMA R12, -RZ, RZ, 0.80126953125, -0.00891876220703125 ; /* 0x3a69a091ff0c7435 */
/* 0x000fe200000001ff */
/*01a0*/ FMUL R2, R9, R2 ; /* 0x0000000209027220 */
/* 0x004fca0000400000 */
/*01b0*/ FSETP.GT.AND P0, PT, |R2|.reuse, 14.5, PT ; /* 0x416800000200780b */
/* 0x040fe40003f04200 */
/*01c0*/ LOP3.LUT R4, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002047812 */
/* 0x000fd600078ec0ff */
/*01d0*/ @P0 LOP3.LUT R2, R4, 0x41680000, RZ, 0xfc, !PT ; /* 0x4168000004020812 */
/* 0x000fc800078efcff */
/*01e0*/ FSETP.GEU.AND P2, PT, R2.reuse, -1, PT ; /* 0xbf8000000200780b */
/* 0x040fe20003f4e000 */
/*01f0*/ FMUL R5, R2, -0.70710676908493041992 ; /* 0xbf3504f302057820 */
/* 0x000fc80000400000 */
/*0200*/ FFMA R7, R2, -0.70710676908493041992, -R5 ; /* 0xbf3504f302077823 */
/* 0x000fc80000000805 */
/*0210*/ FFMA R6, R2, -1.2101617485882343317e-08, R7 ; /* 0xb24fe77a02067823 */
/* 0x000fc80000000007 */
/*0220*/ FADD R4, R5, R6 ; /* 0x0000000605047221 */
/* 0x000fc80000000000 */
/*0230*/ FADD R10, |R4|.reuse, 4 ; /* 0x40800000040a7421 */
/* 0x040fe20000000200 */
/*0240*/ FSETP.GEU.AND P1, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720b */
/* 0x040fe20003f2e000 */
/*0250*/ FADD R7, |R4|, -4 ; /* 0xc080000004077421 */
/* 0x000fe40000000200 */
/*0260*/ @!P2 FADD R5, R5, -R4 ; /* 0x800000040505a221 */
/* 0x000fe40000000000 */
/*0270*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x000e240000001000 */
/*0280*/ @!P2 FADD R6, R6, R5 ; /* 0x000000050606a221 */
/* 0x000fe40000000000 */
/*0290*/ FMUL R9, R7, R10 ; /* 0x0000000a07097220 */
/* 0x001fc40000400000 */
/*02a0*/ FMUL R7, R4, R4 ; /* 0x0000000404077220 */
/* 0x000fe40000400000 */
/*02b0*/ FADD R11, R9, 1 ; /* 0x3f800000090b7421 */
/* 0x000fe40000000000 */
/*02c0*/ FMUL R8, R7, -1.4426950216293334961 ; /* 0xbfb8aa3b07087820 */
/* 0x000fe40000400000 */
/*02d0*/ FFMA R11, R11, -4, |R4| ; /* 0xc08000000b0b7823 */
/* 0x000fc80000000404 */
/*02e0*/ FRND.TRUNC R8, R8 ; /* 0x0000000800087307 */
/* 0x000e22000020d000 */
/*02f0*/ FFMA R11, |R4|, -R9, R11 ; /* 0x80000009040b7223 */
/* 0x000fc8000000020b */
/*0300*/ FFMA R11, R10, R11, R9 ; /* 0x0000000b0a0b7223 */
/* 0x000fe20000000009 */
/*0310*/ MOV R9, 0x40000000 ; /* 0x4000000000097802 */
/* 0x000fc60000000f00 */
/*0320*/ FFMA R10, R11.reuse, R12, 0.0070457882247865200043 ; /* 0x3be6e05b0b0a7423 */
/* 0x040fe4000000000c */
/*0330*/ FFMA R9, |R4|, R9, 1 ; /* 0x3f80000004097423 */
/* 0x000fe40000000209 */
/*0340*/ FFMA R10, R11, R10, -0.015866896137595176697 ; /* 0xbc81fb4b0b0a7423 */
/* 0x000fe2000000000a */
/*0350*/ FSETP.GT.AND P0, PT, |R8|, 126, PT ; /* 0x42fc00000800780b */
/* 0x001fc60003f04200 */
/*0360*/ FFMA R10, R11, R10, 0.036429625004529953003 ; /* 0x3d15373b0b0a7423 */
/* 0x000fe2000000000a */
/*0370*/ LOP3.LUT R12, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000080c7812 */
/* 0x000fc600078ec0ff */
/*0380*/ FFMA R10, R11, R10, -0.066643431782722473145 ; /* 0xbd887c5a0b0a7423 */
/* 0x000fc8000000000a */
/*0390*/ FFMA R10, R11.reuse, R10, 0.093814529478549957275 ; /* 0x3dc021d50b0a7423 */
/* 0x040fe4000000000a */
/*03a0*/ @P0 LOP3.LUT R8, R12, 0x42fc0000, RZ, 0xfc, !PT ; /* 0x42fc00000c080812 */
/* 0x000fe400078efcff */
/*03b0*/ FFMA R10, R11.reuse, R10, -0.10099056363105773926 ; /* 0xbdced4240b0a7423 */
/* 0x040fe2000000000a */
/*03c0*/ MUFU.RCP R12, R9 ; /* 0x00000009000c7308 */
/* 0x000e220000001000 */
/*03d0*/ FSETP.GT.AND P0, PT, |R4|, 10.05500030517578125, PT ; /* 0x4120e1480400780b */
/* 0x000fe20003f04200 */
/*03e0*/ FFMA R13, R8.reuse, -0.69314718246459960938, -R7 ; /* 0xbf317218080d7823 */
/* 0x040fe40000000807 */
/*03f0*/ FFMA R10, R11, R10, 0.06809400022029876709 ; /* 0x3d8b74de0b0a7423 */
/* 0x000fe4000000000a */
/*0400*/ FFMA R13, R8, 1.9046542121259335545e-09, R13 ; /* 0x3102e308080d7823 */
/* 0x000fc4000000000d */
/*0410*/ FFMA R10, R11, R10, 0.015377387404441833496 ; /* 0x3c7bf1700b0a7423 */
/* 0x000fe4000000000a */
/*0420*/ FMUL R14, R13, 1.4426950216293334961 ; /* 0x3fb8aa3b0d0e7820 */
/* 0x000fe40000400000 */
/*0430*/ FFMA R10, R11.reuse, R10, -0.1396210789680480957 ; /* 0xbe0ef8d40b0a7423 */
/* 0x040fe4000000000a */
/*0440*/ MUFU.EX2 R15, R14 ; /* 0x0000000e000f7308 */
/* 0x000e620000000800 */
/*0450*/ FFMA R7, -|R4|, |R4|, R7 ; /* 0x4000000404077223 */
/* 0x000fe40000000307 */
/*0460*/ FFMA R11, R11, R10, 1.232995152473449707 ; /* 0x3f9dd2c90b0b7423 */
/* 0x000fe4000000000a */
/*0470*/ FADD R10, R8, 12583039 ; /* 0x4b40007f080a7421 */
/* 0x000fc40000000000 */
/*0480*/ FMUL R13, R11, R12 ; /* 0x0000000c0b0d7220 */
/* 0x001fc60000400000 */
/*0490*/ SHF.L.U32 R10, R10, 0x17, RZ ; /* 0x000000170a0a7819 */
/* 0x000fe200000006ff */
/*04a0*/ FMUL R8, R13, -2 ; /* 0xc00000000d087820 */
/* 0x000fc80000400000 */
/*04b0*/ FFMA R8, |R4|, R8, R11 ; /* 0x0000000804087223 */
/* 0x000fe4000000020b */
/*04c0*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x002fe40000400000 */
/*04d0*/ FADD R8, -R13, R8 ; /* 0x000000080d087221 */
/* 0x000fe40000000100 */
/*04e0*/ FFMA R7, R10, R7, R10 ; /* 0x000000070a077223 */
/* 0x000fe4000000000a */
/*04f0*/ FFMA R8, R12, R8, R13 ; /* 0x000000080c087223 */
/* 0x000fe4000000000d */
/*0500*/ @!P2 FMUL R4, R4, -2 ; /* 0xc00000000404a820 */
/* 0x000fc40000400000 */
/*0510*/ FMUL R7, R8, R7 ; /* 0x0000000708077220 */
/* 0x000fca0000400000 */
/*0520*/ FSEL R7, R7, RZ, !P0 ; /* 0x000000ff07077208 */
/* 0x000fe40004000000 */
/*0530*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc600078010ff */
/*0540*/ @!P1 FADD R7, -R7, 2 ; /* 0x4000000007079421 */
/* 0x000fe20000000100 */
/*0550*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fc600000f1403 */
/*0560*/ @!P2 FMUL R4, R7, R4 ; /* 0x000000040704a220 */
/* 0x000fc80000400000 */
/*0570*/ @!P2 FFMA R7, R6, R4, R7 ; /* 0x000000040607a223 */
/* 0x000fc80000000007 */
/*0580*/ FMUL R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fc80000400000 */
/*0590*/ F2F.F64.F32 R4, R7 ; /* 0x0000000700047310 */
/* 0x000e240000201800 */
/*05a0*/ DADD R4, R4, -0.5 ; /* 0xbfe0000004047429 */
/* 0x001e0c0000000000 */
/*05b0*/ DADD R4, R4, R4 ; /* 0x0000000004047229 */
/* 0x001e140000000004 */
/*05c0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*05d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ LOP3.LUT P0, RZ, R2, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff02ff7812 */
/* 0x000fda000780c0ff */
/*0600*/ @!P0 MOV R4, R2 ; /* 0x0000000200048202 */
/* 0x000fe20000000f00 */
/*0610*/ @!P0 BRA 0x730 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0620*/ FSETP.GEU.FTZ.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f1e000 */
/*0630*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*0640*/ @!P0 BRA 0x730 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0650*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*0660*/ @P0 FADD.FTZ R4, R2, 1 ; /* 0x3f80000002040421 */
/* 0x000fe20000010000 */
/*0670*/ @P0 BRA 0x730 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0680*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*0690*/ @!P0 MOV R4, R2 ; /* 0x0000000200048202 */
/* 0x000fe20000000f00 */
/*06a0*/ @!P0 BRA 0x730 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*06b0*/ FFMA R2, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002027823 */
/* 0x000fc800000000ff */
/*06c0*/ MUFU.RSQ R5, R2 ; /* 0x0000000200057308 */
/* 0x000e240000001400 */
/*06d0*/ FMUL.FTZ R7, R2, R5 ; /* 0x0000000502077220 */
/* 0x001fe40000410000 */
/*06e0*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*06f0*/ FADD.FTZ R4, -R7, -RZ ; /* 0x800000ff07047221 */
/* 0x000fc80000010100 */
/*0700*/ FFMA R4, R7, R4, R2 ; /* 0x0000000407047223 */
/* 0x000fc80000000002 */
/*0710*/ FFMA R4, R4, R5, R7 ; /* 0x0000000504047223 */
/* 0x000fc80000000007 */
/*0720*/ FMUL.FTZ R4, R4, 2.3283064365386962891e-10 ; /* 0x2f80000004047820 */
/* 0x000fc80000410000 */
/*0730*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0740*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fe40000000f00 */
/*0750*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fc80000000f00 */
/*0760*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff89004007950 */
/* 0x000fea0003c3ffff */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void UniformNormalDistribution(float *from, float *to, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
float tmp;
if (id < size)
{
tmp = normcdf(from[id] * sqrt((float)size));
to[id] = (tmp -0.5)*2;
}
} | .file "tmpxft_0005cf56_00000000-6_UniformNormalDistribution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i
.type _Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i, @function
_Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25UniformNormalDistributionPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i, .-_Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i
.globl _Z25UniformNormalDistributionPfS_i
.type _Z25UniformNormalDistributionPfS_i, @function
_Z25UniformNormalDistributionPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25UniformNormalDistributionPfS_i, .-_Z25UniformNormalDistributionPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25UniformNormalDistributionPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25UniformNormalDistributionPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void UniformNormalDistribution(float *from, float *to, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
float tmp;
if (id < size)
{
tmp = normcdf(from[id] * sqrt((float)size));
to[id] = (tmp -0.5)*2;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UniformNormalDistribution(float *from, float *to, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
float tmp;
if (id < size)
{
tmp = normcdf(from[id] * sqrt((float)size));
to[id] = (tmp -0.5)*2;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UniformNormalDistribution(float *from, float *to, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
float tmp;
if (id < size)
{
tmp = normcdf(from[id] * sqrt((float)size));
to[id] = (tmp -0.5)*2;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25UniformNormalDistributionPfS_i
.globl _Z25UniformNormalDistributionPfS_i
.p2align 8
.type _Z25UniformNormalDistributionPfS_i,@function
_Z25UniformNormalDistributionPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s5, 0xbe41f39d
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x40434d4e
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s4
s_brev_b32 s4, 1
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v4, v3
v_fma_f32 v8, -v6, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v4, v4, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v4, v4, v6, s0
s_mov_b32 s0, 0xdce2b7d6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x37800000, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[2:3], v4
v_and_or_b32 v4, v4, s4, 0x40434d4e
s_mov_b32 s4, 0x54df3c0e
v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, s[0:1]
s_mov_b32 s1, 0xbfe6a09e
s_mov_b32 s0, 0x667f3bcd
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, 0xdce2b7d6, vcc_lo
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[6:7], v[2:3], s[0:1], -v[4:5]
s_mov_b32 s1, 0x3c8bdd34
s_mov_b32 s0, 0x13b26456
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[2:3], s[0:1], v[6:7]
s_mov_b32 s1, 0xbe411663
s_mov_b32 s0, 0x37cfa789
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[4:5], v[6:7]
v_add_f64 v[10:11], |v[8:9]|, 4.0
v_add_f64 v[22:23], |v[8:9]|, |v[8:9]|
v_add_f64 v[4:5], v[8:9], -v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[12:13], v[10:11]
v_add_f64 v[24:25], v[22:23], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[26:27], v[24:25]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[14:15], v[12:13], v[12:13]
v_add_f64 v[14:15], |v[8:9]|, -4.0
v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[12:13], 1.0
v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[12:13]
v_fma_f64 v[24:25], -v[24:25], v[26:27], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_fma_f64 v[24:25], v[24:25], v[26:27], v[26:27]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[12:13], 1.0
v_fma_f64 v[14:15], v[14:15], -4.0, |v[8:9]|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[12:13], |v[8:9]|, v[14:15]
v_fma_f64 v[10:11], v[10:11], v[14:15], v[12:13]
v_mul_f64 v[14:15], v[8:9], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[10:11], s[4:5], s[0:1]
s_mov_b32 s1, 0x3e7b45f1
s_mov_b32 s0, 0xd9802b82
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[14:15]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3e6d9048
s_mov_b32 s0, 0x8a03dcdb
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0xbeab87b0
s_mov_b32 s0, 0x2eba62d8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3e95104b
s_mov_b32 s0, 0xa56e15f1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3ed7f29f
s_mov_b32 s0, 0x71c907de
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0xbee78f5c
s_mov_b32 s0, 0x2cd770fb
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_f64 v[16:17], v[14:15], s[0:1]
s_mov_b32 s1, 0xbef995fb
s_mov_b32 s0, 0x76d0a51a
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3f23be2e
s_mov_b32 s0, 0xc022d0ed
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rndne_f64_e32 v[16:17], v[16:17]
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], s[0:1], v[14:15]
s_mov_b32 s1, 0xbf2a1deb
s_mov_b32 s0, 0x2fdbf62e
v_cvt_i32_f64_e32 v26, v[16:17]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], s[0:1], v[18:19]
s_mov_b32 s1, 0xbf48d4ac
s_mov_b32 s0, 0x3689fc43
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], s[4:5], s[0:1]
s_mov_b32 s1, 0x3f749c67
s_mov_b32 s0, 0x192d909b
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0xbf909623
s_mov_b32 s0, 0x852ff070
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0x3fa3079e
s_mov_b32 s0, 0xdfadea8f
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0xbfb0fb06
s_mov_b32 s0, 0xdff65910
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0x3fb7fee0
s_mov_b32 s0, 0x4de8f32
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0xbfb9ddb2
s_mov_b32 s0, 0x3c3dbeb3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0x3fb16ece
s_mov_b32 s0, 0xfcfa6930
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0x3f8f7f5d
s_mov_b32 s0, 0xf66fb8a3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0xbfc1df1a
s_mov_b32 s0, 0xd154a2a8
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3fcdd2c8
s_mov_b32 s0, 0xb74febf8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[14:15]
s_mov_b32 s1, 0x403b39dc
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[18:19], v[20:21], 1.0
v_fma_f64 v[16:17], v[10:11], v[24:25], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[12:13], v[12:13], v26
v_fma_f64 v[18:19], -v[16:17], v[22:23], 1.0
v_add_f64 v[10:11], v[10:11], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v20, 0x7ff00000, v13, vcc_lo
v_fma_f64 v[13:14], -v[8:9], v[8:9], -v[14:15]
s_and_b32 vcc_lo, s0, vcc_lo
v_add_f64 v[10:11], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v19, 0, v20, s0
v_cndmask_b32_e32 v18, 0, v12, vcc_lo
s_mov_b32 s0, 0x41e48bfc
v_cmp_ngt_f64_e64 vcc_lo, |v[8:9]|, s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[18:19], v[13:14], v[18:19]
v_mul_f64 v[14:15], v[8:9], -2.0
v_fma_f64 v[10:11], v[24:25], v[10:11], v[16:17]
v_mul_f64 v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
v_add_f64 v[12:13], -v[10:11], 2.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v9, v11, v13 :: v_dual_cndmask_b32 v8, v10, v12
v_cmp_nle_f64_e32 vcc_lo, -1.0, v[2:3]
v_add_f64 v[2:3], v[6:7], -v[4:5]
v_mul_f64 v[10:11], v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v5, 0, v11 :: v_dual_cndmask_b32 v4, 0, v10
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_fma_f64 v[2:3], v[2:3], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], 0.5
v_cvt_f32_f64_e32 v2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
v_add_f64 v[2:3], v[2:3], -0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[2:3]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25UniformNormalDistributionPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25UniformNormalDistributionPfS_i, .Lfunc_end0-_Z25UniformNormalDistributionPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25UniformNormalDistributionPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25UniformNormalDistributionPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void UniformNormalDistribution(float *from, float *to, int size)
{
int id = blockDim.x * blockIdx.y * gridDim.x
+ blockDim.x * blockIdx.x
+ threadIdx.x;
float tmp;
if (id < size)
{
tmp = normcdf(from[id] * sqrt((float)size));
to[id] = (tmp -0.5)*2;
}
} | .text
.file "UniformNormalDistribution.hip"
.globl _Z40__device_stub__UniformNormalDistributionPfS_i # -- Begin function _Z40__device_stub__UniformNormalDistributionPfS_i
.p2align 4, 0x90
.type _Z40__device_stub__UniformNormalDistributionPfS_i,@function
_Z40__device_stub__UniformNormalDistributionPfS_i: # @_Z40__device_stub__UniformNormalDistributionPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25UniformNormalDistributionPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z40__device_stub__UniformNormalDistributionPfS_i, .Lfunc_end0-_Z40__device_stub__UniformNormalDistributionPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25UniformNormalDistributionPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25UniformNormalDistributionPfS_i,@object # @_Z25UniformNormalDistributionPfS_i
.section .rodata,"a",@progbits
.globl _Z25UniformNormalDistributionPfS_i
.p2align 3, 0x0
_Z25UniformNormalDistributionPfS_i:
.quad _Z40__device_stub__UniformNormalDistributionPfS_i
.size _Z25UniformNormalDistributionPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25UniformNormalDistributionPfS_i"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__UniformNormalDistributionPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25UniformNormalDistributionPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25UniformNormalDistributionPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F R2, c[0x0][0x170] ; /* 0x00005c0000027b06 */
/* 0x000e220000201400 */
/*0090*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00b0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0209 */
/*00c0*/ IADD3 R3, R2, -0xd000000, RZ ; /* 0xf300000002037810 */
/* 0x001fe20007ffe0ff */
/*00d0*/ MUFU.RSQ R5, R2 ; /* 0x0000000200057308 */
/* 0x0000660000001400 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R3, 0x727fffff, PT ; /* 0x727fffff0300780c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fd60000011400 */
/*0100*/ @!P0 BRA 0x140 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0110*/ MOV R6, 0x130 ; /* 0x0000013000067802 */
/* 0x003fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0x5f0 ; /* 0x000004c000007944 */
/* 0x000fea0003c00000 */
/*0130*/ BRA 0x180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0140*/ FMUL.FTZ R7, R2, R5 ; /* 0x0000000502077220 */
/* 0x003fe40000410000 */
/*0150*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0160*/ FFMA R2, -R7, R7, R2 ; /* 0x0000000707027223 */
/* 0x000fc80000000102 */
/*0170*/ FFMA R2, R2, R5, R7 ; /* 0x0000000502027223 */
/* 0x000fe40000000007 */
/*0180*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0190*/ HFMA2.MMA R12, -RZ, RZ, 0.80126953125, -0.00891876220703125 ; /* 0x3a69a091ff0c7435 */
/* 0x000fe200000001ff */
/*01a0*/ FMUL R2, R9, R2 ; /* 0x0000000209027220 */
/* 0x004fca0000400000 */
/*01b0*/ FSETP.GT.AND P0, PT, |R2|.reuse, 14.5, PT ; /* 0x416800000200780b */
/* 0x040fe40003f04200 */
/*01c0*/ LOP3.LUT R4, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002047812 */
/* 0x000fd600078ec0ff */
/*01d0*/ @P0 LOP3.LUT R2, R4, 0x41680000, RZ, 0xfc, !PT ; /* 0x4168000004020812 */
/* 0x000fc800078efcff */
/*01e0*/ FSETP.GEU.AND P2, PT, R2.reuse, -1, PT ; /* 0xbf8000000200780b */
/* 0x040fe20003f4e000 */
/*01f0*/ FMUL R5, R2, -0.70710676908493041992 ; /* 0xbf3504f302057820 */
/* 0x000fc80000400000 */
/*0200*/ FFMA R7, R2, -0.70710676908493041992, -R5 ; /* 0xbf3504f302077823 */
/* 0x000fc80000000805 */
/*0210*/ FFMA R6, R2, -1.2101617485882343317e-08, R7 ; /* 0xb24fe77a02067823 */
/* 0x000fc80000000007 */
/*0220*/ FADD R4, R5, R6 ; /* 0x0000000605047221 */
/* 0x000fc80000000000 */
/*0230*/ FADD R10, |R4|.reuse, 4 ; /* 0x40800000040a7421 */
/* 0x040fe20000000200 */
/*0240*/ FSETP.GEU.AND P1, PT, R4.reuse, RZ, PT ; /* 0x000000ff0400720b */
/* 0x040fe20003f2e000 */
/*0250*/ FADD R7, |R4|, -4 ; /* 0xc080000004077421 */
/* 0x000fe40000000200 */
/*0260*/ @!P2 FADD R5, R5, -R4 ; /* 0x800000040505a221 */
/* 0x000fe40000000000 */
/*0270*/ MUFU.RCP R10, R10 ; /* 0x0000000a000a7308 */
/* 0x000e240000001000 */
/*0280*/ @!P2 FADD R6, R6, R5 ; /* 0x000000050606a221 */
/* 0x000fe40000000000 */
/*0290*/ FMUL R9, R7, R10 ; /* 0x0000000a07097220 */
/* 0x001fc40000400000 */
/*02a0*/ FMUL R7, R4, R4 ; /* 0x0000000404077220 */
/* 0x000fe40000400000 */
/*02b0*/ FADD R11, R9, 1 ; /* 0x3f800000090b7421 */
/* 0x000fe40000000000 */
/*02c0*/ FMUL R8, R7, -1.4426950216293334961 ; /* 0xbfb8aa3b07087820 */
/* 0x000fe40000400000 */
/*02d0*/ FFMA R11, R11, -4, |R4| ; /* 0xc08000000b0b7823 */
/* 0x000fc80000000404 */
/*02e0*/ FRND.TRUNC R8, R8 ; /* 0x0000000800087307 */
/* 0x000e22000020d000 */
/*02f0*/ FFMA R11, |R4|, -R9, R11 ; /* 0x80000009040b7223 */
/* 0x000fc8000000020b */
/*0300*/ FFMA R11, R10, R11, R9 ; /* 0x0000000b0a0b7223 */
/* 0x000fe20000000009 */
/*0310*/ MOV R9, 0x40000000 ; /* 0x4000000000097802 */
/* 0x000fc60000000f00 */
/*0320*/ FFMA R10, R11.reuse, R12, 0.0070457882247865200043 ; /* 0x3be6e05b0b0a7423 */
/* 0x040fe4000000000c */
/*0330*/ FFMA R9, |R4|, R9, 1 ; /* 0x3f80000004097423 */
/* 0x000fe40000000209 */
/*0340*/ FFMA R10, R11, R10, -0.015866896137595176697 ; /* 0xbc81fb4b0b0a7423 */
/* 0x000fe2000000000a */
/*0350*/ FSETP.GT.AND P0, PT, |R8|, 126, PT ; /* 0x42fc00000800780b */
/* 0x001fc60003f04200 */
/*0360*/ FFMA R10, R11, R10, 0.036429625004529953003 ; /* 0x3d15373b0b0a7423 */
/* 0x000fe2000000000a */
/*0370*/ LOP3.LUT R12, R8, 0x80000000, RZ, 0xc0, !PT ; /* 0x80000000080c7812 */
/* 0x000fc600078ec0ff */
/*0380*/ FFMA R10, R11, R10, -0.066643431782722473145 ; /* 0xbd887c5a0b0a7423 */
/* 0x000fc8000000000a */
/*0390*/ FFMA R10, R11.reuse, R10, 0.093814529478549957275 ; /* 0x3dc021d50b0a7423 */
/* 0x040fe4000000000a */
/*03a0*/ @P0 LOP3.LUT R8, R12, 0x42fc0000, RZ, 0xfc, !PT ; /* 0x42fc00000c080812 */
/* 0x000fe400078efcff */
/*03b0*/ FFMA R10, R11.reuse, R10, -0.10099056363105773926 ; /* 0xbdced4240b0a7423 */
/* 0x040fe2000000000a */
/*03c0*/ MUFU.RCP R12, R9 ; /* 0x00000009000c7308 */
/* 0x000e220000001000 */
/*03d0*/ FSETP.GT.AND P0, PT, |R4|, 10.05500030517578125, PT ; /* 0x4120e1480400780b */
/* 0x000fe20003f04200 */
/*03e0*/ FFMA R13, R8.reuse, -0.69314718246459960938, -R7 ; /* 0xbf317218080d7823 */
/* 0x040fe40000000807 */
/*03f0*/ FFMA R10, R11, R10, 0.06809400022029876709 ; /* 0x3d8b74de0b0a7423 */
/* 0x000fe4000000000a */
/*0400*/ FFMA R13, R8, 1.9046542121259335545e-09, R13 ; /* 0x3102e308080d7823 */
/* 0x000fc4000000000d */
/*0410*/ FFMA R10, R11, R10, 0.015377387404441833496 ; /* 0x3c7bf1700b0a7423 */
/* 0x000fe4000000000a */
/*0420*/ FMUL R14, R13, 1.4426950216293334961 ; /* 0x3fb8aa3b0d0e7820 */
/* 0x000fe40000400000 */
/*0430*/ FFMA R10, R11.reuse, R10, -0.1396210789680480957 ; /* 0xbe0ef8d40b0a7423 */
/* 0x040fe4000000000a */
/*0440*/ MUFU.EX2 R15, R14 ; /* 0x0000000e000f7308 */
/* 0x000e620000000800 */
/*0450*/ FFMA R7, -|R4|, |R4|, R7 ; /* 0x4000000404077223 */
/* 0x000fe40000000307 */
/*0460*/ FFMA R11, R11, R10, 1.232995152473449707 ; /* 0x3f9dd2c90b0b7423 */
/* 0x000fe4000000000a */
/*0470*/ FADD R10, R8, 12583039 ; /* 0x4b40007f080a7421 */
/* 0x000fc40000000000 */
/*0480*/ FMUL R13, R11, R12 ; /* 0x0000000c0b0d7220 */
/* 0x001fc60000400000 */
/*0490*/ SHF.L.U32 R10, R10, 0x17, RZ ; /* 0x000000170a0a7819 */
/* 0x000fe200000006ff */
/*04a0*/ FMUL R8, R13, -2 ; /* 0xc00000000d087820 */
/* 0x000fc80000400000 */
/*04b0*/ FFMA R8, |R4|, R8, R11 ; /* 0x0000000804087223 */
/* 0x000fe4000000020b */
/*04c0*/ FMUL R10, R10, R15 ; /* 0x0000000f0a0a7220 */
/* 0x002fe40000400000 */
/*04d0*/ FADD R8, -R13, R8 ; /* 0x000000080d087221 */
/* 0x000fe40000000100 */
/*04e0*/ FFMA R7, R10, R7, R10 ; /* 0x000000070a077223 */
/* 0x000fe4000000000a */
/*04f0*/ FFMA R8, R12, R8, R13 ; /* 0x000000080c087223 */
/* 0x000fe4000000000d */
/*0500*/ @!P2 FMUL R4, R4, -2 ; /* 0xc00000000404a820 */
/* 0x000fc40000400000 */
/*0510*/ FMUL R7, R8, R7 ; /* 0x0000000708077220 */
/* 0x000fca0000400000 */
/*0520*/ FSEL R7, R7, RZ, !P0 ; /* 0x000000ff07077208 */
/* 0x000fe40004000000 */
/*0530*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc600078010ff */
/*0540*/ @!P1 FADD R7, -R7, 2 ; /* 0x4000000007079421 */
/* 0x000fe20000000100 */
/*0550*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fc600000f1403 */
/*0560*/ @!P2 FMUL R4, R7, R4 ; /* 0x000000040704a220 */
/* 0x000fc80000400000 */
/*0570*/ @!P2 FFMA R7, R6, R4, R7 ; /* 0x000000040607a223 */
/* 0x000fc80000000007 */
/*0580*/ FMUL R7, R7, 0.5 ; /* 0x3f00000007077820 */
/* 0x000fc80000400000 */
/*0590*/ F2F.F64.F32 R4, R7 ; /* 0x0000000700047310 */
/* 0x000e240000201800 */
/*05a0*/ DADD R4, R4, -0.5 ; /* 0xbfe0000004047429 */
/* 0x001e0c0000000000 */
/*05b0*/ DADD R4, R4, R4 ; /* 0x0000000004047229 */
/* 0x001e140000000004 */
/*05c0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*05d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*05e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05f0*/ LOP3.LUT P0, RZ, R2, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff02ff7812 */
/* 0x000fda000780c0ff */
/*0600*/ @!P0 MOV R4, R2 ; /* 0x0000000200048202 */
/* 0x000fe20000000f00 */
/*0610*/ @!P0 BRA 0x730 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0620*/ FSETP.GEU.FTZ.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fda0003f1e000 */
/*0630*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*0640*/ @!P0 BRA 0x730 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0650*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*0660*/ @P0 FADD.FTZ R4, R2, 1 ; /* 0x3f80000002040421 */
/* 0x000fe20000010000 */
/*0670*/ @P0 BRA 0x730 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0680*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*0690*/ @!P0 MOV R4, R2 ; /* 0x0000000200048202 */
/* 0x000fe20000000f00 */
/*06a0*/ @!P0 BRA 0x730 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*06b0*/ FFMA R2, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002027823 */
/* 0x000fc800000000ff */
/*06c0*/ MUFU.RSQ R5, R2 ; /* 0x0000000200057308 */
/* 0x000e240000001400 */
/*06d0*/ FMUL.FTZ R7, R2, R5 ; /* 0x0000000502077220 */
/* 0x001fe40000410000 */
/*06e0*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*06f0*/ FADD.FTZ R4, -R7, -RZ ; /* 0x800000ff07047221 */
/* 0x000fc80000010100 */
/*0700*/ FFMA R4, R7, R4, R2 ; /* 0x0000000407047223 */
/* 0x000fc80000000002 */
/*0710*/ FFMA R4, R4, R5, R7 ; /* 0x0000000504047223 */
/* 0x000fc80000000007 */
/*0720*/ FMUL.FTZ R4, R4, 2.3283064365386962891e-10 ; /* 0x2f80000004047820 */
/* 0x000fc80000410000 */
/*0730*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0740*/ MOV R2, R4 ; /* 0x0000000400027202 */
/* 0x000fe40000000f00 */
/*0750*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fc80000000f00 */
/*0760*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff89004007950 */
/* 0x000fea0003c3ffff */
/*0770*/ BRA 0x770; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25UniformNormalDistributionPfS_i
.globl _Z25UniformNormalDistributionPfS_i
.p2align 8
.type _Z25UniformNormalDistributionPfS_i,@function
_Z25UniformNormalDistributionPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_and_b32 s3, s3, 0xffff
s_add_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s5, 0xbe41f39d
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x40434d4e
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s4
s_brev_b32 s4, 1
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v4, v3
v_fma_f32 v8, -v6, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v7
v_cndmask_b32_e64 v4, v4, v5, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v8
v_cndmask_b32_e64 v4, v4, v6, s0
s_mov_b32 s0, 0xdce2b7d6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, 0x37800000, v4
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cvt_f64_f32_e32 v[2:3], v4
v_and_or_b32 v4, v4, s4, 0x40434d4e
s_mov_b32 s4, 0x54df3c0e
v_cmp_gt_f64_e64 vcc_lo, |v[2:3]|, s[0:1]
s_mov_b32 s1, 0xbfe6a09e
s_mov_b32 s0, 0x667f3bcd
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, 0xdce2b7d6, vcc_lo
v_mul_f64 v[4:5], v[2:3], s[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[6:7], v[2:3], s[0:1], -v[4:5]
s_mov_b32 s1, 0x3c8bdd34
s_mov_b32 s0, 0x13b26456
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[6:7], v[2:3], s[0:1], v[6:7]
s_mov_b32 s1, 0xbe411663
s_mov_b32 s0, 0x37cfa789
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[8:9], v[4:5], v[6:7]
v_add_f64 v[10:11], |v[8:9]|, 4.0
v_add_f64 v[22:23], |v[8:9]|, |v[8:9]|
v_add_f64 v[4:5], v[8:9], -v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[12:13], v[10:11]
v_add_f64 v[24:25], v[22:23], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[26:27], v[24:25]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
v_fma_f64 v[12:13], v[14:15], v[12:13], v[12:13]
v_add_f64 v[14:15], |v[8:9]|, -4.0
v_fma_f64 v[28:29], -v[24:25], v[26:27], 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[12:13], 1.0
v_fma_f64 v[26:27], v[28:29], v[26:27], v[26:27]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[12:13]
v_fma_f64 v[24:25], -v[24:25], v[26:27], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[12:13], v[14:15], v[10:11]
v_fma_f64 v[24:25], v[24:25], v[26:27], v[26:27]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[12:13], 1.0
v_fma_f64 v[14:15], v[14:15], -4.0, |v[8:9]|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], -v[12:13], |v[8:9]|, v[14:15]
v_fma_f64 v[10:11], v[10:11], v[14:15], v[12:13]
v_mul_f64 v[14:15], v[8:9], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_fma_f64 v[12:13], v[10:11], s[4:5], s[0:1]
s_mov_b32 s1, 0x3e7b45f1
s_mov_b32 s0, 0xd9802b82
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[14:15]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3e6d9048
s_mov_b32 s0, 0x8a03dcdb
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0xbeab87b0
s_mov_b32 s0, 0x2eba62d8
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3e95104b
s_mov_b32 s0, 0xa56e15f1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3ed7f29f
s_mov_b32 s0, 0x71c907de
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0xbee78f5c
s_mov_b32 s0, 0x2cd770fb
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3ff71547
s_mov_b32 s0, 0x652b82fe
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_f64 v[16:17], v[14:15], s[0:1]
s_mov_b32 s1, 0xbef995fb
s_mov_b32 s0, 0x76d0a51a
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3f23be2e
s_mov_b32 s0, 0xc022d0ed
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rndne_f64_e32 v[16:17], v[16:17]
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0xbfe62e42
s_mov_b32 s0, 0xfefa39ef
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], s[0:1], v[14:15]
s_mov_b32 s1, 0xbf2a1deb
s_mov_b32 s0, 0x2fdbf62e
v_cvt_i32_f64_e32 v26, v[16:17]
s_delay_alu instid0(VALU_DEP_3)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0xbc7abc9e
s_mov_b32 s0, 0x3b39803f
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_fma_f64 v[18:19], v[16:17], s[0:1], v[18:19]
s_mov_b32 s1, 0xbf48d4ac
s_mov_b32 s0, 0x3689fc43
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], s[4:5], s[0:1]
s_mov_b32 s1, 0x3f749c67
s_mov_b32 s0, 0x192d909b
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0xbf909623
s_mov_b32 s0, 0x852ff070
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0x3fa3079e
s_mov_b32 s0, 0xdfadea8f
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0xbfb0fb06
s_mov_b32 s0, 0xdff65910
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0x3fb7fee0
s_mov_b32 s0, 0x4de8f32
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0xbfb9ddb2
s_mov_b32 s0, 0x3c3dbeb3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0x3fb16ece
s_mov_b32 s0, 0xfcfa6930
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0x3f8f7f5d
s_mov_b32 s0, 0xf66fb8a3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[20:21], v[18:19], v[20:21], s[0:1]
s_mov_b32 s1, 0xbfc1df1a
s_mov_b32 s0, 0xd154a2a8
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[12:13], v[10:11], v[12:13], s[0:1]
s_mov_b32 s1, 0x3fcdd2c8
s_mov_b32 s0, 0xb74febf8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[20:21], v[18:19], v[20:21], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], s[0:1]
v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[14:15]
s_mov_b32 s1, 0x403b39dc
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[12:13], v[18:19], v[20:21], 1.0
v_fma_f64 v[16:17], v[10:11], v[24:25], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[12:13], v[12:13], v26
v_fma_f64 v[18:19], -v[16:17], v[22:23], 1.0
v_add_f64 v[10:11], v[10:11], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v20, 0x7ff00000, v13, vcc_lo
v_fma_f64 v[13:14], -v[8:9], v[8:9], -v[14:15]
s_and_b32 vcc_lo, s0, vcc_lo
v_add_f64 v[10:11], v[18:19], v[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v19, 0, v20, s0
v_cndmask_b32_e32 v18, 0, v12, vcc_lo
s_mov_b32 s0, 0x41e48bfc
v_cmp_ngt_f64_e64 vcc_lo, |v[8:9]|, s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[18:19], v[13:14], v[18:19]
v_mul_f64 v[14:15], v[8:9], -2.0
v_fma_f64 v[10:11], v[24:25], v[10:11], v[16:17]
v_mul_f64 v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v11, 0, v11 :: v_dual_cndmask_b32 v10, 0, v10
v_cmp_gt_f64_e32 vcc_lo, 0, v[8:9]
v_add_f64 v[12:13], -v[10:11], 2.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v9, v11, v13 :: v_dual_cndmask_b32 v8, v10, v12
v_cmp_nle_f64_e32 vcc_lo, -1.0, v[2:3]
v_add_f64 v[2:3], v[6:7], -v[4:5]
v_mul_f64 v[10:11], v[14:15], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v5, 0, v11 :: v_dual_cndmask_b32 v4, 0, v10
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_fma_f64 v[2:3], v[2:3], v[4:5], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], 0.5
v_cvt_f32_f64_e32 v2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v2
v_add_f64 v[2:3], v[2:3], -0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[2:3]
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25UniformNormalDistributionPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25UniformNormalDistributionPfS_i, .Lfunc_end0-_Z25UniformNormalDistributionPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25UniformNormalDistributionPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25UniformNormalDistributionPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005cf56_00000000-6_UniformNormalDistribution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i
.type _Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i, @function
_Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25UniformNormalDistributionPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i, .-_Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i
.globl _Z25UniformNormalDistributionPfS_i
.type _Z25UniformNormalDistributionPfS_i, @function
_Z25UniformNormalDistributionPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z25UniformNormalDistributionPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z25UniformNormalDistributionPfS_i, .-_Z25UniformNormalDistributionPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25UniformNormalDistributionPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25UniformNormalDistributionPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "UniformNormalDistribution.hip"
.globl _Z40__device_stub__UniformNormalDistributionPfS_i # -- Begin function _Z40__device_stub__UniformNormalDistributionPfS_i
.p2align 4, 0x90
.type _Z40__device_stub__UniformNormalDistributionPfS_i,@function
_Z40__device_stub__UniformNormalDistributionPfS_i: # @_Z40__device_stub__UniformNormalDistributionPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25UniformNormalDistributionPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z40__device_stub__UniformNormalDistributionPfS_i, .Lfunc_end0-_Z40__device_stub__UniformNormalDistributionPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25UniformNormalDistributionPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25UniformNormalDistributionPfS_i,@object # @_Z25UniformNormalDistributionPfS_i
.section .rodata,"a",@progbits
.globl _Z25UniformNormalDistributionPfS_i
.p2align 3, 0x0
_Z25UniformNormalDistributionPfS_i:
.quad _Z40__device_stub__UniformNormalDistributionPfS_i
.size _Z25UniformNormalDistributionPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25UniformNormalDistributionPfS_i"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__UniformNormalDistributionPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25UniformNormalDistributionPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <future>
#include <thread>
#include <chrono>
#include <iostream>
#include <iterator>
#include <cstring>
#define N 1000000
#define SIZE 100
__constant__ int factor = 1;
//
// NOTE: while loop is for the case when number of elements in the array exceeds the
// number of blocks possible total in device to be launched
//
__global__
void vectorAdd(int *a, int *b, int *c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
while (i < N) {
c[i] = factor*(a[i] + b[i]);
i += blockDim.x * gridDim.x;
}
}
__global__
void matrixAdd(int **a,int **b, int**c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
c[i][j] = a[i][j] + b[i][j];
}
#define PRINT(x) \
std::cout << #x " = " << x << std::endl
void printImage(char* ptr) {
for (auto i=0; i<SIZE; i++) {
char cpyPtr[SIZE+1];
std::memcpy((void*)cpyPtr, (void*)(ptr + SIZE*i), SIZE);
cpyPtr[SIZE] = '\0';
printf("%s\n", cpyPtr);
}
printf("\n");
}
int main(int argc, char** argv) {
// start time
auto startTime = std::chrono::high_resolution_clock::now();
printf("Hello World\n");
// get the number of devices
int numDevices;
cudaGetDeviceCount(&numDevices);
PRINT(numDevices);
cudaDeviceProp prop;
for (auto i=0 ; i<numDevices; i++) {
cudaGetDeviceProperties(&prop, i);
PRINT(prop.name);
PRINT(prop.totalGlobalMem);
PRINT(prop.sharedMemPerBlock);
PRINT(prop.regsPerBlock);
PRINT(prop.warpSize);
PRINT(prop.memPitch);
PRINT(prop.maxThreadsPerBlock);
PRINT(prop.maxThreadsDim[0]);
PRINT(prop.maxThreadsDim[1]);
PRINT(prop.maxThreadsDim[2]);
PRINT(prop.maxGridSize[0]);
PRINT(prop.maxGridSize[1]);
PRINT(prop.maxGridSize[2]);
PRINT(prop.totalConstMem);
PRINT(prop.major);
PRINT(prop.minor);
PRINT(prop.clockRate);
PRINT(prop.textureAlignment);
PRINT(prop.deviceOverlap);
PRINT(prop.multiProcessorCount);
PRINT(prop.kernelExecTimeoutEnabled);
PRINT(prop.integrated);
PRINT(prop.canMapHostMemory);
PRINT(prop.computeMode);
PRINT(prop.maxTexture1D);
PRINT(prop.maxTexture2D[0]);
PRINT(prop.maxTexture2D[1]);
PRINT(prop.maxTexture3D[0]);
PRINT(prop.maxTexture3D[1]);
PRINT(prop.maxTexture3D[2]);
// PRINT(prop.maxTexture2DArray[0]);
// PRINT(prop.maxTexture2DArray[1]);
// PRINT(prop.maxTexture2DArray[2]);
PRINT(prop.concurrentKernels);
}
int h_a[N], h_b[N], h_c[N];
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, N*sizeof(int));
cudaMalloc(&d_b, N*sizeof(int));
cudaMalloc(&d_c, N*sizeof(int));
for (auto i=0; i<N; i++) {
h_a[i ] = i;
h_b[i] = i*i;
}
cudaMemcpy(d_a, h_a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, N*sizeof(int), cudaMemcpyHostToDevice);
vectorAdd<<<(N+127)/128, 128>>>(d_a, d_b, d_c);
cudaMemcpy(h_c, d_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for (auto i=0; i<N; i++) {
if (i < 10)
printf("c[%d] = %d\n", i, h_c[i]);
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// stop time
auto stopTime = std::chrono::high_resolution_clock::now();
PRINT((stopTime - startTime).count());
printf("Goodbye World\n");
} | code for sm_80
Function : _Z9matrixAddPPiS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R10, R11, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e020b */
/*0070*/ IMAD.WIDE R6, R10.reuse, R11.reuse, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x0c0fe400078e020b */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00a0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc600078e020b */
/*00b0*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e280000002600 */
/*00c0*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*00d0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1b00 */
/*00e0*/ IMAD R13, R13, c[0x0][0x4], R0 ; /* 0x000001000d0d7a24 */
/* 0x001fc800078e0200 */
/*00f0*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x004fc800078e0202 */
/*0100*/ IMAD.WIDE R8, R13.reuse, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x048fe400078e0206 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R2, R13, 0x4, R10 ; /* 0x000000040d027825 */
/* 0x010fe200078e020a */
/*0140*/ IADD3 R7, R4, R9, RZ ; /* 0x0000000904077210 */
/* 0x004fca0007ffe0ff */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9vectorAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xf423f, PT ; /* 0x000f423f0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0xf4240, PT ; /* 0x000f42400000780c */
/* 0x000fe40003f06270 */
/*0100*/ IADD3 R8, R4, R3, RZ ; /* 0x0000000304087210 */
/* 0x004fca0007ffe0ff */
/*0110*/ IMAD R9, R8, c[0x3][0x0], RZ ; /* 0x00c0000008097a24 */
/* 0x000fca00078e02ff */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c101904 */
/*0130*/ @!P0 BRA 0x70 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <future>
#include <thread>
#include <chrono>
#include <iostream>
#include <iterator>
#include <cstring>
#define N 1000000
#define SIZE 100
__constant__ int factor = 1;
//
// NOTE: while loop is for the case when number of elements in the array exceeds the
// number of blocks possible total in device to be launched
//
__global__
void vectorAdd(int *a, int *b, int *c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
while (i < N) {
c[i] = factor*(a[i] + b[i]);
i += blockDim.x * gridDim.x;
}
}
__global__
void matrixAdd(int **a,int **b, int**c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
c[i][j] = a[i][j] + b[i][j];
}
#define PRINT(x) \
std::cout << #x " = " << x << std::endl
void printImage(char* ptr) {
for (auto i=0; i<SIZE; i++) {
char cpyPtr[SIZE+1];
std::memcpy((void*)cpyPtr, (void*)(ptr + SIZE*i), SIZE);
cpyPtr[SIZE] = '\0';
printf("%s\n", cpyPtr);
}
printf("\n");
}
int main(int argc, char** argv) {
// start time
auto startTime = std::chrono::high_resolution_clock::now();
printf("Hello World\n");
// get the number of devices
int numDevices;
cudaGetDeviceCount(&numDevices);
PRINT(numDevices);
cudaDeviceProp prop;
for (auto i=0 ; i<numDevices; i++) {
cudaGetDeviceProperties(&prop, i);
PRINT(prop.name);
PRINT(prop.totalGlobalMem);
PRINT(prop.sharedMemPerBlock);
PRINT(prop.regsPerBlock);
PRINT(prop.warpSize);
PRINT(prop.memPitch);
PRINT(prop.maxThreadsPerBlock);
PRINT(prop.maxThreadsDim[0]);
PRINT(prop.maxThreadsDim[1]);
PRINT(prop.maxThreadsDim[2]);
PRINT(prop.maxGridSize[0]);
PRINT(prop.maxGridSize[1]);
PRINT(prop.maxGridSize[2]);
PRINT(prop.totalConstMem);
PRINT(prop.major);
PRINT(prop.minor);
PRINT(prop.clockRate);
PRINT(prop.textureAlignment);
PRINT(prop.deviceOverlap);
PRINT(prop.multiProcessorCount);
PRINT(prop.kernelExecTimeoutEnabled);
PRINT(prop.integrated);
PRINT(prop.canMapHostMemory);
PRINT(prop.computeMode);
PRINT(prop.maxTexture1D);
PRINT(prop.maxTexture2D[0]);
PRINT(prop.maxTexture2D[1]);
PRINT(prop.maxTexture3D[0]);
PRINT(prop.maxTexture3D[1]);
PRINT(prop.maxTexture3D[2]);
// PRINT(prop.maxTexture2DArray[0]);
// PRINT(prop.maxTexture2DArray[1]);
// PRINT(prop.maxTexture2DArray[2]);
PRINT(prop.concurrentKernels);
}
int h_a[N], h_b[N], h_c[N];
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, N*sizeof(int));
cudaMalloc(&d_b, N*sizeof(int));
cudaMalloc(&d_c, N*sizeof(int));
for (auto i=0; i<N; i++) {
h_a[i ] = i;
h_b[i] = i*i;
}
cudaMemcpy(d_a, h_a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, N*sizeof(int), cudaMemcpyHostToDevice);
vectorAdd<<<(N+127)/128, 128>>>(d_a, d_b, d_c);
cudaMemcpy(h_c, d_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for (auto i=0; i<N; i++) {
if (i < 10)
printf("c[%d] = %d\n", i, h_c[i]);
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// stop time
auto stopTime = std::chrono::high_resolution_clock::now();
PRINT((stopTime - startTime).count());
printf("Goodbye World\n");
} | .file "tmpxft_000afccc_00000000-6_vectorSum_nocmssw.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4963:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4963:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s\n"
.LC1:
.string "\n"
.text
.globl _Z10printImagePc
.type _Z10printImagePc, @function
_Z10printImagePc:
.LFB4957:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $112, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, %rbx
leaq 10000(%rdi), %rbp
leaq .LC0(%rip), %r12
.L4:
movq %rsp, %rdx
movdqu (%rbx), %xmm0
movaps %xmm0, (%rsp)
movdqu 16(%rbx), %xmm1
movaps %xmm1, 16(%rsp)
movdqu 32(%rbx), %xmm2
movaps %xmm2, 32(%rsp)
movdqu 48(%rbx), %xmm3
movaps %xmm3, 48(%rsp)
movdqu 64(%rbx), %xmm4
movaps %xmm4, 64(%rsp)
movdqu 80(%rbx), %xmm5
movaps %xmm5, 80(%rsp)
movl 96(%rbx), %eax
movl %eax, 96(%rsp)
movb $0, 100(%rsp)
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $100, %rbx
cmpq %rbp, %rbx
jne .L4
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4957:
.size _Z10printImagePc, .-_Z10printImagePc
.globl _Z32__device_stub__Z9vectorAddPiS_S_PiS_S_
.type _Z32__device_stub__Z9vectorAddPiS_S_PiS_S_, @function
_Z32__device_stub__Z9vectorAddPiS_S_PiS_S_:
.LFB4985:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9vectorAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4985:
.size _Z32__device_stub__Z9vectorAddPiS_S_PiS_S_, .-_Z32__device_stub__Z9vectorAddPiS_S_PiS_S_
.globl _Z9vectorAddPiS_S_
.type _Z9vectorAddPiS_S_, @function
_Z9vectorAddPiS_S_:
.LFB4986:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9vectorAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4986:
.size _Z9vectorAddPiS_S_, .-_Z9vectorAddPiS_S_
.section .rodata.str1.1
.LC2:
.string "Hello World\n"
.LC3:
.string "numDevices = "
.LC4:
.string "prop.name = "
.LC5:
.string "prop.totalGlobalMem = "
.LC6:
.string "prop.sharedMemPerBlock = "
.LC7:
.string "prop.regsPerBlock = "
.LC8:
.string "prop.warpSize = "
.LC9:
.string "prop.memPitch = "
.LC10:
.string "prop.maxThreadsPerBlock = "
.LC11:
.string "prop.maxThreadsDim[0] = "
.LC12:
.string "prop.maxThreadsDim[1] = "
.LC13:
.string "prop.maxThreadsDim[2] = "
.LC14:
.string "prop.maxGridSize[0] = "
.LC15:
.string "prop.maxGridSize[1] = "
.LC16:
.string "prop.maxGridSize[2] = "
.LC17:
.string "prop.totalConstMem = "
.LC18:
.string "prop.major = "
.LC19:
.string "prop.minor = "
.LC20:
.string "prop.clockRate = "
.LC21:
.string "prop.textureAlignment = "
.LC22:
.string "prop.deviceOverlap = "
.LC23:
.string "prop.multiProcessorCount = "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC24:
.string "prop.kernelExecTimeoutEnabled = "
.section .rodata.str1.1
.LC25:
.string "prop.integrated = "
.LC26:
.string "prop.canMapHostMemory = "
.LC27:
.string "prop.computeMode = "
.LC28:
.string "prop.maxTexture1D = "
.LC29:
.string "prop.maxTexture2D[0] = "
.LC30:
.string "prop.maxTexture2D[1] = "
.LC31:
.string "prop.maxTexture3D[0] = "
.LC32:
.string "prop.maxTexture3D[1] = "
.LC33:
.string "prop.maxTexture3D[2] = "
.LC34:
.string "prop.concurrentKernels = "
.LC35:
.string "c[%d] = %d\n"
.section .rodata.str1.8
.align 8
.LC36:
.string "(stopTime - startTime).count() = "
.section .rodata.str1.1
.LC37:
.string "Goodbye World\n"
.text
.globl main
.type main, @function
main:
.LFB4958:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -11997184(%rsp), %r11
.cfi_def_cfa 11, 11997240
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3960, %rsp
.cfi_def_cfa_offset 12001200
movq %fs:40, %rax
movq %rax, 12001128(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, 8(%rsp)
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 28(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 28(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
cmpl $0, 28(%rsp)
jle .L18
movl $0, %r12d
leaq .LC4(%rip), %r14
leaq _ZSt4cout(%rip), %rbx
leaq .LC5(%rip), %r13
jmp .L143
.L185:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L154
call _ZSt16__throw_bad_castv@PLT
.L154:
call __stack_chk_fail@PLT
.L21:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L22
.L186:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L155
call _ZSt16__throw_bad_castv@PLT
.L155:
call __stack_chk_fail@PLT
.L25:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L187:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L156
call _ZSt16__throw_bad_castv@PLT
.L156:
call __stack_chk_fail@PLT
.L29:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L188:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L157
call _ZSt16__throw_bad_castv@PLT
.L157:
call __stack_chk_fail@PLT
.L33:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.L189:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L158
call _ZSt16__throw_bad_castv@PLT
.L158:
call __stack_chk_fail@PLT
.L37:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L38
.L190:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L159
call _ZSt16__throw_bad_castv@PLT
.L159:
call __stack_chk_fail@PLT
.L41:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L42
.L191:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L160
call _ZSt16__throw_bad_castv@PLT
.L160:
call __stack_chk_fail@PLT
.L45:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L46
.L192:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L161
call _ZSt16__throw_bad_castv@PLT
.L161:
call __stack_chk_fail@PLT
.L49:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L50
.L193:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L162
call _ZSt16__throw_bad_castv@PLT
.L162:
call __stack_chk_fail@PLT
.L53:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L54
.L194:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L163
call _ZSt16__throw_bad_castv@PLT
.L163:
call __stack_chk_fail@PLT
.L57:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L58
.L195:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L164
call _ZSt16__throw_bad_castv@PLT
.L164:
call __stack_chk_fail@PLT
.L61:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L62
.L196:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L165
call _ZSt16__throw_bad_castv@PLT
.L165:
call __stack_chk_fail@PLT
.L65:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L66
.L197:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L166
call _ZSt16__throw_bad_castv@PLT
.L166:
call __stack_chk_fail@PLT
.L69:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L70
.L198:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L167
call _ZSt16__throw_bad_castv@PLT
.L167:
call __stack_chk_fail@PLT
.L73:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L74
.L199:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L168
call _ZSt16__throw_bad_castv@PLT
.L168:
call __stack_chk_fail@PLT
.L77:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L78
.L200:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L169
call _ZSt16__throw_bad_castv@PLT
.L169:
call __stack_chk_fail@PLT
.L81:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L82
.L201:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L170
call _ZSt16__throw_bad_castv@PLT
.L170:
call __stack_chk_fail@PLT
.L85:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L86
.L202:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L171
call _ZSt16__throw_bad_castv@PLT
.L171:
call __stack_chk_fail@PLT
.L89:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L90
.L203:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L172
call _ZSt16__throw_bad_castv@PLT
.L172:
call __stack_chk_fail@PLT
.L93:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L94
.L204:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L173
call _ZSt16__throw_bad_castv@PLT
.L173:
call __stack_chk_fail@PLT
.L97:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L98
.L205:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L174
call _ZSt16__throw_bad_castv@PLT
.L174:
call __stack_chk_fail@PLT
.L101:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L102
.L206:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L175
call _ZSt16__throw_bad_castv@PLT
.L175:
call __stack_chk_fail@PLT
.L105:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L106
.L207:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L176
call _ZSt16__throw_bad_castv@PLT
.L176:
call __stack_chk_fail@PLT
.L109:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L110
.L208:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L177
call _ZSt16__throw_bad_castv@PLT
.L177:
call __stack_chk_fail@PLT
.L113:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L114
.L209:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L178
call _ZSt16__throw_bad_castv@PLT
.L178:
call __stack_chk_fail@PLT
.L117:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L118
.L210:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L179
call _ZSt16__throw_bad_castv@PLT
.L179:
call __stack_chk_fail@PLT
.L121:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L122
.L211:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L180
call _ZSt16__throw_bad_castv@PLT
.L180:
call __stack_chk_fail@PLT
.L125:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L126
.L212:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L181
call _ZSt16__throw_bad_castv@PLT
.L181:
call __stack_chk_fail@PLT
.L129:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L130
.L213:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L182
call _ZSt16__throw_bad_castv@PLT
.L182:
call __stack_chk_fail@PLT
.L133:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L134
.L214:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L183
call _ZSt16__throw_bad_castv@PLT
.L183:
call __stack_chk_fail@PLT
.L137:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L138
.L215:
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L184
call _ZSt16__throw_bad_castv@PLT
.L184:
call __stack_chk_fail@PLT
.L141:
movq %r15, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r15), %rax
movl $10, %esi
movq %r15, %rdi
call *48(%rax)
movl %eax, %esi
.L142:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl %r12d, 28(%rsp)
jle .L18
.L143:
leaq 80(%rsp), %rbp
movl %r12d, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl $12, %edx
movq %r14, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L185
cmpb $0, 56(%rbp)
je .L21
movzbl 67(%rbp), %esi
.L22:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 368(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L186
cmpb $0, 56(%r15)
je .L25
movzbl 67(%r15), %esi
.L26:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $25, %edx
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 376(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L187
cmpb $0, 56(%r15)
je .L29
movzbl 67(%r15), %esi
.L30:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $20, %edx
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 384(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L188
cmpb $0, 56(%r15)
je .L33
movzbl 67(%r15), %esi
.L34:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $16, %edx
leaq .LC8(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 388(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L189
cmpb $0, 56(%r15)
je .L37
movzbl 67(%r15), %esi
.L38:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $16, %edx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 392(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L190
cmpb $0, 56(%r15)
je .L41
movzbl 67(%r15), %esi
.L42:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $26, %edx
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 400(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L191
cmpb $0, 56(%r15)
je .L45
movzbl 67(%r15), %esi
.L46:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $24, %edx
leaq .LC11(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 404(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L192
cmpb $0, 56(%r15)
je .L49
movzbl 67(%r15), %esi
.L50:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $24, %edx
leaq .LC12(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 408(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L193
cmpb $0, 56(%r15)
je .L53
movzbl 67(%r15), %esi
.L54:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $24, %edx
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 412(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L194
cmpb $0, 56(%r15)
je .L57
movzbl 67(%r15), %esi
.L58:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC14(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 416(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L195
cmpb $0, 56(%r15)
je .L61
movzbl 67(%r15), %esi
.L62:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC15(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 420(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L196
cmpb $0, 56(%r15)
je .L65
movzbl 67(%r15), %esi
.L66:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $22, %edx
leaq .LC16(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 424(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L197
cmpb $0, 56(%r15)
je .L69
movzbl 67(%r15), %esi
.L70:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $21, %edx
leaq .LC17(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 432(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L198
cmpb $0, 56(%r15)
je .L73
movzbl 67(%r15), %esi
.L74:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $13, %edx
leaq .LC18(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 440(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L199
cmpb $0, 56(%r15)
je .L77
movzbl 67(%r15), %esi
.L78:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $13, %edx
leaq .LC19(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 444(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L200
cmpb $0, 56(%r15)
je .L81
movzbl 67(%r15), %esi
.L82:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $17, %edx
leaq .LC20(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 428(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L201
cmpb $0, 56(%r15)
je .L85
movzbl 67(%r15), %esi
.L86:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $24, %edx
leaq .LC21(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 448(%rsp), %rsi
movq %rbx, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L202
cmpb $0, 56(%r15)
je .L89
movzbl 67(%r15), %esi
.L90:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $21, %edx
leaq .LC22(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 464(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L203
cmpb $0, 56(%r15)
je .L93
movzbl 67(%r15), %esi
.L94:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $27, %edx
leaq .LC23(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 468(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L204
cmpb $0, 56(%r15)
je .L97
movzbl 67(%r15), %esi
.L98:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $32, %edx
leaq .LC24(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 472(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L205
cmpb $0, 56(%r15)
je .L101
movzbl 67(%r15), %esi
.L102:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $18, %edx
leaq .LC25(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 476(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L206
cmpb $0, 56(%r15)
je .L105
movzbl 67(%r15), %esi
.L106:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $24, %edx
leaq .LC26(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 480(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L207
cmpb $0, 56(%r15)
je .L109
movzbl 67(%r15), %esi
.L110:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $19, %edx
leaq .LC27(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 484(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L208
cmpb $0, 56(%r15)
je .L113
movzbl 67(%r15), %esi
.L114:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $20, %edx
leaq .LC28(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 488(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L209
cmpb $0, 56(%r15)
je .L117
movzbl 67(%r15), %esi
.L118:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $23, %edx
leaq .LC29(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 500(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L210
cmpb $0, 56(%r15)
je .L121
movzbl 67(%r15), %esi
.L122:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $23, %edx
leaq .LC30(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 504(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L211
cmpb $0, 56(%r15)
je .L125
movzbl 67(%r15), %esi
.L126:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $23, %edx
leaq .LC31(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 536(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L212
cmpb $0, 56(%r15)
je .L129
movzbl 67(%r15), %esi
.L130:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $23, %edx
leaq .LC32(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 540(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L213
cmpb $0, 56(%r15)
je .L133
movzbl 67(%r15), %esi
.L134:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $23, %edx
leaq .LC33(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 544(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L214
cmpb $0, 56(%r15)
je .L137
movzbl 67(%r15), %esi
.L138:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $25, %edx
leaq .LC34(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 656(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r15
testq %r15, %r15
je .L215
cmpb $0, 56(%r15)
je .L141
movzbl 67(%r15), %esi
jmp .L142
.L18:
leaq 32(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $0, %eax
.L144:
movl %eax, 1120(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 4001120(%rsp,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L144
leaq 1120(%rsp), %rsi
movl $1, %ecx
movl $4000000, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4001120(%rsp), %rsi
movl $1, %ecx
movl $4000000, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $7813, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L216
.L145:
leaq 8001120(%rsp), %rdi
movl $2, %ecx
movl $4000000, %edx
movq 48(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
.L149:
cmpl $9, %ebx
jle .L217
addq $1, %rbx
cmpq $1000000, %rbx
jne .L149
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC36(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 8(%rsp), %rax
subq %rax, %rbx
movq %rbx, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC37(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 12001128(%rsp), %rax
subq %fs:40, %rax
jne .L218
movl $0, %eax
addq $12001144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L216:
.cfi_restore_state
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z32__device_stub__Z9vectorAddPiS_S_PiS_S_
jmp .L145
.L217:
movl 8001120(%rsp,%rbx,4), %ecx
movl %ebx, %edx
leaq .LC35(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
jmp .L149
.L218:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4958:
.size main, .-main
.globl _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
.type _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_, @function
_Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_:
.LFB4987:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L223
.L219:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L224
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L223:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPPiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L219
.L224:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4987:
.size _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_, .-_Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
.globl _Z9matrixAddPPiS0_S0_
.type _Z9matrixAddPPiS0_S0_, @function
_Z9matrixAddPPiS0_S0_:
.LFB4988:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9matrixAddPPiS0_S0_PPiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4988:
.size _Z9matrixAddPPiS0_S0_, .-_Z9matrixAddPPiS0_S0_
.section .rodata.str1.1
.LC38:
.string "_Z9matrixAddPPiS0_S0_"
.LC39:
.string "_Z9vectorAddPiS_S_"
.LC40:
.string "factor"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4990:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC38(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPPiS0_S0_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC39(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vectorAddPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC40(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6factor(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4990:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL6factor
.comm _ZL6factor,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <future>
#include <thread>
#include <chrono>
#include <iostream>
#include <iterator>
#include <cstring>
#define N 1000000
#define SIZE 100
__constant__ int factor = 1;
//
// NOTE: while loop is for the case when number of elements in the array exceeds the
// number of blocks possible total in device to be launched
//
__global__
void vectorAdd(int *a, int *b, int *c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
while (i < N) {
c[i] = factor*(a[i] + b[i]);
i += blockDim.x * gridDim.x;
}
}
__global__
void matrixAdd(int **a,int **b, int**c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
c[i][j] = a[i][j] + b[i][j];
}
#define PRINT(x) \
std::cout << #x " = " << x << std::endl
void printImage(char* ptr) {
for (auto i=0; i<SIZE; i++) {
char cpyPtr[SIZE+1];
std::memcpy((void*)cpyPtr, (void*)(ptr + SIZE*i), SIZE);
cpyPtr[SIZE] = '\0';
printf("%s\n", cpyPtr);
}
printf("\n");
}
int main(int argc, char** argv) {
// start time
auto startTime = std::chrono::high_resolution_clock::now();
printf("Hello World\n");
// get the number of devices
int numDevices;
cudaGetDeviceCount(&numDevices);
PRINT(numDevices);
cudaDeviceProp prop;
for (auto i=0 ; i<numDevices; i++) {
cudaGetDeviceProperties(&prop, i);
PRINT(prop.name);
PRINT(prop.totalGlobalMem);
PRINT(prop.sharedMemPerBlock);
PRINT(prop.regsPerBlock);
PRINT(prop.warpSize);
PRINT(prop.memPitch);
PRINT(prop.maxThreadsPerBlock);
PRINT(prop.maxThreadsDim[0]);
PRINT(prop.maxThreadsDim[1]);
PRINT(prop.maxThreadsDim[2]);
PRINT(prop.maxGridSize[0]);
PRINT(prop.maxGridSize[1]);
PRINT(prop.maxGridSize[2]);
PRINT(prop.totalConstMem);
PRINT(prop.major);
PRINT(prop.minor);
PRINT(prop.clockRate);
PRINT(prop.textureAlignment);
PRINT(prop.deviceOverlap);
PRINT(prop.multiProcessorCount);
PRINT(prop.kernelExecTimeoutEnabled);
PRINT(prop.integrated);
PRINT(prop.canMapHostMemory);
PRINT(prop.computeMode);
PRINT(prop.maxTexture1D);
PRINT(prop.maxTexture2D[0]);
PRINT(prop.maxTexture2D[1]);
PRINT(prop.maxTexture3D[0]);
PRINT(prop.maxTexture3D[1]);
PRINT(prop.maxTexture3D[2]);
// PRINT(prop.maxTexture2DArray[0]);
// PRINT(prop.maxTexture2DArray[1]);
// PRINT(prop.maxTexture2DArray[2]);
PRINT(prop.concurrentKernels);
}
int h_a[N], h_b[N], h_c[N];
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, N*sizeof(int));
cudaMalloc(&d_b, N*sizeof(int));
cudaMalloc(&d_c, N*sizeof(int));
for (auto i=0; i<N; i++) {
h_a[i ] = i;
h_b[i] = i*i;
}
cudaMemcpy(d_a, h_a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, N*sizeof(int), cudaMemcpyHostToDevice);
vectorAdd<<<(N+127)/128, 128>>>(d_a, d_b, d_c);
cudaMemcpy(h_c, d_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for (auto i=0; i<N; i++) {
if (i < 10)
printf("c[%d] = %d\n", i, h_c[i]);
}
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
// stop time
auto stopTime = std::chrono::high_resolution_clock::now();
PRINT((stopTime - startTime).count());
printf("Goodbye World\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <future>
#include <thread>
#include <chrono>
#include <iostream>
#include <iterator>
#include <cstring>
#define N 1000000
#define SIZE 100
__constant__ int factor = 1;
//
// NOTE: while loop is for the case when number of elements in the array exceeds the
// number of blocks possible total in device to be launched
//
__global__
void vectorAdd(int *a, int *b, int *c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
while (i < N) {
c[i] = factor*(a[i] + b[i]);
i += blockDim.x * gridDim.x;
}
}
__global__
void matrixAdd(int **a,int **b, int**c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
c[i][j] = a[i][j] + b[i][j];
}
#define PRINT(x) \
std::cout << #x " = " << x << std::endl
void printImage(char* ptr) {
for (auto i=0; i<SIZE; i++) {
char cpyPtr[SIZE+1];
std::memcpy((void*)cpyPtr, (void*)(ptr + SIZE*i), SIZE);
cpyPtr[SIZE] = '\0';
printf("%s\n", cpyPtr);
}
printf("\n");
}
int main(int argc, char** argv) {
// start time
auto startTime = std::chrono::high_resolution_clock::now();
printf("Hello World\n");
// get the number of devices
int numDevices;
hipGetDeviceCount(&numDevices);
PRINT(numDevices);
hipDeviceProp_t prop;
for (auto i=0 ; i<numDevices; i++) {
hipGetDeviceProperties(&prop, i);
PRINT(prop.name);
PRINT(prop.totalGlobalMem);
PRINT(prop.sharedMemPerBlock);
PRINT(prop.regsPerBlock);
PRINT(prop.warpSize);
PRINT(prop.memPitch);
PRINT(prop.maxThreadsPerBlock);
PRINT(prop.maxThreadsDim[0]);
PRINT(prop.maxThreadsDim[1]);
PRINT(prop.maxThreadsDim[2]);
PRINT(prop.maxGridSize[0]);
PRINT(prop.maxGridSize[1]);
PRINT(prop.maxGridSize[2]);
PRINT(prop.totalConstMem);
PRINT(prop.major);
PRINT(prop.minor);
PRINT(prop.clockRate);
PRINT(prop.textureAlignment);
PRINT(prop.deviceOverlap);
PRINT(prop.multiProcessorCount);
PRINT(prop.kernelExecTimeoutEnabled);
PRINT(prop.integrated);
PRINT(prop.canMapHostMemory);
PRINT(prop.computeMode);
PRINT(prop.maxTexture1D);
PRINT(prop.maxTexture2D[0]);
PRINT(prop.maxTexture2D[1]);
PRINT(prop.maxTexture3D[0]);
PRINT(prop.maxTexture3D[1]);
PRINT(prop.maxTexture3D[2]);
// PRINT(prop.maxTexture2DArray[0]);
// PRINT(prop.maxTexture2DArray[1]);
// PRINT(prop.maxTexture2DArray[2]);
PRINT(prop.concurrentKernels);
}
int h_a[N], h_b[N], h_c[N];
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, N*sizeof(int));
hipMalloc(&d_b, N*sizeof(int));
hipMalloc(&d_c, N*sizeof(int));
for (auto i=0; i<N; i++) {
h_a[i ] = i;
h_b[i] = i*i;
}
hipMemcpy(d_a, h_a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, N*sizeof(int), hipMemcpyHostToDevice);
vectorAdd<<<(N+127)/128, 128>>>(d_a, d_b, d_c);
hipMemcpy(h_c, d_c, N*sizeof(int), hipMemcpyDeviceToHost);
for (auto i=0; i<N; i++) {
if (i < 10)
printf("c[%d] = %d\n", i, h_c[i]);
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// stop time
auto stopTime = std::chrono::high_resolution_clock::now();
PRINT((stopTime - startTime).count());
printf("Goodbye World\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <future>
#include <thread>
#include <chrono>
#include <iostream>
#include <iterator>
#include <cstring>
#define N 1000000
#define SIZE 100
__constant__ int factor = 1;
//
// NOTE: while loop is for the case when number of elements in the array exceeds the
// number of blocks possible total in device to be launched
//
__global__
void vectorAdd(int *a, int *b, int *c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
while (i < N) {
c[i] = factor*(a[i] + b[i]);
i += blockDim.x * gridDim.x;
}
}
__global__
void matrixAdd(int **a,int **b, int**c) {
int i = blockIdx.x*blockDim.x + threadIdx.x;
int j = blockIdx.y*blockDim.y + threadIdx.y;
c[i][j] = a[i][j] + b[i][j];
}
#define PRINT(x) \
std::cout << #x " = " << x << std::endl
void printImage(char* ptr) {
for (auto i=0; i<SIZE; i++) {
char cpyPtr[SIZE+1];
std::memcpy((void*)cpyPtr, (void*)(ptr + SIZE*i), SIZE);
cpyPtr[SIZE] = '\0';
printf("%s\n", cpyPtr);
}
printf("\n");
}
int main(int argc, char** argv) {
// start time
auto startTime = std::chrono::high_resolution_clock::now();
printf("Hello World\n");
// get the number of devices
int numDevices;
hipGetDeviceCount(&numDevices);
PRINT(numDevices);
hipDeviceProp_t prop;
for (auto i=0 ; i<numDevices; i++) {
hipGetDeviceProperties(&prop, i);
PRINT(prop.name);
PRINT(prop.totalGlobalMem);
PRINT(prop.sharedMemPerBlock);
PRINT(prop.regsPerBlock);
PRINT(prop.warpSize);
PRINT(prop.memPitch);
PRINT(prop.maxThreadsPerBlock);
PRINT(prop.maxThreadsDim[0]);
PRINT(prop.maxThreadsDim[1]);
PRINT(prop.maxThreadsDim[2]);
PRINT(prop.maxGridSize[0]);
PRINT(prop.maxGridSize[1]);
PRINT(prop.maxGridSize[2]);
PRINT(prop.totalConstMem);
PRINT(prop.major);
PRINT(prop.minor);
PRINT(prop.clockRate);
PRINT(prop.textureAlignment);
PRINT(prop.deviceOverlap);
PRINT(prop.multiProcessorCount);
PRINT(prop.kernelExecTimeoutEnabled);
PRINT(prop.integrated);
PRINT(prop.canMapHostMemory);
PRINT(prop.computeMode);
PRINT(prop.maxTexture1D);
PRINT(prop.maxTexture2D[0]);
PRINT(prop.maxTexture2D[1]);
PRINT(prop.maxTexture3D[0]);
PRINT(prop.maxTexture3D[1]);
PRINT(prop.maxTexture3D[2]);
// PRINT(prop.maxTexture2DArray[0]);
// PRINT(prop.maxTexture2DArray[1]);
// PRINT(prop.maxTexture2DArray[2]);
PRINT(prop.concurrentKernels);
}
int h_a[N], h_b[N], h_c[N];
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, N*sizeof(int));
hipMalloc(&d_b, N*sizeof(int));
hipMalloc(&d_c, N*sizeof(int));
for (auto i=0; i<N; i++) {
h_a[i ] = i;
h_b[i] = i*i;
}
hipMemcpy(d_a, h_a, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, N*sizeof(int), hipMemcpyHostToDevice);
vectorAdd<<<(N+127)/128, 128>>>(d_a, d_b, d_c);
hipMemcpy(h_c, d_c, N*sizeof(int), hipMemcpyDeviceToHost);
for (auto i=0; i<N; i++) {
if (i < 10)
printf("c[%d] = %d\n", i, h_c[i]);
}
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
// stop time
auto stopTime = std::chrono::high_resolution_clock::now();
PRINT((stopTime - startTime).count());
printf("Goodbye World\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_
.globl _Z9vectorAddPiS_S_
.p2align 8
.type _Z9vectorAddPiS_S_,@function
_Z9vectorAddPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0xf4240, v1
s_cbranch_execz .LBB0_3
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, factor@rel32@lo+4
s_addc_u32 s11, s11, factor@rel32@hi+12
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s1, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0xf423f, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
v_mul_lo_u32 v0, v0, s1
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPiS_S_, .Lfunc_end0-_Z9vectorAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9matrixAddPPiS0_S0_
.globl _Z9matrixAddPPiS0_S0_
.p2align 8
.type _Z9matrixAddPPiS0_S0_,@function
_Z9matrixAddPPiS0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_mad_u64_u32 v[7:8], null, s15, s2, v[0:1]
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt vmcnt(1)
v_add_co_u32 v3, vcc_lo, v3, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v5, v7
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
flat_load_b32 v2, v[3:4]
flat_load_b32 v3, v[5:6]
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v8, vcc_lo
flat_store_b32 v[0:1], v2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPPiS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9matrixAddPPiS0_S0_, .Lfunc_end1-_Z9matrixAddPPiS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected factor
.type factor,@object
.data
.globl factor
.p2align 2, 0x0
factor:
.long 1
.size factor, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym factor
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPPiS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPPiS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixAddPPiS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R11, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff0b7435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R10, R10, c[0x0][0x0], R3 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R10, R11, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc800078e020b */
/*0070*/ IMAD.WIDE R6, R10.reuse, R11.reuse, c[0x0][0x168] ; /* 0x00005a000a067625 */
/* 0x0c0fe400078e020b */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00a0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x170] ; /* 0x00005c000a0a7625 */
/* 0x000fc600078e020b */
/*00b0*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e280000002600 */
/*00c0*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*00d0*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f22000c1e1b00 */
/*00e0*/ IMAD R13, R13, c[0x0][0x4], R0 ; /* 0x000001000d0d7a24 */
/* 0x001fc800078e0200 */
/*00f0*/ IMAD.WIDE R4, R13, 0x4, R2 ; /* 0x000000040d047825 */
/* 0x004fc800078e0202 */
/*0100*/ IMAD.WIDE R8, R13.reuse, 0x4, R6 ; /* 0x000000040d087825 */
/* 0x048fe400078e0206 */
/*0110*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.WIDE R2, R13, 0x4, R10 ; /* 0x000000040d027825 */
/* 0x010fe200078e020a */
/*0140*/ IADD3 R7, R4, R9, RZ ; /* 0x0000000904077210 */
/* 0x004fca0007ffe0ff */
/*0150*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9vectorAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0xf423f, PT ; /* 0x000f423f0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0xf4240, PT ; /* 0x000f42400000780c */
/* 0x000fe40003f06270 */
/*0100*/ IADD3 R8, R4, R3, RZ ; /* 0x0000000304087210 */
/* 0x004fca0007ffe0ff */
/*0110*/ IMAD R9, R8, c[0x3][0x0], RZ ; /* 0x00c0000008097a24 */
/* 0x000fca00078e02ff */
/*0120*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c101904 */
/*0130*/ @!P0 BRA 0x70 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vectorAddPiS_S_
.globl _Z9vectorAddPiS_S_
.p2align 8
.type _Z9vectorAddPiS_S_,@function
_Z9vectorAddPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0xf4240, v1
s_cbranch_execz .LBB0_3
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, factor@rel32@lo+4
s_addc_u32 s11, s11, factor@rel32@hi+12
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s1, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s8, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0xf423f, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
v_mul_lo_u32 v0, v0, s1
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vectorAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vectorAddPiS_S_, .Lfunc_end0-_Z9vectorAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z9matrixAddPPiS0_S0_
.globl _Z9matrixAddPPiS0_S0_
.p2align 8
.type _Z9matrixAddPPiS0_S0_,@function
_Z9matrixAddPPiS0_S0_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[1:2], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_mad_u64_u32 v[7:8], null, s15, s2, v[0:1]
global_load_b64 v[3:4], v[3:4], off
global_load_b64 v[5:6], v[5:6], off
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_waitcnt vmcnt(1)
v_add_co_u32 v3, vcc_lo, v3, v7
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v8, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v5, vcc_lo, v5, v7
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v8, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
flat_load_b32 v2, v[3:4]
flat_load_b32 v3, v[5:6]
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v0, v7
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v8, vcc_lo
flat_store_b32 v[0:1], v2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPPiS0_S0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z9matrixAddPPiS0_S0_, .Lfunc_end1-_Z9matrixAddPPiS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected factor
.type factor,@object
.data
.globl factor
.p2align 2, 0x0
factor:
.long 1
.size factor, 4
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym factor
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vectorAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vectorAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPPiS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPPiS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <iostream>
// Define kernel function.
__global__ void gpuAdd(int *device_a, int *device_b, int *device_c)
{
*device_c = *device_a + *device_b;
}
int main(int argc, char **argv)
{
// Define host variables and device pointers.
int host_a, host_b, host_c;
int *device_a, *device_b, *device_c;
// Initialize host variables.
host_a = 11;
host_b = 13;
// CUDA 错误处理。
cudaError_t cudaStatus;
// Allocate GPU buffers for three vectors(two input, ont output).
cudaStatus = cudaMalloc((void**)&device_c, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMalloc((void**)&device_a, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMalloc((void**)&device_b, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(device_a, &host_a, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMemcpy(device_b, &host_b, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
// Launch kernel on GPU device with one thread for each element.
gpuAdd <<< 1, 1 >>> (device_a, device_b, device_c);
// Check for any errors launching the kernel.
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// 跳转到标号 Error
goto Error;
}
// Copy output vector from GPU device to host memory.
cudaStatus = cudaMemcpy(&host_c, device_c, sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
printf("Passing parameters by reference output: %d + %d = %d\n", host_a, host_b, host_c);
Error:
// 标号处理，直接释放内存，结束程序。
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | code for sm_80
Function : _Z6gpuAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <iostream>
// Define kernel function.
__global__ void gpuAdd(int *device_a, int *device_b, int *device_c)
{
*device_c = *device_a + *device_b;
}
int main(int argc, char **argv)
{
// Define host variables and device pointers.
int host_a, host_b, host_c;
int *device_a, *device_b, *device_c;
// Initialize host variables.
host_a = 11;
host_b = 13;
// CUDA 错误处理。
cudaError_t cudaStatus;
// Allocate GPU buffers for three vectors(two input, ont output).
cudaStatus = cudaMalloc((void**)&device_c, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMalloc((void**)&device_a, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMalloc((void**)&device_b, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(device_a, &host_a, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMemcpy(device_b, &host_b, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
// Launch kernel on GPU device with one thread for each element.
gpuAdd <<< 1, 1 >>> (device_a, device_b, device_c);
// Check for any errors launching the kernel.
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// 跳转到标号 Error
goto Error;
}
// Copy output vector from GPU device to host memory.
cudaStatus = cudaMemcpy(&host_c, device_c, sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
printf("Passing parameters by reference output: %d + %d = %d\n", host_a, host_b, host_c);
Error:
// 标号处理，直接释放内存，结束程序。
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | .file "tmpxft_00140b7b_00000000-6_4_02_cuda_error_handling.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6gpuAddPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6gpuAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6gpuAddPiS_S_PiS_S_
.globl _Z6gpuAddPiS_S_
.type _Z6gpuAddPiS_S_, @function
_Z6gpuAddPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6gpuAddPiS_S_, .-_Z6gpuAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc failed.\n"
.LC1:
.string "cudaMemcpy failed.\n"
.LC2:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Passing parameters by reference output: %d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $11, (%rsp)
movl $13, 4(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L23
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L24
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L26
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L27
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L18:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl 44(%rsp), %r8d
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L23:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_
jmp .L18
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L30:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6gpuAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6gpuAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <iostream>
// Define kernel function.
__global__ void gpuAdd(int *device_a, int *device_b, int *device_c)
{
*device_c = *device_a + *device_b;
}
int main(int argc, char **argv)
{
// Define host variables and device pointers.
int host_a, host_b, host_c;
int *device_a, *device_b, *device_c;
// Initialize host variables.
host_a = 11;
host_b = 13;
// CUDA 错误处理。
cudaError_t cudaStatus;
// Allocate GPU buffers for three vectors(two input, ont output).
cudaStatus = cudaMalloc((void**)&device_c, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMalloc((void**)&device_a, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMalloc((void**)&device_b, sizeof(int));
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = cudaMemcpy(device_a, &host_a, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = cudaMemcpy(device_b, &host_b, sizeof(int), cudaMemcpyHostToDevice);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
// Launch kernel on GPU device with one thread for each element.
gpuAdd <<< 1, 1 >>> (device_a, device_b, device_c);
// Check for any errors launching the kernel.
cudaStatus = cudaGetLastError();
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// 跳转到标号 Error
goto Error;
}
// Copy output vector from GPU device to host memory.
cudaStatus = cudaMemcpy(&host_c, device_c, sizeof(int), cudaMemcpyDeviceToHost);
if (cudaStatus != cudaSuccess)
{
fprintf(stderr, "cudaMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
printf("Passing parameters by reference output: %d + %d = %d\n", host_a, host_b, host_c);
Error:
// 标号处理，直接释放内存，结束程序。
cudaFree(device_a);
cudaFree(device_b);
cudaFree(device_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
// Define kernel function.
__global__ void gpuAdd(int *device_a, int *device_b, int *device_c)
{
*device_c = *device_a + *device_b;
}
int main(int argc, char **argv)
{
// Define host variables and device pointers.
int host_a, host_b, host_c;
int *device_a, *device_b, *device_c;
// Initialize host variables.
host_a = 11;
host_b = 13;
// CUDA 错误处理。
hipError_t cudaStatus;
// Allocate GPU buffers for three vectors(two input, ont output).
cudaStatus = hipMalloc((void**)&device_c, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMalloc((void**)&device_a, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMalloc((void**)&device_b, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(device_a, &host_a, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMemcpy(device_b, &host_b, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
// Launch kernel on GPU device with one thread for each element.
gpuAdd <<< 1, 1 >>> (device_a, device_b, device_c);
// Check for any errors launching the kernel.
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
// 跳转到标号 Error
goto Error;
}
// Copy output vector from GPU device to host memory.
cudaStatus = hipMemcpy(&host_c, device_c, sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
printf("Passing parameters by reference output: %d + %d = %d\n", host_a, host_b, host_c);
Error:
// 标号处理，直接释放内存，结束程序。
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
// Define kernel function.
__global__ void gpuAdd(int *device_a, int *device_b, int *device_c)
{
*device_c = *device_a + *device_b;
}
int main(int argc, char **argv)
{
// Define host variables and device pointers.
int host_a, host_b, host_c;
int *device_a, *device_b, *device_c;
// Initialize host variables.
host_a = 11;
host_b = 13;
// CUDA 错误处理。
hipError_t cudaStatus;
// Allocate GPU buffers for three vectors(two input, ont output).
cudaStatus = hipMalloc((void**)&device_c, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMalloc((void**)&device_a, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMalloc((void**)&device_b, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(device_a, &host_a, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMemcpy(device_b, &host_b, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
// Launch kernel on GPU device with one thread for each element.
gpuAdd <<< 1, 1 >>> (device_a, device_b, device_c);
// Check for any errors launching the kernel.
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
// 跳转到标号 Error
goto Error;
}
// Copy output vector from GPU device to host memory.
cudaStatus = hipMemcpy(&host_c, device_c, sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
printf("Passing parameters by reference output: %d + %d = %d\n", host_a, host_b, host_c);
Error:
// 标号处理，直接释放内存，结束程序。
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6gpuAddPiS_S_
.globl _Z6gpuAddPiS_S_
.p2align 8
.type _Z6gpuAddPiS_S_,@function
_Z6gpuAddPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6gpuAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6gpuAddPiS_S_, .Lfunc_end0-_Z6gpuAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6gpuAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6gpuAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
// Define kernel function.
__global__ void gpuAdd(int *device_a, int *device_b, int *device_c)
{
*device_c = *device_a + *device_b;
}
int main(int argc, char **argv)
{
// Define host variables and device pointers.
int host_a, host_b, host_c;
int *device_a, *device_b, *device_c;
// Initialize host variables.
host_a = 11;
host_b = 13;
// CUDA 错误处理。
hipError_t cudaStatus;
// Allocate GPU buffers for three vectors(two input, ont output).
cudaStatus = hipMalloc((void**)&device_c, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMalloc((void**)&device_a, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMalloc((void**)&device_b, sizeof(int));
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMalloc failed.\n");
// 跳转到标号 Error
goto Error;
}
// Copy input vectors from host memory to GPU buffers.
cudaStatus = hipMemcpy(device_a, &host_a, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
cudaStatus = hipMemcpy(device_b, &host_b, sizeof(int), hipMemcpyHostToDevice);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
// Launch kernel on GPU device with one thread for each element.
gpuAdd <<< 1, 1 >>> (device_a, device_b, device_c);
// Check for any errors launching the kernel.
cudaStatus = hipGetLastError();
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "addKernel launch failed: %s\n", hipGetErrorString(cudaStatus));
// 跳转到标号 Error
goto Error;
}
// Copy output vector from GPU device to host memory.
cudaStatus = hipMemcpy(&host_c, device_c, sizeof(int), hipMemcpyDeviceToHost);
if (cudaStatus != hipSuccess)
{
fprintf(stderr, "hipMemcpy failed.\n");
// 跳转到标号 Error
goto Error;
}
printf("Passing parameters by reference output: %d + %d = %d\n", host_a, host_b, host_c);
Error:
// 标号处理，直接释放内存，结束程序。
hipFree(device_a);
hipFree(device_b);
hipFree(device_c);
return 0;
} | .text
.file "4_02_cuda_error_handling.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__gpuAddPiS_S_ # -- Begin function _Z21__device_stub__gpuAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__gpuAddPiS_S_,@function
_Z21__device_stub__gpuAddPiS_S_: # @_Z21__device_stub__gpuAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6gpuAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__gpuAddPiS_S_, .Lfunc_end0-_Z21__device_stub__gpuAddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $11, 4(%rsp)
movl $13, (%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.4:
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.5:
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.8:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6gpuAddPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.13:
movl 4(%rsp), %esi
movl (%rsp), %edx
movl 32(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_14
.LBB1_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
.LBB1_2:
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
.LBB1_14:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_14
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6gpuAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6gpuAddPiS_S_,@object # @_Z6gpuAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6gpuAddPiS_S_
.p2align 3, 0x0
_Z6gpuAddPiS_S_:
.quad _Z21__device_stub__gpuAddPiS_S_
.size _Z6gpuAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc failed.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMemcpy failed.\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "addKernel launch failed: %s\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Passing parameters by reference output: %d + %d = %d\n"
.size .L.str.3, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6gpuAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__gpuAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6gpuAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6gpuAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe200078e00ff */
/*0090*/ MOV R7, c[0x0][0x174] ; /* 0x00005d0000077a02 */
/* 0x000fe40000000f00 */
/*00a0*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00b0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6gpuAddPiS_S_
.globl _Z6gpuAddPiS_S_
.p2align 8
.type _Z6gpuAddPiS_S_,@function
_Z6gpuAddPiS_S_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s3, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6gpuAddPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6gpuAddPiS_S_, .Lfunc_end0-_Z6gpuAddPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6gpuAddPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6gpuAddPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00140b7b_00000000-6_4_02_cuda_error_handling.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6gpuAddPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6gpuAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6gpuAddPiS_S_PiS_S_
.globl _Z6gpuAddPiS_S_
.type _Z6gpuAddPiS_S_, @function
_Z6gpuAddPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6gpuAddPiS_S_, .-_Z6gpuAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc failed.\n"
.LC1:
.string "cudaMemcpy failed.\n"
.LC2:
.string "addKernel launch failed: %s\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Passing parameters by reference output: %d + %d = %d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $11, (%rsp)
movl $13, 4(%rsp)
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L23
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L24
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L25
movq %rsp, %rsi
movl $1, %ecx
movl $4, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L26
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L27
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L18:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
leaq 44(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl 44(%rsp), %r8d
movl 4(%rsp), %ecx
movl (%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L23:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L25:
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L26:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L27:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L28:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6gpuAddPiS_S_PiS_S_
jmp .L18
.L29:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L30:
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L13
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6gpuAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6gpuAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "4_02_cuda_error_handling.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__gpuAddPiS_S_ # -- Begin function _Z21__device_stub__gpuAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__gpuAddPiS_S_,@function
_Z21__device_stub__gpuAddPiS_S_: # @_Z21__device_stub__gpuAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6gpuAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__gpuAddPiS_S_, .Lfunc_end0-_Z21__device_stub__gpuAddPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $11, 4(%rsp)
movl $13, (%rsp)
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.3:
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.4:
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB1_1
# %bb.5:
movq 24(%rsp), %rdi
leaq 4(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.7:
movq 16(%rsp), %rdi
movq %rsp, %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.8:
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 104(%rsp), %rax
movq %rax, 48(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6gpuAddPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_10:
callq hipGetLastError
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq 8(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_6
# %bb.13:
movl 4(%rsp), %esi
movl (%rsp), %edx
movl 32(%rsp), %ecx
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB1_14
.LBB1_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
jmp .LBB1_2
.LBB1_6:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
.LBB1_2:
movl $18, %esi
movl $1, %edx
callq fwrite@PLT
.LBB1_14:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
jmp .LBB1_14
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6gpuAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6gpuAddPiS_S_,@object # @_Z6gpuAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6gpuAddPiS_S_
.p2align 3, 0x0
_Z6gpuAddPiS_S_:
.quad _Z21__device_stub__gpuAddPiS_S_
.size _Z6gpuAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc failed.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMemcpy failed.\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "addKernel launch failed: %s\n"
.size .L.str.2, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Passing parameters by reference output: %d + %d = %d\n"
.size .L.str.3, 54
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6gpuAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__gpuAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6gpuAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <numeric>
#include <cstdlib>
// Kolaylık olsun
using namespace std;
// Tipik bir C++ fonksiyonu
void carp(int n, float *x, float *y, float *z)
{
for (int i = 0; i < n; i++)
{
z[i] = x[i] * y[i];
}
}
// Ustteki fonksiyonun CUDA versiyonu
__global__
void carp_cuda(int n, float *x, float *y, float *z)
{
for (int i = threadIdx.x; i < n; i += blockDim.x)
{
z[i] = x[i] * y[i];
}
}
int main(int argc, char *argv[])
{
// Çok büyük bir sayı belirleyelim
int N = 10000;
float *x_gpu, *y_gpu, *z_gpu, *x_cpu, *y_cpu, *z_cpu;
// GPU ve CPU tarafindan ulasilabilen memory ayirtalim
cudaMallocManaged(&x_gpu, N * sizeof(float));
cudaMallocManaged(&y_gpu, N * sizeof(float));
cudaMallocManaged(&z_gpu, N * sizeof(float));
// Sadece CPU tarafindan ulasilabilen memory ayirtalim
x_cpu = new float[N];
y_cpu = new float[N];
z_cpu = new float[N];
//
for (int i = 0; i < N; ++i) {
x_gpu[i] = 1.0f;
y_gpu[i] = 2.0f;
x_cpu[i] = 1.0f;
y_cpu[i] = 2.0f;
}
// Fonksiyonu GPU'da argv[1] blokta ve her blokta argv[2] thread
// olacak sekilde çagiralım
int blok_sayisi = atoi(argv[1]);
int thread_sayisi = atoi(argv[2]);
carp_cuda<<<blok_sayisi, thread_sayisi>>>(N, x_gpu, y_gpu, z_gpu);
// GPU'yu bekleyelim de isini bitirsin, yoksa ortam karisir.
cudaDeviceSynchronize();
// Normal CPU fonlsiyonunu çagiralım
carp(N, x_cpu, y_cpu, z_cpu);
// Bakalim dogru mu yaptik?
// z_gpu ve z_cpu ayni degerlere sahip olması lazim
for(int i = 0; i < N; ++i)
cout << z_cpu[i] << " " << z_gpu[i] << endl;
// Release the Kraken - Kraken'i saliverin gelsin.
cudaFree(x_gpu);
cudaFree(y_gpu);
cudaFree(z_gpu);
delete [] x_cpu;
delete [] y_cpu;
delete [] z_cpu;
return 0;
} | code for sm_80
Function : _Z9carp_cudaiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x040fe200078e0207 */
/*00b0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*00d0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*00f0*/ @!P0 BRA 0x40 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <numeric>
#include <cstdlib>
// Kolaylık olsun
using namespace std;
// Tipik bir C++ fonksiyonu
void carp(int n, float *x, float *y, float *z)
{
for (int i = 0; i < n; i++)
{
z[i] = x[i] * y[i];
}
}
// Ustteki fonksiyonun CUDA versiyonu
__global__
void carp_cuda(int n, float *x, float *y, float *z)
{
for (int i = threadIdx.x; i < n; i += blockDim.x)
{
z[i] = x[i] * y[i];
}
}
int main(int argc, char *argv[])
{
// Çok büyük bir sayı belirleyelim
int N = 10000;
float *x_gpu, *y_gpu, *z_gpu, *x_cpu, *y_cpu, *z_cpu;
// GPU ve CPU tarafindan ulasilabilen memory ayirtalim
cudaMallocManaged(&x_gpu, N * sizeof(float));
cudaMallocManaged(&y_gpu, N * sizeof(float));
cudaMallocManaged(&z_gpu, N * sizeof(float));
// Sadece CPU tarafindan ulasilabilen memory ayirtalim
x_cpu = new float[N];
y_cpu = new float[N];
z_cpu = new float[N];
//
for (int i = 0; i < N; ++i) {
x_gpu[i] = 1.0f;
y_gpu[i] = 2.0f;
x_cpu[i] = 1.0f;
y_cpu[i] = 2.0f;
}
// Fonksiyonu GPU'da argv[1] blokta ve her blokta argv[2] thread
// olacak sekilde çagiralım
int blok_sayisi = atoi(argv[1]);
int thread_sayisi = atoi(argv[2]);
carp_cuda<<<blok_sayisi, thread_sayisi>>>(N, x_gpu, y_gpu, z_gpu);
// GPU'yu bekleyelim de isini bitirsin, yoksa ortam karisir.
cudaDeviceSynchronize();
// Normal CPU fonlsiyonunu çagiralım
carp(N, x_cpu, y_cpu, z_cpu);
// Bakalim dogru mu yaptik?
// z_gpu ve z_cpu ayni degerlere sahip olması lazim
for(int i = 0; i < N; ++i)
cout << z_cpu[i] << " " << z_gpu[i] << endl;
// Release the Kraken - Kraken'i saliverin gelsin.
cudaFree(x_gpu);
cudaFree(y_gpu);
cudaFree(z_gpu);
delete [] x_cpu;
delete [] y_cpu;
delete [] z_cpu;
return 0;
} | .file "tmpxft_0005661b_00000000-6_cuda_ornek.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3712:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4carpiPfS_S_
.type _Z4carpiPfS_S_, @function
_Z4carpiPfS_S_:
.LFB3708:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
salq $2, %rdi
movl $0, %eax
.L5:
movss (%rsi,%rax), %xmm0
mulss (%rdx,%rax), %xmm0
movss %xmm0, (%rcx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3708:
.size _Z4carpiPfS_S_, .-_Z4carpiPfS_S_
.globl _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_
.type _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_, @function
_Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_:
.LFB3734:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9carp_cudaiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3734:
.size _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_, .-_Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_
.globl _Z9carp_cudaiPfS_S_
.type _Z9carp_cudaiPfS_S_, @function
_Z9carp_cudaiPfS_S_:
.LFB3735:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3735:
.size _Z9carp_cudaiPfS_S_, .-_Z9carp_cudaiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3709:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
movl $40000, %edi
call _Znam@PLT
movq %rax, %r14
movl $40000, %edi
call _Znam@PLT
movq %rax, %r13
movl $40000, %edi
call _Znam@PLT
movq %rax, %r15
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L16:
movq 8(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movss %xmm1, (%r14,%rax)
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $40000, %rax
jne .L16
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L17:
call cudaDeviceSynchronize@PLT
movq %r15, %rcx
movq %r13, %rdx
movq %r14, %rsi
movl $10000, %edi
call _Z4carpiPfS_S_
movl $0, %ebp
jmp .L22
.L27:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $10000, %edi
call _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_
jmp .L17
.L30:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
call _ZSt16__throw_bad_castv@PLT
.L28:
call __stack_chk_fail@PLT
.L20:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L21:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbp
cmpq $40000, %rbp
je .L29
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L30
cmpb $0, 56(%r12)
je .L20
movzbl 67(%r12), %esi
jmp .L21
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3709:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9carp_cudaiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3737:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9carp_cudaiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3737:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <numeric>
#include <cstdlib>
// Kolaylık olsun
using namespace std;
// Tipik bir C++ fonksiyonu
void carp(int n, float *x, float *y, float *z)
{
for (int i = 0; i < n; i++)
{
z[i] = x[i] * y[i];
}
}
// Ustteki fonksiyonun CUDA versiyonu
__global__
void carp_cuda(int n, float *x, float *y, float *z)
{
for (int i = threadIdx.x; i < n; i += blockDim.x)
{
z[i] = x[i] * y[i];
}
}
int main(int argc, char *argv[])
{
// Çok büyük bir sayı belirleyelim
int N = 10000;
float *x_gpu, *y_gpu, *z_gpu, *x_cpu, *y_cpu, *z_cpu;
// GPU ve CPU tarafindan ulasilabilen memory ayirtalim
cudaMallocManaged(&x_gpu, N * sizeof(float));
cudaMallocManaged(&y_gpu, N * sizeof(float));
cudaMallocManaged(&z_gpu, N * sizeof(float));
// Sadece CPU tarafindan ulasilabilen memory ayirtalim
x_cpu = new float[N];
y_cpu = new float[N];
z_cpu = new float[N];
//
for (int i = 0; i < N; ++i) {
x_gpu[i] = 1.0f;
y_gpu[i] = 2.0f;
x_cpu[i] = 1.0f;
y_cpu[i] = 2.0f;
}
// Fonksiyonu GPU'da argv[1] blokta ve her blokta argv[2] thread
// olacak sekilde çagiralım
int blok_sayisi = atoi(argv[1]);
int thread_sayisi = atoi(argv[2]);
carp_cuda<<<blok_sayisi, thread_sayisi>>>(N, x_gpu, y_gpu, z_gpu);
// GPU'yu bekleyelim de isini bitirsin, yoksa ortam karisir.
cudaDeviceSynchronize();
// Normal CPU fonlsiyonunu çagiralım
carp(N, x_cpu, y_cpu, z_cpu);
// Bakalim dogru mu yaptik?
// z_gpu ve z_cpu ayni degerlere sahip olması lazim
for(int i = 0; i < N; ++i)
cout << z_cpu[i] << " " << z_gpu[i] << endl;
// Release the Kraken - Kraken'i saliverin gelsin.
cudaFree(x_gpu);
cudaFree(y_gpu);
cudaFree(z_gpu);
delete [] x_cpu;
delete [] y_cpu;
delete [] z_cpu;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <cstdlib>
// Kolaylık olsun
using namespace std;
// Tipik bir C++ fonksiyonu
void carp(int n, float *x, float *y, float *z)
{
for (int i = 0; i < n; i++)
{
z[i] = x[i] * y[i];
}
}
// Ustteki fonksiyonun CUDA versiyonu
__global__
void carp_cuda(int n, float *x, float *y, float *z)
{
for (int i = threadIdx.x; i < n; i += blockDim.x)
{
z[i] = x[i] * y[i];
}
}
int main(int argc, char *argv[])
{
// Çok büyük bir sayı belirleyelim
int N = 10000;
float *x_gpu, *y_gpu, *z_gpu, *x_cpu, *y_cpu, *z_cpu;
// GPU ve CPU tarafindan ulasilabilen memory ayirtalim
hipMallocManaged(&x_gpu, N * sizeof(float));
hipMallocManaged(&y_gpu, N * sizeof(float));
hipMallocManaged(&z_gpu, N * sizeof(float));
// Sadece CPU tarafindan ulasilabilen memory ayirtalim
x_cpu = new float[N];
y_cpu = new float[N];
z_cpu = new float[N];
//
for (int i = 0; i < N; ++i) {
x_gpu[i] = 1.0f;
y_gpu[i] = 2.0f;
x_cpu[i] = 1.0f;
y_cpu[i] = 2.0f;
}
// Fonksiyonu GPU'da argv[1] blokta ve her blokta argv[2] thread
// olacak sekilde çagiralım
int blok_sayisi = atoi(argv[1]);
int thread_sayisi = atoi(argv[2]);
carp_cuda<<<blok_sayisi, thread_sayisi>>>(N, x_gpu, y_gpu, z_gpu);
// GPU'yu bekleyelim de isini bitirsin, yoksa ortam karisir.
hipDeviceSynchronize();
// Normal CPU fonlsiyonunu çagiralım
carp(N, x_cpu, y_cpu, z_cpu);
// Bakalim dogru mu yaptik?
// z_gpu ve z_cpu ayni degerlere sahip olması lazim
for(int i = 0; i < N; ++i)
cout << z_cpu[i] << " " << z_gpu[i] << endl;
// Release the Kraken - Kraken'i saliverin gelsin.
hipFree(x_gpu);
hipFree(y_gpu);
hipFree(z_gpu);
delete [] x_cpu;
delete [] y_cpu;
delete [] z_cpu;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <cstdlib>
// Kolaylık olsun
using namespace std;
// Tipik bir C++ fonksiyonu
void carp(int n, float *x, float *y, float *z)
{
for (int i = 0; i < n; i++)
{
z[i] = x[i] * y[i];
}
}
// Ustteki fonksiyonun CUDA versiyonu
__global__
void carp_cuda(int n, float *x, float *y, float *z)
{
for (int i = threadIdx.x; i < n; i += blockDim.x)
{
z[i] = x[i] * y[i];
}
}
int main(int argc, char *argv[])
{
// Çok büyük bir sayı belirleyelim
int N = 10000;
float *x_gpu, *y_gpu, *z_gpu, *x_cpu, *y_cpu, *z_cpu;
// GPU ve CPU tarafindan ulasilabilen memory ayirtalim
hipMallocManaged(&x_gpu, N * sizeof(float));
hipMallocManaged(&y_gpu, N * sizeof(float));
hipMallocManaged(&z_gpu, N * sizeof(float));
// Sadece CPU tarafindan ulasilabilen memory ayirtalim
x_cpu = new float[N];
y_cpu = new float[N];
z_cpu = new float[N];
//
for (int i = 0; i < N; ++i) {
x_gpu[i] = 1.0f;
y_gpu[i] = 2.0f;
x_cpu[i] = 1.0f;
y_cpu[i] = 2.0f;
}
// Fonksiyonu GPU'da argv[1] blokta ve her blokta argv[2] thread
// olacak sekilde çagiralım
int blok_sayisi = atoi(argv[1]);
int thread_sayisi = atoi(argv[2]);
carp_cuda<<<blok_sayisi, thread_sayisi>>>(N, x_gpu, y_gpu, z_gpu);
// GPU'yu bekleyelim de isini bitirsin, yoksa ortam karisir.
hipDeviceSynchronize();
// Normal CPU fonlsiyonunu çagiralım
carp(N, x_cpu, y_cpu, z_cpu);
// Bakalim dogru mu yaptik?
// z_gpu ve z_cpu ayni degerlere sahip olması lazim
for(int i = 0; i < N; ++i)
cout << z_cpu[i] << " " << z_gpu[i] << endl;
// Release the Kraken - Kraken'i saliverin gelsin.
hipFree(x_gpu);
hipFree(y_gpu);
hipFree(z_gpu);
delete [] x_cpu;
delete [] y_cpu;
delete [] z_cpu;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9carp_cudaiPfS_S_
.globl _Z9carp_cudaiPfS_S_
.p2align 8
.type _Z9carp_cudaiPfS_S_,@function
_Z9carp_cudaiPfS_S_:
s_load_b32 s8, s[0:1], 0x0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_u32 v1, s0, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9carp_cudaiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9carp_cudaiPfS_S_, .Lfunc_end0-_Z9carp_cudaiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9carp_cudaiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z9carp_cudaiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <numeric>
#include <cstdlib>
// Kolaylık olsun
using namespace std;
// Tipik bir C++ fonksiyonu
void carp(int n, float *x, float *y, float *z)
{
for (int i = 0; i < n; i++)
{
z[i] = x[i] * y[i];
}
}
// Ustteki fonksiyonun CUDA versiyonu
__global__
void carp_cuda(int n, float *x, float *y, float *z)
{
for (int i = threadIdx.x; i < n; i += blockDim.x)
{
z[i] = x[i] * y[i];
}
}
int main(int argc, char *argv[])
{
// Çok büyük bir sayı belirleyelim
int N = 10000;
float *x_gpu, *y_gpu, *z_gpu, *x_cpu, *y_cpu, *z_cpu;
// GPU ve CPU tarafindan ulasilabilen memory ayirtalim
hipMallocManaged(&x_gpu, N * sizeof(float));
hipMallocManaged(&y_gpu, N * sizeof(float));
hipMallocManaged(&z_gpu, N * sizeof(float));
// Sadece CPU tarafindan ulasilabilen memory ayirtalim
x_cpu = new float[N];
y_cpu = new float[N];
z_cpu = new float[N];
//
for (int i = 0; i < N; ++i) {
x_gpu[i] = 1.0f;
y_gpu[i] = 2.0f;
x_cpu[i] = 1.0f;
y_cpu[i] = 2.0f;
}
// Fonksiyonu GPU'da argv[1] blokta ve her blokta argv[2] thread
// olacak sekilde çagiralım
int blok_sayisi = atoi(argv[1]);
int thread_sayisi = atoi(argv[2]);
carp_cuda<<<blok_sayisi, thread_sayisi>>>(N, x_gpu, y_gpu, z_gpu);
// GPU'yu bekleyelim de isini bitirsin, yoksa ortam karisir.
hipDeviceSynchronize();
// Normal CPU fonlsiyonunu çagiralım
carp(N, x_cpu, y_cpu, z_cpu);
// Bakalim dogru mu yaptik?
// z_gpu ve z_cpu ayni degerlere sahip olması lazim
for(int i = 0; i < N; ++i)
cout << z_cpu[i] << " " << z_gpu[i] << endl;
// Release the Kraken - Kraken'i saliverin gelsin.
hipFree(x_gpu);
hipFree(y_gpu);
hipFree(z_gpu);
delete [] x_cpu;
delete [] y_cpu;
delete [] z_cpu;
return 0;
} | .text
.file "cuda_ornek.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z4carpiPfS_S_ # -- Begin function _Z4carpiPfS_S_
.p2align 4, 0x90
.type _Z4carpiPfS_S_,@function
_Z4carpiPfS_S_: # @_Z4carpiPfS_S_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %edi, %edi
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdx,%rdi,4), %xmm0
movss %xmm0, (%rcx,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z4carpiPfS_S_, .Lfunc_end0-_Z4carpiPfS_S_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__carp_cudaiPfS_S_ # -- Begin function _Z24__device_stub__carp_cudaiPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__carp_cudaiPfS_S_,@function
_Z24__device_stub__carp_cudaiPfS_S_: # @_Z24__device_stub__carp_cudaiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9carp_cudaiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__carp_cudaiPfS_S_, .Lfunc_end1-_Z24__device_stub__carp_cudaiPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
movl $40000, %edi # imm = 0x9C40
callq _Znam
movq %rax, %rbx
movl $40000, %edi # imm = 0x9C40
callq _Znam
movq %rax, %r14
movl $40000, %edi # imm = 0x9C40
callq _Znam
movq %rax, %r15
movq 24(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
movl $1065353216, (%rbx,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $10000, %rcx # imm = 0x2710
jne .LBB2_1
# %bb.2:
movq 8(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %r13d, %edi
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rdi
movl %eax, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $10000, 36(%rsp) # imm = 0x2710
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9carp_cudaiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB2_5
# %bb.6: # %_Z4carpiPfS_S_.exit.preheader.preheader
xorl %r13d, %r13d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_7 Depth=1
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_7 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpq $10000, %r13 # imm = 0x2710
je .LBB2_12
.LBB2_7: # %_Z4carpiPfS_S_.exit.preheader
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rax
movss (%rax,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_7 Depth=1
cmpb $0, 56(%r12)
je .LBB2_10
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_11
.LBB2_12:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9carp_cudaiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9carp_cudaiPfS_S_,@object # @_Z9carp_cudaiPfS_S_
.section .rodata,"a",@progbits
.globl _Z9carp_cudaiPfS_S_
.p2align 3, 0x0
_Z9carp_cudaiPfS_S_:
.quad _Z24__device_stub__carp_cudaiPfS_S_
.size _Z9carp_cudaiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9carp_cudaiPfS_S_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__carp_cudaiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9carp_cudaiPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9carp_cudaiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x178] ; /* 0x00005e0000067625 */
/* 0x040fe200078e0207 */
/*00b0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fe20003f06270 */
/*00d0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*00f0*/ @!P0 BRA 0x40 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9carp_cudaiPfS_S_
.globl _Z9carp_cudaiPfS_S_
.p2align 8
.type _Z9carp_cudaiPfS_S_,@function
_Z9carp_cudaiPfS_S_:
s_load_b32 s8, s[0:1], 0x0
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s9, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s9, 0xffff
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v2, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_u32 v1, s0, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s3, v2, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9carp_cudaiPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9carp_cudaiPfS_S_, .Lfunc_end0-_Z9carp_cudaiPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9carp_cudaiPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z9carp_cudaiPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005661b_00000000-6_cuda_ornek.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3712:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4carpiPfS_S_
.type _Z4carpiPfS_S_, @function
_Z4carpiPfS_S_:
.LFB3708:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
salq $2, %rdi
movl $0, %eax
.L5:
movss (%rsi,%rax), %xmm0
mulss (%rdx,%rax), %xmm0
movss %xmm0, (%rcx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3708:
.size _Z4carpiPfS_S_, .-_Z4carpiPfS_S_
.globl _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_
.type _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_, @function
_Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_:
.LFB3734:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9carp_cudaiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3734:
.size _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_, .-_Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_
.globl _Z9carp_cudaiPfS_S_
.type _Z9carp_cudaiPfS_S_, @function
_Z9carp_cudaiPfS_S_:
.LFB3735:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3735:
.size _Z9carp_cudaiPfS_S_, .-_Z9carp_cudaiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " "
.text
.globl main
.type main, @function
main:
.LFB3709:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $40000, %esi
call cudaMallocManaged@PLT
movl $40000, %edi
call _Znam@PLT
movq %rax, %r14
movl $40000, %edi
call _Znam@PLT
movq %rax, %r13
movl $40000, %edi
call _Znam@PLT
movq %rax, %r15
movl $0, %eax
movss .LC0(%rip), %xmm1
movss .LC1(%rip), %xmm0
.L16:
movq 8(%rsp), %rdx
movss %xmm1, (%rdx,%rax)
movq 16(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movss %xmm1, (%r14,%rax)
movss %xmm0, 0(%r13,%rax)
addq $4, %rax
cmpq $40000, %rax
jne .L16
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl %ebp, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L27
.L17:
call cudaDeviceSynchronize@PLT
movq %r15, %rcx
movq %r13, %rdx
movq %r14, %rsi
movl $10000, %edi
call _Z4carpiPfS_S_
movl $0, %ebp
jmp .L22
.L27:
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movl $10000, %edi
call _Z33__device_stub__Z9carp_cudaiPfS_S_iPfS_S_
jmp .L17
.L30:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L28
call _ZSt16__throw_bad_castv@PLT
.L28:
call __stack_chk_fail@PLT
.L20:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L21:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %rbp
cmpq $40000, %rbp
je .L29
.L22:
pxor %xmm0, %xmm0
cvtss2sd (%r15,%rbp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq 24(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbp), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L30
cmpb $0, 56(%r12)
je .L20
movzbl 67(%r12), %esi
jmp .L21
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call _ZdaPv@PLT
movq %r13, %rdi
call _ZdaPv@PLT
movq %r15, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L31
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3709:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z9carp_cudaiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3737:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9carp_cudaiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3737:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.align 4
.LC1:
.long 1073741824
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_ornek.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z4carpiPfS_S_ # -- Begin function _Z4carpiPfS_S_
.p2align 4, 0x90
.type _Z4carpiPfS_S_,@function
_Z4carpiPfS_S_: # @_Z4carpiPfS_S_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %edi, %edi
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rdi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%rdx,%rdi,4), %xmm0
movss %xmm0, (%rcx,%rdi,4)
incq %rdi
cmpq %rdi, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z4carpiPfS_S_, .Lfunc_end0-_Z4carpiPfS_S_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__carp_cudaiPfS_S_ # -- Begin function _Z24__device_stub__carp_cudaiPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__carp_cudaiPfS_S_,@function
_Z24__device_stub__carp_cudaiPfS_S_: # @_Z24__device_stub__carp_cudaiPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9carp_cudaiPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__carp_cudaiPfS_S_, .Lfunc_end1-_Z24__device_stub__carp_cudaiPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
leaq 24(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
movl $1, %edx
callq hipMallocManaged
movl $40000, %edi # imm = 0x9C40
callq _Znam
movq %rax, %rbx
movl $40000, %edi # imm = 0x9C40
callq _Znam
movq %rax, %r14
movl $40000, %edi # imm = 0x9C40
callq _Znam
movq %rax, %r15
movq 24(%rsp), %rax
xorl %ecx, %ecx
movq 16(%rsp), %rdx
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rax,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%rdx,%rcx,4) # imm = 0x40000000
movl $1065353216, (%rbx,%rcx,4) # imm = 0x3F800000
movl $1073741824, (%r14,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $10000, %rcx # imm = 0x2710
jne .LBB2_1
# %bb.2:
movq 8(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r13
movq 16(%r12), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %r13d, %edi
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rdi
movl %eax, %edx
orq %rcx, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movl $10000, 36(%rsp) # imm = 0x2710
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 104(%rsp), %rax
movq %rax, 120(%rsp)
leaq 96(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9carp_cudaiPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r14,%rax,4), %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $10000, %rax # imm = 0x2710
jne .LBB2_5
# %bb.6: # %_Z4carpiPfS_S_.exit.preheader.preheader
xorl %r13d, %r13d
jmp .LBB2_7
.p2align 4, 0x90
.LBB2_10: # in Loop: Header=BB2_7 Depth=1
movq %r12, %rdi
movq %rax, %rbp
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %rbp, %rax
.LBB2_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_7 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r13
cmpq $10000, %r13 # imm = 0x2710
je .LBB2_12
.LBB2_7: # %_Z4carpiPfS_S_.exit.preheader
# =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 8(%rsp), %rax
movss (%rax,%r13,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_7 Depth=1
cmpb $0, 56(%r12)
je .LBB2_10
# %bb.9: # in Loop: Header=BB2_7 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB2_11
.LBB2_12:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_13:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9carp_cudaiPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9carp_cudaiPfS_S_,@object # @_Z9carp_cudaiPfS_S_
.section .rodata,"a",@progbits
.globl _Z9carp_cudaiPfS_S_
.p2align 3, 0x0
_Z9carp_cudaiPfS_S_:
.quad _Z24__device_stub__carp_cudaiPfS_S_
.size _Z9carp_cudaiPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9carp_cudaiPfS_S_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__carp_cudaiPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9carp_cudaiPfS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* This code is courtesy of, and copyright 2015,
* Tomas Oppelstrup, Livermore National Lab. Please
* do not redistribute without his approval.
*/
#define NTHREADS_RADIX 128
#define NBLOCKS_RADIX 56
__global__ static void
boxsum_stage1(int nc,int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i;
for(i = pid; i<nc; i+=np)
count[i] = 0;
}
__global__ static void
boxsum_stage2(int n,int v[],int listid[],int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i,vi,x;
volatile __shared__ struct { int vi[NTHREADS_RADIX],x[NTHREADS_RADIX]; } shm;
if(0) {
for(i = pid; i<n; i+=np) {
// Compute index within box.
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
} else {
for(i = pid; i<n+tid; i+=np) {
// Compute index within box.
if(n-(i-tid) < nt) {
if(i < n) {
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
} else {
shm.vi[tid] = v[i];
__syncthreads();
// Requirement is that gcd(11,nt) = 1
shm.x[(19*tid)%nt] = atomicAdd(&count[shm.vi[(19*tid)%nt]],1);
__syncthreads();
listid[i] = shm.x[tid];
}
}
/*
int i0,i1;
{
int q = n/np;
int r = n%np;
if(pid >= r) { i0 = q*pid + r; i1 = i0 + q; }
else { i0 = q*pid + pid; i1 = i0 + q + 1; }
}
for(i = i0; i<i1; i++) {
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
*/
}
}
__global__ static void
boxsum_stage3(int nboxes,int count[],int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i,x;
volatile __shared__ struct { int x[NTHREADS_RADIX]; } shm;
for(i = pid; i<nboxes+tid; i+=np) {
__syncthreads();
x = 0;
if(i < nboxes) x = count[i];
shm.x[tid] = x;
__syncthreads();
if(tid < 64) shm.x[tid] += shm.x[tid+64];
__syncthreads();
if(tid < 32) {
shm.x[tid] += shm.x[tid+32];
shm.x[tid] += shm.x[tid+16];
shm.x[tid] += shm.x[tid+ 8];
shm.x[tid] += shm.x[tid+ 4];
shm.x[tid] += shm.x[tid+ 2];
shm.x[tid] += shm.x[tid+ 1];
}
if(tid == 0) psum[i/nt] = shm.x[0];
}
}
__global__ static void
boxsum_stage4(int n,int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x;
int i,j,x,s;
volatile __shared__ int xshare[NTHREADS_RADIX];
s = 0;
if(bid == 0)
for(i = tid; i<n+tid; i+=nt) {
__syncthreads();
x = 0;
if(i < n) x = psum[i];
xshare[tid] = x;
__syncthreads();
// Make cumulative summation of columns in type!
j = 1;
while(j < nt) {
if(tid >= j) x += xshare[tid-j];
__syncthreads();
xshare[tid] = x;
j = j*2;
__syncthreads();
}
if(i < n) psum[i] = xshare[tid] + s;
s = s + xshare[nt-1];
}
}
__global__ static void
boxsum_stage5(int nboxes,int count[],int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,x,x1;
volatile __shared__ struct {
int psum,x[2][NTHREADS_RADIX],y[2][NTHREADS_RADIX];
} shm;
shm.x[0][tid] = 0;
shm.y[0][tid] = 0;
for(i = pid; i<nboxes+tid; i+=np) {
__syncthreads();
if(tid == 0) shm.psum = psum[i/nt];
x = 0;
if(i < nboxes) x = count[i];
x1 = x;
shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid- 1]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid- 2]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid- 4]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid- 8]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid-16]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid-32]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid-64]; shm.y[1][tid] = x; __syncthreads();
x += shm.psum - shm.y[1][nt-1];
//if(i == nboxes-1) { x=0; x1=0; }
if(i < nboxes) count[i] = x-x1;
}
}
__global__ static void
boxsum_stage6(int n,int v[],int listid[],int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,lid,bno,idx;
for(i = pid; i<n; i+=np) {
lid = listid[i];
bno = v[i];
idx = 0;
if(bno > 0) idx = count[bno];
listid[i] = lid + idx;
}
}
__global__ static void
boxsum_stage7(int n,int listid[],int bin[],float xx[][4], float vv[][4],
int bout[],float xxout[][4], float vvout[][4]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,j,xend;
float x,v;
volatile __shared__ struct { int idx[NTHREADS_RADIX]; } shm;
for(i = pid; i<n+tid; i+=np) {
j = 0;
if(i < n) j = listid[i];
xend = min(nt,n-(i-tid));
__syncthreads();
shm.idx[tid] = j;
__syncthreads();
if(i < n) bout[j] = bin[i];
for(j = tid; j<4*xend; j+=nt) {
x = xx[i-tid][j];
v = vv[i-tid][j];
xxout[shm.idx[j/4]][j%4] = x;
vvout[shm.idx[j/4]][j%4] = v;
}
}
}
void rsort_card(int n,int nc,
int *xin_g,float (*data1in_g)[4],float (*data2in_g)[4],
int *xout_g,float (*data1out_g)[4],float (*data2out_g)[4],
int *count_g) {
static int n_init = 0, nc_init = 0;
static int *psum_g,*listid_g;
int ns = (nc+NTHREADS_RADIX-1)/NTHREADS_RADIX;
if(n <= 0 || nc <= 0) {
if(n_init > 0) {
cudaFree(listid_g);
cudaFree(psum_g);
}
n_init = 0;
nc_init = 0;
} else if(n > n_init || nc > nc_init) {
if(n_init > 0) {
cudaFree(listid_g);
cudaFree(psum_g);
}
cudaMalloc((void **) &psum_g,sizeof(int) * ns);
cudaMalloc((void **) &listid_g,sizeof(int) * n);
n_init = n;
nc_init = nc;
}
if(n > 0 && nc > 0) {
/*
int *listid = (int *) malloc(sizeof(int) * n);
int *count = (int *) malloc(sizeof(int) * nc);
int *count2 = (int *) malloc(sizeof(int) * nc);
int *psum = (int *) malloc(sizeof(int) * ns);
int *psum2 = (int *) malloc(sizeof(int) * ns);
int i,s;
*/
boxsum_stage1<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g);
/*
cudaThreadSynchronize();
s = 0;
for(i = 0; i<nc; i++)
s += abs(count[i]);
if(s != 0)
printf("count not zeroed, s=%d\n",s);
*/
boxsum_stage2<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
/*
cudaThreadSynchronize();
cudaMemcpy(listid,listid_g,sizeof(int) * n,cudaMemcpyDeviceToHost);
cudaMemcpy(count,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<nc; i++)
s += count[i];
if(s != n)
printf("Error in count, s=%d, n=%d\n",s,n);
*/
boxsum_stage3<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(psum,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);
for(i = 0; i<ns; i++) {
int j;
s = 0;
for(j = 0; j<NTHREADS_RADIX; j++)
if(i*NTHREADS_RADIX+j < nc) s += count[i*NTHREADS_RADIX+j];
if(s != psum[i])
printf("psum error, i=%d ns=%d s=%d psum=%d\n",i,ns,s,psum[i]);
}
*/
boxsum_stage4<<<1,NTHREADS_RADIX>>>(ns,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(psum2,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<ns; i++) {
s += psum[i];
if(s != psum2[i])
printf("cumsum error in psum: s=%d psum2=%d i=%d ns=%d\n",
s,psum2[i],i,ns);
}
*/
boxsum_stage5<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(count2,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<nc; i++) {
s += count[i];
if(s != count2[i])
printf("cumsum error in count: s=%d count2=%d i=%d nc=%d\n",
s,count2[i],i,nc);
}
*/
boxsum_stage6<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
boxsum_stage7<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,listid_g,xin_g,
data1in_g,data2in_g,xout_g,
data1out_g,data2out_g);
}
} | .file "tmpxft_0011fc9e_00000000-6_boxsortinc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL34__device_stub__Z13boxsum_stage1iPiiPi, @function
_ZL34__device_stub__Z13boxsum_stage1iPiiPi:
.LFB2052:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL13boxsum_stage1iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL34__device_stub__Z13boxsum_stage1iPiiPi, .-_ZL34__device_stub__Z13boxsum_stage1iPiiPi
.type _ZL13boxsum_stage1iPi, @function
_ZL13boxsum_stage1iPi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z13boxsum_stage1iPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL13boxsum_stage1iPi, .-_ZL13boxsum_stage1iPi
.type _ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_, @function
_ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_:
.LFB2054:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL13boxsum_stage2iPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_, .-_ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_
.type _ZL13boxsum_stage2iPiS_S_, @function
_ZL13boxsum_stage2iPiS_S_:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL13boxsum_stage2iPiS_S_, .-_ZL13boxsum_stage2iPiS_S_
.type _ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_, @function
_ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_:
.LFB2056:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL13boxsum_stage3iPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_, .-_ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_
.type _ZL13boxsum_stage3iPiS_, @function
_ZL13boxsum_stage3iPiS_:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL13boxsum_stage3iPiS_, .-_ZL13boxsum_stage3iPiS_
.type _ZL34__device_stub__Z13boxsum_stage4iPiiPi, @function
_ZL34__device_stub__Z13boxsum_stage4iPiiPi:
.LFB2058:
.cfi_startproc
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL13boxsum_stage4iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _ZL34__device_stub__Z13boxsum_stage4iPiiPi, .-_ZL34__device_stub__Z13boxsum_stage4iPiiPi
.type _ZL13boxsum_stage4iPi, @function
_ZL13boxsum_stage4iPi:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL34__device_stub__Z13boxsum_stage4iPiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL13boxsum_stage4iPi, .-_ZL13boxsum_stage4iPi
.type _ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_, @function
_ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_:
.LFB2060:
.cfi_startproc
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL13boxsum_stage5iPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_, .-_ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_
.type _ZL13boxsum_stage5iPiS_, @function
_ZL13boxsum_stage5iPiS_:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL13boxsum_stage5iPiS_, .-_ZL13boxsum_stage5iPiS_
.type _ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_, @function
_ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_:
.LFB2062:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL13boxsum_stage6iPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_, .-_ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_
.type _ZL13boxsum_stage6iPiS_S_, @function
_ZL13boxsum_stage6iPiS_S_:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL13boxsum_stage6iPiS_S_, .-_ZL13boxsum_stage6iPiS_S_
.type _ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_, @function
_ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_:
.LFB2064:
.cfi_startproc
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq 232(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_, .-_ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_
.type _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, @function
_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 24(%rsp)
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, .-_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
.type _Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_, @function
_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movl %esi, %ebx
movq %rdx, %r13
movq %rcx, 8(%rsp)
movq %r8, %r14
movq %r9, %r15
leal 254(%rsi), %r12d
movl %esi, %eax
addl $127, %eax
cmovns %eax, %r12d
sarl $7, %r12d
testl %edi, %edi
jle .L77
testl %esi, %esi
jle .L77
movl _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip), %eax
cmpl %edi, %eax
jl .L66
cmpl %esi, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
jge .L63
.L67:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
call cudaFree@PLT
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
call cudaFree@PLT
jmp .L69
.L77:
cmpl $0, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip)
jg .L79
.L62:
movl $0, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip)
movl $0, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
testl %ebp, %ebp
jle .L59
testl %ebx, %ebx
jg .L63
.L59:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
call cudaFree@PLT
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
call cudaFree@PLT
jmp .L62
.L66:
testl %eax, %eax
jg .L67
.L69:
movslq %r12d, %rsi
salq $2, %rsi
leaq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
call cudaMalloc@PLT
movslq %ebp, %rsi
salq $2, %rsi
leaq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
call cudaMalloc@PLT
movl %ebp, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip)
movl %ebx, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
.L63:
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $56, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L70:
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $56, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L81
.L71:
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $56, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L82
.L72:
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L83
.L73:
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $56, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L84
.L74:
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $56, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L85
.L75:
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $56, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L59
pushq 120(%rsp)
.cfi_def_cfa_offset 120
pushq 120(%rsp)
.cfi_def_cfa_offset 128
movq %r15, %r9
movq %r14, %r8
movq 24(%rsp), %rcx
movq %r13, %rdx
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rsi
movl %ebp, %edi
call _ZL52__device_stub__Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_iPiS_PA4_fS1_S_S1_S1_
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L59
.L80:
movq 128(%rsp), %rsi
movl %ebx, %edi
call _ZL34__device_stub__Z13boxsum_stage1iPiiPi
jmp .L70
.L81:
movq 128(%rsp), %rcx
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdx
movq %r13, %rsi
movl %ebp, %edi
call _ZL38__device_stub__Z13boxsum_stage2iPiS_S_iPiS_S_
jmp .L71
.L82:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdx
movq 128(%rsp), %rsi
movl %ebx, %edi
call _ZL36__device_stub__Z13boxsum_stage3iPiS_iPiS_
jmp .L72
.L83:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rsi
movl %r12d, %edi
call _ZL34__device_stub__Z13boxsum_stage4iPiiPi
jmp .L73
.L84:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdx
movq 128(%rsp), %rsi
movl %ebx, %edi
call _ZL36__device_stub__Z13boxsum_stage5iPiS_iPiS_
jmp .L74
.L85:
movq 128(%rsp), %rcx
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdx
movq %r13, %rsi
movl %ebp, %edi
call _ZL38__device_stub__Z13boxsum_stage6iPiS_S_iPiS_S_
jmp .L75
.cfi_endproc
.LFE2027:
.size _Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_, .-_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13boxsum_stage6iPiS_S_"
.LC2:
.string "_Z13boxsum_stage5iPiS_"
.LC3:
.string "_Z13boxsum_stage4iPi"
.LC4:
.string "_Z13boxsum_stage3iPiS_"
.LC5:
.string "_Z13boxsum_stage2iPiS_S_"
.LC6:
.string "_Z13boxsum_stage1iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13boxsum_stage6iPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13boxsum_stage5iPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13boxsum_stage4iPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13boxsum_stage3iPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13boxsum_stage2iPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13boxsum_stage1iPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g
.comm _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g,8,8
.local _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g
.comm _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g,8,8
.local _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init
.comm _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init,4,4
.local _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init
.comm _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* This code is courtesy of, and copyright 2015,
* Tomas Oppelstrup, Livermore National Lab. Please
* do not redistribute without his approval.
*/
#define NTHREADS_RADIX 128
#define NBLOCKS_RADIX 56
__global__ static void
boxsum_stage1(int nc,int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i;
for(i = pid; i<nc; i+=np)
count[i] = 0;
}
__global__ static void
boxsum_stage2(int n,int v[],int listid[],int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i,vi,x;
volatile __shared__ struct { int vi[NTHREADS_RADIX],x[NTHREADS_RADIX]; } shm;
if(0) {
for(i = pid; i<n; i+=np) {
// Compute index within box.
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
} else {
for(i = pid; i<n+tid; i+=np) {
// Compute index within box.
if(n-(i-tid) < nt) {
if(i < n) {
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
} else {
shm.vi[tid] = v[i];
__syncthreads();
// Requirement is that gcd(11,nt) = 1
shm.x[(19*tid)%nt] = atomicAdd(&count[shm.vi[(19*tid)%nt]],1);
__syncthreads();
listid[i] = shm.x[tid];
}
}
/*
int i0,i1;
{
int q = n/np;
int r = n%np;
if(pid >= r) { i0 = q*pid + r; i1 = i0 + q; }
else { i0 = q*pid + pid; i1 = i0 + q + 1; }
}
for(i = i0; i<i1; i++) {
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
*/
}
}
__global__ static void
boxsum_stage3(int nboxes,int count[],int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i,x;
volatile __shared__ struct { int x[NTHREADS_RADIX]; } shm;
for(i = pid; i<nboxes+tid; i+=np) {
__syncthreads();
x = 0;
if(i < nboxes) x = count[i];
shm.x[tid] = x;
__syncthreads();
if(tid < 64) shm.x[tid] += shm.x[tid+64];
__syncthreads();
if(tid < 32) {
shm.x[tid] += shm.x[tid+32];
shm.x[tid] += shm.x[tid+16];
shm.x[tid] += shm.x[tid+ 8];
shm.x[tid] += shm.x[tid+ 4];
shm.x[tid] += shm.x[tid+ 2];
shm.x[tid] += shm.x[tid+ 1];
}
if(tid == 0) psum[i/nt] = shm.x[0];
}
}
__global__ static void
boxsum_stage4(int n,int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x;
int i,j,x,s;
volatile __shared__ int xshare[NTHREADS_RADIX];
s = 0;
if(bid == 0)
for(i = tid; i<n+tid; i+=nt) {
__syncthreads();
x = 0;
if(i < n) x = psum[i];
xshare[tid] = x;
__syncthreads();
// Make cumulative summation of columns in type!
j = 1;
while(j < nt) {
if(tid >= j) x += xshare[tid-j];
__syncthreads();
xshare[tid] = x;
j = j*2;
__syncthreads();
}
if(i < n) psum[i] = xshare[tid] + s;
s = s + xshare[nt-1];
}
}
__global__ static void
boxsum_stage5(int nboxes,int count[],int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,x,x1;
volatile __shared__ struct {
int psum,x[2][NTHREADS_RADIX],y[2][NTHREADS_RADIX];
} shm;
shm.x[0][tid] = 0;
shm.y[0][tid] = 0;
for(i = pid; i<nboxes+tid; i+=np) {
__syncthreads();
if(tid == 0) shm.psum = psum[i/nt];
x = 0;
if(i < nboxes) x = count[i];
x1 = x;
shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid- 1]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid- 2]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid- 4]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid- 8]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid-16]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid-32]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid-64]; shm.y[1][tid] = x; __syncthreads();
x += shm.psum - shm.y[1][nt-1];
//if(i == nboxes-1) { x=0; x1=0; }
if(i < nboxes) count[i] = x-x1;
}
}
__global__ static void
boxsum_stage6(int n,int v[],int listid[],int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,lid,bno,idx;
for(i = pid; i<n; i+=np) {
lid = listid[i];
bno = v[i];
idx = 0;
if(bno > 0) idx = count[bno];
listid[i] = lid + idx;
}
}
__global__ static void
boxsum_stage7(int n,int listid[],int bin[],float xx[][4], float vv[][4],
int bout[],float xxout[][4], float vvout[][4]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,j,xend;
float x,v;
volatile __shared__ struct { int idx[NTHREADS_RADIX]; } shm;
for(i = pid; i<n+tid; i+=np) {
j = 0;
if(i < n) j = listid[i];
xend = min(nt,n-(i-tid));
__syncthreads();
shm.idx[tid] = j;
__syncthreads();
if(i < n) bout[j] = bin[i];
for(j = tid; j<4*xend; j+=nt) {
x = xx[i-tid][j];
v = vv[i-tid][j];
xxout[shm.idx[j/4]][j%4] = x;
vvout[shm.idx[j/4]][j%4] = v;
}
}
}
void rsort_card(int n,int nc,
int *xin_g,float (*data1in_g)[4],float (*data2in_g)[4],
int *xout_g,float (*data1out_g)[4],float (*data2out_g)[4],
int *count_g) {
static int n_init = 0, nc_init = 0;
static int *psum_g,*listid_g;
int ns = (nc+NTHREADS_RADIX-1)/NTHREADS_RADIX;
if(n <= 0 || nc <= 0) {
if(n_init > 0) {
cudaFree(listid_g);
cudaFree(psum_g);
}
n_init = 0;
nc_init = 0;
} else if(n > n_init || nc > nc_init) {
if(n_init > 0) {
cudaFree(listid_g);
cudaFree(psum_g);
}
cudaMalloc((void **) &psum_g,sizeof(int) * ns);
cudaMalloc((void **) &listid_g,sizeof(int) * n);
n_init = n;
nc_init = nc;
}
if(n > 0 && nc > 0) {
/*
int *listid = (int *) malloc(sizeof(int) * n);
int *count = (int *) malloc(sizeof(int) * nc);
int *count2 = (int *) malloc(sizeof(int) * nc);
int *psum = (int *) malloc(sizeof(int) * ns);
int *psum2 = (int *) malloc(sizeof(int) * ns);
int i,s;
*/
boxsum_stage1<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g);
/*
cudaThreadSynchronize();
s = 0;
for(i = 0; i<nc; i++)
s += abs(count[i]);
if(s != 0)
printf("count not zeroed, s=%d\n",s);
*/
boxsum_stage2<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
/*
cudaThreadSynchronize();
cudaMemcpy(listid,listid_g,sizeof(int) * n,cudaMemcpyDeviceToHost);
cudaMemcpy(count,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<nc; i++)
s += count[i];
if(s != n)
printf("Error in count, s=%d, n=%d\n",s,n);
*/
boxsum_stage3<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(psum,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);
for(i = 0; i<ns; i++) {
int j;
s = 0;
for(j = 0; j<NTHREADS_RADIX; j++)
if(i*NTHREADS_RADIX+j < nc) s += count[i*NTHREADS_RADIX+j];
if(s != psum[i])
printf("psum error, i=%d ns=%d s=%d psum=%d\n",i,ns,s,psum[i]);
}
*/
boxsum_stage4<<<1,NTHREADS_RADIX>>>(ns,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(psum2,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<ns; i++) {
s += psum[i];
if(s != psum2[i])
printf("cumsum error in psum: s=%d psum2=%d i=%d ns=%d\n",
s,psum2[i],i,ns);
}
*/
boxsum_stage5<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(count2,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<nc; i++) {
s += count[i];
if(s != count2[i])
printf("cumsum error in count: s=%d count2=%d i=%d nc=%d\n",
s,count2[i],i,nc);
}
*/
boxsum_stage6<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
boxsum_stage7<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,listid_g,xin_g,
data1in_g,data2in_g,xout_g,
data1out_g,data2out_g);
}
} | #include <hip/hip_runtime.h>
/*
* This code is courtesy of, and copyright 2015,
* Tomas Oppelstrup, Livermore National Lab. Please
* do not redistribute without his approval.
*/
#define NTHREADS_RADIX 128
#define NBLOCKS_RADIX 56
__global__ static void
boxsum_stage1(int nc,int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i;
for(i = pid; i<nc; i+=np)
count[i] = 0;
}
__global__ static void
boxsum_stage2(int n,int v[],int listid[],int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i,vi,x;
volatile __shared__ struct { int vi[NTHREADS_RADIX],x[NTHREADS_RADIX]; } shm;
if(0) {
for(i = pid; i<n; i+=np) {
// Compute index within box.
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
} else {
for(i = pid; i<n+tid; i+=np) {
// Compute index within box.
if(n-(i-tid) < nt) {
if(i < n) {
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
} else {
shm.vi[tid] = v[i];
__syncthreads();
// Requirement is that gcd(11,nt) = 1
shm.x[(19*tid)%nt] = atomicAdd(&count[shm.vi[(19*tid)%nt]],1);
__syncthreads();
listid[i] = shm.x[tid];
}
}
/*
int i0,i1;
{
int q = n/np;
int r = n%np;
if(pid >= r) { i0 = q*pid + r; i1 = i0 + q; }
else { i0 = q*pid + pid; i1 = i0 + q + 1; }
}
for(i = i0; i<i1; i++) {
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
*/
}
}
__global__ static void
boxsum_stage3(int nboxes,int count[],int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i,x;
volatile __shared__ struct { int x[NTHREADS_RADIX]; } shm;
for(i = pid; i<nboxes+tid; i+=np) {
__syncthreads();
x = 0;
if(i < nboxes) x = count[i];
shm.x[tid] = x;
__syncthreads();
if(tid < 64) shm.x[tid] += shm.x[tid+64];
__syncthreads();
if(tid < 32) {
shm.x[tid] += shm.x[tid+32];
shm.x[tid] += shm.x[tid+16];
shm.x[tid] += shm.x[tid+ 8];
shm.x[tid] += shm.x[tid+ 4];
shm.x[tid] += shm.x[tid+ 2];
shm.x[tid] += shm.x[tid+ 1];
}
if(tid == 0) psum[i/nt] = shm.x[0];
}
}
__global__ static void
boxsum_stage4(int n,int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x;
int i,j,x,s;
volatile __shared__ int xshare[NTHREADS_RADIX];
s = 0;
if(bid == 0)
for(i = tid; i<n+tid; i+=nt) {
__syncthreads();
x = 0;
if(i < n) x = psum[i];
xshare[tid] = x;
__syncthreads();
// Make cumulative summation of columns in type!
j = 1;
while(j < nt) {
if(tid >= j) x += xshare[tid-j];
__syncthreads();
xshare[tid] = x;
j = j*2;
__syncthreads();
}
if(i < n) psum[i] = xshare[tid] + s;
s = s + xshare[nt-1];
}
}
__global__ static void
boxsum_stage5(int nboxes,int count[],int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,x,x1;
volatile __shared__ struct {
int psum,x[2][NTHREADS_RADIX],y[2][NTHREADS_RADIX];
} shm;
shm.x[0][tid] = 0;
shm.y[0][tid] = 0;
for(i = pid; i<nboxes+tid; i+=np) {
__syncthreads();
if(tid == 0) shm.psum = psum[i/nt];
x = 0;
if(i < nboxes) x = count[i];
x1 = x;
shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid- 1]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid- 2]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid- 4]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid- 8]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid-16]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid-32]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid-64]; shm.y[1][tid] = x; __syncthreads();
x += shm.psum - shm.y[1][nt-1];
//if(i == nboxes-1) { x=0; x1=0; }
if(i < nboxes) count[i] = x-x1;
}
}
__global__ static void
boxsum_stage6(int n,int v[],int listid[],int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,lid,bno,idx;
for(i = pid; i<n; i+=np) {
lid = listid[i];
bno = v[i];
idx = 0;
if(bno > 0) idx = count[bno];
listid[i] = lid + idx;
}
}
__global__ static void
boxsum_stage7(int n,int listid[],int bin[],float xx[][4], float vv[][4],
int bout[],float xxout[][4], float vvout[][4]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,j,xend;
float x,v;
volatile __shared__ struct { int idx[NTHREADS_RADIX]; } shm;
for(i = pid; i<n+tid; i+=np) {
j = 0;
if(i < n) j = listid[i];
xend = min(nt,n-(i-tid));
__syncthreads();
shm.idx[tid] = j;
__syncthreads();
if(i < n) bout[j] = bin[i];
for(j = tid; j<4*xend; j+=nt) {
x = xx[i-tid][j];
v = vv[i-tid][j];
xxout[shm.idx[j/4]][j%4] = x;
vvout[shm.idx[j/4]][j%4] = v;
}
}
}
void rsort_card(int n,int nc,
int *xin_g,float (*data1in_g)[4],float (*data2in_g)[4],
int *xout_g,float (*data1out_g)[4],float (*data2out_g)[4],
int *count_g) {
static int n_init = 0, nc_init = 0;
static int *psum_g,*listid_g;
int ns = (nc+NTHREADS_RADIX-1)/NTHREADS_RADIX;
if(n <= 0 || nc <= 0) {
if(n_init > 0) {
hipFree(listid_g);
hipFree(psum_g);
}
n_init = 0;
nc_init = 0;
} else if(n > n_init || nc > nc_init) {
if(n_init > 0) {
hipFree(listid_g);
hipFree(psum_g);
}
hipMalloc((void **) &psum_g,sizeof(int) * ns);
hipMalloc((void **) &listid_g,sizeof(int) * n);
n_init = n;
nc_init = nc;
}
if(n > 0 && nc > 0) {
/*
int *listid = (int *) malloc(sizeof(int) * n);
int *count = (int *) malloc(sizeof(int) * nc);
int *count2 = (int *) malloc(sizeof(int) * nc);
int *psum = (int *) malloc(sizeof(int) * ns);
int *psum2 = (int *) malloc(sizeof(int) * ns);
int i,s;
*/
boxsum_stage1<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g);
/*
cudaThreadSynchronize();
s = 0;
for(i = 0; i<nc; i++)
s += abs(count[i]);
if(s != 0)
printf("count not zeroed, s=%d\n",s);
*/
boxsum_stage2<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
/*
cudaThreadSynchronize();
cudaMemcpy(listid,listid_g,sizeof(int) * n,cudaMemcpyDeviceToHost);
cudaMemcpy(count,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<nc; i++)
s += count[i];
if(s != n)
printf("Error in count, s=%d, n=%d\n",s,n);
*/
boxsum_stage3<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(psum,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);
for(i = 0; i<ns; i++) {
int j;
s = 0;
for(j = 0; j<NTHREADS_RADIX; j++)
if(i*NTHREADS_RADIX+j < nc) s += count[i*NTHREADS_RADIX+j];
if(s != psum[i])
printf("psum error, i=%d ns=%d s=%d psum=%d\n",i,ns,s,psum[i]);
}
*/
boxsum_stage4<<<1,NTHREADS_RADIX>>>(ns,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(psum2,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<ns; i++) {
s += psum[i];
if(s != psum2[i])
printf("cumsum error in psum: s=%d psum2=%d i=%d ns=%d\n",
s,psum2[i],i,ns);
}
*/
boxsum_stage5<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(count2,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<nc; i++) {
s += count[i];
if(s != count2[i])
printf("cumsum error in count: s=%d count2=%d i=%d nc=%d\n",
s,count2[i],i,nc);
}
*/
boxsum_stage6<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
boxsum_stage7<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,listid_g,xin_g,
data1in_g,data2in_g,xout_g,
data1out_g,data2out_g);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* This code is courtesy of, and copyright 2015,
* Tomas Oppelstrup, Livermore National Lab. Please
* do not redistribute without his approval.
*/
#define NTHREADS_RADIX 128
#define NBLOCKS_RADIX 56
__global__ static void
boxsum_stage1(int nc,int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i;
for(i = pid; i<nc; i+=np)
count[i] = 0;
}
__global__ static void
boxsum_stage2(int n,int v[],int listid[],int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i,vi,x;
volatile __shared__ struct { int vi[NTHREADS_RADIX],x[NTHREADS_RADIX]; } shm;
if(0) {
for(i = pid; i<n; i+=np) {
// Compute index within box.
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
} else {
for(i = pid; i<n+tid; i+=np) {
// Compute index within box.
if(n-(i-tid) < nt) {
if(i < n) {
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
} else {
shm.vi[tid] = v[i];
__syncthreads();
// Requirement is that gcd(11,nt) = 1
shm.x[(19*tid)%nt] = atomicAdd(&count[shm.vi[(19*tid)%nt]],1);
__syncthreads();
listid[i] = shm.x[tid];
}
}
/*
int i0,i1;
{
int q = n/np;
int r = n%np;
if(pid >= r) { i0 = q*pid + r; i1 = i0 + q; }
else { i0 = q*pid + pid; i1 = i0 + q + 1; }
}
for(i = i0; i<i1; i++) {
vi = v[i];
x = atomicAdd(&count[vi],1);
listid[i] = x;
}
*/
}
}
__global__ static void
boxsum_stage3(int nboxes,int count[],int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = gridDim.x;
const int pid = bid*nt + tid, np = nb*nt;
int i,x;
volatile __shared__ struct { int x[NTHREADS_RADIX]; } shm;
for(i = pid; i<nboxes+tid; i+=np) {
__syncthreads();
x = 0;
if(i < nboxes) x = count[i];
shm.x[tid] = x;
__syncthreads();
if(tid < 64) shm.x[tid] += shm.x[tid+64];
__syncthreads();
if(tid < 32) {
shm.x[tid] += shm.x[tid+32];
shm.x[tid] += shm.x[tid+16];
shm.x[tid] += shm.x[tid+ 8];
shm.x[tid] += shm.x[tid+ 4];
shm.x[tid] += shm.x[tid+ 2];
shm.x[tid] += shm.x[tid+ 1];
}
if(tid == 0) psum[i/nt] = shm.x[0];
}
}
__global__ static void
boxsum_stage4(int n,int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x;
int i,j,x,s;
volatile __shared__ int xshare[NTHREADS_RADIX];
s = 0;
if(bid == 0)
for(i = tid; i<n+tid; i+=nt) {
__syncthreads();
x = 0;
if(i < n) x = psum[i];
xshare[tid] = x;
__syncthreads();
// Make cumulative summation of columns in type!
j = 1;
while(j < nt) {
if(tid >= j) x += xshare[tid-j];
__syncthreads();
xshare[tid] = x;
j = j*2;
__syncthreads();
}
if(i < n) psum[i] = xshare[tid] + s;
s = s + xshare[nt-1];
}
}
__global__ static void
boxsum_stage5(int nboxes,int count[],int psum[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,x,x1;
volatile __shared__ struct {
int psum,x[2][NTHREADS_RADIX],y[2][NTHREADS_RADIX];
} shm;
shm.x[0][tid] = 0;
shm.y[0][tid] = 0;
for(i = pid; i<nboxes+tid; i+=np) {
__syncthreads();
if(tid == 0) shm.psum = psum[i/nt];
x = 0;
if(i < nboxes) x = count[i];
x1 = x;
shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid- 1]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid- 2]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid- 4]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid- 8]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid-16]; shm.y[1][tid] = x; __syncthreads();
x += shm.y[1][tid-32]; shm.x[1][tid] = x; __syncthreads();
x += shm.x[1][tid-64]; shm.y[1][tid] = x; __syncthreads();
x += shm.psum - shm.y[1][nt-1];
//if(i == nboxes-1) { x=0; x1=0; }
if(i < nboxes) count[i] = x-x1;
}
}
__global__ static void
boxsum_stage6(int n,int v[],int listid[],int count[]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,lid,bno,idx;
for(i = pid; i<n; i+=np) {
lid = listid[i];
bno = v[i];
idx = 0;
if(bno > 0) idx = count[bno];
listid[i] = lid + idx;
}
}
__global__ static void
boxsum_stage7(int n,int listid[],int bin[],float xx[][4], float vv[][4],
int bout[],float xxout[][4], float vvout[][4]) {
const int tid = threadIdx.x, nt = NTHREADS_RADIX;
const int bid = blockIdx.x, nb = NBLOCKS_RADIX;
const int pid = bid*nt + tid, np = nb*nt;
int i,j,xend;
float x,v;
volatile __shared__ struct { int idx[NTHREADS_RADIX]; } shm;
for(i = pid; i<n+tid; i+=np) {
j = 0;
if(i < n) j = listid[i];
xend = min(nt,n-(i-tid));
__syncthreads();
shm.idx[tid] = j;
__syncthreads();
if(i < n) bout[j] = bin[i];
for(j = tid; j<4*xend; j+=nt) {
x = xx[i-tid][j];
v = vv[i-tid][j];
xxout[shm.idx[j/4]][j%4] = x;
vvout[shm.idx[j/4]][j%4] = v;
}
}
}
void rsort_card(int n,int nc,
int *xin_g,float (*data1in_g)[4],float (*data2in_g)[4],
int *xout_g,float (*data1out_g)[4],float (*data2out_g)[4],
int *count_g) {
static int n_init = 0, nc_init = 0;
static int *psum_g,*listid_g;
int ns = (nc+NTHREADS_RADIX-1)/NTHREADS_RADIX;
if(n <= 0 || nc <= 0) {
if(n_init > 0) {
hipFree(listid_g);
hipFree(psum_g);
}
n_init = 0;
nc_init = 0;
} else if(n > n_init || nc > nc_init) {
if(n_init > 0) {
hipFree(listid_g);
hipFree(psum_g);
}
hipMalloc((void **) &psum_g,sizeof(int) * ns);
hipMalloc((void **) &listid_g,sizeof(int) * n);
n_init = n;
nc_init = nc;
}
if(n > 0 && nc > 0) {
/*
int *listid = (int *) malloc(sizeof(int) * n);
int *count = (int *) malloc(sizeof(int) * nc);
int *count2 = (int *) malloc(sizeof(int) * nc);
int *psum = (int *) malloc(sizeof(int) * ns);
int *psum2 = (int *) malloc(sizeof(int) * ns);
int i,s;
*/
boxsum_stage1<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g);
/*
cudaThreadSynchronize();
s = 0;
for(i = 0; i<nc; i++)
s += abs(count[i]);
if(s != 0)
printf("count not zeroed, s=%d\n",s);
*/
boxsum_stage2<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
/*
cudaThreadSynchronize();
cudaMemcpy(listid,listid_g,sizeof(int) * n,cudaMemcpyDeviceToHost);
cudaMemcpy(count,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<nc; i++)
s += count[i];
if(s != n)
printf("Error in count, s=%d, n=%d\n",s,n);
*/
boxsum_stage3<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(psum,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);
for(i = 0; i<ns; i++) {
int j;
s = 0;
for(j = 0; j<NTHREADS_RADIX; j++)
if(i*NTHREADS_RADIX+j < nc) s += count[i*NTHREADS_RADIX+j];
if(s != psum[i])
printf("psum error, i=%d ns=%d s=%d psum=%d\n",i,ns,s,psum[i]);
}
*/
boxsum_stage4<<<1,NTHREADS_RADIX>>>(ns,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(psum2,psum_g,sizeof(int) * ns,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<ns; i++) {
s += psum[i];
if(s != psum2[i])
printf("cumsum error in psum: s=%d psum2=%d i=%d ns=%d\n",
s,psum2[i],i,ns);
}
*/
boxsum_stage5<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(nc,count_g,psum_g);
/*
cudaThreadSynchronize();
cudaMemcpy(count2,count_g,sizeof(int) * nc,cudaMemcpyDeviceToHost);
s = 0;
for(i = 0; i<nc; i++) {
s += count[i];
if(s != count2[i])
printf("cumsum error in count: s=%d count2=%d i=%d nc=%d\n",
s,count2[i],i,nc);
}
*/
boxsum_stage6<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,xin_g,listid_g,count_g);
boxsum_stage7<<<NBLOCKS_RADIX,NTHREADS_RADIX>>>(n,listid_g,xin_g,
data1in_g,data2in_g,xout_g,
data1out_g,data2out_g);
}
} | .text
.file "boxsortinc.hip"
.globl _Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_ # -- Begin function _Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
.p2align 4, 0x90
.type _Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_,@function
_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_: # @_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %r13
movq %r8, 168(%rsp) # 8-byte Spill
movq %rcx, 160(%rsp) # 8-byte Spill
movq %rdx, %r12
movl %esi, %ebx
leal 127(%rbx), %eax
leal 254(%rbx), %r15d
testl %eax, %eax
cmovnsl %eax, %r15d
movl %edi, %ebp
sarl $7, %r15d
movl _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip), %eax
testl %edi, %edi
jle .LBB0_7
# %bb.1:
testl %ebx, %ebx
jle .LBB0_7
# %bb.2:
cmpl %ebp, %eax
jl .LBB0_4
# %bb.3:
cmpl %ebx, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
jge .LBB0_11
.LBB0_4:
testl %eax, %eax
jle .LBB0_6
# %bb.5:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
callq hipFree
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
callq hipFree
.LBB0_6:
movslq %r15d, %rsi
shlq $2, %rsi
movl $_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g, %edi
callq hipMalloc
movl %ebp, %esi
shlq $2, %rsi
movl $_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g, %edi
callq hipMalloc
movl %ebp, %r14d
movl %ebx, %eax
jmp .LBB0_10
.LBB0_7:
xorl %r14d, %r14d
testl %eax, %eax
jle .LBB0_9
# %bb.8:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdi
callq hipFree
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rdi
callq hipFree
.LBB0_9:
xorl %eax, %eax
.LBB0_10: # %.sink.split
movl %r14d, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init(%rip)
movl %eax, _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init(%rip)
.LBB0_11:
testl %ebp, %ebp
jle .LBB0_27
# %bb.12:
testl %ebx, %ebx
jle .LBB0_27
# %bb.13:
movq %r13, 152(%rsp) # 8-byte Spill
movabsq $4294967424, %r13 # imm = 0x100000080
leaq -72(%r13), %r14
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_15
# %bb.14:
movl %ebx, 32(%rsp)
movq 272(%rsp), %rax
movq %rax, 56(%rsp)
leaq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage1iPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_15:
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_17
# %bb.16:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rax
movl %ebp, 72(%rsp)
movq %r12, 56(%rsp)
movq %rax, 48(%rsp)
movq 272(%rsp), %rax
movq %rax, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 32(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage2iPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_17:
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_19
# %bb.18:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rax
movl %ebx, 64(%rsp)
movq 272(%rsp), %rcx
movq %rcx, 56(%rsp)
movq %rax, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage3iPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_19:
leaq -127(%r13), %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_21
# %bb.20:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rax
movl %r15d, 32(%rsp)
movq %rax, 56(%rsp)
leaq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage4iPi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_21:
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_23
# %bb.22:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g(%rip), %rax
movl %ebx, 64(%rsp)
movq 272(%rsp), %rcx
movq %rcx, 56(%rsp)
movq %rax, 48(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage5iPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_23:
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_25
# %bb.24:
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rax
movl %ebp, 72(%rsp)
movq %r12, 56(%rsp)
movq %rax, 48(%rsp)
movq 272(%rsp), %rax
movq %rax, 40(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 32(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage6iPiS_S_, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_25:
movq %r14, %rdi
movl $1, %esi
movq %r13, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 152(%rsp), %rsi # 8-byte Reload
jne .LBB0_27
# %bb.26:
movq 264(%rsp), %rax
movq 256(%rsp), %rcx
movq _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g(%rip), %rdx
movl %ebp, 148(%rsp)
movq %rdx, 56(%rsp)
movq %r12, 48(%rsp)
movq 160(%rsp), %rdx # 8-byte Reload
movq %rdx, 40(%rsp)
movq 168(%rsp), %rdx # 8-byte Reload
movq %rdx, 32(%rsp)
movq %rsi, 64(%rsp)
movq %rcx, 72(%rsp)
movq %rax, 192(%rsp)
leaq 148(%rsp), %rax
movq %rax, 80(%rsp)
leaq 56(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 192(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_27:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_, .Lfunc_end0-_Z10rsort_cardiiPiPA4_fS1_S_S1_S1_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL28__device_stub__boxsum_stage1iPi
.type _ZL28__device_stub__boxsum_stage1iPi,@function
_ZL28__device_stub__boxsum_stage1iPi: # @_ZL28__device_stub__boxsum_stage1iPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL13boxsum_stage1iPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _ZL28__device_stub__boxsum_stage1iPi, .Lfunc_end1-_ZL28__device_stub__boxsum_stage1iPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL28__device_stub__boxsum_stage2iPiS_S_
.type _ZL28__device_stub__boxsum_stage2iPiS_S_,@function
_ZL28__device_stub__boxsum_stage2iPiS_S_: # @_ZL28__device_stub__boxsum_stage2iPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage2iPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _ZL28__device_stub__boxsum_stage2iPiS_S_, .Lfunc_end2-_ZL28__device_stub__boxsum_stage2iPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL28__device_stub__boxsum_stage3iPiS_
.type _ZL28__device_stub__boxsum_stage3iPiS_,@function
_ZL28__device_stub__boxsum_stage3iPiS_: # @_ZL28__device_stub__boxsum_stage3iPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage3iPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _ZL28__device_stub__boxsum_stage3iPiS_, .Lfunc_end3-_ZL28__device_stub__boxsum_stage3iPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL28__device_stub__boxsum_stage4iPi
.type _ZL28__device_stub__boxsum_stage4iPi,@function
_ZL28__device_stub__boxsum_stage4iPi: # @_ZL28__device_stub__boxsum_stage4iPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL13boxsum_stage4iPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _ZL28__device_stub__boxsum_stage4iPi, .Lfunc_end4-_ZL28__device_stub__boxsum_stage4iPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL28__device_stub__boxsum_stage5iPiS_
.type _ZL28__device_stub__boxsum_stage5iPiS_,@function
_ZL28__device_stub__boxsum_stage5iPiS_: # @_ZL28__device_stub__boxsum_stage5iPiS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage5iPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _ZL28__device_stub__boxsum_stage5iPiS_, .Lfunc_end5-_ZL28__device_stub__boxsum_stage5iPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL28__device_stub__boxsum_stage6iPiS_S_
.type _ZL28__device_stub__boxsum_stage6iPiS_S_,@function
_ZL28__device_stub__boxsum_stage6iPiS_S_: # @_ZL28__device_stub__boxsum_stage6iPiS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_ZL13boxsum_stage6iPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _ZL28__device_stub__boxsum_stage6iPiS_S_, .Lfunc_end6-_ZL28__device_stub__boxsum_stage6iPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
.type _ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,@function
_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_: # @_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 4(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movq %r9, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end7:
.size _ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, .Lfunc_end7-_ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL13boxsum_stage1iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL13boxsum_stage2iPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL13boxsum_stage3iPiS_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL13boxsum_stage4iPi, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL13boxsum_stage5iPiS_, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL13boxsum_stage6iPiS_S_, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init,@object # @_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init
.local _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init
.comm _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6n_init,4,4
.type _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init,@object # @_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init
.local _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init
.comm _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E7nc_init,4,4
.type _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g,@object # @_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g
.local _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g
.comm _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g,8,8
.type _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g,@object # @_ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g
.local _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g
.comm _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g,8,8
.type _ZL13boxsum_stage1iPi,@object # @_ZL13boxsum_stage1iPi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL13boxsum_stage1iPi:
.quad _ZL28__device_stub__boxsum_stage1iPi
.size _ZL13boxsum_stage1iPi, 8
.type _ZL13boxsum_stage2iPiS_S_,@object # @_ZL13boxsum_stage2iPiS_S_
.p2align 3, 0x0
_ZL13boxsum_stage2iPiS_S_:
.quad _ZL28__device_stub__boxsum_stage2iPiS_S_
.size _ZL13boxsum_stage2iPiS_S_, 8
.type _ZL13boxsum_stage3iPiS_,@object # @_ZL13boxsum_stage3iPiS_
.p2align 3, 0x0
_ZL13boxsum_stage3iPiS_:
.quad _ZL28__device_stub__boxsum_stage3iPiS_
.size _ZL13boxsum_stage3iPiS_, 8
.type _ZL13boxsum_stage4iPi,@object # @_ZL13boxsum_stage4iPi
.p2align 3, 0x0
_ZL13boxsum_stage4iPi:
.quad _ZL28__device_stub__boxsum_stage4iPi
.size _ZL13boxsum_stage4iPi, 8
.type _ZL13boxsum_stage5iPiS_,@object # @_ZL13boxsum_stage5iPiS_
.p2align 3, 0x0
_ZL13boxsum_stage5iPiS_:
.quad _ZL28__device_stub__boxsum_stage5iPiS_
.size _ZL13boxsum_stage5iPiS_, 8
.type _ZL13boxsum_stage6iPiS_S_,@object # @_ZL13boxsum_stage6iPiS_S_
.p2align 3, 0x0
_ZL13boxsum_stage6iPiS_S_:
.quad _ZL28__device_stub__boxsum_stage6iPiS_S_
.size _ZL13boxsum_stage6iPiS_S_, 8
.type _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_,@object # @_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
.p2align 3, 0x0
_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_:
.quad _ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
.size _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_ZL13boxsum_stage1iPi"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_ZL13boxsum_stage2iPiS_S_"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_ZL13boxsum_stage3iPiS_"
.size .L__unnamed_3, 24
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_ZL13boxsum_stage4iPi"
.size .L__unnamed_4, 22
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_ZL13boxsum_stage5iPiS_"
.size .L__unnamed_5, 24
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_ZL13boxsum_stage6iPiS_S_"
.size .L__unnamed_6, 26
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "_ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_"
.size .L__unnamed_7, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL28__device_stub__boxsum_stage1iPi
.addrsig_sym _ZL28__device_stub__boxsum_stage2iPiS_S_
.addrsig_sym _ZL28__device_stub__boxsum_stage3iPiS_
.addrsig_sym _ZL28__device_stub__boxsum_stage4iPi
.addrsig_sym _ZL28__device_stub__boxsum_stage5iPiS_
.addrsig_sym _ZL28__device_stub__boxsum_stage6iPiS_S_
.addrsig_sym _ZL28__device_stub__boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E6psum_g
.addrsig_sym _ZZ10rsort_cardiiPiPA4_fS1_S_S1_S1_S_E8listid_g
.addrsig_sym _ZL13boxsum_stage1iPi
.addrsig_sym _ZL13boxsum_stage2iPiS_S_
.addrsig_sym _ZL13boxsum_stage3iPiS_
.addrsig_sym _ZL13boxsum_stage4iPi
.addrsig_sym _ZL13boxsum_stage5iPiS_
.addrsig_sym _ZL13boxsum_stage6iPiS_S_
.addrsig_sym _ZL13boxsum_stage7iPiS_PA4_fS1_S_S1_S1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 -c %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES
// Test the correct placement of the offloading actions for compiling CUDA sources (*.cu) in SYCL.
// DEFAULT-PHASES: +- 0: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 1: preprocessor, {0}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 2: compiler, {1}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES:+- 3: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {2}, ir
// DEFAULT-PHASES:| +- 4: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES:| +- 5: preprocessor, {4}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES:| +- 6: compiler, {5}, ir, (host-cuda)
// DEFAULT-PHASES:| | +- 7: backend, {2}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 8: assembler, {7}, object, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {8}, object
// DEFAULT-PHASES:| | |- 10: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, assembler
// DEFAULT-PHASES:| |- 11: linker, {9, 10}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES:| +- 12: offload, "host-cuda (x86_64-unknown-linux-gnu)" {6}, "device-cuda (nvptx64-nvidia-cuda)" {11}, ir
// DEFAULT-PHASES:| +- 13: backend, {12}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES:|- 14: assembler, {13}, object, (host-cuda-sycl)
// DEFAULT-PHASES:15: clang-offload-bundler, {3, 14}, object, (host-cuda-sycl)
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL --cuda-path=%S/Inputs/CUDA_111/usr/local/cuda -fsycl-libspirv-path=%S/Inputs/SYCL/lib/nvidiacl -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES2
// DEFAULT-PHASES2: +- 0: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES2: +- 1: preprocessor, {0}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES2: +- 2: compiler, {1}, ir, (host-cuda)
// DEFAULT-PHASES2: | +- 3: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 5: compiler, {4}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 6: backend, {5}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 7: assembler, {6}, object, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, object
// DEFAULT-PHASES2: | |- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {6}, assembler
// DEFAULT-PHASES2: |- 10: linker, {8, 9}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES2: +- 11: offload, "host-cuda (x86_64-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {10}, ir
// DEFAULT-PHASES2: +- 12: backend, {11}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 13: assembler, {12}, object, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 14: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {13}, object
// DEFAULT-PHASES2:+- 15: linker, {14}, image, (host-cuda-sycl)
// DEFAULT-PHASES2:| +- 16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {5}, ir
// DEFAULT-PHASES2:| +- 17: linker, {16}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 18: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 19: clang-offload-unbundler, {18}, object
// DEFAULT-PHASES2:| |- 20: offload, " (nvptx64-nvidia-cuda)" {19}, object
// DEFAULT-PHASES2:| | +- 21: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 22: clang-offload-unbundler, {21}, object
// DEFAULT-PHASES2:| |- 23: offload, " (nvptx64-nvidia-cuda)" {22}, object
// DEFAULT-PHASES2:| | +- 24: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 25: clang-offload-unbundler, {24}, object
// DEFAULT-PHASES2:| |- 26: offload, " (nvptx64-nvidia-cuda)" {25}, object
// DEFAULT-PHASES2:| | +- 27: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 28: clang-offload-unbundler, {27}, object
// DEFAULT-PHASES2:| |- 29: offload, " (nvptx64-nvidia-cuda)" {28}, object
// DEFAULT-PHASES2:| | +- 30: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 31: clang-offload-unbundler, {30}, object
// DEFAULT-PHASES2:| |- 32: offload, " (nvptx64-nvidia-cuda)" {31}, object
// DEFAULT-PHASES2:| | +- 33: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 34: clang-offload-unbundler, {33}, object
// DEFAULT-PHASES2:| |- 35: offload, " (nvptx64-nvidia-cuda)" {34}, object
// DEFAULT-PHASES2:| | +- 36: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 37: clang-offload-unbundler, {36}, object
// DEFAULT-PHASES2:| |- 38: offload, " (nvptx64-nvidia-cuda)" {37}, object
// DEFAULT-PHASES2:| | +- 39: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 40: clang-offload-unbundler, {39}, object
// DEFAULT-PHASES2:| |- 41: offload, " (nvptx64-nvidia-cuda)" {40}, object
// DEFAULT-PHASES2:| | +- 42: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 43: clang-offload-unbundler, {42}, object
// DEFAULT-PHASES2:| |- 44: offload, " (nvptx64-nvidia-cuda)" {43}, object
// DEFAULT-PHASES2:| | +- 45: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 46: clang-offload-unbundler, {45}, object
// DEFAULT-PHASES2:| |- 47: offload, " (nvptx64-nvidia-cuda)" {46}, object
// DEFAULT-PHASES2:| | +- 48: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 49: clang-offload-unbundler, {48}, object
// DEFAULT-PHASES2:| |- 50: offload, " (nvptx64-nvidia-cuda)" {49}, object
// DEFAULT-PHASES2:| | +- 51: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 52: clang-offload-unbundler, {51}, object
// DEFAULT-PHASES2:| |- 53: offload, " (nvptx64-nvidia-cuda)" {52}, object
// DEFAULT-PHASES2:| | +- 54: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 55: clang-offload-unbundler, {54}, object
// DEFAULT-PHASES2:| |- 56: offload, " (nvptx64-nvidia-cuda)" {55}, object
// DEFAULT-PHASES2:| | +- 57: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 58: clang-offload-unbundler, {57}, object
// DEFAULT-PHASES2:| |- 59: offload, " (nvptx64-nvidia-cuda)" {58}, object
// DEFAULT-PHASES2:| | +- 60: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 61: clang-offload-unbundler, {60}, object
// DEFAULT-PHASES2:| |- 62: offload, " (nvptx64-nvidia-cuda)" {61}, object
// DEFAULT-PHASES2:| | +- 63: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 64: clang-offload-unbundler, {63}, object
// DEFAULT-PHASES2:| |- 65: offload, " (nvptx64-nvidia-cuda)" {64}, object
// DEFAULT-PHASES2:| | +- 66: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 67: clang-offload-unbundler, {66}, object
// DEFAULT-PHASES2:| |- 68: offload, " (nvptx64-nvidia-cuda)" {67}, object
// DEFAULT-PHASES2:| | +- 69: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 70: clang-offload-unbundler, {69}, object
// DEFAULT-PHASES2:| |- 71: offload, " (nvptx64-nvidia-cuda)" {70}, object
// DEFAULT-PHASES2:| | +- 72: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 73: clang-offload-unbundler, {72}, object
// DEFAULT-PHASES2:| |- 74: offload, " (nvptx64-nvidia-cuda)" {73}, object
// DEFAULT-PHASES2:| | +- 75: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 76: clang-offload-unbundler, {75}, object
// DEFAULT-PHASES2:| |- 77: offload, " (nvptx64-nvidia-cuda)" {76}, object
// DEFAULT-PHASES2:| |- 78: input, "{{.*}}nvidiacl{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 79: input, "{{.*}}libdevice{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 80: linker, {17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59, 62, 65, 68, 71, 74, 77, 78, 79}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 81: sycl-post-link, {80}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 82: file-table-tform, {81}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | +- 83: backend, {82}, assembler, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | |- 84: assembler, {83}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | |- 85: linker, {83, 84}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 86: foreach, {82, 85}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 87: file-table-tform, {81, 86}, tempfiletable, (device-sycl, sm_80)
// DEFAULT-PHASES2:|- 88: clang-offload-wrapper, {87}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:89: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {15}, "device-sycl (nvptx64-nvidia-cuda:sm_80)" {88}, image | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 -c %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES
// Test the correct placement of the offloading actions for compiling CUDA sources (*.cu) in SYCL.
// DEFAULT-PHASES: +- 0: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 1: preprocessor, {0}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 2: compiler, {1}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES:+- 3: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {2}, ir
// DEFAULT-PHASES:| +- 4: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES:| +- 5: preprocessor, {4}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES:| +- 6: compiler, {5}, ir, (host-cuda)
// DEFAULT-PHASES:| | +- 7: backend, {2}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 8: assembler, {7}, object, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {8}, object
// DEFAULT-PHASES:| | |- 10: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, assembler
// DEFAULT-PHASES:| |- 11: linker, {9, 10}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES:| +- 12: offload, "host-cuda (x86_64-unknown-linux-gnu)" {6}, "device-cuda (nvptx64-nvidia-cuda)" {11}, ir
// DEFAULT-PHASES:| +- 13: backend, {12}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES:|- 14: assembler, {13}, object, (host-cuda-sycl)
// DEFAULT-PHASES:15: clang-offload-bundler, {3, 14}, object, (host-cuda-sycl)
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL --cuda-path=%S/Inputs/CUDA_111/usr/local/cuda -fsycl-libspirv-path=%S/Inputs/SYCL/lib/nvidiacl -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES2
// DEFAULT-PHASES2: +- 0: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES2: +- 1: preprocessor, {0}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES2: +- 2: compiler, {1}, ir, (host-cuda)
// DEFAULT-PHASES2: | +- 3: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 5: compiler, {4}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 6: backend, {5}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 7: assembler, {6}, object, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, object
// DEFAULT-PHASES2: | |- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {6}, assembler
// DEFAULT-PHASES2: |- 10: linker, {8, 9}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES2: +- 11: offload, "host-cuda (x86_64-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {10}, ir
// DEFAULT-PHASES2: +- 12: backend, {11}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 13: assembler, {12}, object, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 14: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {13}, object
// DEFAULT-PHASES2:+- 15: linker, {14}, image, (host-cuda-sycl)
// DEFAULT-PHASES2:| +- 16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {5}, ir
// DEFAULT-PHASES2:| +- 17: linker, {16}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 18: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 19: clang-offload-unbundler, {18}, object
// DEFAULT-PHASES2:| |- 20: offload, " (nvptx64-nvidia-cuda)" {19}, object
// DEFAULT-PHASES2:| | +- 21: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 22: clang-offload-unbundler, {21}, object
// DEFAULT-PHASES2:| |- 23: offload, " (nvptx64-nvidia-cuda)" {22}, object
// DEFAULT-PHASES2:| | +- 24: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 25: clang-offload-unbundler, {24}, object
// DEFAULT-PHASES2:| |- 26: offload, " (nvptx64-nvidia-cuda)" {25}, object
// DEFAULT-PHASES2:| | +- 27: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 28: clang-offload-unbundler, {27}, object
// DEFAULT-PHASES2:| |- 29: offload, " (nvptx64-nvidia-cuda)" {28}, object
// DEFAULT-PHASES2:| | +- 30: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 31: clang-offload-unbundler, {30}, object
// DEFAULT-PHASES2:| |- 32: offload, " (nvptx64-nvidia-cuda)" {31}, object
// DEFAULT-PHASES2:| | +- 33: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 34: clang-offload-unbundler, {33}, object
// DEFAULT-PHASES2:| |- 35: offload, " (nvptx64-nvidia-cuda)" {34}, object
// DEFAULT-PHASES2:| | +- 36: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 37: clang-offload-unbundler, {36}, object
// DEFAULT-PHASES2:| |- 38: offload, " (nvptx64-nvidia-cuda)" {37}, object
// DEFAULT-PHASES2:| | +- 39: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 40: clang-offload-unbundler, {39}, object
// DEFAULT-PHASES2:| |- 41: offload, " (nvptx64-nvidia-cuda)" {40}, object
// DEFAULT-PHASES2:| | +- 42: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 43: clang-offload-unbundler, {42}, object
// DEFAULT-PHASES2:| |- 44: offload, " (nvptx64-nvidia-cuda)" {43}, object
// DEFAULT-PHASES2:| | +- 45: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 46: clang-offload-unbundler, {45}, object
// DEFAULT-PHASES2:| |- 47: offload, " (nvptx64-nvidia-cuda)" {46}, object
// DEFAULT-PHASES2:| | +- 48: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 49: clang-offload-unbundler, {48}, object
// DEFAULT-PHASES2:| |- 50: offload, " (nvptx64-nvidia-cuda)" {49}, object
// DEFAULT-PHASES2:| | +- 51: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 52: clang-offload-unbundler, {51}, object
// DEFAULT-PHASES2:| |- 53: offload, " (nvptx64-nvidia-cuda)" {52}, object
// DEFAULT-PHASES2:| | +- 54: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 55: clang-offload-unbundler, {54}, object
// DEFAULT-PHASES2:| |- 56: offload, " (nvptx64-nvidia-cuda)" {55}, object
// DEFAULT-PHASES2:| | +- 57: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 58: clang-offload-unbundler, {57}, object
// DEFAULT-PHASES2:| |- 59: offload, " (nvptx64-nvidia-cuda)" {58}, object
// DEFAULT-PHASES2:| | +- 60: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 61: clang-offload-unbundler, {60}, object
// DEFAULT-PHASES2:| |- 62: offload, " (nvptx64-nvidia-cuda)" {61}, object
// DEFAULT-PHASES2:| | +- 63: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 64: clang-offload-unbundler, {63}, object
// DEFAULT-PHASES2:| |- 65: offload, " (nvptx64-nvidia-cuda)" {64}, object
// DEFAULT-PHASES2:| | +- 66: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 67: clang-offload-unbundler, {66}, object
// DEFAULT-PHASES2:| |- 68: offload, " (nvptx64-nvidia-cuda)" {67}, object
// DEFAULT-PHASES2:| | +- 69: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 70: clang-offload-unbundler, {69}, object
// DEFAULT-PHASES2:| |- 71: offload, " (nvptx64-nvidia-cuda)" {70}, object
// DEFAULT-PHASES2:| | +- 72: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 73: clang-offload-unbundler, {72}, object
// DEFAULT-PHASES2:| |- 74: offload, " (nvptx64-nvidia-cuda)" {73}, object
// DEFAULT-PHASES2:| | +- 75: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 76: clang-offload-unbundler, {75}, object
// DEFAULT-PHASES2:| |- 77: offload, " (nvptx64-nvidia-cuda)" {76}, object
// DEFAULT-PHASES2:| |- 78: input, "{{.*}}nvidiacl{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 79: input, "{{.*}}libdevice{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 80: linker, {17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59, 62, 65, 68, 71, 74, 77, 78, 79}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 81: sycl-post-link, {80}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 82: file-table-tform, {81}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | +- 83: backend, {82}, assembler, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | |- 84: assembler, {83}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | |- 85: linker, {83, 84}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 86: foreach, {82, 85}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 87: file-table-tform, {81, 86}, tempfiletable, (device-sycl, sm_80)
// DEFAULT-PHASES2:|- 88: clang-offload-wrapper, {87}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:89: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {15}, "device-sycl (nvptx64-nvidia-cuda:sm_80)" {88}, image | .file "tmpxft_00090e3c_00000000-6_sycl-cuda-tu-offload.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 -c %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES
// Test the correct placement of the offloading actions for compiling CUDA sources (*.cu) in SYCL.
// DEFAULT-PHASES: +- 0: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 1: preprocessor, {0}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 2: compiler, {1}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES:+- 3: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {2}, ir
// DEFAULT-PHASES:| +- 4: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES:| +- 5: preprocessor, {4}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES:| +- 6: compiler, {5}, ir, (host-cuda)
// DEFAULT-PHASES:| | +- 7: backend, {2}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 8: assembler, {7}, object, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {8}, object
// DEFAULT-PHASES:| | |- 10: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, assembler
// DEFAULT-PHASES:| |- 11: linker, {9, 10}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES:| +- 12: offload, "host-cuda (x86_64-unknown-linux-gnu)" {6}, "device-cuda (nvptx64-nvidia-cuda)" {11}, ir
// DEFAULT-PHASES:| +- 13: backend, {12}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES:|- 14: assembler, {13}, object, (host-cuda-sycl)
// DEFAULT-PHASES:15: clang-offload-bundler, {3, 14}, object, (host-cuda-sycl)
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL --cuda-path=%S/Inputs/CUDA_111/usr/local/cuda -fsycl-libspirv-path=%S/Inputs/SYCL/lib/nvidiacl -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES2
// DEFAULT-PHASES2: +- 0: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES2: +- 1: preprocessor, {0}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES2: +- 2: compiler, {1}, ir, (host-cuda)
// DEFAULT-PHASES2: | +- 3: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 5: compiler, {4}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 6: backend, {5}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 7: assembler, {6}, object, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, object
// DEFAULT-PHASES2: | |- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {6}, assembler
// DEFAULT-PHASES2: |- 10: linker, {8, 9}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES2: +- 11: offload, "host-cuda (x86_64-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {10}, ir
// DEFAULT-PHASES2: +- 12: backend, {11}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 13: assembler, {12}, object, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 14: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {13}, object
// DEFAULT-PHASES2:+- 15: linker, {14}, image, (host-cuda-sycl)
// DEFAULT-PHASES2:| +- 16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {5}, ir
// DEFAULT-PHASES2:| +- 17: linker, {16}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 18: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 19: clang-offload-unbundler, {18}, object
// DEFAULT-PHASES2:| |- 20: offload, " (nvptx64-nvidia-cuda)" {19}, object
// DEFAULT-PHASES2:| | +- 21: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 22: clang-offload-unbundler, {21}, object
// DEFAULT-PHASES2:| |- 23: offload, " (nvptx64-nvidia-cuda)" {22}, object
// DEFAULT-PHASES2:| | +- 24: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 25: clang-offload-unbundler, {24}, object
// DEFAULT-PHASES2:| |- 26: offload, " (nvptx64-nvidia-cuda)" {25}, object
// DEFAULT-PHASES2:| | +- 27: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 28: clang-offload-unbundler, {27}, object
// DEFAULT-PHASES2:| |- 29: offload, " (nvptx64-nvidia-cuda)" {28}, object
// DEFAULT-PHASES2:| | +- 30: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 31: clang-offload-unbundler, {30}, object
// DEFAULT-PHASES2:| |- 32: offload, " (nvptx64-nvidia-cuda)" {31}, object
// DEFAULT-PHASES2:| | +- 33: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 34: clang-offload-unbundler, {33}, object
// DEFAULT-PHASES2:| |- 35: offload, " (nvptx64-nvidia-cuda)" {34}, object
// DEFAULT-PHASES2:| | +- 36: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 37: clang-offload-unbundler, {36}, object
// DEFAULT-PHASES2:| |- 38: offload, " (nvptx64-nvidia-cuda)" {37}, object
// DEFAULT-PHASES2:| | +- 39: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 40: clang-offload-unbundler, {39}, object
// DEFAULT-PHASES2:| |- 41: offload, " (nvptx64-nvidia-cuda)" {40}, object
// DEFAULT-PHASES2:| | +- 42: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 43: clang-offload-unbundler, {42}, object
// DEFAULT-PHASES2:| |- 44: offload, " (nvptx64-nvidia-cuda)" {43}, object
// DEFAULT-PHASES2:| | +- 45: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 46: clang-offload-unbundler, {45}, object
// DEFAULT-PHASES2:| |- 47: offload, " (nvptx64-nvidia-cuda)" {46}, object
// DEFAULT-PHASES2:| | +- 48: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 49: clang-offload-unbundler, {48}, object
// DEFAULT-PHASES2:| |- 50: offload, " (nvptx64-nvidia-cuda)" {49}, object
// DEFAULT-PHASES2:| | +- 51: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 52: clang-offload-unbundler, {51}, object
// DEFAULT-PHASES2:| |- 53: offload, " (nvptx64-nvidia-cuda)" {52}, object
// DEFAULT-PHASES2:| | +- 54: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 55: clang-offload-unbundler, {54}, object
// DEFAULT-PHASES2:| |- 56: offload, " (nvptx64-nvidia-cuda)" {55}, object
// DEFAULT-PHASES2:| | +- 57: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 58: clang-offload-unbundler, {57}, object
// DEFAULT-PHASES2:| |- 59: offload, " (nvptx64-nvidia-cuda)" {58}, object
// DEFAULT-PHASES2:| | +- 60: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 61: clang-offload-unbundler, {60}, object
// DEFAULT-PHASES2:| |- 62: offload, " (nvptx64-nvidia-cuda)" {61}, object
// DEFAULT-PHASES2:| | +- 63: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 64: clang-offload-unbundler, {63}, object
// DEFAULT-PHASES2:| |- 65: offload, " (nvptx64-nvidia-cuda)" {64}, object
// DEFAULT-PHASES2:| | +- 66: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 67: clang-offload-unbundler, {66}, object
// DEFAULT-PHASES2:| |- 68: offload, " (nvptx64-nvidia-cuda)" {67}, object
// DEFAULT-PHASES2:| | +- 69: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 70: clang-offload-unbundler, {69}, object
// DEFAULT-PHASES2:| |- 71: offload, " (nvptx64-nvidia-cuda)" {70}, object
// DEFAULT-PHASES2:| | +- 72: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 73: clang-offload-unbundler, {72}, object
// DEFAULT-PHASES2:| |- 74: offload, " (nvptx64-nvidia-cuda)" {73}, object
// DEFAULT-PHASES2:| | +- 75: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 76: clang-offload-unbundler, {75}, object
// DEFAULT-PHASES2:| |- 77: offload, " (nvptx64-nvidia-cuda)" {76}, object
// DEFAULT-PHASES2:| |- 78: input, "{{.*}}nvidiacl{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 79: input, "{{.*}}libdevice{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 80: linker, {17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59, 62, 65, 68, 71, 74, 77, 78, 79}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 81: sycl-post-link, {80}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 82: file-table-tform, {81}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | +- 83: backend, {82}, assembler, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | |- 84: assembler, {83}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | |- 85: linker, {83, 84}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 86: foreach, {82, 85}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 87: file-table-tform, {81, 86}, tempfiletable, (device-sycl, sm_80)
// DEFAULT-PHASES2:|- 88: clang-offload-wrapper, {87}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:89: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {15}, "device-sycl (nvptx64-nvidia-cuda:sm_80)" {88}, image | #include <hip/hip_runtime.h>
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 -c %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES
// Test the correct placement of the offloading actions for compiling CUDA sources (*.cu) in SYCL.
// DEFAULT-PHASES: +- 0: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 1: preprocessor, {0}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 2: compiler, {1}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES:+- 3: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {2}, ir
// DEFAULT-PHASES:| +- 4: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES:| +- 5: preprocessor, {4}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES:| +- 6: compiler, {5}, ir, (host-cuda)
// DEFAULT-PHASES:| | +- 7: backend, {2}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 8: assembler, {7}, object, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {8}, object
// DEFAULT-PHASES:| | |- 10: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, assembler
// DEFAULT-PHASES:| |- 11: linker, {9, 10}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES:| +- 12: offload, "host-cuda (x86_64-unknown-linux-gnu)" {6}, "device-cuda (nvptx64-nvidia-cuda)" {11}, ir
// DEFAULT-PHASES:| +- 13: backend, {12}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES:|- 14: assembler, {13}, object, (host-cuda-sycl)
// DEFAULT-PHASES:15: clang-offload-bundler, {3, 14}, object, (host-cuda-sycl)
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL --cuda-path=%S/Inputs/CUDA_111/usr/local/cuda -fsycl-libspirv-path=%S/Inputs/SYCL/lib/nvidiacl -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES2
// DEFAULT-PHASES2: +- 0: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES2: +- 1: preprocessor, {0}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES2: +- 2: compiler, {1}, ir, (host-cuda)
// DEFAULT-PHASES2: | +- 3: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 5: compiler, {4}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 6: backend, {5}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 7: assembler, {6}, object, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, object
// DEFAULT-PHASES2: | |- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {6}, assembler
// DEFAULT-PHASES2: |- 10: linker, {8, 9}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES2: +- 11: offload, "host-cuda (x86_64-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {10}, ir
// DEFAULT-PHASES2: +- 12: backend, {11}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 13: assembler, {12}, object, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 14: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {13}, object
// DEFAULT-PHASES2:+- 15: linker, {14}, image, (host-cuda-sycl)
// DEFAULT-PHASES2:| +- 16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {5}, ir
// DEFAULT-PHASES2:| +- 17: linker, {16}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 18: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 19: clang-offload-unbundler, {18}, object
// DEFAULT-PHASES2:| |- 20: offload, " (nvptx64-nvidia-cuda)" {19}, object
// DEFAULT-PHASES2:| | +- 21: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 22: clang-offload-unbundler, {21}, object
// DEFAULT-PHASES2:| |- 23: offload, " (nvptx64-nvidia-cuda)" {22}, object
// DEFAULT-PHASES2:| | +- 24: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 25: clang-offload-unbundler, {24}, object
// DEFAULT-PHASES2:| |- 26: offload, " (nvptx64-nvidia-cuda)" {25}, object
// DEFAULT-PHASES2:| | +- 27: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 28: clang-offload-unbundler, {27}, object
// DEFAULT-PHASES2:| |- 29: offload, " (nvptx64-nvidia-cuda)" {28}, object
// DEFAULT-PHASES2:| | +- 30: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 31: clang-offload-unbundler, {30}, object
// DEFAULT-PHASES2:| |- 32: offload, " (nvptx64-nvidia-cuda)" {31}, object
// DEFAULT-PHASES2:| | +- 33: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 34: clang-offload-unbundler, {33}, object
// DEFAULT-PHASES2:| |- 35: offload, " (nvptx64-nvidia-cuda)" {34}, object
// DEFAULT-PHASES2:| | +- 36: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 37: clang-offload-unbundler, {36}, object
// DEFAULT-PHASES2:| |- 38: offload, " (nvptx64-nvidia-cuda)" {37}, object
// DEFAULT-PHASES2:| | +- 39: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 40: clang-offload-unbundler, {39}, object
// DEFAULT-PHASES2:| |- 41: offload, " (nvptx64-nvidia-cuda)" {40}, object
// DEFAULT-PHASES2:| | +- 42: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 43: clang-offload-unbundler, {42}, object
// DEFAULT-PHASES2:| |- 44: offload, " (nvptx64-nvidia-cuda)" {43}, object
// DEFAULT-PHASES2:| | +- 45: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 46: clang-offload-unbundler, {45}, object
// DEFAULT-PHASES2:| |- 47: offload, " (nvptx64-nvidia-cuda)" {46}, object
// DEFAULT-PHASES2:| | +- 48: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 49: clang-offload-unbundler, {48}, object
// DEFAULT-PHASES2:| |- 50: offload, " (nvptx64-nvidia-cuda)" {49}, object
// DEFAULT-PHASES2:| | +- 51: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 52: clang-offload-unbundler, {51}, object
// DEFAULT-PHASES2:| |- 53: offload, " (nvptx64-nvidia-cuda)" {52}, object
// DEFAULT-PHASES2:| | +- 54: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 55: clang-offload-unbundler, {54}, object
// DEFAULT-PHASES2:| |- 56: offload, " (nvptx64-nvidia-cuda)" {55}, object
// DEFAULT-PHASES2:| | +- 57: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 58: clang-offload-unbundler, {57}, object
// DEFAULT-PHASES2:| |- 59: offload, " (nvptx64-nvidia-cuda)" {58}, object
// DEFAULT-PHASES2:| | +- 60: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 61: clang-offload-unbundler, {60}, object
// DEFAULT-PHASES2:| |- 62: offload, " (nvptx64-nvidia-cuda)" {61}, object
// DEFAULT-PHASES2:| | +- 63: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 64: clang-offload-unbundler, {63}, object
// DEFAULT-PHASES2:| |- 65: offload, " (nvptx64-nvidia-cuda)" {64}, object
// DEFAULT-PHASES2:| | +- 66: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 67: clang-offload-unbundler, {66}, object
// DEFAULT-PHASES2:| |- 68: offload, " (nvptx64-nvidia-cuda)" {67}, object
// DEFAULT-PHASES2:| | +- 69: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 70: clang-offload-unbundler, {69}, object
// DEFAULT-PHASES2:| |- 71: offload, " (nvptx64-nvidia-cuda)" {70}, object
// DEFAULT-PHASES2:| | +- 72: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 73: clang-offload-unbundler, {72}, object
// DEFAULT-PHASES2:| |- 74: offload, " (nvptx64-nvidia-cuda)" {73}, object
// DEFAULT-PHASES2:| | +- 75: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 76: clang-offload-unbundler, {75}, object
// DEFAULT-PHASES2:| |- 77: offload, " (nvptx64-nvidia-cuda)" {76}, object
// DEFAULT-PHASES2:| |- 78: input, "{{.*}}nvidiacl{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 79: input, "{{.*}}libdevice{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 80: linker, {17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59, 62, 65, 68, 71, 74, 77, 78, 79}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 81: sycl-post-link, {80}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 82: file-table-tform, {81}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | +- 83: backend, {82}, assembler, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | |- 84: assembler, {83}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | |- 85: linker, {83, 84}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 86: foreach, {82, 85}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 87: file-table-tform, {81, 86}, tempfiletable, (device-sycl, sm_80)
// DEFAULT-PHASES2:|- 88: clang-offload-wrapper, {87}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:89: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {15}, "device-sycl (nvptx64-nvidia-cuda:sm_80)" {88}, image |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 -c %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES
// Test the correct placement of the offloading actions for compiling CUDA sources (*.cu) in SYCL.
// DEFAULT-PHASES: +- 0: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 1: preprocessor, {0}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 2: compiler, {1}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES:+- 3: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {2}, ir
// DEFAULT-PHASES:| +- 4: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES:| +- 5: preprocessor, {4}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES:| +- 6: compiler, {5}, ir, (host-cuda)
// DEFAULT-PHASES:| | +- 7: backend, {2}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 8: assembler, {7}, object, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {8}, object
// DEFAULT-PHASES:| | |- 10: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, assembler
// DEFAULT-PHASES:| |- 11: linker, {9, 10}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES:| +- 12: offload, "host-cuda (x86_64-unknown-linux-gnu)" {6}, "device-cuda (nvptx64-nvidia-cuda)" {11}, ir
// DEFAULT-PHASES:| +- 13: backend, {12}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES:|- 14: assembler, {13}, object, (host-cuda-sycl)
// DEFAULT-PHASES:15: clang-offload-bundler, {3, 14}, object, (host-cuda-sycl)
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL --cuda-path=%S/Inputs/CUDA_111/usr/local/cuda -fsycl-libspirv-path=%S/Inputs/SYCL/lib/nvidiacl -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES2
// DEFAULT-PHASES2: +- 0: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES2: +- 1: preprocessor, {0}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES2: +- 2: compiler, {1}, ir, (host-cuda)
// DEFAULT-PHASES2: | +- 3: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 5: compiler, {4}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 6: backend, {5}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 7: assembler, {6}, object, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, object
// DEFAULT-PHASES2: | |- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {6}, assembler
// DEFAULT-PHASES2: |- 10: linker, {8, 9}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES2: +- 11: offload, "host-cuda (x86_64-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {10}, ir
// DEFAULT-PHASES2: +- 12: backend, {11}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 13: assembler, {12}, object, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 14: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {13}, object
// DEFAULT-PHASES2:+- 15: linker, {14}, image, (host-cuda-sycl)
// DEFAULT-PHASES2:| +- 16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {5}, ir
// DEFAULT-PHASES2:| +- 17: linker, {16}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 18: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 19: clang-offload-unbundler, {18}, object
// DEFAULT-PHASES2:| |- 20: offload, " (nvptx64-nvidia-cuda)" {19}, object
// DEFAULT-PHASES2:| | +- 21: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 22: clang-offload-unbundler, {21}, object
// DEFAULT-PHASES2:| |- 23: offload, " (nvptx64-nvidia-cuda)" {22}, object
// DEFAULT-PHASES2:| | +- 24: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 25: clang-offload-unbundler, {24}, object
// DEFAULT-PHASES2:| |- 26: offload, " (nvptx64-nvidia-cuda)" {25}, object
// DEFAULT-PHASES2:| | +- 27: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 28: clang-offload-unbundler, {27}, object
// DEFAULT-PHASES2:| |- 29: offload, " (nvptx64-nvidia-cuda)" {28}, object
// DEFAULT-PHASES2:| | +- 30: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 31: clang-offload-unbundler, {30}, object
// DEFAULT-PHASES2:| |- 32: offload, " (nvptx64-nvidia-cuda)" {31}, object
// DEFAULT-PHASES2:| | +- 33: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 34: clang-offload-unbundler, {33}, object
// DEFAULT-PHASES2:| |- 35: offload, " (nvptx64-nvidia-cuda)" {34}, object
// DEFAULT-PHASES2:| | +- 36: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 37: clang-offload-unbundler, {36}, object
// DEFAULT-PHASES2:| |- 38: offload, " (nvptx64-nvidia-cuda)" {37}, object
// DEFAULT-PHASES2:| | +- 39: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 40: clang-offload-unbundler, {39}, object
// DEFAULT-PHASES2:| |- 41: offload, " (nvptx64-nvidia-cuda)" {40}, object
// DEFAULT-PHASES2:| | +- 42: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 43: clang-offload-unbundler, {42}, object
// DEFAULT-PHASES2:| |- 44: offload, " (nvptx64-nvidia-cuda)" {43}, object
// DEFAULT-PHASES2:| | +- 45: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 46: clang-offload-unbundler, {45}, object
// DEFAULT-PHASES2:| |- 47: offload, " (nvptx64-nvidia-cuda)" {46}, object
// DEFAULT-PHASES2:| | +- 48: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 49: clang-offload-unbundler, {48}, object
// DEFAULT-PHASES2:| |- 50: offload, " (nvptx64-nvidia-cuda)" {49}, object
// DEFAULT-PHASES2:| | +- 51: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 52: clang-offload-unbundler, {51}, object
// DEFAULT-PHASES2:| |- 53: offload, " (nvptx64-nvidia-cuda)" {52}, object
// DEFAULT-PHASES2:| | +- 54: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 55: clang-offload-unbundler, {54}, object
// DEFAULT-PHASES2:| |- 56: offload, " (nvptx64-nvidia-cuda)" {55}, object
// DEFAULT-PHASES2:| | +- 57: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 58: clang-offload-unbundler, {57}, object
// DEFAULT-PHASES2:| |- 59: offload, " (nvptx64-nvidia-cuda)" {58}, object
// DEFAULT-PHASES2:| | +- 60: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 61: clang-offload-unbundler, {60}, object
// DEFAULT-PHASES2:| |- 62: offload, " (nvptx64-nvidia-cuda)" {61}, object
// DEFAULT-PHASES2:| | +- 63: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 64: clang-offload-unbundler, {63}, object
// DEFAULT-PHASES2:| |- 65: offload, " (nvptx64-nvidia-cuda)" {64}, object
// DEFAULT-PHASES2:| | +- 66: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 67: clang-offload-unbundler, {66}, object
// DEFAULT-PHASES2:| |- 68: offload, " (nvptx64-nvidia-cuda)" {67}, object
// DEFAULT-PHASES2:| | +- 69: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 70: clang-offload-unbundler, {69}, object
// DEFAULT-PHASES2:| |- 71: offload, " (nvptx64-nvidia-cuda)" {70}, object
// DEFAULT-PHASES2:| | +- 72: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 73: clang-offload-unbundler, {72}, object
// DEFAULT-PHASES2:| |- 74: offload, " (nvptx64-nvidia-cuda)" {73}, object
// DEFAULT-PHASES2:| | +- 75: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 76: clang-offload-unbundler, {75}, object
// DEFAULT-PHASES2:| |- 77: offload, " (nvptx64-nvidia-cuda)" {76}, object
// DEFAULT-PHASES2:| |- 78: input, "{{.*}}nvidiacl{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 79: input, "{{.*}}libdevice{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 80: linker, {17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59, 62, 65, 68, 71, 74, 77, 78, 79}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 81: sycl-post-link, {80}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 82: file-table-tform, {81}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | +- 83: backend, {82}, assembler, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | |- 84: assembler, {83}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | |- 85: linker, {83, 84}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 86: foreach, {82, 85}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 87: file-table-tform, {81, 86}, tempfiletable, (device-sycl, sm_80)
// DEFAULT-PHASES2:|- 88: clang-offload-wrapper, {87}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:89: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {15}, "device-sycl (nvptx64-nvidia-cuda:sm_80)" {88}, image | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 -c %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES
// Test the correct placement of the offloading actions for compiling CUDA sources (*.cu) in SYCL.
// DEFAULT-PHASES: +- 0: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 1: preprocessor, {0}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES: +- 2: compiler, {1}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES:+- 3: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {2}, ir
// DEFAULT-PHASES:| +- 4: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES:| +- 5: preprocessor, {4}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES:| +- 6: compiler, {5}, ir, (host-cuda)
// DEFAULT-PHASES:| | +- 7: backend, {2}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 8: assembler, {7}, object, (device-cuda, sm_80)
// DEFAULT-PHASES:| | +- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {8}, object
// DEFAULT-PHASES:| | |- 10: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, assembler
// DEFAULT-PHASES:| |- 11: linker, {9, 10}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES:| +- 12: offload, "host-cuda (x86_64-unknown-linux-gnu)" {6}, "device-cuda (nvptx64-nvidia-cuda)" {11}, ir
// DEFAULT-PHASES:| +- 13: backend, {12}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES:|- 14: assembler, {13}, object, (host-cuda-sycl)
// DEFAULT-PHASES:15: clang-offload-bundler, {3, 14}, object, (host-cuda-sycl)
// RUN: %clangxx -ccc-print-phases --sysroot=%S/Inputs/SYCL --cuda-path=%S/Inputs/CUDA_111/usr/local/cuda -fsycl-libspirv-path=%S/Inputs/SYCL/lib/nvidiacl -target x86_64-unknown-linux-gnu -fsycl -fsycl-targets=nvptx64-nvidia-cuda -Xsycl-target-backend --cuda-gpu-arch=sm_80 --cuda-gpu-arch=sm_80 %s 2>&1 | FileCheck %s --check-prefix=DEFAULT-PHASES2
// DEFAULT-PHASES2: +- 0: input, "{{.*}}", cuda, (host-cuda)
// DEFAULT-PHASES2: +- 1: preprocessor, {0}, cuda-cpp-output, (host-cuda)
// DEFAULT-PHASES2: +- 2: compiler, {1}, ir, (host-cuda)
// DEFAULT-PHASES2: | +- 3: input, "{{.*}}", cuda, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 4: preprocessor, {3}, cuda-cpp-output, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 5: compiler, {4}, ir, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 6: backend, {5}, assembler, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 7: assembler, {6}, object, (device-cuda, sm_80)
// DEFAULT-PHASES2: | +- 8: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {7}, object
// DEFAULT-PHASES2: | |- 9: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {6}, assembler
// DEFAULT-PHASES2: |- 10: linker, {8, 9}, cuda-fatbin, (device-cuda)
// DEFAULT-PHASES2: +- 11: offload, "host-cuda (x86_64-unknown-linux-gnu)" {2}, "device-cuda (nvptx64-nvidia-cuda)" {10}, ir
// DEFAULT-PHASES2: +- 12: backend, {11}, assembler, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 13: assembler, {12}, object, (host-cuda-sycl)
// DEFAULT-PHASES2: +- 14: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {13}, object
// DEFAULT-PHASES2:+- 15: linker, {14}, image, (host-cuda-sycl)
// DEFAULT-PHASES2:| +- 16: offload, "device-cuda (nvptx64-nvidia-cuda:sm_80)" {5}, ir
// DEFAULT-PHASES2:| +- 17: linker, {16}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 18: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 19: clang-offload-unbundler, {18}, object
// DEFAULT-PHASES2:| |- 20: offload, " (nvptx64-nvidia-cuda)" {19}, object
// DEFAULT-PHASES2:| | +- 21: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 22: clang-offload-unbundler, {21}, object
// DEFAULT-PHASES2:| |- 23: offload, " (nvptx64-nvidia-cuda)" {22}, object
// DEFAULT-PHASES2:| | +- 24: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 25: clang-offload-unbundler, {24}, object
// DEFAULT-PHASES2:| |- 26: offload, " (nvptx64-nvidia-cuda)" {25}, object
// DEFAULT-PHASES2:| | +- 27: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 28: clang-offload-unbundler, {27}, object
// DEFAULT-PHASES2:| |- 29: offload, " (nvptx64-nvidia-cuda)" {28}, object
// DEFAULT-PHASES2:| | +- 30: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 31: clang-offload-unbundler, {30}, object
// DEFAULT-PHASES2:| |- 32: offload, " (nvptx64-nvidia-cuda)" {31}, object
// DEFAULT-PHASES2:| | +- 33: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 34: clang-offload-unbundler, {33}, object
// DEFAULT-PHASES2:| |- 35: offload, " (nvptx64-nvidia-cuda)" {34}, object
// DEFAULT-PHASES2:| | +- 36: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 37: clang-offload-unbundler, {36}, object
// DEFAULT-PHASES2:| |- 38: offload, " (nvptx64-nvidia-cuda)" {37}, object
// DEFAULT-PHASES2:| | +- 39: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 40: clang-offload-unbundler, {39}, object
// DEFAULT-PHASES2:| |- 41: offload, " (nvptx64-nvidia-cuda)" {40}, object
// DEFAULT-PHASES2:| | +- 42: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 43: clang-offload-unbundler, {42}, object
// DEFAULT-PHASES2:| |- 44: offload, " (nvptx64-nvidia-cuda)" {43}, object
// DEFAULT-PHASES2:| | +- 45: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 46: clang-offload-unbundler, {45}, object
// DEFAULT-PHASES2:| |- 47: offload, " (nvptx64-nvidia-cuda)" {46}, object
// DEFAULT-PHASES2:| | +- 48: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 49: clang-offload-unbundler, {48}, object
// DEFAULT-PHASES2:| |- 50: offload, " (nvptx64-nvidia-cuda)" {49}, object
// DEFAULT-PHASES2:| | +- 51: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 52: clang-offload-unbundler, {51}, object
// DEFAULT-PHASES2:| |- 53: offload, " (nvptx64-nvidia-cuda)" {52}, object
// DEFAULT-PHASES2:| | +- 54: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 55: clang-offload-unbundler, {54}, object
// DEFAULT-PHASES2:| |- 56: offload, " (nvptx64-nvidia-cuda)" {55}, object
// DEFAULT-PHASES2:| | +- 57: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 58: clang-offload-unbundler, {57}, object
// DEFAULT-PHASES2:| |- 59: offload, " (nvptx64-nvidia-cuda)" {58}, object
// DEFAULT-PHASES2:| | +- 60: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 61: clang-offload-unbundler, {60}, object
// DEFAULT-PHASES2:| |- 62: offload, " (nvptx64-nvidia-cuda)" {61}, object
// DEFAULT-PHASES2:| | +- 63: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 64: clang-offload-unbundler, {63}, object
// DEFAULT-PHASES2:| |- 65: offload, " (nvptx64-nvidia-cuda)" {64}, object
// DEFAULT-PHASES2:| | +- 66: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 67: clang-offload-unbundler, {66}, object
// DEFAULT-PHASES2:| |- 68: offload, " (nvptx64-nvidia-cuda)" {67}, object
// DEFAULT-PHASES2:| | +- 69: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 70: clang-offload-unbundler, {69}, object
// DEFAULT-PHASES2:| |- 71: offload, " (nvptx64-nvidia-cuda)" {70}, object
// DEFAULT-PHASES2:| | +- 72: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 73: clang-offload-unbundler, {72}, object
// DEFAULT-PHASES2:| |- 74: offload, " (nvptx64-nvidia-cuda)" {73}, object
// DEFAULT-PHASES2:| | +- 75: input, "{{.*}}", object
// DEFAULT-PHASES2:| | +- 76: clang-offload-unbundler, {75}, object
// DEFAULT-PHASES2:| |- 77: offload, " (nvptx64-nvidia-cuda)" {76}, object
// DEFAULT-PHASES2:| |- 78: input, "{{.*}}nvidiacl{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 79: input, "{{.*}}libdevice{{.*}}", ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 80: linker, {17, 20, 23, 26, 29, 32, 35, 38, 41, 44, 47, 50, 53, 56, 59, 62, 65, 68, 71, 74, 77, 78, 79}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 81: sycl-post-link, {80}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | +- 82: file-table-tform, {81}, ir, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | +- 83: backend, {82}, assembler, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | | |- 84: assembler, {83}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:| | |- 85: linker, {83, 84}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| |- 86: foreach, {82, 85}, cuda-fatbin, (device-sycl, sm_80)
// DEFAULT-PHASES2:| +- 87: file-table-tform, {81, 86}, tempfiletable, (device-sycl, sm_80)
// DEFAULT-PHASES2:|- 88: clang-offload-wrapper, {87}, object, (device-sycl, sm_80)
// DEFAULT-PHASES2:89: offload, "host-cuda-sycl (x86_64-unknown-linux-gnu)" {15}, "device-sycl (nvptx64-nvidia-cuda:sm_80)" {88}, image | .text
.file "sycl-cuda-tu-offload.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00090e3c_00000000-6_sycl-cuda-tu-offload.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sycl-cuda-tu-offload.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
add_bias(float *a, float *bias, float *out,
int size_x, int size_y, int size_z)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
int k = (i * size_y + j) * size_z;
for (int c = 0; c < size_z; c++)
out[k+c] = a[k+c] + bias[c];
}
} | code for sm_80
Function : _Z8add_biasPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fc80000000f00 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0120*/ @!P0 BRA 0xc40 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R8, -R0, c[0x0][0x180], RZ ; /* 0x0000600000087a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD R7, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005077a24 */
/* 0x000fe200078e0204 */
/*0150*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD R7, R7, c[0x0][0x180], RZ ; /* 0x0000600007077a24 */
/* 0x000fd000078e02ff */
/*01c0*/ @!P0 BRA 0xa40 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x710 ; /* 0x0000051000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea2000c1e1900 */
/*0230*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fca00078e020a */
/*0250*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R13, UR9 ; /* 0x00000009000d7c02 */
/* 0x000fe20008000f00 */
/*0270*/ IMAD.U32 R12, RZ, RZ, UR8 ; /* 0x00000008ff0c7e24 */
/* 0x000fc8000f8e00ff */
/*0280*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0290*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x004fca0000000000 */
/*02a0*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R12.64+0x4], R15 ; /* 0x0000040f0c007986 */
/* 0x0003e8000c101904 */
/*02f0*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R17, [R10.64+0x8] ; /* 0x000008040a117981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x004fca0000000000 */
/*0320*/ STG.E [R12.64+0x8], R17 ; /* 0x000008110c007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R19, [R10.64+0xc] ; /* 0x00000c040a137981 */
/* 0x000ee4000c1e1900 */
/*0350*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x008fca0000000000 */
/*0360*/ STG.E [R12.64+0xc], R19 ; /* 0x00000c130c007986 */
/* 0x0007e8000c101904 */
/*0370*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100402097981 */
/* 0x001f28000c1e1900 */
/*0380*/ LDG.E R14, [R10.64+0x10] ; /* 0x000010040a0e7981 */
/* 0x000f24000c1e1900 */
/*0390*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x010fca0000000000 */
/*03a0*/ STG.E [R12.64+0x10], R9 ; /* 0x000010090c007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000f28000c1e1900 */
/*03c0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f24000c1e1900 */
/*03d0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x010fca0000000000 */
/*03e0*/ STG.E [R12.64+0x14], R15 ; /* 0x0000140f0c007986 */
/* 0x0003e8000c101904 */
/*03f0*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R17, [R10.64+0x18] ; /* 0x000018040a117981 */
/* 0x004f24000c1e1900 */
/*0410*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x010fca0000000000 */
/*0420*/ STG.E [R12.64+0x18], R17 ; /* 0x000018110c007986 */
/* 0x0005e8000c101904 */
/*0430*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000f28000c1e1900 */
/*0440*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x008f24000c1e1900 */
/*0450*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x010fca0000000000 */
/*0460*/ STG.E [R12.64+0x1c], R19 ; /* 0x00001c130c007986 */
/* 0x0007e8000c101904 */
/*0470*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200402097981 */
/* 0x001f28000c1e1900 */
/*0480*/ LDG.E R14, [R10.64+0x20] ; /* 0x000020040a0e7981 */
/* 0x000f24000c1e1900 */
/*0490*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x010fca0000000000 */
/*04a0*/ STG.E [R12.64+0x20], R9 ; /* 0x000020090c007986 */
/* 0x0001e8000c101904 */
/*04b0*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000f28000c1e1900 */
/*04c0*/ LDG.E R15, [R10.64+0x24] ; /* 0x000024040a0f7981 */
/* 0x002f24000c1e1900 */
/*04d0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x010fca0000000000 */
/*04e0*/ STG.E [R12.64+0x24], R15 ; /* 0x0000240f0c007986 */
/* 0x0003e8000c101904 */
/*04f0*/ LDG.E R14, [R2.64+0x28] ; /* 0x00002804020e7981 */
/* 0x000f28000c1e1900 */
/*0500*/ LDG.E R17, [R10.64+0x28] ; /* 0x000028040a117981 */
/* 0x004f24000c1e1900 */
/*0510*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x010fca0000000000 */
/*0520*/ STG.E [R12.64+0x28], R17 ; /* 0x000028110c007986 */
/* 0x0005e8000c101904 */
/*0530*/ LDG.E R14, [R2.64+0x2c] ; /* 0x00002c04020e7981 */
/* 0x000f28000c1e1900 */
/*0540*/ LDG.E R19, [R10.64+0x2c] ; /* 0x00002c040a137981 */
/* 0x008f24000c1e1900 */
/*0550*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x010fca0000000000 */
/*0560*/ STG.E [R12.64+0x2c], R19 ; /* 0x00002c130c007986 */
/* 0x0007e8000c101904 */
/*0570*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */
/* 0x001f28000c1e1900 */
/*0580*/ LDG.E R14, [R10.64+0x30] ; /* 0x000030040a0e7981 */
/* 0x000f24000c1e1900 */
/*0590*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x010fca0000000000 */
/*05a0*/ STG.E [R12.64+0x30], R9 ; /* 0x000030090c007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R14, [R2.64+0x34] ; /* 0x00003404020e7981 */
/* 0x000f28000c1e1900 */
/*05c0*/ LDG.E R15, [R10.64+0x34] ; /* 0x000034040a0f7981 */
/* 0x002f24000c1e1900 */
/*05d0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x010fca0000000000 */
/*05e0*/ STG.E [R12.64+0x34], R15 ; /* 0x0000340f0c007986 */
/* 0x0001e8000c101904 */
/*05f0*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x000f28000c1e1900 */
/*0600*/ LDG.E R17, [R10.64+0x38] ; /* 0x000038040a117981 */
/* 0x004f22000c1e1900 */
/*0610*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0620*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x010fca0000000000 */
/*0630*/ STG.E [R12.64+0x38], R17 ; /* 0x000038110c007986 */
/* 0x0001e8000c101904 */
/*0640*/ LDG.E R19, [R10.64+0x3c] ; /* 0x00003c040a137981 */
/* 0x008ea8000c1e1900 */
/*0650*/ LDG.E R14, [R2.64+0x3c] ; /* 0x00003c04020e7981 */
/* 0x0002a2000c1e1900 */
/*0660*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0670*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fc4000ff1e03f */
/*0680*/ UIADD3 UR8, UP1, UR8, 0x40, URZ ; /* 0x0000004008087890 */
/* 0x000fe4000ff3e03f */
/*0690*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*06a0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe20008ffe43f */
/*06b0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fe40007f5e0ff */
/*06c0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*06e0*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x004fca0000000000 */
/*06f0*/ STG.E [R12.64+0x3c], R19 ; /* 0x00003c130c007986 */
/* 0x0001e2000c101904 */
/*0700*/ @P1 BRA 0x210 ; /* 0xfffffb0000001947 */
/* 0x000fea000383ffff */
/*0710*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0720*/ @!P1 BRA 0xa20 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0730*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0740*/ IMAD.U32 R10, RZ, RZ, UR6 ; /* 0x00000006ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*0750*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea6000c1e1900 */
/*0760*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fca00078e020a */
/*0770*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0780*/ MOV R12, UR8 ; /* 0x00000008000c7c02 */
/* 0x000fe20008000f00 */
/*0790*/ IMAD.U32 R13, RZ, RZ, UR9 ; /* 0x00000009ff0d7e24 */
/* 0x000fc8000f8e00ff */
/*07a0*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*07b0*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x004fca0000000000 */
/*07c0*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e8000c101904 */
/*07d0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x000ea4000c1e1900 */
/*07f0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x004fca0000000000 */
/*0800*/ STG.E [R12.64+0x4], R15 ; /* 0x0000040f0c007986 */
/* 0x0003e8000c101904 */
/*0810*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea8000c1e1900 */
/*0820*/ LDG.E R17, [R10.64+0x8] ; /* 0x000008040a117981 */
/* 0x000ea4000c1e1900 */
/*0830*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x004fca0000000000 */
/*0840*/ STG.E [R12.64+0x8], R17 ; /* 0x000008110c007986 */
/* 0x0005e8000c101904 */
/*0850*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R19, [R10.64+0xc] ; /* 0x00000c040a137981 */
/* 0x000ee4000c1e1900 */
/*0870*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x008fca0000000000 */
/*0880*/ STG.E [R12.64+0xc], R19 ; /* 0x00000c130c007986 */
/* 0x0007e8000c101904 */
/*0890*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100402097981 */
/* 0x001f28000c1e1900 */
/*08a0*/ LDG.E R14, [R10.64+0x10] ; /* 0x000010040a0e7981 */
/* 0x000f24000c1e1900 */
/*08b0*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x010fca0000000000 */
/*08c0*/ STG.E [R12.64+0x10], R9 ; /* 0x000010090c007986 */
/* 0x0001e8000c101904 */
/*08d0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000f28000c1e1900 */
/*08e0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f24000c1e1900 */
/*08f0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x010fca0000000000 */
/*0900*/ STG.E [R12.64+0x14], R15 ; /* 0x0000140f0c007986 */
/* 0x0001e8000c101904 */
/*0910*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000f28000c1e1900 */
/*0920*/ LDG.E R17, [R10.64+0x18] ; /* 0x000018040a117981 */
/* 0x004f24000c1e1900 */
/*0930*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x010fca0000000000 */
/*0940*/ STG.E [R12.64+0x18], R17 ; /* 0x000018110c007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x008ea8000c1e1900 */
/*0960*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x0002a2000c1e1900 */
/*0970*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0980*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0990*/ UIADD3 UR8, UP1, UR8, 0x20, URZ ; /* 0x0000002008087890 */
/* 0x000fe2000ff3e03f */
/*09a0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fc40007ffe0ff */
/*09b0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x002fe20007f3e0ff */
/*09d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc600087fe43f */
/*09e0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*09f0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe20008ffe43f */
/*0a00*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x004fca0000000000 */
/*0a10*/ STG.E [R12.64+0x1c], R19 ; /* 0x00001c130c007986 */
/* 0x0001e8000c101904 */
/*0a20*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a30*/ @!P0 BRA 0xc40 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0a40*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0a50*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fe2000f8e00ff */
/*0a60*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea6000c1e1900 */
/*0a70*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fca00078e020a */
/*0a80*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0a90*/ MOV R12, UR8 ; /* 0x00000008000c7c02 */
/* 0x000fe40008000f00 */
/*0aa0*/ MOV R13, UR9 ; /* 0x00000009000d7c02 */
/* 0x000fca0008000f00 */
/*0ab0*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0ac0*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x004fca0000000000 */
/*0ad0*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e8000c101904 */
/*0ae0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x004fca0000000000 */
/*0b10*/ STG.E [R12.64+0x4], R15 ; /* 0x0000040f0c007986 */
/* 0x0001e8000c101904 */
/*0b20*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea8000c1e1900 */
/*0b30*/ LDG.E R17, [R10.64+0x8] ; /* 0x000008040a117981 */
/* 0x000ea2000c1e1900 */
/*0b40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x004fca0000000000 */
/*0b60*/ STG.E [R12.64+0x8], R17 ; /* 0x000008110c007986 */
/* 0x0001e8000c101904 */
/*0b70*/ LDG.E R19, [R10.64+0xc] ; /* 0x00000c040a137981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0ba0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fc4000ff1e03f */
/*0bb0*/ UIADD3 UR8, UP1, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe4000ff3e03f */
/*0bc0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0bd0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe20008ffe43f */
/*0be0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x002fe40007f3e0ff */
/*0bf0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0c00*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0c10*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x004fca0000000000 */
/*0c20*/ STG.E [R12.64+0xc], R19 ; /* 0x00000c130c007986 */
/* 0x0001e4000c101904 */
/*0c30*/ @P0 BRA 0xa40 ; /* 0xfffffe0000000947 */
/* 0x001fea000383ffff */
/*0c40*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0c50*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c60*/ IMAD R3, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005037a24 */
/* 0x000fe200078e0204 */
/*0c70*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0c80*/ IMAD R4, R3, c[0x0][0x180], R6 ; /* 0x0000600003047a24 */
/* 0x000fce00078e0206 */
/*0c90*/ IMAD.WIDE R6, R6, R5, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0205 */
/*0ca0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fe200078e0205 */
/*0cb0*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fc60000000f00 */
/*0cc0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0cd0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*0ce0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe20000000f00 */
/*0cf0*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x001fe400078e0007 */
/*0d00*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0005 */
/*0d10*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x001fe20000000f00 */
/*0d20*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0d30*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fca0000000f00 */
/*0d40*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0d50*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0002a2000c1e1900 */
/*0d60*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0d70*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*0d80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0d90*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x001fe20000000f00 */
/*0da0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0db0*/ IADD3 R4, P3, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x002fc80007f7e0ff */
/*0dc0*/ IADD3.X R9, RZ, R9, RZ, P3, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20001ffe4ff */
/*0dd0*/ FADD R7, R2, R5 ; /* 0x0000000502077221 */
/* 0x004fe20000000000 */
/*0de0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fe40000000f00 */
/*0df0*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007f5e0ff */
/*0e00*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*0e10*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe200017fe4ff */
/*0e20*/ @P0 BRA 0xd10 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
add_bias(float *a, float *bias, float *out,
int size_x, int size_y, int size_z)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
int k = (i * size_y + j) * size_z;
for (int c = 0; c < size_z; c++)
out[k+c] = a[k+c] + bias[c];
}
} | .file "tmpxft_000c173e_00000000-6_add_bias.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii
.type _Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii, @function
_Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8add_biasPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii, .-_Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii
.globl _Z8add_biasPfS_S_iii
.type _Z8add_biasPfS_S_iii, @function
_Z8add_biasPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8add_biasPfS_S_iii, .-_Z8add_biasPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8add_biasPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8add_biasPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
add_bias(float *a, float *bias, float *out,
int size_x, int size_y, int size_z)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
int k = (i * size_y + j) * size_z;
for (int c = 0; c < size_z; c++)
out[k+c] = a[k+c] + bias[c];
}
} | #include <hip/hip_runtime.h>
__global__ void
add_bias(float *a, float *bias, float *out,
int size_x, int size_y, int size_z)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
int k = (i * size_y + j) * size_z;
for (int c = 0; c < size_z; c++)
out[k+c] = a[k+c] + bias[c];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
add_bias(float *a, float *bias, float *out,
int size_x, int size_y, int size_z)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
int k = (i * size_y + j) * size_z;
for (int c = 0; c < size_z; c++)
out[k+c] = a[k+c] + bias[c];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_biasPfS_S_iii
.globl _Z8add_biasPfS_S_iii
.p2align 8
.type _Z8add_biasPfS_S_iii,@function
_Z8add_biasPfS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v2, s2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v4, s[6:7]
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8add_biasPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8add_biasPfS_S_iii, .Lfunc_end0-_Z8add_biasPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8add_biasPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8add_biasPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
add_bias(float *a, float *bias, float *out,
int size_x, int size_y, int size_z)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size_x && j < size_y)
{
int k = (i * size_y + j) * size_z;
for (int c = 0; c < size_z; c++)
out[k+c] = a[k+c] + bias[c];
}
} | .text
.file "add_bias.hip"
.globl _Z23__device_stub__add_biasPfS_S_iii # -- Begin function _Z23__device_stub__add_biasPfS_S_iii
.p2align 4, 0x90
.type _Z23__device_stub__add_biasPfS_S_iii,@function
_Z23__device_stub__add_biasPfS_S_iii: # @_Z23__device_stub__add_biasPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8add_biasPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__add_biasPfS_S_iii, .Lfunc_end0-_Z23__device_stub__add_biasPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8add_biasPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8add_biasPfS_S_iii,@object # @_Z8add_biasPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z8add_biasPfS_S_iii
.p2align 3, 0x0
_Z8add_biasPfS_S_iii:
.quad _Z23__device_stub__add_biasPfS_S_iii
.size _Z8add_biasPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8add_biasPfS_S_iii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__add_biasPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8add_biasPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8add_biasPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x4], R0 ; /* 0x0000010005057a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fc80000000f00 */
/*00b0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fda0003f06070 */
/*0120*/ @!P0 BRA 0xc40 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R8, -R0, c[0x0][0x180], RZ ; /* 0x0000600000087a10 */
/* 0x000fe20007ffe1ff */
/*0140*/ IMAD R7, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005077a24 */
/* 0x000fe200078e0204 */
/*0150*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000a00 */
/*0160*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0170*/ ISETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f04270 */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*01a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD R7, R7, c[0x0][0x180], RZ ; /* 0x0000600007077a24 */
/* 0x000fd000078e02ff */
/*01c0*/ @!P0 BRA 0xa40 ; /* 0x0000087000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x710 ; /* 0x0000051000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea2000c1e1900 */
/*0230*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fca00078e020a */
/*0250*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R13, UR9 ; /* 0x00000009000d7c02 */
/* 0x000fe20008000f00 */
/*0270*/ IMAD.U32 R12, RZ, RZ, UR8 ; /* 0x00000008ff0c7e24 */
/* 0x000fc8000f8e00ff */
/*0280*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0290*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x004fca0000000000 */
/*02a0*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R12.64+0x4], R15 ; /* 0x0000040f0c007986 */
/* 0x0003e8000c101904 */
/*02f0*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea8000c1e1900 */
/*0300*/ LDG.E R17, [R10.64+0x8] ; /* 0x000008040a117981 */
/* 0x000ea4000c1e1900 */
/*0310*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x004fca0000000000 */
/*0320*/ STG.E [R12.64+0x8], R17 ; /* 0x000008110c007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R19, [R10.64+0xc] ; /* 0x00000c040a137981 */
/* 0x000ee4000c1e1900 */
/*0350*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x008fca0000000000 */
/*0360*/ STG.E [R12.64+0xc], R19 ; /* 0x00000c130c007986 */
/* 0x0007e8000c101904 */
/*0370*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100402097981 */
/* 0x001f28000c1e1900 */
/*0380*/ LDG.E R14, [R10.64+0x10] ; /* 0x000010040a0e7981 */
/* 0x000f24000c1e1900 */
/*0390*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x010fca0000000000 */
/*03a0*/ STG.E [R12.64+0x10], R9 ; /* 0x000010090c007986 */
/* 0x0001e8000c101904 */
/*03b0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000f28000c1e1900 */
/*03c0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f24000c1e1900 */
/*03d0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x010fca0000000000 */
/*03e0*/ STG.E [R12.64+0x14], R15 ; /* 0x0000140f0c007986 */
/* 0x0003e8000c101904 */
/*03f0*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000f28000c1e1900 */
/*0400*/ LDG.E R17, [R10.64+0x18] ; /* 0x000018040a117981 */
/* 0x004f24000c1e1900 */
/*0410*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x010fca0000000000 */
/*0420*/ STG.E [R12.64+0x18], R17 ; /* 0x000018110c007986 */
/* 0x0005e8000c101904 */
/*0430*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x000f28000c1e1900 */
/*0440*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x008f24000c1e1900 */
/*0450*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x010fca0000000000 */
/*0460*/ STG.E [R12.64+0x1c], R19 ; /* 0x00001c130c007986 */
/* 0x0007e8000c101904 */
/*0470*/ LDG.E R9, [R2.64+0x20] ; /* 0x0000200402097981 */
/* 0x001f28000c1e1900 */
/*0480*/ LDG.E R14, [R10.64+0x20] ; /* 0x000020040a0e7981 */
/* 0x000f24000c1e1900 */
/*0490*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x010fca0000000000 */
/*04a0*/ STG.E [R12.64+0x20], R9 ; /* 0x000020090c007986 */
/* 0x0001e8000c101904 */
/*04b0*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000f28000c1e1900 */
/*04c0*/ LDG.E R15, [R10.64+0x24] ; /* 0x000024040a0f7981 */
/* 0x002f24000c1e1900 */
/*04d0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x010fca0000000000 */
/*04e0*/ STG.E [R12.64+0x24], R15 ; /* 0x0000240f0c007986 */
/* 0x0003e8000c101904 */
/*04f0*/ LDG.E R14, [R2.64+0x28] ; /* 0x00002804020e7981 */
/* 0x000f28000c1e1900 */
/*0500*/ LDG.E R17, [R10.64+0x28] ; /* 0x000028040a117981 */
/* 0x004f24000c1e1900 */
/*0510*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x010fca0000000000 */
/*0520*/ STG.E [R12.64+0x28], R17 ; /* 0x000028110c007986 */
/* 0x0005e8000c101904 */
/*0530*/ LDG.E R14, [R2.64+0x2c] ; /* 0x00002c04020e7981 */
/* 0x000f28000c1e1900 */
/*0540*/ LDG.E R19, [R10.64+0x2c] ; /* 0x00002c040a137981 */
/* 0x008f24000c1e1900 */
/*0550*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x010fca0000000000 */
/*0560*/ STG.E [R12.64+0x2c], R19 ; /* 0x00002c130c007986 */
/* 0x0007e8000c101904 */
/*0570*/ LDG.E R9, [R2.64+0x30] ; /* 0x0000300402097981 */
/* 0x001f28000c1e1900 */
/*0580*/ LDG.E R14, [R10.64+0x30] ; /* 0x000030040a0e7981 */
/* 0x000f24000c1e1900 */
/*0590*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x010fca0000000000 */
/*05a0*/ STG.E [R12.64+0x30], R9 ; /* 0x000030090c007986 */
/* 0x0001e8000c101904 */
/*05b0*/ LDG.E R14, [R2.64+0x34] ; /* 0x00003404020e7981 */
/* 0x000f28000c1e1900 */
/*05c0*/ LDG.E R15, [R10.64+0x34] ; /* 0x000034040a0f7981 */
/* 0x002f24000c1e1900 */
/*05d0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x010fca0000000000 */
/*05e0*/ STG.E [R12.64+0x34], R15 ; /* 0x0000340f0c007986 */
/* 0x0001e8000c101904 */
/*05f0*/ LDG.E R14, [R2.64+0x38] ; /* 0x00003804020e7981 */
/* 0x000f28000c1e1900 */
/*0600*/ LDG.E R17, [R10.64+0x38] ; /* 0x000038040a117981 */
/* 0x004f22000c1e1900 */
/*0610*/ IADD3 R8, R8, -0x10, RZ ; /* 0xfffffff008087810 */
/* 0x000fe20007ffe0ff */
/*0620*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x010fca0000000000 */
/*0630*/ STG.E [R12.64+0x38], R17 ; /* 0x000038110c007986 */
/* 0x0001e8000c101904 */
/*0640*/ LDG.E R19, [R10.64+0x3c] ; /* 0x00003c040a137981 */
/* 0x008ea8000c1e1900 */
/*0650*/ LDG.E R14, [R2.64+0x3c] ; /* 0x00003c04020e7981 */
/* 0x0002a2000c1e1900 */
/*0660*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fe20003f24270 */
/*0670*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fc4000ff1e03f */
/*0680*/ UIADD3 UR8, UP1, UR8, 0x40, URZ ; /* 0x0000004008087890 */
/* 0x000fe4000ff3e03f */
/*0690*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*06a0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe20008ffe43f */
/*06b0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x002fe40007f5e0ff */
/*06c0*/ IADD3 R6, R6, 0x10, RZ ; /* 0x0000001006067810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*06e0*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x004fca0000000000 */
/*06f0*/ STG.E [R12.64+0x3c], R19 ; /* 0x00003c130c007986 */
/* 0x0001e2000c101904 */
/*0700*/ @P1 BRA 0x210 ; /* 0xfffffb0000001947 */
/* 0x000fea000383ffff */
/*0710*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*0720*/ @!P1 BRA 0xa20 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*0730*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0740*/ IMAD.U32 R10, RZ, RZ, UR6 ; /* 0x00000006ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*0750*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea6000c1e1900 */
/*0760*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fca00078e020a */
/*0770*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0780*/ MOV R12, UR8 ; /* 0x00000008000c7c02 */
/* 0x000fe20008000f00 */
/*0790*/ IMAD.U32 R13, RZ, RZ, UR9 ; /* 0x00000009ff0d7e24 */
/* 0x000fc8000f8e00ff */
/*07a0*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*07b0*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x004fca0000000000 */
/*07c0*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e8000c101904 */
/*07d0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000ea8000c1e1900 */
/*07e0*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x000ea4000c1e1900 */
/*07f0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x004fca0000000000 */
/*0800*/ STG.E [R12.64+0x4], R15 ; /* 0x0000040f0c007986 */
/* 0x0003e8000c101904 */
/*0810*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea8000c1e1900 */
/*0820*/ LDG.E R17, [R10.64+0x8] ; /* 0x000008040a117981 */
/* 0x000ea4000c1e1900 */
/*0830*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x004fca0000000000 */
/*0840*/ STG.E [R12.64+0x8], R17 ; /* 0x000008110c007986 */
/* 0x0005e8000c101904 */
/*0850*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x000ee8000c1e1900 */
/*0860*/ LDG.E R19, [R10.64+0xc] ; /* 0x00000c040a137981 */
/* 0x000ee4000c1e1900 */
/*0870*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x008fca0000000000 */
/*0880*/ STG.E [R12.64+0xc], R19 ; /* 0x00000c130c007986 */
/* 0x0007e8000c101904 */
/*0890*/ LDG.E R9, [R2.64+0x10] ; /* 0x0000100402097981 */
/* 0x001f28000c1e1900 */
/*08a0*/ LDG.E R14, [R10.64+0x10] ; /* 0x000010040a0e7981 */
/* 0x000f24000c1e1900 */
/*08b0*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x010fca0000000000 */
/*08c0*/ STG.E [R12.64+0x10], R9 ; /* 0x000010090c007986 */
/* 0x0001e8000c101904 */
/*08d0*/ LDG.E R14, [R2.64+0x14] ; /* 0x00001404020e7981 */
/* 0x000f28000c1e1900 */
/*08e0*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f24000c1e1900 */
/*08f0*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x010fca0000000000 */
/*0900*/ STG.E [R12.64+0x14], R15 ; /* 0x0000140f0c007986 */
/* 0x0001e8000c101904 */
/*0910*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000f28000c1e1900 */
/*0920*/ LDG.E R17, [R10.64+0x18] ; /* 0x000018040a117981 */
/* 0x004f24000c1e1900 */
/*0930*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x010fca0000000000 */
/*0940*/ STG.E [R12.64+0x18], R17 ; /* 0x000018110c007986 */
/* 0x0001e8000c101904 */
/*0950*/ LDG.E R19, [R10.64+0x1c] ; /* 0x00001c040a137981 */
/* 0x008ea8000c1e1900 */
/*0960*/ LDG.E R14, [R2.64+0x1c] ; /* 0x00001c04020e7981 */
/* 0x0002a2000c1e1900 */
/*0970*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0980*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0990*/ UIADD3 UR8, UP1, UR8, 0x20, URZ ; /* 0x0000002008087890 */
/* 0x000fe2000ff3e03f */
/*09a0*/ IADD3 R6, R6, 0x8, RZ ; /* 0x0000000806067810 */
/* 0x000fc40007ffe0ff */
/*09b0*/ IADD3 R8, R8, -0x8, RZ ; /* 0xfffffff808087810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R2, P1, R2, 0x20, RZ ; /* 0x0000002002027810 */
/* 0x002fe20007f3e0ff */
/*09d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fc600087fe43f */
/*09e0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*09f0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe20008ffe43f */
/*0a00*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x004fca0000000000 */
/*0a10*/ STG.E [R12.64+0x1c], R19 ; /* 0x00001c130c007986 */
/* 0x0001e8000c101904 */
/*0a20*/ ISETP.NE.OR P0, PT, R8, RZ, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0000705670 */
/*0a30*/ @!P0 BRA 0xc40 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0a40*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe20008000f00 */
/*0a50*/ IMAD.U32 R11, RZ, RZ, UR7 ; /* 0x00000007ff0b7e24 */
/* 0x000fe2000f8e00ff */
/*0a60*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea6000c1e1900 */
/*0a70*/ IMAD.WIDE R10, R7, 0x4, R10 ; /* 0x00000004070a7825 */
/* 0x000fca00078e020a */
/*0a80*/ LDG.E R14, [R10.64] ; /* 0x000000040a0e7981 */
/* 0x000ea2000c1e1900 */
/*0a90*/ MOV R12, UR8 ; /* 0x00000008000c7c02 */
/* 0x000fe40008000f00 */
/*0aa0*/ MOV R13, UR9 ; /* 0x00000009000d7c02 */
/* 0x000fca0008000f00 */
/*0ab0*/ IMAD.WIDE R12, R7, 0x4, R12 ; /* 0x00000004070c7825 */
/* 0x000fc800078e020c */
/*0ac0*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x004fca0000000000 */
/*0ad0*/ STG.E [R12.64], R9 ; /* 0x000000090c007986 */
/* 0x0001e8000c101904 */
/*0ae0*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000ea8000c1e1900 */
/*0af0*/ LDG.E R15, [R10.64+0x4] ; /* 0x000004040a0f7981 */
/* 0x000ea4000c1e1900 */
/*0b00*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x004fca0000000000 */
/*0b10*/ STG.E [R12.64+0x4], R15 ; /* 0x0000040f0c007986 */
/* 0x0001e8000c101904 */
/*0b20*/ LDG.E R14, [R2.64+0x8] ; /* 0x00000804020e7981 */
/* 0x000ea8000c1e1900 */
/*0b30*/ LDG.E R17, [R10.64+0x8] ; /* 0x000008040a117981 */
/* 0x000ea2000c1e1900 */
/*0b40*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0b50*/ FADD R17, R14, R17 ; /* 0x000000110e117221 */
/* 0x004fca0000000000 */
/*0b60*/ STG.E [R12.64+0x8], R17 ; /* 0x000008110c007986 */
/* 0x0001e8000c101904 */
/*0b70*/ LDG.E R19, [R10.64+0xc] ; /* 0x00000c040a137981 */
/* 0x000ea8000c1e1900 */
/*0b80*/ LDG.E R14, [R2.64+0xc] ; /* 0x00000c04020e7981 */
/* 0x0002a2000c1e1900 */
/*0b90*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0ba0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fc4000ff1e03f */
/*0bb0*/ UIADD3 UR8, UP1, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe4000ff3e03f */
/*0bc0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0bd0*/ UIADD3.X UR9, URZ, UR9, URZ, UP1, !UPT ; /* 0x000000093f097290 */
/* 0x000fe20008ffe43f */
/*0be0*/ IADD3 R2, P1, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x002fe40007f3e0ff */
/*0bf0*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007ffe0ff */
/*0c00*/ IMAD.X R3, RZ, RZ, R3, P1 ; /* 0x000000ffff037224 */
/* 0x000fe400008e0603 */
/*0c10*/ FADD R19, R14, R19 ; /* 0x000000130e137221 */
/* 0x004fca0000000000 */
/*0c20*/ STG.E [R12.64+0xc], R19 ; /* 0x00000c130c007986 */
/* 0x0001e4000c101904 */
/*0c30*/ @P0 BRA 0xa40 ; /* 0xfffffe0000000947 */
/* 0x001fea000383ffff */
/*0c40*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0c50*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c60*/ IMAD R3, R5, c[0x0][0x17c], R4 ; /* 0x00005f0005037a24 */
/* 0x000fe200078e0204 */
/*0c70*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0c80*/ IMAD R4, R3, c[0x0][0x180], R6 ; /* 0x0000600003047a24 */
/* 0x000fce00078e0206 */
/*0c90*/ IMAD.WIDE R6, R6, R5, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0205 */
/*0ca0*/ IMAD.WIDE R2, R4, R5, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fe200078e0205 */
/*0cb0*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fc60000000f00 */
/*0cc0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0205 */
/*0cd0*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*0ce0*/ MOV R11, R3 ; /* 0x00000003000b7202 */
/* 0x000fe20000000f00 */
/*0cf0*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x001fe400078e0007 */
/*0d00*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0005 */
/*0d10*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x001fe20000000f00 */
/*0d20*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0d30*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fca0000000f00 */
/*0d40*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x0000a8000c1e1900 */
/*0d50*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x0002a2000c1e1900 */
/*0d60*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0d70*/ IADD3 R8, P1, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe40007f3e0ff */
/*0d80*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0d90*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x001fe20000000f00 */
/*0da0*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0db0*/ IADD3 R4, P3, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x002fc80007f7e0ff */
/*0dc0*/ IADD3.X R9, RZ, R9, RZ, P3, !PT ; /* 0x00000009ff097210 */
/* 0x000fe20001ffe4ff */
/*0dd0*/ FADD R7, R2, R5 ; /* 0x0000000502077221 */
/* 0x004fe20000000000 */
/*0de0*/ MOV R2, R6 ; /* 0x0000000600027202 */
/* 0x000fe40000000f00 */
/*0df0*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fc60007f5e0ff */
/*0e00*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e2000c101904 */
/*0e10*/ IADD3.X R11, RZ, R11, RZ, P2, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe200017fe4ff */
/*0e20*/ @P0 BRA 0xd10 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_biasPfS_S_iii
.globl _Z8add_biasPfS_S_iii
.p2align 8
.type _Z8add_biasPfS_S_iii,@function
_Z8add_biasPfS_S_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v2, s2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
.p2align 6
.LBB0_3:
global_load_b32 v5, v[0:1], off
global_load_b32 v6, v4, s[6:7]
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_i32 s2, s2, -1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s2, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v5, v5, v6
global_store_b32 v[2:3], v5, off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8add_biasPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8add_biasPfS_S_iii, .Lfunc_end0-_Z8add_biasPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8add_biasPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8add_biasPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c173e_00000000-6_add_bias.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii
.type _Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii, @function
_Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8add_biasPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii, .-_Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii
.globl _Z8add_biasPfS_S_iii
.type _Z8add_biasPfS_S_iii, @function
_Z8add_biasPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z8add_biasPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8add_biasPfS_S_iii, .-_Z8add_biasPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8add_biasPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8add_biasPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_bias.hip"
.globl _Z23__device_stub__add_biasPfS_S_iii # -- Begin function _Z23__device_stub__add_biasPfS_S_iii
.p2align 4, 0x90
.type _Z23__device_stub__add_biasPfS_S_iii,@function
_Z23__device_stub__add_biasPfS_S_iii: # @_Z23__device_stub__add_biasPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8add_biasPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z23__device_stub__add_biasPfS_S_iii, .Lfunc_end0-_Z23__device_stub__add_biasPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8add_biasPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8add_biasPfS_S_iii,@object # @_Z8add_biasPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z8add_biasPfS_S_iii
.p2align 3, 0x0
_Z8add_biasPfS_S_iii:
.quad _Z23__device_stub__add_biasPfS_S_iii
.size _Z8add_biasPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8add_biasPfS_S_iii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__add_biasPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8add_biasPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <vector>
#define MAX_THREADS 256
#define SIZE 131072
#define __START__ cudaEventCreate(&start); cudaEventCreate(&stop); cudaEventRecord(start, 0);
#define __STOP__(_V) cudaEventRecord(stop, 0); cudaEventSynchronize(stop); cudaEventElapsedTime(&time, start, stop); _V.push_back(time); cudaEventDestroy(start); cudaEventDestroy(stop);
#define __NEXT__(_V) __STOP__(_V) __START__
template<class T>
__global__ void square_kernel(T *d_vector)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i >= SIZE)
return;
d_vector[i] = d_vector[i]*d_vector[i];
}
void showMean(std::vector<float> v)
{
float sum(0);
for (unsigned int i(0) ; i!=v.size() ; i++)
sum += v[i];
std::cout << 1000.*sum/v.size() << " microseconds" << std::endl;
}
int main(int argc, char **argv)
{
std::cout << "SIZE (Datatype): " << SIZE << std::endl;
cudaEvent_t start, stop;
std::vector<float> intRun, floatRun, doubleRun;
float time(0);
cudaFree(0); // Force runtime API context establishment
int h_vector_i[SIZE]; // For input and output
float h_vector_f[SIZE]; // For input and output
double h_vector_d[SIZE]; // For input and output
for (unsigned int i(0) ; i!=SIZE ; i++)
{
h_vector_i[i] = i;
h_vector_f[i] = i;
h_vector_d[i] = i;
}
for (unsigned int i(0) ; i!=1000 ; i++)
{
int *d_vector_i;
float *d_vector_f;
double *d_vector_d;
/* INT */
cudaMalloc(&d_vector_i, SIZE*sizeof(int));
cudaMemcpy(d_vector_i, h_vector_i, SIZE*sizeof(int), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_i);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(intRun);
cudaMemcpy(h_vector_i, d_vector_i, SIZE*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_vector_i);
/* FLOAT */
cudaMalloc(&d_vector_f, SIZE*sizeof(float));
cudaMemcpy(d_vector_f, h_vector_f, SIZE*sizeof(float), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_f);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(floatRun);
cudaMemcpy(h_vector_f, d_vector_f, SIZE*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_vector_f);
/* DOUBLE */
cudaMalloc(&d_vector_d, SIZE*sizeof(double));
cudaMemcpy(d_vector_d, h_vector_d, SIZE*sizeof(double), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_d);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(doubleRun);
cudaMemcpy(h_vector_d, d_vector_d, SIZE*sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(d_vector_d);
}
showMean(intRun);
showMean(floatRun);
showMean(doubleRun);
} | code for sm_80
Function : _Z13square_kernelIdEvPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1ffff, PT ; /* 0x0001ffff0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x004e0e0000000000 */
/*00b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13square_kernelIfEvPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1ffff, PT ; /* 0x0001ffff0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13square_kernelIiEvPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1ffff, PT ; /* 0x0001ffff0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <vector>
#define MAX_THREADS 256
#define SIZE 131072
#define __START__ cudaEventCreate(&start); cudaEventCreate(&stop); cudaEventRecord(start, 0);
#define __STOP__(_V) cudaEventRecord(stop, 0); cudaEventSynchronize(stop); cudaEventElapsedTime(&time, start, stop); _V.push_back(time); cudaEventDestroy(start); cudaEventDestroy(stop);
#define __NEXT__(_V) __STOP__(_V) __START__
template<class T>
__global__ void square_kernel(T *d_vector)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i >= SIZE)
return;
d_vector[i] = d_vector[i]*d_vector[i];
}
void showMean(std::vector<float> v)
{
float sum(0);
for (unsigned int i(0) ; i!=v.size() ; i++)
sum += v[i];
std::cout << 1000.*sum/v.size() << " microseconds" << std::endl;
}
int main(int argc, char **argv)
{
std::cout << "SIZE (Datatype): " << SIZE << std::endl;
cudaEvent_t start, stop;
std::vector<float> intRun, floatRun, doubleRun;
float time(0);
cudaFree(0); // Force runtime API context establishment
int h_vector_i[SIZE]; // For input and output
float h_vector_f[SIZE]; // For input and output
double h_vector_d[SIZE]; // For input and output
for (unsigned int i(0) ; i!=SIZE ; i++)
{
h_vector_i[i] = i;
h_vector_f[i] = i;
h_vector_d[i] = i;
}
for (unsigned int i(0) ; i!=1000 ; i++)
{
int *d_vector_i;
float *d_vector_f;
double *d_vector_d;
/* INT */
cudaMalloc(&d_vector_i, SIZE*sizeof(int));
cudaMemcpy(d_vector_i, h_vector_i, SIZE*sizeof(int), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_i);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(intRun);
cudaMemcpy(h_vector_i, d_vector_i, SIZE*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_vector_i);
/* FLOAT */
cudaMalloc(&d_vector_f, SIZE*sizeof(float));
cudaMemcpy(d_vector_f, h_vector_f, SIZE*sizeof(float), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_f);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(floatRun);
cudaMemcpy(h_vector_f, d_vector_f, SIZE*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_vector_f);
/* DOUBLE */
cudaMalloc(&d_vector_d, SIZE*sizeof(double));
cudaMemcpy(d_vector_d, h_vector_d, SIZE*sizeof(double), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_d);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(doubleRun);
cudaMemcpy(h_vector_d, d_vector_d, SIZE*sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(d_vector_d);
}
showMean(intRun);
showMean(floatRun);
showMean(doubleRun);
} | .file "tmpxft_0007d1f0_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL38__device_stub__Z13square_kernelIiEvPT_Pi, @function
_ZL38__device_stub__Z13square_kernelIiEvPT_Pi:
.LFB4070:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13square_kernelIiEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4070:
.size _ZL38__device_stub__Z13square_kernelIiEvPT_Pi, .-_ZL38__device_stub__Z13square_kernelIiEvPT_Pi
.section .text._Z13square_kernelIiEvPT_,"axG",@progbits,_Z13square_kernelIiEvPT_,comdat
.weak _Z13square_kernelIiEvPT_
.type _Z13square_kernelIiEvPT_, @function
_Z13square_kernelIiEvPT_:
.LFB4396:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL38__device_stub__Z13square_kernelIiEvPT_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4396:
.size _Z13square_kernelIiEvPT_, .-_Z13square_kernelIiEvPT_
.text
.type _ZL38__device_stub__Z13square_kernelIfEvPT_Pf, @function
_ZL38__device_stub__Z13square_kernelIfEvPT_Pf:
.LFB4072:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13square_kernelIfEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4072:
.size _ZL38__device_stub__Z13square_kernelIfEvPT_Pf, .-_ZL38__device_stub__Z13square_kernelIfEvPT_Pf
.section .text._Z13square_kernelIfEvPT_,"axG",@progbits,_Z13square_kernelIfEvPT_,comdat
.weak _Z13square_kernelIfEvPT_
.type _Z13square_kernelIfEvPT_, @function
_Z13square_kernelIfEvPT_:
.LFB4400:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL38__device_stub__Z13square_kernelIfEvPT_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4400:
.size _Z13square_kernelIfEvPT_, .-_Z13square_kernelIfEvPT_
.text
.type _ZL38__device_stub__Z13square_kernelIdEvPT_Pd, @function
_ZL38__device_stub__Z13square_kernelIdEvPT_Pd:
.LFB4074:
.cfi_startproc
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13square_kernelIdEvPT_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4074:
.size _ZL38__device_stub__Z13square_kernelIdEvPT_Pd, .-_ZL38__device_stub__Z13square_kernelIdEvPT_Pd
.section .text._Z13square_kernelIdEvPT_,"axG",@progbits,_Z13square_kernelIdEvPT_,comdat
.weak _Z13square_kernelIdEvPT_
.type _Z13square_kernelIdEvPT_, @function
_Z13square_kernelIdEvPT_:
.LFB4402:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL38__device_stub__Z13square_kernelIdEvPT_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4402:
.size _Z13square_kernelIdEvPT_, .-_Z13square_kernelIdEvPT_
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4048:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4048:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " microseconds"
.text
.globl _Z8showMeanSt6vectorIfSaIfEE
.type _Z8showMeanSt6vectorIfSaIfEE, @function
_Z8showMeanSt6vectorIfSaIfEE:
.LFB4034:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq (%rdi), %rsi
movq 8(%rdi), %rcx
subq %rsi, %rcx
sarq $2, %rcx
je .L35
movl $0, %edx
pxor %xmm0, %xmm0
movl $0, %eax
.L29:
addss (%rsi,%rax,4), %xmm0
addl $1, %edx
movl %edx, %eax
cmpq %rcx, %rax
jne .L29
.L28:
cvtss2sd %xmm0, %xmm0
mulsd .LC1(%rip), %xmm0
testq %rcx, %rcx
js .L30
pxor %xmm1, %xmm1
cvtsi2sdq %rcx, %xmm1
.L31:
divsd %xmm1, %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movl $13, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L38
cmpb $0, 56(%rbp)
je .L33
movzbl 67(%rbp), %esi
.L34:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
pxor %xmm0, %xmm0
jmp .L28
.L30:
movq %rcx, %rax
shrq %rax
andl $1, %ecx
orq %rcx, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L31
.L38:
call _ZSt16__throw_bad_castv@PLT
.L33:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L34
.cfi_endproc
.LFE4034:
.size _Z8showMeanSt6vectorIfSaIfEE, .-_Z8showMeanSt6vectorIfSaIfEE
.section .rodata.str1.1
.LC3:
.string "_Z13square_kernelIdEvPT_"
.LC4:
.string "_Z13square_kernelIfEvPT_"
.LC5:
.string "_Z13square_kernelIiEvPT_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4077:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13square_kernelIdEvPT_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13square_kernelIfEvPT_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13square_kernelIiEvPT_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4077:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4393:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L44
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L44:
ret
.cfi_endproc
.LFE4393:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .text._ZNSt6vectorIfSaIfEEC2ERKS1_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5ERKS1_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEEC2ERKS1_
.type _ZNSt6vectorIfSaIfEEC2ERKS1_, @function
_ZNSt6vectorIfSaIfEEC2ERKS1_:
.LFB4404:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r13
movq 8(%rsi), %r12
subq (%rsi), %r12
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
je .L52
movabsq $9223372036854775804, %rax
cmpq %r12, %rax
jb .L54
movq %r12, %rdi
call _Znwm@PLT
movq %rax, %rbp
.L48:
movq %rbp, (%rbx)
movq %rbp, 8(%rbx)
addq %rbp, %r12
movq %r12, 16(%rbx)
movq 0(%r13), %rsi
movq 8(%r13), %r12
subq %rsi, %r12
cmpq $4, %r12
jle .L50
movq %r12, %rdx
movq %rbp, %rdi
call memmove@PLT
.L51:
addq %r12, %rbp
movq %rbp, 8(%rbx)
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore_state
call _ZSt28__throw_bad_array_new_lengthv@PLT
.L52:
movl $0, %ebp
jmp .L48
.L50:
jne .L51
movss (%rsi), %xmm0
movss %xmm0, 0(%rbp)
jmp .L51
.cfi_endproc
.LFE4404:
.size _ZNSt6vectorIfSaIfEEC2ERKS1_, .-_ZNSt6vectorIfSaIfEEC2ERKS1_
.weak _ZNSt6vectorIfSaIfEEC1ERKS1_
.set _ZNSt6vectorIfSaIfEEC1ERKS1_,_ZNSt6vectorIfSaIfEEC2ERKS1_
.section .rodata._ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC6:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_
.type _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_, @function
_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_:
.LFB4563:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L72
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L58
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L59
jmp .L66
.L72:
leaq .LC6(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L73:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L61
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L65
.L58:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L66:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L59:
movq 8(%rsp), %rax
movss (%rax), %xmm0
movss %xmm0, (%r12,%r15)
testq %r15, %r15
jg .L73
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L63
.L61:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L63:
addq %rbp, %r15
testq %r13, %r13
je .L64
movq 16(%rbx), %rsi
subq %r13, %rsi
.L65:
movq %r13, %rdi
call _ZdlPvm@PLT
.L64:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4563:
.size _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_, .-_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_
.section .rodata.str1.1
.LC7:
.string "SIZE (Datatype): "
.text
.globl main
.type main, @function
main:
.LFB4035:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4035
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -2097152(%rsp), %r11
.cfi_def_cfa 11, 2097176
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $216, %rsp
.cfi_def_cfa_offset 2097392
movq %fs:40, %rax
movq %rax, 2097352(%rsp)
xorl %eax, %eax
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $131072, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE0:
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movq $0, 96(%rsp)
movq $0, 104(%rsp)
movq $0, 112(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movl $0x00000000, 4(%rsp)
movl $0, %edi
.LEHB1:
call cudaFree@PLT
movl $0, %eax
.L79:
movl %eax, 192(%rsp,%rax,4)
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, 524480(%rsp,%rax,4)
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
movsd %xmm0, 1048768(%rsp,%rax,8)
addq $1, %rax
cmpq $131072, %rax
jne .L79
movl $1000, %ebx
leaq 24(%rsp), %rbp
jmp .L89
.L108:
leaq 192(%rsp), %rsi
movl $1, %ecx
movl $524288, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L80
movq 24(%rsp), %rdi
call _ZL38__device_stub__Z13square_kernelIiEvPT_Pi
.L80:
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 72(%rsp), %rsi
cmpq 80(%rsp), %rsi
je .L81
movss 4(%rsp), %xmm0
movss %xmm0, (%rsi)
addq $4, %rsi
movq %rsi, 72(%rsp)
.L82:
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
jmp .L104
.L81:
leaq 4(%rsp), %rdx
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_
jmp .L82
.L104:
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
leaq 192(%rsp), %rdi
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq 32(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 524480(%rsp), %rsi
movl $1, %ecx
movl $524288, %edx
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L83
movq 32(%rsp), %rdi
call _ZL38__device_stub__Z13square_kernelIfEvPT_Pf
.L83:
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 104(%rsp), %rsi
cmpq 112(%rsp), %rsi
je .L84
movss 4(%rsp), %xmm0
movss %xmm0, (%rsi)
addq $4, %rsi
movq %rsi, 104(%rsp)
.L85:
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
jmp .L105
.L84:
leaq 4(%rsp), %rdx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_
jmp .L85
.L105:
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
leaq 524480(%rsp), %rdi
movl $2, %ecx
movl $524288, %edx
movq 32(%rsp), %rsi
call cudaMemcpy@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
leaq 40(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 1048768(%rsp), %rsi
movl $1, %ecx
movl $1048576, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $256, 160(%rsp)
movl $1, 164(%rsp)
movl $1, 168(%rsp)
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 160(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L86
movq 40(%rsp), %rdi
call _ZL38__device_stub__Z13square_kernelIdEvPT_Pd
.L86:
call cudaThreadSynchronize@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 136(%rsp), %rsi
cmpq 144(%rsp), %rsi
je .L87
movss 4(%rsp), %xmm0
movss %xmm0, (%rsi)
addq $4, %rsi
movq %rsi, 136(%rsp)
.L88:
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
jmp .L106
.L87:
leaq 4(%rsp), %rdx
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_
jmp .L88
.L106:
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
leaq 1048768(%rsp), %rdi
movl $2, %ecx
movl $1048576, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
subl $1, %ebx
je .L107
.L89:
movl $524288, %esi
movq %rbp, %rdi
call cudaMalloc@PLT
jmp .L108
.L107:
leaq 64(%rsp), %rsi
leaq 160(%rsp), %rdi
call _ZNSt6vectorIfSaIfEEC1ERKS1_
.LEHE1:
leaq 160(%rsp), %rdi
.LEHB2:
call _Z8showMeanSt6vectorIfSaIfEE
.LEHE2:
leaq 160(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rsi
movq %rbx, %rdi
.LEHB3:
call _ZNSt6vectorIfSaIfEEC1ERKS1_
.LEHE3:
movq %rbx, %rdi
.LEHB4:
call _Z8showMeanSt6vectorIfSaIfEE
.LEHE4:
movq %rbx, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 128(%rsp), %rsi
movq %rbx, %rdi
.LEHB5:
call _ZNSt6vectorIfSaIfEEC1ERKS1_
.LEHE5:
movq %rbx, %rdi
.LEHB6:
call _Z8showMeanSt6vectorIfSaIfEE
.LEHE6:
movq %rbx, %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 2097352(%rsp), %rax
subq %fs:40, %rax
jne .L109
movl $0, %eax
addq $2097368, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L97:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 160(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L91:
leaq 128(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 2097352(%rsp), %rax
subq %fs:40, %rax
je .L94
call __stack_chk_fail@PLT
.L98:
endbr64
movq %rax, %rbx
leaq 160(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L91
.L99:
endbr64
movq %rax, %rbx
leaq 160(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
jmp .L91
.L96:
endbr64
movq %rax, %rbx
jmp .L91
.L94:
movq %rbx, %rdi
.LEHB7:
call _Unwind_Resume@PLT
.LEHE7:
.L109:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4035:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4035:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4035-.LLSDACSB4035
.LLSDACSB4035:
.uleb128 .LEHB0-.LFB4035
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4035
.uleb128 .LEHE1-.LEHB1
.uleb128 .L96-.LFB4035
.uleb128 0
.uleb128 .LEHB2-.LFB4035
.uleb128 .LEHE2-.LEHB2
.uleb128 .L97-.LFB4035
.uleb128 0
.uleb128 .LEHB3-.LFB4035
.uleb128 .LEHE3-.LEHB3
.uleb128 .L96-.LFB4035
.uleb128 0
.uleb128 .LEHB4-.LFB4035
.uleb128 .LEHE4-.LEHB4
.uleb128 .L98-.LFB4035
.uleb128 0
.uleb128 .LEHB5-.LFB4035
.uleb128 .LEHE5-.LEHB5
.uleb128 .L96-.LFB4035
.uleb128 0
.uleb128 .LEHB6-.LFB4035
.uleb128 .LEHE6-.LEHB6
.uleb128 .L99-.LFB4035
.uleb128 0
.uleb128 .LEHB7-.LFB4035
.uleb128 .LEHE7-.LEHB7
.uleb128 0
.uleb128 0
.LLSDACSE4035:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1083129856
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <vector>
#define MAX_THREADS 256
#define SIZE 131072
#define __START__ cudaEventCreate(&start); cudaEventCreate(&stop); cudaEventRecord(start, 0);
#define __STOP__(_V) cudaEventRecord(stop, 0); cudaEventSynchronize(stop); cudaEventElapsedTime(&time, start, stop); _V.push_back(time); cudaEventDestroy(start); cudaEventDestroy(stop);
#define __NEXT__(_V) __STOP__(_V) __START__
template<class T>
__global__ void square_kernel(T *d_vector)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i >= SIZE)
return;
d_vector[i] = d_vector[i]*d_vector[i];
}
void showMean(std::vector<float> v)
{
float sum(0);
for (unsigned int i(0) ; i!=v.size() ; i++)
sum += v[i];
std::cout << 1000.*sum/v.size() << " microseconds" << std::endl;
}
int main(int argc, char **argv)
{
std::cout << "SIZE (Datatype): " << SIZE << std::endl;
cudaEvent_t start, stop;
std::vector<float> intRun, floatRun, doubleRun;
float time(0);
cudaFree(0); // Force runtime API context establishment
int h_vector_i[SIZE]; // For input and output
float h_vector_f[SIZE]; // For input and output
double h_vector_d[SIZE]; // For input and output
for (unsigned int i(0) ; i!=SIZE ; i++)
{
h_vector_i[i] = i;
h_vector_f[i] = i;
h_vector_d[i] = i;
}
for (unsigned int i(0) ; i!=1000 ; i++)
{
int *d_vector_i;
float *d_vector_f;
double *d_vector_d;
/* INT */
cudaMalloc(&d_vector_i, SIZE*sizeof(int));
cudaMemcpy(d_vector_i, h_vector_i, SIZE*sizeof(int), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_i);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(intRun);
cudaMemcpy(h_vector_i, d_vector_i, SIZE*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(d_vector_i);
/* FLOAT */
cudaMalloc(&d_vector_f, SIZE*sizeof(float));
cudaMemcpy(d_vector_f, h_vector_f, SIZE*sizeof(float), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_f);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(floatRun);
cudaMemcpy(h_vector_f, d_vector_f, SIZE*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(d_vector_f);
/* DOUBLE */
cudaMalloc(&d_vector_d, SIZE*sizeof(double));
cudaMemcpy(d_vector_d, h_vector_d, SIZE*sizeof(double), cudaMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_d);
cudaThreadSynchronize(); // Block until the device is finished
__STOP__(doubleRun);
cudaMemcpy(h_vector_d, d_vector_d, SIZE*sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(d_vector_d);
}
showMean(intRun);
showMean(floatRun);
showMean(doubleRun);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <vector>
#define MAX_THREADS 256
#define SIZE 131072
#define __START__ hipEventCreate(&start); hipEventCreate(&stop); hipEventRecord(start, 0);
#define __STOP__(_V) hipEventRecord(stop, 0); hipEventSynchronize(stop); hipEventElapsedTime(&time, start, stop); _V.push_back(time); hipEventDestroy(start); hipEventDestroy(stop);
#define __NEXT__(_V) __STOP__(_V) __START__
template<class T>
__global__ void square_kernel(T *d_vector)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i >= SIZE)
return;
d_vector[i] = d_vector[i]*d_vector[i];
}
void showMean(std::vector<float> v)
{
float sum(0);
for (unsigned int i(0) ; i!=v.size() ; i++)
sum += v[i];
std::cout << 1000.*sum/v.size() << " microseconds" << std::endl;
}
int main(int argc, char **argv)
{
std::cout << "SIZE (Datatype): " << SIZE << std::endl;
hipEvent_t start, stop;
std::vector<float> intRun, floatRun, doubleRun;
float time(0);
hipFree(0); // Force runtime API context establishment
int h_vector_i[SIZE]; // For input and output
float h_vector_f[SIZE]; // For input and output
double h_vector_d[SIZE]; // For input and output
for (unsigned int i(0) ; i!=SIZE ; i++)
{
h_vector_i[i] = i;
h_vector_f[i] = i;
h_vector_d[i] = i;
}
for (unsigned int i(0) ; i!=1000 ; i++)
{
int *d_vector_i;
float *d_vector_f;
double *d_vector_d;
/* INT */
hipMalloc(&d_vector_i, SIZE*sizeof(int));
hipMemcpy(d_vector_i, h_vector_i, SIZE*sizeof(int), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_i);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(intRun);
hipMemcpy(h_vector_i, d_vector_i, SIZE*sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_vector_i);
/* FLOAT */
hipMalloc(&d_vector_f, SIZE*sizeof(float));
hipMemcpy(d_vector_f, h_vector_f, SIZE*sizeof(float), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_f);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(floatRun);
hipMemcpy(h_vector_f, d_vector_f, SIZE*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_vector_f);
/* DOUBLE */
hipMalloc(&d_vector_d, SIZE*sizeof(double));
hipMemcpy(d_vector_d, h_vector_d, SIZE*sizeof(double), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_d);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(doubleRun);
hipMemcpy(h_vector_d, d_vector_d, SIZE*sizeof(double), hipMemcpyDeviceToHost);
hipFree(d_vector_d);
}
showMean(intRun);
showMean(floatRun);
showMean(doubleRun);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <vector>
#define MAX_THREADS 256
#define SIZE 131072
#define __START__ hipEventCreate(&start); hipEventCreate(&stop); hipEventRecord(start, 0);
#define __STOP__(_V) hipEventRecord(stop, 0); hipEventSynchronize(stop); hipEventElapsedTime(&time, start, stop); _V.push_back(time); hipEventDestroy(start); hipEventDestroy(stop);
#define __NEXT__(_V) __STOP__(_V) __START__
template<class T>
__global__ void square_kernel(T *d_vector)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i >= SIZE)
return;
d_vector[i] = d_vector[i]*d_vector[i];
}
void showMean(std::vector<float> v)
{
float sum(0);
for (unsigned int i(0) ; i!=v.size() ; i++)
sum += v[i];
std::cout << 1000.*sum/v.size() << " microseconds" << std::endl;
}
int main(int argc, char **argv)
{
std::cout << "SIZE (Datatype): " << SIZE << std::endl;
hipEvent_t start, stop;
std::vector<float> intRun, floatRun, doubleRun;
float time(0);
hipFree(0); // Force runtime API context establishment
int h_vector_i[SIZE]; // For input and output
float h_vector_f[SIZE]; // For input and output
double h_vector_d[SIZE]; // For input and output
for (unsigned int i(0) ; i!=SIZE ; i++)
{
h_vector_i[i] = i;
h_vector_f[i] = i;
h_vector_d[i] = i;
}
for (unsigned int i(0) ; i!=1000 ; i++)
{
int *d_vector_i;
float *d_vector_f;
double *d_vector_d;
/* INT */
hipMalloc(&d_vector_i, SIZE*sizeof(int));
hipMemcpy(d_vector_i, h_vector_i, SIZE*sizeof(int), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_i);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(intRun);
hipMemcpy(h_vector_i, d_vector_i, SIZE*sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_vector_i);
/* FLOAT */
hipMalloc(&d_vector_f, SIZE*sizeof(float));
hipMemcpy(d_vector_f, h_vector_f, SIZE*sizeof(float), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_f);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(floatRun);
hipMemcpy(h_vector_f, d_vector_f, SIZE*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_vector_f);
/* DOUBLE */
hipMalloc(&d_vector_d, SIZE*sizeof(double));
hipMemcpy(d_vector_d, h_vector_d, SIZE*sizeof(double), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_d);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(doubleRun);
hipMemcpy(h_vector_d, d_vector_d, SIZE*sizeof(double), hipMemcpyDeviceToHost);
hipFree(d_vector_d);
}
showMean(intRun);
showMean(floatRun);
showMean(doubleRun);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z13square_kernelIiEvPT_,"axG",@progbits,_Z13square_kernelIiEvPT_,comdat
.protected _Z13square_kernelIiEvPT_
.globl _Z13square_kernelIiEvPT_
.p2align 8
.type _Z13square_kernelIiEvPT_,@function
_Z13square_kernelIiEvPT_:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x20000, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13square_kernelIiEvPT_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13square_kernelIiEvPT_,"axG",@progbits,_Z13square_kernelIiEvPT_,comdat
.Lfunc_end0:
.size _Z13square_kernelIiEvPT_, .Lfunc_end0-_Z13square_kernelIiEvPT_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z13square_kernelIfEvPT_,"axG",@progbits,_Z13square_kernelIfEvPT_,comdat
.protected _Z13square_kernelIfEvPT_
.globl _Z13square_kernelIfEvPT_
.p2align 8
.type _Z13square_kernelIfEvPT_,@function
_Z13square_kernelIfEvPT_:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x20000, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13square_kernelIfEvPT_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13square_kernelIfEvPT_,"axG",@progbits,_Z13square_kernelIfEvPT_,comdat
.Lfunc_end1:
.size _Z13square_kernelIfEvPT_, .Lfunc_end1-_Z13square_kernelIfEvPT_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z13square_kernelIdEvPT_,"axG",@progbits,_Z13square_kernelIdEvPT_,comdat
.protected _Z13square_kernelIdEvPT_
.globl _Z13square_kernelIdEvPT_
.p2align 8
.type _Z13square_kernelIdEvPT_,@function
_Z13square_kernelIdEvPT_:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x20000, v1
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13square_kernelIdEvPT_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13square_kernelIdEvPT_,"axG",@progbits,_Z13square_kernelIdEvPT_,comdat
.Lfunc_end2:
.size _Z13square_kernelIdEvPT_, .Lfunc_end2-_Z13square_kernelIdEvPT_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13square_kernelIiEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13square_kernelIiEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13square_kernelIfEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13square_kernelIfEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13square_kernelIdEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13square_kernelIdEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdio.h>
#include <vector>
#define MAX_THREADS 256
#define SIZE 131072
#define __START__ hipEventCreate(&start); hipEventCreate(&stop); hipEventRecord(start, 0);
#define __STOP__(_V) hipEventRecord(stop, 0); hipEventSynchronize(stop); hipEventElapsedTime(&time, start, stop); _V.push_back(time); hipEventDestroy(start); hipEventDestroy(stop);
#define __NEXT__(_V) __STOP__(_V) __START__
template<class T>
__global__ void square_kernel(T *d_vector)
{
int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i >= SIZE)
return;
d_vector[i] = d_vector[i]*d_vector[i];
}
void showMean(std::vector<float> v)
{
float sum(0);
for (unsigned int i(0) ; i!=v.size() ; i++)
sum += v[i];
std::cout << 1000.*sum/v.size() << " microseconds" << std::endl;
}
int main(int argc, char **argv)
{
std::cout << "SIZE (Datatype): " << SIZE << std::endl;
hipEvent_t start, stop;
std::vector<float> intRun, floatRun, doubleRun;
float time(0);
hipFree(0); // Force runtime API context establishment
int h_vector_i[SIZE]; // For input and output
float h_vector_f[SIZE]; // For input and output
double h_vector_d[SIZE]; // For input and output
for (unsigned int i(0) ; i!=SIZE ; i++)
{
h_vector_i[i] = i;
h_vector_f[i] = i;
h_vector_d[i] = i;
}
for (unsigned int i(0) ; i!=1000 ; i++)
{
int *d_vector_i;
float *d_vector_f;
double *d_vector_d;
/* INT */
hipMalloc(&d_vector_i, SIZE*sizeof(int));
hipMemcpy(d_vector_i, h_vector_i, SIZE*sizeof(int), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_i);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(intRun);
hipMemcpy(h_vector_i, d_vector_i, SIZE*sizeof(int), hipMemcpyDeviceToHost);
hipFree(d_vector_i);
/* FLOAT */
hipMalloc(&d_vector_f, SIZE*sizeof(float));
hipMemcpy(d_vector_f, h_vector_f, SIZE*sizeof(float), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_f);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(floatRun);
hipMemcpy(h_vector_f, d_vector_f, SIZE*sizeof(float), hipMemcpyDeviceToHost);
hipFree(d_vector_f);
/* DOUBLE */
hipMalloc(&d_vector_d, SIZE*sizeof(double));
hipMemcpy(d_vector_d, h_vector_d, SIZE*sizeof(double), hipMemcpyHostToDevice);
__START__
square_kernel<<<(SIZE+MAX_THREADS-1)/MAX_THREADS, MAX_THREADS>>>(d_vector_d);
hipDeviceSynchronize(); // Block until the device is finished
__STOP__(doubleRun);
hipMemcpy(h_vector_d, d_vector_d, SIZE*sizeof(double), hipMemcpyDeviceToHost);
hipFree(d_vector_d);
}
showMean(intRun);
showMean(floatRun);
showMean(doubleRun);
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8showMeanSt6vectorIfSaIfEE
.LCPI0_0:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl _Z8showMeanSt6vectorIfSaIfEE
.p2align 4, 0x90
.type _Z8showMeanSt6vectorIfSaIfEE,@function
_Z8showMeanSt6vectorIfSaIfEE: # @_Z8showMeanSt6vectorIfSaIfEE
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq (%rdi), %rcx
movq 8(%rdi), %rdx
movq %rdx, %rax
subq %rcx, %rax
sarq $2, %rax
cmpq %rcx, %rdx
je .LBB0_1
# %bb.8: # %.lr.ph.preheader
xorps %xmm0, %xmm0
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_9: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addss (%rcx,%rdx,4), %xmm0
incq %rdx
movl %edx, %esi
cmpq %rsi, %rax
jne .LBB0_9
# %bb.2: # %._crit_edge.loopexit
cvtss2sd %xmm0, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
jmp .LBB0_3
.LBB0_1:
xorpd %xmm0, %xmm0
.LBB0_3: # %._crit_edge
movq %rax, %xmm1
punpckldq .LCPI0_1(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI0_2(%rip), %xmm1
movapd %xmm1, %xmm2
unpckhpd %xmm1, %xmm2 # xmm2 = xmm2[1],xmm1[1]
addsd %xmm1, %xmm2
divsd %xmm2, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str, %esi
movl $13, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_10
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_6
# %bb.5:
movzbl 67(%r14), %eax
jmp .LBB0_7
.LBB0_6:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB0_10:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size _Z8showMeanSt6vectorIfSaIfEE, .Lfunc_end0-_Z8showMeanSt6vectorIfSaIfEE
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $2097432, %rsp # imm = 0x200118
.cfi_def_cfa_offset 2097488
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $131072, %esi # imm = 0x20000
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_163
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB1_4
.LBB1_3:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
.cfi_escape 0x2e, 0x00
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
movl $0, 4(%rsp)
.Ltmp0:
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq hipFree
.Ltmp1:
# %bb.5:
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movl %eax, %ecx
xorps %xmm0, %xmm0
cvtsi2ss %rcx, %xmm0
movss %xmm0, 272(%rsp,%rax,4)
xorps %xmm0, %xmm0
cvtsi2sd %rcx, %xmm0
movl %eax, 524560(%rsp,%rax,4)
movsd %xmm0, 1048848(%rsp,%rax,8)
incq %rax
cmpq $131072, %rax # imm = 0x20000
jne .LBB1_6
# %bb.7: # %.preheader
movl $1000, %ebp # imm = 0x3E8
xorl %eax, %eax
movq %rax, 40(%rsp) # 8-byte Spill
xorl %ebx, %ebx
xorl %eax, %eax
movq %rax, 168(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 32(%rsp) # 8-byte Spill
xorl %r13d, %r13d
xorl %eax, %eax
movq %rax, 160(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 24(%rsp) # 8-byte Spill
xorl %r12d, %r12d
xorl %eax, %eax
movq %rax, 152(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_8: # =>This Inner Loop Header: Depth=1
.Ltmp3:
.cfi_escape 0x2e, 0x00
movl $524288, %esi # imm = 0x80000
leaq 136(%rsp), %rdi
callq hipMalloc
.Ltmp4:
# %bb.9: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
# in Loop: Header=BB1_8 Depth=1
movq 136(%rsp), %rdi
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl $524288, %edx # imm = 0x80000
leaq 524560(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp6:
# %bb.10: # in Loop: Header=BB1_8 Depth=1
.Ltmp7:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp8:
# %bb.11: # in Loop: Header=BB1_8 Depth=1
.Ltmp9:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp10:
# %bb.12: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rdi
.Ltmp11:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp12:
# %bb.13: # in Loop: Header=BB1_8 Depth=1
.Ltmp13:
.cfi_escape 0x2e, 0x00
movabsq $4294967808, %rdi # imm = 0x100000200
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp14:
# %bb.14: # in Loop: Header=BB1_8 Depth=1
movl %ebp, 148(%rsp) # 4-byte Spill
testl %eax, %eax
jne .LBB1_17
# %bb.15: # in Loop: Header=BB1_8 Depth=1
movq 136(%rsp), %rax
movq %rax, 112(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
.Ltmp15:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp16:
# %bb.16: # %.noexc35
# in Loop: Header=BB1_8 Depth=1
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp17:
.cfi_escape 0x2e, 0x10
movl $_Z13square_kernelIiEvPT_, %edi
leaq 48(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp18:
.LBB1_17: # in Loop: Header=BB1_8 Depth=1
.Ltmp19:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp20:
# %bb.18: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp21:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp22:
# %bb.19: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp23:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp24:
# %bb.20: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp25:
.cfi_escape 0x2e, 0x00
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp26:
# %bb.21: # in Loop: Header=BB1_8 Depth=1
cmpq 168(%rsp), %rbx # 8-byte Folded Reload
je .LBB1_23
# %bb.22: # in Loop: Header=BB1_8 Depth=1
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rbx)
jmp .LBB1_37
.p2align 4, 0x90
.LBB1_23: # in Loop: Header=BB1_8 Depth=1
subq 40(%rsp), %rbx # 8-byte Folded Reload
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %rbx
je .LBB1_159
# %bb.24: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB1_8 Depth=1
movq %rbx, %rbp
sarq $2, %rbp
cmpq $1, %rbp
movq %rbp, %rax
adcq $0, %rax
leaq (%rax,%rbp), %rcx
movabsq $2305843009213693951, %r14 # imm = 0x1FFFFFFFFFFFFFFF
cmpq %r14, %rcx
jb .LBB1_25
# %bb.29: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB1_8 Depth=1
movq %r14, %rcx
addq %rbp, %rax
jae .LBB1_30
.LBB1_26: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB1_8 Depth=1
testq %r14, %r14
je .LBB1_31
.LBB1_27: # in Loop: Header=BB1_8 Depth=1
leaq (,%r14,4), %rdi
.Ltmp27:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp28:
# %bb.28: # in Loop: Header=BB1_8 Depth=1
movq %rax, %r15
jmp .LBB1_32
.p2align 4, 0x90
.LBB1_25: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB1_8 Depth=1
addq %rbp, %rax
jb .LBB1_26
.LBB1_30: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i
# in Loop: Header=BB1_8 Depth=1
movq %rcx, %r14
testq %r14, %r14
jne .LBB1_27
.LBB1_31: # in Loop: Header=BB1_8 Depth=1
xorl %r15d, %r15d
.LBB1_32: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit.i.i
# in Loop: Header=BB1_8 Depth=1
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r15,%rbp,4)
testq %rbx, %rbx
movq 40(%rsp), %rbp # 8-byte Reload
jle .LBB1_34
# %bb.33: # in Loop: Header=BB1_8 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rbp, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB1_34: # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit.i.i
# in Loop: Header=BB1_8 Depth=1
testq %rbp, %rbp
je .LBB1_36
# %bb.35: # in Loop: Header=BB1_8 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZdlPv
.LBB1_36: # %_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.exit.i
# in Loop: Header=BB1_8 Depth=1
addq %r15, %rbx
leaq (%r15,%r14,4), %rax
movq %rax, 168(%rsp) # 8-byte Spill
movq %r15, 40(%rsp) # 8-byte Spill
.LBB1_37: # %_ZNSt6vectorIfSaIfEE9push_backERKf.exit
# in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rdi
.Ltmp29:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp30:
# %bb.38: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp32:
# %bb.39: # in Loop: Header=BB1_8 Depth=1
movq 136(%rsp), %rsi
.Ltmp33:
.cfi_escape 0x2e, 0x00
movl $524288, %edx # imm = 0x80000
leaq 524560(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp34:
# %bb.40: # in Loop: Header=BB1_8 Depth=1
movq 136(%rsp), %rdi
.Ltmp35:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp36:
# %bb.41: # in Loop: Header=BB1_8 Depth=1
.Ltmp37:
.cfi_escape 0x2e, 0x00
movl $524288, %esi # imm = 0x80000
leaq 128(%rsp), %rdi
callq hipMalloc
.Ltmp38:
# %bb.42: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
# in Loop: Header=BB1_8 Depth=1
movq 128(%rsp), %rdi
.Ltmp39:
.cfi_escape 0x2e, 0x00
movl $524288, %edx # imm = 0x80000
leaq 272(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp40:
# %bb.43: # in Loop: Header=BB1_8 Depth=1
.Ltmp41:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp42:
# %bb.44: # in Loop: Header=BB1_8 Depth=1
.Ltmp43:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp44:
# %bb.45: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rdi
.Ltmp45:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp46:
# %bb.46: # in Loop: Header=BB1_8 Depth=1
.Ltmp47:
.cfi_escape 0x2e, 0x00
movabsq $4294967808, %rdi # imm = 0x100000200
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp48:
# %bb.47: # in Loop: Header=BB1_8 Depth=1
testl %eax, %eax
jne .LBB1_50
# %bb.48: # in Loop: Header=BB1_8 Depth=1
movq 128(%rsp), %rax
movq %rax, 112(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
.Ltmp49:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp50:
# %bb.49: # %.noexc46
# in Loop: Header=BB1_8 Depth=1
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp51:
.cfi_escape 0x2e, 0x10
movl $_Z13square_kernelIfEvPT_, %edi
leaq 48(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp52:
.LBB1_50: # in Loop: Header=BB1_8 Depth=1
.Ltmp53:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp54:
# %bb.51: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp55:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp56:
# %bb.52: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp57:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp58:
# %bb.53: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp59:
.cfi_escape 0x2e, 0x00
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp60:
# %bb.54: # in Loop: Header=BB1_8 Depth=1
cmpq 160(%rsp), %r13 # 8-byte Folded Reload
je .LBB1_56
# %bb.55: # in Loop: Header=BB1_8 Depth=1
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r13)
jmp .LBB1_70
.p2align 4, 0x90
.LBB1_56: # in Loop: Header=BB1_8 Depth=1
subq 32(%rsp), %r13 # 8-byte Folded Reload
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r13
je .LBB1_161
# %bb.57: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i49
# in Loop: Header=BB1_8 Depth=1
movq %r13, %rbp
sarq $2, %rbp
cmpq $1, %rbp
movq %rbp, %rax
adcq $0, %rax
leaq (%rax,%rbp), %rcx
movabsq $2305843009213693951, %r14 # imm = 0x1FFFFFFFFFFFFFFF
cmpq %r14, %rcx
jb .LBB1_58
# %bb.62: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i49
# in Loop: Header=BB1_8 Depth=1
movq %r14, %rcx
addq %rbp, %rax
jae .LBB1_63
.LBB1_59: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i49
# in Loop: Header=BB1_8 Depth=1
testq %r14, %r14
je .LBB1_64
.LBB1_60: # in Loop: Header=BB1_8 Depth=1
leaq (,%r14,4), %rdi
.Ltmp61:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp62:
# %bb.61: # in Loop: Header=BB1_8 Depth=1
movq %rax, %r15
jmp .LBB1_65
.p2align 4, 0x90
.LBB1_58: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i49
# in Loop: Header=BB1_8 Depth=1
addq %rbp, %rax
jb .LBB1_59
.LBB1_63: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i49
# in Loop: Header=BB1_8 Depth=1
movq %rcx, %r14
testq %r14, %r14
jne .LBB1_60
.LBB1_64: # in Loop: Header=BB1_8 Depth=1
xorl %r15d, %r15d
.LBB1_65: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit.i.i52
# in Loop: Header=BB1_8 Depth=1
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r15,%rbp,4)
testq %r13, %r13
movq 32(%rsp), %rbp # 8-byte Reload
jle .LBB1_67
# %bb.66: # in Loop: Header=BB1_8 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rbp, %rsi
movq %r13, %rdx
callq memmove@PLT
.LBB1_67: # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit.i.i53
# in Loop: Header=BB1_8 Depth=1
testq %rbp, %rbp
je .LBB1_69
# %bb.68: # in Loop: Header=BB1_8 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZdlPv
.LBB1_69: # %_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.exit.i55
# in Loop: Header=BB1_8 Depth=1
addq %r15, %r13
leaq (%r15,%r14,4), %rax
movq %rax, 160(%rsp) # 8-byte Spill
movq %r15, 32(%rsp) # 8-byte Spill
.LBB1_70: # %_ZNSt6vectorIfSaIfEE9push_backERKf.exit58
# in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rdi
.Ltmp63:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp64:
# %bb.71: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp65:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp66:
# %bb.72: # in Loop: Header=BB1_8 Depth=1
movq 128(%rsp), %rsi
.Ltmp67:
.cfi_escape 0x2e, 0x00
movl $524288, %edx # imm = 0x80000
leaq 272(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp68:
# %bb.73: # in Loop: Header=BB1_8 Depth=1
movq 128(%rsp), %rdi
.Ltmp69:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp70:
# %bb.74: # in Loop: Header=BB1_8 Depth=1
.Ltmp71:
.cfi_escape 0x2e, 0x00
movl $1048576, %esi # imm = 0x100000
leaq 120(%rsp), %rdi
callq hipMalloc
.Ltmp72:
# %bb.75: # %_ZL9hipMallocIdE10hipError_tPPT_m.exit
# in Loop: Header=BB1_8 Depth=1
movq 120(%rsp), %rdi
.Ltmp73:
.cfi_escape 0x2e, 0x00
movl $1048576, %edx # imm = 0x100000
leaq 1048848(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp74:
# %bb.76: # in Loop: Header=BB1_8 Depth=1
.Ltmp75:
.cfi_escape 0x2e, 0x00
leaq 16(%rsp), %rdi
callq hipEventCreate
.Ltmp76:
# %bb.77: # in Loop: Header=BB1_8 Depth=1
.Ltmp77:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
callq hipEventCreate
.Ltmp78:
# %bb.78: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rdi
.Ltmp79:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp80:
# %bb.79: # in Loop: Header=BB1_8 Depth=1
.Ltmp81:
.cfi_escape 0x2e, 0x00
movabsq $4294967808, %rdi # imm = 0x100000200
movl $1, %esi
movabsq $4294967552, %rdx # imm = 0x100000100
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp82:
# %bb.80: # in Loop: Header=BB1_8 Depth=1
testl %eax, %eax
jne .LBB1_83
# %bb.81: # in Loop: Header=BB1_8 Depth=1
movq 120(%rsp), %rax
movq %rax, 112(%rsp)
leaq 112(%rsp), %rax
movq %rax, 48(%rsp)
.Ltmp83:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp84:
# %bb.82: # %.noexc66
# in Loop: Header=BB1_8 Depth=1
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp85:
.cfi_escape 0x2e, 0x10
movl $_Z13square_kernelIdEvPT_, %edi
leaq 48(%rsp), %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp86:
.LBB1_83: # in Loop: Header=BB1_8 Depth=1
.Ltmp87:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp88:
# %bb.84: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp89:
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq hipEventRecord
.Ltmp90:
# %bb.85: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp91:
.cfi_escape 0x2e, 0x00
callq hipEventSynchronize
.Ltmp92:
# %bb.86: # in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp93:
.cfi_escape 0x2e, 0x00
leaq 4(%rsp), %rdi
callq hipEventElapsedTime
.Ltmp94:
# %bb.87: # in Loop: Header=BB1_8 Depth=1
cmpq 152(%rsp), %r12 # 8-byte Folded Reload
je .LBB1_89
# %bb.88: # in Loop: Header=BB1_8 Depth=1
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r12)
jmp .LBB1_103
.p2align 4, 0x90
.LBB1_89: # in Loop: Header=BB1_8 Depth=1
subq 24(%rsp), %r12 # 8-byte Folded Reload
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %r12
je .LBB1_157
# %bb.90: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i69
# in Loop: Header=BB1_8 Depth=1
movq %r12, %rbp
sarq $2, %rbp
cmpq $1, %rbp
movq %rbp, %rax
adcq $0, %rax
leaq (%rax,%rbp), %rcx
movabsq $2305843009213693951, %r14 # imm = 0x1FFFFFFFFFFFFFFF
cmpq %r14, %rcx
jb .LBB1_91
# %bb.95: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i69
# in Loop: Header=BB1_8 Depth=1
movq %r14, %rcx
addq %rbp, %rax
jae .LBB1_96
.LBB1_92: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i69
# in Loop: Header=BB1_8 Depth=1
testq %r14, %r14
je .LBB1_97
.LBB1_93: # in Loop: Header=BB1_8 Depth=1
leaq (,%r14,4), %rdi
.Ltmp95:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp96:
# %bb.94: # in Loop: Header=BB1_8 Depth=1
movq %rax, %r15
jmp .LBB1_98
.p2align 4, 0x90
.LBB1_91: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i69
# in Loop: Header=BB1_8 Depth=1
addq %rbp, %rax
jb .LBB1_92
.LBB1_96: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i69
# in Loop: Header=BB1_8 Depth=1
movq %rcx, %r14
testq %r14, %r14
jne .LBB1_93
.LBB1_97: # in Loop: Header=BB1_8 Depth=1
xorl %r15d, %r15d
.LBB1_98: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit.i.i72
# in Loop: Header=BB1_8 Depth=1
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r15,%rbp,4)
testq %r12, %r12
movq 24(%rsp), %rbp # 8-byte Reload
jle .LBB1_100
# %bb.99: # in Loop: Header=BB1_8 Depth=1
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
movq %rbp, %rsi
movq %r12, %rdx
callq memmove@PLT
.LBB1_100: # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit.i.i73
# in Loop: Header=BB1_8 Depth=1
testq %rbp, %rbp
je .LBB1_102
# %bb.101: # in Loop: Header=BB1_8 Depth=1
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZdlPv
.LBB1_102: # %_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJRKfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.exit.i75
# in Loop: Header=BB1_8 Depth=1
addq %r15, %r12
leaq (%r15,%r14,4), %rax
movq %rax, 152(%rsp) # 8-byte Spill
movq %r15, 24(%rsp) # 8-byte Spill
.LBB1_103: # %_ZNSt6vectorIfSaIfEE9push_backERKf.exit78
# in Loop: Header=BB1_8 Depth=1
movq 16(%rsp), %rdi
.Ltmp97:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp98:
movl 148(%rsp), %ebp # 4-byte Reload
# %bb.104: # in Loop: Header=BB1_8 Depth=1
movq 8(%rsp), %rdi
.Ltmp99:
.cfi_escape 0x2e, 0x00
callq hipEventDestroy
.Ltmp100:
# %bb.105: # in Loop: Header=BB1_8 Depth=1
movq 120(%rsp), %rsi
.Ltmp101:
.cfi_escape 0x2e, 0x00
movl $1048576, %edx # imm = 0x100000
leaq 1048848(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp102:
# %bb.106: # in Loop: Header=BB1_8 Depth=1
movq 120(%rsp), %rdi
.Ltmp103:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp104:
# %bb.107: # in Loop: Header=BB1_8 Depth=1
addq $4, %rbx
addq $4, %r13
addq $4, %r12
decl %ebp
jne .LBB1_8
# %bb.108:
movq %rbx, %r15
movq 40(%rsp), %rbp # 8-byte Reload
subq %rbp, %r15
sarq $2, %r15
xorpd %xmm0, %xmm0
movapd %xmm0, 240(%rsp)
movq $0, 256(%rsp)
subq %rbp, %rbx
je .LBB1_112
# %bb.109:
movabsq $2305843009213693951, %rax # imm = 0x1FFFFFFFFFFFFFFF
cmpq %rax, %r15
ja .LBB1_154
# %bb.110: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i
.Ltmp106:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Znwm
.Ltmp107:
# %bb.111:
movq %rax, %r14
jmp .LBB1_113
.LBB1_112:
xorl %r14d, %r14d
.LBB1_113: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movq %r14, 240(%rsp)
movq %r14, 248(%rsp)
leaq (%r14,%r15,4), %rax
movq %rax, 256(%rsp)
cmpq $5, %rbx
jl .LBB1_148
# %bb.114:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq %rbp, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB1_115: # %_ZNSt6vectorIfSaIfEEC2ERKS1_.exit
addq %r14, %rbx
movq %rbx, 248(%rsp)
.Ltmp108:
.cfi_escape 0x2e, 0x00
leaq 240(%rsp), %rdi
callq _Z8showMeanSt6vectorIfSaIfEE
.Ltmp109:
# %bb.116:
testq %r14, %r14
je .LBB1_118
# %bb.117:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_118: # %_ZNSt6vectorIfSaIfEED2Ev.exit
movq %r13, %rbx
movq 32(%rsp), %rax # 8-byte Reload
subq %rax, %rbx
sarq $2, %rbx
xorpd %xmm0, %xmm0
movapd %xmm0, 208(%rsp)
movq $0, 224(%rsp)
subq %rax, %r13
je .LBB1_122
# %bb.119:
movabsq $2305843009213693951, %rax # imm = 0x1FFFFFFFFFFFFFFF
cmpq %rax, %rbx
ja .LBB1_145
# %bb.120: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i81
.Ltmp111:
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
callq _Znwm
.Ltmp112:
# %bb.121:
movq %rax, %r14
jmp .LBB1_123
.LBB1_122:
xorl %r14d, %r14d
.LBB1_123: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i82
movq %r14, 208(%rsp)
movq %r14, 216(%rsp)
leaq (%r14,%rbx,4), %rax
movq %rax, 224(%rsp)
cmpq $5, %r13
jl .LBB1_150
# %bb.124:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq 32(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
callq memmove@PLT
.LBB1_125: # %_ZNSt6vectorIfSaIfEEC2ERKS1_.exit88
addq %r14, %r13
movq %r13, 216(%rsp)
.Ltmp113:
.cfi_escape 0x2e, 0x00
leaq 208(%rsp), %rdi
callq _Z8showMeanSt6vectorIfSaIfEE
.Ltmp114:
# %bb.126:
testq %r14, %r14
movabsq $2305843009213693951, %r15 # imm = 0x1FFFFFFFFFFFFFFF
je .LBB1_128
# %bb.127:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_128: # %_ZNSt6vectorIfSaIfEED2Ev.exit90
movq %r12, %rbx
movq 24(%rsp), %rax # 8-byte Reload
subq %rax, %rbx
sarq $2, %rbx
xorpd %xmm0, %xmm0
movapd %xmm0, 176(%rsp)
movq $0, 192(%rsp)
subq %rax, %r12
je .LBB1_132
# %bb.129:
cmpq %r15, %rbx
ja .LBB1_145
# %bb.130: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i92
.Ltmp116:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Znwm
.Ltmp117:
# %bb.131:
movq %rax, %r14
jmp .LBB1_133
.LBB1_132:
xorl %r14d, %r14d
.LBB1_133: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i93
movq %r14, 176(%rsp)
movq %r14, 184(%rsp)
leaq (%r14,%rbx,4), %rax
movq %rax, 192(%rsp)
cmpq $5, %r12
jl .LBB1_152
# %bb.134:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
movq 24(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
callq memmove@PLT
.LBB1_135: # %_ZNSt6vectorIfSaIfEEC2ERKS1_.exit99
addq %r14, %r12
movq %r12, 184(%rsp)
.Ltmp123:
.cfi_escape 0x2e, 0x00
leaq 176(%rsp), %rdi
callq _Z8showMeanSt6vectorIfSaIfEE
.Ltmp124:
# %bb.136:
testq %r14, %r14
je .LBB1_138
# %bb.137:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_138: # %_ZNSt6vectorIfSaIfEED2Ev.exit101
movq 24(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB1_140
# %bb.139:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_140: # %_ZNSt6vectorIfSaIfEED2Ev.exit103
movq 32(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB1_142
# %bb.141:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_142: # %_ZNSt6vectorIfSaIfEED2Ev.exit105
testq %rbp, %rbp
je .LBB1_144
# %bb.143:
.cfi_escape 0x2e, 0x00
movq %rbp, %rdi
callq _ZdlPv
.LBB1_144: # %_ZNSt6vectorIfSaIfEED2Ev.exit107
xorl %eax, %eax
addq $2097432, %rsp # imm = 0x200118
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_145:
.cfi_def_cfa_offset 2097488
shrq $62, %rbx
je .LBB1_155
.LBB1_146: # %.noexc.i.i95.invoke
.Ltmp120:
.cfi_escape 0x2e, 0x00
callq _ZSt28__throw_bad_array_new_lengthv
.Ltmp121:
# %bb.147: # %.noexc.i.i95.cont
.LBB1_148:
cmpq $4, %rbx
jne .LBB1_115
# %bb.149:
movss (%rbp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r14)
jmp .LBB1_115
.LBB1_150:
cmpq $4, %r13
jne .LBB1_125
# %bb.151:
movq 32(%rsp), %rax # 8-byte Reload
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r14)
jmp .LBB1_125
.LBB1_152:
cmpq $4, %r12
jne .LBB1_135
# %bb.153:
movq 24(%rsp), %rax # 8-byte Reload
movss (%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r14)
jmp .LBB1_135
.LBB1_154:
shrq $62, %r15
jne .LBB1_146
.LBB1_155: # %.noexc4.i.i94.invoke
.Ltmp118:
.cfi_escape 0x2e, 0x00
callq _ZSt17__throw_bad_allocv
.Ltmp119:
# %bb.156: # %.noexc4.i.i94.cont
.LBB1_157:
.Ltmp126:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp127:
# %bb.158: # %.noexc76
.LBB1_159:
.Ltmp130:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp131:
# %bb.160: # %.noexc37
.LBB1_161:
.Ltmp128:
.cfi_escape 0x2e, 0x00
movl $.L.str.2, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp129:
# %bb.162: # %.noexc56
.LBB1_163:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.LBB1_164:
.Ltmp125:
movq %rax, %rbx
testq %r14, %r14
je .LBB1_176
# %bb.165:
.cfi_escape 0x2e, 0x00
jmp .LBB1_170
.LBB1_166:
.Ltmp115:
movq %rax, %rbx
testq %r14, %r14
je .LBB1_176
# %bb.167:
.cfi_escape 0x2e, 0x00
jmp .LBB1_170
.LBB1_168:
.Ltmp110:
movq %rax, %rbx
testq %r14, %r14
je .LBB1_176
# %bb.169:
.cfi_escape 0x2e, 0x00
.LBB1_170: # %_ZNSt6vectorIfSaIfEED2Ev.exit109
movq %r14, %rdi
callq _ZdlPv
jmp .LBB1_176
.LBB1_171:
.Ltmp2:
movq %rax, %rbx
xorl %eax, %eax
movq %rax, 24(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 32(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 40(%rsp) # 8-byte Spill
jmp .LBB1_176
.LBB1_172: # %.loopexit.split-lp
.Ltmp132:
jmp .LBB1_175
.LBB1_173:
.Ltmp122:
jmp .LBB1_175
.LBB1_174: # %.loopexit
.Ltmp105:
.LBB1_175:
movq %rax, %rbx
.LBB1_176:
movq 24(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
movq 40(%rsp), %r14 # 8-byte Reload
je .LBB1_178
# %bb.177:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
.LBB1_178: # %_ZNSt6vectorIfSaIfEED2Ev.exit115
movq 32(%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
jne .LBB1_181
# %bb.179: # %_ZNSt6vectorIfSaIfEED2Ev.exit117
testq %r14, %r14
jne .LBB1_182
.LBB1_180: # %_ZNSt6vectorIfSaIfEED2Ev.exit119
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.LBB1_181:
.cfi_escape 0x2e, 0x00
callq _ZdlPv
testq %r14, %r14
je .LBB1_180
.LBB1_182:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp28-.Ltmp3 # Call between .Ltmp3 and .Ltmp28
.uleb128 .Ltmp105-.Lfunc_begin0 # jumps to .Ltmp105
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp29-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp62-.Ltmp29 # Call between .Ltmp29 and .Ltmp62
.uleb128 .Ltmp105-.Lfunc_begin0 # jumps to .Ltmp105
.byte 0 # On action: cleanup
.uleb128 .Ltmp62-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp63-.Ltmp62 # Call between .Ltmp62 and .Ltmp63
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp96-.Ltmp63 # Call between .Ltmp63 and .Ltmp96
.uleb128 .Ltmp105-.Lfunc_begin0 # jumps to .Ltmp105
.byte 0 # On action: cleanup
.uleb128 .Ltmp96-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp97-.Ltmp96 # Call between .Ltmp96 and .Ltmp97
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp97-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp104-.Ltmp97 # Call between .Ltmp97 and .Ltmp104
.uleb128 .Ltmp105-.Lfunc_begin0 # jumps to .Ltmp105
.byte 0 # On action: cleanup
.uleb128 .Ltmp106-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp107-.Ltmp106 # Call between .Ltmp106 and .Ltmp107
.uleb128 .Ltmp122-.Lfunc_begin0 # jumps to .Ltmp122
.byte 0 # On action: cleanup
.uleb128 .Ltmp107-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp108-.Ltmp107 # Call between .Ltmp107 and .Ltmp108
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp108-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp109-.Ltmp108 # Call between .Ltmp108 and .Ltmp109
.uleb128 .Ltmp110-.Lfunc_begin0 # jumps to .Ltmp110
.byte 0 # On action: cleanup
.uleb128 .Ltmp111-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp112-.Ltmp111 # Call between .Ltmp111 and .Ltmp112
.uleb128 .Ltmp122-.Lfunc_begin0 # jumps to .Ltmp122
.byte 0 # On action: cleanup
.uleb128 .Ltmp112-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp113-.Ltmp112 # Call between .Ltmp112 and .Ltmp113
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp113-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp114-.Ltmp113 # Call between .Ltmp113 and .Ltmp114
.uleb128 .Ltmp115-.Lfunc_begin0 # jumps to .Ltmp115
.byte 0 # On action: cleanup
.uleb128 .Ltmp116-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp117-.Ltmp116 # Call between .Ltmp116 and .Ltmp117
.uleb128 .Ltmp122-.Lfunc_begin0 # jumps to .Ltmp122
.byte 0 # On action: cleanup
.uleb128 .Ltmp117-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp123-.Ltmp117 # Call between .Ltmp117 and .Ltmp123
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp123-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp124-.Ltmp123 # Call between .Ltmp123 and .Ltmp124
.uleb128 .Ltmp125-.Lfunc_begin0 # jumps to .Ltmp125
.byte 0 # On action: cleanup
.uleb128 .Ltmp120-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp119-.Ltmp120 # Call between .Ltmp120 and .Ltmp119
.uleb128 .Ltmp122-.Lfunc_begin0 # jumps to .Ltmp122
.byte 0 # On action: cleanup
.uleb128 .Ltmp126-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Ltmp129-.Ltmp126 # Call between .Ltmp126 and .Ltmp129
.uleb128 .Ltmp132-.Lfunc_begin0 # jumps to .Ltmp132
.byte 0 # On action: cleanup
.uleb128 .Ltmp129-.Lfunc_begin0 # >> Call Site 21 <<
.uleb128 .Lfunc_end1-.Ltmp129 # Call between .Ltmp129 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._Z28__device_stub__square_kernelIiEvPT_,"axG",@progbits,_Z28__device_stub__square_kernelIiEvPT_,comdat
.weak _Z28__device_stub__square_kernelIiEvPT_ # -- Begin function _Z28__device_stub__square_kernelIiEvPT_
.p2align 4, 0x90
.type _Z28__device_stub__square_kernelIiEvPT_,@function
_Z28__device_stub__square_kernelIiEvPT_: # @_Z28__device_stub__square_kernelIiEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13square_kernelIiEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z28__device_stub__square_kernelIiEvPT_, .Lfunc_end2-_Z28__device_stub__square_kernelIiEvPT_
.cfi_endproc
# -- End function
.section .text._Z28__device_stub__square_kernelIfEvPT_,"axG",@progbits,_Z28__device_stub__square_kernelIfEvPT_,comdat
.weak _Z28__device_stub__square_kernelIfEvPT_ # -- Begin function _Z28__device_stub__square_kernelIfEvPT_
.p2align 4, 0x90
.type _Z28__device_stub__square_kernelIfEvPT_,@function
_Z28__device_stub__square_kernelIfEvPT_: # @_Z28__device_stub__square_kernelIfEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13square_kernelIfEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z28__device_stub__square_kernelIfEvPT_, .Lfunc_end3-_Z28__device_stub__square_kernelIfEvPT_
.cfi_endproc
# -- End function
.section .text._Z28__device_stub__square_kernelIdEvPT_,"axG",@progbits,_Z28__device_stub__square_kernelIdEvPT_,comdat
.weak _Z28__device_stub__square_kernelIdEvPT_ # -- Begin function _Z28__device_stub__square_kernelIdEvPT_
.p2align 4, 0x90
.type _Z28__device_stub__square_kernelIdEvPT_,@function
_Z28__device_stub__square_kernelIdEvPT_: # @_Z28__device_stub__square_kernelIdEvPT_
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13square_kernelIdEvPT_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end4:
.size _Z28__device_stub__square_kernelIdEvPT_, .Lfunc_end4-_Z28__device_stub__square_kernelIdEvPT_
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13square_kernelIiEvPT_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13square_kernelIfEvPT_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13square_kernelIdEvPT_, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " microseconds"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "SIZE (Datatype): "
.size .L.str.1, 18
.type _Z13square_kernelIiEvPT_,@object # @_Z13square_kernelIiEvPT_
.section .rodata._Z13square_kernelIiEvPT_,"aG",@progbits,_Z13square_kernelIiEvPT_,comdat
.weak _Z13square_kernelIiEvPT_
.p2align 3, 0x0
_Z13square_kernelIiEvPT_:
.quad _Z28__device_stub__square_kernelIiEvPT_
.size _Z13square_kernelIiEvPT_, 8
.type _Z13square_kernelIfEvPT_,@object # @_Z13square_kernelIfEvPT_
.section .rodata._Z13square_kernelIfEvPT_,"aG",@progbits,_Z13square_kernelIfEvPT_,comdat
.weak _Z13square_kernelIfEvPT_
.p2align 3, 0x0
_Z13square_kernelIfEvPT_:
.quad _Z28__device_stub__square_kernelIfEvPT_
.size _Z13square_kernelIfEvPT_, 8
.type _Z13square_kernelIdEvPT_,@object # @_Z13square_kernelIdEvPT_
.section .rodata._Z13square_kernelIdEvPT_,"aG",@progbits,_Z13square_kernelIdEvPT_,comdat
.weak _Z13square_kernelIdEvPT_
.p2align 3, 0x0
_Z13square_kernelIdEvPT_:
.quad _Z28__device_stub__square_kernelIdEvPT_
.size _Z13square_kernelIdEvPT_, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "vector::_M_realloc_insert"
.size .L.str.2, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13square_kernelIiEvPT_"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13square_kernelIfEvPT_"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13square_kernelIdEvPT_"
.size .L__unnamed_3, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Z28__device_stub__square_kernelIiEvPT_
.addrsig_sym _Z28__device_stub__square_kernelIfEvPT_
.addrsig_sym _Z28__device_stub__square_kernelIdEvPT_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym _Z13square_kernelIiEvPT_
.addrsig_sym _Z13square_kernelIfEvPT_
.addrsig_sym _Z13square_kernelIdEvPT_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13square_kernelIdEvPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1ffff, PT ; /* 0x0001ffff0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1b00 */
/*00a0*/ DMUL R4, R4, R4 ; /* 0x0000000404047228 */
/* 0x004e0e0000000000 */
/*00b0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe2000c101b04 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13square_kernelIfEvPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1ffff, PT ; /* 0x0001ffff0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13square_kernelIiEvPT_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x1ffff, PT ; /* 0x0001ffff0200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ IMAD R5, R0, R0, RZ ; /* 0x0000000000057224 */
/* 0x004fca00078e02ff */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z13square_kernelIiEvPT_,"axG",@progbits,_Z13square_kernelIiEvPT_,comdat
.protected _Z13square_kernelIiEvPT_
.globl _Z13square_kernelIiEvPT_
.p2align 8
.type _Z13square_kernelIiEvPT_,@function
_Z13square_kernelIiEvPT_:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x20000, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13square_kernelIiEvPT_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13square_kernelIiEvPT_,"axG",@progbits,_Z13square_kernelIiEvPT_,comdat
.Lfunc_end0:
.size _Z13square_kernelIiEvPT_, .Lfunc_end0-_Z13square_kernelIiEvPT_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z13square_kernelIfEvPT_,"axG",@progbits,_Z13square_kernelIfEvPT_,comdat
.protected _Z13square_kernelIfEvPT_
.globl _Z13square_kernelIfEvPT_
.p2align 8
.type _Z13square_kernelIfEvPT_,@function
_Z13square_kernelIfEvPT_:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x20000, v1
s_cbranch_execz .LBB1_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13square_kernelIfEvPT_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13square_kernelIfEvPT_,"axG",@progbits,_Z13square_kernelIfEvPT_,comdat
.Lfunc_end1:
.size _Z13square_kernelIfEvPT_, .Lfunc_end1-_Z13square_kernelIfEvPT_
.section .AMDGPU.csdata,"",@progbits
.section .text._Z13square_kernelIdEvPT_,"axG",@progbits,_Z13square_kernelIdEvPT_,comdat
.protected _Z13square_kernelIdEvPT_
.globl _Z13square_kernelIdEvPT_
.p2align 8
.type _Z13square_kernelIdEvPT_,@function
_Z13square_kernelIdEvPT_:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x20000, v1
s_cbranch_execz .LBB2_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[2:3], v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13square_kernelIdEvPT_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13square_kernelIdEvPT_,"axG",@progbits,_Z13square_kernelIdEvPT_,comdat
.Lfunc_end2:
.size _Z13square_kernelIdEvPT_, .Lfunc_end2-_Z13square_kernelIdEvPT_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13square_kernelIiEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13square_kernelIiEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13square_kernelIfEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13square_kernelIfEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13square_kernelIdEvPT_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13square_kernelIdEvPT_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "nms_kern.cuh"
#include <algorithm>
#include <cassert>
namespace {
#if __CUDACC_VER_MAJOR__ >= 9
#define __shfl_down(x, y) __shfl_down_sync(0xffffffffu, x, y)
#endif
// each thread computs one bit
const int THREADS_PER_BLOCK = 64;
const int WARP_SIZE = 32;
// use aligned structure for large memory transaction
struct __align__(16) Box {
float x0, y0, x1, y1;
};
//! return whether IoU(a, b) > thresh
__device__ __forceinline__ bool box_iou(Box a, Box b, float thresh) {
float left = max(a.x0, b.x0), right = min(a.x1, b.x1);
float top = max(a.y0, b.y0), bottom = min(a.y1, b.y1);
float width = max(right - left, 0.f), height = max(bottom - top, 0.f);
float interS = width * height;
float Sa = (a.x1 - a.x0) * (a.y1 - a.y0);
float Sb = (b.x1 - b.x0) * (b.y1 - b.y0);
return interS > (Sa + Sb - interS) * thresh;
}
//! store uint64_t with cache streaming
__device__ __forceinline__ void store_u64_cs(uint64_t* ptr, uint64_t val) {
asm volatile("st.cs.u64 [%0], %1;" : : "l"(ptr), "l"(val));
}
//! load uint64_t with cache streaming
__device__ __forceinline__ uint64_t load_u64_cs(const uint64_t* ptr) {
uint64_t val;
asm volatile("ld.cs.u64 %0, [%1];" : "=l"(val) : "l"(ptr));
return val;
}
__global__ void kern_gen_mask(
const int nr_boxes, const float nms_overlap_thresh, const Box* dev_boxes,
const int dev_mask_width, uint64_t* dev_mask) {
const int box_group_row = blockIdx.y, box_group_col = blockIdx.x;
if (box_group_row > box_group_col)
return;
const int row_nr_boxes = min(
nr_boxes - box_group_row * THREADS_PER_BLOCK, THREADS_PER_BLOCK),
col_nr_boxes = min(
nr_boxes - box_group_col * THREADS_PER_BLOCK, THREADS_PER_BLOCK);
__shared__ Box block_boxes[THREADS_PER_BLOCK];
if (threadIdx.x < col_nr_boxes) {
block_boxes[threadIdx.x] =
dev_boxes[THREADS_PER_BLOCK * box_group_col + threadIdx.x];
}
__syncthreads();
if (threadIdx.x < row_nr_boxes) {
const int cur_box_idx = THREADS_PER_BLOCK * box_group_row + threadIdx.x;
Box cur_box = dev_boxes[cur_box_idx];
uint64_t result = 0;
const int start = (box_group_row == box_group_col) ? threadIdx.x + 1
: // blocks on diagnal
0;
for (int i = start; i < col_nr_boxes; ++i) {
result |= static_cast<uint64_t>(
box_iou(cur_box, block_boxes[i], nms_overlap_thresh))
<< i;
}
store_u64_cs(&dev_mask[cur_box_idx * dev_mask_width + box_group_col], result);
}
}
//! true -> ~0, false -> 0
__device__ __forceinline__ uint32_t bool_as_u32_mask(bool v) {
return (!v) - 1;
}
//! return min value of val in current warp
__device__ __forceinline__ uint32_t warp_reduce_min_brdcst(uint32_t val) {
__shared__ uint32_t ans;
static_assert(WARP_SIZE == 32, "warp size != 32");
#pragma unroll
for (uint32_t offset = WARP_SIZE / 2; offset; offset /= 2)
val = min(val, __shfl_down(val, offset));
if (!threadIdx.x)
ans = val;
__syncthreads();
return ans;
}
struct BitwiseOrArgs {
uint64_t* dst;
const uint64_t* src;
uint32_t size;
};
__device__ __forceinline__ void bitwise_or_single_warp(BitwiseOrArgs args) {
uint64_t* __restrict__ dst = args.dst;
const uint64_t* __restrict__ src = args.src;
uint32_t size = args.size;
for (uint32_t i = threadIdx.x; i < size; i += WARP_SIZE) {
dst[i] |= load_u64_cs(&src[i]);
}
}
__global__ void kern_gen_indices(
uint32_t nr_boxes, uint32_t max_output, uint32_t overlap_mask_width,
const uint64_t* __restrict__ overlap_mask, uint64_t* __restrict__ rm_mask,
uint32_t* __restrict__ out_idx, uint32_t* __restrict__ out_size) {
__shared__ uint32_t out_pos;
__shared__ BitwiseOrArgs bitwise_or_args;
const uint32_t nr_box_blocks = DIVUP(nr_boxes, 64);
if (!threadIdx.x) {
uint32_t cnt = nr_box_blocks * 64 - nr_boxes;
// mark the padded boxes as having been removed
rm_mask[nr_box_blocks - 1] = ((1ull << cnt) - 1) << (64 - cnt);
out_pos = 0;
}
__syncthreads();
uint32_t box_block_id = threadIdx.x, th0_box_block_id = 0;
while (th0_box_block_id < nr_box_blocks) {
bool in_range = box_block_id < nr_box_blocks;
uint64_t cur_mask = ~rm_mask[box_block_id & bool_as_u32_mask(in_range)];
uint32_t min_box_block_id = warp_reduce_min_brdcst(
box_block_id | bool_as_u32_mask(!(in_range && cur_mask)));
if (min_box_block_id + 1) {
// min_box_block_id != UINT32_MAX, so at least one thread finds a
// un-removed box
if (min_box_block_id == box_block_id) {
// exactly one thread can take this path
uint32_t box_id_in_block = __ffsll(cur_mask) - 1,
box_id = box_block_id * 64 + box_id_in_block;
// so this box would not be processed again
rm_mask[box_block_id] |= 1ull << box_id_in_block;
bitwise_or_args.dst = &rm_mask[box_block_id];
bitwise_or_args.src =
&overlap_mask[box_id * overlap_mask_width + box_block_id];
bitwise_or_args.size = nr_box_blocks - box_block_id;
out_idx[out_pos++] = box_id;
}
__syncthreads();
if (out_pos == max_output)
break;
bitwise_or_single_warp(bitwise_or_args);
// skip the blocks before min_box_block_id
th0_box_block_id = min_box_block_id;
box_block_id = min_box_block_id + threadIdx.x;
} else {
th0_box_block_id += WARP_SIZE;
box_block_id += WARP_SIZE;
}
}
if (out_pos < max_output) {
// fill the values after out_pos
uint32_t val = out_idx[out_pos - 1];
for (uint32_t i = out_pos + threadIdx.x; i < max_output; i += WARP_SIZE) {
out_idx[i] = val;
}
}
if (!threadIdx.x) {
*out_size = out_pos;
}
}
} // anonymous namespace
void mgb::opr::standalone::nms::launch_gen_mask(
const int nr_boxes, const float nms_overlap_thresh, const float* dev_boxes,
const int dev_mask_width, uint64_t* dev_mask, cudaStream_t stream) {
dim3 blocks(DIVUP(nr_boxes, THREADS_PER_BLOCK), DIVUP(nr_boxes, THREADS_PER_BLOCK));
dim3 threads(THREADS_PER_BLOCK);
kern_gen_mask<<<blocks, threads, 0, stream>>>(
nr_boxes, nms_overlap_thresh, reinterpret_cast<const Box*>(dev_boxes),
dev_mask_width, dev_mask);
}
void mgb::opr::standalone::nms::launch_gen_indices(
int nr_boxes, int max_output, int overlap_mask_width,
const uint64_t* overlap_mask, uint64_t* rm_mask, uint32_t* out_idx,
uint32_t* out_size, cudaStream_t stream) {
kern_gen_indices<<<1, WARP_SIZE, 0, stream>>>(
nr_boxes, max_output, overlap_mask_width, overlap_mask, rm_mask, out_idx,
out_size);
}
// vim: ft=cuda syntax=cuda.doxygen | .file "tmpxft_00162f34_00000000-6_nms_kern.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2317:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2317:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
.hidden _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
.type _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm, @function
_Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm:
.LFB2339:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2339:
.size _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm, .-_Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
.globl _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm
.hidden _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm
.type _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm, @function
_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm:
.LFB2340:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2340:
.size _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm, .-_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm
.globl _ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st
.type _ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st, @function
_ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st:
.LFB2313:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movss %xmm0, 12(%rsp)
movq %rsi, %rbp
movl %edx, %r12d
movq %rcx, %r13
leal 62(%rdi), %eax
movl %edi, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $6, %eax
addl $1, %eax
movl %eax, 24(%rsp)
movl %eax, 28(%rsp)
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movq %r8, %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movl %r12d, %edx
movq %rbp, %rsi
movss 12(%rsp), %xmm0
movl %ebx, %edi
call _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
jmp .L11
.cfi_endproc
.LFE2313:
.size _ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st, .-_ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st
.globl _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
.hidden _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
.type _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_, @function
_Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_:
.LFB2341:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rcx, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
movq %r8, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2341:
.size _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_, .-_Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
.globl _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_
.hidden _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_
.type _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_, @function
_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_:
.LFB2342:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2342:
.size _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_, .-_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_
.globl _ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st
.type _ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st, @function
_ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st:
.LFB2314:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movq 104(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2314:
.size _ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st, .-_ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_"
.align 8
.LC1:
.string "_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2344:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2344:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "nms_kern.cuh"
#include <algorithm>
#include <cassert>
namespace {
#if __CUDACC_VER_MAJOR__ >= 9
#define __shfl_down(x, y) __shfl_down_sync(0xffffffffu, x, y)
#endif
// each thread computs one bit
const int THREADS_PER_BLOCK = 64;
const int WARP_SIZE = 32;
// use aligned structure for large memory transaction
struct __align__(16) Box {
float x0, y0, x1, y1;
};
//! return whether IoU(a, b) > thresh
__device__ __forceinline__ bool box_iou(Box a, Box b, float thresh) {
float left = max(a.x0, b.x0), right = min(a.x1, b.x1);
float top = max(a.y0, b.y0), bottom = min(a.y1, b.y1);
float width = max(right - left, 0.f), height = max(bottom - top, 0.f);
float interS = width * height;
float Sa = (a.x1 - a.x0) * (a.y1 - a.y0);
float Sb = (b.x1 - b.x0) * (b.y1 - b.y0);
return interS > (Sa + Sb - interS) * thresh;
}
//! store uint64_t with cache streaming
__device__ __forceinline__ void store_u64_cs(uint64_t* ptr, uint64_t val) {
asm volatile("st.cs.u64 [%0], %1;" : : "l"(ptr), "l"(val));
}
//! load uint64_t with cache streaming
__device__ __forceinline__ uint64_t load_u64_cs(const uint64_t* ptr) {
uint64_t val;
asm volatile("ld.cs.u64 %0, [%1];" : "=l"(val) : "l"(ptr));
return val;
}
__global__ void kern_gen_mask(
const int nr_boxes, const float nms_overlap_thresh, const Box* dev_boxes,
const int dev_mask_width, uint64_t* dev_mask) {
const int box_group_row = blockIdx.y, box_group_col = blockIdx.x;
if (box_group_row > box_group_col)
return;
const int row_nr_boxes = min(
nr_boxes - box_group_row * THREADS_PER_BLOCK, THREADS_PER_BLOCK),
col_nr_boxes = min(
nr_boxes - box_group_col * THREADS_PER_BLOCK, THREADS_PER_BLOCK);
__shared__ Box block_boxes[THREADS_PER_BLOCK];
if (threadIdx.x < col_nr_boxes) {
block_boxes[threadIdx.x] =
dev_boxes[THREADS_PER_BLOCK * box_group_col + threadIdx.x];
}
__syncthreads();
if (threadIdx.x < row_nr_boxes) {
const int cur_box_idx = THREADS_PER_BLOCK * box_group_row + threadIdx.x;
Box cur_box = dev_boxes[cur_box_idx];
uint64_t result = 0;
const int start = (box_group_row == box_group_col) ? threadIdx.x + 1
: // blocks on diagnal
0;
for (int i = start; i < col_nr_boxes; ++i) {
result |= static_cast<uint64_t>(
box_iou(cur_box, block_boxes[i], nms_overlap_thresh))
<< i;
}
store_u64_cs(&dev_mask[cur_box_idx * dev_mask_width + box_group_col], result);
}
}
//! true -> ~0, false -> 0
__device__ __forceinline__ uint32_t bool_as_u32_mask(bool v) {
return (!v) - 1;
}
//! return min value of val in current warp
__device__ __forceinline__ uint32_t warp_reduce_min_brdcst(uint32_t val) {
__shared__ uint32_t ans;
static_assert(WARP_SIZE == 32, "warp size != 32");
#pragma unroll
for (uint32_t offset = WARP_SIZE / 2; offset; offset /= 2)
val = min(val, __shfl_down(val, offset));
if (!threadIdx.x)
ans = val;
__syncthreads();
return ans;
}
struct BitwiseOrArgs {
uint64_t* dst;
const uint64_t* src;
uint32_t size;
};
__device__ __forceinline__ void bitwise_or_single_warp(BitwiseOrArgs args) {
uint64_t* __restrict__ dst = args.dst;
const uint64_t* __restrict__ src = args.src;
uint32_t size = args.size;
for (uint32_t i = threadIdx.x; i < size; i += WARP_SIZE) {
dst[i] |= load_u64_cs(&src[i]);
}
}
__global__ void kern_gen_indices(
uint32_t nr_boxes, uint32_t max_output, uint32_t overlap_mask_width,
const uint64_t* __restrict__ overlap_mask, uint64_t* __restrict__ rm_mask,
uint32_t* __restrict__ out_idx, uint32_t* __restrict__ out_size) {
__shared__ uint32_t out_pos;
__shared__ BitwiseOrArgs bitwise_or_args;
const uint32_t nr_box_blocks = DIVUP(nr_boxes, 64);
if (!threadIdx.x) {
uint32_t cnt = nr_box_blocks * 64 - nr_boxes;
// mark the padded boxes as having been removed
rm_mask[nr_box_blocks - 1] = ((1ull << cnt) - 1) << (64 - cnt);
out_pos = 0;
}
__syncthreads();
uint32_t box_block_id = threadIdx.x, th0_box_block_id = 0;
while (th0_box_block_id < nr_box_blocks) {
bool in_range = box_block_id < nr_box_blocks;
uint64_t cur_mask = ~rm_mask[box_block_id & bool_as_u32_mask(in_range)];
uint32_t min_box_block_id = warp_reduce_min_brdcst(
box_block_id | bool_as_u32_mask(!(in_range && cur_mask)));
if (min_box_block_id + 1) {
// min_box_block_id != UINT32_MAX, so at least one thread finds a
// un-removed box
if (min_box_block_id == box_block_id) {
// exactly one thread can take this path
uint32_t box_id_in_block = __ffsll(cur_mask) - 1,
box_id = box_block_id * 64 + box_id_in_block;
// so this box would not be processed again
rm_mask[box_block_id] |= 1ull << box_id_in_block;
bitwise_or_args.dst = &rm_mask[box_block_id];
bitwise_or_args.src =
&overlap_mask[box_id * overlap_mask_width + box_block_id];
bitwise_or_args.size = nr_box_blocks - box_block_id;
out_idx[out_pos++] = box_id;
}
__syncthreads();
if (out_pos == max_output)
break;
bitwise_or_single_warp(bitwise_or_args);
// skip the blocks before min_box_block_id
th0_box_block_id = min_box_block_id;
box_block_id = min_box_block_id + threadIdx.x;
} else {
th0_box_block_id += WARP_SIZE;
box_block_id += WARP_SIZE;
}
}
if (out_pos < max_output) {
// fill the values after out_pos
uint32_t val = out_idx[out_pos - 1];
for (uint32_t i = out_pos + threadIdx.x; i < max_output; i += WARP_SIZE) {
out_idx[i] = val;
}
}
if (!threadIdx.x) {
*out_size = out_pos;
}
}
} // anonymous namespace
void mgb::opr::standalone::nms::launch_gen_mask(
const int nr_boxes, const float nms_overlap_thresh, const float* dev_boxes,
const int dev_mask_width, uint64_t* dev_mask, cudaStream_t stream) {
dim3 blocks(DIVUP(nr_boxes, THREADS_PER_BLOCK), DIVUP(nr_boxes, THREADS_PER_BLOCK));
dim3 threads(THREADS_PER_BLOCK);
kern_gen_mask<<<blocks, threads, 0, stream>>>(
nr_boxes, nms_overlap_thresh, reinterpret_cast<const Box*>(dev_boxes),
dev_mask_width, dev_mask);
}
void mgb::opr::standalone::nms::launch_gen_indices(
int nr_boxes, int max_output, int overlap_mask_width,
const uint64_t* overlap_mask, uint64_t* rm_mask, uint32_t* out_idx,
uint32_t* out_size, cudaStream_t stream) {
kern_gen_indices<<<1, WARP_SIZE, 0, stream>>>(
nr_boxes, max_output, overlap_mask_width, overlap_mask, rm_mask, out_idx,
out_size);
}
// vim: ft=cuda syntax=cuda.doxygen | #pragma once
#include <hip/hip_runtime.h>
#include <stddef.h>
#include <stdint.h>
#define DIVUP(m, n) (((m)-1) / (n) + 1)
namespace mgb {
namespace opr {
namespace standalone {
namespace nms {
/*!
* \brief launch the kernel to generate nms mask
* \param nr_boxes number of input boxes
* \param nms_overlap_thresh overlapping threshold for IoU
* \param[in] dev_boxes boxes in [n, 4] layout,
* each row containing (x0, y0, x1, y1)
* \param dev_mask_width width in number of uint64_t elements of div_mask
* matrix; must be at least ceil(n, 64)
* \param[out] dev_mask [n, dev_mask_width] dev_mask[i] is a
* bitmask of length n indicating whether i overlaps with each box. Only
* the upper triangle (row < col) are filled.
*/
void launch_gen_mask(
const int nr_boxes, const float nms_overlap_thresh, const float* dev_boxes,
const int dev_mask_width, uint64_t* dev_mask, hipStream_t stream);
/*!
* \brief launch the kernel to generate indices of kept boxes
* \param max_output max number of entries to be written to out_idx
* \param overlap_mask the mask generated by launch_gen_mask
* \param[in,out] rm_mask mask of removed boxes; must be initialized as 0
* \param[out] out_idx indices of boxes to be kept
* \param[out] out_size number of items written to out_idx; the remaining items
* would be filled with the last valid item
*/
void launch_gen_indices(
int nr_boxes, int max_output, int overlap_mask_width,
const uint64_t* overlap_mask, uint64_t* rm_mask, uint32_t* out_idx,
uint32_t* out_size, hipStream_t stream);
} // namespace nms
} // namespace standalone
} // namespace opr
} // namespace mgb
// vim: ft=cuda syntax=cuda.doxygen |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma once
#include <hip/hip_runtime.h>
#include <stddef.h>
#include <stdint.h>
#define DIVUP(m, n) (((m)-1) / (n) + 1)
namespace mgb {
namespace opr {
namespace standalone {
namespace nms {
/*!
* \brief launch the kernel to generate nms mask
* \param nr_boxes number of input boxes
* \param nms_overlap_thresh overlapping threshold for IoU
* \param[in] dev_boxes boxes in [n, 4] layout,
* each row containing (x0, y0, x1, y1)
* \param dev_mask_width width in number of uint64_t elements of div_mask
* matrix; must be at least ceil(n, 64)
* \param[out] dev_mask [n, dev_mask_width] dev_mask[i] is a
* bitmask of length n indicating whether i overlaps with each box. Only
* the upper triangle (row < col) are filled.
*/
void launch_gen_mask(
const int nr_boxes, const float nms_overlap_thresh, const float* dev_boxes,
const int dev_mask_width, uint64_t* dev_mask, hipStream_t stream);
/*!
* \brief launch the kernel to generate indices of kept boxes
* \param max_output max number of entries to be written to out_idx
* \param overlap_mask the mask generated by launch_gen_mask
* \param[in,out] rm_mask mask of removed boxes; must be initialized as 0
* \param[out] out_idx indices of boxes to be kept
* \param[out] out_size number of items written to out_idx; the remaining items
* would be filled with the last valid item
*/
void launch_gen_indices(
int nr_boxes, int max_output, int overlap_mask_width,
const uint64_t* overlap_mask, uint64_t* rm_mask, uint32_t* out_idx,
uint32_t* out_size, hipStream_t stream);
} // namespace nms
} // namespace standalone
} // namespace opr
} // namespace mgb
// vim: ft=cuda syntax=cuda.doxygen | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma once
#include <hip/hip_runtime.h>
#include <stddef.h>
#include <stdint.h>
#define DIVUP(m, n) (((m)-1) / (n) + 1)
namespace mgb {
namespace opr {
namespace standalone {
namespace nms {
/*!
* \brief launch the kernel to generate nms mask
* \param nr_boxes number of input boxes
* \param nms_overlap_thresh overlapping threshold for IoU
* \param[in] dev_boxes boxes in [n, 4] layout,
* each row containing (x0, y0, x1, y1)
* \param dev_mask_width width in number of uint64_t elements of div_mask
* matrix; must be at least ceil(n, 64)
* \param[out] dev_mask [n, dev_mask_width] dev_mask[i] is a
* bitmask of length n indicating whether i overlaps with each box. Only
* the upper triangle (row < col) are filled.
*/
void launch_gen_mask(
const int nr_boxes, const float nms_overlap_thresh, const float* dev_boxes,
const int dev_mask_width, uint64_t* dev_mask, hipStream_t stream);
/*!
* \brief launch the kernel to generate indices of kept boxes
* \param max_output max number of entries to be written to out_idx
* \param overlap_mask the mask generated by launch_gen_mask
* \param[in,out] rm_mask mask of removed boxes; must be initialized as 0
* \param[out] out_idx indices of boxes to be kept
* \param[out] out_size number of items written to out_idx; the remaining items
* would be filled with the last valid item
*/
void launch_gen_indices(
int nr_boxes, int max_output, int overlap_mask_width,
const uint64_t* overlap_mask, uint64_t* rm_mask, uint32_t* out_idx,
uint32_t* out_size, hipStream_t stream);
} // namespace nms
} // namespace standalone
} // namespace opr
} // namespace mgb
// vim: ft=cuda syntax=cuda.doxygen | .text
.file "nms_kern.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00162f34_00000000-6_nms_kern.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2317:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2317:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
.hidden _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
.type _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm, @function
_Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm:
.LFB2339:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2339:
.size _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm, .-_Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
.globl _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm
.hidden _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm
.type _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm, @function
_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm:
.LFB2340:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2340:
.size _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm, .-_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm
.globl _ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st
.type _ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st, @function
_ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st:
.LFB2313:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movss %xmm0, 12(%rsp)
movq %rsi, %rbp
movl %edx, %r12d
movq %rcx, %r13
leal 62(%rdi), %eax
movl %edi, %edx
subl $1, %edx
cmovns %edx, %eax
sarl $6, %eax
addl $1, %eax
movl %eax, 24(%rsp)
movl %eax, 28(%rsp)
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movq %r8, %r9
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movl %r12d, %edx
movq %rbp, %rsi
movss 12(%rsp), %xmm0
movl %ebx, %edi
call _Z94__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPmifPKN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b3BoxEiPm
jmp .L11
.cfi_endproc
.LFE2313:
.size _ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st, .-_ZN3mgb3opr10standalone3nms15launch_gen_maskEifPKfiPmP11CUstream_st
.globl _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
.hidden _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
.type _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_, @function
_Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_:
.LFB2341:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rcx, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
movq %r8, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
movq %r9, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2341:
.size _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_, .-_Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
.globl _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_
.hidden _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_
.type _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_, @function
_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_:
.LFB2342:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2342:
.size _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_, .-_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_
.globl _ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st
.type _ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st, @function
_ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st:
.LFB2314:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebx
movl %esi, %ebp
movl %edx, %r12d
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
movl $32, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movq 104(%rsp), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 104
pushq 104(%rsp)
.cfi_def_cfa_offset 112
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movl %r12d, %edx
movl %ebp, %esi
movl %ebx, %edi
call _Z95__device_stub__ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_jjjPKmPmPjS2_
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L23
.cfi_endproc
.LFE2314:
.size _ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st, .-_ZN3mgb3opr10standalone3nms18launch_gen_indicesEiiiPKmPmPjS6_P11CUstream_st
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_"
.align 8
.LC1:
.string "_ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2344:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b16kern_gen_indicesEjjjPKmPmPjS3_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZN44_GLOBAL__N__f0db970a_11_nms_kern_cu_fa56c34b13kern_gen_maskEifPKNS_3BoxEiPm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2344:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "nms_kern.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <vector>
#include <algorithm>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 5
using namespace std;
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
vector<DATA_TYPE> int_vector;
unsigned long N = 32000;
DATA_TYPE sum1 = 0;
DATA_TYPE sum2 = 0;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_vector.push_back((DATA_TYPE)(rand() % 500000));
}
clock_gettime(CLOCK_REALTIME,&start);
for(int c = 0; c < ITERATIONS; c++){
sum1 += *min_element(int_vector.begin(),int_vector.end());
sum2 += *max_element(int_vector.begin(),int_vector.end());
}
clock_gettime(CLOCK_REALTIME,&stop);
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_vector.clear();
}
assert(sum1 != sum2);
printf("%lu\n", total_time);
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <vector>
#include <algorithm>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 5
using namespace std;
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
vector<DATA_TYPE> int_vector;
unsigned long N = 32000;
DATA_TYPE sum1 = 0;
DATA_TYPE sum2 = 0;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_vector.push_back((DATA_TYPE)(rand() % 500000));
}
clock_gettime(CLOCK_REALTIME,&start);
for(int c = 0; c < ITERATIONS; c++){
sum1 += *min_element(int_vector.begin(),int_vector.end());
sum2 += *max_element(int_vector.begin(),int_vector.end());
}
clock_gettime(CLOCK_REALTIME,&stop);
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_vector.clear();
}
assert(sum1 != sum2);
printf("%lu\n", total_time);
return 0;
} | .file "tmpxft_00189e9c_00000000-6_reductions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3194:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3194:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3217:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3217:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC0:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_
.type _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_, @function
_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_:
.LFB3371:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $2, %rax
movabsq $2305843009213693951, %rdx
cmpq %rdx, %rax
je .L22
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L8
movabsq $2305843009213693951, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L9
jmp .L16
.L22:
leaq .LC0(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L23:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L11
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L15
.L8:
movq (%rsp), %r15
subq %r13, %r15
movabsq $2305843009213693951, %r14
.L16:
leaq 0(,%r14,4), %rdi
call _Znwm@PLT
movq %rax, %r12
.L9:
movq 8(%rsp), %rax
movss (%rax), %xmm0
movss %xmm0, (%r12,%r15)
testq %r15, %r15
jg .L23
leaq 4(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L13
.L11:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L13:
addq %rbp, %r15
testq %r13, %r13
je .L14
movq 16(%rbx), %rsi
subq %r13, %rsi
.L15:
movq %r13, %rdi
call _ZdlPvm@PLT
.L14:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,4), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3371:
.size _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_, .-_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "%lu\n"
.text
.globl main
.type main, @function
main:
.LFB3180:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3180
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 48(%rsp)
movq $0, 56(%rsp)
movq $0, 64(%rsp)
movl $32000, %r14d
cmpl $1, %edi
jg .L54
.L25:
movl $5, %r12d
movl $0, %r13d
leaq 12(%rsp), %r15
jmp .L37
.L54:
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
jmp .L25
.L27:
leaq 48(%rsp), %rdi
movq %r15, %rdx
.LEHB0:
call _ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_
.L28:
subl $1, %ebx
je .L26
.L29:
call rand@PLT
movslq %eax, %rdx
imulq $1125899907, %rdx, %rdx
sarq $49, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $500000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 12(%rsp)
movq 56(%rsp), %rsi
cmpq 64(%rsp), %rsi
je .L27
movss %xmm0, (%rsi)
addq $4, %rsi
movq %rsi, 56(%rsp)
jmp .L28
.L30:
subl $1, %ecx
je .L55
.L35:
cmpq %rbx, %rbp
je .L30
cmpq %rsi, %rbx
je .L30
movq %rsi, %rax
movq %rbp, %rdx
.L32:
movss (%rdx), %xmm0
ucomiss (%rax), %xmm0
cmova %rax, %rdx
addq $4, %rax
cmpq %rax, %rbx
jne .L32
cmpq %rsi, %rbx
je .L30
movq %rsi, %rax
movq %rbp, %rdx
.L34:
movss (%rax), %xmm0
ucomiss (%rdx), %xmm0
cmova %rax, %rdx
addq $4, %rax
cmpq %rax, %rbx
jne .L34
jmp .L30
.L55:
leaq 32(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 32(%rsp), %rax
subq 16(%rsp), %rax
imulq $1000000000, %rax, %rax
addq 40(%rsp), %rax
subq 24(%rsp), %rax
addq %rax, %r13
cmpq %rbx, %rbp
je .L36
movq %rbp, 56(%rsp)
.L36:
subl $1, %r12d
je .L56
.L37:
movl %r14d, %ebx
testl %r14d, %r14d
jg .L29
.L26:
leaq 16(%rsp), %rsi
movl $0, %edi
call clock_gettime@PLT
movq 56(%rsp), %rbx
movq 48(%rsp), %rbp
leaq 4(%rbp), %rsi
movl $5, %ecx
jmp .L35
.L56:
movq %r13, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.LEHE0:
testq %rbp, %rbp
je .L38
movq 64(%rsp), %rsi
subq %rbp, %rsi
movq %rbp, %rdi
call _ZdlPvm@PLT
.L38:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L57
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
endbr64
movq %rax, %rbx
movq 48(%rsp), %rdi
movq 64(%rsp), %rsi
subq %rdi, %rsi
testq %rdi, %rdi
je .L40
call _ZdlPvm@PLT
.L40:
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L41
call __stack_chk_fail@PLT
.L41:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L57:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3180:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3180:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3180-.LLSDACSB3180
.LLSDACSB3180:
.uleb128 .LEHB0-.LFB3180
.uleb128 .LEHE0-.LEHB0
.uleb128 .L46-.LFB3180
.uleb128 0
.uleb128 .LEHB1-.LFB3180
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE3180:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <vector>
#include <algorithm>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 5
using namespace std;
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
vector<DATA_TYPE> int_vector;
unsigned long N = 32000;
DATA_TYPE sum1 = 0;
DATA_TYPE sum2 = 0;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_vector.push_back((DATA_TYPE)(rand() % 500000));
}
clock_gettime(CLOCK_REALTIME,&start);
for(int c = 0; c < ITERATIONS; c++){
sum1 += *min_element(int_vector.begin(),int_vector.end());
sum2 += *max_element(int_vector.begin(),int_vector.end());
}
clock_gettime(CLOCK_REALTIME,&stop);
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_vector.clear();
}
assert(sum1 != sum2);
printf("%lu\n", total_time);
return 0;
} | #include <hip/hip_runtime.h>
#include <vector>
#include <algorithm>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 5
using namespace std;
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
vector<DATA_TYPE> int_vector;
unsigned long N = 32000;
DATA_TYPE sum1 = 0;
DATA_TYPE sum2 = 0;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_vector.push_back((DATA_TYPE)(rand() % 500000));
}
clock_gettime(CLOCK_REALTIME,&start);
for(int c = 0; c < ITERATIONS; c++){
sum1 += *min_element(int_vector.begin(),int_vector.end());
sum2 += *max_element(int_vector.begin(),int_vector.end());
}
clock_gettime(CLOCK_REALTIME,&stop);
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_vector.clear();
}
assert(sum1 != sum2);
printf("%lu\n", total_time);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <algorithm>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 5
using namespace std;
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
vector<DATA_TYPE> int_vector;
unsigned long N = 32000;
DATA_TYPE sum1 = 0;
DATA_TYPE sum2 = 0;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_vector.push_back((DATA_TYPE)(rand() % 500000));
}
clock_gettime(CLOCK_REALTIME,&start);
for(int c = 0; c < ITERATIONS; c++){
sum1 += *min_element(int_vector.begin(),int_vector.end());
sum2 += *max_element(int_vector.begin(),int_vector.end());
}
clock_gettime(CLOCK_REALTIME,&stop);
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_vector.clear();
}
assert(sum1 != sum2);
printf("%lu\n", total_time);
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <vector>
#include <algorithm>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 5
using namespace std;
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
vector<DATA_TYPE> int_vector;
unsigned long N = 32000;
DATA_TYPE sum1 = 0;
DATA_TYPE sum2 = 0;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_vector.push_back((DATA_TYPE)(rand() % 500000));
}
clock_gettime(CLOCK_REALTIME,&start);
for(int c = 0; c < ITERATIONS; c++){
sum1 += *min_element(int_vector.begin(),int_vector.end());
sum2 += *max_element(int_vector.begin(),int_vector.end());
}
clock_gettime(CLOCK_REALTIME,&stop);
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_vector.clear();
}
assert(sum1 != sum2);
printf("%lu\n", total_time);
return 0;
} | .text
.file "reductions.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $32000, %eax # imm = 0x7D00
cmpl $2, %edi
jl .LBB0_2
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
.LBB0_2:
leal 1(%rax), %ecx
movl %ecx, 12(%rsp) # 4-byte Spill
xorl %esi, %esi
movabsq $2305843009213693951, %rbx # imm = 0x1FFFFFFFFFFFFFFF
xorl %ecx, %ecx
xorl %r12d, %r12d
xorl %r13d, %r13d
movq %rax, 24(%rsp) # 8-byte Spill
jmp .LBB0_3
.p2align 4, 0x90
.LBB0_4: # %._crit_edge
# in Loop: Header=BB0_3 Depth=1
xorl %edi, %edi
leaq 56(%rsp), %rsi
callq clock_gettime
xorl %edi, %edi
leaq 40(%rsp), %rsi
callq clock_gettime
movq 40(%rsp), %rax
subq 56(%rsp), %rax
movq 32(%rsp), %rsi # 8-byte Reload
addq 48(%rsp), %rsi
subq 64(%rsp), %rsi
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
addq %rax, %rsi
movl 16(%rsp), %ecx # 4-byte Reload
incl %ecx
cmpl $5, %ecx
movq 24(%rsp), %rax # 8-byte Reload
je .LBB0_5
.LBB0_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_8 Depth 2
movl %ecx, 16(%rsp) # 4-byte Spill
movq %rsi, 32(%rsp) # 8-byte Spill
movl 12(%rsp), %r14d # 4-byte Reload
movq %r12, %rbp
testl %eax, %eax
jg .LBB0_8
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_9: # in Loop: Header=BB0_8 Depth=2
movss %xmm0, (%rbp)
.LBB0_26: # %_ZNSt6vectorIfSaIfEE9push_backEOf.exit
# in Loop: Header=BB0_8 Depth=2
addq $4, %rbp
decl %r14d
cmpl $1, %r14d
jle .LBB0_4
.LBB0_8: # %.lr.ph
# Parent Loop BB0_3 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1125899907, %rax, %rcx # imm = 0x431BDE83
movq %rcx, %rdx
shrq $63, %rdx
sarq $49, %rcx
addl %edx, %ecx
imull $500000, %ecx, %ecx # imm = 0x7A120
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
cmpq %r13, %rbp
jne .LBB0_9
# %bb.10: # in Loop: Header=BB0_8 Depth=2
subq %r12, %rbp
movabsq $9223372036854775804, %rax # imm = 0x7FFFFFFFFFFFFFFC
cmpq %rax, %rbp
je .LBB0_11
# %bb.13: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB0_8 Depth=2
movq %rbp, %r15
sarq $2, %r15
cmpq $1, %r15
movq %r15, %rax
adcq $0, %rax
leaq (%rax,%r15), %rcx
cmpq %rbx, %rcx
jb .LBB0_15
# %bb.14: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB0_8 Depth=2
movq %rbx, %rcx
.LBB0_15: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB0_8 Depth=2
movq %rbx, %r13
addq %r15, %rax
jb .LBB0_17
# %bb.16: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB0_8 Depth=2
movq %rcx, %r13
.LBB0_17: # %_ZNKSt6vectorIfSaIfEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB0_8 Depth=2
testq %r13, %r13
je .LBB0_18
# %bb.19: # in Loop: Header=BB0_8 Depth=2
movss %xmm0, 20(%rsp) # 4-byte Spill
leaq (,%r13,4), %rdi
.Ltmp0:
callq _Znwm
.Ltmp1:
# %bb.20: # in Loop: Header=BB0_8 Depth=2
movq %rax, %rbx
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
jmp .LBB0_21
.LBB0_18: # in Loop: Header=BB0_8 Depth=2
xorl %ebx, %ebx
.LBB0_21: # %_ZNSt12_Vector_baseIfSaIfEE11_M_allocateEm.exit.i.i.i
# in Loop: Header=BB0_8 Depth=2
movss %xmm0, (%rbx,%r15,4)
testq %rbp, %rbp
jle .LBB0_23
# %bb.22: # in Loop: Header=BB0_8 Depth=2
movq %rbx, %rdi
movq %r12, %rsi
movq %rbp, %rdx
callq memmove@PLT
.LBB0_23: # %_ZNSt6vectorIfSaIfEE11_S_relocateEPfS2_S2_RS0_.exit.i.i.i
# in Loop: Header=BB0_8 Depth=2
testq %r12, %r12
je .LBB0_25
# %bb.24: # in Loop: Header=BB0_8 Depth=2
movq %r12, %rdi
callq _ZdlPv
.LBB0_25: # %_ZNSt6vectorIfSaIfEE17_M_realloc_insertIJfEEEvN9__gnu_cxx17__normal_iteratorIPfS1_EEDpOT_.exit.i.i
# in Loop: Header=BB0_8 Depth=2
addq %rbx, %rbp
leaq (%rbx,%r13,4), %r13
movq %rbx, %r12
movabsq $2305843009213693951, %rbx # imm = 0x1FFFFFFFFFFFFFFF
jmp .LBB0_26
.LBB0_5:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testq %r12, %r12
je .LBB0_7
# %bb.6:
movq %r12, %rdi
callq _ZdlPv
.LBB0_7: # %_ZNSt6vectorIfSaIfEED2Ev.exit
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_11:
.cfi_def_cfa_offset 128
.Ltmp3:
movl $.L.str.1, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp4:
# %bb.12: # %.noexc
.LBB0_27: # %.loopexit
.Ltmp2:
jmp .LBB0_29
.LBB0_28: # %.loopexit.split-lp
.Ltmp5:
.LBB0_29:
movq %rax, %rbx
testq %r12, %r12
je .LBB0_31
# %bb.30:
movq %r12, %rdi
callq _ZdlPv
.LBB0_31: # %_ZNSt6vectorIfSaIfEED2Ev.exit40
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end0-.Ltmp4 # Call between .Ltmp4 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%lu\n"
.size .L.str, 5
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "vector::_M_realloc_insert"
.size .L.str.1, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym __hip_cuid_ |
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