system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <ctime>
//Function that verify cuda calls and return cuda error if any
#define gpuCheck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//Initialise ascendant array with random values in
void init_array(int* array, int size, int const adder=10)
{
array[0] = rand()%adder;
for(int i = 0; i < size;i++)
{
array[i] = array[i-1] + rand()%adder;
}
}
//Function that initialise array with random values
void init_array_no_order(int* array, int size, int const adder=10)
{
array[0] = rand()%adder;
for(int i = 0; i < size;i++)
{
array[i] = rand()%adder;
}
}
//Function that copy array in another
void copy_array(int* a, int* a_copy, int n){
for(int i = 0;i < n;i++){
a_copy[i] = a[i];
}
}
//Function that print an array of size size
void print_array(int* a, int size)
{
printf("[");
for(int i = 0; i < size;i++)
{
//printf("i = %d | v = %d " ,i, a[i]);
printf("%d " ,a[i]);
}
printf("]\n");
}
//Device version of parallel merge of a and b in m with |m|<1024
__global__ void mergeSmall_k(int* m, int n, int size)
{
int gbx = blockIdx.x;
int tidx = threadIdx.x;
int i = gbx * blockDim.x + tidx;
if(i < n)
{
int L1, R1, L2, R2;
L1 = gbx*blockDim.x;
R1 = gbx*blockDim.x + size-1;
L2 = gbx*blockDim.x + size;
R2 = gbx*blockDim.x + 2*size-1;
if(L2 < n)
{
// printf("L1 : %d, R1 : %d, L2 : %d, R2 : %d\n", L1, R1, L2, R2);
if(R2 >= n){
R2 = n-1;
}
__shared__ int *d_a, *d_b;
int n_a = R1-L1+1;
int n_b = R2-L2+1;
int n_m = n_a+n_b;
d_a = (int*)malloc(n_a*sizeof(int));
d_b = (int*)malloc(n_b*sizeof(int));
__syncthreads();
// printf("tidx : %d, n_a : %d\n", tidx, n_a);
if (tidx < n_a)
{
// printf("m[%d] : %d\n", i, m[i]);
d_a[tidx] = m[i];
// printf("d_a_%d[%d] = %d\n", gbx, tidx, d_a[tidx]);
}
else if (tidx < n_m)
{
d_b[tidx - n_a] = m[i];
// printf("d_b_%d[%d] = %d\n", gbx, tidx - n_a, d_b[tidx - n_a]);
}
__syncthreads();
int2 K;
int2 P;
int2 Q;
// printf("n_a : %d, n_b : %d\n", n_a, n_b);
if(tidx > n_a)
{
K.x = tidx - n_a;
K.y = n_a;
P.x = n_a;
P.y = tidx - n_a;
}
else
{
K.x = 0;
K.y = tidx;
P.x = tidx;
P.y = 0;
}
int offset = 0;
while(1)
{
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
{
m[i] = d_a[Q.y];
// printf("## m[%d] : %d, d_a_%d[%d] : %d\n",i, m[i], gbx, Q.y, d_a[Q.y]);
}
else
{
m[i] = d_b[Q.x];
// printf("## m[%d] : %d, d_b_%d[%d] : %d\n",i, m[i], gbx, Q.x, d_b[Q.x]);
}
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
__syncthreads();
}
}
}
/**
Parallel version of merge of A and B with |A| + |B| <= 1024
@param d_a, d_b : device versions of arrays to merge
d_m : device version of merge of a and b
n_a, n_b, n_b : respective sizes of d_a, d_b, d_m
*/
__device__ void mergeSmall_k(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
int i = threadIdx.x;
if(i < n_m)
{
int2 K;
int2 P;
int2 Q;
if(i > n_a)
{
K.x = i - n_a;
K.y = n_a;
P.x = n_a;
P.y = i - n_a;
}
else
{
K.x = 0;
K.y = i;
P.x = i;
P.y = 0;
}
int offset = 0;
while(1)
{
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
{
d_m[i] = d_a[Q.y];
}
else
{
d_m[i] = d_b[Q.x];
}
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
}
}
//Giving a path ( from pathBig_k ) each block merge (with mergeParallel) each piece a_k and b_k in m_k of a and b. Then it replace elements in m
__global__ void mergeBig_k(int *m, int n_m, int *a, int n_a, int *b, int n_b, int2 *path, int n_path, int nbPartitions, int size)
{
int blockId = blockIdx.x;
int threadId = threadIdx.x;
int i = blockId * blockDim.x + threadId;
if (blockId <= nbPartitions)//On utilise un block pour chaque partition
{
int x0, y0, x1, y1;
x0 = path[blockId].x;
y0 = path[blockId].y;
x1 = path[blockId+1].x;
y1 = path[blockId+1].y;
const int dimx=x1-x0;
const int dimy = y1-y0;
//A modifier par dimx dimy dimx+dimy
__shared__ int a_k[1024];
__shared__ int b_k[1024];
__shared__ int m_k[1024];
if (threadId < dimx) //On rempli a_k[i] : 0 <= i < dimx
{
a_k[threadId] = a[x0+threadId];
}
else if (threadId < dimy+dimx)//On rempli b_k[i] : indice dimx <= i < dimx+dimy+1
{
b_k[threadId-dimx] = b[y0+threadId-dimx];
}
__syncthreads();
// mergeParallel(m_k, dimx+dimy, size);
m[i] = m_k[threadId];
}
}
//Function that generate a path to break down m into pieces that could be merge without conflict
//On appelle |m|/TPB blocks avec chacun un seul thread. Chaque thread s'occupe de la diagonale thread
__global__ void pathBig_k(int pas, int2* path, int n_path , int* d_a, int n_a ,int* d_b, int n_b)
{
int thread_i = blockIdx.x * blockDim.x + threadIdx.x;
if(thread_i <= (n_a + n_b)/pas) //<------------//On vérifie que l'indice du thread est inférieur à la taille du tableau de retour et qu'il est un multiple du pas
{
int i = thread_i*pas;
int2 K;
int2 P;
int2 Q;
if(i > n_a)
{
K.x = i - n_a;
K.y = n_a;
P.x = n_a;
P.y = i - n_a;
}
else
{
K.x = 0;
K.y = i;
P.x = i;
P.y = 0;
}
int offset = 0;
while(1)
{
//Calcul des coordonnées du milieu de P et K
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
//
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
//
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
//printf("thread : %d => (%d, %d)\n", thread_i, Q.y, Q.x);
//!\\ Problème ordre x et y
path[thread_i].x=Q.y;
path[thread_i].y=Q.x;
}
//Si |m| n'est pas un mutliple de pas, le thread 0 ajoute (n_a, n_b) à la fin du tableau
if (thread_i==0 && (n_a+n_b)%pas!=0)
{
//printf("thread : %d => (%d, %d)\n", thread_i, n_a, n_b);
path[n_path-1].x=n_a;
path[n_path-1].y=n_b;
}
}
//Function that sort any array
void fusionSort(int *mGPU, int n_m)
{
//L1 : indice du premier élément de m_part1
//R1 : indice du dernier élément de m_part1
//L2 : indice du premier élément de m_part2
//R2 : indice du dernier élément de m_part2
int size = 1;
int i;
int *m = (int*)malloc(n_m*sizeof(int));
while (size < n_m)
{
i = 0;
if (size < 1024)
{
printf("Size : %d\n", size);
mergeSmall_k<<<n_m/(2*size) + 1, 2*size>>>(mGPU, n_m, size);
gpuCheck(cudaMemcpy(m, mGPU, n_m*sizeof(int), cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
print_array(m, n_m);
}
size *= 2;
}
}
void fusionMergeSeq(int* A, int* tmp, int L1, int R1, int L2, int R2){
int i = 0;
while(L1 <= R1 && L2 <= R2){
if(A[L1] <= A[L2]){
tmp[i] = A[L1];
i++;
L1++;
}
else{
tmp[i] = A[L2];
i++;
L2++;
}
}
while(L1 <= R1){
tmp[i] = A[L1];
i++;
L1++;
}
while(L2 <= R2){
tmp[i] = A[L2];
i++;
L2++;
}
}
void fusionSortSeq(int* A, int n){
int len = 1;
int i;
int L1, R1, L2, R2;
int* tmp = (int*)malloc(n*sizeof(int));
while(len < n){
i = 0;
while(i < n){
L1 = i;
R1 = i + len - 1;
L2 = i + len;
R2 = i + 2*len - 1;
tmp = (int*)realloc(tmp, (R2-L1+1)*sizeof(int));
if(L2 >= n){
break;
}
if(R2 >= n){
R2 = n - 1;
}
fusionMergeSeq(A, tmp, L1, R1, L2, R2);
for(int j = 0;j < R2-L1+1;j++){
A[i+j] = tmp[j];
}
i = i + 2*len;
}
len *= 2;
}
free(tmp);
}
//Fonction qui trie un tableau M en parallèle par tri fusion itératif (question 3)
//Fonctions de vérification
//Fonction qui vérifie qu'un tableau est bien trié (tous ses éléments rangés dans l'ordre croissant)
int assertOrder(int *tab, int size){
for (int i=0; i<size-1; i++){
if (tab[i] > tab[i+1]){
printf("WARNING : Unsuccessful merge or sort ... : unordered array on indice %d ...\n", i);
printf("tab[i]= %d > tab[i+1] = %d\n", tab[i], tab[i+1]);
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments des deux tableaux qu'on veut fusionner
int assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
{
int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
for(int i = 0;i<size;i++){
verif[i] = 0;
}
for (int i=0; i<size; i++){
for(int j = 0;j < n1;j++){
if(tab[j] == m[i] && verif[i] == 0){ //si il y a une valeur identique et que celle-ci n'a pas été vérifiée
verif[i] = 1;
}
}
}
for (int i=0; i<size; i++){
for(int j = 0;j < n2;j++){
if(tab2[j] == m[i] && verif[i] == 0){
verif[i] = 1;
}
}
}
for(int i = 0;i<size;i++){
if(verif[i] != 1){
printf("\nWARNING : Unsuccessful merge : incorrect elements...\n");
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments du tableau qu'on veut trier
int assertSortAllValuesPresent(int* m, int* m_sorted, int size){
int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
for(int i = 0;i<size;i++){
verif[i] = 0;
}
for (int i=0; i<size; i++){
for(int j = 0;j < size;j++){
if(m_sorted[j] == m[i]){ //si il y a une valeur identique
verif[i] = 1;
}
}
}
for(int i = 0;i<size;i++){
if(verif[i] != 1){
printf("i : %d\n", i);
printf("\nWARNING : Unsuccessful sort : incorrect elements...\n");
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'un tableau est bien trié et la fusion de deux tableaux
//tab et tab2 : les deux tableaux qu'on veut fusionner
//m : le tableau qui est la fusion triée de tab et tab2
int assertMerge(int *tab, int n1, int *tab2, int n2, int* m, int size){
int successfulOrder = assertOrder(m, size);
int successfulElements = assertMergeAllValuesPresent(tab, n1, tab2, n2, m, size);
//assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
if(successfulOrder && successfulElements){
printf("\nSuccessful merge !\n");
return 1;
}
else{
printf("\nUnsuccessful merge !\n");
return 0;
}
}
//Fonction qui vérifie qu'un tableau est bien trié
//m : le tableau non trié qu'on veut trier
//m_sorted : le tableau m soi-disant trié (on veut vérifier si c'est bien le cas)
//size : la taille du tableau
int assertSorted(int* m, int* m_sorted, int size)
{
int successfulOrder = assertOrder(m_sorted, size); // les éléments du tableau sont ils bien dans le bon ordre ?
int successfulElements = assertSortAllValuesPresent(m, m_sorted, size); //retrouve t-on bien toutes les valeurs ?
if(successfulOrder && successfulElements){
printf("\nSuccessful sort !\n");
return 1;
}
else{
printf("\nUnsuccessful sort !\n");
return 0;
}
}
int main(int argc, char *argv[])
{
std::clock_t startS, endS;
float seqMergeTime, parMergeTime;
srand(time(NULL));
int n_m = 200;
int *m, *mseq, *mref, *mGPU;
if(argc==2)
{
n_m = atoi(argv[1]);
}
printf("========== Path Sort : =========\n");
printf("* Size of array : %d\n\n", n_m);
//int* mseq;
m = (int*)malloc(n_m*sizeof(int));
init_array_no_order(m, n_m, n_m*10);
gpuCheck(cudaMalloc(&mGPU, n_m*sizeof(int)));
gpuCheck(cudaMemcpy(mGPU, m, n_m*sizeof(int), cudaMemcpyHostToDevice));
print_array(m, n_m);
mseq = (int*)malloc(n_m*sizeof(int)); //copie de m
copy_array(m, mseq, n_m);
mref = (int*)malloc(n_m*sizeof(int)); //copie de m
copy_array(m, mref, n_m);
//Partie des calculs1024
//================ Paral1024lel : =======================\\
//Etape de prétraitement :
startS = std::clock();
fusionSort(mGPU, n_m);
cudaDeviceSynchronize();
endS = std::clock();
parMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;
gpuCheck(cudaMemcpy(m, mGPU, n_m*sizeof(int), cudaMemcpyDeviceToHost));
//Etape du tri fusion :
startS = std::clock();
fusionSortSeq(mseq, n_m);
endS = std::clock();
seqMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;
printf("========= Parallel sort : =============\n");
printf("Total time elapsed : %f s\n", parMergeTime);
assertSorted(mref, m, n_m);
printf("Parrallel algorithm is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
printf("Parrallel merge is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
printf("========= Sequential sort : =============\n");
printf("Total time elapsed : %f s\n", seqMergeTime);
// assertSorted(mref, mseq, n_m);
return 0;
} | .file "tmpxft_001babfc_00000000-6_pathSort_test2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
.string "GPUassert: %s %s %d\n"
.section .text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
.weak _Z9gpuAssert9cudaErrorPKcib
.type _Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L9
ret
.L9:
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl %edi, %ebx
movq %rsi, %r13
movl %edx, %r12d
movl %ecx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r12d, %r9d
movq %r13, %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
testb %bpl, %bpl
jne .L10
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %ebx, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
.text
.globl _Z10init_arrayPiii
.type _Z10init_arrayPiii, @function
_Z10init_arrayPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movl %esi, %r12d
movl %edx, %ebp
call rand@PLT
cltd
idivl %ebp
movl %edx, 0(%r13)
testl %r12d, %r12d
jle .L11
movq %r13, %rbx
movslq %r12d, %r12
leaq 0(%r13,%r12,4), %r12
.L13:
movl -4(%rbx), %r13d
call rand@PLT
cltd
idivl %ebp
addl %r13d, %edx
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L13
.L11:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10init_arrayPiii, .-_Z10init_arrayPiii
.globl _Z19init_array_no_orderPiii
.type _Z19init_array_no_orderPiii, @function
_Z19init_array_no_orderPiii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movl %esi, %r12d
movl %edx, %ebp
call rand@PLT
cltd
idivl %ebp
movl %edx, 0(%r13)
testl %r12d, %r12d
jle .L16
movq %r13, %rbx
movslq %r12d, %r12
leaq 0(%r13,%r12,4), %r12
.L18:
call rand@PLT
cltd
idivl %ebp
movl %edx, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L18
.L16:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z19init_array_no_orderPiii, .-_Z19init_array_no_orderPiii
.globl _Z10copy_arrayPiS_i
.type _Z10copy_arrayPiS_i, @function
_Z10copy_arrayPiS_i:
.LFB2060:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L21
movslq %edx, %rdx
leaq 0(,%rdx,4), %rcx
movl $0, %eax
.L23:
movl (%rdi,%rax), %edx
movl %edx, (%rsi,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L23
.L21:
ret
.cfi_endproc
.LFE2060:
.size _Z10copy_arrayPiS_i, .-_Z10copy_arrayPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "["
.LC2:
.string "%d "
.LC3:
.string "]\n"
.text
.globl _Z11print_arrayPii
.type _Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2061:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L26
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC2(%rip), %rbp
.L27:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L27
.L26:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z11print_arrayPii, .-_Z11print_arrayPii
.globl _Z12mergeSmall_kPiS_S_iii
.type _Z12mergeSmall_kPiS_S_iii, @function
_Z12mergeSmall_kPiS_S_iii:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z12mergeSmall_kPiS_S_iii, .-_Z12mergeSmall_kPiS_S_iii
.globl _Z14fusionMergeSeqPiS_iiii
.type _Z14fusionMergeSeqPiS_iiii, @function
_Z14fusionMergeSeqPiS_iiii:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %r11
movl %ecx, %esi
cmpl %ecx, %edx
jg .L42
cmpl %r9d, %r8d
jg .L42
movq %r11, %rcx
movl $1, %eax
jmp .L36
.L34:
movl %r10d, (%rcx)
movl %eax, %r10d
addl $1, %r8d
.L35:
addl $1, %eax
addq $4, %rcx
cmpl %esi, %edx
jg .L33
cmpl %r9d, %r8d
jg .L33
.L36:
movslq %edx, %r10
movl (%rdi,%r10,4), %ebx
movslq %r8d, %r10
movl (%rdi,%r10,4), %r10d
cmpl %r10d, %ebx
jg .L34
movl %ebx, (%rcx)
movl %eax, %r10d
addl $1, %edx
jmp .L35
.L42:
movl $0, %r10d
.L33:
cmpl %edx, %esi
jl .L38
movslq %edx, %rax
movslq %r10d, %rcx
subq %rax, %rcx
leaq (%r11,%rcx,4), %rbx
.L39:
movl (%rdi,%rax,4), %ecx
movl %ecx, (%rbx,%rax,4)
addq $1, %rax
cmpl %eax, %esi
jge .L39
leal 1(%r10,%rsi), %r10d
subl %edx, %r10d
.L38:
cmpl %r8d, %r9d
jl .L32
movslq %r8d, %r8
movslq %r10d, %r10
subq %r8, %r10
leaq (%r11,%r10,4), %rdx
.L41:
movl (%rdi,%r8,4), %eax
movl %eax, (%rdx,%r8,4)
addq $1, %r8
cmpl %r8d, %r9d
jge .L41
.L32:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z14fusionMergeSeqPiS_iiii, .-_Z14fusionMergeSeqPiS_iiii
.globl _Z13fusionSortSeqPii
.type _Z13fusionSortSeqPii, @function
_Z13fusionSortSeqPii:
.LFB2065:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 24(%rsp)
movl %esi, %r15d
movslq %esi, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
movl $1, %edi
leal -1(%r15), %eax
movl %eax, 44(%rsp)
cmpl $1, %r15d
jg .L48
.L49:
movq %rbx, %rdi
call free@PLT
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl 40(%rsp), %eax
addl %eax, %r15d
movq 32(%rsp), %rax
addq %rax, %rbp
cmpl %r13d, %r14d
jge .L50
.L54:
movl %r15d, 12(%rsp)
leal -1(%r15), %eax
movl %eax, 16(%rsp)
movl %r14d, %eax
movl 20(%rsp), %edi
addl %edi, %r14d
leal -1(%r14), %r12d
movl %r14d, %esi
movl %eax, 8(%rsp)
subl %eax, %esi
movslq %esi, %rsi
salq $2, %rsi
movq %rbx, %rdi
call realloc@PLT
movq %rax, %rbx
cmpl %r13d, %r15d
jge .L50
cmpl %r12d, %r13d
cmovle 44(%rsp), %r12d
movl %r12d, %r9d
movl 12(%rsp), %r8d
movl 16(%rsp), %ecx
movl 8(%rsp), %edx
movq %rax, %rsi
movq 24(%rsp), %rdi
call _Z14fusionMergeSeqPiS_iiii
movl 8(%rsp), %eax
subl %eax, %r12d
js .L52
leal 1(%r12), %ecx
salq $2, %rcx
movl $0, %eax
.L53:
movl (%rbx,%rax), %edx
movl %edx, 0(%rbp,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L53
jmp .L52
.L50:
movl 20(%rsp), %edi
movl %r13d, %r15d
cmpl %r13d, %edi
jge .L49
.L48:
movl %edi, %eax
addl %edi, %edi
movl %edi, 40(%rsp)
movl %eax, %r13d
movslq %edi, %rax
salq $2, %rax
movq %rax, 32(%rsp)
movq 24(%rsp), %rbp
movl $0, %r14d
movl %edi, 20(%rsp)
movl %r15d, %eax
movl %r13d, %r15d
movl %eax, %r13d
jmp .L54
.cfi_endproc
.LFE2065:
.size _Z13fusionSortSeqPii, .-_Z13fusionSortSeqPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "WARNING : Unsuccessful merge or sort ... : unordered array on indice %d ...\n"
.section .rodata.str1.1
.LC5:
.string "tab[i]= %d > tab[i+1] = %d\n"
.text
.globl _Z11assertOrderPii
.type _Z11assertOrderPii, @function
_Z11assertOrderPii:
.LFB2066:
.cfi_startproc
endbr64
cmpl $1, %esi
jle .L66
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
subl $1, %esi
movl $0, %edx
.L65:
movq %rbx, %rbp
addq $4, %rbx
movl 4(%rbp), %eax
cmpl %eax, 0(%rbp)
jg .L72
addl $1, %edx
cmpl %esi, %edx
jne .L65
movl $1, %eax
jmp .L62
.L72:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx), %ecx
movl 0(%rbp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L62:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore 3
.cfi_restore 6
movl $1, %eax
ret
.cfi_endproc
.LFE2066:
.size _Z11assertOrderPii, .-_Z11assertOrderPii
.section .rodata.str1.8
.align 8
.LC6:
.string "\nWARNING : Unsuccessful merge : incorrect elements...\n"
.text
.globl _Z27assertMergeAllValuesPresentPiiS_iS_i
.type _Z27assertMergeAllValuesPresentPiiS_iS_i, @function
_Z27assertMergeAllValuesPresentPiiS_iS_i:
.LFB2067:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $16, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %rdi, %r12
movq %rdx, %rbx
movl %ecx, %r11d
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
movslq %r9d, %r10
salq $2, %r10
leaq 15(%r10), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L74:
cmpq %rdx, %rsp
je .L75
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L74
.L75:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L76
orq $0, -8(%rsp,%rax)
.L76:
movq %rsp, %rcx
testl %r9d, %r9d
jle .L93
movq %rcx, %rdi
leaq (%rcx,%r10), %r9
movq %rcx, %rax
.L78:
movl $0, (%rax)
addq $4, %rax
cmpq %r9, %rax
jne .L78
movslq %esi, %rax
leaq (%r12,%rax,4), %r13
movl $0, %r14d
jmp .L79
.L80:
addq $4, %rax
cmpq %r13, %rax
je .L84
.L81:
cmpl %edx, (%rax)
jne .L80
cmpl $0, (%rcx,%r14)
jne .L80
movl $1, (%rcx,%r14)
jmp .L80
.L84:
addq $4, %r14
cmpq %r14, %r10
je .L82
.L79:
testl %esi, %esi
jle .L84
movl (%r8,%r14), %edx
movq %r12, %rax
jmp .L81
.L82:
movslq %r11d, %rax
leaq (%rbx,%rax,4), %rsi
movl $0, %r12d
jmp .L85
.L86:
addq $4, %rax
cmpq %rsi, %rax
je .L90
.L87:
cmpl %edx, (%rax)
jne .L86
cmpl $0, (%rcx,%r12)
jne .L86
movl $1, (%rcx,%r12)
jmp .L86
.L90:
addq $4, %r12
cmpq %r12, %r10
je .L88
.L85:
testl %r11d, %r11d
jle .L90
movl (%r8,%r12), %edx
movq %rbx, %rax
jmp .L87
.L88:
movl (%rdi), %eax
cmpl $1, %eax
jne .L100
addq $4, %rdi
cmpq %r9, %rdi
jne .L88
jmp .L73
.L100:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L73:
movq -40(%rbp), %rdx
subq %fs:40, %rdx
jne .L101
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L93:
.cfi_restore_state
movl $1, %eax
jmp .L73
.L101:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.size _Z27assertMergeAllValuesPresentPiiS_iS_i, .-_Z27assertMergeAllValuesPresentPiiS_iS_i
.section .rodata.str1.1
.LC7:
.string "i : %d\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "\nWARNING : Unsuccessful sort : incorrect elements...\n"
.text
.globl _Z26assertSortAllValuesPresentPiS_i
.type _Z26assertSortAllValuesPresentPiS_i, @function
_Z26assertSortAllValuesPresentPiS_i:
.LFB2068:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
subq $16, %rsp
movq %rdi, %r10
movq %rsi, %r8
movq %fs:40, %rax
movq %rax, -8(%rbp)
xorl %eax, %eax
movslq %edx, %r11
leaq 0(,%r11,4), %r9
leaq 15(%r9), %rax
movq %rax, %rsi
andq $-16, %rsi
andq $-4096, %rax
movq %rsp, %rcx
subq %rax, %rcx
.L103:
cmpq %rcx, %rsp
je .L104
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L103
.L104:
movq %rsi, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L105
orq $0, -8(%rsp,%rax)
.L105:
movq %rsp, %rdi
testl %edx, %edx
jle .L114
movq %rdi, %rax
leaq (%rdi,%r9), %rdx
.L107:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L107
leaq (%r8,%r9), %rcx
movl $0, %esi
jmp .L108
.L109:
addq $4, %rax
cmpq %rcx, %rax
je .L120
.L110:
cmpl %edx, (%rax)
jne .L109
movl $1, (%rdi,%rsi)
jmp .L109
.L120:
addq $4, %rsi
cmpq %rsi, %r9
je .L115
.L108:
movl (%r10,%rsi), %edx
movq %r8, %rax
jmp .L110
.L115:
movl $0, %edx
.L111:
movl (%rdi,%rdx,4), %eax
cmpl $1, %eax
jne .L121
addq $1, %rdx
cmpq %rdx, %r11
jne .L111
jmp .L102
.L121:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L102:
movq -8(%rbp), %rdx
subq %fs:40, %rdx
jne .L122
leave
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L114:
.cfi_restore_state
movl $1, %eax
jmp .L102
.L122:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2068:
.size _Z26assertSortAllValuesPresentPiS_i, .-_Z26assertSortAllValuesPresentPiS_i
.section .rodata.str1.1
.LC9:
.string "\nSuccessful merge !\n"
.LC10:
.string "\nUnsuccessful merge !\n"
.text
.globl _Z11assertMergePiiS_iS_i
.type _Z11assertMergePiiS_iS_i, @function
_Z11assertMergePiiS_iS_i:
.LFB2069:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 8(%rsp)
movl %esi, %r13d
movq %rdx, %r14
movl %ecx, %r15d
movq %r8, %rbx
movl %r9d, %ebp
movl %r9d, %esi
movq %r8, %rdi
call _Z11assertOrderPii
movl %eax, %r12d
movl %ebp, %r9d
movq %rbx, %r8
movl %r15d, %ecx
movq %r14, %rdx
movl %r13d, %esi
movq 8(%rsp), %rdi
call _Z27assertMergeAllValuesPresentPiiS_iS_i
testl %r12d, %r12d
je .L124
testl %eax, %eax
je .L124
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L123:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L124:
.cfi_restore_state
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L123
.cfi_endproc
.LFE2069:
.size _Z11assertMergePiiS_iS_i, .-_Z11assertMergePiiS_iS_i
.section .rodata.str1.1
.LC11:
.string "\nSuccessful sort !\n"
.LC12:
.string "\nUnsuccessful sort !\n"
.text
.globl _Z12assertSortedPiS_i
.type _Z12assertSortedPiS_i, @function
_Z12assertSortedPiS_i:
.LFB2070:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r13
movq %rsi, %rbx
movl %edx, %ebp
movl %edx, %esi
movq %rbx, %rdi
call _Z11assertOrderPii
movl %eax, %r12d
movl %ebp, %edx
movq %rbx, %rsi
movq %r13, %rdi
call _Z26assertSortAllValuesPresentPiS_i
testl %r12d, %r12d
je .L128
testl %eax, %eax
je .L128
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L127:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L128:
.cfi_restore_state
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L127
.cfi_endproc
.LFE2070:
.size _Z12assertSortedPiS_i, .-_Z12assertSortedPiS_i
.globl _Z34__device_stub__Z12mergeSmall_kPiiiPiii
.type _Z34__device_stub__Z12mergeSmall_kPiiiPiii, @function
_Z34__device_stub__Z12mergeSmall_kPiiiPiii:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L135
.L131:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L136
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L135:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mergeSmall_kPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L131
.L136:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z34__device_stub__Z12mergeSmall_kPiiiPiii, .-_Z34__device_stub__Z12mergeSmall_kPiiiPiii
.globl _Z12mergeSmall_kPiii
.type _Z12mergeSmall_kPiii, @function
_Z12mergeSmall_kPiii:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12mergeSmall_kPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z12mergeSmall_kPiii, .-_Z12mergeSmall_kPiii
.section .rodata.str1.1
.LC13:
.string "Size : %d\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "/home/ubuntu/Datasets/stackv2/train-structured/homerdurand/HPCA/main/pathSort_test2.cu"
.text
.globl _Z10fusionSortPii
.type _Z10fusionSortPii, @function
_Z10fusionSortPii:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movl %esi, %ebp
movslq %esi, %r13
salq $2, %r13
movq %r13, %rdi
call malloc@PLT
cmpl $1, %ebp
jle .L139
movq %rax, %r14
movl $1, %ebx
leaq .LC13(%rip), %r15
jmp .L144
.L147:
movl %ebx, %edx
movl %ebp, %esi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12mergeSmall_kPiiiPiii
jmp .L142
.L148:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $354, %r9d
leaq .LC14(%rip), %r8
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L141:
addl %ebx, %ebx
cmpl %ebx, %ebp
jle .L139
.L144:
cmpl $1023, %ebx
jg .L141
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leal (%rbx,%rbx), %ecx
movl %ecx, 36(%rsp)
movl $1, 40(%rsp)
movl %ebp, %eax
cltd
idivl %ecx
addl $1, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L147
.L142:
movl $2, %ecx
movq %r13, %rdx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L148
call cudaDeviceSynchronize@PLT
movl %ebp, %esi
movq %r14, %rdi
call _Z11print_arrayPii
jmp .L141
.L139:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z10fusionSortPii, .-_Z10fusionSortPii
.section .rodata.str1.8
.align 8
.LC15:
.string "========== Path Sort : =========\n"
.section .rodata.str1.1
.LC16:
.string "* Size of array : %d\n\n"
.section .rodata.str1.8
.align 8
.LC18:
.string "========= Parallel sort : =============\n"
.section .rodata.str1.1
.LC19:
.string "Total time elapsed : %f s\n"
.section .rodata.str1.8
.align 8
.LC20:
.string "Parrallel algorithm is %f times faster than sequential merge !\n"
.align 8
.LC21:
.string "Parrallel merge is %f times faster than sequential merge !\n"
.align 8
.LC22:
.string "========= Sequential sort : =============\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movl %edi, %ebp
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $200, %ebx
cmpl $2, %ebp
je .L154
.L150:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
leal (%rbx,%rbx,4), %edx
addl %edx, %edx
movl %ebx, %esi
movq %rax, %rdi
call _Z19init_array_no_orderPiii
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %edi
movl $1, %ecx
movl $549, %edx
leaq .LC14(%rip), %r14
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $550, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
movl %ebx, %esi
movq %rbp, %rdi
call _Z11print_arrayPii
movq %r12, %rdi
call malloc@PLT
movq %rax, %r13
movl %ebx, %edx
movq %rax, %rsi
movq %rbp, %rdi
call _Z10copy_arrayPiS_i
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
movl %ebx, %edx
movq %rax, %rsi
movq %rbp, %rdi
call _Z10copy_arrayPiS_i
call clock@PLT
movq %rax, (%rsp)
movl %ebx, %esi
movq 16(%rsp), %rdi
call _Z10fusionSortPii
call cudaDeviceSynchronize@PLT
call clock@PLT
movq (%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC17(%rip), %xmm0
movss %xmm0, (%rsp)
movl $2, %ecx
movq %r12, %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $1, %ecx
movl $566, %edx
movq %r14, %rsi
call _Z9gpuAssert9cudaErrorPKcib
call clock@PLT
movq %rax, %r12
movl %ebx, %esi
movq %r13, %rdi
call _Z13fusionSortSeqPii
call clock@PLT
subq %r12, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC17(%rip), %xmm0
movss %xmm0, 12(%rsp)
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
leaq .LC19(%rip), %r12
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl %ebx, %edx
movq %rbp, %rsi
movq %r15, %rdi
call _Z12assertSortedPiS_i
movss 12(%rsp), %xmm0
divss (%rsp), %xmm0
pxor %xmm2, %xmm2
cvtss2sd %xmm0, %xmm2
movq %xmm2, %rbx
movapd %xmm2, %xmm0
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %xmm0
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L155
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L154:
.cfi_restore_state
movq 8(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L150
.L155:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.globl _Z46__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiiPiiS_iS_iP4int2iii
.type _Z46__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiiPiiS_iS_iP4int2iii, @function
_Z46__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiiPiiS_iS_iP4int2iii:
.LFB2098:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq 224(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L160
.L156:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L161
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L160:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10mergeBig_kPiiS_iS_iP4int2iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L156
.L161:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z46__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiiPiiS_iS_iP4int2iii, .-_Z46__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiiPiiS_iS_iP4int2iii
.globl _Z10mergeBig_kPiiS_iS_iP4int2iii
.type _Z10mergeBig_kPiiS_iS_iP4int2iii, @function
_Z10mergeBig_kPiiS_iS_iP4int2iii:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z46__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiiPiiS_iS_iP4int2iii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z10mergeBig_kPiiS_iS_iP4int2iii, .-_Z10mergeBig_kPiiS_iS_iP4int2iii
.globl _Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
.type _Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i, @function
_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i:
.LFB2100:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 40(%rsp)
movq %rcx, 24(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L168
.L164:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L169
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L168:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9pathBig_kiP4int2iPiiS1_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L164
.L169:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2100:
.size _Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i, .-_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
.globl _Z9pathBig_kiP4int2iPiiS1_i
.type _Z9pathBig_kiP4int2iPiiS1_i, @function
_Z9pathBig_kiP4int2iPiiS1_i:
.LFB2101:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _Z9pathBig_kiP4int2iPiiS1_i, .-_Z9pathBig_kiP4int2iPiiS1_i
.section .rodata.str1.1
.LC23:
.string "_Z9pathBig_kiP4int2iPiiS1_i"
.section .rodata.str1.8
.align 8
.LC24:
.string "_Z10mergeBig_kPiiS_iS_iP4int2iii"
.section .rodata.str1.1
.LC25:
.string "_Z12mergeSmall_kPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2103:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC23(%rip), %rdx
movq %rdx, %rcx
leaq _Z9pathBig_kiP4int2iPiiS1_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z10mergeBig_kPiiS_iS_iP4int2iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mergeSmall_kPiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2103:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <ctime>
//Function that verify cuda calls and return cuda error if any
#define gpuCheck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//Initialise ascendant array with random values in
void init_array(int* array, int size, int const adder=10)
{
array[0] = rand()%adder;
for(int i = 0; i < size;i++)
{
array[i] = array[i-1] + rand()%adder;
}
}
//Function that initialise array with random values
void init_array_no_order(int* array, int size, int const adder=10)
{
array[0] = rand()%adder;
for(int i = 0; i < size;i++)
{
array[i] = rand()%adder;
}
}
//Function that copy array in another
void copy_array(int* a, int* a_copy, int n){
for(int i = 0;i < n;i++){
a_copy[i] = a[i];
}
}
//Function that print an array of size size
void print_array(int* a, int size)
{
printf("[");
for(int i = 0; i < size;i++)
{
//printf("i = %d | v = %d " ,i, a[i]);
printf("%d " ,a[i]);
}
printf("]\n");
}
//Device version of parallel merge of a and b in m with |m|<1024
__global__ void mergeSmall_k(int* m, int n, int size)
{
int gbx = blockIdx.x;
int tidx = threadIdx.x;
int i = gbx * blockDim.x + tidx;
if(i < n)
{
int L1, R1, L2, R2;
L1 = gbx*blockDim.x;
R1 = gbx*blockDim.x + size-1;
L2 = gbx*blockDim.x + size;
R2 = gbx*blockDim.x + 2*size-1;
if(L2 < n)
{
// printf("L1 : %d, R1 : %d, L2 : %d, R2 : %d\n", L1, R1, L2, R2);
if(R2 >= n){
R2 = n-1;
}
__shared__ int *d_a, *d_b;
int n_a = R1-L1+1;
int n_b = R2-L2+1;
int n_m = n_a+n_b;
d_a = (int*)malloc(n_a*sizeof(int));
d_b = (int*)malloc(n_b*sizeof(int));
__syncthreads();
// printf("tidx : %d, n_a : %d\n", tidx, n_a);
if (tidx < n_a)
{
// printf("m[%d] : %d\n", i, m[i]);
d_a[tidx] = m[i];
// printf("d_a_%d[%d] = %d\n", gbx, tidx, d_a[tidx]);
}
else if (tidx < n_m)
{
d_b[tidx - n_a] = m[i];
// printf("d_b_%d[%d] = %d\n", gbx, tidx - n_a, d_b[tidx - n_a]);
}
__syncthreads();
int2 K;
int2 P;
int2 Q;
// printf("n_a : %d, n_b : %d\n", n_a, n_b);
if(tidx > n_a)
{
K.x = tidx - n_a;
K.y = n_a;
P.x = n_a;
P.y = tidx - n_a;
}
else
{
K.x = 0;
K.y = tidx;
P.x = tidx;
P.y = 0;
}
int offset = 0;
while(1)
{
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
{
m[i] = d_a[Q.y];
// printf("## m[%d] : %d, d_a_%d[%d] : %d\n",i, m[i], gbx, Q.y, d_a[Q.y]);
}
else
{
m[i] = d_b[Q.x];
// printf("## m[%d] : %d, d_b_%d[%d] : %d\n",i, m[i], gbx, Q.x, d_b[Q.x]);
}
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
__syncthreads();
}
}
}
/**
Parallel version of merge of A and B with |A| + |B| <= 1024
@param d_a, d_b : device versions of arrays to merge
d_m : device version of merge of a and b
n_a, n_b, n_b : respective sizes of d_a, d_b, d_m
*/
__device__ void mergeSmall_k(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
int i = threadIdx.x;
if(i < n_m)
{
int2 K;
int2 P;
int2 Q;
if(i > n_a)
{
K.x = i - n_a;
K.y = n_a;
P.x = n_a;
P.y = i - n_a;
}
else
{
K.x = 0;
K.y = i;
P.x = i;
P.y = 0;
}
int offset = 0;
while(1)
{
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
{
d_m[i] = d_a[Q.y];
}
else
{
d_m[i] = d_b[Q.x];
}
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
}
}
//Giving a path ( from pathBig_k ) each block merge (with mergeParallel) each piece a_k and b_k in m_k of a and b. Then it replace elements in m
__global__ void mergeBig_k(int *m, int n_m, int *a, int n_a, int *b, int n_b, int2 *path, int n_path, int nbPartitions, int size)
{
int blockId = blockIdx.x;
int threadId = threadIdx.x;
int i = blockId * blockDim.x + threadId;
if (blockId <= nbPartitions)//On utilise un block pour chaque partition
{
int x0, y0, x1, y1;
x0 = path[blockId].x;
y0 = path[blockId].y;
x1 = path[blockId+1].x;
y1 = path[blockId+1].y;
const int dimx=x1-x0;
const int dimy = y1-y0;
//A modifier par dimx dimy dimx+dimy
__shared__ int a_k[1024];
__shared__ int b_k[1024];
__shared__ int m_k[1024];
if (threadId < dimx) //On rempli a_k[i] : 0 <= i < dimx
{
a_k[threadId] = a[x0+threadId];
}
else if (threadId < dimy+dimx)//On rempli b_k[i] : indice dimx <= i < dimx+dimy+1
{
b_k[threadId-dimx] = b[y0+threadId-dimx];
}
__syncthreads();
// mergeParallel(m_k, dimx+dimy, size);
m[i] = m_k[threadId];
}
}
//Function that generate a path to break down m into pieces that could be merge without conflict
//On appelle |m|/TPB blocks avec chacun un seul thread. Chaque thread s'occupe de la diagonale thread
__global__ void pathBig_k(int pas, int2* path, int n_path , int* d_a, int n_a ,int* d_b, int n_b)
{
int thread_i = blockIdx.x * blockDim.x + threadIdx.x;
if(thread_i <= (n_a + n_b)/pas) //<------------//On vérifie que l'indice du thread est inférieur à la taille du tableau de retour et qu'il est un multiple du pas
{
int i = thread_i*pas;
int2 K;
int2 P;
int2 Q;
if(i > n_a)
{
K.x = i - n_a;
K.y = n_a;
P.x = n_a;
P.y = i - n_a;
}
else
{
K.x = 0;
K.y = i;
P.x = i;
P.y = 0;
}
int offset = 0;
while(1)
{
//Calcul des coordonnées du milieu de P et K
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
//
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
//
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
//printf("thread : %d => (%d, %d)\n", thread_i, Q.y, Q.x);
//!\\ Problème ordre x et y
path[thread_i].x=Q.y;
path[thread_i].y=Q.x;
}
//Si |m| n'est pas un mutliple de pas, le thread 0 ajoute (n_a, n_b) à la fin du tableau
if (thread_i==0 && (n_a+n_b)%pas!=0)
{
//printf("thread : %d => (%d, %d)\n", thread_i, n_a, n_b);
path[n_path-1].x=n_a;
path[n_path-1].y=n_b;
}
}
//Function that sort any array
void fusionSort(int *mGPU, int n_m)
{
//L1 : indice du premier élément de m_part1
//R1 : indice du dernier élément de m_part1
//L2 : indice du premier élément de m_part2
//R2 : indice du dernier élément de m_part2
int size = 1;
int i;
int *m = (int*)malloc(n_m*sizeof(int));
while (size < n_m)
{
i = 0;
if (size < 1024)
{
printf("Size : %d\n", size);
mergeSmall_k<<<n_m/(2*size) + 1, 2*size>>>(mGPU, n_m, size);
gpuCheck(cudaMemcpy(m, mGPU, n_m*sizeof(int), cudaMemcpyDeviceToHost));
cudaDeviceSynchronize();
print_array(m, n_m);
}
size *= 2;
}
}
void fusionMergeSeq(int* A, int* tmp, int L1, int R1, int L2, int R2){
int i = 0;
while(L1 <= R1 && L2 <= R2){
if(A[L1] <= A[L2]){
tmp[i] = A[L1];
i++;
L1++;
}
else{
tmp[i] = A[L2];
i++;
L2++;
}
}
while(L1 <= R1){
tmp[i] = A[L1];
i++;
L1++;
}
while(L2 <= R2){
tmp[i] = A[L2];
i++;
L2++;
}
}
void fusionSortSeq(int* A, int n){
int len = 1;
int i;
int L1, R1, L2, R2;
int* tmp = (int*)malloc(n*sizeof(int));
while(len < n){
i = 0;
while(i < n){
L1 = i;
R1 = i + len - 1;
L2 = i + len;
R2 = i + 2*len - 1;
tmp = (int*)realloc(tmp, (R2-L1+1)*sizeof(int));
if(L2 >= n){
break;
}
if(R2 >= n){
R2 = n - 1;
}
fusionMergeSeq(A, tmp, L1, R1, L2, R2);
for(int j = 0;j < R2-L1+1;j++){
A[i+j] = tmp[j];
}
i = i + 2*len;
}
len *= 2;
}
free(tmp);
}
//Fonction qui trie un tableau M en parallèle par tri fusion itératif (question 3)
//Fonctions de vérification
//Fonction qui vérifie qu'un tableau est bien trié (tous ses éléments rangés dans l'ordre croissant)
int assertOrder(int *tab, int size){
for (int i=0; i<size-1; i++){
if (tab[i] > tab[i+1]){
printf("WARNING : Unsuccessful merge or sort ... : unordered array on indice %d ...\n", i);
printf("tab[i]= %d > tab[i+1] = %d\n", tab[i], tab[i+1]);
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments des deux tableaux qu'on veut fusionner
int assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
{
int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
for(int i = 0;i<size;i++){
verif[i] = 0;
}
for (int i=0; i<size; i++){
for(int j = 0;j < n1;j++){
if(tab[j] == m[i] && verif[i] == 0){ //si il y a une valeur identique et que celle-ci n'a pas été vérifiée
verif[i] = 1;
}
}
}
for (int i=0; i<size; i++){
for(int j = 0;j < n2;j++){
if(tab2[j] == m[i] && verif[i] == 0){
verif[i] = 1;
}
}
}
for(int i = 0;i<size;i++){
if(verif[i] != 1){
printf("\nWARNING : Unsuccessful merge : incorrect elements...\n");
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments du tableau qu'on veut trier
int assertSortAllValuesPresent(int* m, int* m_sorted, int size){
int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
for(int i = 0;i<size;i++){
verif[i] = 0;
}
for (int i=0; i<size; i++){
for(int j = 0;j < size;j++){
if(m_sorted[j] == m[i]){ //si il y a une valeur identique
verif[i] = 1;
}
}
}
for(int i = 0;i<size;i++){
if(verif[i] != 1){
printf("i : %d\n", i);
printf("\nWARNING : Unsuccessful sort : incorrect elements...\n");
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'un tableau est bien trié et la fusion de deux tableaux
//tab et tab2 : les deux tableaux qu'on veut fusionner
//m : le tableau qui est la fusion triée de tab et tab2
int assertMerge(int *tab, int n1, int *tab2, int n2, int* m, int size){
int successfulOrder = assertOrder(m, size);
int successfulElements = assertMergeAllValuesPresent(tab, n1, tab2, n2, m, size);
//assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
if(successfulOrder && successfulElements){
printf("\nSuccessful merge !\n");
return 1;
}
else{
printf("\nUnsuccessful merge !\n");
return 0;
}
}
//Fonction qui vérifie qu'un tableau est bien trié
//m : le tableau non trié qu'on veut trier
//m_sorted : le tableau m soi-disant trié (on veut vérifier si c'est bien le cas)
//size : la taille du tableau
int assertSorted(int* m, int* m_sorted, int size)
{
int successfulOrder = assertOrder(m_sorted, size); // les éléments du tableau sont ils bien dans le bon ordre ?
int successfulElements = assertSortAllValuesPresent(m, m_sorted, size); //retrouve t-on bien toutes les valeurs ?
if(successfulOrder && successfulElements){
printf("\nSuccessful sort !\n");
return 1;
}
else{
printf("\nUnsuccessful sort !\n");
return 0;
}
}
int main(int argc, char *argv[])
{
std::clock_t startS, endS;
float seqMergeTime, parMergeTime;
srand(time(NULL));
int n_m = 200;
int *m, *mseq, *mref, *mGPU;
if(argc==2)
{
n_m = atoi(argv[1]);
}
printf("========== Path Sort : =========\n");
printf("* Size of array : %d\n\n", n_m);
//int* mseq;
m = (int*)malloc(n_m*sizeof(int));
init_array_no_order(m, n_m, n_m*10);
gpuCheck(cudaMalloc(&mGPU, n_m*sizeof(int)));
gpuCheck(cudaMemcpy(mGPU, m, n_m*sizeof(int), cudaMemcpyHostToDevice));
print_array(m, n_m);
mseq = (int*)malloc(n_m*sizeof(int)); //copie de m
copy_array(m, mseq, n_m);
mref = (int*)malloc(n_m*sizeof(int)); //copie de m
copy_array(m, mref, n_m);
//Partie des calculs1024
//================ Paral1024lel : =======================\\
//Etape de prétraitement :
startS = std::clock();
fusionSort(mGPU, n_m);
cudaDeviceSynchronize();
endS = std::clock();
parMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;
gpuCheck(cudaMemcpy(m, mGPU, n_m*sizeof(int), cudaMemcpyDeviceToHost));
//Etape du tri fusion :
startS = std::clock();
fusionSortSeq(mseq, n_m);
endS = std::clock();
seqMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;
printf("========= Parallel sort : =============\n");
printf("Total time elapsed : %f s\n", parMergeTime);
assertSorted(mref, m, n_m);
printf("Parrallel algorithm is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
printf("Parrallel merge is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
printf("========= Sequential sort : =============\n");
printf("Total time elapsed : %f s\n", seqMergeTime);
// assertSorted(mref, mseq, n_m);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <ctime>
//Function that verify cuda calls and return cuda error if any
#define gpuCheck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
//Initialise ascendant array with random values in
void init_array(int* array, int size, int const adder=10)
{
array[0] = rand()%adder;
for(int i = 0; i < size;i++)
{
array[i] = array[i-1] + rand()%adder;
}
}
//Function that initialise array with random values
void init_array_no_order(int* array, int size, int const adder=10)
{
array[0] = rand()%adder;
for(int i = 0; i < size;i++)
{
array[i] = rand()%adder;
}
}
//Function that copy array in another
void copy_array(int* a, int* a_copy, int n){
for(int i = 0;i < n;i++){
a_copy[i] = a[i];
}
}
//Function that print an array of size size
void print_array(int* a, int size)
{
printf("[");
for(int i = 0; i < size;i++)
{
//printf("i = %d | v = %d " ,i, a[i]);
printf("%d " ,a[i]);
}
printf("]\n");
}
//Device version of parallel merge of a and b in m with |m|<1024
__global__ void mergeSmall_k(int* m, int n, int size)
{
int gbx = blockIdx.x;
int tidx = threadIdx.x;
int i = gbx * blockDim.x + tidx;
if(i < n)
{
int L1, R1, L2, R2;
L1 = gbx*blockDim.x;
R1 = gbx*blockDim.x + size-1;
L2 = gbx*blockDim.x + size;
R2 = gbx*blockDim.x + 2*size-1;
if(L2 < n)
{
// printf("L1 : %d, R1 : %d, L2 : %d, R2 : %d\n", L1, R1, L2, R2);
if(R2 >= n){
R2 = n-1;
}
__shared__ int *d_a, *d_b;
int n_a = R1-L1+1;
int n_b = R2-L2+1;
int n_m = n_a+n_b;
d_a = (int*)malloc(n_a*sizeof(int));
d_b = (int*)malloc(n_b*sizeof(int));
__syncthreads();
// printf("tidx : %d, n_a : %d\n", tidx, n_a);
if (tidx < n_a)
{
// printf("m[%d] : %d\n", i, m[i]);
d_a[tidx] = m[i];
// printf("d_a_%d[%d] = %d\n", gbx, tidx, d_a[tidx]);
}
else if (tidx < n_m)
{
d_b[tidx - n_a] = m[i];
// printf("d_b_%d[%d] = %d\n", gbx, tidx - n_a, d_b[tidx - n_a]);
}
__syncthreads();
int2 K;
int2 P;
int2 Q;
// printf("n_a : %d, n_b : %d\n", n_a, n_b);
if(tidx > n_a)
{
K.x = tidx - n_a;
K.y = n_a;
P.x = n_a;
P.y = tidx - n_a;
}
else
{
K.x = 0;
K.y = tidx;
P.x = tidx;
P.y = 0;
}
int offset = 0;
while(1)
{
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
{
m[i] = d_a[Q.y];
// printf("## m[%d] : %d, d_a_%d[%d] : %d\n",i, m[i], gbx, Q.y, d_a[Q.y]);
}
else
{
m[i] = d_b[Q.x];
// printf("## m[%d] : %d, d_b_%d[%d] : %d\n",i, m[i], gbx, Q.x, d_b[Q.x]);
}
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
__syncthreads();
}
}
}
/**
Parallel version of merge of A and B with |A| + |B| <= 1024
@param d_a, d_b : device versions of arrays to merge
d_m : device version of merge of a and b
n_a, n_b, n_b : respective sizes of d_a, d_b, d_m
*/
__device__ void mergeSmall_k(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
int i = threadIdx.x;
if(i < n_m)
{
int2 K;
int2 P;
int2 Q;
if(i > n_a)
{
K.x = i - n_a;
K.y = n_a;
P.x = n_a;
P.y = i - n_a;
}
else
{
K.x = 0;
K.y = i;
P.x = i;
P.y = 0;
}
int offset = 0;
while(1)
{
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
{
d_m[i] = d_a[Q.y];
}
else
{
d_m[i] = d_b[Q.x];
}
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
}
}
//Giving a path ( from pathBig_k ) each block merge (with mergeParallel) each piece a_k and b_k in m_k of a and b. Then it replace elements in m
__global__ void mergeBig_k(int *m, int n_m, int *a, int n_a, int *b, int n_b, int2 *path, int n_path, int nbPartitions, int size)
{
int blockId = blockIdx.x;
int threadId = threadIdx.x;
int i = blockId * blockDim.x + threadId;
if (blockId <= nbPartitions)//On utilise un block pour chaque partition
{
int x0, y0, x1, y1;
x0 = path[blockId].x;
y0 = path[blockId].y;
x1 = path[blockId+1].x;
y1 = path[blockId+1].y;
const int dimx=x1-x0;
const int dimy = y1-y0;
//A modifier par dimx dimy dimx+dimy
__shared__ int a_k[1024];
__shared__ int b_k[1024];
__shared__ int m_k[1024];
if (threadId < dimx) //On rempli a_k[i] : 0 <= i < dimx
{
a_k[threadId] = a[x0+threadId];
}
else if (threadId < dimy+dimx)//On rempli b_k[i] : indice dimx <= i < dimx+dimy+1
{
b_k[threadId-dimx] = b[y0+threadId-dimx];
}
__syncthreads();
// mergeParallel(m_k, dimx+dimy, size);
m[i] = m_k[threadId];
}
}
//Function that generate a path to break down m into pieces that could be merge without conflict
//On appelle |m|/TPB blocks avec chacun un seul thread. Chaque thread s'occupe de la diagonale thread
__global__ void pathBig_k(int pas, int2* path, int n_path , int* d_a, int n_a ,int* d_b, int n_b)
{
int thread_i = blockIdx.x * blockDim.x + threadIdx.x;
if(thread_i <= (n_a + n_b)/pas) //<------------//On vérifie que l'indice du thread est inférieur à la taille du tableau de retour et qu'il est un multiple du pas
{
int i = thread_i*pas;
int2 K;
int2 P;
int2 Q;
if(i > n_a)
{
K.x = i - n_a;
K.y = n_a;
P.x = n_a;
P.y = i - n_a;
}
else
{
K.x = 0;
K.y = i;
P.x = i;
P.y = 0;
}
int offset = 0;
while(1)
{
//Calcul des coordonnées du milieu de P et K
offset = abs(K.y - P.y)/2;
Q.x = K.x + offset;
Q.y = K.y - offset;
//
if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
{
//
if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
{
break;
}
else
{
K.x = Q.x + 1;
K.y = Q.y - 1;
}
}
else
{
P.x = Q.x - 1;
P.y = Q.y + 1;
}
}
//printf("thread : %d => (%d, %d)\n", thread_i, Q.y, Q.x);
//!\\ Problème ordre x et y
path[thread_i].x=Q.y;
path[thread_i].y=Q.x;
}
//Si |m| n'est pas un mutliple de pas, le thread 0 ajoute (n_a, n_b) à la fin du tableau
if (thread_i==0 && (n_a+n_b)%pas!=0)
{
//printf("thread : %d => (%d, %d)\n", thread_i, n_a, n_b);
path[n_path-1].x=n_a;
path[n_path-1].y=n_b;
}
}
//Function that sort any array
void fusionSort(int *mGPU, int n_m)
{
//L1 : indice du premier élément de m_part1
//R1 : indice du dernier élément de m_part1
//L2 : indice du premier élément de m_part2
//R2 : indice du dernier élément de m_part2
int size = 1;
int i;
int *m = (int*)malloc(n_m*sizeof(int));
while (size < n_m)
{
i = 0;
if (size < 1024)
{
printf("Size : %d\n", size);
mergeSmall_k<<<n_m/(2*size) + 1, 2*size>>>(mGPU, n_m, size);
gpuCheck(hipMemcpy(m, mGPU, n_m*sizeof(int), hipMemcpyDeviceToHost));
hipDeviceSynchronize();
print_array(m, n_m);
}
size *= 2;
}
}
void fusionMergeSeq(int* A, int* tmp, int L1, int R1, int L2, int R2){
int i = 0;
while(L1 <= R1 && L2 <= R2){
if(A[L1] <= A[L2]){
tmp[i] = A[L1];
i++;
L1++;
}
else{
tmp[i] = A[L2];
i++;
L2++;
}
}
while(L1 <= R1){
tmp[i] = A[L1];
i++;
L1++;
}
while(L2 <= R2){
tmp[i] = A[L2];
i++;
L2++;
}
}
void fusionSortSeq(int* A, int n){
int len = 1;
int i;
int L1, R1, L2, R2;
int* tmp = (int*)malloc(n*sizeof(int));
while(len < n){
i = 0;
while(i < n){
L1 = i;
R1 = i + len - 1;
L2 = i + len;
R2 = i + 2*len - 1;
tmp = (int*)realloc(tmp, (R2-L1+1)*sizeof(int));
if(L2 >= n){
break;
}
if(R2 >= n){
R2 = n - 1;
}
fusionMergeSeq(A, tmp, L1, R1, L2, R2);
for(int j = 0;j < R2-L1+1;j++){
A[i+j] = tmp[j];
}
i = i + 2*len;
}
len *= 2;
}
free(tmp);
}
//Fonction qui trie un tableau M en parallèle par tri fusion itératif (question 3)
//Fonctions de vérification
//Fonction qui vérifie qu'un tableau est bien trié (tous ses éléments rangés dans l'ordre croissant)
int assertOrder(int *tab, int size){
for (int i=0; i<size-1; i++){
if (tab[i] > tab[i+1]){
printf("WARNING : Unsuccessful merge or sort ... : unordered array on indice %d ...\n", i);
printf("tab[i]= %d > tab[i+1] = %d\n", tab[i], tab[i+1]);
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments des deux tableaux qu'on veut fusionner
int assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
{
int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
for(int i = 0;i<size;i++){
verif[i] = 0;
}
for (int i=0; i<size; i++){
for(int j = 0;j < n1;j++){
if(tab[j] == m[i] && verif[i] == 0){ //si il y a une valeur identique et que celle-ci n'a pas été vérifiée
verif[i] = 1;
}
}
}
for (int i=0; i<size; i++){
for(int j = 0;j < n2;j++){
if(tab2[j] == m[i] && verif[i] == 0){
verif[i] = 1;
}
}
}
for(int i = 0;i<size;i++){
if(verif[i] != 1){
printf("\nWARNING : Unsuccessful merge : incorrect elements...\n");
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments du tableau qu'on veut trier
int assertSortAllValuesPresent(int* m, int* m_sorted, int size){
int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
for(int i = 0;i<size;i++){
verif[i] = 0;
}
for (int i=0; i<size; i++){
for(int j = 0;j < size;j++){
if(m_sorted[j] == m[i]){ //si il y a une valeur identique
verif[i] = 1;
}
}
}
for(int i = 0;i<size;i++){
if(verif[i] != 1){
printf("i : %d\n", i);
printf("\nWARNING : Unsuccessful sort : incorrect elements...\n");
return 0;
}
}
return 1;
}
//Fonction qui vérifie qu'un tableau est bien trié et la fusion de deux tableaux
//tab et tab2 : les deux tableaux qu'on veut fusionner
//m : le tableau qui est la fusion triée de tab et tab2
int assertMerge(int *tab, int n1, int *tab2, int n2, int* m, int size){
int successfulOrder = assertOrder(m, size);
int successfulElements = assertMergeAllValuesPresent(tab, n1, tab2, n2, m, size);
//assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
if(successfulOrder && successfulElements){
printf("\nSuccessful merge !\n");
return 1;
}
else{
printf("\nUnsuccessful merge !\n");
return 0;
}
}
//Fonction qui vérifie qu'un tableau est bien trié
//m : le tableau non trié qu'on veut trier
//m_sorted : le tableau m soi-disant trié (on veut vérifier si c'est bien le cas)
//size : la taille du tableau
int assertSorted(int* m, int* m_sorted, int size)
{
int successfulOrder = assertOrder(m_sorted, size); // les éléments du tableau sont ils bien dans le bon ordre ?
int successfulElements = assertSortAllValuesPresent(m, m_sorted, size); //retrouve t-on bien toutes les valeurs ?
if(successfulOrder && successfulElements){
printf("\nSuccessful sort !\n");
return 1;
}
else{
printf("\nUnsuccessful sort !\n");
return 0;
}
}
int main(int argc, char *argv[])
{
std::clock_t startS, endS;
float seqMergeTime, parMergeTime;
srand(time(NULL));
int n_m = 200;
int *m, *mseq, *mref, *mGPU;
if(argc==2)
{
n_m = atoi(argv[1]);
}
printf("========== Path Sort : =========\n");
printf("* Size of array : %d\n\n", n_m);
//int* mseq;
m = (int*)malloc(n_m*sizeof(int));
init_array_no_order(m, n_m, n_m*10);
gpuCheck(hipMalloc(&mGPU, n_m*sizeof(int)));
gpuCheck(hipMemcpy(mGPU, m, n_m*sizeof(int), hipMemcpyHostToDevice));
print_array(m, n_m);
mseq = (int*)malloc(n_m*sizeof(int)); //copie de m
copy_array(m, mseq, n_m);
mref = (int*)malloc(n_m*sizeof(int)); //copie de m
copy_array(m, mref, n_m);
//Partie des calculs1024
//================ Paral1024lel : =======================\\
//Etape de prétraitement :
startS = std::clock();
fusionSort(mGPU, n_m);
hipDeviceSynchronize();
endS = std::clock();
parMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;
gpuCheck(hipMemcpy(m, mGPU, n_m*sizeof(int), hipMemcpyDeviceToHost));
//Etape du tri fusion :
startS = std::clock();
fusionSortSeq(mseq, n_m);
endS = std::clock();
seqMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;
printf("========= Parallel sort : =============\n");
printf("Total time elapsed : %f s\n", parMergeTime);
assertSorted(mref, m, n_m);
printf("Parrallel algorithm is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
printf("Parrallel merge is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
printf("========= Sequential sort : =============\n");
printf("Total time elapsed : %f s\n", seqMergeTime);
// assertSorted(mref, mseq, n_m);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void)
{
printf("Hello World from thread [%d, %d]! From device\n", threadIdx.x, blockIdx.x);
}
int main(void)
{
printf("Hello World from host!\n");
print_from_gpu<<<1,2>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z14print_from_gpuv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*00a0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100a00 */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void)
{
printf("Hello World from thread [%d, %d]! From device\n", threadIdx.x, blockIdx.x);
}
int main(void)
{
printf("Hello World from host!\n");
print_from_gpu<<<1,2>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0000d8fc_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14print_from_gpuvv
.type _Z33__device_stub__Z14print_from_gpuvv, @function
_Z33__device_stub__Z14print_from_gpuvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14print_from_gpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14print_from_gpuvv, .-_Z33__device_stub__Z14print_from_gpuvv
.globl _Z14print_from_gpuv
.type _Z14print_from_gpuv, @function
_Z14print_from_gpuv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14print_from_gpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14print_from_gpuv, .-_Z14print_from_gpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from host!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z33__device_stub__Z14print_from_gpuvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14print_from_gpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14print_from_gpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void)
{
printf("Hello World from thread [%d, %d]! From device\n", threadIdx.x, blockIdx.x);
}
int main(void)
{
printf("Hello World from host!\n");
print_from_gpu<<<1,2>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void)
{
printf("Hello World from thread [%d, %d]! From device\n", threadIdx.x, blockIdx.x);
}
int main(void)
{
printf("Hello World from host!\n");
print_from_gpu<<<1,2>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void print_from_gpu(void)
{
printf("Hello World from thread [%d, %d]! From device\n", threadIdx.x, blockIdx.x);
}
int main(void)
{
printf("Hello World from host!\n");
print_from_gpu<<<1,2>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "hello_world.hip"
.globl _Z29__device_stub__print_from_gpuv # -- Begin function _Z29__device_stub__print_from_gpuv
.p2align 4, 0x90
.type _Z29__device_stub__print_from_gpuv,@function
_Z29__device_stub__print_from_gpuv: # @_Z29__device_stub__print_from_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__print_from_gpuv, .Lfunc_end0-_Z29__device_stub__print_from_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14print_from_gpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14print_from_gpuv,@object # @_Z14print_from_gpuv
.section .rodata,"a",@progbits
.globl _Z14print_from_gpuv
.p2align 3, 0x0
_Z14print_from_gpuv:
.quad _Z29__device_stub__print_from_gpuv
.size _Z14print_from_gpuv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14print_from_gpuv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from host!"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__print_from_gpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14print_from_gpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000d8fc_00000000-6_hello_world.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z14print_from_gpuvv
.type _Z33__device_stub__Z14print_from_gpuvv, @function
_Z33__device_stub__Z14print_from_gpuvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z14print_from_gpuv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z14print_from_gpuvv, .-_Z33__device_stub__Z14print_from_gpuvv
.globl _Z14print_from_gpuv
.type _Z14print_from_gpuv, @function
_Z14print_from_gpuv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z14print_from_gpuvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z14print_from_gpuv, .-_Z14print_from_gpuv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello World from host!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z33__device_stub__Z14print_from_gpuvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z14print_from_gpuv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14print_from_gpuv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "hello_world.hip"
.globl _Z29__device_stub__print_from_gpuv # -- Begin function _Z29__device_stub__print_from_gpuv
.p2align 4, 0x90
.type _Z29__device_stub__print_from_gpuv,@function
_Z29__device_stub__print_from_gpuv: # @_Z29__device_stub__print_from_gpuv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z29__device_stub__print_from_gpuv, .Lfunc_end0-_Z29__device_stub__print_from_gpuv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z14print_from_gpuv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14print_from_gpuv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14print_from_gpuv,@object # @_Z14print_from_gpuv
.section .rodata,"a",@progbits
.globl _Z14print_from_gpuv
.p2align 3, 0x0
_Z14print_from_gpuv:
.quad _Z29__device_stub__print_from_gpuv
.size _Z14print_from_gpuv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14print_from_gpuv"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello World from host!"
.size .Lstr, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__print_from_gpuv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14print_from_gpuv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
//__device__ float Determinant(float *a,int n,float *temp);
__device__ __shared__ float result[3];
__device__ void MatrixDeterminant(void *param)
{
float *input = (float *) param;
int warp_size=32;
int n = (int)input[0];
float* matrix = input+1;
int thread = threadIdx.x % warp_size;
float value =0;
float *det = matrix +n*n;
if(n < 1){
//Error return 0
value = 0;
}
else {
if(n==1)
value = matrix[0];
else if(n==2)
value = matrix[0] * matrix[3] - matrix[2] * matrix[1];
else if (n==3){
if(thread < 3){
result[thread] = pow(-1.0,thread) *(matrix[thread]*(matrix[1*n + (thread+1)%3]*matrix[2*n + (thread+2)%3] - matrix[1*n + (thread+2)%3]*matrix[2 *n + (thread+1)%3]));
}
}
else
value = 0;//This program works only for n=1 to 3
}
if(n==3 && thread ==0)
{
for(int i=0; i < n; i++)
{
value = value + result[i];
}
*det = value;
}
else if(n<3)
*det = value;
}
//Recursive function not working
/*
__device__ float Determinant(float *a,int n,float *m)
{
int i,j,j1,j2;
float det = 0;
printf("%dInput\n",n);
if (n < 1) { * Error
} else if (n == 1) { /* Shouldn't get used
det = a[0];
} else if (n == 2) {
det = a[0] * a[3] - a[2] * a[1];
} else {
det = 0;
for (j1=0;j1<n;j1++) {
// m = (float *)malloc((n-1)*(n-1) * sizeof(float));
// for (i=0;i<n-1;i++)
// m[i] = (float *)malloc((n-1)*sizeof(float));
for (i=1;i<n;i++) {
j2 = 0;
for (j=0;j<n;j++) {
if (j == j1)
continue;
m[(i-1)*n+j2] = a[i * n + j];
j2++;
}
}
det += pow(-1.0,1.0+j1+1.0) * a[j1] * Determinant(m,n-1,a);
printf("%f Intermidiate det\n", det);
// free(m);
}
}
return(det);
}*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
//__device__ float Determinant(float *a,int n,float *temp);
__device__ __shared__ float result[3];
__device__ void MatrixDeterminant(void *param)
{
float *input = (float *) param;
int warp_size=32;
int n = (int)input[0];
float* matrix = input+1;
int thread = threadIdx.x % warp_size;
float value =0;
float *det = matrix +n*n;
if(n < 1){
//Error return 0
value = 0;
}
else {
if(n==1)
value = matrix[0];
else if(n==2)
value = matrix[0] * matrix[3] - matrix[2] * matrix[1];
else if (n==3){
if(thread < 3){
result[thread] = pow(-1.0,thread) *(matrix[thread]*(matrix[1*n + (thread+1)%3]*matrix[2*n + (thread+2)%3] - matrix[1*n + (thread+2)%3]*matrix[2 *n + (thread+1)%3]));
}
}
else
value = 0;//This program works only for n=1 to 3
}
if(n==3 && thread ==0)
{
for(int i=0; i < n; i++)
{
value = value + result[i];
}
*det = value;
}
else if(n<3)
*det = value;
}
//Recursive function not working
/*
__device__ float Determinant(float *a,int n,float *m)
{
int i,j,j1,j2;
float det = 0;
printf("%dInput\n",n);
if (n < 1) { * Error
} else if (n == 1) { /* Shouldn't get used
det = a[0];
} else if (n == 2) {
det = a[0] * a[3] - a[2] * a[1];
} else {
det = 0;
for (j1=0;j1<n;j1++) {
// m = (float *)malloc((n-1)*(n-1) * sizeof(float));
// for (i=0;i<n-1;i++)
// m[i] = (float *)malloc((n-1)*sizeof(float));
for (i=1;i<n;i++) {
j2 = 0;
for (j=0;j<n;j++) {
if (j == j1)
continue;
m[(i-1)*n+j2] = a[i * n + j];
j2++;
}
}
det += pow(-1.0,1.0+j1+1.0) * a[j1] * Determinant(m,n-1,a);
printf("%f Intermidiate det\n", det);
// free(m);
}
}
return(det);
}*/ | .file "tmpxft_00087bcf_00000000-6_MatrixDet.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17MatrixDeterminantPv
.type _Z17MatrixDeterminantPv, @function
_Z17MatrixDeterminantPv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z17MatrixDeterminantPv, .-_Z17MatrixDeterminantPv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
//__device__ float Determinant(float *a,int n,float *temp);
__device__ __shared__ float result[3];
__device__ void MatrixDeterminant(void *param)
{
float *input = (float *) param;
int warp_size=32;
int n = (int)input[0];
float* matrix = input+1;
int thread = threadIdx.x % warp_size;
float value =0;
float *det = matrix +n*n;
if(n < 1){
//Error return 0
value = 0;
}
else {
if(n==1)
value = matrix[0];
else if(n==2)
value = matrix[0] * matrix[3] - matrix[2] * matrix[1];
else if (n==3){
if(thread < 3){
result[thread] = pow(-1.0,thread) *(matrix[thread]*(matrix[1*n + (thread+1)%3]*matrix[2*n + (thread+2)%3] - matrix[1*n + (thread+2)%3]*matrix[2 *n + (thread+1)%3]));
}
}
else
value = 0;//This program works only for n=1 to 3
}
if(n==3 && thread ==0)
{
for(int i=0; i < n; i++)
{
value = value + result[i];
}
*det = value;
}
else if(n<3)
*det = value;
}
//Recursive function not working
/*
__device__ float Determinant(float *a,int n,float *m)
{
int i,j,j1,j2;
float det = 0;
printf("%dInput\n",n);
if (n < 1) { * Error
} else if (n == 1) { /* Shouldn't get used
det = a[0];
} else if (n == 2) {
det = a[0] * a[3] - a[2] * a[1];
} else {
det = 0;
for (j1=0;j1<n;j1++) {
// m = (float *)malloc((n-1)*(n-1) * sizeof(float));
// for (i=0;i<n-1;i++)
// m[i] = (float *)malloc((n-1)*sizeof(float));
for (i=1;i<n;i++) {
j2 = 0;
for (j=0;j<n;j++) {
if (j == j1)
continue;
m[(i-1)*n+j2] = a[i * n + j];
j2++;
}
}
det += pow(-1.0,1.0+j1+1.0) * a[j1] * Determinant(m,n-1,a);
printf("%f Intermidiate det\n", det);
// free(m);
}
}
return(det);
}*/ | #include <hip/hip_runtime.h>
#include <stdio.h>
//__device__ float Determinant(float *a,int n,float *temp);
__device__ __shared__ float result[3];
__device__ void MatrixDeterminant(void *param)
{
float *input = (float *) param;
int warp_size=32;
int n = (int)input[0];
float* matrix = input+1;
int thread = threadIdx.x % warp_size;
float value =0;
float *det = matrix +n*n;
if(n < 1){
//Error return 0
value = 0;
}
else {
if(n==1)
value = matrix[0];
else if(n==2)
value = matrix[0] * matrix[3] - matrix[2] * matrix[1];
else if (n==3){
if(thread < 3){
result[thread] = pow(-1.0,thread) *(matrix[thread]*(matrix[1*n + (thread+1)%3]*matrix[2*n + (thread+2)%3] - matrix[1*n + (thread+2)%3]*matrix[2 *n + (thread+1)%3]));
}
}
else
value = 0;//This program works only for n=1 to 3
}
if(n==3 && thread ==0)
{
for(int i=0; i < n; i++)
{
value = value + result[i];
}
*det = value;
}
else if(n<3)
*det = value;
}
//Recursive function not working
/*
__device__ float Determinant(float *a,int n,float *m)
{
int i,j,j1,j2;
float det = 0;
printf("%dInput\n",n);
if (n < 1) { * Error
} else if (n == 1) { /* Shouldn't get used
det = a[0];
} else if (n == 2) {
det = a[0] * a[3] - a[2] * a[1];
} else {
det = 0;
for (j1=0;j1<n;j1++) {
// m = (float *)malloc((n-1)*(n-1) * sizeof(float));
// for (i=0;i<n-1;i++)
// m[i] = (float *)malloc((n-1)*sizeof(float));
for (i=1;i<n;i++) {
j2 = 0;
for (j=0;j<n;j++) {
if (j == j1)
continue;
m[(i-1)*n+j2] = a[i * n + j];
j2++;
}
}
det += pow(-1.0,1.0+j1+1.0) * a[j1] * Determinant(m,n-1,a);
printf("%f Intermidiate det\n", det);
// free(m);
}
}
return(det);
}*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//__device__ float Determinant(float *a,int n,float *temp);
__device__ __shared__ float result[3];
__device__ void MatrixDeterminant(void *param)
{
float *input = (float *) param;
int warp_size=32;
int n = (int)input[0];
float* matrix = input+1;
int thread = threadIdx.x % warp_size;
float value =0;
float *det = matrix +n*n;
if(n < 1){
//Error return 0
value = 0;
}
else {
if(n==1)
value = matrix[0];
else if(n==2)
value = matrix[0] * matrix[3] - matrix[2] * matrix[1];
else if (n==3){
if(thread < 3){
result[thread] = pow(-1.0,thread) *(matrix[thread]*(matrix[1*n + (thread+1)%3]*matrix[2*n + (thread+2)%3] - matrix[1*n + (thread+2)%3]*matrix[2 *n + (thread+1)%3]));
}
}
else
value = 0;//This program works only for n=1 to 3
}
if(n==3 && thread ==0)
{
for(int i=0; i < n; i++)
{
value = value + result[i];
}
*det = value;
}
else if(n<3)
*det = value;
}
//Recursive function not working
/*
__device__ float Determinant(float *a,int n,float *m)
{
int i,j,j1,j2;
float det = 0;
printf("%dInput\n",n);
if (n < 1) { * Error
} else if (n == 1) { /* Shouldn't get used
det = a[0];
} else if (n == 2) {
det = a[0] * a[3] - a[2] * a[1];
} else {
det = 0;
for (j1=0;j1<n;j1++) {
// m = (float *)malloc((n-1)*(n-1) * sizeof(float));
// for (i=0;i<n-1;i++)
// m[i] = (float *)malloc((n-1)*sizeof(float));
for (i=1;i<n;i++) {
j2 = 0;
for (j=0;j<n;j++) {
if (j == j1)
continue;
m[(i-1)*n+j2] = a[i * n + j];
j2++;
}
}
det += pow(-1.0,1.0+j1+1.0) * a[j1] * Determinant(m,n-1,a);
printf("%f Intermidiate det\n", det);
// free(m);
}
}
return(det);
}*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym result
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
//__device__ float Determinant(float *a,int n,float *temp);
__device__ __shared__ float result[3];
__device__ void MatrixDeterminant(void *param)
{
float *input = (float *) param;
int warp_size=32;
int n = (int)input[0];
float* matrix = input+1;
int thread = threadIdx.x % warp_size;
float value =0;
float *det = matrix +n*n;
if(n < 1){
//Error return 0
value = 0;
}
else {
if(n==1)
value = matrix[0];
else if(n==2)
value = matrix[0] * matrix[3] - matrix[2] * matrix[1];
else if (n==3){
if(thread < 3){
result[thread] = pow(-1.0,thread) *(matrix[thread]*(matrix[1*n + (thread+1)%3]*matrix[2*n + (thread+2)%3] - matrix[1*n + (thread+2)%3]*matrix[2 *n + (thread+1)%3]));
}
}
else
value = 0;//This program works only for n=1 to 3
}
if(n==3 && thread ==0)
{
for(int i=0; i < n; i++)
{
value = value + result[i];
}
*det = value;
}
else if(n<3)
*det = value;
}
//Recursive function not working
/*
__device__ float Determinant(float *a,int n,float *m)
{
int i,j,j1,j2;
float det = 0;
printf("%dInput\n",n);
if (n < 1) { * Error
} else if (n == 1) { /* Shouldn't get used
det = a[0];
} else if (n == 2) {
det = a[0] * a[3] - a[2] * a[1];
} else {
det = 0;
for (j1=0;j1<n;j1++) {
// m = (float *)malloc((n-1)*(n-1) * sizeof(float));
// for (i=0;i<n-1;i++)
// m[i] = (float *)malloc((n-1)*sizeof(float));
for (i=1;i<n;i++) {
j2 = 0;
for (j=0;j<n;j++) {
if (j == j1)
continue;
m[(i-1)*n+j2] = a[i * n + j];
j2++;
}
}
det += pow(-1.0,1.0+j1+1.0) * a[j1] * Determinant(m,n-1,a);
printf("%f Intermidiate det\n", det);
// free(m);
}
}
return(det);
}*/ | .text
.file "MatrixDet.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $result, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $12, %r9d
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type result,@object # @result
.local result
.comm result,12,4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "result"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym result
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym result
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00087bcf_00000000-6_MatrixDet.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17MatrixDeterminantPv
.type _Z17MatrixDeterminantPv, @function
_Z17MatrixDeterminantPv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z17MatrixDeterminantPv, .-_Z17MatrixDeterminantPv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixDet.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $result, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $12, %r9d
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type result,@object # @result
.local result
.comm result,12,4
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "result"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym result
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
} | code for sm_80
Function : _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0050*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe40000000800 */
/*0060*/ ULDC UR5, c[0x0][0x164] ; /* 0x0000590000057ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0090*/ ISETP.GE.AND P0, PT, R11, UR4, PT ; /* 0x000000040b007c0c */
/* 0x001fe2000bf06270 */
/*00a0*/ BSSY B0, 0xe10 ; /* 0x00000d6000007945 */
/* 0x000fd80003800000 */
/*00b0*/ @P0 BRA 0xe00 ; /* 0x00000d4000000947 */
/* 0x000fea0003800000 */
/*00c0*/ IMAD R9, R10, c[0x0][0x164], RZ ; /* 0x000059000a097a24 */
/* 0x000fe200078e02ff */
/*00d0*/ MOV R8, R11 ; /* 0x0000000b00087202 */
/* 0x000fe40000000f00 */
/*00e0*/ IABS R5, c[0x0][0x16c] ; /* 0x00005b0000057a13 */
/* 0x000fe20000000000 */
/*00f0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc600078e00ff */
/*0100*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x001e300000209400 */
/*0110*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0120*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*0130*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0140*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*0150*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a03 */
/*0160*/ IMAD R7, R4, R5, RZ ; /* 0x0000000504077224 */
/* 0x000fe200078e02ff */
/*0170*/ IABS R4, R8 ; /* 0x0000000800047213 */
/* 0x000fc80000000000 */
/*0180*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0190*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R0, RZ, RZ, -R3 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a03 */
/*01b0*/ IMAD R0, R5, R0, R4 ; /* 0x0000000005007224 */
/* 0x000fca00078e0204 */
/*01c0*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*01d0*/ @!P2 IADD3 R0, R0, -R5.reuse, RZ ; /* 0x800000050000a210 */
/* 0x080fe40007ffe0ff */
/*01e0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe40003f06070 */
/*0200*/ LOP3.LUT R0, R8, c[0x0][0x16c], RZ, 0x3c, !PT ; /* 0x00005b0008007a12 */
/* 0x000fe400078e3cff */
/*0210*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f45270 */
/*0220*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f26270 */
/*0230*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0240*/ IMAD.MOV.U32 R0, RZ, RZ, R3 ; /* 0x000000ffff007224 */
/* 0x000fca00078e0003 */
/*0250*/ @!P1 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff00009210 */
/* 0x000fe40007ffe1ff */
/*0260*/ @!P2 LOP3.LUT R0, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff00aa12 */
/* 0x000fc800078e33ff */
/*0270*/ IADD3 R6, R9, R0, RZ ; /* 0x0000000009067210 */
/* 0x000fca0007ffe0ff */
/*0280*/ IMAD.WIDE R2, R6, R13, c[0x0][0x180] ; /* 0x0000600006027625 */
/* 0x000fca00078e020d */
/*0290*/ LDG.E R19, [R2.64] ; /* 0x0000000602137981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ BSSY B1, 0xdc0 ; /* 0x00000b1000017945 */
/* 0x000fe20003800000 */
/*02b0*/ IMAD.MOV R5, RZ, RZ, -R0 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a00 */
/*02c0*/ ISETP.GE.AND P0, PT, R19, 0x1, PT ; /* 0x000000011300780c */
/* 0x004fda0003f06270 */
/*02d0*/ @!P0 BRA 0xdb0 ; /* 0x00000ad000008947 */
/* 0x000fea0003800000 */
/*02e0*/ IADD3 R0, R19, -0x1, RZ ; /* 0xffffffff13007810 */
/* 0x000fe20007ffe0ff */
/*02f0*/ I2F R7, R19 ; /* 0x0000001300077306 */
/* 0x0000620000201400 */
/*0300*/ IMAD R16, R9, c[0x0][0x16c], R8.reuse ; /* 0x00005b0009107a24 */
/* 0x100fe200078e0208 */
/*0310*/ BSSY B2, 0x960 ; /* 0x0000064000027945 */
/* 0x000fe20003800000 */
/*0320*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0330*/ IMAD R5, R5, c[0x0][0x16c], R8 ; /* 0x00005b0005057a24 */
/* 0x000fe200078e0208 */
/*0340*/ LOP3.LUT R4, R19, 0x3, RZ, 0xc0, !PT ; /* 0x0000000313047812 */
/* 0x000fe200078ec0ff */
/*0350*/ IMAD R6, R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a24 */
/* 0x000fe200078e02ff */
/*0360*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*0370*/ IMAD.WIDE R16, R16, R13, c[0x0][0x190] ; /* 0x0000640010107625 */
/* 0x000fd000078e020d */
/*0380*/ @!P0 BRA 0x950 ; /* 0x000005c000008947 */
/* 0x000fea0003800000 */
/*0390*/ LDG.E R21, [R16.64] ; /* 0x0000000610157981 */
/* 0x003162000c1e1900 */
/*03a0*/ IMAD.WIDE R2, R6, R13, c[0x0][0x178] ; /* 0x00005e0006027625 */
/* 0x000fc800078e020d */
/*03b0*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0002 */
/*03c0*/ MOV R15, R3 ; /* 0x00000003000f7202 */
/* 0x000fe20000000f00 */
/*03d0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*03e0*/ IMAD.IADD R2, R19, 0x1, -R4 ; /* 0x0000000113027824 */
/* 0x000fc600078e0a04 */
/*03f0*/ LDG.E R13, [R14.64] ; /* 0x000000060e0d7981 */
/* 0x000ea4000c1e1900 */
/*0400*/ IMAD R0, R10, c[0x0][0x168], R13 ; /* 0x00005a000a007a24 */
/* 0x004fe400078e020d */
/*0410*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*0420*/ IMAD R0, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000007a24 */
/* 0x000fc800078e0205 */
/*0430*/ IMAD.WIDE R12, R0, R13, c[0x0][0x188] ; /* 0x00006200000c7625 */
/* 0x000fca00078e020d */
/*0440*/ LDG.E R22, [R12.64] ; /* 0x000000060c167981 */
/* 0x000ea2000c1e1900 */
/*0450*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x000e620000001000 */
/*0460*/ BSSY B3, 0x510 ; /* 0x000000a000037945 */
/* 0x000fe20003800000 */
/*0470*/ FFMA R19, -R7, R0, 1 ; /* 0x3f80000007137423 */
/* 0x002fc80000000100 */
/*0480*/ FFMA R19, R0, R19, R0 ; /* 0x0000001300137223 */
/* 0x000fe40000000000 */
/*0490*/ FCHK P0, R22, R7 ; /* 0x0000000716007302 */
/* 0x004e640000000000 */
/*04a0*/ FFMA R0, R22, R19, RZ ; /* 0x0000001316007223 */
/* 0x000fc800000000ff */
/*04b0*/ FFMA R18, -R7, R0, R22 ; /* 0x0000000007127223 */
/* 0x000fc80000000116 */
/*04c0*/ FFMA R0, R19, R18, R0 ; /* 0x0000001213007223 */
/* 0x000fe20000000000 */
/*04d0*/ @!P0 BRA 0x500 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*04e0*/ MOV R12, 0x500 ; /* 0x00000500000c7802 */
/* 0x000fe40000000f00 */
/*04f0*/ CALL.REL.NOINC 0xe60 ; /* 0x0000096000007944 */
/* 0x021fea0003c00000 */
/*0500*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0510*/ FADD R21, R0, R21 ; /* 0x0000001500157221 */
/* 0x020fca0000000000 */
/*0520*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e8000c101906 */
/*0530*/ LDG.E R13, [R14.64+0x4] ; /* 0x000004060e0d7981 */
/* 0x000ea4000c1e1900 */
/*0540*/ IMAD R0, R10, c[0x0][0x168], R13 ; /* 0x00005a000a007a24 */
/* 0x004fe200078e020d */
/*0550*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fc60000000f00 */
/*0560*/ IMAD R0, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000007a24 */
/* 0x000fc800078e0205 */
/*0570*/ IMAD.WIDE R12, R0, R13, c[0x0][0x188] ; /* 0x00006200000c7625 */
/* 0x000fca00078e020d */
/*0580*/ LDG.E R22, [R12.64] ; /* 0x000000060c167981 */
/* 0x000ea2000c1e1900 */
/*0590*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x000ee20000001000 */
/*05a0*/ BSSY B3, 0x650 ; /* 0x000000a000037945 */
/* 0x000fe20003800000 */
/*05b0*/ FFMA R19, -R7, R0, 1 ; /* 0x3f80000007137423 */
/* 0x008fc80000000100 */
/*05c0*/ FFMA R23, R0, R19, R0 ; /* 0x0000001300177223 */
/* 0x000fe40000000000 */
/*05d0*/ FCHK P0, R22, R7 ; /* 0x0000000716007302 */
/* 0x004ea40000000000 */
/*05e0*/ FFMA R0, R23, R22, RZ ; /* 0x0000001617007223 */
/* 0x000fc800000000ff */
/*05f0*/ FFMA R19, -R7, R0, R22 ; /* 0x0000000007137223 */
/* 0x000fc80000000116 */
/*0600*/ FFMA R0, R23, R19, R0 ; /* 0x0000001317007223 */
/* 0x000fe20000000000 */
/*0610*/ @!P0 BRA 0x640 ; /* 0x0000002000008947 */
/* 0x004fea0003800000 */
/*0620*/ MOV R12, 0x640 ; /* 0x00000640000c7802 */
/* 0x002fe40000000f00 */
/*0630*/ CALL.REL.NOINC 0xe60 ; /* 0x0000082000007944 */
/* 0x001fea0003c00000 */
/*0640*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x002fea0003800000 */
/*0650*/ FADD R21, R21, R0 ; /* 0x0000000015157221 */
/* 0x000fca0000000000 */
/*0660*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e8000c101906 */
/*0670*/ LDG.E R13, [R14.64+0x8] ; /* 0x000008060e0d7981 */
/* 0x000ea4000c1e1900 */
/*0680*/ IMAD R0, R10, c[0x0][0x168], R13 ; /* 0x00005a000a007a24 */
/* 0x004fe400078e020d */
/*0690*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD R0, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000007a24 */
/* 0x000fc800078e0205 */
/*06b0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x188] ; /* 0x00006200000c7625 */
/* 0x000fca00078e020d */
/*06c0*/ LDG.E R22, [R12.64] ; /* 0x000000060c167981 */
/* 0x000ea2000c1e1900 */
/*06d0*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x000ee20000001000 */
/*06e0*/ BSSY B3, 0x790 ; /* 0x000000a000037945 */
/* 0x000fe20003800000 */
/*06f0*/ FFMA R19, -R7, R0, 1 ; /* 0x3f80000007137423 */
/* 0x008fc80000000100 */
/*0700*/ FFMA R23, R0, R19, R0 ; /* 0x0000001300177223 */
/* 0x000fe40000000000 */
/*0710*/ FCHK P0, R22, R7 ; /* 0x0000000716007302 */
/* 0x004ea40000000000 */
/*0720*/ FFMA R0, R23, R22, RZ ; /* 0x0000001617007223 */
/* 0x000fc800000000ff */
/*0730*/ FFMA R19, -R7, R0, R22 ; /* 0x0000000007137223 */
/* 0x000fc80000000116 */
/*0740*/ FFMA R0, R23, R19, R0 ; /* 0x0000001317007223 */
/* 0x000fe20000000000 */
/*0750*/ @!P0 BRA 0x780 ; /* 0x0000002000008947 */
/* 0x004fea0003800000 */
/*0760*/ MOV R12, 0x780 ; /* 0x00000780000c7802 */
/* 0x002fe40000000f00 */
/*0770*/ CALL.REL.NOINC 0xe60 ; /* 0x000006e000007944 */
/* 0x001fea0003c00000 */
/*0780*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x002fea0003800000 */
/*0790*/ FADD R21, R21, R0 ; /* 0x0000000015157221 */
/* 0x000fca0000000000 */
/*07a0*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e8000c101906 */
/*07b0*/ LDG.E R13, [R14.64+0xc] ; /* 0x00000c060e0d7981 */
/* 0x000ea4000c1e1900 */
/*07c0*/ IMAD R0, R10, c[0x0][0x168], R13 ; /* 0x00005a000a007a24 */
/* 0x004fe200078e020d */
/*07d0*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fc600000001ff */
/*07e0*/ IMAD R0, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000007a24 */
/* 0x000fce00078e0205 */
/*07f0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x188] ; /* 0x00006200000c7625 */
/* 0x000fca00078e020d */
/*0800*/ LDG.E R22, [R12.64] ; /* 0x000000060c167981 */
/* 0x000ea2000c1e1900 */
/*0810*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x000ee20000001000 */
/*0820*/ BSSY B3, 0x8d0 ; /* 0x000000a000037945 */
/* 0x000fe20003800000 */
/*0830*/ FFMA R19, -R7, R0, 1 ; /* 0x3f80000007137423 */
/* 0x008fc80000000100 */
/*0840*/ FFMA R23, R0, R19, R0 ; /* 0x0000001300177223 */
/* 0x000fe40000000000 */
/*0850*/ FCHK P0, R22, R7 ; /* 0x0000000716007302 */
/* 0x004ea40000000000 */
/*0860*/ FFMA R0, R23, R22, RZ ; /* 0x0000001617007223 */
/* 0x000fc800000000ff */
/*0870*/ FFMA R19, -R7, R0, R22 ; /* 0x0000000007137223 */
/* 0x000fc80000000116 */
/*0880*/ FFMA R0, R23, R19, R0 ; /* 0x0000001317007223 */
/* 0x000fe20000000000 */
/*0890*/ @!P0 BRA 0x8c0 ; /* 0x0000002000008947 */
/* 0x004fea0003800000 */
/*08a0*/ MOV R12, 0x8c0 ; /* 0x000008c0000c7802 */
/* 0x002fe40000000f00 */
/*08b0*/ CALL.REL.NOINC 0xe60 ; /* 0x000005a000007944 */
/* 0x001fea0003c00000 */
/*08c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x002fea0003800000 */
/*08d0*/ FADD R21, R21, R0 ; /* 0x0000000015157221 */
/* 0x000fe20000000000 */
/*08e0*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */
/* 0x000fe40007ffe0ff */
/*08f0*/ IADD3 R14, P1, R14, 0x10, RZ ; /* 0x000000100e0e7810 */
/* 0x000fe40007f3e0ff */
/*0900*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e2000c101906 */
/*0910*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0920*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe200008e060f */
/*0930*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fd40007ffe0ff */
/*0940*/ @P0 BRA 0x3f0 ; /* 0xfffffaa000000947 */
/* 0x002fea000383ffff */
/*0950*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x003fea0003800000 */
/*0960*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0970*/ @!P0 BRA 0xdb0 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0980*/ IADD3 R14, R6, R3, RZ ; /* 0x00000003060e7210 */
/* 0x000fe20007ffe0ff */
/*0990*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*09a0*/ IMAD.WIDE R14, R14, R13, c[0x0][0x178] ; /* 0x00005e000e0e7625 */
/* 0x000fca00078e020d */
/*09b0*/ LDG.E R3, [R14.64] ; /* 0x000000060e037981 */
/* 0x000ea4000c1e1900 */
/*09c0*/ IMAD R0, R10, c[0x0][0x168], R3 ; /* 0x00005a000a007a24 */
/* 0x004fc800078e0203 */
/*09d0*/ IMAD R0, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000007a24 */
/* 0x000fc800078e0205 */
/*09e0*/ IMAD.WIDE R2, R0, R13, c[0x0][0x188] ; /* 0x0000620000027625 */
/* 0x000fca00078e020d */
/*09f0*/ LDG.E R22, [R2.64] ; /* 0x0000000602167981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x000e220000001000 */
/*0a10*/ BSSY B2, 0xac0 ; /* 0x000000a000027945 */
/* 0x000fe20003800000 */
/*0a20*/ FFMA R13, -R7, R0, 1 ; /* 0x3f800000070d7423 */
/* 0x001fc80000000100 */
/*0a30*/ FFMA R19, R0, R13, R0 ; /* 0x0000000d00137223 */
/* 0x000fe40000000000 */
/*0a40*/ FCHK P0, R22, R7 ; /* 0x0000000716007302 */
/* 0x004e240000000000 */
/*0a50*/ FFMA R0, R19, R22, RZ ; /* 0x0000001613007223 */
/* 0x000fc800000000ff */
/*0a60*/ FFMA R13, -R7, R0, R22 ; /* 0x00000000070d7223 */
/* 0x000fc80000000116 */
/*0a70*/ FFMA R0, R19, R13, R0 ; /* 0x0000000d13007223 */
/* 0x000fe20000000000 */
/*0a80*/ @!P0 BRA 0xab0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0a90*/ MOV R12, 0xab0 ; /* 0x00000ab0000c7802 */
/* 0x000fe40000000f00 */
/*0aa0*/ CALL.REL.NOINC 0xe60 ; /* 0x000003b000007944 */
/* 0x000fea0003c00000 */
/*0ab0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0ac0*/ LDG.E R3, [R16.64] ; /* 0x0000000610037981 */
/* 0x000ea2000c1e1900 */
/*0ad0*/ ISETP.NE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f05270 */
/*0ae0*/ FADD R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x004fca0000000000 */
/*0af0*/ STG.E [R16.64], R3 ; /* 0x0000000310007986 */
/* 0x0001ee000c101906 */
/*0b00*/ @!P0 BRA 0xdb0 ; /* 0x000002a000008947 */
/* 0x000fea0003800000 */
/*0b10*/ LDG.E R13, [R14.64+0x4] ; /* 0x000004060e0d7981 */
/* 0x000ea4000c1e1900 */
/*0b20*/ IMAD R0, R10, c[0x0][0x168], R13 ; /* 0x00005a000a007a24 */
/* 0x004fe200078e020d */
/*0b30*/ MOV R13, 0x4 ; /* 0x00000004000d7802 */
/* 0x000fc60000000f00 */
/*0b40*/ IMAD R0, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000007a24 */
/* 0x000fc800078e0205 */
/*0b50*/ IMAD.WIDE R12, R0, R13, c[0x0][0x188] ; /* 0x00006200000c7625 */
/* 0x000fca00078e020d */
/*0b60*/ LDG.E R22, [R12.64] ; /* 0x000000060c167981 */
/* 0x000ea2000c1e1900 */
/*0b70*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x000e620000001000 */
/*0b80*/ BSSY B2, 0xc30 ; /* 0x000000a000027945 */
/* 0x000fe20003800000 */
/*0b90*/ FFMA R19, -R7, R0, 1 ; /* 0x3f80000007137423 */
/* 0x002fc80000000100 */
/*0ba0*/ FFMA R21, R0, R19, R0 ; /* 0x0000001300157223 */
/* 0x000fe40000000000 */
/*0bb0*/ FCHK P0, R22, R7 ; /* 0x0000000716007302 */
/* 0x004e640000000000 */
/*0bc0*/ FFMA R0, R21, R22, RZ ; /* 0x0000001615007223 */
/* 0x000fc800000000ff */
/*0bd0*/ FFMA R19, -R7, R0, R22 ; /* 0x0000000007137223 */
/* 0x000fc80000000116 */
/*0be0*/ FFMA R0, R21, R19, R0 ; /* 0x0000001315007223 */
/* 0x000fe20000000000 */
/*0bf0*/ @!P0 BRA 0xc20 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0c00*/ MOV R12, 0xc20 ; /* 0x00000c20000c7802 */
/* 0x000fe40000000f00 */
/*0c10*/ CALL.REL.NOINC 0xe60 ; /* 0x0000024000007944 */
/* 0x001fea0003c00000 */
/*0c20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0c30*/ FADD R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x001fe20000000000 */
/*0c40*/ ISETP.NE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x000fc80003f05270 */
/*0c50*/ STG.E [R16.64], R3 ; /* 0x0000000310007986 */
/* 0x0001f2000c101906 */
/*0c60*/ @!P0 BRA 0xdb0 ; /* 0x0000014000008947 */
/* 0x000fea0003800000 */
/*0c70*/ LDG.E R15, [R14.64+0x8] ; /* 0x000008060e0f7981 */
/* 0x000ea2000c1e1900 */
/*0c80*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc400078e00ff */
/*0c90*/ IMAD R0, R10, c[0x0][0x168], R15 ; /* 0x00005a000a007a24 */
/* 0x004fc800078e020f */
/*0ca0*/ IMAD R5, R0, c[0x0][0x16c], R5 ; /* 0x00005b0000057a24 */
/* 0x000fc800078e0205 */
/*0cb0*/ IMAD.WIDE R4, R5, R4, c[0x0][0x188] ; /* 0x0000620005047625 */
/* 0x000fca00078e0204 */
/*0cc0*/ LDG.E R22, [R4.64] ; /* 0x0000000604167981 */
/* 0x000ea2000c1e1900 */
/*0cd0*/ MUFU.RCP R0, R7 ; /* 0x0000000700007308 */
/* 0x000e620000001000 */
/*0ce0*/ BSSY B2, 0xd90 ; /* 0x000000a000027945 */
/* 0x000fe20003800000 */
/*0cf0*/ FFMA R13, -R7, R0, 1 ; /* 0x3f800000070d7423 */
/* 0x002fc80000000100 */
/*0d00*/ FFMA R19, R0, R13, R0 ; /* 0x0000000d00137223 */
/* 0x000fe40000000000 */
/*0d10*/ FCHK P0, R22, R7 ; /* 0x0000000716007302 */
/* 0x004e640000000000 */
/*0d20*/ FFMA R0, R19, R22, RZ ; /* 0x0000001613007223 */
/* 0x000fc800000000ff */
/*0d30*/ FFMA R13, -R7, R0, R22 ; /* 0x00000000070d7223 */
/* 0x000fc80000000116 */
/*0d40*/ FFMA R0, R19, R13, R0 ; /* 0x0000000d13007223 */
/* 0x000fe20000000000 */
/*0d50*/ @!P0 BRA 0xd80 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0d60*/ MOV R12, 0xd80 ; /* 0x00000d80000c7802 */
/* 0x000fe40000000f00 */
/*0d70*/ CALL.REL.NOINC 0xe60 ; /* 0x000000e000007944 */
/* 0x001fea0003c00000 */
/*0d80*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0d90*/ FADD R3, R3, R0 ; /* 0x0000000003037221 */
/* 0x001fca0000000000 */
/*0da0*/ STG.E [R16.64], R3 ; /* 0x0000000310007986 */
/* 0x0001e4000c101906 */
/*0db0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0dc0*/ IADD3 R8, R8, c[0x0][0x0], RZ ; /* 0x0000000008087a10 */
/* 0x000fc80007ffe0ff */
/*0dd0*/ ISETP.GE.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fda000bf06270 */
/*0de0*/ @P0 CALL.REL.NOINC 0xe00 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0df0*/ BRA 0xe0 ; /* 0xfffff2e000007947 */
/* 0x000fea000383ffff */
/*0e00*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e10*/ IADD3 R10, R10, c[0x0][0xc], RZ ; /* 0x000003000a0a7a10 */
/* 0x000fc80007ffe0ff */
/*0e20*/ ISETP.GE.AND P0, PT, R10, c[0x0][0x160], PT ; /* 0x000058000a007a0c */
/* 0x000fda0003f06270 */
/*0e30*/ @P0 CALL.REL.NOINC 0xe50 ; /* 0x0000001000000944 */
/* 0x000fe20003c00000 */
/*0e40*/ BRA 0x90 ; /* 0xfffff24000007947 */
/* 0x000fea000383ffff */
/*0e50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e60*/ SHF.R.U32.HI R0, RZ, 0x17, R7 ; /* 0x00000017ff007819 */
/* 0x000fe20000011607 */
/*0e70*/ BSSY B4, 0x14b0 ; /* 0x0000063000047945 */
/* 0x000fe20003800000 */
/*0e80*/ SHF.R.U32.HI R19, RZ, 0x17, R22 ; /* 0x00000017ff137819 */
/* 0x000fe40000011616 */
/*0e90*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe400078ec0ff */
/*0ea0*/ LOP3.LUT R19, R19, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff13137812 */
/* 0x000fe400078ec0ff */
/*0eb0*/ IADD3 R18, R0, -0x1, RZ ; /* 0xffffffff00127810 */
/* 0x000fe40007ffe0ff */
/*0ec0*/ IADD3 R20, R19, -0x1, RZ ; /* 0xffffffff13147810 */
/* 0x000fc40007ffe0ff */
/*0ed0*/ ISETP.GT.U32.AND P0, PT, R18, 0xfd, PT ; /* 0x000000fd1200780c */
/* 0x000fe40003f04070 */
/*0ee0*/ MOV R23, R7 ; /* 0x0000000700177202 */
/* 0x000fe40000000f00 */
/*0ef0*/ ISETP.GT.U32.OR P0, PT, R20, 0xfd, P0 ; /* 0x000000fd1400780c */
/* 0x000fda0000704470 */
/*0f00*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d8224 */
/* 0x000fe200078e00ff */
/*0f10*/ @!P0 BRA 0x1090 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0f20*/ FSETP.GTU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fe40003f1c200 */
/*0f30*/ FSETP.GTU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fc80003f3c200 */
/*0f40*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0f50*/ @P0 BRA 0x1490 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0f60*/ LOP3.LUT P0, RZ, R23, 0x7fffffff, R22, 0xc8, !PT ; /* 0x7fffffff17ff7812 */
/* 0x000fda000780c816 */
/*0f70*/ @!P0 BRA 0x1470 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0f80*/ FSETP.NEU.FTZ.AND P2, PT, |R22|.reuse, +INF , PT ; /* 0x7f8000001600780b */
/* 0x040fe40003f5d200 */
/*0f90*/ FSETP.NEU.FTZ.AND P1, PT, |R7|, +INF , PT ; /* 0x7f8000000700780b */
/* 0x000fe40003f3d200 */
/*0fa0*/ FSETP.NEU.FTZ.AND P0, PT, |R22|, +INF , PT ; /* 0x7f8000001600780b */
/* 0x000fd60003f1d200 */
/*0fb0*/ @!P1 BRA !P2, 0x1470 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0fc0*/ LOP3.LUT P2, RZ, R22, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff16ff7812 */
/* 0x000fc8000784c0ff */
/*0fd0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0fe0*/ @P1 BRA 0x1450 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0ff0*/ LOP3.LUT P1, RZ, R23, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff17ff7812 */
/* 0x000fc8000782c0ff */
/*1000*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*1010*/ @P0 BRA 0x1420 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*1020*/ ISETP.GE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe40003f06270 */
/*1030*/ ISETP.GE.AND P1, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fd60003f26270 */
/*1040*/ @P0 MOV R13, RZ ; /* 0x000000ff000d0202 */
/* 0x000fe20000000f00 */
/*1050*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, -0x40 ; /* 0xffffffc0ff0d8424 */
/* 0x000fe400078e00ff */
/*1060*/ @!P0 FFMA R22, R22, 1.84467440737095516160e+19, RZ ; /* 0x5f80000016168823 */
/* 0x000fe400000000ff */
/*1070*/ @!P1 FFMA R23, R7, 1.84467440737095516160e+19, RZ ; /* 0x5f80000007179823 */
/* 0x000fe200000000ff */
/*1080*/ @!P1 IADD3 R13, R13, 0x40, RZ ; /* 0x000000400d0d9810 */
/* 0x000fe40007ffe0ff */
/*1090*/ LEA R18, R0, 0xc0800000, 0x17 ; /* 0xc080000000127811 */
/* 0x000fe200078eb8ff */
/*10a0*/ BSSY B5, 0x1410 ; /* 0x0000036000057945 */
/* 0x000fe20003800000 */
/*10b0*/ IADD3 R19, R19, -0x7f, RZ ; /* 0xffffff8113137810 */
/* 0x000fe40007ffe0ff */
/*10c0*/ IADD3 R24, -R18, R23, RZ ; /* 0x0000001712187210 */
/* 0x000fc60007ffe1ff */
/*10d0*/ IMAD R23, R19.reuse, -0x800000, R22 ; /* 0xff80000013177824 */
/* 0x040fe200078e0216 */
/*10e0*/ MUFU.RCP R25, R24 ; /* 0x0000001800197308 */
/* 0x0000620000001000 */
/*10f0*/ FADD.FTZ R18, -R24, -RZ ; /* 0x800000ff18127221 */
/* 0x000fe20000010100 */
/*1100*/ IADD3 R24, R19, 0x7f, -R0 ; /* 0x0000007f13187810 */
/* 0x001fca0007ffe800 */
/*1110*/ IMAD.IADD R13, R24, 0x1, R13 ; /* 0x00000001180d7824 */
/* 0x000fe400078e020d */
/*1120*/ FFMA R20, R25, R18, 1 ; /* 0x3f80000019147423 */
/* 0x002fc80000000012 */
/*1130*/ FFMA R20, R25, R20, R25 ; /* 0x0000001419147223 */
/* 0x000fc80000000019 */
/*1140*/ FFMA R25, R23, R20, RZ ; /* 0x0000001417197223 */
/* 0x000fc800000000ff */
/*1150*/ FFMA R22, R18, R25, R23 ; /* 0x0000001912167223 */
/* 0x000fc80000000017 */
/*1160*/ FFMA R25, R20, R22, R25 ; /* 0x0000001614197223 */
/* 0x000fc80000000019 */
/*1170*/ FFMA R18, R18, R25, R23 ; /* 0x0000001912127223 */
/* 0x000fc80000000017 */
/*1180*/ FFMA R22, R20, R18, R25 ; /* 0x0000001214167223 */
/* 0x000fca0000000019 */
/*1190*/ SHF.R.U32.HI R0, RZ, 0x17, R22 ; /* 0x00000017ff007819 */
/* 0x000fc80000011616 */
/*11a0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fc800078ec0ff */
/*11b0*/ IADD3 R0, R0, R13, RZ ; /* 0x0000000d00007210 */
/* 0x000fc80007ffe0ff */
/*11c0*/ IADD3 R19, R0, -0x1, RZ ; /* 0xffffffff00137810 */
/* 0x000fc80007ffe0ff */
/*11d0*/ ISETP.GE.U32.AND P0, PT, R19, 0xfe, PT ; /* 0x000000fe1300780c */
/* 0x000fda0003f06070 */
/*11e0*/ @!P0 BRA 0x13f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*11f0*/ ISETP.GT.AND P0, PT, R0, 0xfe, PT ; /* 0x000000fe0000780c */
/* 0x000fda0003f04270 */
/*1200*/ @P0 BRA 0x13c0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*1210*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f06270 */
/*1220*/ @P0 BRA 0x1400 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*1230*/ ISETP.GE.AND P0, PT, R0, -0x18, PT ; /* 0xffffffe80000780c */
/* 0x000fe40003f06270 */
/*1240*/ LOP3.LUT R22, R22, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000016167812 */
/* 0x000fd600078ec0ff */
/*1250*/ @!P0 BRA 0x1400 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*1260*/ FFMA.RZ R13, R20, R18.reuse, R25.reuse ; /* 0x00000012140d7223 */
/* 0x180fe2000000c019 */
/*1270*/ ISETP.NE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f45270 */
/*1280*/ FFMA.RP R19, R20, R18.reuse, R25.reuse ; /* 0x0000001214137223 */
/* 0x180fe20000008019 */
/*1290*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*12a0*/ FFMA.RM R18, R20, R18, R25 ; /* 0x0000001214127223 */
/* 0x000fe20000004019 */
/*12b0*/ LOP3.LUT R13, R13, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0d0d7812 */
/* 0x000fe400078ec0ff */
/*12c0*/ IADD3 R20, R0, 0x20, RZ ; /* 0x0000002000147810 */
/* 0x000fe20007ffe0ff */
/*12d0*/ IMAD.MOV R0, RZ, RZ, -R0 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0a00 */
/*12e0*/ LOP3.LUT R13, R13, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000d0d7812 */
/* 0x000fe400078efcff */
/*12f0*/ FSETP.NEU.FTZ.AND P0, PT, R19, R18, PT ; /* 0x000000121300720b */
/* 0x000fc40003f1d000 */
/*1300*/ SHF.L.U32 R20, R13, R20, RZ ; /* 0x000000140d147219 */
/* 0x000fe400000006ff */
/*1310*/ SEL R0, R0, RZ, P2 ; /* 0x000000ff00007207 */
/* 0x000fe40001000000 */
/*1320*/ ISETP.NE.AND P1, PT, R20, RZ, P1 ; /* 0x000000ff1400720c */
/* 0x000fe40000f25270 */
/*1330*/ SHF.R.U32.HI R0, RZ, R0, R13 ; /* 0x00000000ff007219 */
/* 0x000fe4000001160d */
/*1340*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*1350*/ SHF.R.U32.HI R18, RZ, 0x1, R0 ; /* 0x00000001ff127819 */
/* 0x000fc40000011600 */
/*1360*/ SEL R13, RZ, 0x1, !P0 ; /* 0x00000001ff0d7807 */
/* 0x000fc80004000000 */
/*1370*/ LOP3.LUT R13, R13, 0x1, R18, 0xf8, !PT ; /* 0x000000010d0d7812 */
/* 0x000fc800078ef812 */
/*1380*/ LOP3.LUT R13, R13, R0, RZ, 0xc0, !PT ; /* 0x000000000d0d7212 */
/* 0x000fc800078ec0ff */
/*1390*/ IADD3 R13, R18, R13, RZ ; /* 0x0000000d120d7210 */
/* 0x000fc80007ffe0ff */
/*13a0*/ LOP3.LUT R22, R13, R22, RZ, 0xfc, !PT ; /* 0x000000160d167212 */
/* 0x000fe200078efcff */
/*13b0*/ BRA 0x1400 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*13c0*/ LOP3.LUT R22, R22, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000016167812 */
/* 0x000fc800078ec0ff */
/*13d0*/ LOP3.LUT R22, R22, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000016167812 */
/* 0x000fe200078efcff */
/*13e0*/ BRA 0x1400 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*13f0*/ IMAD R22, R13, 0x800000, R22 ; /* 0x008000000d167824 */
/* 0x000fe400078e0216 */
/*1400*/ BSYNC B5 ; /* 0x0000000000057941 */
/* 0x000fea0003800000 */
/*1410*/ BRA 0x14a0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*1420*/ LOP3.LUT R22, R23, 0x80000000, R22, 0x48, !PT ; /* 0x8000000017167812 */
/* 0x000fc800078e4816 */
/*1430*/ LOP3.LUT R22, R22, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000016167812 */
/* 0x000fe200078efcff */
/*1440*/ BRA 0x14a0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1450*/ LOP3.LUT R22, R23, 0x80000000, R22, 0x48, !PT ; /* 0x8000000017167812 */
/* 0x000fe200078e4816 */
/*1460*/ BRA 0x14a0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*1470*/ MUFU.RSQ R22, -QNAN ; /* 0xffc0000000167908 */
/* 0x000e220000001400 */
/*1480*/ BRA 0x14a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1490*/ FADD.FTZ R22, R22, R7 ; /* 0x0000000716167221 */
/* 0x000fe40000010000 */
/*14a0*/ BSYNC B4 ; /* 0x0000000000047941 */
/* 0x000fea0003800000 */
/*14b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe200078e00ff */
/*14c0*/ MOV R0, R22 ; /* 0x0000001600007202 */
/* 0x001fc60000000f00 */
/*14d0*/ RET.REL.NODEC R12 0x0 ; /* 0xffffeb200c007950 */
/* 0x000fea0003c3ffff */
/*14e0*/ BRA 0x14e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*14f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
} | .file "tmpxft_000c56d5_00000000-6_mean_interpolate_forward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.type _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, @function
_Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 224(%rsp), %rax
movq %rax, 24(%rsp)
movq 232(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, .-_Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, @function
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, .-_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 8
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf,@function
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
s_load_b32 s12, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_9
s_clause 0x1
s_load_b128 s[16:19], s[0:1], 0x4
s_load_b32 s20, s[0:1], 0x38
s_add_u32 s2, s0, 56
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s13, s18, 31
s_mul_i32 s21, s18, s16
s_add_i32 s4, s18, s13
s_mul_i32 s22, s15, s16
s_xor_b32 s14, s4, s13
s_mul_i32 s23, s20, s16
v_cvt_f32_u32_e32 v1, s14
s_sub_i32 s4, 0, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, s4, v1
s_load_b256 s[4:11], s[0:1], 0x18
v_cmp_gt_i32_e64 s0, s21, v0
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v6, v1, v2
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s24
s_add_i32 s15, s20, s15
s_add_i32 s22, s22, s23
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_9
.LBB0_3:
s_delay_alu instid0(VALU_DEP_3)
s_and_saveexec_b32 s24, s0
s_cbranch_execz .LBB0_2
s_load_b32 s1, s[2:3], 0xc
v_mov_b32_e32 v7, v0
s_mul_i32 s25, s15, s16
s_mul_i32 s26, s15, s17
s_mul_i32 s27, s25, s18
s_mov_b32 s29, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s28, s1, 0xffff
s_branch .LBB0_6
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s30
v_add_nc_u32_e32 v7, s28, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s21, v7
s_or_b32 s29, vcc_lo, s29
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_2
.LBB0_6:
v_ashrrev_i32_e32 v1, 31, v7
s_mov_b32 s30, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v7, v1
v_xor_b32_e32 v2, v2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v2, v6
v_mul_lo_u32 v4, v3, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v4, 1, v3
v_subrev_nc_u32_e32 v5, s14, v2
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v3, v4, vcc_lo
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_xor_b32_e32 v3, s13, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v5, 1, v4
v_cmp_le_u32_e32 vcc_lo, s14, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v4, v5, vcc_lo
v_xor_b32_e32 v5, v1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v5, v3
v_add_nc_u32_e32 v1, s25, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v8, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v8
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v1, s27, v7
v_add_nc_u32_e32 v5, s22, v5
v_mul_lo_u32 v10, v4, s18
s_mov_b32 s31, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v2, 31, v1
v_sub_nc_u32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_mul_lo_u32 v3, s19, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s10, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s11, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
global_load_b32 v9, v[1:2], off
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_sub_nc_u32_e32 v3, v7, v10
v_cvt_f32_i32_e32 v10, v8
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_8:
global_load_b32 v11, v[4:5], off
v_add_nc_u32_e32 v8, -1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s1, 0, v8
s_or_b32 s31, s1, s31
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v13, s26, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v13, s18, v[3:4]
v_ashrrev_i32_e32 v12, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v11, vcc_lo, s8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
global_load_b32 v11, v[11:12], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v12, null, v10, v10, v11
v_div_scale_f32 v15, vcc_lo, v11, v10, v11
v_rcp_f32_e32 v13, v12
s_waitcnt_depctr 0xfff
v_fma_f32 v14, -v12, v13, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v13, v14, v13
v_mul_f32_e32 v14, v15, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v12, v14, v15
v_fmac_f32_e32 v14, v16, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v12, v14, v15
v_div_fmas_f32 v12, v12, v13, v14
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v11, v12, v10, v11
v_add_f32_e32 v9, v9, v11
global_store_b32 v[1:2], v9, off
s_and_not1_b32 exec_lo, exec_lo, s31
s_cbranch_execnz .LBB0_8
s_branch .LBB0_5
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, .Lfunc_end0-_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mean_interpolate_forward(int B, int N, int M, int C, int K, const int* nnIndex, const int* nnCount, const float* input, float* output)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<N*C;j+=blockDim.x)
{
int n = j/C;
int c = j%C;
int nnSize = nnCount[i*N+n];
for(int k=0;k<nnSize;k++)
{
int m = nnIndex[i*N*K+n*K+k];
output[i*N*C+j] += input[i*M*C+m*C+c]/nnSize;
}
}
}
} | .text
.file "mean_interpolate_forward.hip"
.globl _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf # -- Begin function _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf,@function
_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf: # @_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf, .Lfunc_end0-_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf,@object # @_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.section .rodata,"a",@progbits
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 3, 0x0
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
.quad _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c56d5_00000000-6_mean_interpolate_forward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.type _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, @function
_Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 60(%rsp)
movl %esi, 56(%rsp)
movl %edx, 52(%rsp)
movl %ecx, 48(%rsp)
movl %r8d, 44(%rsp)
movq %r9, 32(%rsp)
movq 224(%rsp), %rax
movq %rax, 24(%rsp)
movq 232(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 16(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf, .-_Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, @function
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z58__device_stub__Z24mean_interpolate_forwardiiiiiPKiS0_PKfPfiiiiiPKiS0_PKfPf
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, .-_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mean_interpolate_forward.hip"
.globl _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf # -- Begin function _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 4, 0x90
.type _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf,@function
_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf: # @_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf, .Lfunc_end0-_Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf,@object # @_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.section .rodata,"a",@progbits
.globl _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.p2align 3, 0x0
_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf:
.quad _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.size _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__mean_interpolate_forwardiiiiiPKiS0_PKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24mean_interpolate_forwardiiiiiPKiS0_PKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void HelloWorldFromGPU(void)
{
printf("Hello world from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
HelloWorldFromGPU<<<1,10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z17HelloWorldFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void HelloWorldFromGPU(void)
{
printf("Hello world from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
HelloWorldFromGPU<<<1,10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_000d1278_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z17HelloWorldFromGPUvv
.type _Z36__device_stub__Z17HelloWorldFromGPUvv, @function
_Z36__device_stub__Z17HelloWorldFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17HelloWorldFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z17HelloWorldFromGPUvv, .-_Z36__device_stub__Z17HelloWorldFromGPUvv
.globl _Z17HelloWorldFromGPUv
.type _Z17HelloWorldFromGPUv, @function
_Z17HelloWorldFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17HelloWorldFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17HelloWorldFromGPUv, .-_Z17HelloWorldFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello world from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z36__device_stub__Z17HelloWorldFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z17HelloWorldFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17HelloWorldFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
__global__ void HelloWorldFromGPU(void)
{
printf("Hello world from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
HelloWorldFromGPU<<<1,10>>>();
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void HelloWorldFromGPU(void)
{
printf("Hello world from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
HelloWorldFromGPU<<<1,10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void HelloWorldFromGPU(void)
{
printf("Hello world from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
HelloWorldFromGPU<<<1,10>>>();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17HelloWorldFromGPUv
.globl _Z17HelloWorldFromGPUv
.p2align 8
.type _Z17HelloWorldFromGPUv,@function
_Z17HelloWorldFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17HelloWorldFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17HelloWorldFromGPUv, .Lfunc_end0-_Z17HelloWorldFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello world from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17HelloWorldFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z17HelloWorldFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void HelloWorldFromGPU(void)
{
printf("Hello world from GPU!\n");
}
int main()
{
printf("Hello world from CPU!\n");
HelloWorldFromGPU<<<1,10>>>();
hipDeviceReset();
return 0;
} | .text
.file "helloworld.hip"
.globl _Z32__device_stub__HelloWorldFromGPUv # -- Begin function _Z32__device_stub__HelloWorldFromGPUv
.p2align 4, 0x90
.type _Z32__device_stub__HelloWorldFromGPUv,@function
_Z32__device_stub__HelloWorldFromGPUv: # @_Z32__device_stub__HelloWorldFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17HelloWorldFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z32__device_stub__HelloWorldFromGPUv, .Lfunc_end0-_Z32__device_stub__HelloWorldFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17HelloWorldFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17HelloWorldFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17HelloWorldFromGPUv,@object # @_Z17HelloWorldFromGPUv
.section .rodata,"a",@progbits
.globl _Z17HelloWorldFromGPUv
.p2align 3, 0x0
_Z17HelloWorldFromGPUv:
.quad _Z32__device_stub__HelloWorldFromGPUv
.size _Z17HelloWorldFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17HelloWorldFromGPUv"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello world from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__HelloWorldFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17HelloWorldFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17HelloWorldFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17HelloWorldFromGPUv
.globl _Z17HelloWorldFromGPUv
.p2align 8
.type _Z17HelloWorldFromGPUv,@function
_Z17HelloWorldFromGPUv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 23
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17HelloWorldFromGPUv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17HelloWorldFromGPUv, .Lfunc_end0-_Z17HelloWorldFromGPUv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello world from GPU!\n"
.size .str, 23
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17HelloWorldFromGPUv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z17HelloWorldFromGPUv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d1278_00000000-6_helloworld.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z17HelloWorldFromGPUvv
.type _Z36__device_stub__Z17HelloWorldFromGPUvv, @function
_Z36__device_stub__Z17HelloWorldFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z17HelloWorldFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z17HelloWorldFromGPUvv, .-_Z36__device_stub__Z17HelloWorldFromGPUvv
.globl _Z17HelloWorldFromGPUv
.type _Z17HelloWorldFromGPUv, @function
_Z17HelloWorldFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z17HelloWorldFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z17HelloWorldFromGPUv, .-_Z17HelloWorldFromGPUv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Hello world from CPU!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z36__device_stub__Z17HelloWorldFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z17HelloWorldFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17HelloWorldFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloworld.hip"
.globl _Z32__device_stub__HelloWorldFromGPUv # -- Begin function _Z32__device_stub__HelloWorldFromGPUv
.p2align 4, 0x90
.type _Z32__device_stub__HelloWorldFromGPUv,@function
_Z32__device_stub__HelloWorldFromGPUv: # @_Z32__device_stub__HelloWorldFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17HelloWorldFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z32__device_stub__HelloWorldFromGPUv, .Lfunc_end0-_Z32__device_stub__HelloWorldFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z17HelloWorldFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17HelloWorldFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17HelloWorldFromGPUv,@object # @_Z17HelloWorldFromGPUv
.section .rodata,"a",@progbits
.globl _Z17HelloWorldFromGPUv
.p2align 3, 0x0
_Z17HelloWorldFromGPUv:
.quad _Z32__device_stub__HelloWorldFromGPUv
.size _Z17HelloWorldFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17HelloWorldFromGPUv"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Hello world from CPU!"
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__HelloWorldFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17HelloWorldFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <vector_types.h>
#include <stdio.h>
#include <random>
using copy1_t = int;
using copy2_t = int2;
using copy4_t = int4;
__global__
void copy(float* buffer) {
extern __shared__ float shmem[];
const int lane_id = threadIdx.x % 32;
#pragma unroll
for (int i = 0; i < 15; ++i) {
*((copy4_t *)(shmem + i * 128) + lane_id) = *((copy4_t *)(buffer + i * 128) + lane_id);
}
}
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
int main(void) {
dim3 dimBlock(32, 1);
dim3 dimGrid(1, 1);
int shmem_bytes = 65536;
float* h = new float[128 * 16];
float* d;
cudaError_t err = cudaMalloc((void **) &d, 128 * 16 * sizeof(float));
initRandMatrix(h, 16, 128);
cudaMemcpy(d, h, 128 * 16 * sizeof(float), cudaMemcpyHostToDevice);
cudaFuncSetAttribute(copy, cudaFuncAttributeMaxDynamicSharedMemorySize, shmem_bytes);
copy<<<dimGrid, dimBlock, shmem_bytes>>>(d);
delete [] h;
cudaFree(d);
return 0;
}
/*
printf(" Total amount of shared memory per block: %zu bytes\n",
deviceProp.sharedMemPerBlock);
*/ | code for sm_80
Function : _Z4copyPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ SHF.L.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007819 */
/* 0x001fc800000006ff */
/*0040*/ LOP3.LUT R0, R0, 0x1f0, RZ, 0xc0, !PT ; /* 0x000001f000007812 */
/* 0x000fc800078ec0ff */
/*0050*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fca0007f1e0ff */
/*0060*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0070*/ LDG.E.128.CONSTANT R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ea8000c1e9d00 */
/*0080*/ LDG.E.128.CONSTANT R4, [R2.64+0x800] ; /* 0x0008000402047981 */
/* 0x000ee8000c1e9d00 */
/*0090*/ LDG.E.128.CONSTANT R8, [R2.64+0xa00] ; /* 0x000a000402087981 */
/* 0x000f28000c1e9d00 */
/*00a0*/ LDG.E.128.CONSTANT R12, [R2.64+0xc00] ; /* 0x000c0004020c7981 */
/* 0x000f68000c1e9d00 */
/*00b0*/ LDG.E.128.CONSTANT R16, [R2.64+0xe00] ; /* 0x000e000402107981 */
/* 0x000f68000c1e9d00 */
/*00c0*/ LDG.E.128.CONSTANT R20, [R2.64+0x1000] ; /* 0x0010000402147981 */
/* 0x000f68000c1e9d00 */
/*00d0*/ LDG.E.128.CONSTANT R28, [R2.64+0x200] ; /* 0x00020004021c7981 */
/* 0x000f68000c1e9d00 */
/*00e0*/ LDG.E.128.CONSTANT R32, [R2.64+0x400] ; /* 0x0004000402207981 */
/* 0x000f68000c1e9d00 */
/*00f0*/ LDG.E.128.CONSTANT R36, [R2.64+0x600] ; /* 0x0006000402247981 */
/* 0x000f68000c1e9d00 */
/*0100*/ STS.128 [R0], R24 ; /* 0x0000001800007388 */
/* 0x004fe80000000c00 */
/*0110*/ STS.128 [R0+0x800], R4 ; /* 0x0008000400007388 */
/* 0x0081e80000000c00 */
/*0120*/ STS.128 [R0+0xa00], R8 ; /* 0x000a000800007388 */
/* 0x0103e80000000c00 */
/*0130*/ STS.128 [R0+0xc00], R12 ; /* 0x000c000c00007388 */
/* 0x0205e80000000c00 */
/*0140*/ STS.128 [R0+0xe00], R16 ; /* 0x000e001000007388 */
/* 0x0007e80000000c00 */
/*0150*/ STS.128 [R0+0x1000], R20 ; /* 0x0010001400007388 */
/* 0x0009e80000000c00 */
/*0160*/ LDG.E.128.CONSTANT R4, [R2.64+0x1200] ; /* 0x0012000402047981 */
/* 0x001f68000c1e9d00 */
/*0170*/ LDG.E.128.CONSTANT R8, [R2.64+0x1400] ; /* 0x0014000402087981 */
/* 0x002f68000c1e9d00 */
/*0180*/ LDG.E.128.CONSTANT R12, [R2.64+0x1600] ; /* 0x00160004020c7981 */
/* 0x004ea8000c1e9d00 */
/*0190*/ LDG.E.128.CONSTANT R16, [R2.64+0x1800] ; /* 0x0018000402107981 */
/* 0x008ee8000c1e9d00 */
/*01a0*/ LDG.E.128.CONSTANT R20, [R2.64+0x1a00] ; /* 0x001a000402147981 */
/* 0x010f28000c1e9d00 */
/*01b0*/ LDG.E.128.CONSTANT R24, [R2.64+0x1c00] ; /* 0x001c000402187981 */
/* 0x000f28000c1e9d00 */
/*01c0*/ STS.128 [R0+0x200], R28 ; /* 0x0002001c00007388 */
/* 0x000fe80000000c00 */
/*01d0*/ STS.128 [R0+0x400], R32 ; /* 0x0004002000007388 */
/* 0x000fe80000000c00 */
/*01e0*/ STS.128 [R0+0x600], R36 ; /* 0x0006002400007388 */
/* 0x000fe80000000c00 */
/*01f0*/ STS.128 [R0+0x1200], R4 ; /* 0x0012000400007388 */
/* 0x020fe80000000c00 */
/*0200*/ STS.128 [R0+0x1400], R8 ; /* 0x0014000800007388 */
/* 0x000fe80000000c00 */
/*0210*/ STS.128 [R0+0x1600], R12 ; /* 0x0016000c00007388 */
/* 0x004fe80000000c00 */
/*0220*/ STS.128 [R0+0x1800], R16 ; /* 0x0018001000007388 */
/* 0x008fe80000000c00 */
/*0230*/ STS.128 [R0+0x1a00], R20 ; /* 0x001a001400007388 */
/* 0x010fe80000000c00 */
/*0240*/ STS.128 [R0+0x1c00], R24 ; /* 0x001c001800007388 */
/* 0x000fe20000000c00 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <vector_types.h>
#include <stdio.h>
#include <random>
using copy1_t = int;
using copy2_t = int2;
using copy4_t = int4;
__global__
void copy(float* buffer) {
extern __shared__ float shmem[];
const int lane_id = threadIdx.x % 32;
#pragma unroll
for (int i = 0; i < 15; ++i) {
*((copy4_t *)(shmem + i * 128) + lane_id) = *((copy4_t *)(buffer + i * 128) + lane_id);
}
}
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
int main(void) {
dim3 dimBlock(32, 1);
dim3 dimGrid(1, 1);
int shmem_bytes = 65536;
float* h = new float[128 * 16];
float* d;
cudaError_t err = cudaMalloc((void **) &d, 128 * 16 * sizeof(float));
initRandMatrix(h, 16, 128);
cudaMemcpy(d, h, 128 * 16 * sizeof(float), cudaMemcpyHostToDevice);
cudaFuncSetAttribute(copy, cudaFuncAttributeMaxDynamicSharedMemorySize, shmem_bytes);
copy<<<dimGrid, dimBlock, shmem_bytes>>>(d);
delete [] h;
cudaFree(d);
return 0;
}
/*
printf(" Total amount of shared memory per block: %zu bytes\n",
deviceProp.sharedMemPerBlock);
*/ | .file "tmpxft_0002e076_00000000-6_copy.cudafe1.cpp"
.text
#APP
#NO_APP
.section .text._ZNSt13random_deviceD2Ev,"axG",@progbits,_ZNSt13random_deviceD5Ev,comdat
.align 2
.weak _ZNSt13random_deviceD2Ev
.type _ZNSt13random_deviceD2Ev, @function
_ZNSt13random_deviceD2Ev:
.LFB3901:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3901
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZNSt13random_device7_M_finiEv@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3901:
.globl __gxx_personality_v0
.section .gcc_except_table._ZNSt13random_deviceD2Ev,"aG",@progbits,_ZNSt13random_deviceD5Ev,comdat
.LLSDA3901:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3901-.LLSDACSB3901
.LLSDACSB3901:
.LLSDACSE3901:
.section .text._ZNSt13random_deviceD2Ev,"axG",@progbits,_ZNSt13random_deviceD5Ev,comdat
.size _ZNSt13random_deviceD2Ev, .-_ZNSt13random_deviceD2Ev
.weak _ZNSt13random_deviceD1Ev
.set _ZNSt13random_deviceD1Ev,_ZNSt13random_deviceD2Ev
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4519:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4519:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4copyPfPf
.type _Z23__device_stub__Z4copyPfPf, @function
_Z23__device_stub__Z4copyPfPf:
.LFB4541:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4copyPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4541:
.size _Z23__device_stub__Z4copyPfPf, .-_Z23__device_stub__Z4copyPfPf
.globl _Z4copyPf
.type _Z4copyPf, @function
_Z4copyPf:
.LFB4542:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4copyPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4542:
.size _Z4copyPf, .-_Z4copyPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4copyPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4544:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4copyPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4544:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv:
.LFB5178:
.cfi_startproc
endbr64
movq %rdi, %rdx
leaq 1816(%rdi), %r9
movq %rdi, %rcx
movl $2567483615, %r8d
.L17:
movq (%rcx), %rax
andq $-2147483648, %rax
movq 8(%rcx), %rsi
andl $2147483647, %esi
orq %rsi, %rax
movq %rax, %rsi
shrq %rsi
xorq 3176(%rcx), %rsi
andl $1, %eax
cmovne %r8, %rax
xorq %rsi, %rax
movq %rax, (%rcx)
addq $8, %rcx
cmpq %r9, %rcx
jne .L17
leaq 3168(%rdi), %r8
movl $2567483615, %esi
.L19:
movq 1816(%rdx), %rax
andq $-2147483648, %rax
movq 1824(%rdx), %rcx
andl $2147483647, %ecx
orq %rcx, %rax
movq %rax, %rcx
shrq %rcx
xorq (%rdx), %rcx
andl $1, %eax
cmovne %rsi, %rax
xorq %rcx, %rax
movq %rax, 1816(%rdx)
addq $8, %rdx
cmpq %r8, %rdx
jne .L19
movq 4984(%rdi), %rax
andq $-2147483648, %rax
movq (%rdi), %rdx
andl $2147483647, %edx
orq %rdx, %rax
movq %rax, %rdx
shrq %rdx
xorq 3168(%rdi), %rdx
andl $1, %eax
movl $2567483615, %ecx
cmovne %rcx, %rax
xorq %rdx, %rax
movq %rax, 4984(%rdi)
movq $0, 4992(%rdi)
ret
.cfi_endproc
.LFE5178:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.align 2
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, @function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv:
.LFB5117:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpq $623, 4992(%rdi)
ja .L26
.L24:
movq 4992(%rbx), %rax
leaq 1(%rax), %rdx
movq %rdx, 4992(%rbx)
movq (%rbx,%rax,8), %rax
movq %rax, %rdx
shrq $11, %rdx
movl %edx, %edx
xorq %rax, %rdx
movq %rdx, %rax
salq $7, %rax
andl $2636928640, %eax
xorq %rdx, %rax
movq %rax, %rdx
salq $15, %rdx
andl $4022730752, %edx
xorq %rax, %rdx
movq %rdx, %rax
shrq $18, %rax
xorq %rdx, %rax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv
jmp .L24
.cfi_endproc
.LFE5117:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.align 2
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, @function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE:
.LFB5016:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %rdx, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movslq 4(%rdx), %rbx
movslq (%rdx), %rax
subq %rax, %rbx
movl $4294967294, %eax
cmpq %rbx, %rax
jnb .L38
movq %rdi, %r14
movq %rbx, %rax
shrq $32, %rax
je .L32
movq %rsp, %r15
.L36:
movl $0, (%rsp)
movl $-1, 4(%rsp)
movq %r15, %rdx
movq %rbp, %rsi
movq %r14, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movq %rax, %r13
salq $32, %r13
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %r13, %rax
cmpq %rax, %rbx
jb .L36
cmpq %r13, %rax
jb .L36
jmp .L31
.L38:
addq $1, %rbx
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %ebx, %eax
jnb .L29
movl %ebx, %eax
negl %eax
movl $0, %edx
divl %ebx
movl %edx, %r13d
cmpl %edx, %ecx
jnb .L29
.L30:
movq %rbp, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %rbx, %rax
movq %rax, %rcx
cmpl %r13d, %eax
jb .L30
.L29:
movq %rcx, %rax
shrq $32, %rax
.L31:
addl (%r12), %eax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L39
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq %rsi, %rdi
call _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .L31
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE5016:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.text
.globl _Z14initRandMatrixPfii
.type _Z14initRandMatrixPfii, @function
_Z14initRandMatrixPfii:
.LFB4515:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4515
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movzbl _ZGVZ14initRandMatrixPfiiE2rd(%rip), %eax
testb %al, %al
jne .L41
leaq _ZGVZ14initRandMatrixPfiiE2rd(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
jne .L61
.L41:
movzbl _ZGVZ14initRandMatrixPfiiE3gen(%rip), %eax
testb %al, %al
jne .L45
leaq _ZGVZ14initRandMatrixPfiiE3gen(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
jne .L62
.L45:
movzbl _ZGVZ14initRandMatrixPfiiE3dis(%rip), %eax
testb %al, %al
je .L63
.L47:
cmpl $0, 12(%rsp)
jle .L40
movl $0, %r15d
movl $0, %r14d
movslq 8(%rsp), %rax
movq %rax, 24(%rsp)
leaq _ZZ14initRandMatrixPfiiE3dis(%rip), %rbp
leaq _ZZ14initRandMatrixPfiiE3gen(%rip), %r13
jmp .L49
.L61:
leaq 32(%rsp), %rsi
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
movl $1634100580, 48(%rsp)
movl $1953264993, 51(%rsp)
movq $7, 40(%rsp)
movb $0, 55(%rsp)
leaq _ZZ14initRandMatrixPfiiE2rd(%rip), %rdi
.LEHB0:
call _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE@PLT
.LEHE0:
movq 32(%rsp), %rdi
leaq 48(%rsp), %rax
cmpq %rax, %rdi
je .L42
movq 48(%rsp), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
.L42:
leaq __dso_handle(%rip), %rdx
leaq _ZZ14initRandMatrixPfiiE2rd(%rip), %rsi
leaq _ZNSt13random_deviceD1Ev(%rip), %rdi
call __cxa_atexit@PLT
leaq _ZGVZ14initRandMatrixPfiiE2rd(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L41
.L57:
endbr64
movq %rax, %rbx
leaq 32(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq _ZGVZ14initRandMatrixPfiiE2rd(%rip), %rdi
call __cxa_guard_abort@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L44
call __stack_chk_fail@PLT
.L44:
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L62:
leaq _ZZ14initRandMatrixPfiiE2rd(%rip), %rdi
.LEHB2:
call _ZNSt13random_device9_M_getvalEv@PLT
.LEHE2:
movl %eax, %eax
movq %rax, _ZZ14initRandMatrixPfiiE3gen(%rip)
movl $1, %ecx
leaq -8+_ZZ14initRandMatrixPfiiE3gen(%rip), %r9
leaq 8(%r9), %r8
movabsq $945986875574848801, %rdi
.L46:
movq (%r9,%rcx,8), %rax
movq %rax, %rdx
shrq $30, %rdx
xorq %rdx, %rax
imulq $1812433253, %rax, %rsi
movq %rcx, %rdx
shrq $4, %rdx
movq %rdx, %rax
mulq %rdi
shrq %rdx
imulq $624, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
addl %esi, %eax
movq %rax, (%r8,%rcx,8)
addq $1, %rcx
cmpq $624, %rcx
jne .L46
movq $624, 4992+_ZZ14initRandMatrixPfiiE3gen(%rip)
leaq _ZGVZ14initRandMatrixPfiiE3gen(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L45
.L63:
leaq _ZGVZ14initRandMatrixPfiiE3dis(%rip), %rdi
call __cxa_guard_acquire@PLT
testl %eax, %eax
je .L47
movl $0, _ZZ14initRandMatrixPfiiE3dis(%rip)
movl $1, 4+_ZZ14initRandMatrixPfiiE3dis(%rip)
leaq _ZGVZ14initRandMatrixPfiiE3dis(%rip), %rdi
call __cxa_guard_release@PLT
jmp .L47
.L51:
movslq %r15d, %rax
movq 16(%rsp), %rdi
leaq (%rdi,%rax,4), %rbx
movq 24(%rsp), %rcx
addq %rcx, %rax
leaq (%rdi,%rax,4), %r12
.L50:
movq %rbp, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L50
.L52:
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, 12(%rsp)
je .L40
.L49:
cmpl $0, 8(%rsp)
jg .L51
jmp .L52
.L56:
endbr64
movq %rax, %rbx
leaq _ZGVZ14initRandMatrixPfiiE3gen(%rip), %rdi
call __cxa_guard_abort@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L40:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4515:
.section .gcc_except_table,"a",@progbits
.LLSDA4515:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4515-.LLSDACSB4515
.LLSDACSB4515:
.uleb128 .LEHB0-.LFB4515
.uleb128 .LEHE0-.LEHB0
.uleb128 .L57-.LFB4515
.uleb128 0
.uleb128 .LEHB1-.LFB4515
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.uleb128 .LEHB2-.LFB4515
.uleb128 .LEHE2-.LEHB2
.uleb128 .L56-.LFB4515
.uleb128 0
.uleb128 .LEHB3-.LFB4515
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4515:
.text
.size _Z14initRandMatrixPfii, .-_Z14initRandMatrixPfii
.globl main
.type main, @function
main:
.LFB4516:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $32, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $8192, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $8192, %esi
call cudaMalloc@PLT
movl $128, %edx
movl $16, %esi
movq %rbx, %rdi
call _Z14initRandMatrixPfii
movl $1, %ecx
movl $8192, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $65536, %edx
movl $8, %esi
leaq _Z4copyPf(%rip), %rdi
call cudaFuncSetAttribute@PLT
movl 24(%rsp), %ecx
movl $0, %r9d
movl $65536, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L66:
movq %rbx, %rdi
call _ZdaPv@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L70
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z23__device_stub__Z4copyPfPf
jmp .L66
.L70:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4516:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZGVZ14initRandMatrixPfiiE3dis
.comm _ZGVZ14initRandMatrixPfiiE3dis,8,8
.local _ZZ14initRandMatrixPfiiE3dis
.comm _ZZ14initRandMatrixPfiiE3dis,8,8
.local _ZGVZ14initRandMatrixPfiiE3gen
.comm _ZGVZ14initRandMatrixPfiiE3gen,8,8
.local _ZZ14initRandMatrixPfiiE3gen
.comm _ZZ14initRandMatrixPfiiE3gen,5000,32
.local _ZGVZ14initRandMatrixPfiiE2rd
.comm _ZGVZ14initRandMatrixPfiiE2rd,8,8
.local _ZZ14initRandMatrixPfiiE2rd
.comm _ZZ14initRandMatrixPfiiE2rd,5000,32
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.hidden __dso_handle
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_fp16.h>
#include <vector_types.h>
#include <stdio.h>
#include <random>
using copy1_t = int;
using copy2_t = int2;
using copy4_t = int4;
__global__
void copy(float* buffer) {
extern __shared__ float shmem[];
const int lane_id = threadIdx.x % 32;
#pragma unroll
for (int i = 0; i < 15; ++i) {
*((copy4_t *)(shmem + i * 128) + lane_id) = *((copy4_t *)(buffer + i * 128) + lane_id);
}
}
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
int main(void) {
dim3 dimBlock(32, 1);
dim3 dimGrid(1, 1);
int shmem_bytes = 65536;
float* h = new float[128 * 16];
float* d;
cudaError_t err = cudaMalloc((void **) &d, 128 * 16 * sizeof(float));
initRandMatrix(h, 16, 128);
cudaMemcpy(d, h, 128 * 16 * sizeof(float), cudaMemcpyHostToDevice);
cudaFuncSetAttribute(copy, cudaFuncAttributeMaxDynamicSharedMemorySize, shmem_bytes);
copy<<<dimGrid, dimBlock, shmem_bytes>>>(d);
delete [] h;
cudaFree(d);
return 0;
}
/*
printf(" Total amount of shared memory per block: %zu bytes\n",
deviceProp.sharedMemPerBlock);
*/ | #include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
#include <hip/hip_vector_types.h>
#include <stdio.h>
#include <random>
using copy1_t = int;
using copy2_t = int2;
using copy4_t = int4;
__global__
void copy(float* buffer) {
extern __shared__ float shmem[];
const int lane_id = threadIdx.x % 32;
#pragma unroll
for (int i = 0; i < 15; ++i) {
*((copy4_t *)(shmem + i * 128) + lane_id) = *((copy4_t *)(buffer + i * 128) + lane_id);
}
}
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
int main(void) {
dim3 dimBlock(32, 1);
dim3 dimGrid(1, 1);
int shmem_bytes = 65536;
float* h = new float[128 * 16];
float* d;
hipError_t err = hipMalloc((void **) &d, 128 * 16 * sizeof(float));
initRandMatrix(h, 16, 128);
hipMemcpy(d, h, 128 * 16 * sizeof(float), hipMemcpyHostToDevice);
hipFuncSetAttribute(reinterpret_cast<const void*>(copy), hipFuncAttributeMaxDynamicSharedMemorySize, shmem_bytes);
copy<<<dimGrid, dimBlock, shmem_bytes>>>(d);
delete [] h;
hipFree(d);
return 0;
}
/*
printf(" Total amount of shared memory per block: %zu bytes\n",
deviceProp.sharedMemPerBlock);
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
#include <hip/hip_vector_types.h>
#include <stdio.h>
#include <random>
using copy1_t = int;
using copy2_t = int2;
using copy4_t = int4;
__global__
void copy(float* buffer) {
extern __shared__ float shmem[];
const int lane_id = threadIdx.x % 32;
#pragma unroll
for (int i = 0; i < 15; ++i) {
*((copy4_t *)(shmem + i * 128) + lane_id) = *((copy4_t *)(buffer + i * 128) + lane_id);
}
}
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
int main(void) {
dim3 dimBlock(32, 1);
dim3 dimGrid(1, 1);
int shmem_bytes = 65536;
float* h = new float[128 * 16];
float* d;
hipError_t err = hipMalloc((void **) &d, 128 * 16 * sizeof(float));
initRandMatrix(h, 16, 128);
hipMemcpy(d, h, 128 * 16 * sizeof(float), hipMemcpyHostToDevice);
hipFuncSetAttribute(reinterpret_cast<const void*>(copy), hipFuncAttributeMaxDynamicSharedMemorySize, shmem_bytes);
copy<<<dimGrid, dimBlock, shmem_bytes>>>(d);
delete [] h;
hipFree(d);
return 0;
}
/*
printf(" Total amount of shared memory per block: %zu bytes\n",
deviceProp.sharedMemPerBlock);
*/ | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPf
.globl _Z4copyPf
.p2align 8
.type _Z4copyPf,@function
_Z4copyPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_and_b32_e32 v0, 31, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v60, 4, v0
s_waitcnt lgkmcnt(0)
s_clause 0x3
global_load_b128 v[0:3], v60, s[0:1]
global_load_b128 v[4:7], v60, s[0:1] offset:512
global_load_b128 v[8:11], v60, s[0:1] offset:1024
global_load_b128 v[12:15], v60, s[0:1] offset:1536
v_add_co_u32 v16, s2, s0, v60
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v17, null, s1, 0, s2
v_add_co_u32 v56, vcc_lo, 0x1000, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v57, vcc_lo, 0, v17, vcc_lo
s_clause 0xa
global_load_b128 v[16:19], v60, s[0:1] offset:2048
global_load_b128 v[20:23], v60, s[0:1] offset:2560
global_load_b128 v[24:27], v60, s[0:1] offset:3072
global_load_b128 v[28:31], v60, s[0:1] offset:3584
global_load_b128 v[32:35], v[56:57], off
global_load_b128 v[36:39], v[56:57], off offset:512
global_load_b128 v[40:43], v[56:57], off offset:1024
global_load_b128 v[44:47], v[56:57], off offset:1536
global_load_b128 v[48:51], v[56:57], off offset:2048
global_load_b128 v[52:55], v[56:57], off offset:2560
global_load_b128 v[56:59], v[56:57], off offset:3072
v_add_nc_u32_e32 v60, 0, v60
s_waitcnt vmcnt(14)
ds_store_b128 v60, v[0:3]
s_waitcnt vmcnt(13)
ds_store_b128 v60, v[4:7] offset:512
s_waitcnt vmcnt(12)
ds_store_b128 v60, v[8:11] offset:1024
s_waitcnt vmcnt(11)
ds_store_b128 v60, v[12:15] offset:1536
s_waitcnt vmcnt(10)
ds_store_b128 v60, v[16:19] offset:2048
s_waitcnt vmcnt(9)
ds_store_b128 v60, v[20:23] offset:2560
s_waitcnt vmcnt(8)
ds_store_b128 v60, v[24:27] offset:3072
s_waitcnt vmcnt(7)
ds_store_b128 v60, v[28:31] offset:3584
s_waitcnt vmcnt(6)
ds_store_b128 v60, v[32:35] offset:4096
s_waitcnt vmcnt(5)
ds_store_b128 v60, v[36:39] offset:4608
s_waitcnt vmcnt(4)
ds_store_b128 v60, v[40:43] offset:5120
s_waitcnt vmcnt(3)
ds_store_b128 v60, v[44:47] offset:5632
s_waitcnt vmcnt(2)
ds_store_b128 v60, v[48:51] offset:6144
s_waitcnt vmcnt(1)
ds_store_b128 v60, v[52:55] offset:6656
s_waitcnt vmcnt(0)
ds_store_b128 v60, v[56:59] offset:7168
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 61
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPf, .Lfunc_end0-_Z4copyPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPf
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z4copyPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 61
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hip/hip_fp16.h>
#include <hip/hip_vector_types.h>
#include <stdio.h>
#include <random>
using copy1_t = int;
using copy2_t = int2;
using copy4_t = int4;
__global__
void copy(float* buffer) {
extern __shared__ float shmem[];
const int lane_id = threadIdx.x % 32;
#pragma unroll
for (int i = 0; i < 15; ++i) {
*((copy4_t *)(shmem + i * 128) + lane_id) = *((copy4_t *)(buffer + i * 128) + lane_id);
}
}
void initRandMatrix(float* mem, int rows, int cols) {
static std::random_device rd;
static std::mt19937 gen(rd());
static std::uniform_int_distribution<int> dis(0, 1);
for (int i = 0; i < rows; ++i) {
for (int j = 0; j < cols; ++j) {
mem[j + cols * i] = dis(gen);
}
}
return;
}
int main(void) {
dim3 dimBlock(32, 1);
dim3 dimGrid(1, 1);
int shmem_bytes = 65536;
float* h = new float[128 * 16];
float* d;
hipError_t err = hipMalloc((void **) &d, 128 * 16 * sizeof(float));
initRandMatrix(h, 16, 128);
hipMemcpy(d, h, 128 * 16 * sizeof(float), hipMemcpyHostToDevice);
hipFuncSetAttribute(reinterpret_cast<const void*>(copy), hipFuncAttributeMaxDynamicSharedMemorySize, shmem_bytes);
copy<<<dimGrid, dimBlock, shmem_bytes>>>(d);
delete [] h;
hipFree(d);
return 0;
}
/*
printf(" Total amount of shared memory per block: %zu bytes\n",
deviceProp.sharedMemPerBlock);
*/ | .text
.file "copy.hip"
.globl _Z19__device_stub__copyPf # -- Begin function _Z19__device_stub__copyPf
.p2align 4, 0x90
.type _Z19__device_stub__copyPf,@function
_Z19__device_stub__copyPf: # @_Z19__device_stub__copyPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4copyPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__copyPf, .Lfunc_end0-_Z19__device_stub__copyPf
.cfi_endproc
# -- End function
.globl _Z14initRandMatrixPfii # -- Begin function _Z14initRandMatrixPfii
.p2align 4, 0x90
.type _Z14initRandMatrixPfii,@function
_Z14initRandMatrixPfii: # @_Z14initRandMatrixPfii
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, 8(%rsp) # 8-byte Spill
movzbl _ZGVZ14initRandMatrixPfiiE2rd(%rip), %eax
testb %al, %al
je .LBB1_1
.LBB1_4:
movzbl _ZGVZ14initRandMatrixPfiiE3gen(%rip), %eax
testb %al, %al
je .LBB1_5
.LBB1_10:
movzbl _ZGVZ14initRandMatrixPfiiE3dis(%rip), %eax
testb %al, %al
je .LBB1_11
.LBB1_13:
testl %ebp, %ebp
jle .LBB1_19
# %bb.14: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_15
.p2align 4, 0x90
.LBB1_18: # %._crit_edge
# in Loop: Header=BB1_15 Depth=1
incq %rbp
movl %r15d, %edx
addl %r15d, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_19
.LBB1_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_17 Depth 2
movl %edx, %r15d
testl %edx, %edx
jle .LBB1_18
# %bb.16: # %.lr.ph
# in Loop: Header=BB1_15 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_17: # Parent Loop BB1_15 Depth=1
# => This Inner Loop Header: Depth=2
movl $_ZZ14initRandMatrixPfiiE3dis, %edi
movl $_ZZ14initRandMatrixPfiiE3gen, %esi
movl $_ZZ14initRandMatrixPfiiE3dis, %edx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rbx,4)
incq %rbx
cmpq %rbx, %r12
jne .LBB1_17
jmp .LBB1_18
.LBB1_19: # %._crit_edge20
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 80
movl $_ZGVZ14initRandMatrixPfiiE2rd, %edi
movl %edx, %ebx
callq __cxa_guard_acquire
movl %ebx, %edx
testl %eax, %eax
je .LBB1_4
# %bb.2:
.Ltmp0:
movl %edx, %ebx
movl $_ZZ14initRandMatrixPfiiE2rd, %edi
callq _ZNSt13random_deviceC2Ev
.Ltmp1:
# %bb.3:
movl $_ZNSt13random_deviceD2Ev, %edi
movl $_ZZ14initRandMatrixPfiiE2rd, %esi
movl $__dso_handle, %edx
callq __cxa_atexit
movl $_ZGVZ14initRandMatrixPfiiE2rd, %edi
callq __cxa_guard_release
movl %ebx, %edx
jmp .LBB1_4
.LBB1_5:
movl $_ZGVZ14initRandMatrixPfiiE3gen, %edi
movl %edx, %ebx
callq __cxa_guard_acquire
movl %ebx, %edx
testl %eax, %eax
je .LBB1_10
# %bb.6:
.Ltmp3:
movl %edx, %ebx
movl $_ZZ14initRandMatrixPfiiE2rd, %edi
callq _ZNSt13random_device9_M_getvalEv
.Ltmp4:
# %bb.7: # %_ZNSt13random_deviceclEv.exit
movl %eax, %eax
movq %rax, _ZZ14initRandMatrixPfiiE3gen(%rip)
movl $1, %ecx
.LBB1_8: # =>This Inner Loop Header: Depth=1
movq %rax, %rdx
shrq $30, %rdx
xorl %eax, %edx
imull $1812433253, %edx, %eax # imm = 0x6C078965
addl %ecx, %eax
movq %rax, _ZZ14initRandMatrixPfiiE3gen(,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB1_8
# %bb.9: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEC2Em.exit
movq $624, _ZZ14initRandMatrixPfiiE3gen+4992(%rip) # imm = 0x270
movl $_ZGVZ14initRandMatrixPfiiE3gen, %edi
callq __cxa_guard_release
movl %ebx, %edx
jmp .LBB1_10
.LBB1_11:
movl $_ZGVZ14initRandMatrixPfiiE3dis, %edi
movl %edx, %ebx
callq __cxa_guard_acquire
movl %ebx, %edx
testl %eax, %eax
je .LBB1_13
# %bb.12:
movabsq $4294967296, %rax # imm = 0x100000000
movq %rax, _ZZ14initRandMatrixPfiiE3dis(%rip)
movl $_ZGVZ14initRandMatrixPfiiE3dis, %edi
callq __cxa_guard_release
movl %ebx, %edx
jmp .LBB1_13
.LBB1_22:
.Ltmp5:
movq %rax, %rbx
movl $_ZGVZ14initRandMatrixPfiiE3gen, %edi
jmp .LBB1_21
.LBB1_20:
.Ltmp2:
movq %rax, %rbx
movl $_ZGVZ14initRandMatrixPfiiE2rd, %edi
.LBB1_21:
callq __cxa_guard_abort
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size _Z14initRandMatrixPfii, .Lfunc_end1-_Z14initRandMatrixPfii
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp5-.Lfunc_begin0 # jumps to .Ltmp5
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end1-.Ltmp4 # Call between .Ltmp4 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt13random_deviceC2Ev,"axG",@progbits,_ZNSt13random_deviceC2Ev,comdat
.weak _ZNSt13random_deviceC2Ev # -- Begin function _ZNSt13random_deviceC2Ev
.p2align 4, 0x90
.type _ZNSt13random_deviceC2Ev,@function
_ZNSt13random_deviceC2Ev: # @_ZNSt13random_deviceC2Ev
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $40, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 24(%rsp), %r14
movq %r14, 8(%rsp)
movl $1634100580, 24(%rsp) # imm = 0x61666564
movl $1953264993, 27(%rsp) # imm = 0x746C7561
movq $7, 16(%rsp)
movb $0, 31(%rsp)
.Ltmp6:
leaq 8(%rsp), %rsi
callq _ZNSt13random_device7_M_initERKNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
.Ltmp7:
# %bb.1:
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_3
# %bb.2: # %.critedge.i.i
callq _ZdlPv
.LBB2_3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
addq $40, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB2_4:
.cfi_def_cfa_offset 64
.Ltmp8:
movq %rax, %rbx
movq 8(%rsp), %rdi
cmpq %r14, %rdi
je .LBB2_6
# %bb.5: # %.critedge.i.i6
callq _ZdlPv
.LBB2_6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit8
movq %rbx, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size _ZNSt13random_deviceC2Ev, .Lfunc_end2-_ZNSt13random_deviceC2Ev
.cfi_endproc
.section .gcc_except_table._ZNSt13random_deviceC2Ev,"aG",@progbits,_ZNSt13random_deviceC2Ev,comdat
.p2align 2, 0x0
GCC_except_table2:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp6-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp7-.Ltmp6 # Call between .Ltmp6 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin1 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Lfunc_end2-.Ltmp7 # Call between .Ltmp7 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt13random_deviceD2Ev,"axG",@progbits,_ZNSt13random_deviceD2Ev,comdat
.weak _ZNSt13random_deviceD2Ev # -- Begin function _ZNSt13random_deviceD2Ev
.p2align 4, 0x90
.type _ZNSt13random_deviceD2Ev,@function
_ZNSt13random_deviceD2Ev: # @_ZNSt13random_deviceD2Ev
.Lfunc_begin2:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception2
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
.Ltmp9:
callq _ZNSt13random_device7_M_finiEv
.Ltmp10:
# %bb.1:
popq %rax
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 16
.Ltmp11:
movq %rax, %rdi
callq __clang_call_terminate
.Lfunc_end3:
.size _ZNSt13random_deviceD2Ev, .Lfunc_end3-_ZNSt13random_deviceD2Ev
.cfi_endproc
.section .gcc_except_table._ZNSt13random_deviceD2Ev,"aG",@progbits,_ZNSt13random_deviceD2Ev,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception2:
.byte 255 # @LPStart Encoding = omit
.byte 3 # @TType Encoding = udata4
.uleb128 .Lttbase0-.Lttbaseref0
.Lttbaseref0:
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end2-.Lcst_begin2
.Lcst_begin2:
.uleb128 .Ltmp9-.Lfunc_begin2 # >> Call Site 1 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin2 # jumps to .Ltmp11
.byte 1 # On action: 1
.Lcst_end2:
.byte 1 # >> Action Record 1 <<
# Catch TypeInfo 1
.byte 0 # No further actions
.p2align 2, 0x0
# >> Catch TypeInfos <<
.long 0 # TypeInfo 1
.Lttbase0:
.p2align 2, 0x0
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $8192, %edi # imm = 0x2000
callq _Znam
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movq %rbx, %rdi
movl $16, %esi
movl $128, %edx
callq _Z14initRandMatrixPfii
movq 8(%rsp), %rdi
movl $8192, %edx # imm = 0x2000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_Z4copyPf, %edi
movl $8, %esi
movl $65536, %edx # imm = 0x10000
callq hipFuncSetAttribute
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 31(%rdi), %rdx
movl $65536, %r8d # imm = 0x10000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z4copyPf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
movq %rbx, %rdi
callq _ZdaPv
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.section .text.__clang_call_terminate,"axG",@progbits,__clang_call_terminate,comdat
.hidden __clang_call_terminate # -- Begin function __clang_call_terminate
.weak __clang_call_terminate
.p2align 4, 0x90
.type __clang_call_terminate,@function
__clang_call_terminate: # @__clang_call_terminate
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq __cxa_begin_catch
callq _ZSt9terminatev
.Lfunc_end5:
.size __clang_call_terminate, .Lfunc_end5-__clang_call_terminate
.cfi_endproc
# -- End function
.section .text._ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,"axG",@progbits,_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,comdat
.weak _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE # -- Begin function _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.p2align 4, 0x90
.type _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE,@function
_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE: # @_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r14
movslq 4(%rdx), %r15
movq %rdx, 8(%rsp) # 8-byte Spill
movslq (%rdx), %rax
subq %rax, %r15
movl $4294967294, %eax # imm = 0xFFFFFFFE
cmpq %rax, %r15
ja .LBB6_6
# %bb.1:
leal 1(%r15), %r12d
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %r12d
jbe .LBB6_5
# %bb.2:
notl %r15d
movq %rax, %rcx
movl %r15d, %eax
xorl %edx, %edx
divl %r12d
movq %rcx, %rax
cmpl %eax, %edx
jbe .LBB6_5
# %bb.3: # %.lr.ph.i.preheader
movl %edx, %ebp
.p2align 4, 0x90
.LBB6_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
imulq %r12, %rax
cmpl %eax, %ebp
ja .LBB6_4
.LBB6_5: # %_ZNSt24uniform_int_distributionIiE5_S_ndImSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEjEET1_RT0_S4_.exit
shrq $32, %rax
jmp .LBB6_11
.LBB6_6:
movl $4294967295, %eax # imm = 0xFFFFFFFF
cmpq %rax, %r15
jne .LBB6_7
# %bb.10:
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
jmp .LBB6_11
.LBB6_7: # %.preheader
movq %rdi, %r12
movabsq $-4294967296, %rbx # imm = 0xFFFFFFFF00000000
leaq 16(%rsp), %r13
.p2align 4, 0x90
.LBB6_8: # =>This Inner Loop Header: Depth=1
movq %rbx, 16(%rsp)
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
callq _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
movl %eax, %ebp
shlq $32, %rbp
movq %r14, %rdi
callq _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
addq %rbp, %rax
setb %cl
cmpq %r15, %rax
ja .LBB6_8
# %bb.9: # in Loop: Header=BB6_8 Depth=1
testb %cl, %cl
jne .LBB6_8
.LBB6_11: # %.loopexit
movq 8(%rsp), %rcx # 8-byte Reload
addl (%rcx), %eax
# kill: def $eax killed $eax killed $rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE, .Lfunc_end6-_ZNSt24uniform_int_distributionIiEclISt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEEEiRT_RKNS0_10param_typeE
.cfi_endproc
# -- End function
.section .text._ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,"axG",@progbits,_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,comdat
.weak _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv # -- Begin function _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.p2align 4, 0x90
.type _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv,@function
_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv: # @_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_startproc
# %bb.0:
cmpq $624, 4992(%rdi) # imm = 0x270
jb .LBB7_6
# %bb.1: # %.preheader.preheader
movl $2567483615, %eax # imm = 0x9908B0DF
xorl %edx, %edx
movq $-2147483648, %rcx # imm = 0x80000000
.p2align 4, 0x90
.LBB7_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rdi,%rdx,8), %rsi
andq %rcx, %rsi
movq 8(%rdi,%rdx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq 3176(%rdi,%rdx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, (%rdi,%rdx,8)
leaq 1(%rdx), %rsi
movq %rsi, %rdx
cmpq $227, %rsi
jne .LBB7_2
# %bb.3: # %.preheader.i.preheader
movl $228, %ecx
movq $-2147483648, %rdx # imm = 0x80000000
.p2align 4, 0x90
.LBB7_4: # %.preheader.i
# =>This Inner Loop Header: Depth=1
movq -8(%rdi,%rcx,8), %rsi
andq %rdx, %rsi
movq (%rdi,%rcx,8), %r8
movl %r8d, %r9d
andl $2147483646, %r9d # imm = 0x7FFFFFFE
orq %rsi, %r9
shrq %r9
xorq -1824(%rdi,%rcx,8), %r9
andl $1, %r8d
negl %r8d
andl %eax, %r8d
xorq %r9, %r8
movq %r8, -8(%rdi,%rcx,8)
incq %rcx
cmpq $624, %rcx # imm = 0x270
jne .LBB7_4
# %bb.5: # %_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv.exit
movq $-2147483648, %rcx # imm = 0x80000000
andq 4984(%rdi), %rcx
movq (%rdi), %rdx
movl %edx, %esi
andl $2147483646, %esi # imm = 0x7FFFFFFE
orq %rcx, %rsi
shrq %rsi
xorq 3168(%rdi), %rsi
andl $1, %edx
negl %edx
andl %eax, %edx
xorq %rsi, %rdx
movq %rdx, 4984(%rdi)
movq $0, 4992(%rdi)
.LBB7_6:
movq 4992(%rdi), %rax
leaq 1(%rax), %rcx
movq %rcx, 4992(%rdi)
movq (%rdi,%rax,8), %rax
movq %rax, %rcx
shrq $11, %rcx
movl %ecx, %ecx
xorq %rax, %rcx
movl %ecx, %eax
shll $7, %eax
andl $-1658038656, %eax # imm = 0x9D2C5680
xorq %rcx, %rax
movl %eax, %ecx
shll $15, %ecx
andl $-272236544, %ecx # imm = 0xEFC60000
xorq %rax, %rcx
movq %rcx, %rax
shrq $18, %rax
xorq %rcx, %rax
retq
.Lfunc_end7:
.size _ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv, .Lfunc_end7-_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EEclEv
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4copyPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4copyPf,@object # @_Z4copyPf
.section .rodata,"a",@progbits
.globl _Z4copyPf
.p2align 3, 0x0
_Z4copyPf:
.quad _Z19__device_stub__copyPf
.size _Z4copyPf, 8
.type _ZZ14initRandMatrixPfiiE2rd,@object # @_ZZ14initRandMatrixPfiiE2rd
.local _ZZ14initRandMatrixPfiiE2rd
.comm _ZZ14initRandMatrixPfiiE2rd,5000,8
.type _ZGVZ14initRandMatrixPfiiE2rd,@object # @_ZGVZ14initRandMatrixPfiiE2rd
.local _ZGVZ14initRandMatrixPfiiE2rd
.comm _ZGVZ14initRandMatrixPfiiE2rd,8,8
.hidden __dso_handle
.type _ZZ14initRandMatrixPfiiE3gen,@object # @_ZZ14initRandMatrixPfiiE3gen
.local _ZZ14initRandMatrixPfiiE3gen
.comm _ZZ14initRandMatrixPfiiE3gen,5000,8
.type _ZGVZ14initRandMatrixPfiiE3gen,@object # @_ZGVZ14initRandMatrixPfiiE3gen
.local _ZGVZ14initRandMatrixPfiiE3gen
.comm _ZGVZ14initRandMatrixPfiiE3gen,8,8
.type _ZZ14initRandMatrixPfiiE3dis,@object # @_ZZ14initRandMatrixPfiiE3dis
.local _ZZ14initRandMatrixPfiiE3dis
.comm _ZZ14initRandMatrixPfiiE3dis,8,4
.type _ZGVZ14initRandMatrixPfiiE3dis,@object # @_ZGVZ14initRandMatrixPfiiE3dis
.local _ZGVZ14initRandMatrixPfiiE3dis
.comm _ZGVZ14initRandMatrixPfiiE3dis,8,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "default"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4copyPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__copyPf
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z4copyPf
.addrsig_sym _ZZ14initRandMatrixPfiiE2rd
.addrsig_sym _ZGVZ14initRandMatrixPfiiE2rd
.addrsig_sym __dso_handle
.addrsig_sym _ZZ14initRandMatrixPfiiE3gen
.addrsig_sym _ZGVZ14initRandMatrixPfiiE3gen
.addrsig_sym _ZZ14initRandMatrixPfiiE3dis
.addrsig_sym _ZGVZ14initRandMatrixPfiiE3dis
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4copyPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ SHF.L.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007819 */
/* 0x001fc800000006ff */
/*0040*/ LOP3.LUT R0, R0, 0x1f0, RZ, 0xc0, !PT ; /* 0x000001f000007812 */
/* 0x000fc800078ec0ff */
/*0050*/ IADD3 R2, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000027a10 */
/* 0x000fca0007f1e0ff */
/*0060*/ IMAD.X R3, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff037624 */
/* 0x000fca00000e06ff */
/*0070*/ LDG.E.128.CONSTANT R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ea8000c1e9d00 */
/*0080*/ LDG.E.128.CONSTANT R4, [R2.64+0x800] ; /* 0x0008000402047981 */
/* 0x000ee8000c1e9d00 */
/*0090*/ LDG.E.128.CONSTANT R8, [R2.64+0xa00] ; /* 0x000a000402087981 */
/* 0x000f28000c1e9d00 */
/*00a0*/ LDG.E.128.CONSTANT R12, [R2.64+0xc00] ; /* 0x000c0004020c7981 */
/* 0x000f68000c1e9d00 */
/*00b0*/ LDG.E.128.CONSTANT R16, [R2.64+0xe00] ; /* 0x000e000402107981 */
/* 0x000f68000c1e9d00 */
/*00c0*/ LDG.E.128.CONSTANT R20, [R2.64+0x1000] ; /* 0x0010000402147981 */
/* 0x000f68000c1e9d00 */
/*00d0*/ LDG.E.128.CONSTANT R28, [R2.64+0x200] ; /* 0x00020004021c7981 */
/* 0x000f68000c1e9d00 */
/*00e0*/ LDG.E.128.CONSTANT R32, [R2.64+0x400] ; /* 0x0004000402207981 */
/* 0x000f68000c1e9d00 */
/*00f0*/ LDG.E.128.CONSTANT R36, [R2.64+0x600] ; /* 0x0006000402247981 */
/* 0x000f68000c1e9d00 */
/*0100*/ STS.128 [R0], R24 ; /* 0x0000001800007388 */
/* 0x004fe80000000c00 */
/*0110*/ STS.128 [R0+0x800], R4 ; /* 0x0008000400007388 */
/* 0x0081e80000000c00 */
/*0120*/ STS.128 [R0+0xa00], R8 ; /* 0x000a000800007388 */
/* 0x0103e80000000c00 */
/*0130*/ STS.128 [R0+0xc00], R12 ; /* 0x000c000c00007388 */
/* 0x0205e80000000c00 */
/*0140*/ STS.128 [R0+0xe00], R16 ; /* 0x000e001000007388 */
/* 0x0007e80000000c00 */
/*0150*/ STS.128 [R0+0x1000], R20 ; /* 0x0010001400007388 */
/* 0x0009e80000000c00 */
/*0160*/ LDG.E.128.CONSTANT R4, [R2.64+0x1200] ; /* 0x0012000402047981 */
/* 0x001f68000c1e9d00 */
/*0170*/ LDG.E.128.CONSTANT R8, [R2.64+0x1400] ; /* 0x0014000402087981 */
/* 0x002f68000c1e9d00 */
/*0180*/ LDG.E.128.CONSTANT R12, [R2.64+0x1600] ; /* 0x00160004020c7981 */
/* 0x004ea8000c1e9d00 */
/*0190*/ LDG.E.128.CONSTANT R16, [R2.64+0x1800] ; /* 0x0018000402107981 */
/* 0x008ee8000c1e9d00 */
/*01a0*/ LDG.E.128.CONSTANT R20, [R2.64+0x1a00] ; /* 0x001a000402147981 */
/* 0x010f28000c1e9d00 */
/*01b0*/ LDG.E.128.CONSTANT R24, [R2.64+0x1c00] ; /* 0x001c000402187981 */
/* 0x000f28000c1e9d00 */
/*01c0*/ STS.128 [R0+0x200], R28 ; /* 0x0002001c00007388 */
/* 0x000fe80000000c00 */
/*01d0*/ STS.128 [R0+0x400], R32 ; /* 0x0004002000007388 */
/* 0x000fe80000000c00 */
/*01e0*/ STS.128 [R0+0x600], R36 ; /* 0x0006002400007388 */
/* 0x000fe80000000c00 */
/*01f0*/ STS.128 [R0+0x1200], R4 ; /* 0x0012000400007388 */
/* 0x020fe80000000c00 */
/*0200*/ STS.128 [R0+0x1400], R8 ; /* 0x0014000800007388 */
/* 0x000fe80000000c00 */
/*0210*/ STS.128 [R0+0x1600], R12 ; /* 0x0016000c00007388 */
/* 0x004fe80000000c00 */
/*0220*/ STS.128 [R0+0x1800], R16 ; /* 0x0018001000007388 */
/* 0x008fe80000000c00 */
/*0230*/ STS.128 [R0+0x1a00], R20 ; /* 0x001a001400007388 */
/* 0x010fe80000000c00 */
/*0240*/ STS.128 [R0+0x1c00], R24 ; /* 0x001c001800007388 */
/* 0x000fe20000000c00 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4copyPf
.globl _Z4copyPf
.p2align 8
.type _Z4copyPf,@function
_Z4copyPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_and_b32_e32 v0, 31, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v60, 4, v0
s_waitcnt lgkmcnt(0)
s_clause 0x3
global_load_b128 v[0:3], v60, s[0:1]
global_load_b128 v[4:7], v60, s[0:1] offset:512
global_load_b128 v[8:11], v60, s[0:1] offset:1024
global_load_b128 v[12:15], v60, s[0:1] offset:1536
v_add_co_u32 v16, s2, s0, v60
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v17, null, s1, 0, s2
v_add_co_u32 v56, vcc_lo, 0x1000, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v57, vcc_lo, 0, v17, vcc_lo
s_clause 0xa
global_load_b128 v[16:19], v60, s[0:1] offset:2048
global_load_b128 v[20:23], v60, s[0:1] offset:2560
global_load_b128 v[24:27], v60, s[0:1] offset:3072
global_load_b128 v[28:31], v60, s[0:1] offset:3584
global_load_b128 v[32:35], v[56:57], off
global_load_b128 v[36:39], v[56:57], off offset:512
global_load_b128 v[40:43], v[56:57], off offset:1024
global_load_b128 v[44:47], v[56:57], off offset:1536
global_load_b128 v[48:51], v[56:57], off offset:2048
global_load_b128 v[52:55], v[56:57], off offset:2560
global_load_b128 v[56:59], v[56:57], off offset:3072
v_add_nc_u32_e32 v60, 0, v60
s_waitcnt vmcnt(14)
ds_store_b128 v60, v[0:3]
s_waitcnt vmcnt(13)
ds_store_b128 v60, v[4:7] offset:512
s_waitcnt vmcnt(12)
ds_store_b128 v60, v[8:11] offset:1024
s_waitcnt vmcnt(11)
ds_store_b128 v60, v[12:15] offset:1536
s_waitcnt vmcnt(10)
ds_store_b128 v60, v[16:19] offset:2048
s_waitcnt vmcnt(9)
ds_store_b128 v60, v[20:23] offset:2560
s_waitcnt vmcnt(8)
ds_store_b128 v60, v[24:27] offset:3072
s_waitcnt vmcnt(7)
ds_store_b128 v60, v[28:31] offset:3584
s_waitcnt vmcnt(6)
ds_store_b128 v60, v[32:35] offset:4096
s_waitcnt vmcnt(5)
ds_store_b128 v60, v[36:39] offset:4608
s_waitcnt vmcnt(4)
ds_store_b128 v60, v[40:43] offset:5120
s_waitcnt vmcnt(3)
ds_store_b128 v60, v[44:47] offset:5632
s_waitcnt vmcnt(2)
ds_store_b128 v60, v[48:51] offset:6144
s_waitcnt vmcnt(1)
ds_store_b128 v60, v[52:55] offset:6656
s_waitcnt vmcnt(0)
ds_store_b128 v60, v[56:59] offset:7168
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4copyPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 61
.amdhsa_next_free_sgpr 3
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4copyPf, .Lfunc_end0-_Z4copyPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4copyPf
.private_segment_fixed_size: 0
.sgpr_count: 5
.sgpr_spill_count: 0
.symbol: _Z4copyPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 61
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cuda_runtime.h>
using namespace std;
__global__ void transp(int *A, int n){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n*n){
int j = idx % n;
int i = idx / n;
int tmp = A[i * n + j];
A[i * n + j] = A[j * n + i];
A[j * n + i] = tmp;
}
}
bool check(int *c, int *t, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << c[i * n + j] << " " << t[j * n + i] << endl;
if (c[i * n + j] != t[j * n + i]) return false;
}
}
return true;
}
int main(int argc, char **argv){
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int n = atoi(argv[1]);
int *h_a = (int *) malloc(n * n * sizeof(int));
int *h_b = (int *) malloc(n * n * sizeof(int));
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
h_a[i * n + j] = i * n + j + 1;
h_b[i * n + j] = i * n + j + 1;
//cout << h_a[i * n + j] << " ";
}
//cout << endl;
}
cout << endl;
int *d_a;
cudaEventRecord(start);
cudaMalloc(&d_a, n * n * sizeof(int));
cudaMemcpy(d_a, h_a, n * n * sizeof(int), cudaMemcpyHostToDevice);
int blockSize, gridSize;
blockSize = 1024;
gridSize = (n - 1) / 1024 + 1;
transp<<<gridSize, blockSize>>>(d_a, n);
cudaDeviceSynchronize();
cudaMemcpy(h_a, d_a, n * n * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
cudaFree(d_a);
if (check(h_a, h_b, n) == true) cout << "OK\n";
else cout << "Incorrect";
/*
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << h_a[i * n + j] << " ";
}
cout << endl;
}
*/
return 0;
} | code for sm_80
Function : _Z6transpPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x168] ; /* 0x00005a0000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0130*/ LOP3.LUT R2, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000027a12 */
/* 0x000fc800078e3cff */
/*0140*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0150*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0a03 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0190*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01a0*/ @!P2 IADD3 R4, R4, -R5.reuse, RZ ; /* 0x800000050404a210 */
/* 0x080fe40007ffe0ff */
/*01b0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f06070 */
/*01d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fd60003f45270 */
/*01e0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01f0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0200*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff03aa12 */
/* 0x000fc800078e33ff */
/*0210*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0220*/ IMAD R0, R5, c[0x0][0x168], R0 ; /* 0x00005a0005007a24 */
/* 0x000fc800078e0200 */
/*0230*/ IMAD R4, R0, c[0x0][0x168], R3 ; /* 0x00005a0000047a24 */
/* 0x000fe400078e0203 */
/*0240*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fe400078e0200 */
/*0250*/ IMAD.WIDE R4, R4, R2, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0202 */
/*0260*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0270*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1900 */
/*0290*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe8000c101904 */
/*02a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x008fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cuda_runtime.h>
using namespace std;
__global__ void transp(int *A, int n){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n*n){
int j = idx % n;
int i = idx / n;
int tmp = A[i * n + j];
A[i * n + j] = A[j * n + i];
A[j * n + i] = tmp;
}
}
bool check(int *c, int *t, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << c[i * n + j] << " " << t[j * n + i] << endl;
if (c[i * n + j] != t[j * n + i]) return false;
}
}
return true;
}
int main(int argc, char **argv){
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int n = atoi(argv[1]);
int *h_a = (int *) malloc(n * n * sizeof(int));
int *h_b = (int *) malloc(n * n * sizeof(int));
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
h_a[i * n + j] = i * n + j + 1;
h_b[i * n + j] = i * n + j + 1;
//cout << h_a[i * n + j] << " ";
}
//cout << endl;
}
cout << endl;
int *d_a;
cudaEventRecord(start);
cudaMalloc(&d_a, n * n * sizeof(int));
cudaMemcpy(d_a, h_a, n * n * sizeof(int), cudaMemcpyHostToDevice);
int blockSize, gridSize;
blockSize = 1024;
gridSize = (n - 1) / 1024 + 1;
transp<<<gridSize, blockSize>>>(d_a, n);
cudaDeviceSynchronize();
cudaMemcpy(h_a, d_a, n * n * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
cudaFree(d_a);
if (check(h_a, h_b, n) == true) cout << "OK\n";
else cout << "Incorrect";
/*
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << h_a[i * n + j] << " ";
}
cout << endl;
}
*/
return 0;
} | .file "tmpxft_001967f5_00000000-6_task2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z5checkPiS_i
.type _Z5checkPiS_i, @function
_Z5checkPiS_i:
.LFB3669:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L10
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r15
movslq %edx, %rcx
leaq 0(,%rcx,4), %rdx
leaq (%rdi,%rdx), %rbx
movq %rcx, %rsi
negq %rsi
leaq 0(,%rsi,4), %rbp
movl $0, %r14d
movq %rcx, 40(%rsp)
movq %rdx, 8(%rsp)
movq %rbx, %rdx
movq %r15, 16(%rsp)
movq %r14, %r15
movq %rbp, 24(%rsp)
.L5:
movq 24(%rsp), %rax
leaq (%rdx,%rax), %rbx
movq 16(%rsp), %rax
leaq (%rax,%r15,4), %rbp
movq %r15, 32(%rsp)
movq %rdx, (%rsp)
jmp .L9
.L19:
call _ZSt16__throw_bad_castv@PLT
.L20:
movzbl 67(%r13), %esi
.L8:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl (%r15), %eax
cmpl %eax, (%r14)
jne .L11
addq $4, %rbx
movq 8(%rsp), %rax
addq %rax, %rbp
movq (%rsp), %rax
cmpq %rax, %rbx
je .L18
.L9:
movq %rbx, %r14
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $1, %edx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %r15
movl 0(%rbp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L19
cmpb $0, 56(%r13)
jne .L20
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L18:
movq 32(%rsp), %r15
movq %rax, %rdx
addq $1, %r15
movq 8(%rsp), %rax
addq %rax, %rdx
movq 40(%rsp), %rax
cmpq %rax, %r15
jne .L5
movl $1, %eax
jmp .L3
.L10:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
movl $1, %eax
ret
.L11:
.cfi_def_cfa_offset 112
.cfi_offset 3, -56
.cfi_offset 6, -48
.cfi_offset 12, -40
.cfi_offset 13, -32
.cfi_offset 14, -24
.cfi_offset 15, -16
movl $0, %eax
.L3:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z5checkPiS_i, .-_Z5checkPiS_i
.globl _Z26__device_stub__Z6transpPiiPii
.type _Z26__device_stub__Z6transpPiiPii, @function
_Z26__device_stub__Z6transpPiiPii:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6transpPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z6transpPiiPii, .-_Z26__device_stub__Z6transpPiiPii
.globl _Z6transpPii
.type _Z6transpPii, @function
_Z6transpPii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6transpPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z6transpPii, .-_Z6transpPii
.section .rodata.str1.1
.LC2:
.string "OK\n"
.LC3:
.string "Incorrect"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r13d
movl %eax, %r14d
imull %eax, %r14d
movslq %r14d, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
testl %r12d, %r12d
jle .L30
movl %r12d, %r9d
movslq %r12d, %r10
salq $2, %r10
leal 1(%r12), %ecx
movl $0, %r8d
movl $1, %edi
movl $0, %esi
.L31:
movq %r8, %rdx
movl %edi, %eax
.L32:
movl %eax, (%rbx,%rdx)
movl %eax, 0(%rbp,%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L32
addl $1, %esi
addl %r9d, %edi
addq %r10, %r8
addl %r9d, %ecx
cmpl %r13d, %esi
jne .L31
.L30:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 1022(%r12), %eax
subl $1, %r12d
cmovns %r12d, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L33:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %r13d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z5checkPiS_i
testb %al, %al
je .L34
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L35:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %r13d, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6transpPiiPii
jmp .L33
.L34:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6transpPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6transpPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cuda_runtime.h>
using namespace std;
__global__ void transp(int *A, int n){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n*n){
int j = idx % n;
int i = idx / n;
int tmp = A[i * n + j];
A[i * n + j] = A[j * n + i];
A[j * n + i] = tmp;
}
}
bool check(int *c, int *t, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << c[i * n + j] << " " << t[j * n + i] << endl;
if (c[i * n + j] != t[j * n + i]) return false;
}
}
return true;
}
int main(int argc, char **argv){
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
int n = atoi(argv[1]);
int *h_a = (int *) malloc(n * n * sizeof(int));
int *h_b = (int *) malloc(n * n * sizeof(int));
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
h_a[i * n + j] = i * n + j + 1;
h_b[i * n + j] = i * n + j + 1;
//cout << h_a[i * n + j] << " ";
}
//cout << endl;
}
cout << endl;
int *d_a;
cudaEventRecord(start);
cudaMalloc(&d_a, n * n * sizeof(int));
cudaMemcpy(d_a, h_a, n * n * sizeof(int), cudaMemcpyHostToDevice);
int blockSize, gridSize;
blockSize = 1024;
gridSize = (n - 1) / 1024 + 1;
transp<<<gridSize, blockSize>>>(d_a, n);
cudaDeviceSynchronize();
cudaMemcpy(h_a, d_a, n * n * sizeof(int), cudaMemcpyDeviceToHost);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float milliseconds = 0;
cudaEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
cudaFree(d_a);
if (check(h_a, h_b, n) == true) cout << "OK\n";
else cout << "Incorrect";
/*
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << h_a[i * n + j] << " ";
}
cout << endl;
}
*/
return 0;
} | #include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void transp(int *A, int n){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n*n){
int j = idx % n;
int i = idx / n;
int tmp = A[i * n + j];
A[i * n + j] = A[j * n + i];
A[j * n + i] = tmp;
}
}
bool check(int *c, int *t, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << c[i * n + j] << " " << t[j * n + i] << endl;
if (c[i * n + j] != t[j * n + i]) return false;
}
}
return true;
}
int main(int argc, char **argv){
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int n = atoi(argv[1]);
int *h_a = (int *) malloc(n * n * sizeof(int));
int *h_b = (int *) malloc(n * n * sizeof(int));
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
h_a[i * n + j] = i * n + j + 1;
h_b[i * n + j] = i * n + j + 1;
//cout << h_a[i * n + j] << " ";
}
//cout << endl;
}
cout << endl;
int *d_a;
hipEventRecord(start);
hipMalloc(&d_a, n * n * sizeof(int));
hipMemcpy(d_a, h_a, n * n * sizeof(int), hipMemcpyHostToDevice);
int blockSize, gridSize;
blockSize = 1024;
gridSize = (n - 1) / 1024 + 1;
transp<<<gridSize, blockSize>>>(d_a, n);
hipDeviceSynchronize();
hipMemcpy(h_a, d_a, n * n * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
hipFree(d_a);
if (check(h_a, h_b, n) == true) cout << "OK\n";
else cout << "Incorrect";
/*
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << h_a[i * n + j] << " ";
}
cout << endl;
}
*/
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void transp(int *A, int n){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n*n){
int j = idx % n;
int i = idx / n;
int tmp = A[i * n + j];
A[i * n + j] = A[j * n + i];
A[j * n + i] = tmp;
}
}
bool check(int *c, int *t, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << c[i * n + j] << " " << t[j * n + i] << endl;
if (c[i * n + j] != t[j * n + i]) return false;
}
}
return true;
}
int main(int argc, char **argv){
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int n = atoi(argv[1]);
int *h_a = (int *) malloc(n * n * sizeof(int));
int *h_b = (int *) malloc(n * n * sizeof(int));
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
h_a[i * n + j] = i * n + j + 1;
h_b[i * n + j] = i * n + j + 1;
//cout << h_a[i * n + j] << " ";
}
//cout << endl;
}
cout << endl;
int *d_a;
hipEventRecord(start);
hipMalloc(&d_a, n * n * sizeof(int));
hipMemcpy(d_a, h_a, n * n * sizeof(int), hipMemcpyHostToDevice);
int blockSize, gridSize;
blockSize = 1024;
gridSize = (n - 1) / 1024 + 1;
transp<<<gridSize, blockSize>>>(d_a, n);
hipDeviceSynchronize();
hipMemcpy(h_a, d_a, n * n * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
hipFree(d_a);
if (check(h_a, h_b, n) == true) cout << "OK\n";
else cout << "Incorrect";
/*
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << h_a[i * n + j] << " ";
}
cout << endl;
}
*/
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6transpPii
.globl _Z6transpPii
.p2align 8
.type _Z6transpPii,@function
_Z6transpPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_load_b64 s[0:1], s[0:1], 0x0
s_xor_b32 s4, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s4
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s2
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b32 v[0:1], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6transpPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6transpPii, .Lfunc_end0-_Z6transpPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6transpPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6transpPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void transp(int *A, int n){
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < n*n){
int j = idx % n;
int i = idx / n;
int tmp = A[i * n + j];
A[i * n + j] = A[j * n + i];
A[j * n + i] = tmp;
}
}
bool check(int *c, int *t, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << c[i * n + j] << " " << t[j * n + i] << endl;
if (c[i * n + j] != t[j * n + i]) return false;
}
}
return true;
}
int main(int argc, char **argv){
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
int n = atoi(argv[1]);
int *h_a = (int *) malloc(n * n * sizeof(int));
int *h_b = (int *) malloc(n * n * sizeof(int));
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
h_a[i * n + j] = i * n + j + 1;
h_b[i * n + j] = i * n + j + 1;
//cout << h_a[i * n + j] << " ";
}
//cout << endl;
}
cout << endl;
int *d_a;
hipEventRecord(start);
hipMalloc(&d_a, n * n * sizeof(int));
hipMemcpy(d_a, h_a, n * n * sizeof(int), hipMemcpyHostToDevice);
int blockSize, gridSize;
blockSize = 1024;
gridSize = (n - 1) / 1024 + 1;
transp<<<gridSize, blockSize>>>(d_a, n);
hipDeviceSynchronize();
hipMemcpy(h_a, d_a, n * n * sizeof(int), hipMemcpyDeviceToHost);
hipEventRecord(stop);
hipEventSynchronize(stop);
float milliseconds = 0;
hipEventElapsedTime(&milliseconds, start, stop);
cout << milliseconds << endl;
hipFree(d_a);
if (check(h_a, h_b, n) == true) cout << "OK\n";
else cout << "Incorrect";
/*
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
cout << h_a[i * n + j] << " ";
}
cout << endl;
}
*/
return 0;
} | .text
.file "task2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__transpPii # -- Begin function _Z21__device_stub__transpPii
.p2align 4, 0x90
.type _Z21__device_stub__transpPii,@function
_Z21__device_stub__transpPii: # @_Z21__device_stub__transpPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6transpPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__transpPii, .Lfunc_end0-_Z21__device_stub__transpPii
.cfi_endproc
# -- End function
.globl _Z5checkPiS_i # -- Begin function _Z5checkPiS_i
.p2align 4, 0x90
.type _Z5checkPiS_i,@function
_Z5checkPiS_i: # @_Z5checkPiS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 24(%rsp) # 8-byte Spill
testl %edx, %edx
setle 15(%rsp) # 1-byte Folded Spill
jle .LBB1_11
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movl %edx, %r12d
leaq (,%r12,4), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movq %r12, %rax
negq %rax
movq %rax, 48(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
testb $1, %bpl
jne .LBB1_11
.LBB1_10: # %.critedge
# in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %rcx # 8-byte Reload
incq %rcx
cmpq %r12, %rcx
setae 15(%rsp) # 1-byte Folded Spill
addq 32(%rsp), %r14 # 8-byte Folded Reload
addq $4, 24(%rsp) # 8-byte Folded Spill
movq %rcx, %rax
movq %rcx, 16(%rsp) # 8-byte Spill
cmpq %r12, %rcx
je .LBB1_11
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movb $1, %bpl
movq 24(%rsp), %rbx # 8-byte Reload
movl $1, %r13d
movq %r14, 40(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl -4(%r14,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_12
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_4 Depth=2
cmpb $0, 56(%r15)
je .LBB1_7
# %bb.6: # in Loop: Header=BB1_4 Depth=2
movzbl 67(%r15), %ecx
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_4 Depth=2
movq %r15, %rdi
movq %r12, %r14
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
movq %r14, %r12
movq 40(%rsp), %r14 # 8-byte Reload
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_4 Depth=2
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl -4(%r14,%r13,4), %eax
cmpl (%rbx), %eax
jne .LBB1_9
# %bb.3: # in Loop: Header=BB1_4 Depth=2
cmpq %r12, %r13
setb %bpl
addq 32(%rsp), %rbx # 8-byte Folded Reload
movq 48(%rsp), %rax # 8-byte Reload
addq %r13, %rax
incq %rax
incq %r13
cmpq $1, %rax
jne .LBB1_4
jmp .LBB1_10
.LBB1_11: # %._crit_edge
movzbl 15(%rsp), %eax # 1-byte Folded Reload
andb $1, %al
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z5checkPiS_i, .Lfunc_end1-_Z5checkPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 8(%rbx), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %ebx, %r12d
imull %r12d, %r12d
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testl %ebx, %ebx
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %eax
movl $1, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r13d, %edi
leaq (%r15,%rdi,4), %rsi
leaq (%r14,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%r8), %r9d
movl %r9d, (%rdi,%r8,4)
movl %r9d, (%rsi,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addl %ebx, %r13d
addq %rbx, %rcx
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge54
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB2_19
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB2_8
# %bb.7:
movzbl 67(%r13), %eax
jmp .LBB2_9
.LBB2_8:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal -1(%rbx), %eax
leal 1022(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movl %ebx, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6transpPii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_19
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
cmpb $0, 56(%r12)
je .LBB2_14
# %bb.13:
movzbl 67(%r12), %ecx
jmp .LBB2_15
.LBB2_14:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
movq %r15, %rsi
movl %ebx, %edx
callq _Z5checkPiS_i
movl $_ZSt4cout, %edi
testb %al, %al
je .LBB2_17
# %bb.16:
movl $.L.str.1, %esi
movl $3, %edx
jmp .LBB2_18
.LBB2_17:
movl $.L.str.2, %esi
movl $9, %edx
.LBB2_18:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_19:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6transpPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6transpPii,@object # @_Z6transpPii
.section .rodata,"a",@progbits
.globl _Z6transpPii
.p2align 3, 0x0
_Z6transpPii:
.quad _Z21__device_stub__transpPii
.size _Z6transpPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "OK\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Incorrect"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6transpPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__transpPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6transpPii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6transpPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IABS R5, c[0x0][0x168] ; /* 0x00005a0000057a13 */
/* 0x000fe20000000000 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ I2F.RP R4, R5 ; /* 0x0000000500047306 */
/* 0x000e300000209400 */
/*00b0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00e0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00f0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*0100*/ IMAD R7, R6, R5, RZ ; /* 0x0000000506077224 */
/* 0x000fe200078e02ff */
/*0110*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fc80000000000 */
/*0120*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fe200078e0002 */
/*0130*/ LOP3.LUT R2, R0, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0000027a12 */
/* 0x000fc800078e3cff */
/*0140*/ ISETP.GE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f26270 */
/*0150*/ IMAD.HI.U32 R3, R3, R6, RZ ; /* 0x0000000603037227 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0a03 */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD R4, R5, R4, R6 ; /* 0x0000000405047224 */
/* 0x000fca00078e0206 */
/*0190*/ ISETP.GT.U32.AND P2, PT, R5, R4, PT ; /* 0x000000040500720c */
/* 0x000fda0003f44070 */
/*01a0*/ @!P2 IADD3 R4, R4, -R5.reuse, RZ ; /* 0x800000050404a210 */
/* 0x080fe40007ffe0ff */
/*01b0*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f06070 */
/*01d0*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fd60003f45270 */
/*01e0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01f0*/ @!P1 IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff039224 */
/* 0x000fe200078e0a03 */
/*0200*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff03aa12 */
/* 0x000fc800078e33ff */
/*0210*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*0220*/ IMAD R0, R5, c[0x0][0x168], R0 ; /* 0x00005a0005007a24 */
/* 0x000fc800078e0200 */
/*0230*/ IMAD R4, R0, c[0x0][0x168], R3 ; /* 0x00005a0000047a24 */
/* 0x000fe400078e0203 */
/*0240*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fe400078e0200 */
/*0250*/ IMAD.WIDE R4, R4, R2, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0202 */
/*0260*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0202 */
/*0270*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee8000c1e1900 */
/*0290*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x004fe8000c101904 */
/*02a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x008fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6transpPii
.globl _Z6transpPii
.p2align 8
.type _Z6transpPii,@function
_Z6transpPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mul_i32 s3, s2, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s3, s2, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s4, s2, s3
s_load_b64 s[0:1], s[0:1], 0x0
s_xor_b32 s4, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s5, 0, s4
v_xor_b32_e32 v4, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s5, v0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s4
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s4, v2
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s4, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s2
v_sub_nc_u32_e32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x1
global_load_b32 v4, v[2:3], off
global_load_b32 v5, v[0:1], off
s_waitcnt vmcnt(1)
global_store_b32 v[0:1], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v5, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6transpPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6transpPii, .Lfunc_end0-_Z6transpPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6transpPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6transpPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001967f5_00000000-6_task2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z5checkPiS_i
.type _Z5checkPiS_i, @function
_Z5checkPiS_i:
.LFB3669:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L10
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %r15
movslq %edx, %rcx
leaq 0(,%rcx,4), %rdx
leaq (%rdi,%rdx), %rbx
movq %rcx, %rsi
negq %rsi
leaq 0(,%rsi,4), %rbp
movl $0, %r14d
movq %rcx, 40(%rsp)
movq %rdx, 8(%rsp)
movq %rbx, %rdx
movq %r15, 16(%rsp)
movq %r14, %r15
movq %rbp, 24(%rsp)
.L5:
movq 24(%rsp), %rax
leaq (%rdx,%rax), %rbx
movq 16(%rsp), %rax
leaq (%rax,%r15,4), %rbp
movq %r15, 32(%rsp)
movq %rdx, (%rsp)
jmp .L9
.L19:
call _ZSt16__throw_bad_castv@PLT
.L20:
movzbl 67(%r13), %esi
.L8:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl (%r15), %eax
cmpl %eax, (%r14)
jne .L11
addq $4, %rbx
movq 8(%rsp), %rax
addq %rax, %rbp
movq (%rsp), %rax
cmpq %rax, %rbx
je .L18
.L9:
movq %rbx, %r14
movl (%rbx), %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movl $1, %edx
leaq .LC0(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %r15
movl 0(%rbp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L19
cmpb $0, 56(%r13)
jne .L20
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.L18:
movq 32(%rsp), %r15
movq %rax, %rdx
addq $1, %r15
movq 8(%rsp), %rax
addq %rax, %rdx
movq 40(%rsp), %rax
cmpq %rax, %r15
jne .L5
movl $1, %eax
jmp .L3
.L10:
.cfi_def_cfa_offset 8
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
movl $1, %eax
ret
.L11:
.cfi_def_cfa_offset 112
.cfi_offset 3, -56
.cfi_offset 6, -48
.cfi_offset 12, -40
.cfi_offset 13, -32
.cfi_offset 14, -24
.cfi_offset 15, -16
movl $0, %eax
.L3:
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3669:
.size _Z5checkPiS_i, .-_Z5checkPiS_i
.globl _Z26__device_stub__Z6transpPiiPii
.type _Z26__device_stub__Z6transpPiiPii, @function
_Z26__device_stub__Z6transpPiiPii:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6transpPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z26__device_stub__Z6transpPiiPii, .-_Z26__device_stub__Z6transpPiiPii
.globl _Z6transpPii
.type _Z6transpPii, @function
_Z6transpPii:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6transpPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z6transpPii, .-_Z6transpPii
.section .rodata.str1.1
.LC2:
.string "OK\n"
.LC3:
.string "Incorrect"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %r13d
movl %eax, %r14d
imull %eax, %r14d
movslq %r14d, %r14
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r14, %rdi
call malloc@PLT
movq %rax, %rbp
testl %r12d, %r12d
jle .L30
movl %r12d, %r9d
movslq %r12d, %r10
salq $2, %r10
leal 1(%r12), %ecx
movl $0, %r8d
movl $1, %edi
movl $0, %esi
.L31:
movq %r8, %rdx
movl %edi, %eax
.L32:
movl %eax, (%rbx,%rdx)
movl %eax, 0(%rbp,%rdx)
addl $1, %eax
addq $4, %rdx
cmpl %ecx, %eax
jne .L32
addl $1, %esi
addl %r9d, %edi
addq %r10, %r8
addl %r9d, %ecx
cmpl %r13d, %esi
jne .L31
.L30:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leal 1022(%r12), %eax
subl $1, %r12d
cmovns %r12d, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L33:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %r13d, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z5checkPiS_i
testb %al, %al
je .L34
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L35:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl %r13d, %esi
movq 24(%rsp), %rdi
call _Z26__device_stub__Z6transpPiiPii
jmp .L33
.L34:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z6transpPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z6transpPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "task2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__transpPii # -- Begin function _Z21__device_stub__transpPii
.p2align 4, 0x90
.type _Z21__device_stub__transpPii,@function
_Z21__device_stub__transpPii: # @_Z21__device_stub__transpPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6transpPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__transpPii, .Lfunc_end0-_Z21__device_stub__transpPii
.cfi_endproc
# -- End function
.globl _Z5checkPiS_i # -- Begin function _Z5checkPiS_i
.p2align 4, 0x90
.type _Z5checkPiS_i,@function
_Z5checkPiS_i: # @_Z5checkPiS_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $56, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 24(%rsp) # 8-byte Spill
testl %edx, %edx
setle 15(%rsp) # 1-byte Folded Spill
jle .LBB1_11
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movl %edx, %r12d
leaq (,%r12,4), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movq %r12, %rax
negq %rax
movq %rax, 48(%rsp) # 8-byte Spill
xorl %eax, %eax
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_2 Depth=1
testb $1, %bpl
jne .LBB1_11
.LBB1_10: # %.critedge
# in Loop: Header=BB1_2 Depth=1
movq 16(%rsp), %rcx # 8-byte Reload
incq %rcx
cmpq %r12, %rcx
setae 15(%rsp) # 1-byte Folded Spill
addq 32(%rsp), %r14 # 8-byte Folded Reload
addq $4, 24(%rsp) # 8-byte Folded Spill
movq %rcx, %rax
movq %rcx, 16(%rsp) # 8-byte Spill
cmpq %r12, %rcx
je .LBB1_11
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
movb $1, %bpl
movq 24(%rsp), %rbx # 8-byte Reload
movl $1, %r13d
movq %r14, 40(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl -4(%r14,%r13,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_12
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_4 Depth=2
cmpb $0, 56(%r15)
je .LBB1_7
# %bb.6: # in Loop: Header=BB1_4 Depth=2
movzbl 67(%r15), %ecx
jmp .LBB1_8
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_4 Depth=2
movq %r15, %rdi
movq %r12, %r14
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
movq %r14, %r12
movq 40(%rsp), %r14 # 8-byte Reload
.LBB1_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_4 Depth=2
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl -4(%r14,%r13,4), %eax
cmpl (%rbx), %eax
jne .LBB1_9
# %bb.3: # in Loop: Header=BB1_4 Depth=2
cmpq %r12, %r13
setb %bpl
addq 32(%rsp), %rbx # 8-byte Folded Reload
movq 48(%rsp), %rax # 8-byte Reload
addq %r13, %rax
incq %rax
incq %r13
cmpq $1, %rax
jne .LBB1_4
jmp .LBB1_10
.LBB1_11: # %._crit_edge
movzbl 15(%rsp), %eax # 1-byte Folded Reload
andb $1, %al
addq $56, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 112
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z5checkPiS_i, .Lfunc_end1-_Z5checkPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movq 8(%rbx), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl %ebx, %r12d
imull %r12d, %r12d
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testl %ebx, %ebx
jle .LBB2_5
# %bb.1: # %.preheader.lr.ph
movl %ebx, %eax
movl $1, %ecx
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
movl %r13d, %edi
leaq (%r15,%rdi,4), %rsi
leaq (%r14,%rdi,4), %rdi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
leal (%rcx,%r8), %r9d
movl %r9d, (%rdi,%r8,4)
movl %r9d, (%rsi,%r8,4)
incq %r8
cmpq %r8, %rax
jne .LBB2_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rdx
addl %ebx, %r13d
addq %rbx, %rcx
cmpq %rax, %rdx
jne .LBB2_2
.LBB2_5: # %._crit_edge54
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB2_19
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB2_8
# %bb.7:
movzbl 67(%r13), %eax
jmp .LBB2_9
.LBB2_8:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 8(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leal -1(%rbx), %eax
leal 1022(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
incl %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 8(%rsp), %rax
movq %rax, 104(%rsp)
movl %ebx, 28(%rsp)
leaq 104(%rsp), %rax
movq %rax, 32(%rsp)
leaq 28(%rsp), %rax
movq %rax, 40(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z6transpPii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movl $0, 32(%rsp)
movq 48(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 32(%rsp), %rdi
callq hipEventElapsedTime
movss 32(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB2_19
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i45
cmpb $0, 56(%r12)
je .LBB2_14
# %bb.13:
movzbl 67(%r12), %ecx
jmp .LBB2_15
.LBB2_14:
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit48
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
movq %r15, %rsi
movl %ebx, %edx
callq _Z5checkPiS_i
movl $_ZSt4cout, %edi
testb %al, %al
je .LBB2_17
# %bb.16:
movl $.L.str.1, %esi
movl $3, %edx
jmp .LBB2_18
.LBB2_17:
movl $.L.str.2, %esi
movl $9, %edx
.LBB2_18:
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_19:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6transpPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6transpPii,@object # @_Z6transpPii
.section .rodata,"a",@progbits
.globl _Z6transpPii
.p2align 3, 0x0
_Z6transpPii:
.quad _Z21__device_stub__transpPii
.size _Z6transpPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "OK\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Incorrect"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6transpPii"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__transpPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6transpPii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void test(float *A){
int i = threadIdx.x;
for(int j = 0; j < 5; j++){
A[i] = A[i+1];
}
} | code for sm_80
Function : _Z4testPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void test(float *A){
int i = threadIdx.x;
for(int j = 0; j < 5; j++){
A[i] = A[i+1];
}
} | .file "tmpxft_0006af43_00000000-6_DR-1-simpleFor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4testPfPf
.type _Z23__device_stub__Z4testPfPf, @function
_Z23__device_stub__Z4testPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z4testPfPf, .-_Z23__device_stub__Z4testPfPf
.globl _Z4testPf
.type _Z4testPf, @function
_Z4testPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4testPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4testPf, .-_Z4testPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void test(float *A){
int i = threadIdx.x;
for(int j = 0; j < 5; j++){
A[i] = A[i+1];
}
} | #include <hip/hip_runtime.h>
__global__ void test(float *A){
int i = threadIdx.x;
for(int j = 0; j < 5; j++){
A[i] = A[i+1];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void test(float *A){
int i = threadIdx.x;
for(int j = 0; j < 5; j++){
A[i] = A[i+1];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPf
.globl _Z4testPf
.p2align 8
.type _Z4testPf,@function
_Z4testPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testPf, .Lfunc_end0-_Z4testPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testPf
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z4testPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void test(float *A){
int i = threadIdx.x;
for(int j = 0; j < 5; j++){
A[i] = A[i+1];
}
} | .text
.file "DR-1-simpleFor.hip"
.globl _Z19__device_stub__testPf # -- Begin function _Z19__device_stub__testPf
.p2align 4, 0x90
.type _Z19__device_stub__testPf,@function
_Z19__device_stub__testPf: # @_Z19__device_stub__testPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4testPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__testPf, .Lfunc_end0-_Z19__device_stub__testPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testPf,@object # @_Z4testPf
.section .rodata,"a",@progbits
.globl _Z4testPf
.p2align 3, 0x0
_Z4testPf:
.quad _Z19__device_stub__testPf
.size _Z4testPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0203 */
/*0050*/ LDG.E R5, [R2.64+0x4] ; /* 0x0000040402057981 */
/* 0x000ea8000c1e1900 */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4testPf
.globl _Z4testPf
.p2align 8
.type _Z4testPf,@function
_Z4testPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1] offset:4
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4testPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4testPf, .Lfunc_end0-_Z4testPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4testPf
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z4testPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006af43_00000000-6_DR-1-simpleFor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z23__device_stub__Z4testPfPf
.type _Z23__device_stub__Z4testPfPf, @function
_Z23__device_stub__Z4testPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4testPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z23__device_stub__Z4testPfPf, .-_Z23__device_stub__Z4testPfPf
.globl _Z4testPf
.type _Z4testPf, @function
_Z4testPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z4testPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4testPf, .-_Z4testPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4testPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4testPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "DR-1-simpleFor.hip"
.globl _Z19__device_stub__testPf # -- Begin function _Z19__device_stub__testPf
.p2align 4, 0x90
.type _Z19__device_stub__testPf,@function
_Z19__device_stub__testPf: # @_Z19__device_stub__testPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z4testPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z19__device_stub__testPf, .Lfunc_end0-_Z19__device_stub__testPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4testPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4testPf,@object # @_Z4testPf
.section .rodata,"a",@progbits
.globl _Z4testPf
.p2align 3, 0x0
_Z4testPf:
.quad _Z19__device_stub__testPf
.size _Z4testPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4testPf"
.size .L__unnamed_1, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__testPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4testPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void kernel1(int m, int n, int k, double *d_A, double *d_B, double *d_C){
for(int i = 0; i < m; i++){
for(int j = 0; j < n; j++){
d_C[i*n + j] = 0.0;
}
}
//mkn
for(int i = 0; i < m; i++){
for(int s = 0; s < k; s++){
for(int j = 0; j < n; j++){
d_C[i*n + j] += d_A[i*k + s] * d_B[s*n + j]; }
}
}
}
extern "C" {
void matmult_gpu1(int m, int n, int k, double *A, double *B, double *C) {
double *d_A, *d_B, *d_C; //variable on device
int size_matrix_A = m * k * sizeof(double);
cudaMalloc((void**)&d_A, size_matrix_A); // allocate memory on GPU
int size_matrix_B = k * n * sizeof(double);
cudaMalloc((void**)&d_B, size_matrix_B);
int size_matrix_C = m * n * sizeof(double);
cudaMalloc((void**)&d_C, size_matrix_C);
//copy A and B to GPU
cudaMemcpy(d_A, A, size_matrix_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size_matrix_B, cudaMemcpyHostToDevice);
// Launch kernel using 1 thread per block and 1 block
kernel1<<<1,1>>>(m, n, k, d_A, d_B, d_C);
cudaDeviceSynchronize();
//transfer C back to CPU
cudaMemcpy(C, d_C, size_matrix_C, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C); }
} | .file "tmpxft_001a07c6_00000000-6_matmult_gpu1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_
.type _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_, @function
_Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kernel1iiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_, .-_Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_
.globl _Z7kernel1iiiPdS_S_
.type _Z7kernel1iiiPdS_S_, @function
_Z7kernel1iiiPdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7kernel1iiiPdS_S_, .-_Z7kernel1iiiPdS_S_
.globl matmult_gpu1
.type matmult_gpu1, @function
matmult_gpu1:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r13d
movl %esi, %r14d
movl %edx, %r15d
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %edi, %r12d
imull %edx, %r12d
sall $3, %r12d
movslq %r12d, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %r15d, %ebp
imull %r14d, %ebp
sall $3, %ebp
movslq %ebp, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r13d, %ebx
imull %r14d, %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movl %r15d, %edx
movl %r14d, %esi
movl %r13d, %edi
call _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size matmult_gpu1, .-matmult_gpu1
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernel1iiiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1iiiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void kernel1(int m, int n, int k, double *d_A, double *d_B, double *d_C){
for(int i = 0; i < m; i++){
for(int j = 0; j < n; j++){
d_C[i*n + j] = 0.0;
}
}
//mkn
for(int i = 0; i < m; i++){
for(int s = 0; s < k; s++){
for(int j = 0; j < n; j++){
d_C[i*n + j] += d_A[i*k + s] * d_B[s*n + j]; }
}
}
}
extern "C" {
void matmult_gpu1(int m, int n, int k, double *A, double *B, double *C) {
double *d_A, *d_B, *d_C; //variable on device
int size_matrix_A = m * k * sizeof(double);
cudaMalloc((void**)&d_A, size_matrix_A); // allocate memory on GPU
int size_matrix_B = k * n * sizeof(double);
cudaMalloc((void**)&d_B, size_matrix_B);
int size_matrix_C = m * n * sizeof(double);
cudaMalloc((void**)&d_C, size_matrix_C);
//copy A and B to GPU
cudaMemcpy(d_A, A, size_matrix_A, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, size_matrix_B, cudaMemcpyHostToDevice);
// Launch kernel using 1 thread per block and 1 block
kernel1<<<1,1>>>(m, n, k, d_A, d_B, d_C);
cudaDeviceSynchronize();
//transfer C back to CPU
cudaMemcpy(C, d_C, size_matrix_C, cudaMemcpyDeviceToHost);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C); }
} | #include <hip/hip_runtime.h>
__global__ void kernel1(int m, int n, int k, double *d_A, double *d_B, double *d_C){
for(int i = 0; i < m; i++){
for(int j = 0; j < n; j++){
d_C[i*n + j] = 0.0;
}
}
//mkn
for(int i = 0; i < m; i++){
for(int s = 0; s < k; s++){
for(int j = 0; j < n; j++){
d_C[i*n + j] += d_A[i*k + s] * d_B[s*n + j]; }
}
}
}
extern "C" {
void matmult_gpu1(int m, int n, int k, double *A, double *B, double *C) {
double *d_A, *d_B, *d_C; //variable on device
int size_matrix_A = m * k * sizeof(double);
hipMalloc((void**)&d_A, size_matrix_A); // allocate memory on GPU
int size_matrix_B = k * n * sizeof(double);
hipMalloc((void**)&d_B, size_matrix_B);
int size_matrix_C = m * n * sizeof(double);
hipMalloc((void**)&d_C, size_matrix_C);
//copy A and B to GPU
hipMemcpy(d_A, A, size_matrix_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size_matrix_B, hipMemcpyHostToDevice);
// Launch kernel using 1 thread per block and 1 block
kernel1<<<1,1>>>(m, n, k, d_A, d_B, d_C);
hipDeviceSynchronize();
//transfer C back to CPU
hipMemcpy(C, d_C, size_matrix_C, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C); }
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void kernel1(int m, int n, int k, double *d_A, double *d_B, double *d_C){
for(int i = 0; i < m; i++){
for(int j = 0; j < n; j++){
d_C[i*n + j] = 0.0;
}
}
//mkn
for(int i = 0; i < m; i++){
for(int s = 0; s < k; s++){
for(int j = 0; j < n; j++){
d_C[i*n + j] += d_A[i*k + s] * d_B[s*n + j]; }
}
}
}
extern "C" {
void matmult_gpu1(int m, int n, int k, double *A, double *B, double *C) {
double *d_A, *d_B, *d_C; //variable on device
int size_matrix_A = m * k * sizeof(double);
hipMalloc((void**)&d_A, size_matrix_A); // allocate memory on GPU
int size_matrix_B = k * n * sizeof(double);
hipMalloc((void**)&d_B, size_matrix_B);
int size_matrix_C = m * n * sizeof(double);
hipMalloc((void**)&d_C, size_matrix_C);
//copy A and B to GPU
hipMemcpy(d_A, A, size_matrix_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size_matrix_B, hipMemcpyHostToDevice);
// Launch kernel using 1 thread per block and 1 block
kernel1<<<1,1>>>(m, n, k, d_A, d_B, d_C);
hipDeviceSynchronize();
//transfer C back to CPU
hipMemcpy(C, d_C, size_matrix_C, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C); }
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7kernel1iiiPdS_S_
.globl _Z7kernel1iiiPdS_S_
.p2align 8
.type _Z7kernel1iiiPdS_S_,@function
_Z7kernel1iiiPdS_S_:
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[10:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_6
s_cmp_gt_i32 s9, 0
s_mov_b32 s5, 0
s_cselect_b32 s2, -1, 0
s_mov_b32 s4, s5
v_cndmask_b32_e64 v0, 0, 1, s2
s_mov_b32 s3, s5
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_ne_u32_e64 s2, 1, v0
v_mov_b32_e32 v0, 0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_add_i32 s3, s3, 1
s_add_i32 s4, s4, s9
s_cmp_eq_u32 s3, s8
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_2
s_lshl_b64 s[6:7], s[4:5], 3
s_mov_b32 s12, s9
s_add_u32 s6, s10, s6
s_addc_u32 s7, s11, s7
.LBB0_5:
v_mov_b32_e32 v2, v1
s_add_i32 s12, s12, -1
global_store_b64 v0, v[1:2], s[6:7]
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s12, 0
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_cmp_lt_i32 s8, 1
s_cbranch_scc1 .LBB0_15
s_clause 0x1
s_load_b32 s22, s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x10
s_mov_b32 s3, 0
s_mov_b32 s23, 0
s_mov_b32 s12, s3
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s22, 0
s_cselect_b32 s0, -1, 0
s_cmp_gt_i32 s9, 0
v_cndmask_b32_e64 v0, 0, 1, s0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, 0, 1, s0
v_cmp_ne_u32_e64 s0, 1, v0
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ne_u32_e64 s1, 1, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_add_i32 s23, s23, 1
s_add_i32 s12, s12, s9
s_cmp_eq_u32 s23, s8
s_cbranch_scc1 .LBB0_15
.LBB0_9:
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_8
s_mov_b32 s13, s3
s_mov_b32 s2, 0
s_lshl_b64 s[14:15], s[12:13], 3
s_mul_i32 s24, s23, s22
s_add_u32 s14, s10, s14
s_addc_u32 s15, s11, s15
s_mov_b32 s13, s2
s_branch .LBB0_12
.p2align 6
.LBB0_11:
s_add_i32 s13, s13, 1
s_add_i32 s2, s2, s9
s_cmp_eq_u32 s13, s22
s_cbranch_scc1 .LBB0_8
.LBB0_12:
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_11
s_lshl_b64 s[16:17], s[2:3], 3
s_mov_b32 s19, s3
s_add_u32 s16, s6, s16
s_addc_u32 s17, s7, s17
s_add_i32 s18, s13, s24
s_mov_b32 s25, s9
s_lshl_b64 s[20:21], s[18:19], 3
s_mov_b64 s[18:19], s[14:15]
s_add_u32 s20, s4, s20
s_addc_u32 s21, s5, s21
.p2align 6
.LBB0_14:
s_clause 0x2
global_load_b64 v[1:2], v0, s[20:21]
global_load_b64 v[3:4], v0, s[16:17]
global_load_b64 v[5:6], v0, s[18:19]
s_add_i32 s25, s25, -1
s_waitcnt vmcnt(0)
v_fma_f64 v[1:2], v[1:2], v[3:4], v[5:6]
global_store_b64 v0, v[1:2], s[18:19]
s_add_u32 s18, s18, 8
s_addc_u32 s19, s19, 0
s_add_u32 s16, s16, 8
s_addc_u32 s17, s17, 0
s_cmp_eq_u32 s25, 0
s_cbranch_scc0 .LBB0_14
s_branch .LBB0_11
.LBB0_15:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7kernel1iiiPdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7kernel1iiiPdS_S_, .Lfunc_end0-_Z7kernel1iiiPdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7kernel1iiiPdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z7kernel1iiiPdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void kernel1(int m, int n, int k, double *d_A, double *d_B, double *d_C){
for(int i = 0; i < m; i++){
for(int j = 0; j < n; j++){
d_C[i*n + j] = 0.0;
}
}
//mkn
for(int i = 0; i < m; i++){
for(int s = 0; s < k; s++){
for(int j = 0; j < n; j++){
d_C[i*n + j] += d_A[i*k + s] * d_B[s*n + j]; }
}
}
}
extern "C" {
void matmult_gpu1(int m, int n, int k, double *A, double *B, double *C) {
double *d_A, *d_B, *d_C; //variable on device
int size_matrix_A = m * k * sizeof(double);
hipMalloc((void**)&d_A, size_matrix_A); // allocate memory on GPU
int size_matrix_B = k * n * sizeof(double);
hipMalloc((void**)&d_B, size_matrix_B);
int size_matrix_C = m * n * sizeof(double);
hipMalloc((void**)&d_C, size_matrix_C);
//copy A and B to GPU
hipMemcpy(d_A, A, size_matrix_A, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, size_matrix_B, hipMemcpyHostToDevice);
// Launch kernel using 1 thread per block and 1 block
kernel1<<<1,1>>>(m, n, k, d_A, d_B, d_C);
hipDeviceSynchronize();
//transfer C back to CPU
hipMemcpy(C, d_C, size_matrix_C, hipMemcpyDeviceToHost);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C); }
} | .text
.file "matmult_gpu1.hip"
.globl _Z22__device_stub__kernel1iiiPdS_S_ # -- Begin function _Z22__device_stub__kernel1iiiPdS_S_
.p2align 4, 0x90
.type _Z22__device_stub__kernel1iiiPdS_S_,@function
_Z22__device_stub__kernel1iiiPdS_S_: # @_Z22__device_stub__kernel1iiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernel1iiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1iiiPdS_S_, .Lfunc_end0-_Z22__device_stub__kernel1iiiPdS_S_
.cfi_endproc
# -- End function
.globl matmult_gpu1 # -- Begin function matmult_gpu1
.p2align 4, 0x90
.type matmult_gpu1,@function
matmult_gpu1: # @matmult_gpu1
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 64(%rsp) # 8-byte Spill
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, %rbx
movl %edx, %ebp
movl %esi, %r15d
# kill: def $edi killed $edi def $rdi
movq %rdi, 48(%rsp) # 8-byte Spill
leal (,%rdi,8), %r13d
movl %r13d, %eax
imull %edx, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %r15d, %eax
imull %ebp, %eax
shll $3, %eax
movslq %eax, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
imull %r15d, %r13d
movslq %r13d, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 48(%rsp), %rsi # 8-byte Reload
movl %esi, 44(%rsp)
movl %r15d, 40(%rsp)
movl %ebp, 36(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z7kernel1iiiPdS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size matmult_gpu1, .Lfunc_end1-matmult_gpu1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1iiiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1iiiPdS_S_,@object # @_Z7kernel1iiiPdS_S_
.section .rodata,"a",@progbits
.globl _Z7kernel1iiiPdS_S_
.p2align 3, 0x0
_Z7kernel1iiiPdS_S_:
.quad _Z22__device_stub__kernel1iiiPdS_S_
.size _Z7kernel1iiiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernel1iiiPdS_S_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1iiiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1iiiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a07c6_00000000-6_matmult_gpu1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_
.type _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_, @function
_Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7kernel1iiiPdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_, .-_Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_
.globl _Z7kernel1iiiPdS_S_
.type _Z7kernel1iiiPdS_S_, @function
_Z7kernel1iiiPdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z7kernel1iiiPdS_S_, .-_Z7kernel1iiiPdS_S_
.globl matmult_gpu1
.type matmult_gpu1, @function
matmult_gpu1:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r13d
movl %esi, %r14d
movl %edx, %r15d
movq %rcx, 8(%rsp)
movq %r8, 16(%rsp)
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %edi, %r12d
imull %edx, %r12d
sall $3, %r12d
movslq %r12d, %r12
leaq 40(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %r15d, %ebp
imull %r14d, %ebp
sall $3, %ebp
movslq %ebp, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %r13d, %ebx
imull %r14d, %ebx
sall $3, %ebx
movslq %ebx, %rbx
leaq 56(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 56(%rsp), %r9
movq 48(%rsp), %r8
movq 40(%rsp), %rcx
movl %r15d, %edx
movl %r14d, %esi
movl %r13d, %edi
call _Z33__device_stub__Z7kernel1iiiPdS_S_iiiPdS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size matmult_gpu1, .-matmult_gpu1
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7kernel1iiiPdS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7kernel1iiiPdS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matmult_gpu1.hip"
.globl _Z22__device_stub__kernel1iiiPdS_S_ # -- Begin function _Z22__device_stub__kernel1iiiPdS_S_
.p2align 4, 0x90
.type _Z22__device_stub__kernel1iiiPdS_S_,@function
_Z22__device_stub__kernel1iiiPdS_S_: # @_Z22__device_stub__kernel1iiiPdS_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 88(%rsp)
movq %r8, 80(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7kernel1iiiPdS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__kernel1iiiPdS_S_, .Lfunc_end0-_Z22__device_stub__kernel1iiiPdS_S_
.cfi_endproc
# -- End function
.globl matmult_gpu1 # -- Begin function matmult_gpu1
.p2align 4, 0x90
.type matmult_gpu1,@function
matmult_gpu1: # @matmult_gpu1
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 64(%rsp) # 8-byte Spill
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, %rbx
movl %edx, %ebp
movl %esi, %r15d
# kill: def $edi killed $edi def $rdi
movq %rdi, 48(%rsp) # 8-byte Spill
leal (,%rdi,8), %r13d
movl %r13d, %eax
imull %edx, %eax
movslq %eax, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl %r15d, %eax
imull %ebp, %eax
shll $3, %eax
movslq %eax, %r12
leaq 16(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
imull %r15d, %r13d
movslq %r13d, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq 56(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq 48(%rsp), %rsi # 8-byte Reload
movl %esi, 44(%rsp)
movl %r15d, 40(%rsp)
movl %ebp, 36(%rsp)
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 136(%rsp), %rax
movq %rax, 168(%rsp)
leaq 128(%rsp), %rax
movq %rax, 176(%rsp)
leaq 120(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z7kernel1iiiPdS_S_, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movq 64(%rsp), %rdi # 8-byte Reload
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size matmult_gpu1, .Lfunc_end1-matmult_gpu1
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7kernel1iiiPdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7kernel1iiiPdS_S_,@object # @_Z7kernel1iiiPdS_S_
.section .rodata,"a",@progbits
.globl _Z7kernel1iiiPdS_S_
.p2align 3, 0x0
_Z7kernel1iiiPdS_S_:
.quad _Z22__device_stub__kernel1iiiPdS_S_
.size _Z7kernel1iiiPdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7kernel1iiiPdS_S_"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__kernel1iiiPdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7kernel1iiiPdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
using namespace std;
#define imin(a,b) (a<b?a:b)
#define BAR_INIT 0
#define BAR_ENTER 1
#define BAR_WAIT 2
#define BAR_EXIT 3
#define BAR_FINISH 4
const int N = 128;
const int threadsPerBlock = 128;
const int blocksPerGrid = 1;
/*
__global__ void dot(int *a, int *b, int *c, int *d) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
__shared__ int counter_enter;
__shared__ int counter_exit;
counter_enter = 0;
counter_exit = N;
//__syncthreads();
int gid = threadIdx.x + blockIdx.x * blockDim.x;
if (gid == 0) {
} else {
}
//atomic add 1 to counter
int r = atomicAdd(&counter_enter, 1);
for (;;) {
if (r == N)
break;
else
r = atomicAdd(&counter_enter, 0);
}
c[gid] = r;
r = atomicSub(&counter_exit, 1);
//__syncthreads();
while(r != 0) {
r = atomicSub(&counter_exit, 0);
}
d[gid] = r;
//d[gid] = counter_exit;
//printf("post_print, %d\n", gid);
// if (gid % 2 == 1)
// else
// c[gid] = 1;
// c[gid] = c[gid] + 1;
}*/
//__global__ void dot2(float *a, float *b, float*c) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
//}
//__global__ void mykernel(int *data){
// atomicAdd(data, 10);
//}
__global__ void dot(int *bar_state_array, int *bar_counter_enter_array, int *bar_counter_exit_array) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
int bar_state = bar_state_array[gid];
int bar_counter_enter = bar_counter_enter_array[gid];
int bar_counter_exit = bar_counter_exit_array[gid];
if (gid == 0) {
if (bar_state == BAR_INIT) {
bar_state = BAR_ENTER;
} else if(bar_state == BAR_ENTER) {
if (bar_counter_exit == 0) {
if (bar_counter_enter == (N-1)) {
bar_counter_enter = N;
bar_state = BAR_EXIT;
bar_counter_exit = N;
}
else {
bar_counter_enter += 1;
bar_state = BAR_WAIT;
}
}
} else if(bar_state == BAR_WAIT) {
if (bar_counter_enter == N) {
bar_state = BAR_EXIT;
}
} else if (bar_state == BAR_EXIT) {
if (bar_counter_exit == 1) {
bar_counter_enter = 0;
bar_counter_exit = 0;
bar_state = BAR_FINISH;
} else {
bar_counter_exit -= 1;
bar_state = BAR_FINISH;
}
} else if (bar_state == BAR_FINISH)
bar_state = BAR_INIT;
}
bar_state_array[gid] = bar_state;
bar_counter_enter_array[gid] = bar_counter_enter;
bar_counter_exit_array[gid] = bar_counter_exit;
}
int main(){
//int *a, *b, *partial_c, *partial_d;
int *bar_state_array, *bar_counter_enter_array, *bar_counter_exit_array;
int *dev_bar_state_array, *dev_bar_counter_enter_array, *dev_bar_counter_exit_array;
bar_state_array = new int[N];
bar_counter_enter_array = new int[N];
bar_counter_exit_array = new int[N];
cudaMalloc((void **)&dev_bar_state_array, sizeof(int) * N);
cudaMalloc((void **)&dev_bar_counter_enter_array, sizeof(int) * N);
cudaMalloc((void **)&dev_bar_counter_exit_array, sizeof(int) * N);
for (int i = 0; i < N; i++) {
bar_state_array[i] = 0;
bar_counter_enter_array[i] = 0;
bar_counter_exit_array[i] = 0;
}
bar_state_array[0] = 1;
bar_counter_enter_array[0] = N - 1;
bar_counter_exit_array[0] = 0;
cudaMemcpy(dev_bar_state_array, bar_state_array, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_bar_counter_enter_array, bar_counter_enter_array, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_bar_counter_exit_array, bar_counter_exit_array, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_bar_state_array, dev_bar_counter_enter_array, dev_bar_counter_exit_array);
cudaMemcpy(bar_state_array, dev_bar_state_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(bar_counter_enter_array, dev_bar_counter_enter_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(bar_counter_exit_array, dev_bar_counter_exit_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(dev_bar_state_array);
cudaFree(dev_bar_counter_enter_array);
cudaFree(dev_bar_counter_exit_array);
printf("%d\n", bar_state_array[0]);
printf("%d\n", bar_counter_enter_array[0]);
printf("%d\n", bar_counter_exit_array[0]);
delete[] bar_state_array;
delete[] bar_counter_enter_array;
delete[] bar_counter_exit_array;
//int *dev_a, *dev_b, *dev_partial_c, *dev_partial_d;
/*
a = new int[N];
b = new int[N];
partial_c = new int[N];
partial_d = new int[N];
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2.0f;
partial_c[i] = 200;
partial_d[i] = 250;
}
cudaMalloc((void **)&dev_a, sizeof(int) * N);
cudaMalloc((void **)&dev_b, sizeof(int) * N);
cudaMalloc((void **)&dev_partial_c, N*sizeof(int));
cudaMalloc((void **)&dev_partial_d, N*sizeof(int));
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_partial_c, dev_partial_d);
cudaMemcpy( partial_c, dev_partial_c, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( partial_d, dev_partial_d, N*sizeof(int), cudaMemcpyDeviceToHost);
#define sum_sq(x) (x*(x+1)*(2*x+1)/6)
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
cudaFree(dev_partial_d);
for(int i = 0 ; i < N; i++) {
printf("enter %d has %d\n", i, partial_c[i]);
}
for (int i = 0; i < N; i++) {
printf("exit %d, has %d\n", i, partial_d[i]);
}
delete[] a;
delete[] b;
delete[] partial_c;
*/
} | code for sm_80
Function : _Z3dotPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe200078e0207 */
/*0080*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea6000c1e1900 */
/*0090*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x040fe200078e0207 */
/*00a0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000168000c1e1900 */
/*00b0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000162000c1e1900 */
/*00c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00d0*/ BSSY B0, 0x2c0 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R13, RZ, RZ, R8 ; /* 0x000000ffff0d7224 */
/* 0x004fd600078e0008 */
/*00f0*/ @P0 BRA 0x2b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fd800078e00ff */
/*0120*/ @!P0 BRA 0x2b0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f05270 */
/*0140*/ @P0 BRA 0x1e0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x020fda0003f05270 */
/*0160*/ @P0 BRA 0x2b0 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.NE.AND P0, PT, R9.reuse, 0x7f, PT ; /* 0x0000007f0900780c */
/* 0x040fe20003f05270 */
/*0180*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3 ; /* 0x00000003ff0d7424 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ SEL R11, RZ, 0x80, P0 ; /* 0x00000080ff0b7807 */
/* 0x000fe40000000000 */
/*01b0*/ SEL R9, R9, 0x80, P0 ; /* 0x0000008009097807 */
/* 0x000fe40000000000 */
/*01c0*/ SEL R13, R13, 0x2, !P0 ; /* 0x000000020d0d7807 */
/* 0x000fe20004000000 */
/*01d0*/ BRA 0x2b0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.NE.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fda0003f05270 */
/*01f0*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, 0x3 ; /* 0x00000003ff0d8424 */
/* 0x000fe200078e00ff */
/*0200*/ @!P0 ISETP.NE.AND P1, PT, R9, 0x80, PT ; /* 0x000000800900880c */
/* 0x020fc80003f25270 */
/*0210*/ @!P0 SEL R13, R13, 0x2, !P1 ; /* 0x000000020d0d8807 */
/* 0x000fe20004800000 */
/*0220*/ @!P0 BRA 0x2b0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.NE.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fda0003f05270 */
/*0240*/ @!P0 ISETP.NE.AND P1, PT, R11.reuse, 0x1, PT ; /* 0x000000010b00880c */
/* 0x040fe20003f25270 */
/*0250*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d8424 */
/* 0x000fe200078e00ff */
/*0260*/ @P0 ISETP.NE.AND P2, PT, R8.reuse, 0x4, PT ; /* 0x000000040800080c */
/* 0x040fe40003f45270 */
/*0270*/ @!P0 IADD3 R0, R11, -0x1, RZ ; /* 0xffffffff0b008810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @P0 SEL R13, R8, RZ, P2 ; /* 0x000000ff080d0207 */
/* 0x000fe40001000000 */
/*0290*/ @!P0 SEL R11, R0, RZ, P1 ; /* 0x000000ff000b8207 */
/* 0x000fe40000800000 */
/*02a0*/ @!P0 SEL R9, R9, RZ, P1 ; /* 0x000000ff09098207 */
/* 0x000fc40000800000 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x020fe8000c101904 */
/*02e0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
using namespace std;
#define imin(a,b) (a<b?a:b)
#define BAR_INIT 0
#define BAR_ENTER 1
#define BAR_WAIT 2
#define BAR_EXIT 3
#define BAR_FINISH 4
const int N = 128;
const int threadsPerBlock = 128;
const int blocksPerGrid = 1;
/*
__global__ void dot(int *a, int *b, int *c, int *d) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
__shared__ int counter_enter;
__shared__ int counter_exit;
counter_enter = 0;
counter_exit = N;
//__syncthreads();
int gid = threadIdx.x + blockIdx.x * blockDim.x;
if (gid == 0) {
} else {
}
//atomic add 1 to counter
int r = atomicAdd(&counter_enter, 1);
for (;;) {
if (r == N)
break;
else
r = atomicAdd(&counter_enter, 0);
}
c[gid] = r;
r = atomicSub(&counter_exit, 1);
//__syncthreads();
while(r != 0) {
r = atomicSub(&counter_exit, 0);
}
d[gid] = r;
//d[gid] = counter_exit;
//printf("post_print, %d\n", gid);
// if (gid % 2 == 1)
// else
// c[gid] = 1;
// c[gid] = c[gid] + 1;
}*/
//__global__ void dot2(float *a, float *b, float*c) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
//}
//__global__ void mykernel(int *data){
// atomicAdd(data, 10);
//}
__global__ void dot(int *bar_state_array, int *bar_counter_enter_array, int *bar_counter_exit_array) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
int bar_state = bar_state_array[gid];
int bar_counter_enter = bar_counter_enter_array[gid];
int bar_counter_exit = bar_counter_exit_array[gid];
if (gid == 0) {
if (bar_state == BAR_INIT) {
bar_state = BAR_ENTER;
} else if(bar_state == BAR_ENTER) {
if (bar_counter_exit == 0) {
if (bar_counter_enter == (N-1)) {
bar_counter_enter = N;
bar_state = BAR_EXIT;
bar_counter_exit = N;
}
else {
bar_counter_enter += 1;
bar_state = BAR_WAIT;
}
}
} else if(bar_state == BAR_WAIT) {
if (bar_counter_enter == N) {
bar_state = BAR_EXIT;
}
} else if (bar_state == BAR_EXIT) {
if (bar_counter_exit == 1) {
bar_counter_enter = 0;
bar_counter_exit = 0;
bar_state = BAR_FINISH;
} else {
bar_counter_exit -= 1;
bar_state = BAR_FINISH;
}
} else if (bar_state == BAR_FINISH)
bar_state = BAR_INIT;
}
bar_state_array[gid] = bar_state;
bar_counter_enter_array[gid] = bar_counter_enter;
bar_counter_exit_array[gid] = bar_counter_exit;
}
int main(){
//int *a, *b, *partial_c, *partial_d;
int *bar_state_array, *bar_counter_enter_array, *bar_counter_exit_array;
int *dev_bar_state_array, *dev_bar_counter_enter_array, *dev_bar_counter_exit_array;
bar_state_array = new int[N];
bar_counter_enter_array = new int[N];
bar_counter_exit_array = new int[N];
cudaMalloc((void **)&dev_bar_state_array, sizeof(int) * N);
cudaMalloc((void **)&dev_bar_counter_enter_array, sizeof(int) * N);
cudaMalloc((void **)&dev_bar_counter_exit_array, sizeof(int) * N);
for (int i = 0; i < N; i++) {
bar_state_array[i] = 0;
bar_counter_enter_array[i] = 0;
bar_counter_exit_array[i] = 0;
}
bar_state_array[0] = 1;
bar_counter_enter_array[0] = N - 1;
bar_counter_exit_array[0] = 0;
cudaMemcpy(dev_bar_state_array, bar_state_array, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_bar_counter_enter_array, bar_counter_enter_array, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_bar_counter_exit_array, bar_counter_exit_array, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_bar_state_array, dev_bar_counter_enter_array, dev_bar_counter_exit_array);
cudaMemcpy(bar_state_array, dev_bar_state_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(bar_counter_enter_array, dev_bar_counter_enter_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(bar_counter_exit_array, dev_bar_counter_exit_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(dev_bar_state_array);
cudaFree(dev_bar_counter_enter_array);
cudaFree(dev_bar_counter_exit_array);
printf("%d\n", bar_state_array[0]);
printf("%d\n", bar_counter_enter_array[0]);
printf("%d\n", bar_counter_exit_array[0]);
delete[] bar_state_array;
delete[] bar_counter_enter_array;
delete[] bar_counter_exit_array;
//int *dev_a, *dev_b, *dev_partial_c, *dev_partial_d;
/*
a = new int[N];
b = new int[N];
partial_c = new int[N];
partial_d = new int[N];
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2.0f;
partial_c[i] = 200;
partial_d[i] = 250;
}
cudaMalloc((void **)&dev_a, sizeof(int) * N);
cudaMalloc((void **)&dev_b, sizeof(int) * N);
cudaMalloc((void **)&dev_partial_c, N*sizeof(int));
cudaMalloc((void **)&dev_partial_d, N*sizeof(int));
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_partial_c, dev_partial_d);
cudaMemcpy( partial_c, dev_partial_c, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( partial_d, dev_partial_d, N*sizeof(int), cudaMemcpyDeviceToHost);
#define sum_sq(x) (x*(x+1)*(2*x+1)/6)
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
cudaFree(dev_partial_d);
for(int i = 0 ; i < N; i++) {
printf("enter %d has %d\n", i, partial_c[i]);
}
for (int i = 0; i < N; i++) {
printf("exit %d, has %d\n", i, partial_d[i]);
}
delete[] a;
delete[] b;
delete[] partial_c;
*/
} | .file "tmpxft_001980d4_00000000-6_tbar.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPiS_S_PiS_S_
.type _Z26__device_stub__Z3dotPiS_S_PiS_S_, @function
_Z26__device_stub__Z3dotPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3dotPiS_S_PiS_S_, .-_Z26__device_stub__Z3dotPiS_S_PiS_S_
.globl _Z3dotPiS_S_
.type _Z3dotPiS_S_, @function
_Z3dotPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3dotPiS_S_, .-_Z3dotPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, %edi
call _Znam@PLT
movq %rax, %r12
movl $512, %edi
call _Znam@PLT
movq %rax, %rbp
movl $512, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl $0, (%r12,%rax)
movl $0, 0(%rbp,%rax)
movl $0, (%rbx,%rax)
addq $4, %rax
cmpq $512, %rax
jne .L12
movl $1, (%r12)
movl $127, 0(%rbp)
movl $0, (%rbx)
movl $1, %ecx
movl $512, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $512, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $512, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl (%r12), %edx
leaq .LC0(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3dotPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cuda.h>
using namespace std;
#define imin(a,b) (a<b?a:b)
#define BAR_INIT 0
#define BAR_ENTER 1
#define BAR_WAIT 2
#define BAR_EXIT 3
#define BAR_FINISH 4
const int N = 128;
const int threadsPerBlock = 128;
const int blocksPerGrid = 1;
/*
__global__ void dot(int *a, int *b, int *c, int *d) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
__shared__ int counter_enter;
__shared__ int counter_exit;
counter_enter = 0;
counter_exit = N;
//__syncthreads();
int gid = threadIdx.x + blockIdx.x * blockDim.x;
if (gid == 0) {
} else {
}
//atomic add 1 to counter
int r = atomicAdd(&counter_enter, 1);
for (;;) {
if (r == N)
break;
else
r = atomicAdd(&counter_enter, 0);
}
c[gid] = r;
r = atomicSub(&counter_exit, 1);
//__syncthreads();
while(r != 0) {
r = atomicSub(&counter_exit, 0);
}
d[gid] = r;
//d[gid] = counter_exit;
//printf("post_print, %d\n", gid);
// if (gid % 2 == 1)
// else
// c[gid] = 1;
// c[gid] = c[gid] + 1;
}*/
//__global__ void dot2(float *a, float *b, float*c) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
//}
//__global__ void mykernel(int *data){
// atomicAdd(data, 10);
//}
__global__ void dot(int *bar_state_array, int *bar_counter_enter_array, int *bar_counter_exit_array) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
int bar_state = bar_state_array[gid];
int bar_counter_enter = bar_counter_enter_array[gid];
int bar_counter_exit = bar_counter_exit_array[gid];
if (gid == 0) {
if (bar_state == BAR_INIT) {
bar_state = BAR_ENTER;
} else if(bar_state == BAR_ENTER) {
if (bar_counter_exit == 0) {
if (bar_counter_enter == (N-1)) {
bar_counter_enter = N;
bar_state = BAR_EXIT;
bar_counter_exit = N;
}
else {
bar_counter_enter += 1;
bar_state = BAR_WAIT;
}
}
} else if(bar_state == BAR_WAIT) {
if (bar_counter_enter == N) {
bar_state = BAR_EXIT;
}
} else if (bar_state == BAR_EXIT) {
if (bar_counter_exit == 1) {
bar_counter_enter = 0;
bar_counter_exit = 0;
bar_state = BAR_FINISH;
} else {
bar_counter_exit -= 1;
bar_state = BAR_FINISH;
}
} else if (bar_state == BAR_FINISH)
bar_state = BAR_INIT;
}
bar_state_array[gid] = bar_state;
bar_counter_enter_array[gid] = bar_counter_enter;
bar_counter_exit_array[gid] = bar_counter_exit;
}
int main(){
//int *a, *b, *partial_c, *partial_d;
int *bar_state_array, *bar_counter_enter_array, *bar_counter_exit_array;
int *dev_bar_state_array, *dev_bar_counter_enter_array, *dev_bar_counter_exit_array;
bar_state_array = new int[N];
bar_counter_enter_array = new int[N];
bar_counter_exit_array = new int[N];
cudaMalloc((void **)&dev_bar_state_array, sizeof(int) * N);
cudaMalloc((void **)&dev_bar_counter_enter_array, sizeof(int) * N);
cudaMalloc((void **)&dev_bar_counter_exit_array, sizeof(int) * N);
for (int i = 0; i < N; i++) {
bar_state_array[i] = 0;
bar_counter_enter_array[i] = 0;
bar_counter_exit_array[i] = 0;
}
bar_state_array[0] = 1;
bar_counter_enter_array[0] = N - 1;
bar_counter_exit_array[0] = 0;
cudaMemcpy(dev_bar_state_array, bar_state_array, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_bar_counter_enter_array, bar_counter_enter_array, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_bar_counter_exit_array, bar_counter_exit_array, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_bar_state_array, dev_bar_counter_enter_array, dev_bar_counter_exit_array);
cudaMemcpy(bar_state_array, dev_bar_state_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(bar_counter_enter_array, dev_bar_counter_enter_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(bar_counter_exit_array, dev_bar_counter_exit_array, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaFree(dev_bar_state_array);
cudaFree(dev_bar_counter_enter_array);
cudaFree(dev_bar_counter_exit_array);
printf("%d\n", bar_state_array[0]);
printf("%d\n", bar_counter_enter_array[0]);
printf("%d\n", bar_counter_exit_array[0]);
delete[] bar_state_array;
delete[] bar_counter_enter_array;
delete[] bar_counter_exit_array;
//int *dev_a, *dev_b, *dev_partial_c, *dev_partial_d;
/*
a = new int[N];
b = new int[N];
partial_c = new int[N];
partial_d = new int[N];
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2.0f;
partial_c[i] = 200;
partial_d[i] = 250;
}
cudaMalloc((void **)&dev_a, sizeof(int) * N);
cudaMalloc((void **)&dev_b, sizeof(int) * N);
cudaMalloc((void **)&dev_partial_c, N*sizeof(int));
cudaMalloc((void **)&dev_partial_d, N*sizeof(int));
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_partial_c, dev_partial_d);
cudaMemcpy( partial_c, dev_partial_c, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( partial_d, dev_partial_d, N*sizeof(int), cudaMemcpyDeviceToHost);
#define sum_sq(x) (x*(x+1)*(2*x+1)/6)
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
cudaFree(dev_partial_d);
for(int i = 0 ; i < N; i++) {
printf("enter %d has %d\n", i, partial_c[i]);
}
for (int i = 0; i < N; i++) {
printf("exit %d, has %d\n", i, partial_d[i]);
}
delete[] a;
delete[] b;
delete[] partial_c;
*/
} | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
#define imin(a,b) (a<b?a:b)
#define BAR_INIT 0
#define BAR_ENTER 1
#define BAR_WAIT 2
#define BAR_EXIT 3
#define BAR_FINISH 4
const int N = 128;
const int threadsPerBlock = 128;
const int blocksPerGrid = 1;
/*
__global__ void dot(int *a, int *b, int *c, int *d) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
__shared__ int counter_enter;
__shared__ int counter_exit;
counter_enter = 0;
counter_exit = N;
//__syncthreads();
int gid = threadIdx.x + blockIdx.x * blockDim.x;
if (gid == 0) {
} else {
}
//atomic add 1 to counter
int r = atomicAdd(&counter_enter, 1);
for (;;) {
if (r == N)
break;
else
r = atomicAdd(&counter_enter, 0);
}
c[gid] = r;
r = atomicSub(&counter_exit, 1);
//__syncthreads();
while(r != 0) {
r = atomicSub(&counter_exit, 0);
}
d[gid] = r;
//d[gid] = counter_exit;
//printf("post_print, %d\n", gid);
// if (gid % 2 == 1)
// else
// c[gid] = 1;
// c[gid] = c[gid] + 1;
}*/
//__global__ void dot2(float *a, float *b, float*c) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
//}
//__global__ void mykernel(int *data){
// atomicAdd(data, 10);
//}
__global__ void dot(int *bar_state_array, int *bar_counter_enter_array, int *bar_counter_exit_array) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
int bar_state = bar_state_array[gid];
int bar_counter_enter = bar_counter_enter_array[gid];
int bar_counter_exit = bar_counter_exit_array[gid];
if (gid == 0) {
if (bar_state == BAR_INIT) {
bar_state = BAR_ENTER;
} else if(bar_state == BAR_ENTER) {
if (bar_counter_exit == 0) {
if (bar_counter_enter == (N-1)) {
bar_counter_enter = N;
bar_state = BAR_EXIT;
bar_counter_exit = N;
}
else {
bar_counter_enter += 1;
bar_state = BAR_WAIT;
}
}
} else if(bar_state == BAR_WAIT) {
if (bar_counter_enter == N) {
bar_state = BAR_EXIT;
}
} else if (bar_state == BAR_EXIT) {
if (bar_counter_exit == 1) {
bar_counter_enter = 0;
bar_counter_exit = 0;
bar_state = BAR_FINISH;
} else {
bar_counter_exit -= 1;
bar_state = BAR_FINISH;
}
} else if (bar_state == BAR_FINISH)
bar_state = BAR_INIT;
}
bar_state_array[gid] = bar_state;
bar_counter_enter_array[gid] = bar_counter_enter;
bar_counter_exit_array[gid] = bar_counter_exit;
}
int main(){
//int *a, *b, *partial_c, *partial_d;
int *bar_state_array, *bar_counter_enter_array, *bar_counter_exit_array;
int *dev_bar_state_array, *dev_bar_counter_enter_array, *dev_bar_counter_exit_array;
bar_state_array = new int[N];
bar_counter_enter_array = new int[N];
bar_counter_exit_array = new int[N];
hipMalloc((void **)&dev_bar_state_array, sizeof(int) * N);
hipMalloc((void **)&dev_bar_counter_enter_array, sizeof(int) * N);
hipMalloc((void **)&dev_bar_counter_exit_array, sizeof(int) * N);
for (int i = 0; i < N; i++) {
bar_state_array[i] = 0;
bar_counter_enter_array[i] = 0;
bar_counter_exit_array[i] = 0;
}
bar_state_array[0] = 1;
bar_counter_enter_array[0] = N - 1;
bar_counter_exit_array[0] = 0;
hipMemcpy(dev_bar_state_array, bar_state_array, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_bar_counter_enter_array, bar_counter_enter_array, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_bar_counter_exit_array, bar_counter_exit_array, N*sizeof(int), hipMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_bar_state_array, dev_bar_counter_enter_array, dev_bar_counter_exit_array);
hipMemcpy(bar_state_array, dev_bar_state_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(bar_counter_enter_array, dev_bar_counter_enter_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(bar_counter_exit_array, dev_bar_counter_exit_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipFree(dev_bar_state_array);
hipFree(dev_bar_counter_enter_array);
hipFree(dev_bar_counter_exit_array);
printf("%d\n", bar_state_array[0]);
printf("%d\n", bar_counter_enter_array[0]);
printf("%d\n", bar_counter_exit_array[0]);
delete[] bar_state_array;
delete[] bar_counter_enter_array;
delete[] bar_counter_exit_array;
//int *dev_a, *dev_b, *dev_partial_c, *dev_partial_d;
/*
a = new int[N];
b = new int[N];
partial_c = new int[N];
partial_d = new int[N];
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2.0f;
partial_c[i] = 200;
partial_d[i] = 250;
}
cudaMalloc((void **)&dev_a, sizeof(int) * N);
cudaMalloc((void **)&dev_b, sizeof(int) * N);
cudaMalloc((void **)&dev_partial_c, N*sizeof(int));
cudaMalloc((void **)&dev_partial_d, N*sizeof(int));
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_partial_c, dev_partial_d);
cudaMemcpy( partial_c, dev_partial_c, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( partial_d, dev_partial_d, N*sizeof(int), cudaMemcpyDeviceToHost);
#define sum_sq(x) (x*(x+1)*(2*x+1)/6)
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
cudaFree(dev_partial_d);
for(int i = 0 ; i < N; i++) {
printf("enter %d has %d\n", i, partial_c[i]);
}
for (int i = 0; i < N; i++) {
printf("exit %d, has %d\n", i, partial_d[i]);
}
delete[] a;
delete[] b;
delete[] partial_c;
*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
#define imin(a,b) (a<b?a:b)
#define BAR_INIT 0
#define BAR_ENTER 1
#define BAR_WAIT 2
#define BAR_EXIT 3
#define BAR_FINISH 4
const int N = 128;
const int threadsPerBlock = 128;
const int blocksPerGrid = 1;
/*
__global__ void dot(int *a, int *b, int *c, int *d) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
__shared__ int counter_enter;
__shared__ int counter_exit;
counter_enter = 0;
counter_exit = N;
//__syncthreads();
int gid = threadIdx.x + blockIdx.x * blockDim.x;
if (gid == 0) {
} else {
}
//atomic add 1 to counter
int r = atomicAdd(&counter_enter, 1);
for (;;) {
if (r == N)
break;
else
r = atomicAdd(&counter_enter, 0);
}
c[gid] = r;
r = atomicSub(&counter_exit, 1);
//__syncthreads();
while(r != 0) {
r = atomicSub(&counter_exit, 0);
}
d[gid] = r;
//d[gid] = counter_exit;
//printf("post_print, %d\n", gid);
// if (gid % 2 == 1)
// else
// c[gid] = 1;
// c[gid] = c[gid] + 1;
}*/
//__global__ void dot2(float *a, float *b, float*c) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
//}
//__global__ void mykernel(int *data){
// atomicAdd(data, 10);
//}
__global__ void dot(int *bar_state_array, int *bar_counter_enter_array, int *bar_counter_exit_array) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
int bar_state = bar_state_array[gid];
int bar_counter_enter = bar_counter_enter_array[gid];
int bar_counter_exit = bar_counter_exit_array[gid];
if (gid == 0) {
if (bar_state == BAR_INIT) {
bar_state = BAR_ENTER;
} else if(bar_state == BAR_ENTER) {
if (bar_counter_exit == 0) {
if (bar_counter_enter == (N-1)) {
bar_counter_enter = N;
bar_state = BAR_EXIT;
bar_counter_exit = N;
}
else {
bar_counter_enter += 1;
bar_state = BAR_WAIT;
}
}
} else if(bar_state == BAR_WAIT) {
if (bar_counter_enter == N) {
bar_state = BAR_EXIT;
}
} else if (bar_state == BAR_EXIT) {
if (bar_counter_exit == 1) {
bar_counter_enter = 0;
bar_counter_exit = 0;
bar_state = BAR_FINISH;
} else {
bar_counter_exit -= 1;
bar_state = BAR_FINISH;
}
} else if (bar_state == BAR_FINISH)
bar_state = BAR_INIT;
}
bar_state_array[gid] = bar_state;
bar_counter_enter_array[gid] = bar_counter_enter;
bar_counter_exit_array[gid] = bar_counter_exit;
}
int main(){
//int *a, *b, *partial_c, *partial_d;
int *bar_state_array, *bar_counter_enter_array, *bar_counter_exit_array;
int *dev_bar_state_array, *dev_bar_counter_enter_array, *dev_bar_counter_exit_array;
bar_state_array = new int[N];
bar_counter_enter_array = new int[N];
bar_counter_exit_array = new int[N];
hipMalloc((void **)&dev_bar_state_array, sizeof(int) * N);
hipMalloc((void **)&dev_bar_counter_enter_array, sizeof(int) * N);
hipMalloc((void **)&dev_bar_counter_exit_array, sizeof(int) * N);
for (int i = 0; i < N; i++) {
bar_state_array[i] = 0;
bar_counter_enter_array[i] = 0;
bar_counter_exit_array[i] = 0;
}
bar_state_array[0] = 1;
bar_counter_enter_array[0] = N - 1;
bar_counter_exit_array[0] = 0;
hipMemcpy(dev_bar_state_array, bar_state_array, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_bar_counter_enter_array, bar_counter_enter_array, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_bar_counter_exit_array, bar_counter_exit_array, N*sizeof(int), hipMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_bar_state_array, dev_bar_counter_enter_array, dev_bar_counter_exit_array);
hipMemcpy(bar_state_array, dev_bar_state_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(bar_counter_enter_array, dev_bar_counter_enter_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(bar_counter_exit_array, dev_bar_counter_exit_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipFree(dev_bar_state_array);
hipFree(dev_bar_counter_enter_array);
hipFree(dev_bar_counter_exit_array);
printf("%d\n", bar_state_array[0]);
printf("%d\n", bar_counter_enter_array[0]);
printf("%d\n", bar_counter_exit_array[0]);
delete[] bar_state_array;
delete[] bar_counter_enter_array;
delete[] bar_counter_exit_array;
//int *dev_a, *dev_b, *dev_partial_c, *dev_partial_d;
/*
a = new int[N];
b = new int[N];
partial_c = new int[N];
partial_d = new int[N];
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2.0f;
partial_c[i] = 200;
partial_d[i] = 250;
}
cudaMalloc((void **)&dev_a, sizeof(int) * N);
cudaMalloc((void **)&dev_b, sizeof(int) * N);
cudaMalloc((void **)&dev_partial_c, N*sizeof(int));
cudaMalloc((void **)&dev_partial_d, N*sizeof(int));
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_partial_c, dev_partial_d);
cudaMemcpy( partial_c, dev_partial_c, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( partial_d, dev_partial_d, N*sizeof(int), cudaMemcpyDeviceToHost);
#define sum_sq(x) (x*(x+1)*(2*x+1)/6)
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
cudaFree(dev_partial_d);
for(int i = 0 ; i < N; i++) {
printf("enter %d has %d\n", i, partial_c[i]);
}
for (int i = 0; i < N; i++) {
printf("exit %d, has %d\n", i, partial_d[i]);
}
delete[] a;
delete[] b;
delete[] partial_c;
*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPiS_S_
.globl _Z3dotPiS_S_
.p2align 8
.type _Z3dotPiS_S_,@function
_Z3dotPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[9:10]
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v8, v[0:1], off
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_22
s_mov_b32 s1, 0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(2)
v_cmpx_lt_i32_e32 1, v8
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_9
s_mov_b32 s3, exec_lo
v_cmpx_lt_i32_e32 2, v8
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_6
s_mov_b32 s1, -1
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 3, v8
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 1, v7
v_add_nc_u32_e32 v9, -1, v7
s_mov_b32 s4, 4
s_xor_b32 s1, exec_lo, -1
v_cndmask_b32_e32 v10, 0, v6, vcc_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s1, s1, exec_lo
.LBB0_6:
s_or_saveexec_b32 s3, s3
v_mov_b32_e32 v11, s4
s_xor_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_8
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e32 vcc_lo, 0x80, v6
s_waitcnt vmcnt(0)
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v10, v6
v_cndmask_b32_e64 v11, 2, 3, vcc_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s1, s1, exec_lo
.LBB0_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_19
s_mov_b32 s3, exec_lo
v_cmpx_lt_i32_e32 0, v8
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_16
s_waitcnt vmcnt(1)
v_dual_mov_b32 v11, 1 :: v_dual_mov_b32 v10, v6
s_waitcnt vmcnt(0)
v_mov_b32_e32 v9, v7
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v7
s_cbranch_execz .LBB0_15
v_dual_mov_b32 v9, 0x80 :: v_dual_mov_b32 v10, 0x80
v_mov_b32_e32 v11, 3
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0x7f, v6
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v10, 1, v6
v_mov_b32_e32 v11, 2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_16:
s_or_saveexec_b32 s3, s3
s_mov_b32 s4, s1
s_xor_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_18
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_waitcnt vmcnt(1)
v_dual_mov_b32 v11, 1 :: v_dual_mov_b32 v10, v6
s_waitcnt vmcnt(0)
v_mov_b32_e32 v9, v7
s_and_not1_b32 s4, s1, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s4, s5
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s1, s1, exec_lo
s_and_b32 s3, s4, exec_lo
s_or_b32 s1, s1, s3
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_21
v_cmp_ne_u32_e32 vcc_lo, 4, v8
s_waitcnt vmcnt(0)
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v10, v6
v_cndmask_b32_e32 v11, 0, v8, vcc_lo
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v6, v10
v_mov_b32_e32 v8, v11
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(2)
global_store_b32 v[0:1], v8, off
s_waitcnt vmcnt(1)
global_store_b32 v[2:3], v6, off
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v7, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPiS_S_, .Lfunc_end0-_Z3dotPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <hip/hip_runtime.h>
using namespace std;
#define imin(a,b) (a<b?a:b)
#define BAR_INIT 0
#define BAR_ENTER 1
#define BAR_WAIT 2
#define BAR_EXIT 3
#define BAR_FINISH 4
const int N = 128;
const int threadsPerBlock = 128;
const int blocksPerGrid = 1;
/*
__global__ void dot(int *a, int *b, int *c, int *d) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
__shared__ int counter_enter;
__shared__ int counter_exit;
counter_enter = 0;
counter_exit = N;
//__syncthreads();
int gid = threadIdx.x + blockIdx.x * blockDim.x;
if (gid == 0) {
} else {
}
//atomic add 1 to counter
int r = atomicAdd(&counter_enter, 1);
for (;;) {
if (r == N)
break;
else
r = atomicAdd(&counter_enter, 0);
}
c[gid] = r;
r = atomicSub(&counter_exit, 1);
//__syncthreads();
while(r != 0) {
r = atomicSub(&counter_exit, 0);
}
d[gid] = r;
//d[gid] = counter_exit;
//printf("post_print, %d\n", gid);
// if (gid % 2 == 1)
// else
// c[gid] = 1;
// c[gid] = c[gid] + 1;
}*/
//__global__ void dot2(float *a, float *b, float*c) {
//int gid = threadIdx.x + blockIdx.x * blockDim.x;
//int i = a[gid];
//int j = b[gid];
//int k = i + j;
//}
//__global__ void mykernel(int *data){
// atomicAdd(data, 10);
//}
__global__ void dot(int *bar_state_array, int *bar_counter_enter_array, int *bar_counter_exit_array) {
int gid = threadIdx.x + blockIdx.x * blockDim.x;
int bar_state = bar_state_array[gid];
int bar_counter_enter = bar_counter_enter_array[gid];
int bar_counter_exit = bar_counter_exit_array[gid];
if (gid == 0) {
if (bar_state == BAR_INIT) {
bar_state = BAR_ENTER;
} else if(bar_state == BAR_ENTER) {
if (bar_counter_exit == 0) {
if (bar_counter_enter == (N-1)) {
bar_counter_enter = N;
bar_state = BAR_EXIT;
bar_counter_exit = N;
}
else {
bar_counter_enter += 1;
bar_state = BAR_WAIT;
}
}
} else if(bar_state == BAR_WAIT) {
if (bar_counter_enter == N) {
bar_state = BAR_EXIT;
}
} else if (bar_state == BAR_EXIT) {
if (bar_counter_exit == 1) {
bar_counter_enter = 0;
bar_counter_exit = 0;
bar_state = BAR_FINISH;
} else {
bar_counter_exit -= 1;
bar_state = BAR_FINISH;
}
} else if (bar_state == BAR_FINISH)
bar_state = BAR_INIT;
}
bar_state_array[gid] = bar_state;
bar_counter_enter_array[gid] = bar_counter_enter;
bar_counter_exit_array[gid] = bar_counter_exit;
}
int main(){
//int *a, *b, *partial_c, *partial_d;
int *bar_state_array, *bar_counter_enter_array, *bar_counter_exit_array;
int *dev_bar_state_array, *dev_bar_counter_enter_array, *dev_bar_counter_exit_array;
bar_state_array = new int[N];
bar_counter_enter_array = new int[N];
bar_counter_exit_array = new int[N];
hipMalloc((void **)&dev_bar_state_array, sizeof(int) * N);
hipMalloc((void **)&dev_bar_counter_enter_array, sizeof(int) * N);
hipMalloc((void **)&dev_bar_counter_exit_array, sizeof(int) * N);
for (int i = 0; i < N; i++) {
bar_state_array[i] = 0;
bar_counter_enter_array[i] = 0;
bar_counter_exit_array[i] = 0;
}
bar_state_array[0] = 1;
bar_counter_enter_array[0] = N - 1;
bar_counter_exit_array[0] = 0;
hipMemcpy(dev_bar_state_array, bar_state_array, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_bar_counter_enter_array, bar_counter_enter_array, N*sizeof(int), hipMemcpyHostToDevice);
hipMemcpy(dev_bar_counter_exit_array, bar_counter_exit_array, N*sizeof(int), hipMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_bar_state_array, dev_bar_counter_enter_array, dev_bar_counter_exit_array);
hipMemcpy(bar_state_array, dev_bar_state_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(bar_counter_enter_array, dev_bar_counter_enter_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(bar_counter_exit_array, dev_bar_counter_exit_array, N*sizeof(int), hipMemcpyDeviceToHost);
hipFree(dev_bar_state_array);
hipFree(dev_bar_counter_enter_array);
hipFree(dev_bar_counter_exit_array);
printf("%d\n", bar_state_array[0]);
printf("%d\n", bar_counter_enter_array[0]);
printf("%d\n", bar_counter_exit_array[0]);
delete[] bar_state_array;
delete[] bar_counter_enter_array;
delete[] bar_counter_exit_array;
//int *dev_a, *dev_b, *dev_partial_c, *dev_partial_d;
/*
a = new int[N];
b = new int[N];
partial_c = new int[N];
partial_d = new int[N];
for (int i = 0; i < N; i++) {
a[i] = i;
b[i] = i * 2.0f;
partial_c[i] = 200;
partial_d[i] = 250;
}
cudaMalloc((void **)&dev_a, sizeof(int) * N);
cudaMalloc((void **)&dev_b, sizeof(int) * N);
cudaMalloc((void **)&dev_partial_c, N*sizeof(int));
cudaMalloc((void **)&dev_partial_d, N*sizeof(int));
cudaMemcpy(dev_a, a, N*sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, N*sizeof(int), cudaMemcpyHostToDevice);
dot<<<blocksPerGrid, threadsPerBlock>>>(dev_a, dev_b, dev_partial_c, dev_partial_d);
cudaMemcpy( partial_c, dev_partial_c, N*sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy( partial_d, dev_partial_d, N*sizeof(int), cudaMemcpyDeviceToHost);
#define sum_sq(x) (x*(x+1)*(2*x+1)/6)
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_partial_c);
cudaFree(dev_partial_d);
for(int i = 0 ; i < N; i++) {
printf("enter %d has %d\n", i, partial_c[i]);
}
for (int i = 0; i < N; i++) {
printf("exit %d, has %d\n", i, partial_d[i]);
}
delete[] a;
delete[] b;
delete[] partial_c;
*/
} | .text
.file "tbar.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPiS_S_ # -- Begin function _Z18__device_stub__dotPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPiS_S_,@function
_Z18__device_stub__dotPiS_S_: # @_Z18__device_stub__dotPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPiS_S_, .Lfunc_end0-_Z18__device_stub__dotPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq _Znam
movq %rax, %rbx
movl $512, %edi # imm = 0x200
callq _Znam
movq %rax, %r14
movl $512, %edi # imm = 0x200
callq _Znam
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $512, %edx # imm = 0x200
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $512, %edx # imm = 0x200
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1, (%rbx)
movl $127, (%r14)
movl $0, (%r15)
movq 16(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%r14), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPiS_S_,@object # @_Z3dotPiS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPiS_S_
.p2align 3, 0x0
_Z3dotPiS_S_:
.quad _Z18__device_stub__dotPiS_S_
.size _Z3dotPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3dotPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe200078e0207 */
/*0080*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea6000c1e1900 */
/*0090*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x040fe200078e0207 */
/*00a0*/ LDG.E R9, [R4.64] ; /* 0x0000000404097981 */
/* 0x000168000c1e1900 */
/*00b0*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000162000c1e1900 */
/*00c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00d0*/ BSSY B0, 0x2c0 ; /* 0x000001e000007945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R13, RZ, RZ, R8 ; /* 0x000000ffff0d7224 */
/* 0x004fd600078e0008 */
/*00f0*/ @P0 BRA 0x2b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x001fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, 0x1 ; /* 0x00000001ff0d7424 */
/* 0x000fd800078e00ff */
/*0120*/ @!P0 BRA 0x2b0 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*0130*/ ISETP.NE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f05270 */
/*0140*/ @P0 BRA 0x1e0 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.NE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x020fda0003f05270 */
/*0160*/ @P0 BRA 0x2b0 ; /* 0x0000014000000947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.NE.AND P0, PT, R9.reuse, 0x7f, PT ; /* 0x0000007f0900780c */
/* 0x040fe20003f05270 */
/*0180*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3 ; /* 0x00000003ff0d7424 */
/* 0x000fe200078e00ff */
/*0190*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ SEL R11, RZ, 0x80, P0 ; /* 0x00000080ff0b7807 */
/* 0x000fe40000000000 */
/*01b0*/ SEL R9, R9, 0x80, P0 ; /* 0x0000008009097807 */
/* 0x000fe40000000000 */
/*01c0*/ SEL R13, R13, 0x2, !P0 ; /* 0x000000020d0d7807 */
/* 0x000fe20004000000 */
/*01d0*/ BRA 0x2b0 ; /* 0x000000d000007947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.NE.AND P0, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fda0003f05270 */
/*01f0*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, 0x3 ; /* 0x00000003ff0d8424 */
/* 0x000fe200078e00ff */
/*0200*/ @!P0 ISETP.NE.AND P1, PT, R9, 0x80, PT ; /* 0x000000800900880c */
/* 0x020fc80003f25270 */
/*0210*/ @!P0 SEL R13, R13, 0x2, !P1 ; /* 0x000000020d0d8807 */
/* 0x000fe20004800000 */
/*0220*/ @!P0 BRA 0x2b0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0230*/ ISETP.NE.AND P0, PT, R8, 0x3, PT ; /* 0x000000030800780c */
/* 0x000fda0003f05270 */
/*0240*/ @!P0 ISETP.NE.AND P1, PT, R11.reuse, 0x1, PT ; /* 0x000000010b00880c */
/* 0x040fe20003f25270 */
/*0250*/ @!P0 IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d8424 */
/* 0x000fe200078e00ff */
/*0260*/ @P0 ISETP.NE.AND P2, PT, R8.reuse, 0x4, PT ; /* 0x000000040800080c */
/* 0x040fe40003f45270 */
/*0270*/ @!P0 IADD3 R0, R11, -0x1, RZ ; /* 0xffffffff0b008810 */
/* 0x000fe40007ffe0ff */
/*0280*/ @P0 SEL R13, R8, RZ, P2 ; /* 0x000000ff080d0207 */
/* 0x000fe40001000000 */
/*0290*/ @!P0 SEL R11, R0, RZ, P1 ; /* 0x000000ff000b8207 */
/* 0x000fe40000800000 */
/*02a0*/ @!P0 SEL R9, R9, RZ, P1 ; /* 0x000000ff09098207 */
/* 0x000fc40000800000 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*02c0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101904 */
/*02d0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x020fe8000c101904 */
/*02e0*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPiS_S_
.globl _Z3dotPiS_S_
.p2align 8
.type _Z3dotPiS_S_,@function
_Z3dotPiS_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[9:10]
v_add_co_u32 v0, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v8, v[0:1], off
global_load_b32 v6, v[2:3], off
global_load_b32 v7, v[4:5], off
s_mov_b32 s0, exec_lo
v_cmpx_eq_u32_e32 0, v9
s_cbranch_execz .LBB0_22
s_mov_b32 s1, 0
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(2)
v_cmpx_lt_i32_e32 1, v8
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_9
s_mov_b32 s3, exec_lo
v_cmpx_lt_i32_e32 2, v8
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_6
s_mov_b32 s1, -1
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 3, v8
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 1, v7
v_add_nc_u32_e32 v9, -1, v7
s_mov_b32 s4, 4
s_xor_b32 s1, exec_lo, -1
v_cndmask_b32_e32 v10, 0, v6, vcc_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s1, s1, exec_lo
.LBB0_6:
s_or_saveexec_b32 s3, s3
v_mov_b32_e32 v11, s4
s_xor_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_8
s_waitcnt vmcnt(1)
v_cmp_eq_u32_e32 vcc_lo, 0x80, v6
s_waitcnt vmcnt(0)
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v10, v6
v_cndmask_b32_e64 v11, 2, 3, vcc_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s1, s1, exec_lo
.LBB0_9:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_19
s_mov_b32 s3, exec_lo
v_cmpx_lt_i32_e32 0, v8
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_16
s_waitcnt vmcnt(1)
v_dual_mov_b32 v11, 1 :: v_dual_mov_b32 v10, v6
s_waitcnt vmcnt(0)
v_mov_b32_e32 v9, v7
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v7
s_cbranch_execz .LBB0_15
v_dual_mov_b32 v9, 0x80 :: v_dual_mov_b32 v10, 0x80
v_mov_b32_e32 v11, 3
s_mov_b32 s5, exec_lo
v_cmpx_ne_u32_e32 0x7f, v6
v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v10, 1, v6
v_mov_b32_e32 v11, 2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_16:
s_or_saveexec_b32 s3, s3
s_mov_b32 s4, s1
s_xor_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_18
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_waitcnt vmcnt(1)
v_dual_mov_b32 v11, 1 :: v_dual_mov_b32 v10, v6
s_waitcnt vmcnt(0)
v_mov_b32_e32 v9, v7
s_and_not1_b32 s4, s1, exec_lo
s_and_b32 s5, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s4, s5
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s1, s1, exec_lo
s_and_b32 s3, s4, exec_lo
s_or_b32 s1, s1, s3
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s1
s_cbranch_execz .LBB0_21
v_cmp_ne_u32_e32 vcc_lo, 4, v8
s_waitcnt vmcnt(0)
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v10, v6
v_cndmask_b32_e32 v11, 0, v8, vcc_lo
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mov_b32 v7, v9 :: v_dual_mov_b32 v6, v10
v_mov_b32_e32 v8, v11
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(2)
global_store_b32 v[0:1], v8, off
s_waitcnt vmcnt(1)
global_store_b32 v[2:3], v6, off
s_waitcnt vmcnt(0)
global_store_b32 v[4:5], v7, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPiS_S_, .Lfunc_end0-_Z3dotPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001980d4_00000000-6_tbar.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPiS_S_PiS_S_
.type _Z26__device_stub__Z3dotPiS_S_PiS_S_, @function
_Z26__device_stub__Z3dotPiS_S_PiS_S_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z26__device_stub__Z3dotPiS_S_PiS_S_, .-_Z26__device_stub__Z3dotPiS_S_PiS_S_
.globl _Z3dotPiS_S_
.type _Z3dotPiS_S_, @function
_Z3dotPiS_S_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3dotPiS_S_, .-_Z3dotPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $512, %edi
call _Znam@PLT
movq %rax, %r12
movl $512, %edi
call _Znam@PLT
movq %rax, %rbp
movl $512, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl $0, (%r12,%rax)
movl $0, 0(%rbp,%rax)
movl $0, (%rbx,%rax)
addq $4, %rax
cmpq $512, %rax
jne .L12
movl $1, (%r12)
movl $127, 0(%rbp)
movl $0, (%rbx)
movl $1, %ecx
movl $512, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $512, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $512, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $512, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $512, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl (%r12), %edx
leaq .LC0(%rip), %r13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%rbp), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call _ZdaPv@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq %rbx, %rdi
call _ZdaPv@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3dotPiS_S_PiS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3dotPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tbar.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__dotPiS_S_ # -- Begin function _Z18__device_stub__dotPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPiS_S_,@function
_Z18__device_stub__dotPiS_S_: # @_Z18__device_stub__dotPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPiS_S_, .Lfunc_end0-_Z18__device_stub__dotPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $512, %edi # imm = 0x200
callq _Znam
movq %rax, %rbx
movl $512, %edi # imm = 0x200
callq _Znam
movq %rax, %r14
movl $512, %edi # imm = 0x200
callq _Znam
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movl $512, %edx # imm = 0x200
movq %r14, %rdi
xorl %esi, %esi
callq memset@PLT
movl $512, %edx # imm = 0x200
movq %r15, %rdi
xorl %esi, %esi
callq memset@PLT
movl $1, (%rbx)
movl $127, (%r14)
movl $0, (%r15)
movq 16(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq (%rsp), %rsi
movl $512, %edx # imm = 0x200
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl (%rbx), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%r14), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl (%r15), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq _ZdaPv
movq %r14, %rdi
callq _ZdaPv
movq %r15, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPiS_S_,@object # @_Z3dotPiS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPiS_S_
.p2align 3, 0x0
_Z3dotPiS_S_:
.quad _Z18__device_stub__dotPiS_S_
.size _Z3dotPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include"cuda_runtime.h"
#include"device_launch_parameters.h"
#include<stdio.h>
__global__ void convert(int *b, int *c, int n)
{
int tx,ty,i;
tx = threadIdx.x;
ty = threadIdx.y;
if(tx==ty)
{
c[tx*n+ty]=0;
}
else if(tx>ty)
{
int fact = 1;
for(i=1;i<b[ty*n+tx];i++)
{
fact += fact * i;
}
c[ty*n+tx]=fact;
//printf("\nx = %d, y= %d ,fact =%d",tx,ty,fact);
}
else if(ty>tx)
{
int num=b[ty*n+tx];
int r=0;
while(num>0)
{
r+=num%10;
num=num/10;
}
c[ty*n+tx]=r;
//printf("\nx = %d, y= %d ,num =%d",tx,ty,r);
}
}
int main(void)
{
int n,i,j,a[3][3],b[9],c[9];
int *d_b,*d_c, size;
printf("Enter value of n\n");
scanf("%d", &n);
printf("Enter the elements of the matrix\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
scanf("%d", &a[i][j]);
}
}
/*for(i=0;i<n*n;i++)
{
b[i]=a[i][j];
}*/
size = sizeof(int);
cudaMalloc((void **)&d_b,n*n*size);
cudaMalloc((void **)&d_c,n*n*size);
cudaMemcpy(d_b,a,n*n*size,cudaMemcpyHostToDevice);
dim3 dimgrid(1,1,1);
dim3 dimblock(n,n,1);
convert<<<dimgrid,dimblock>>>(d_b,d_c,n);
cudaMemcpy(c,d_c,n*n*size,cudaMemcpyDeviceToHost);
printf("\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t", c[i*n+j]);
}
printf("\n");
}
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z7convertPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.NE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x001fda0003f05270 */
/*0050*/ @!P0 BRA 0x8a0 ; /* 0x0000084000008947 */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0080*/ IMAD R2, R0, c[0x0][0x170], R7 ; /* 0x00005c0000027a24 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0203 */
/*00b0*/ @P0 BRA 0x1f0 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f04270 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ BSSY B0, 0x1d0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f06270 */
/*0120*/ @!P0 BRA 0x1c0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0004 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.WIDE.U32 R4, R0.reuse, -0x33333333, RZ ; /* 0xcccccccd00047825 */
/* 0x040fe200078e00ff */
/*0160*/ ISETP.GT.U32.AND P0, PT, R0, 0x9, PT ; /* 0x000000090000780c */
/* 0x000fc80003f04070 */
/*0170*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*0180*/ IMAD R0, R5, -0xa, R0 ; /* 0xfffffff605007824 */
/* 0x000fc800078e0200 */
/*0190*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x000fe400078e0207 */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0005 */
/*01b0*/ @P0 BRA 0x150 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0200*/ BSSY B2, 0x880 ; /* 0x0000067000027945 */
/* 0x000fe20003800000 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x004fda0003f06270 */
/*0230*/ @!P0 BRA 0x870 ; /* 0x0000063000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R0, R4.reuse, -0x2, RZ ; /* 0xfffffffe04007810 */
/* 0x040fe20007ffe0ff */
/*0250*/ BSSY B1, 0x800 ; /* 0x000005a000017945 */
/* 0x000fe20003800000 */
/*0260*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0280*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*02a0*/ LOP3.LUT R0, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305007812 */
/* 0x000fd600078ec0ff */
/*02b0*/ @!P0 BRA 0x7f0 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a00 */
/*02d0*/ BSSY B0, 0x740 ; /* 0x0000046000007945 */
/* 0x000fe20003800000 */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc600078e00ff */
/*02f0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f04270 */
/*0300*/ @!P0 BRA 0x730 ; /* 0x0000042000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0320*/ BSSY B3, 0x5a0 ; /* 0x0000027000037945 */
/* 0x000fe20003800000 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0340*/ @!P1 BRA 0x590 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0360*/ IADD3 R6, R4.reuse, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x040fe20007ffe0ff */
/*0370*/ IMAD R7, R4.reuse, R7, R7 ; /* 0x0000000704077224 */
/* 0x040fe200078e0207 */
/*0380*/ IADD3 R9, R4.reuse, 0x2, RZ ; /* 0x0000000204097810 */
/* 0x040fe40007ffe0ff */
/*0390*/ IADD3 R8, R4.reuse, 0x3, RZ ; /* 0x0000000304087810 */
/* 0x040fe20007ffe0ff */
/*03a0*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*03b0*/ IADD3 R7, R4, 0x4, RZ ; /* 0x0000000404077810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fe200078e0206 */
/*03e0*/ IADD3 R6, R4, 0x5, RZ ; /* 0x0000000504067810 */
/* 0x000fc40007ffe0ff */
/*03f0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0400*/ IMAD R8, R9, R8, R9 ; /* 0x0000000809087224 */
/* 0x000fe200078e0209 */
/*0410*/ IADD3 R9, R4, 0x6, RZ ; /* 0x0000000604097810 */
/* 0x000fc60007ffe0ff */
/*0420*/ IMAD R7, R8, R7, R8 ; /* 0x0000000708077224 */
/* 0x000fe200078e0208 */
/*0430*/ IADD3 R8, R4, 0x7, RZ ; /* 0x0000000704087810 */
/* 0x000fc60007ffe0ff */
/*0440*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*0450*/ IADD3 R7, R4, 0x8, RZ ; /* 0x0000000804077810 */
/* 0x000fc60007ffe0ff */
/*0460*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fe200078e0206 */
/*0470*/ IADD3 R6, R4, 0x9, RZ ; /* 0x0000000904067810 */
/* 0x000fc60007ffe0ff */
/*0480*/ IMAD R8, R9, R8, R9 ; /* 0x0000000809087224 */
/* 0x000fe200078e0209 */
/*0490*/ IADD3 R9, R4, 0xa, RZ ; /* 0x0000000a04097810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ IMAD R7, R8, R7, R8 ; /* 0x0000000708077224 */
/* 0x000fe200078e0208 */
/*04b0*/ IADD3 R8, R4, 0xb, RZ ; /* 0x0000000b04087810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*04d0*/ IADD3 R7, R4, 0xc, RZ ; /* 0x0000000c04077810 */
/* 0x000fc60007ffe0ff */
/*04e0*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fe200078e0206 */
/*04f0*/ IADD3 R6, R4, 0xd, RZ ; /* 0x0000000d04067810 */
/* 0x000fc60007ffe0ff */
/*0500*/ IMAD R8, R9, R8, R9 ; /* 0x0000000809087224 */
/* 0x000fe200078e0209 */
/*0510*/ IADD3 R9, R4, 0xe, RZ ; /* 0x0000000e04097810 */
/* 0x000fc60007ffe0ff */
/*0520*/ IMAD R7, R8, R7, R8 ; /* 0x0000000708077224 */
/* 0x000fe200078e0208 */
/*0530*/ IADD3 R8, R4.reuse, 0xf, RZ ; /* 0x0000000f04087810 */
/* 0x040fe40007ffe0ff */
/*0540*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fc800078e0207 */
/*0560*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fc800078e0206 */
/*0570*/ IMAD R7, R9, R8, R9 ; /* 0x0000000809077224 */
/* 0x000fe200078e0209 */
/*0580*/ @P1 BRA 0x360 ; /* 0xfffffdd000001947 */
/* 0x000fea000383ffff */
/*0590*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fe20003f24270 */
/*05b0*/ BSSY B3, 0x700 ; /* 0x0000014000037945 */
/* 0x000fd80003800000 */
/*05c0*/ @!P1 BRA 0x6f0 ; /* 0x0000012000009947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R6, R4.reuse, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x040fe20007ffe0ff */
/*05e0*/ IMAD R7, R7, R4, R7 ; /* 0x0000000407077224 */
/* 0x000fe200078e0207 */
/*05f0*/ IADD3 R9, R4.reuse, 0x2, RZ ; /* 0x0000000204097810 */
/* 0x040fe40007ffe0ff */
/*0600*/ IADD3 R8, R4.reuse, 0x3, RZ ; /* 0x0000000304087810 */
/* 0x040fe20007ffe0ff */
/*0610*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*0620*/ IADD3 R7, R4, 0x4, RZ ; /* 0x0000000404077810 */
/* 0x000fe40007ffe0ff */
/*0630*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0640*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fe200078e0206 */
/*0650*/ IADD3 R6, R4, 0x5, RZ ; /* 0x0000000504067810 */
/* 0x000fc40007ffe0ff */
/*0660*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0670*/ IMAD R8, R9, R8, R9 ; /* 0x0000000809087224 */
/* 0x000fe200078e0209 */
/*0680*/ IADD3 R9, R4, 0x6, RZ ; /* 0x0000000604097810 */
/* 0x000fc60007ffe0ff */
/*0690*/ IMAD R7, R8, R7, R8 ; /* 0x0000000708077224 */
/* 0x000fe200078e0208 */
/*06a0*/ IADD3 R8, R4.reuse, 0x7, RZ ; /* 0x0000000704087810 */
/* 0x040fe40007ffe0ff */
/*06b0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fc800078e0207 */
/*06d0*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fc800078e0206 */
/*06e0*/ IMAD R7, R9, R8, R9 ; /* 0x0000000809077224 */
/* 0x000fe400078e0209 */
/*06f0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0710*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0720*/ @!P0 BRA 0x7f0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0730*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD R7, R4.reuse, R7, R7 ; /* 0x0000000704077224 */
/* 0x040fe200078e0207 */
/*0760*/ IADD3 R6, R4.reuse, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x040fe40007ffe0ff */
/*0770*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0780*/ IADD3 R9, R4.reuse, 0x2, RZ ; /* 0x0000000204097810 */
/* 0x040fe20007ffe0ff */
/*0790*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*07a0*/ IADD3 R8, R4.reuse, 0x3, RZ ; /* 0x0000000304087810 */
/* 0x040fe40007ffe0ff */
/*07b0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fc800078e0206 */
/*07d0*/ IMAD R7, R9, R8, R9 ; /* 0x0000000809077224 */
/* 0x000fe400078e0209 */
/*07e0*/ @P0 BRA 0x740 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*07f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0810*/ @!P0 BRA 0x870 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0820*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0830*/ IMAD R7, R4.reuse, R7, R7 ; /* 0x0000000704077224 */
/* 0x040fe200078e0207 */
/*0840*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0860*/ @P0 BRA 0x820 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0870*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0880*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*08b0*/ IMAD R2, R7, c[0x0][0x170], R7 ; /* 0x00005c0007027a24 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*08d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include"cuda_runtime.h"
#include"device_launch_parameters.h"
#include<stdio.h>
__global__ void convert(int *b, int *c, int n)
{
int tx,ty,i;
tx = threadIdx.x;
ty = threadIdx.y;
if(tx==ty)
{
c[tx*n+ty]=0;
}
else if(tx>ty)
{
int fact = 1;
for(i=1;i<b[ty*n+tx];i++)
{
fact += fact * i;
}
c[ty*n+tx]=fact;
//printf("\nx = %d, y= %d ,fact =%d",tx,ty,fact);
}
else if(ty>tx)
{
int num=b[ty*n+tx];
int r=0;
while(num>0)
{
r+=num%10;
num=num/10;
}
c[ty*n+tx]=r;
//printf("\nx = %d, y= %d ,num =%d",tx,ty,r);
}
}
int main(void)
{
int n,i,j,a[3][3],b[9],c[9];
int *d_b,*d_c, size;
printf("Enter value of n\n");
scanf("%d", &n);
printf("Enter the elements of the matrix\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
scanf("%d", &a[i][j]);
}
}
/*for(i=0;i<n*n;i++)
{
b[i]=a[i][j];
}*/
size = sizeof(int);
cudaMalloc((void **)&d_b,n*n*size);
cudaMalloc((void **)&d_c,n*n*size);
cudaMemcpy(d_b,a,n*n*size,cudaMemcpyHostToDevice);
dim3 dimgrid(1,1,1);
dim3 dimblock(n,n,1);
convert<<<dimgrid,dimblock>>>(d_b,d_c,n);
cudaMemcpy(c,d_c,n*n*size,cudaMemcpyDeviceToHost);
printf("\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t", c[i*n+j]);
}
printf("\n");
}
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_00105fcf_00000000-6_w8p3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7convertPiS_iPiS_i
.type _Z29__device_stub__Z7convertPiS_iPiS_i, @function
_Z29__device_stub__Z7convertPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7convertPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7convertPiS_iPiS_i, .-_Z29__device_stub__Z7convertPiS_iPiS_i
.globl _Z7convertPiS_i
.type _Z7convertPiS_i, @function
_Z7convertPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7convertPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7convertPiS_i, .-_Z7convertPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value of n\n"
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Enter the elements of the matrix\n"
.section .rodata.str1.1
.LC3:
.string "\n"
.LC4:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $144, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jle .L12
leaq 48(%rsp), %r14
movl $0, %r13d
leaq .LC1(%rip), %r12
jmp .L13
.L14:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 4(%rsp)
jg .L14
.L15:
movl 4(%rsp), %eax
addq $1, %r13
addq $12, %r14
cmpl %r13d, %eax
jle .L12
.L13:
movq %r14, %rbp
movl $0, %ebx
cmpl $0, 4(%rsp)
jg .L14
jmp .L15
.L12:
imull %eax, %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 48(%rsp), %rsi
movl $1, %ecx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl 4(%rsp), %eax
movl %eax, 36(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L16:
movl 4(%rsp), %eax
imull %eax, %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 96(%rsp), %rdi
movl $2, %ecx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC4(%rip), %r12
leaq .LC3(%rip), %r13
cmpl $0, 4(%rsp)
jg .L17
.L18:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl 4(%rsp), %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z7convertPiS_iPiS_i
jmp .L16
.L19:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl 96(%rsp,%rax,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L19
.L20:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L18
.L17:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L19
jmp .L20
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z7convertPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7convertPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include"cuda_runtime.h"
#include"device_launch_parameters.h"
#include<stdio.h>
__global__ void convert(int *b, int *c, int n)
{
int tx,ty,i;
tx = threadIdx.x;
ty = threadIdx.y;
if(tx==ty)
{
c[tx*n+ty]=0;
}
else if(tx>ty)
{
int fact = 1;
for(i=1;i<b[ty*n+tx];i++)
{
fact += fact * i;
}
c[ty*n+tx]=fact;
//printf("\nx = %d, y= %d ,fact =%d",tx,ty,fact);
}
else if(ty>tx)
{
int num=b[ty*n+tx];
int r=0;
while(num>0)
{
r+=num%10;
num=num/10;
}
c[ty*n+tx]=r;
//printf("\nx = %d, y= %d ,num =%d",tx,ty,r);
}
}
int main(void)
{
int n,i,j,a[3][3],b[9],c[9];
int *d_b,*d_c, size;
printf("Enter value of n\n");
scanf("%d", &n);
printf("Enter the elements of the matrix\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
scanf("%d", &a[i][j]);
}
}
/*for(i=0;i<n*n;i++)
{
b[i]=a[i][j];
}*/
size = sizeof(int);
cudaMalloc((void **)&d_b,n*n*size);
cudaMalloc((void **)&d_c,n*n*size);
cudaMemcpy(d_b,a,n*n*size,cudaMemcpyHostToDevice);
dim3 dimgrid(1,1,1);
dim3 dimblock(n,n,1);
convert<<<dimgrid,dimblock>>>(d_b,d_c,n);
cudaMemcpy(c,d_c,n*n*size,cudaMemcpyDeviceToHost);
printf("\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t", c[i*n+j]);
}
printf("\n");
}
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include"hip/hip_runtime.h"
#include<stdio.h>
__global__ void convert(int *b, int *c, int n)
{
int tx,ty,i;
tx = threadIdx.x;
ty = threadIdx.y;
if(tx==ty)
{
c[tx*n+ty]=0;
}
else if(tx>ty)
{
int fact = 1;
for(i=1;i<b[ty*n+tx];i++)
{
fact += fact * i;
}
c[ty*n+tx]=fact;
//printf("\nx = %d, y= %d ,fact =%d",tx,ty,fact);
}
else if(ty>tx)
{
int num=b[ty*n+tx];
int r=0;
while(num>0)
{
r+=num%10;
num=num/10;
}
c[ty*n+tx]=r;
//printf("\nx = %d, y= %d ,num =%d",tx,ty,r);
}
}
int main(void)
{
int n,i,j,a[3][3],b[9],c[9];
int *d_b,*d_c, size;
printf("Enter value of n\n");
scanf("%d", &n);
printf("Enter the elements of the matrix\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
scanf("%d", &a[i][j]);
}
}
/*for(i=0;i<n*n;i++)
{
b[i]=a[i][j];
}*/
size = sizeof(int);
hipMalloc((void **)&d_b,n*n*size);
hipMalloc((void **)&d_c,n*n*size);
hipMemcpy(d_b,a,n*n*size,hipMemcpyHostToDevice);
dim3 dimgrid(1,1,1);
dim3 dimblock(n,n,1);
convert<<<dimgrid,dimblock>>>(d_b,d_c,n);
hipMemcpy(c,d_c,n*n*size,hipMemcpyDeviceToHost);
printf("\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t", c[i*n+j]);
}
printf("\n");
}
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include"hip/hip_runtime.h"
#include<stdio.h>
__global__ void convert(int *b, int *c, int n)
{
int tx,ty,i;
tx = threadIdx.x;
ty = threadIdx.y;
if(tx==ty)
{
c[tx*n+ty]=0;
}
else if(tx>ty)
{
int fact = 1;
for(i=1;i<b[ty*n+tx];i++)
{
fact += fact * i;
}
c[ty*n+tx]=fact;
//printf("\nx = %d, y= %d ,fact =%d",tx,ty,fact);
}
else if(ty>tx)
{
int num=b[ty*n+tx];
int r=0;
while(num>0)
{
r+=num%10;
num=num/10;
}
c[ty*n+tx]=r;
//printf("\nx = %d, y= %d ,num =%d",tx,ty,r);
}
}
int main(void)
{
int n,i,j,a[3][3],b[9],c[9];
int *d_b,*d_c, size;
printf("Enter value of n\n");
scanf("%d", &n);
printf("Enter the elements of the matrix\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
scanf("%d", &a[i][j]);
}
}
/*for(i=0;i<n*n;i++)
{
b[i]=a[i][j];
}*/
size = sizeof(int);
hipMalloc((void **)&d_b,n*n*size);
hipMalloc((void **)&d_c,n*n*size);
hipMemcpy(d_b,a,n*n*size,hipMemcpyHostToDevice);
dim3 dimgrid(1,1,1);
dim3 dimblock(n,n,1);
convert<<<dimgrid,dimblock>>>(d_b,d_c,n);
hipMemcpy(c,d_c,n*n*size,hipMemcpyDeviceToHost);
printf("\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t", c[i*n+j]);
}
printf("\n");
}
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7convertPiS_i
.globl _Z7convertPiS_i
.p2align 8
.type _Z7convertPiS_i,@function
_Z7convertPiS_i:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e64 v2, v3
s_xor_b32 s5, exec_lo, s3
s_cbranch_execz .LBB0_16
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s6, 0
s_mov_b32 s7, exec_lo
v_cmpx_le_u32_e64 v2, v3
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_9
s_mov_b32 s8, 0
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 v3, v2
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_mov_b32_e32 v4, 0
s_mov_b32 s9, 0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v2
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v4, 0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v2, 0xcccccccd
v_cmp_gt_u32_e32 vcc_lo, 10, v2
s_or_b32 s9, vcc_lo, s9
v_lshrrev_b32_e32 v3, 3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v3, 10
v_sub_nc_u32_e32 v5, v2, v5
v_mov_b32_e32 v2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v5
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s9
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_mov_b32 s8, exec_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s8, exec_lo
.LBB0_9:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_mov_b32_e32 v4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, 1
s_mov_b32 s2, exec_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 1, v2
s_cbranch_execz .LBB0_14
s_mov_b32 s8, 0
s_mov_b32 s9, 1
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, 1
v_cmp_eq_u32_e32 vcc_lo, s9, v2
s_mul_i32 s3, s3, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v4, s3
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s8
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_or_b32 s6, s6, exec_lo
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s6, exec_lo
.LBB0_16:
s_and_not1_saveexec_b32 s3, s5
s_cbranch_execz .LBB0_18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_mov_b32_e32 v4, 0
s_or_b32 s2, s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7convertPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7convertPiS_i, .Lfunc_end0-_Z7convertPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7convertPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z7convertPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include"hip/hip_runtime.h"
#include<stdio.h>
__global__ void convert(int *b, int *c, int n)
{
int tx,ty,i;
tx = threadIdx.x;
ty = threadIdx.y;
if(tx==ty)
{
c[tx*n+ty]=0;
}
else if(tx>ty)
{
int fact = 1;
for(i=1;i<b[ty*n+tx];i++)
{
fact += fact * i;
}
c[ty*n+tx]=fact;
//printf("\nx = %d, y= %d ,fact =%d",tx,ty,fact);
}
else if(ty>tx)
{
int num=b[ty*n+tx];
int r=0;
while(num>0)
{
r+=num%10;
num=num/10;
}
c[ty*n+tx]=r;
//printf("\nx = %d, y= %d ,num =%d",tx,ty,r);
}
}
int main(void)
{
int n,i,j,a[3][3],b[9],c[9];
int *d_b,*d_c, size;
printf("Enter value of n\n");
scanf("%d", &n);
printf("Enter the elements of the matrix\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
scanf("%d", &a[i][j]);
}
}
/*for(i=0;i<n*n;i++)
{
b[i]=a[i][j];
}*/
size = sizeof(int);
hipMalloc((void **)&d_b,n*n*size);
hipMalloc((void **)&d_c,n*n*size);
hipMemcpy(d_b,a,n*n*size,hipMemcpyHostToDevice);
dim3 dimgrid(1,1,1);
dim3 dimblock(n,n,1);
convert<<<dimgrid,dimblock>>>(d_b,d_c,n);
hipMemcpy(c,d_c,n*n*size,hipMemcpyDeviceToHost);
printf("\n");
for(i=0;i<n;i++)
{
for(j=0;j<n;j++)
{
printf("%d\t", c[i*n+j]);
}
printf("\n");
}
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "w8p3.hip"
.globl _Z22__device_stub__convertPiS_i # -- Begin function _Z22__device_stub__convertPiS_i
.p2align 4, 0x90
.type _Z22__device_stub__convertPiS_i,@function
_Z22__device_stub__convertPiS_i: # @_Z22__device_stub__convertPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7convertPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__convertPiS_i, .Lfunc_end0-_Z22__device_stub__convertPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.1, %edi
callq puts@PLT
movl 4(%rsp), %esi
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader30.preheader
leaq 144(%rsp), %r14
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r15
movslq 4(%rsp), %rsi
addq $12, %r14
cmpq %rsi, %r15
jge .LBB1_6
.LBB1_2: # %.preheader30
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 4(%rsp)
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movq %r14, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 4(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r12
jl .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge33
imull %esi, %esi
shll $2, %esi
leaq 16(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %esi
imull %esi, %esi
shll $2, %esi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movl 4(%rsp), %edx
imull %edx, %edx
shll $2, %edx
leaq 144(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
movq %rax, %rdx
shlq $32, %rdx
orq %rax, %rdx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7convertPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
movl 4(%rsp), %edx
imull %edx, %edx
shll $2, %edx
leaq 96(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl $10, %edi
callq putchar@PLT
cmpl $0, 4(%rsp)
jle .LBB1_14
# %bb.9: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_13: # %._crit_edge36
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB1_14
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_13
# %bb.11: # %.lr.ph35.preheader
# in Loop: Header=BB1_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph35
# Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebx, %eax
cltq
addq %r14, %rax
movl 96(%rsp,%rax,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 4(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_12
jmp .LBB1_13
.LBB1_14: # %._crit_edge38
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7convertPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7convertPiS_i,@object # @_Z7convertPiS_i
.section .rodata,"a",@progbits
.globl _Z7convertPiS_i
.p2align 3, 0x0
_Z7convertPiS_i:
.quad _Z22__device_stub__convertPiS_i
.size _Z7convertPiS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d\t"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7convertPiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter value of n"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter the elements of the matrix"
.size .Lstr.1, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__convertPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7convertPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7convertPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ ISETP.NE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x001fda0003f05270 */
/*0050*/ @!P0 BRA 0x8a0 ; /* 0x0000084000008947 */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GT.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0080*/ IMAD R2, R0, c[0x0][0x170], R7 ; /* 0x00005c0000027a24 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R2, R3, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fe400078e0203 */
/*00b0*/ @P0 BRA 0x1f0 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GT.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fda0003f04270 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ BSSY B0, 0x1d0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0100*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0110*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x004fda0003f06270 */
/*0120*/ @!P0 BRA 0x1c0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, R4 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0004 */
/*0140*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.WIDE.U32 R4, R0.reuse, -0x33333333, RZ ; /* 0xcccccccd00047825 */
/* 0x040fe200078e00ff */
/*0160*/ ISETP.GT.U32.AND P0, PT, R0, 0x9, PT ; /* 0x000000090000780c */
/* 0x000fc80003f04070 */
/*0170*/ SHF.R.U32.HI R5, RZ, 0x3, R5 ; /* 0x00000003ff057819 */
/* 0x000fca0000011605 */
/*0180*/ IMAD R0, R5, -0xa, R0 ; /* 0xfffffff605007824 */
/* 0x000fc800078e0200 */
/*0190*/ IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100077824 */
/* 0x000fe400078e0207 */
/*01a0*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x000fe200078e0005 */
/*01b0*/ @P0 BRA 0x150 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*01c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0200*/ BSSY B2, 0x880 ; /* 0x0000067000027945 */
/* 0x000fe20003800000 */
/*0210*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0220*/ ISETP.GE.AND P0, PT, R4, 0x2, PT ; /* 0x000000020400780c */
/* 0x004fda0003f06270 */
/*0230*/ @!P0 BRA 0x870 ; /* 0x0000063000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R0, R4.reuse, -0x2, RZ ; /* 0xfffffffe04007810 */
/* 0x040fe20007ffe0ff */
/*0250*/ BSSY B1, 0x800 ; /* 0x000005a000017945 */
/* 0x000fe20003800000 */
/*0260*/ IADD3 R5, R4, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x000fe20007ffe0ff */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0280*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*02a0*/ LOP3.LUT R0, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305007812 */
/* 0x000fd600078ec0ff */
/*02b0*/ @!P0 BRA 0x7f0 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.IADD R5, R5, 0x1, -R0 ; /* 0x0000000105057824 */
/* 0x000fe200078e0a00 */
/*02d0*/ BSSY B0, 0x740 ; /* 0x0000046000007945 */
/* 0x000fe20003800000 */
/*02e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fc600078e00ff */
/*02f0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f04270 */
/*0300*/ @!P0 BRA 0x730 ; /* 0x0000042000008947 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0320*/ BSSY B3, 0x5a0 ; /* 0x0000027000037945 */
/* 0x000fe20003800000 */
/*0330*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0340*/ @!P1 BRA 0x590 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0350*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0360*/ IADD3 R6, R4.reuse, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x040fe20007ffe0ff */
/*0370*/ IMAD R7, R4.reuse, R7, R7 ; /* 0x0000000704077224 */
/* 0x040fe200078e0207 */
/*0380*/ IADD3 R9, R4.reuse, 0x2, RZ ; /* 0x0000000204097810 */
/* 0x040fe40007ffe0ff */
/*0390*/ IADD3 R8, R4.reuse, 0x3, RZ ; /* 0x0000000304087810 */
/* 0x040fe20007ffe0ff */
/*03a0*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*03b0*/ IADD3 R7, R4, 0x4, RZ ; /* 0x0000000404077810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fe200078e0206 */
/*03e0*/ IADD3 R6, R4, 0x5, RZ ; /* 0x0000000504067810 */
/* 0x000fc40007ffe0ff */
/*03f0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0400*/ IMAD R8, R9, R8, R9 ; /* 0x0000000809087224 */
/* 0x000fe200078e0209 */
/*0410*/ IADD3 R9, R4, 0x6, RZ ; /* 0x0000000604097810 */
/* 0x000fc60007ffe0ff */
/*0420*/ IMAD R7, R8, R7, R8 ; /* 0x0000000708077224 */
/* 0x000fe200078e0208 */
/*0430*/ IADD3 R8, R4, 0x7, RZ ; /* 0x0000000704087810 */
/* 0x000fc60007ffe0ff */
/*0440*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*0450*/ IADD3 R7, R4, 0x8, RZ ; /* 0x0000000804077810 */
/* 0x000fc60007ffe0ff */
/*0460*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fe200078e0206 */
/*0470*/ IADD3 R6, R4, 0x9, RZ ; /* 0x0000000904067810 */
/* 0x000fc60007ffe0ff */
/*0480*/ IMAD R8, R9, R8, R9 ; /* 0x0000000809087224 */
/* 0x000fe200078e0209 */
/*0490*/ IADD3 R9, R4, 0xa, RZ ; /* 0x0000000a04097810 */
/* 0x000fc60007ffe0ff */
/*04a0*/ IMAD R7, R8, R7, R8 ; /* 0x0000000708077224 */
/* 0x000fe200078e0208 */
/*04b0*/ IADD3 R8, R4, 0xb, RZ ; /* 0x0000000b04087810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*04d0*/ IADD3 R7, R4, 0xc, RZ ; /* 0x0000000c04077810 */
/* 0x000fc60007ffe0ff */
/*04e0*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fe200078e0206 */
/*04f0*/ IADD3 R6, R4, 0xd, RZ ; /* 0x0000000d04067810 */
/* 0x000fc60007ffe0ff */
/*0500*/ IMAD R8, R9, R8, R9 ; /* 0x0000000809087224 */
/* 0x000fe200078e0209 */
/*0510*/ IADD3 R9, R4, 0xe, RZ ; /* 0x0000000e04097810 */
/* 0x000fc60007ffe0ff */
/*0520*/ IMAD R7, R8, R7, R8 ; /* 0x0000000708077224 */
/* 0x000fe200078e0208 */
/*0530*/ IADD3 R8, R4.reuse, 0xf, RZ ; /* 0x0000000f04087810 */
/* 0x040fe40007ffe0ff */
/*0540*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fc800078e0207 */
/*0560*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fc800078e0206 */
/*0570*/ IMAD R7, R9, R8, R9 ; /* 0x0000000809077224 */
/* 0x000fe200078e0209 */
/*0580*/ @P1 BRA 0x360 ; /* 0xfffffdd000001947 */
/* 0x000fea000383ffff */
/*0590*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fe20003f24270 */
/*05b0*/ BSSY B3, 0x700 ; /* 0x0000014000037945 */
/* 0x000fd80003800000 */
/*05c0*/ @!P1 BRA 0x6f0 ; /* 0x0000012000009947 */
/* 0x000fea0003800000 */
/*05d0*/ IADD3 R6, R4.reuse, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x040fe20007ffe0ff */
/*05e0*/ IMAD R7, R7, R4, R7 ; /* 0x0000000407077224 */
/* 0x000fe200078e0207 */
/*05f0*/ IADD3 R9, R4.reuse, 0x2, RZ ; /* 0x0000000204097810 */
/* 0x040fe40007ffe0ff */
/*0600*/ IADD3 R8, R4.reuse, 0x3, RZ ; /* 0x0000000304087810 */
/* 0x040fe20007ffe0ff */
/*0610*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*0620*/ IADD3 R7, R4, 0x4, RZ ; /* 0x0000000404077810 */
/* 0x000fe40007ffe0ff */
/*0630*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0640*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fe200078e0206 */
/*0650*/ IADD3 R6, R4, 0x5, RZ ; /* 0x0000000504067810 */
/* 0x000fc40007ffe0ff */
/*0660*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0670*/ IMAD R8, R9, R8, R9 ; /* 0x0000000809087224 */
/* 0x000fe200078e0209 */
/*0680*/ IADD3 R9, R4, 0x6, RZ ; /* 0x0000000604097810 */
/* 0x000fc60007ffe0ff */
/*0690*/ IMAD R7, R8, R7, R8 ; /* 0x0000000708077224 */
/* 0x000fe200078e0208 */
/*06a0*/ IADD3 R8, R4.reuse, 0x7, RZ ; /* 0x0000000704087810 */
/* 0x040fe40007ffe0ff */
/*06b0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fc800078e0207 */
/*06d0*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fc800078e0206 */
/*06e0*/ IMAD R7, R9, R8, R9 ; /* 0x0000000809077224 */
/* 0x000fe400078e0209 */
/*06f0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0710*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*0720*/ @!P0 BRA 0x7f0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0730*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0740*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0750*/ IMAD R7, R4.reuse, R7, R7 ; /* 0x0000000704077224 */
/* 0x040fe200078e0207 */
/*0760*/ IADD3 R6, R4.reuse, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x040fe40007ffe0ff */
/*0770*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f05270 */
/*0780*/ IADD3 R9, R4.reuse, 0x2, RZ ; /* 0x0000000204097810 */
/* 0x040fe20007ffe0ff */
/*0790*/ IMAD R6, R7, R6, R7 ; /* 0x0000000607067224 */
/* 0x000fe200078e0207 */
/*07a0*/ IADD3 R8, R4.reuse, 0x3, RZ ; /* 0x0000000304087810 */
/* 0x040fe40007ffe0ff */
/*07b0*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fe20007ffe0ff */
/*07c0*/ IMAD R9, R6, R9, R6 ; /* 0x0000000906097224 */
/* 0x000fc800078e0206 */
/*07d0*/ IMAD R7, R9, R8, R9 ; /* 0x0000000809077224 */
/* 0x000fe400078e0209 */
/*07e0*/ @P0 BRA 0x740 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*07f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0800*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0810*/ @!P0 BRA 0x870 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0820*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe20007ffe0ff */
/*0830*/ IMAD R7, R4.reuse, R7, R7 ; /* 0x0000000704077224 */
/* 0x040fe200078e0207 */
/*0840*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0850*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0860*/ @P0 BRA 0x820 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*0870*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0880*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*08b0*/ IMAD R2, R7, c[0x0][0x170], R7 ; /* 0x00005c0007027a24 */
/* 0x000fc800078e0207 */
/*08c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*08d0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*08e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08f0*/ BRA 0x8f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7convertPiS_i
.globl _Z7convertPiS_i
.p2align 8
.type _Z7convertPiS_i,@function
_Z7convertPiS_i:
s_load_b32 s4, s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ne_u32_e64 v2, v3
s_xor_b32 s5, exec_lo, s3
s_cbranch_execz .LBB0_16
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s6, 0
s_mov_b32 s7, exec_lo
v_cmpx_le_u32_e64 v2, v3
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_9
s_mov_b32 s8, 0
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 v3, v2
s_xor_b32 s6, exec_lo, s6
s_cbranch_execz .LBB0_8
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_mov_b32_e32 v4, 0
s_mov_b32 s9, 0
s_mov_b32 s8, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 0, v2
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v4, 0
.LBB0_5:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v2, 0xcccccccd
v_cmp_gt_u32_e32 vcc_lo, 10, v2
s_or_b32 s9, vcc_lo, s9
v_lshrrev_b32_e32 v3, 3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v3, 10
v_sub_nc_u32_e32 v5, v2, v5
v_mov_b32_e32 v2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v4, v4, v5
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_5
s_or_b32 exec_lo, exec_lo, s9
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s8
s_mov_b32 s8, exec_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s6, s8, exec_lo
.LBB0_9:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
v_mov_b32_e32 v4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s3, 1
s_mov_b32 s2, exec_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 1, v2
s_cbranch_execz .LBB0_14
s_mov_b32 s8, 0
s_mov_b32 s9, 1
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, 1
v_cmp_eq_u32_e32 vcc_lo, s9, v2
s_mul_i32 s3, s3, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v4, s3
s_or_b32 s8, vcc_lo, s8
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s8
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_or_b32 s6, s6, exec_lo
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s6, exec_lo
.LBB0_16:
s_and_not1_saveexec_b32 s3, s5
s_cbranch_execz .LBB0_18
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[0:1], null, v2, s4, v[3:4]
v_mov_b32_e32 v4, 0
s_or_b32 s2, s2, exec_lo
s_delay_alu instid0(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_20
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7convertPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7convertPiS_i, .Lfunc_end0-_Z7convertPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7convertPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z7convertPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00105fcf_00000000-6_w8p3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z7convertPiS_iPiS_i
.type _Z29__device_stub__Z7convertPiS_iPiS_i, @function
_Z29__device_stub__Z7convertPiS_iPiS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7convertPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z7convertPiS_iPiS_i, .-_Z29__device_stub__Z7convertPiS_iPiS_i
.globl _Z7convertPiS_i
.type _Z7convertPiS_i, @function
_Z7convertPiS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z7convertPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7convertPiS_i, .-_Z7convertPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value of n\n"
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Enter the elements of the matrix\n"
.section .rodata.str1.1
.LC3:
.string "\n"
.LC4:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $144, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jle .L12
leaq 48(%rsp), %r14
movl $0, %r13d
leaq .LC1(%rip), %r12
jmp .L13
.L14:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
addq $4, %rbp
cmpl %ebx, 4(%rsp)
jg .L14
.L15:
movl 4(%rsp), %eax
addq $1, %r13
addq $12, %r14
cmpl %r13d, %eax
jle .L12
.L13:
movq %r14, %rbp
movl $0, %ebx
cmpl $0, 4(%rsp)
jg .L14
jmp .L15
.L12:
imull %eax, %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
imull %eax, %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 48(%rsp), %rsi
movl $1, %ecx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl 4(%rsp), %eax
movl %eax, 36(%rsp)
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L16:
movl 4(%rsp), %eax
imull %eax, %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 96(%rsp), %rdi
movl $2, %ecx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC4(%rip), %r12
leaq .LC3(%rip), %r13
cmpl $0, 4(%rsp)
jg .L17
.L18:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movl 4(%rsp), %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z7convertPiS_iPiS_i
jmp .L16
.L19:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl 96(%rsp,%rax,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L19
.L20:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L18
.L17:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L19
jmp .L20
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z7convertPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7convertPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "w8p3.hip"
.globl _Z22__device_stub__convertPiS_i # -- Begin function _Z22__device_stub__convertPiS_i
.p2align 4, 0x90
.type _Z22__device_stub__convertPiS_i,@function
_Z22__device_stub__convertPiS_i: # @_Z22__device_stub__convertPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7convertPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z22__device_stub__convertPiS_i, .Lfunc_end0-_Z22__device_stub__convertPiS_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
leaq 4(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr.1, %edi
callq puts@PLT
movl 4(%rsp), %esi
testl %esi, %esi
jle .LBB1_6
# %bb.1: # %.preheader30.preheader
leaq 144(%rsp), %r14
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r15
movslq 4(%rsp), %rsi
addq $12, %r14
cmpq %rsi, %r15
jge .LBB1_6
.LBB1_2: # %.preheader30
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
cmpl $0, 4(%rsp)
jle .LBB1_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB1_2 Depth=1
movq %r14, %rbx
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r12
movslq 4(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r12
jl .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge33
imull %esi, %esi
shll $2, %esi
leaq 16(%rsp), %rdi
callq hipMalloc
movl 4(%rsp), %esi
imull %esi, %esi
shll $2, %esi
leaq 8(%rsp), %rdi
callq hipMalloc
movq 16(%rsp), %rdi
movl 4(%rsp), %edx
imull %edx, %edx
shll $2, %edx
leaq 144(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %eax
movq %rax, %rdx
shlq $32, %rdx
orq %rax, %rdx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %edx, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7convertPiS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 8(%rsp), %rsi
movl 4(%rsp), %edx
imull %edx, %edx
shll $2, %edx
leaq 96(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl $10, %edi
callq putchar@PLT
cmpl $0, 4(%rsp)
jle .LBB1_14
# %bb.9: # %.preheader.preheader
xorl %ebx, %ebx
jmp .LBB1_10
.p2align 4, 0x90
.LBB1_13: # %._crit_edge36
# in Loop: Header=BB1_10 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB1_14
.LBB1_10: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_12 Depth 2
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB1_13
# %bb.11: # %.lr.ph35.preheader
# in Loop: Header=BB1_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_12: # %.lr.ph35
# Parent Loop BB1_10 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebx, %eax
cltq
addq %r14, %rax
movl 96(%rsp,%rax,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl 4(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_12
jmp .LBB1_13
.LBB1_14: # %._crit_edge38
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7convertPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7convertPiS_i,@object # @_Z7convertPiS_i
.section .rodata,"a",@progbits
.globl _Z7convertPiS_i
.p2align 3, 0x0
_Z7convertPiS_i:
.quad _Z22__device_stub__convertPiS_i
.size _Z7convertPiS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d\t"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7convertPiS_i"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter value of n"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter the elements of the matrix"
.size .Lstr.1, 33
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__convertPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7convertPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
__global__ void helloFromGPU(){
printf("Hello World from GPU: %d\n",threadIdx.x);
}
int main(void){
helloFromGPU<<<1,10>>>();
cudaDeviceReset();
//cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z12helloFromGPUv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
__global__ void helloFromGPU(){
printf("Hello World from GPU: %d\n",threadIdx.x);
}
int main(void){
helloFromGPU<<<1,10>>>();
cudaDeviceReset();
//cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_00114ec4_00000000-6_helloFromGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
__global__ void helloFromGPU(){
printf("Hello World from GPU: %d\n",threadIdx.x);
}
int main(void){
helloFromGPU<<<1,10>>>();
cudaDeviceReset();
//cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void helloFromGPU(){
printf("Hello World from GPU: %d\n",threadIdx.x);
}
int main(void){
helloFromGPU<<<1,10>>>();
hipDeviceReset();
//cudaDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
__global__ void helloFromGPU(){
printf("Hello World from GPU: %d\n",threadIdx.x);
}
int main(void){
helloFromGPU<<<1,10>>>();
hipDeviceReset();
//cudaDeviceSynchronize();
return 0;
} | .text
.file "helloFromGPU.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00114ec4_00000000-6_helloFromGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z12helloFromGPUvv
.type _Z31__device_stub__Z12helloFromGPUvv, @function
_Z31__device_stub__Z12helloFromGPUvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12helloFromGPUv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z12helloFromGPUvv, .-_Z31__device_stub__Z12helloFromGPUvv
.globl _Z12helloFromGPUv
.type _Z12helloFromGPUv, @function
_Z12helloFromGPUv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z12helloFromGPUvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12helloFromGPUv, .-_Z12helloFromGPUv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceReset@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z31__device_stub__Z12helloFromGPUvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12helloFromGPUv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12helloFromGPUv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "helloFromGPU.hip"
.globl _Z27__device_stub__helloFromGPUv # -- Begin function _Z27__device_stub__helloFromGPUv
.p2align 4, 0x90
.type _Z27__device_stub__helloFromGPUv,@function
_Z27__device_stub__helloFromGPUv: # @_Z27__device_stub__helloFromGPUv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z27__device_stub__helloFromGPUv, .Lfunc_end0-_Z27__device_stub__helloFromGPUv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z12helloFromGPUv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceReset
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12helloFromGPUv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12helloFromGPUv,@object # @_Z12helloFromGPUv
.section .rodata,"a",@progbits
.globl _Z12helloFromGPUv
.p2align 3, 0x0
_Z12helloFromGPUv:
.quad _Z27__device_stub__helloFromGPUv
.size _Z12helloFromGPUv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12helloFromGPUv"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__helloFromGPUv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12helloFromGPUv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "math.h"
#include <fstream>
#include <sstream>
#include <float.h>
__device__
double euclideanDistance(double *training, double *test, int trainingIndexStart, int testIndexStart, int size) {
double temporary = 0;
for(unsigned i = 0; i < size; i++) {
temporary += (training[trainingIndexStart + i] - training[testIndexStart + i]) * (training[trainingIndexStart + i] - training[testIndexStart + i]);
}
return sqrt(temporary);
}
__global__
void runAlgorithm(double* result, double *training, double *test, int rowsTraining, int rowsTest, int columns) {
int currentTrainingRow = 0;
int minDistanceLabel = 0;
double minDistance = DBL_MAX;
int stride = blockDim.x * gridDim.x;
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < rowsTraining * columns; i += stride, currentTrainingRow++) {
for (int j = 0; j < rowsTest * columns; j += columns) {
double distance = euclideanDistance(training, test, i, j, columns-1);
if (distance < minDistance) {
minDistance = distance;
minDistanceLabel = test[j+columns-1];
}
}
minDistance = DBL_MAX;
result[currentTrainingRow] = minDistanceLabel;
}
}
__host__
double showAccuracy(double *data, double* predictions, int rows, int columns) {
double count = 0;
int row = 0;
for(int i = columns-1; i < rows * columns; i += columns, row++) {
if (data[i] == predictions[row]) {
count++;
}
}
return (count / rows) * 100;
}
__host__
int countWords(const std::string& text, char delimiter) {
std::stringstream stream(text);
std::string temp;
int counter = 0;
while(getline(stream, temp, delimiter)) {
counter++;
}
return counter;
}
__host__
void countRowsAndColumns(std::string filename, int* rows, int* columns) {
std::ifstream featuresFile(filename);
std::string line;
std::getline(featuresFile, line);
*columns = countWords(line, ',');
*rows = 1;
while (std::getline(featuresFile, line))
(*rows)++;
featuresFile.close();
}
__host__
void readFeaturesFromCsv(std::string filename, double* result, int rows, int columns) {
std::ifstream featuresFile(filename);
std::string line;
int i = 0;
while(std::getline(featuresFile, line))
{
std::stringstream ss(line);
double value;
while(ss >> value){
result[i] = value;
if(ss.peek() == ',') ss.ignore();
i++;
}
}
featuresFile.close();
}
__host__
void splitForTestAndTrainingData(double *data, int columns, double *training, double*test, int rowsTraining, int rowsTest)
{
int counter = 0;
int dataCounter = 0;
while(++counter < rowsTest)
{
for(int j = 0; j < columns; j++, dataCounter++)
test[dataCounter] = data[dataCounter];
}
counter = 0;
int i = 0;
while(++counter < rowsTraining)
{
for(int j = 0; j < columns; j++, dataCounter++, i++)
training[i] = data[dataCounter];
}
}
int main(int argc, char* argv[]) {
int rows, columns;
std::string fileName("./data.csv");
countRowsAndColumns(fileName, &rows, &columns);
double *input = new double[rows * columns];
readFeaturesFromCsv(fileName, input, rows, columns);
int rowsTraining = rows * 0.8;
int rowsTest = rows - rowsTraining;
double *test = new double[rowsTest*columns];
double *training = new double[rowsTraining*columns];
double *predictions = new double[rowsTraining * columns];
double *cudaTraining;
double *cudaTest;
double *cudaPrediction;
splitForTestAndTrainingData(input, columns, training, test, rowsTraining, rowsTest);
cudaMalloc((void **) &cudaTraining, rowsTraining * columns * sizeof(double));
cudaMemcpy(cudaTraining, training, rowsTraining * columns * sizeof(double), cudaMemcpyHostToDevice);
cudaMalloc((void **) &cudaTest, rowsTest * columns * sizeof(double));
cudaMemcpy(cudaTest, test, rowsTest * columns * sizeof(double), cudaMemcpyHostToDevice);
cudaMalloc((void **) &cudaPrediction, rowsTraining * sizeof(double));
cudaMemcpy(cudaPrediction, predictions, rowsTraining * sizeof(double), cudaMemcpyHostToDevice);
cudaEvent_t startTime, stopTime;
cudaEventCreate(&startTime);
cudaEventCreate(&stopTime);
cudaEventRecord(startTime);
runAlgorithm<<<1, 1>>>(cudaPrediction, cudaTraining, cudaTest, rowsTraining, rowsTest, columns);
float resultTime;
cudaEventRecord(stopTime);
cudaEventSynchronize(stopTime);
cudaEventElapsedTime(&resultTime, startTime, stopTime);
cudaMemcpy(predictions, cudaPrediction, rowsTraining * sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(cudaTraining);
cudaFree(cudaTest);
cudaFree(cudaPrediction);
printf("Algorithm took: %f (ms)\n", resultTime);
double accuracy = showAccuracy(training, predictions, rowsTraining, columns);
printf("Accuracy: %f\n", accuracy);
} | #include <hip/hip_runtime.h>
#include "math.h"
#include <fstream>
#include <sstream>
#include <float.h>
__device__
double euclideanDistance(double *training, double *test, int trainingIndexStart, int testIndexStart, int size) {
double temporary = 0;
for(unsigned i = 0; i < size; i++) {
temporary += (training[trainingIndexStart + i] - training[testIndexStart + i]) * (training[trainingIndexStart + i] - training[testIndexStart + i]);
}
return sqrt(temporary);
}
__global__
void runAlgorithm(double* result, double *training, double *test, int rowsTraining, int rowsTest, int columns) {
int currentTrainingRow = 0;
int minDistanceLabel = 0;
double minDistance = DBL_MAX;
int stride = blockDim.x * gridDim.x;
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < rowsTraining * columns; i += stride, currentTrainingRow++) {
for (int j = 0; j < rowsTest * columns; j += columns) {
double distance = euclideanDistance(training, test, i, j, columns-1);
if (distance < minDistance) {
minDistance = distance;
minDistanceLabel = test[j+columns-1];
}
}
minDistance = DBL_MAX;
result[currentTrainingRow] = minDistanceLabel;
}
}
__host__
double showAccuracy(double *data, double* predictions, int rows, int columns) {
double count = 0;
int row = 0;
for(int i = columns-1; i < rows * columns; i += columns, row++) {
if (data[i] == predictions[row]) {
count++;
}
}
return (count / rows) * 100;
}
__host__
int countWords(const std::string& text, char delimiter) {
std::stringstream stream(text);
std::string temp;
int counter = 0;
while(getline(stream, temp, delimiter)) {
counter++;
}
return counter;
}
__host__
void countRowsAndColumns(std::string filename, int* rows, int* columns) {
std::ifstream featuresFile(filename);
std::string line;
std::getline(featuresFile, line);
*columns = countWords(line, ',');
*rows = 1;
while (std::getline(featuresFile, line))
(*rows)++;
featuresFile.close();
}
__host__
void readFeaturesFromCsv(std::string filename, double* result, int rows, int columns) {
std::ifstream featuresFile(filename);
std::string line;
int i = 0;
while(std::getline(featuresFile, line))
{
std::stringstream ss(line);
double value;
while(ss >> value){
result[i] = value;
if(ss.peek() == ',') ss.ignore();
i++;
}
}
featuresFile.close();
}
__host__
void splitForTestAndTrainingData(double *data, int columns, double *training, double*test, int rowsTraining, int rowsTest)
{
int counter = 0;
int dataCounter = 0;
while(++counter < rowsTest)
{
for(int j = 0; j < columns; j++, dataCounter++)
test[dataCounter] = data[dataCounter];
}
counter = 0;
int i = 0;
while(++counter < rowsTraining)
{
for(int j = 0; j < columns; j++, dataCounter++, i++)
training[i] = data[dataCounter];
}
}
int main(int argc, char* argv[]) {
int rows, columns;
std::string fileName("./data.csv");
countRowsAndColumns(fileName, &rows, &columns);
double *input = new double[rows * columns];
readFeaturesFromCsv(fileName, input, rows, columns);
int rowsTraining = rows * 0.8;
int rowsTest = rows - rowsTraining;
double *test = new double[rowsTest*columns];
double *training = new double[rowsTraining*columns];
double *predictions = new double[rowsTraining * columns];
double *cudaTraining;
double *cudaTest;
double *cudaPrediction;
splitForTestAndTrainingData(input, columns, training, test, rowsTraining, rowsTest);
hipMalloc((void **) &cudaTraining, rowsTraining * columns * sizeof(double));
hipMemcpy(cudaTraining, training, rowsTraining * columns * sizeof(double), hipMemcpyHostToDevice);
hipMalloc((void **) &cudaTest, rowsTest * columns * sizeof(double));
hipMemcpy(cudaTest, test, rowsTest * columns * sizeof(double), hipMemcpyHostToDevice);
hipMalloc((void **) &cudaPrediction, rowsTraining * sizeof(double));
hipMemcpy(cudaPrediction, predictions, rowsTraining * sizeof(double), hipMemcpyHostToDevice);
hipEvent_t startTime, stopTime;
hipEventCreate(&startTime);
hipEventCreate(&stopTime);
hipEventRecord(startTime);
runAlgorithm<<<1, 1>>>(cudaPrediction, cudaTraining, cudaTest, rowsTraining, rowsTest, columns);
float resultTime;
hipEventRecord(stopTime);
hipEventSynchronize(stopTime);
hipEventElapsedTime(&resultTime, startTime, stopTime);
hipMemcpy(predictions, cudaPrediction, rowsTraining * sizeof(double), hipMemcpyDeviceToHost);
hipFree(cudaTraining);
hipFree(cudaTest);
hipFree(cudaPrediction);
printf("Algorithm took: %f (ms)\n", resultTime);
double accuracy = showAccuracy(training, predictions, rowsTraining, columns);
printf("Accuracy: %f\n", accuracy);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "math.h"
#include <fstream>
#include <sstream>
#include <float.h>
__device__
double euclideanDistance(double *training, double *test, int trainingIndexStart, int testIndexStart, int size) {
double temporary = 0;
for(unsigned i = 0; i < size; i++) {
temporary += (training[trainingIndexStart + i] - training[testIndexStart + i]) * (training[trainingIndexStart + i] - training[testIndexStart + i]);
}
return sqrt(temporary);
}
__global__
void runAlgorithm(double* result, double *training, double *test, int rowsTraining, int rowsTest, int columns) {
int currentTrainingRow = 0;
int minDistanceLabel = 0;
double minDistance = DBL_MAX;
int stride = blockDim.x * gridDim.x;
for(int i = blockIdx.x * blockDim.x + threadIdx.x; i < rowsTraining * columns; i += stride, currentTrainingRow++) {
for (int j = 0; j < rowsTest * columns; j += columns) {
double distance = euclideanDistance(training, test, i, j, columns-1);
if (distance < minDistance) {
minDistance = distance;
minDistanceLabel = test[j+columns-1];
}
}
minDistance = DBL_MAX;
result[currentTrainingRow] = minDistanceLabel;
}
}
__host__
double showAccuracy(double *data, double* predictions, int rows, int columns) {
double count = 0;
int row = 0;
for(int i = columns-1; i < rows * columns; i += columns, row++) {
if (data[i] == predictions[row]) {
count++;
}
}
return (count / rows) * 100;
}
__host__
int countWords(const std::string& text, char delimiter) {
std::stringstream stream(text);
std::string temp;
int counter = 0;
while(getline(stream, temp, delimiter)) {
counter++;
}
return counter;
}
__host__
void countRowsAndColumns(std::string filename, int* rows, int* columns) {
std::ifstream featuresFile(filename);
std::string line;
std::getline(featuresFile, line);
*columns = countWords(line, ',');
*rows = 1;
while (std::getline(featuresFile, line))
(*rows)++;
featuresFile.close();
}
__host__
void readFeaturesFromCsv(std::string filename, double* result, int rows, int columns) {
std::ifstream featuresFile(filename);
std::string line;
int i = 0;
while(std::getline(featuresFile, line))
{
std::stringstream ss(line);
double value;
while(ss >> value){
result[i] = value;
if(ss.peek() == ',') ss.ignore();
i++;
}
}
featuresFile.close();
}
__host__
void splitForTestAndTrainingData(double *data, int columns, double *training, double*test, int rowsTraining, int rowsTest)
{
int counter = 0;
int dataCounter = 0;
while(++counter < rowsTest)
{
for(int j = 0; j < columns; j++, dataCounter++)
test[dataCounter] = data[dataCounter];
}
counter = 0;
int i = 0;
while(++counter < rowsTraining)
{
for(int j = 0; j < columns; j++, dataCounter++, i++)
training[i] = data[dataCounter];
}
}
int main(int argc, char* argv[]) {
int rows, columns;
std::string fileName("./data.csv");
countRowsAndColumns(fileName, &rows, &columns);
double *input = new double[rows * columns];
readFeaturesFromCsv(fileName, input, rows, columns);
int rowsTraining = rows * 0.8;
int rowsTest = rows - rowsTraining;
double *test = new double[rowsTest*columns];
double *training = new double[rowsTraining*columns];
double *predictions = new double[rowsTraining * columns];
double *cudaTraining;
double *cudaTest;
double *cudaPrediction;
splitForTestAndTrainingData(input, columns, training, test, rowsTraining, rowsTest);
hipMalloc((void **) &cudaTraining, rowsTraining * columns * sizeof(double));
hipMemcpy(cudaTraining, training, rowsTraining * columns * sizeof(double), hipMemcpyHostToDevice);
hipMalloc((void **) &cudaTest, rowsTest * columns * sizeof(double));
hipMemcpy(cudaTest, test, rowsTest * columns * sizeof(double), hipMemcpyHostToDevice);
hipMalloc((void **) &cudaPrediction, rowsTraining * sizeof(double));
hipMemcpy(cudaPrediction, predictions, rowsTraining * sizeof(double), hipMemcpyHostToDevice);
hipEvent_t startTime, stopTime;
hipEventCreate(&startTime);
hipEventCreate(&stopTime);
hipEventRecord(startTime);
runAlgorithm<<<1, 1>>>(cudaPrediction, cudaTraining, cudaTest, rowsTraining, rowsTest, columns);
float resultTime;
hipEventRecord(stopTime);
hipEventSynchronize(stopTime);
hipEventElapsedTime(&resultTime, startTime, stopTime);
hipMemcpy(predictions, cudaPrediction, rowsTraining * sizeof(double), hipMemcpyDeviceToHost);
hipFree(cudaTraining);
hipFree(cudaTest);
hipFree(cudaPrediction);
printf("Algorithm took: %f (ms)\n", resultTime);
double accuracy = showAccuracy(training, predictions, rowsTraining, columns);
printf("Accuracy: %f\n", accuracy);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12runAlgorithmPdS_S_iii
.globl _Z12runAlgorithmPdS_S_iii
.p2align 8
.type _Z12runAlgorithmPdS_S_iii,@function
_Z12runAlgorithmPdS_S_iii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b32 s5, s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mul_i32 s11, s10, s5
s_mov_b32 s5, exec_lo
v_cmpx_gt_i32_e64 s11, v1
s_cbranch_execz .LBB0_11
s_clause 0x1
s_load_b32 s7, s[0:1], 0x1c
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s17, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v0, 0
s_mov_b32 s5, 0
s_mov_b32 s6, -1
s_mov_b32 s19, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s12, s10, s7
s_add_u32 s13, s8, -8
s_addc_u32 s14, s9, -1
s_cmp_gt_i32 s12, 0
s_mul_i32 s17, s17, s4
s_cselect_b32 s15, -1, 0
s_add_i32 s16, s10, -1
s_mov_b32 s7, 0x7fefffff
s_cmp_lg_u32 s16, 0
s_mov_b32 s8, s5
s_cselect_b32 s18, -1, 0
s_branch .LBB0_3
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cvt_f64_i32_e32 v[2:3], v6
v_add_nc_u32_e32 v1, s17, v1
s_mov_b32 s9, s5
s_lshl_b64 s[20:21], s[8:9], 3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s11, v1
s_add_u32 s20, s0, s20
s_addc_u32 s21, s1, s21
s_add_i32 s8, s8, 1
s_or_b32 s19, vcc_lo, s19
global_store_b64 v0, v[2:3], s[20:21]
s_and_not1_b32 exec_lo, exec_lo, s19
s_cbranch_execz .LBB0_11
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_2
v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
s_mov_b32 s9, 0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s9, s9, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s9, s12
s_cbranch_scc1 .LBB0_2
.LBB0_6:
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_and_not1_b32 vcc_lo, exec_lo, s18
s_cbranch_vccnz .LBB0_9
s_mov_b32 s20, 0
.p2align 6
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, s20, v1
s_add_i32 s4, s9, s20
s_lshl_b64 s[22:23], s[4:5], 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_add_u32 s22, s2, s22
s_addc_u32 s23, s3, s23
s_add_i32 s20, s20, 1
s_cmp_lg_u32 s16, s20
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_clause 0x1
global_load_b64 v[7:8], v[7:8], off
global_load_b64 v[9:10], v0, s[22:23]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[7:8], -v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[4:5], v[7:8], v[7:8], v[4:5]
s_cbranch_scc1 .LBB0_8
.LBB0_9:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[4:5]
s_mov_b32 s4, exec_lo
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_lshlrev_b32_e32 v7, 8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v7
v_rsq_f64_e32 v[7:8], v[4:5]
s_waitcnt_depctr 0xfff
v_mul_f64 v[9:10], v[4:5], v[7:8]
v_mul_f64 v[7:8], v[7:8], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 0.5
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[7:8], v[7:8], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[9:10], v[9:10], v[4:5]
v_fma_f64 v[9:10], v[11:12], v[7:8], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[9:10], v[9:10], v[4:5]
v_fma_f64 v[7:8], v[11:12], v[7:8], v[9:10]
v_cndmask_b32_e64 v9, 0, 0xffffff80, vcc_lo
v_cmp_class_f64_e64 vcc_lo, v[4:5], 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[7:8], v[7:8], v9
v_dual_cndmask_b32 v5, v8, v5 :: v_dual_cndmask_b32 v4, v7, v4
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_f64_e32 v[4:5], v[2:3]
s_cbranch_execz .LBB0_5
s_add_i32 s20, s9, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s21, s20, 31
s_lshl_b64 s[20:21], s[20:21], 3
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s20, s13, s20
s_addc_u32 s21, s14, s21
global_load_b64 v[2:3], v0, s[20:21]
s_waitcnt vmcnt(0)
v_cvt_i32_f64_e32 v6, v[2:3]
v_dual_mov_b32 v2, v4 :: v_dual_mov_b32 v3, v5
s_branch .LBB0_5
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12runAlgorithmPdS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12runAlgorithmPdS_S_iii, .Lfunc_end0-_Z12runAlgorithmPdS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12runAlgorithmPdS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z12runAlgorithmPdS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <sys/time.h>
timeval StartingTime;
void setTime(){
gettimeofday( &StartingTime, NULL );
}
double getTime(){
timeval PausingTime, ElapsedTime;
gettimeofday( &PausingTime, NULL );
timersub(&PausingTime, &StartingTime, &ElapsedTime);
return ElapsedTime.tv_sec*1000.0+ElapsedTime.tv_usec/1000.0; // Returning in milliseconds.
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <sys/time.h>
timeval StartingTime;
void setTime(){
gettimeofday( &StartingTime, NULL );
}
double getTime(){
timeval PausingTime, ElapsedTime;
gettimeofday( &PausingTime, NULL );
timersub(&PausingTime, &StartingTime, &ElapsedTime);
return ElapsedTime.tv_sec*1000.0+ElapsedTime.tv_usec/1000.0; // Returning in milliseconds.
} | .file "tmpxft_001600f6_00000000-6_simpleTime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7setTimev
.type _Z7setTimev, @function
_Z7setTimev:
.LFB2027:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq StartingTime(%rip), %rdi
call gettimeofday@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z7setTimev, .-_Z7setTimev
.globl _Z7getTimev
.type _Z7getTimev, @function
_Z7getTimev:
.LFB2028:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movq (%rsp), %rdx
subq StartingTime(%rip), %rdx
movq 8(%rsp), %rax
subq 8+StartingTime(%rip), %rax
js .L9
.L6:
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
movsd .LC0(%rip), %xmm2
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd %xmm2, %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
subq $1, %rdx
addq $1000000, %rax
jmp .L6
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size _Z7getTimev, .-_Z7getTimev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl StartingTime
.bss
.align 16
.type StartingTime, @object
.size StartingTime, 16
StartingTime:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <sys/time.h>
timeval StartingTime;
void setTime(){
gettimeofday( &StartingTime, NULL );
}
double getTime(){
timeval PausingTime, ElapsedTime;
gettimeofday( &PausingTime, NULL );
timersub(&PausingTime, &StartingTime, &ElapsedTime);
return ElapsedTime.tv_sec*1000.0+ElapsedTime.tv_usec/1000.0; // Returning in milliseconds.
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
timeval StartingTime;
void setTime(){
gettimeofday( &StartingTime, NULL );
}
double getTime(){
timeval PausingTime, ElapsedTime;
gettimeofday( &PausingTime, NULL );
timersub(&PausingTime, &StartingTime, &ElapsedTime);
return ElapsedTime.tv_sec*1000.0+ElapsedTime.tv_usec/1000.0; // Returning in milliseconds.
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
timeval StartingTime;
void setTime(){
gettimeofday( &StartingTime, NULL );
}
double getTime(){
timeval PausingTime, ElapsedTime;
gettimeofday( &PausingTime, NULL );
timersub(&PausingTime, &StartingTime, &ElapsedTime);
return ElapsedTime.tv_sec*1000.0+ElapsedTime.tv_usec/1000.0; // Returning in milliseconds.
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
timeval StartingTime;
void setTime(){
gettimeofday( &StartingTime, NULL );
}
double getTime(){
timeval PausingTime, ElapsedTime;
gettimeofday( &PausingTime, NULL );
timersub(&PausingTime, &StartingTime, &ElapsedTime);
return ElapsedTime.tv_sec*1000.0+ElapsedTime.tv_usec/1000.0; // Returning in milliseconds.
} | .text
.file "simpleTime.hip"
.globl _Z7setTimev # -- Begin function _Z7setTimev
.p2align 4, 0x90
.type _Z7setTimev,@function
_Z7setTimev: # @_Z7setTimev
.cfi_startproc
# %bb.0:
movl $StartingTime, %edi
xorl %esi, %esi
jmp gettimeofday # TAILCALL
.Lfunc_end0:
.size _Z7setTimev, .Lfunc_end0-_Z7setTimev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7getTimev
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z7getTimev
.p2align 4, 0x90
.type _Z7getTimev,@function
_Z7getTimev: # @_Z7getTimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq StartingTime(%rip), %rax
subq StartingTime+8(%rip), %rcx
leaq 1000000(%rcx), %rdx
testq %rcx, %rcx
cmovnsq %rcx, %rdx
sarq $63, %rcx
addq %rax, %rcx
cvtsi2sd %rcx, %xmm1
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
cvtsi2sd %rdx, %xmm0
mulsd %xmm2, %xmm1
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7getTimev, .Lfunc_end1-_Z7getTimev
.cfi_endproc
# -- End function
.type StartingTime,@object # @StartingTime
.bss
.globl StartingTime
.p2align 3, 0x0
StartingTime:
.zero 16
.size StartingTime, 16
.type __hip_cuid_,@object # @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym StartingTime
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001600f6_00000000-6_simpleTime.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7setTimev
.type _Z7setTimev, @function
_Z7setTimev:
.LFB2027:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq StartingTime(%rip), %rdi
call gettimeofday@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size _Z7setTimev, .-_Z7setTimev
.globl _Z7getTimev
.type _Z7getTimev, @function
_Z7getTimev:
.LFB2028:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
movq (%rsp), %rdx
subq StartingTime(%rip), %rdx
movq 8(%rsp), %rax
subq 8+StartingTime(%rip), %rax
js .L9
.L6:
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
movsd .LC0(%rip), %xmm2
mulsd %xmm2, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
divsd %xmm2, %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
subq $1, %rdx
addq $1000000, %rax
jmp .L6
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size _Z7getTimev, .-_Z7getTimev
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl StartingTime
.bss
.align 16
.type StartingTime, @object
.size StartingTime, 16
StartingTime:
.zero 16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simpleTime.hip"
.globl _Z7setTimev # -- Begin function _Z7setTimev
.p2align 4, 0x90
.type _Z7setTimev,@function
_Z7setTimev: # @_Z7setTimev
.cfi_startproc
# %bb.0:
movl $StartingTime, %edi
xorl %esi, %esi
jmp gettimeofday # TAILCALL
.Lfunc_end0:
.size _Z7setTimev, .Lfunc_end0-_Z7setTimev
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7getTimev
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl _Z7getTimev
.p2align 4, 0x90
.type _Z7getTimev,@function
_Z7getTimev: # @_Z7getTimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
subq StartingTime(%rip), %rax
subq StartingTime+8(%rip), %rcx
leaq 1000000(%rcx), %rdx
testq %rcx, %rcx
cmovnsq %rcx, %rdx
sarq $63, %rcx
addq %rax, %rcx
cvtsi2sd %rcx, %xmm1
movsd .LCPI1_0(%rip), %xmm2 # xmm2 = mem[0],zero
cvtsi2sd %rdx, %xmm0
mulsd %xmm2, %xmm1
divsd %xmm2, %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z7getTimev, .Lfunc_end1-_Z7getTimev
.cfi_endproc
# -- End function
.type StartingTime,@object # @StartingTime
.bss
.globl StartingTime
.p2align 3, 0x0
StartingTime:
.zero 16
.size StartingTime, 16
.type __hip_cuid_,@object # @__hip_cuid_
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym StartingTime
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double seconds() {
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
int total_size = 1024 * 1024; // 1MB
void test(int size) {
double iStart, iElaps;
int num = total_size / size;
float *d[num];
iStart = seconds();
for (int i = 0; i < num; i++) {
cudaMalloc((float **)&d[i], size);
}
iElaps = seconds() - iStart;
printf("cudaMalloc(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
iStart = seconds();
for (int i = 0; i < num; i++) {
cudaFree(d[i]);
}
iElaps = seconds() - iStart;
printf("cudaFree(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
}
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d: %s\n", dev, deviceProp.name);
cudaSetDevice(dev);
int size = atoi(argv[1]);
test(size);
return (0);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double seconds() {
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
int total_size = 1024 * 1024; // 1MB
void test(int size) {
double iStart, iElaps;
int num = total_size / size;
float *d[num];
iStart = seconds();
for (int i = 0; i < num; i++) {
cudaMalloc((float **)&d[i], size);
}
iElaps = seconds() - iStart;
printf("cudaMalloc(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
iStart = seconds();
for (int i = 0; i < num; i++) {
cudaFree(d[i]);
}
iElaps = seconds() - iStart;
printf("cudaFree(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
}
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d: %s\n", dev, deviceProp.name);
cudaSetDevice(dev);
int size = atoi(argv[1]);
test(size);
return (0);
} | .file "tmpxft_0004d951_00000000-6_cudaMallocBenchmark.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaMalloc(%d) x %d Time elapsed %f sec\n"
.align 8
.LC2:
.string "cudaFree(%d) x %d Time elapsed %f sec\n"
.text
.globl _Z4testi
.type _Z4testi, @function
_Z4testi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -100(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl total_size(%rip), %eax
cltd
idivl %edi
movl %eax, %r14d
movslq %eax, %r15
salq $3, %r15
leaq 15(%r15), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L4:
cmpq %rdx, %rsp
je .L5
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L4
.L5:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L6
orq $0, -8(%rsp,%rax)
.L6:
movq %rsp, %rbx
movq %rbx, -120(%rbp)
leaq -88(%rbp), %rsi
leaq -80(%rbp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq -72(%rbp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -80(%rbp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, -112(%rbp)
testl %r14d, %r14d
jle .L7
leaq (%rbx,%r15), %r13
movslq -100(%rbp), %r12
.L8:
movq %r12, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
addq $8, %rbx
cmpq %r13, %rbx
jne .L8
.L7:
leaq -88(%rbp), %rbx
leaq -80(%rbp), %r12
movq %rbx, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq -72(%rbp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -80(%rbp), %xmm1
addsd %xmm1, %xmm0
subsd -112(%rbp), %xmm0
movl %r14d, %ecx
movl -100(%rbp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq -72(%rbp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -80(%rbp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, -112(%rbp)
testl %r14d, %r14d
jle .L9
movq -120(%rbp), %rax
movq %rax, %rbx
addq %r15, %rax
movq %rax, %r15
.L10:
movq (%rbx), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq %r15, %rbx
jne .L10
.L9:
leaq -88(%rbp), %rsi
leaq -80(%rbp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq -72(%rbp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -80(%rbp), %xmm1
addsd %xmm1, %xmm0
subsd -112(%rbp), %xmm0
movl %r14d, %ecx
movl -100(%rbp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L15
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z4testi, .-_Z4testi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%s Starting...\n"
.LC4:
.string "Using Device %d: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rbp
movl $0, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rcx
movl $0, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call _Z4testi
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl total_size
.data
.align 4
.type total_size, @object
.size total_size, 4
total_size:
.long 1048576
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double seconds() {
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
int total_size = 1024 * 1024; // 1MB
void test(int size) {
double iStart, iElaps;
int num = total_size / size;
float *d[num];
iStart = seconds();
for (int i = 0; i < num; i++) {
cudaMalloc((float **)&d[i], size);
}
iElaps = seconds() - iStart;
printf("cudaMalloc(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
iStart = seconds();
for (int i = 0; i < num; i++) {
cudaFree(d[i]);
}
iElaps = seconds() - iStart;
printf("cudaFree(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
}
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
// set up device
int dev = 0;
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d: %s\n", dev, deviceProp.name);
cudaSetDevice(dev);
int size = atoi(argv[1]);
test(size);
return (0);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double seconds() {
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
int total_size = 1024 * 1024; // 1MB
void test(int size) {
double iStart, iElaps;
int num = total_size / size;
float *d[num];
iStart = seconds();
for (int i = 0; i < num; i++) {
hipMalloc((float **)&d[i], size);
}
iElaps = seconds() - iStart;
printf("cudaMalloc(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
iStart = seconds();
for (int i = 0; i < num; i++) {
hipFree(d[i]);
}
iElaps = seconds() - iStart;
printf("cudaFree(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
}
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d: %s\n", dev, deviceProp.name);
hipSetDevice(dev);
int size = atoi(argv[1]);
test(size);
return (0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double seconds() {
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
int total_size = 1024 * 1024; // 1MB
void test(int size) {
double iStart, iElaps;
int num = total_size / size;
float *d[num];
iStart = seconds();
for (int i = 0; i < num; i++) {
hipMalloc((float **)&d[i], size);
}
iElaps = seconds() - iStart;
printf("cudaMalloc(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
iStart = seconds();
for (int i = 0; i < num; i++) {
hipFree(d[i]);
}
iElaps = seconds() - iStart;
printf("cudaFree(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
}
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d: %s\n", dev, deviceProp.name);
hipSetDevice(dev);
int size = atoi(argv[1]);
test(size);
return (0);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
inline double seconds() {
struct timeval tp;
struct timezone tzp;
int i = gettimeofday(&tp, &tzp);
return ((double)tp.tv_sec + (double)tp.tv_usec * 1.e-6);
}
int total_size = 1024 * 1024; // 1MB
void test(int size) {
double iStart, iElaps;
int num = total_size / size;
float *d[num];
iStart = seconds();
for (int i = 0; i < num; i++) {
hipMalloc((float **)&d[i], size);
}
iElaps = seconds() - iStart;
printf("cudaMalloc(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
iStart = seconds();
for (int i = 0; i < num; i++) {
hipFree(d[i]);
}
iElaps = seconds() - iStart;
printf("cudaFree(%d) x %d Time elapsed %f sec\n", size, num, iElaps);
}
int main(int argc, char **argv) {
printf("%s Starting...\n", argv[0]);
// set up device
int dev = 0;
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
printf("Using Device %d: %s\n", dev, deviceProp.name);
hipSetDevice(dev);
int size = atoi(argv[1]);
test(size);
return (0);
} | .text
.file "cudaMallocBenchmark.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4testi
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z4testi
.p2align 4, 0x90
.type _Z4testi,@function
_Z4testi: # @_Z4testi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl total_size(%rip), %eax
cltd
movl %edi, -44(%rbp) # 4-byte Spill
idivl %edi
movl %eax, %ebx
leaq 15(,%rbx,8), %rax
andq $-16, %rax
movq %rsp, %r13
subq %rax, %r13
movq %r13, %rsp
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
callq gettimeofday
cvtsi2sdq -64(%rbp), %xmm0
cvtsi2sdq -56(%rbp), %xmm1
mulsd .LCPI0_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, -72(%rbp) # 8-byte Spill
movl %ebx, %r14d
movq %rbx, -88(%rbp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB0_3
# %bb.1: # %.lr.ph
movslq -44(%rbp), %r15 # 4-byte Folded Reload
movq %r14, %rbx
movq %r13, %r12
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movq %r15, %rsi
callq hipMalloc
addq $8, %r12
decq %rbx
jne .LBB0_2
.LBB0_3: # %._crit_edge
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq -64(%rbp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq -56(%rbp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd -72(%rbp), %xmm0 # 8-byte Folded Reload
movl $.L.str, %edi
movl -44(%rbp), %esi # 4-byte Reload
movq -88(%rbp), %rbx # 8-byte Reload
movl %ebx, %edx
movb $1, %al
callq printf
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
callq gettimeofday
movq -64(%rbp), %r15
movq -56(%rbp), %r12
testl %ebx, %ebx
jle .LBB0_6
# %bb.4: # %.lr.ph24.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # %.lr.ph24
# =>This Inner Loop Header: Depth=1
movq (%r13,%rbx,8), %rdi
callq hipFree
incq %rbx
cmpq %rbx, %r14
jne .LBB0_5
.LBB0_6: # %._crit_edge25
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, -72(%rbp) # 8-byte Spill
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq -64(%rbp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq -56(%rbp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd -72(%rbp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movl -44(%rbp), %esi # 4-byte Reload
movq -88(%rbp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movb $1, %al
callq printf
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size _Z4testi, .Lfunc_end0-_Z4testi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq (%rsi), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %r14
movq %r14, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.3, %edi
xorl %esi, %esi
movq %r14, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq _Z4testi
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type total_size,@object # @total_size
.data
.globl total_size
.p2align 2, 0x0
total_size:
.long 1048576 # 0x100000
.size total_size, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaMalloc(%d) x %d Time elapsed %f sec\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaFree(%d) x %d Time elapsed %f sec\n"
.size .L.str.1, 39
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s Starting...\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Using Device %d: %s\n"
.size .L.str.3, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d951_00000000-6_cudaMallocBenchmark.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cudaMalloc(%d) x %d Time elapsed %f sec\n"
.align 8
.LC2:
.string "cudaFree(%d) x %d Time elapsed %f sec\n"
.text
.globl _Z4testi
.type _Z4testi, @function
_Z4testi:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 15, -24
.cfi_offset 14, -32
.cfi_offset 13, -40
.cfi_offset 12, -48
.cfi_offset 3, -56
movl %edi, -100(%rbp)
movq %fs:40, %rax
movq %rax, -56(%rbp)
xorl %eax, %eax
movl total_size(%rip), %eax
cltd
idivl %edi
movl %eax, %r14d
movslq %eax, %r15
salq $3, %r15
leaq 15(%r15), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L4:
cmpq %rdx, %rsp
je .L5
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L4
.L5:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L6
orq $0, -8(%rsp,%rax)
.L6:
movq %rsp, %rbx
movq %rbx, -120(%rbp)
leaq -88(%rbp), %rsi
leaq -80(%rbp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq -72(%rbp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -80(%rbp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, -112(%rbp)
testl %r14d, %r14d
jle .L7
leaq (%rbx,%r15), %r13
movslq -100(%rbp), %r12
.L8:
movq %r12, %rsi
movq %rbx, %rdi
call cudaMalloc@PLT
addq $8, %rbx
cmpq %r13, %rbx
jne .L8
.L7:
leaq -88(%rbp), %rbx
leaq -80(%rbp), %r12
movq %rbx, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq -72(%rbp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -80(%rbp), %xmm1
addsd %xmm1, %xmm0
subsd -112(%rbp), %xmm0
movl %r14d, %ecx
movl -100(%rbp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movq %r12, %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq -72(%rbp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -80(%rbp), %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, -112(%rbp)
testl %r14d, %r14d
jle .L9
movq -120(%rbp), %rax
movq %rax, %rbx
addq %r15, %rax
movq %rax, %r15
.L10:
movq (%rbx), %rdi
call cudaFree@PLT
addq $8, %rbx
cmpq %r15, %rbx
jne .L10
.L9:
leaq -88(%rbp), %rsi
leaq -80(%rbp), %rdi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq -72(%rbp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq -80(%rbp), %xmm1
addsd %xmm1, %xmm0
subsd -112(%rbp), %xmm0
movl %r14d, %ecx
movl -100(%rbp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -56(%rbp), %rax
subq %fs:40, %rax
jne .L15
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z4testi, .-_Z4testi
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%s Starting...\n"
.LC4:
.string "Using Device %d: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1048, %rsp
.cfi_def_cfa_offset 1072
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq (%rsi), %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rbp
movl $0, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbp, %rcx
movl $0, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edi
call _Z4testi
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $1048, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl total_size
.data
.align 4
.type total_size, @object
.size total_size, 4
total_size:
.long 1048576
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaMallocBenchmark.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z4testi
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z4testi
.p2align 4, 0x90
.type _Z4testi,@function
_Z4testi: # @_Z4testi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $56, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl total_size(%rip), %eax
cltd
movl %edi, -44(%rbp) # 4-byte Spill
idivl %edi
movl %eax, %ebx
leaq 15(,%rbx,8), %rax
andq $-16, %rax
movq %rsp, %r13
subq %rax, %r13
movq %r13, %rsp
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
callq gettimeofday
cvtsi2sdq -64(%rbp), %xmm0
cvtsi2sdq -56(%rbp), %xmm1
mulsd .LCPI0_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, -72(%rbp) # 8-byte Spill
movl %ebx, %r14d
movq %rbx, -88(%rbp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB0_3
# %bb.1: # %.lr.ph
movslq -44(%rbp), %r15 # 4-byte Folded Reload
movq %r14, %rbx
movq %r13, %r12
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movq %r15, %rsi
callq hipMalloc
addq $8, %r12
decq %rbx
jne .LBB0_2
.LBB0_3: # %._crit_edge
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq -64(%rbp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq -56(%rbp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd -72(%rbp), %xmm0 # 8-byte Folded Reload
movl $.L.str, %edi
movl -44(%rbp), %esi # 4-byte Reload
movq -88(%rbp), %rbx # 8-byte Reload
movl %ebx, %edx
movb $1, %al
callq printf
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
callq gettimeofday
movq -64(%rbp), %r15
movq -56(%rbp), %r12
testl %ebx, %ebx
jle .LBB0_6
# %bb.4: # %.lr.ph24.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # %.lr.ph24
# =>This Inner Loop Header: Depth=1
movq (%r13,%rbx,8), %rdi
callq hipFree
incq %rbx
cmpq %rbx, %r14
jne .LBB0_5
.LBB0_6: # %._crit_edge25
xorps %xmm0, %xmm0
cvtsi2sd %r12, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, -72(%rbp) # 8-byte Spill
leaq -64(%rbp), %rdi
leaq -80(%rbp), %rsi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq -64(%rbp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq -56(%rbp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd -72(%rbp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movl -44(%rbp), %esi # 4-byte Reload
movq -88(%rbp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movb $1, %al
callq printf
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.Lfunc_end0:
.size _Z4testi, .Lfunc_end0-_Z4testi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq (%rsi), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 8(%rsp), %r14
movq %r14, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.3, %edi
xorl %esi, %esi
movq %r14, %rdx
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq hipSetDevice
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, %edi
callq _Z4testi
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type total_size,@object # @total_size
.data
.globl total_size
.p2align 2, 0x0
total_size:
.long 1048576 # 0x100000
.size total_size, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "cudaMalloc(%d) x %d Time elapsed %f sec\n"
.size .L.str, 41
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "cudaFree(%d) x %d Time elapsed %f sec\n"
.size .L.str.1, 39
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s Starting...\n"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Using Device %d: %s\n"
.size .L.str.3, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 32
//Código device
__global__ void soma_vetor(int *a, int *b, int *c){
int indice = blockIdx.x;
if(indice < N)
c[indice] = a[indice] + b[indice];
}
//Código host
int main(){
int a[N],b[N],c[N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
cudaMalloc((void**)&dev_a, tam);
cudaMalloc((void**)&dev_b, tam);
cudaMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
cudaMemcpy(dev_a, &a, tam, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, &b, tam, cudaMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
soma_vetor<<<N,1>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
cudaMemcpy(&c, dev_c, tam, cudaMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++)
printf("%d ",c[i]);
printf("\n\n");
//Liberando a memória na GPU:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z10soma_vetorPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x1f, PT ; /* 0x0000001f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 32
//Código device
__global__ void soma_vetor(int *a, int *b, int *c){
int indice = blockIdx.x;
if(indice < N)
c[indice] = a[indice] + b[indice];
}
//Código host
int main(){
int a[N],b[N],c[N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
cudaMalloc((void**)&dev_a, tam);
cudaMalloc((void**)&dev_b, tam);
cudaMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
cudaMemcpy(dev_a, &a, tam, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, &b, tam, cudaMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
soma_vetor<<<N,1>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
cudaMemcpy(&c, dev_c, tam, cudaMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++)
printf("%d ",c[i]);
printf("\n\n");
//Liberando a memória na GPU:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_000f42a4_00000000-6_soma_vetor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_
.type _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_, @function
_Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10soma_vetorPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_, .-_Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_
.globl _Z10soma_vetorPiS_S_
.type _Z10soma_vetorPiS_S_, @function
_Z10soma_vetorPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10soma_vetorPiS_S_, .-_Z10soma_vetorPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $448, %rsp
.cfi_def_cfa_offset 480
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 176(%rsp,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L12
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 304(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 432(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $448, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10soma_vetorPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10soma_vetorPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 32
//Código device
__global__ void soma_vetor(int *a, int *b, int *c){
int indice = blockIdx.x;
if(indice < N)
c[indice] = a[indice] + b[indice];
}
//Código host
int main(){
int a[N],b[N],c[N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
cudaMalloc((void**)&dev_a, tam);
cudaMalloc((void**)&dev_b, tam);
cudaMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
cudaMemcpy(dev_a, &a, tam, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, &b, tam, cudaMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
soma_vetor<<<N,1>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
cudaMemcpy(&c, dev_c, tam, cudaMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++)
printf("%d ",c[i]);
printf("\n\n");
//Liberando a memória na GPU:
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 32
//Código device
__global__ void soma_vetor(int *a, int *b, int *c){
int indice = blockIdx.x;
if(indice < N)
c[indice] = a[indice] + b[indice];
}
//Código host
int main(){
int a[N],b[N],c[N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
hipMalloc((void**)&dev_a, tam);
hipMalloc((void**)&dev_b, tam);
hipMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
hipMemcpy(dev_a, &a, tam, hipMemcpyHostToDevice);
hipMemcpy(dev_b, &b, tam, hipMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
soma_vetor<<<N,1>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
hipMemcpy(&c, dev_c, tam, hipMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++)
printf("%d ",c[i]);
printf("\n\n");
//Liberando a memória na GPU:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 32
//Código device
__global__ void soma_vetor(int *a, int *b, int *c){
int indice = blockIdx.x;
if(indice < N)
c[indice] = a[indice] + b[indice];
}
//Código host
int main(){
int a[N],b[N],c[N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
hipMalloc((void**)&dev_a, tam);
hipMalloc((void**)&dev_b, tam);
hipMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
hipMemcpy(dev_a, &a, tam, hipMemcpyHostToDevice);
hipMemcpy(dev_b, &b, tam, hipMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
soma_vetor<<<N,1>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
hipMemcpy(&c, dev_c, tam, hipMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++)
printf("%d ",c[i]);
printf("\n\n");
//Liberando a memória na GPU:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10soma_vetorPiS_S_
.globl _Z10soma_vetorPiS_S_
.p2align 8
.type _Z10soma_vetorPiS_S_,@function
_Z10soma_vetorPiS_S_:
s_cmp_gt_i32 s15, 31
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10soma_vetorPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10soma_vetorPiS_S_, .Lfunc_end0-_Z10soma_vetorPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10soma_vetorPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10soma_vetorPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 32
//Código device
__global__ void soma_vetor(int *a, int *b, int *c){
int indice = blockIdx.x;
if(indice < N)
c[indice] = a[indice] + b[indice];
}
//Código host
int main(){
int a[N],b[N],c[N];
int* dev_a;
int* dev_b;
int* dev_c;
int tam = N*sizeof(int);
//Inicializando as variáveis do host:
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i*2;
}
//Alocando espaço para as variáveis da GPU:
hipMalloc((void**)&dev_a, tam);
hipMalloc((void**)&dev_b, tam);
hipMalloc((void**)&dev_c, tam);
//Copiando as variáveis da CPU para a GPU:
hipMemcpy(dev_a, &a, tam, hipMemcpyHostToDevice);
hipMemcpy(dev_b, &b, tam, hipMemcpyHostToDevice);
//Chamada à função da GPU (kernel):
soma_vetor<<<N,1>>>(dev_a, dev_b, dev_c);
//Copiando o resultado da GPU para a CPU:
hipMemcpy(&c, dev_c, tam, hipMemcpyDeviceToHost);
//Visualizando o resultado:
for(int i = 0; i < N; i++)
printf("%d ",c[i]);
printf("\n\n");
//Liberando a memória na GPU:
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.file "soma_vetor.hip"
.globl _Z25__device_stub__soma_vetorPiS_S_ # -- Begin function _Z25__device_stub__soma_vetorPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__soma_vetorPiS_S_,@function
_Z25__device_stub__soma_vetorPiS_S_: # @_Z25__device_stub__soma_vetorPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10soma_vetorPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__soma_vetorPiS_S_, .Lfunc_end0-_Z25__device_stub__soma_vetorPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $480, %rsp # imm = 0x1E0
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 352(%rsp,%rcx,4)
movl %eax, 224(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $32, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 352(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 31(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10soma_vetorPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB1_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $480, %rsp # imm = 0x1E0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10soma_vetorPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10soma_vetorPiS_S_,@object # @_Z10soma_vetorPiS_S_
.section .rodata,"a",@progbits
.globl _Z10soma_vetorPiS_S_
.p2align 3, 0x0
_Z10soma_vetorPiS_S_:
.quad _Z25__device_stub__soma_vetorPiS_S_
.size _Z10soma_vetorPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10soma_vetorPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__soma_vetorPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10soma_vetorPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10soma_vetorPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R6, 0x1f, PT ; /* 0x0000001f0600780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00b0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00c0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10soma_vetorPiS_S_
.globl _Z10soma_vetorPiS_S_
.p2align 8
.type _Z10soma_vetorPiS_S_,@function
_Z10soma_vetorPiS_S_:
s_cmp_gt_i32 s15, 31
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s4, s2
s_addc_u32 s5, s5, s3
s_add_u32 s6, s6, s2
s_addc_u32 s7, s7, s3
s_load_b32 s4, s[4:5], 0x0
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10soma_vetorPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10soma_vetorPiS_S_, .Lfunc_end0-_Z10soma_vetorPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10soma_vetorPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10soma_vetorPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f42a4_00000000-6_soma_vetor.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_
.type _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_, @function
_Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10soma_vetorPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_, .-_Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_
.globl _Z10soma_vetorPiS_S_
.type _Z10soma_vetorPiS_S_, @function
_Z10soma_vetorPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10soma_vetorPiS_S_, .-_Z10soma_vetorPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d "
.LC1:
.string "\n\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $448, %rsp
.cfi_def_cfa_offset 480
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
.L12:
movl %eax, 48(%rsp,%rax,4)
leal (%rax,%rax), %edx
movl %edx, 176(%rsp,%rax,4)
addq $1, %rax
cmpq $32, %rax
jne .L12
movq %rsp, %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 176(%rsp), %rsi
movl $1, %ecx
movl $128, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $32, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 304(%rsp), %rbx
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 432(%rsp), %r12
leaq .LC0(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $448, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z34__device_stub__Z10soma_vetorPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10soma_vetorPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10soma_vetorPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "soma_vetor.hip"
.globl _Z25__device_stub__soma_vetorPiS_S_ # -- Begin function _Z25__device_stub__soma_vetorPiS_S_
.p2align 4, 0x90
.type _Z25__device_stub__soma_vetorPiS_S_,@function
_Z25__device_stub__soma_vetorPiS_S_: # @_Z25__device_stub__soma_vetorPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10soma_vetorPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__soma_vetorPiS_S_, .Lfunc_end0-_Z25__device_stub__soma_vetorPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $480, %rsp # imm = 0x1E0
.cfi_def_cfa_offset 496
.cfi_offset %rbx, -16
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ecx, 352(%rsp,%rcx,4)
movl %eax, 224(%rsp,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $32, %rcx
jne .LBB1_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 352(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 224(%rsp), %rsi
movl $128, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 31(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10soma_vetorPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $128, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $32, %rbx
jne .LBB1_5
# %bb.6:
movl $.Lstr, %edi
callq puts@PLT
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $480, %rsp # imm = 0x1E0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10soma_vetorPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10soma_vetorPiS_S_,@object # @_Z10soma_vetorPiS_S_
.section .rodata,"a",@progbits
.globl _Z10soma_vetorPiS_S_
.p2align 3, 0x0
_Z10soma_vetorPiS_S_:
.quad _Z25__device_stub__soma_vetorPiS_S_
.size _Z10soma_vetorPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d "
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10soma_vetorPiS_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__soma_vetorPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10soma_vetorPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void set_kernel(const int n, const float alpha, float *y) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n);
i += blockDim.x * gridDim.x) {
y[i] = alpha;
}
} | code for sm_80
Function : _Z10set_kernelifPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fce0000000f00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xa0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void set_kernel(const int n, const float alpha, float *y) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n);
i += blockDim.x * gridDim.x) {
y[i] = alpha;
}
} | .file "tmpxft_00083c4e_00000000-6_set_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10set_kernelifPfifPf
.type _Z32__device_stub__Z10set_kernelifPfifPf, @function
_Z32__device_stub__Z10set_kernelifPfifPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10set_kernelifPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10set_kernelifPfifPf, .-_Z32__device_stub__Z10set_kernelifPfifPf
.globl _Z10set_kernelifPf
.type _Z10set_kernelifPf, @function
_Z10set_kernelifPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10set_kernelifPfifPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10set_kernelifPf, .-_Z10set_kernelifPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10set_kernelifPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10set_kernelifPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void set_kernel(const int n, const float alpha, float *y) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n);
i += blockDim.x * gridDim.x) {
y[i] = alpha;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_kernel(const int n, const float alpha, float *y) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n);
i += blockDim.x * gridDim.x) {
y[i] = alpha;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_kernel(const int n, const float alpha, float *y) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n);
i += blockDim.x * gridDim.x) {
y[i] = alpha;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10set_kernelifPf
.globl _Z10set_kernelifPf
.p2align 8
.type _Z10set_kernelifPf,@function
_Z10set_kernelifPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0x4
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s6
s_mul_i32 s1, s7, s5
s_mov_b32 s5, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10set_kernelifPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10set_kernelifPf, .Lfunc_end0-_Z10set_kernelifPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10set_kernelifPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10set_kernelifPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void set_kernel(const int n, const float alpha, float *y) {
for (int i = blockIdx.x * blockDim.x + threadIdx.x; i < (n);
i += blockDim.x * gridDim.x) {
y[i] = alpha;
}
} | .text
.file "set_kernel.hip"
.globl _Z25__device_stub__set_kernelifPf # -- Begin function _Z25__device_stub__set_kernelifPf
.p2align 4, 0x90
.type _Z25__device_stub__set_kernelifPf,@function
_Z25__device_stub__set_kernelifPf: # @_Z25__device_stub__set_kernelifPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movss %xmm0, (%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10set_kernelifPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__set_kernelifPf, .Lfunc_end0-_Z25__device_stub__set_kernelifPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10set_kernelifPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10set_kernelifPf,@object # @_Z10set_kernelifPf
.section .rodata,"a",@progbits
.globl _Z10set_kernelifPf
.p2align 3, 0x0
_Z10set_kernelifPf:
.quad _Z25__device_stub__set_kernelifPf
.size _Z10set_kernelifPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10set_kernelifPf"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__set_kernelifPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10set_kernelifPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10set_kernelifPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ MOV R7, c[0x0][0x164] ; /* 0x0000590000077a02 */
/* 0x000fe20000000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fce0000000f00 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00b0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xa0 ; /* 0xffffffb000008947 */
/* 0x001fea000383ffff */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10set_kernelifPf
.globl _Z10set_kernelifPf
.p2align 8
.type _Z10set_kernelifPf,@function
_Z10set_kernelifPf:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x0
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s5, v[0:1]
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_3
s_load_b32 s6, s[0:1], 0x4
s_load_b32 s7, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s6
s_mul_i32 s1, s7, s5
s_mov_b32 s5, 0
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_cmp_le_i32_e32 vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s2, v2
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s5, vcc_lo, s5
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10set_kernelifPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10set_kernelifPf, .Lfunc_end0-_Z10set_kernelifPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10set_kernelifPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10set_kernelifPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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