system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mmul(const float *A, const float *B, float *C, int ds) {
// declare cache in shared memory
__shared__ float As[block_size][block_size];
__shared__ float Bs[block_size][block_size];
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create thread x index
int idy = threadIdx.y+blockDim.y*blockIdx.y; // create thread y index
if ((idx < ds) && (idy < ds)){
float temp = 0;
for (int i = 0; i < ds/block_size; i++) {
// Load data into shared memory
As[threadIdx.y][threadIdx.x] = A[idy * ds + (i * block_size + threadIdx.x)];
Bs[threadIdx.y][threadIdx.x] = B[(i * block_size + threadIdx.y) * ds + idx];
// Synchronize
__syncthreads();
// Keep track of the running sum
for (int k = 0; k < block_size; k++)
temp += As[threadIdx.y][k] * Bs[k][threadIdx.x]; // dot product of row and column
__syncthreads();
}
// Write to global memory
C[idy*ds+idx] = temp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4mmulPKfS0_Pfi
.globl _Z4mmulPKfS0_Pfi
.p2align 8
.type _Z4mmulPKfS0_Pfi,@function
_Z4mmulPKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[0:1], null, s14, s4, v[6:7]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s2, 32
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v6
v_lshlrev_b32_e32 v7, 7, v3
s_ashr_i32 s3, s2, 31
s_mov_b32 s8, 0
s_lshr_b32 s3, s3, 27
v_or_b32_e32 v8, 0x1000, v2
v_mad_u64_u32 v[4:5], null, v1, s2, v[6:7]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v6, v8, v7
s_add_i32 s3, s2, s3
s_ashr_i32 s3, s3, 5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_lshl_b32 s9, s8, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v13, s9, v3
v_add_nc_u32_e32 v9, s9, v4
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v13, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v12, v10
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v5, v10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_4:
v_add_nc_u32_e32 v10, s9, v7
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 0x80, v9
s_cmpk_eq_i32 s9, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_4
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4mmulPKfS0_Pfi
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4mmulPKfS0_Pfi, .Lfunc_end0-_Z4mmulPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4mmulPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4mmulPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void mmul(const float *A, const float *B, float *C, int ds) {
// declare cache in shared memory
__shared__ float As[block_size][block_size];
__shared__ float Bs[block_size][block_size];
int idx = threadIdx.x+blockDim.x*blockIdx.x; // create thread x index
int idy = threadIdx.y+blockDim.y*blockIdx.y; // create thread y index
if ((idx < ds) && (idy < ds)){
float temp = 0;
for (int i = 0; i < ds/block_size; i++) {
// Load data into shared memory
As[threadIdx.y][threadIdx.x] = A[idy * ds + (i * block_size + threadIdx.x)];
Bs[threadIdx.y][threadIdx.x] = B[(i * block_size + threadIdx.y) * ds + idx];
// Synchronize
__syncthreads();
// Keep track of the running sum
for (int k = 0; k < block_size; k++)
temp += As[threadIdx.y][k] * Bs[k][threadIdx.x]; // dot product of row and column
__syncthreads();
}
// Write to global memory
C[idy*ds+idx] = temp;
}
} | .text
.file "mmul.hip"
.globl _Z19__device_stub__mmulPKfS0_Pfi # -- Begin function _Z19__device_stub__mmulPKfS0_Pfi
.p2align 4, 0x90
.type _Z19__device_stub__mmulPKfS0_Pfi,@function
_Z19__device_stub__mmulPKfS0_Pfi: # @_Z19__device_stub__mmulPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mmulPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__mmulPKfS0_Pfi, .Lfunc_end0-_Z19__device_stub__mmulPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mmulPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4mmulPKfS0_Pfi,@object # @_Z4mmulPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z4mmulPKfS0_Pfi
.p2align 3, 0x0
_Z4mmulPKfS0_Pfi:
.quad _Z19__device_stub__mmulPKfS0_Pfi
.size _Z4mmulPKfS0_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4mmulPKfS0_Pfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__mmulPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4mmulPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4mmulPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R16, SR_CTAID.Y ; /* 0x0000000000107919 */
/* 0x000e280000002600 */
/*0020*/ S2R R19, SR_TID.Y ; /* 0x0000000000137919 */
/* 0x000e280000002200 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R16, R16, c[0x0][0x4], R19 ; /* 0x0000010010107a24 */
/* 0x001fca00078e0213 */
/*0060*/ ISETP.GE.AND P0, PT, R16, c[0x0][0x178], PT ; /* 0x00005e0010007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R21, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff157435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R20, R16, c[0x0][0x178], R3 ; /* 0x00005e0010147a24 */
/* 0x000fe200078e0203 */
/*00d0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x20, PT ; /* 0x000000200200780c */
/* 0x000fe20003f06270 */
/*00f0*/ HFMA2.MMA R13, -RZ, RZ, 0, 0 ; /* 0x00000000ff0d7435 */
/* 0x000fcc00000001ff */
/*0100*/ IMAD.WIDE R20, R20, R21, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fcc00078e0215 */
/*0110*/ @!P0 BRA 0x710 ; /* 0x000005f000008947 */
/* 0x000fea0003800000 */
/*0120*/ SHF.R.S32.HI R4, RZ, 0x1f, R2 ; /* 0x0000001fff047819 */
/* 0x000fe20000011402 */
/*0130*/ IMAD R3, R19.reuse, c[0x0][0x178], R3 ; /* 0x00005e0013037a24 */
/* 0x040fe200078e0203 */
/*0140*/ SHF.L.U32 R19, R19, 0x7, RZ ; /* 0x0000000713137819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD R16, R16, c[0x0][0x178], R0 ; /* 0x00005e0010107a24 */
/* 0x000fe200078e0200 */
/*0160*/ LEA.HI R4, R4, c[0x0][0x178], RZ, 0x5 ; /* 0x00005e0004047a11 */
/* 0x000fe200078f28ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe40000000f00 */
/*0190*/ LEA R18, R0, R19, 0x2 ; /* 0x0000001300127211 */
/* 0x000fe400078e10ff */
/*01a0*/ SHF.R.S32.HI R17, RZ, 0x5, R4 ; /* 0x00000005ff117819 */
/* 0x000fc40000011404 */
/*01b0*/ MOV R14, 0x4 ; /* 0x00000004000e7802 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE.U32 R8, R16, R14, c[0x0][0x160] ; /* 0x0000580010087625 */
/* 0x000fc800078e000e */
/*01d0*/ IMAD.WIDE.U32 R14, R3, R14, c[0x0][0x168] ; /* 0x00005a00030e7625 */
/* 0x000fe200078e000e */
/*01e0*/ LDG.E R23, [R8.64] ; /* 0x0000000608177981 */
/* 0x000eaa000c1e1900 */
/*01f0*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000ee2000c1e1900 */
/*0200*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0210*/ IADD3 R16, R16, 0x20, RZ ; /* 0x0000002010107810 */
/* 0x000fe40007ffe0ff */
/*0220*/ LEA R3, R2, R3, 0x5 ; /* 0x0000000302037211 */
/* 0x000fc600078e28ff */
/*0230*/ ISETP.LE.AND P0, PT, R17, UR4, PT ; /* 0x0000000411007c0c */
/* 0x000fe2000bf03270 */
/*0240*/ STS [R18], R23 ; /* 0x0000001712007388 */
/* 0x004fe80000000800 */
/*0250*/ STS [R18+0x1000], R15 ; /* 0x0010000f12007388 */
/* 0x008fe80000000800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ LDS R12, [R0.X4+0x1000] ; /* 0x00100000000c7984 */
/* 0x000fe80000004800 */
/*0280*/ LDS.128 R4, [R19] ; /* 0x0000000013047984 */
/* 0x000e280000000c00 */
/*0290*/ LDS R28, [R0.X4+0x1080] ; /* 0x00108000001c7984 */
/* 0x000e680000004800 */
/*02a0*/ LDS R29, [R0.X4+0x1100] ; /* 0x00110000001d7984 */
/* 0x000ea80000004800 */
/*02b0*/ LDS R26, [R0.X4+0x1180] ; /* 0x00118000001a7984 */
/* 0x000ee80000004800 */
/*02c0*/ LDS R27, [R0.X4+0x1200] ; /* 0x00120000001b7984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.128 R8, [R19+0x10] ; /* 0x0000100013087984 */
/* 0x000f280000000c00 */
/*02e0*/ LDS R24, [R0.X4+0x1280] ; /* 0x0012800000187984 */
/* 0x000f680000004800 */
/*02f0*/ LDS R25, [R0.X4+0x1300] ; /* 0x0013000000197984 */
/* 0x000f680000004800 */
/*0300*/ LDS R22, [R0.X4+0x1380] ; /* 0x0013800000167984 */
/* 0x000f680000004800 */
/*0310*/ LDS R23, [R0.X4+0x1400] ; /* 0x0014000000177984 */
/* 0x000fe20000004800 */
/*0320*/ FFMA R4, R12, R4, R13 ; /* 0x000000040c047223 */
/* 0x001fc6000000000d */
/*0330*/ LDS.128 R12, [R19+0x20] ; /* 0x00002000130c7984 */
/* 0x000e220000000c00 */
/*0340*/ FFMA R5, R28, R5, R4 ; /* 0x000000051c057223 */
/* 0x002fc60000000004 */
/*0350*/ LDS R28, [R0.X4+0x1480] ; /* 0x00148000001c7984 */
/* 0x000e620000004800 */
/*0360*/ FFMA R5, R29, R6, R5 ; /* 0x000000061d057223 */
/* 0x004fc60000000005 */
/*0370*/ LDS R29, [R0.X4+0x1500] ; /* 0x00150000001d7984 */
/* 0x000ea20000004800 */
/*0380*/ FFMA R5, R26, R7, R5 ; /* 0x000000071a057223 */
/* 0x008fc60000000005 */
/*0390*/ LDS R26, [R0.X4+0x1680] ; /* 0x00168000001a7984 */
/* 0x000fe20000004800 */
/*03a0*/ FFMA R5, R27, R8, R5 ; /* 0x000000081b057223 */
/* 0x010fc60000000005 */
/*03b0*/ LDS R27, [R0.X4+0x1700] ; /* 0x00170000001b7984 */
/* 0x000fe20000004800 */
/*03c0*/ FFMA R5, R24, R9, R5 ; /* 0x0000000918057223 */
/* 0x020fc60000000005 */
/*03d0*/ LDS R24, [R0.X4+0x1580] ; /* 0x0015800000187984 */
/* 0x000ee20000004800 */
/*03e0*/ FFMA R10, R25, R10, R5 ; /* 0x0000000a190a7223 */
/* 0x000fc60000000005 */
/*03f0*/ LDS R25, [R0.X4+0x1600] ; /* 0x0016000000197984 */
/* 0x000fe20000004800 */
/*0400*/ FFMA R10, R22, R11, R10 ; /* 0x0000000b160a7223 */
/* 0x000fc6000000000a */
/*0410*/ LDS.128 R4, [R19+0x30] ; /* 0x0000300013047984 */
/* 0x000f280000000c00 */
/*0420*/ LDS R22, [R0.X4+0x1780] ; /* 0x0017800000167984 */
/* 0x000f620000004800 */
/*0430*/ FFMA R10, R23, R12, R10 ; /* 0x0000000c170a7223 */
/* 0x001fc6000000000a */
/*0440*/ LDS R23, [R0.X4+0x1800] ; /* 0x0018000000177984 */
/* 0x000fe20000004800 */
/*0450*/ FFMA R10, R28, R13, R10 ; /* 0x0000000d1c0a7223 */
/* 0x002fc6000000000a */
/*0460*/ LDS R28, [R0.X4+0x1a80] ; /* 0x001a8000001c7984 */
/* 0x000fe20000004800 */
/*0470*/ FFMA R14, R29, R14, R10 ; /* 0x0000000e1d0e7223 */
/* 0x004fc6000000000a */
/*0480*/ LDS.128 R8, [R19+0x40] ; /* 0x0000400013087984 */
/* 0x000e280000000c00 */
/*0490*/ LDS R29, [R0.X4+0x1900] ; /* 0x00190000001d7984 */
/* 0x000fe20000004800 */
/*04a0*/ FFMA R14, R24, R15, R14 ; /* 0x0000000f180e7223 */
/* 0x008fc6000000000e */
/*04b0*/ LDS R24, [R0.X4+0x1880] ; /* 0x0018800000187984 */
/* 0x000e620000004800 */
/*04c0*/ FFMA R4, R25, R4, R14 ; /* 0x0000000419047223 */
/* 0x010fc6000000000e */
/*04d0*/ LDS R25, [R0.X4+0x1a00] ; /* 0x001a000000197984 */
/* 0x000fe20000004800 */
/*04e0*/ FFMA R4, R26, R5, R4 ; /* 0x000000051a047223 */
/* 0x000fc60000000004 */
/*04f0*/ LDS R26, [R0.X4+0x1980] ; /* 0x00198000001a7984 */
/* 0x000ea20000004800 */
/*0500*/ FFMA R4, R27, R6, R4 ; /* 0x000000061b047223 */
/* 0x000fc60000000004 */
/*0510*/ LDS.128 R12, [R19+0x50] ; /* 0x00005000130c7984 */
/* 0x000ee20000000c00 */
/*0520*/ FFMA R4, R22, R7, R4 ; /* 0x0000000716047223 */
/* 0x020fc60000000004 */
/*0530*/ LDS R27, [R0.X4+0x1b00] ; /* 0x001b0000001b7984 */
/* 0x000f280000004800 */
/*0540*/ LDS R22, [R0.X4+0x1b80] ; /* 0x001b800000167984 */
/* 0x000f620000004800 */
/*0550*/ FFMA R4, R23, R8, R4 ; /* 0x0000000817047223 */
/* 0x001fc60000000004 */
/*0560*/ LDS R23, [R0.X4+0x1c00] ; /* 0x001c000000177984 */
/* 0x000fe20000004800 */
/*0570*/ FFMA R4, R24, R9, R4 ; /* 0x0000000918047223 */
/* 0x002fc60000000004 */
/*0580*/ LDS R24, [R0.X4+0x1c80] ; /* 0x001c800000187984 */
/* 0x000fe20000004800 */
/*0590*/ FFMA R10, R29, R10, R4 ; /* 0x0000000a1d0a7223 */
/* 0x000fc60000000004 */
/*05a0*/ LDS.128 R4, [R19+0x60] ; /* 0x0000600013047984 */
/* 0x000e220000000c00 */
/*05b0*/ FFMA R10, R26, R11, R10 ; /* 0x0000000b1a0a7223 */
/* 0x004fc8000000000a */
/*05c0*/ FFMA R10, R25, R12, R10 ; /* 0x0000000c190a7223 */
/* 0x008fe4000000000a */
/*05d0*/ LDS R25, [R0.X4+0x1d00] ; /* 0x001d000000197984 */
/* 0x000e640000004800 */
/*05e0*/ FFMA R10, R28, R13, R10 ; /* 0x0000000d1c0a7223 */
/* 0x000fe4000000000a */
/*05f0*/ LDS R12, [R0.X4+0x1d80] ; /* 0x001d8000000c7984 */
/* 0x000ea40000004800 */
/*0600*/ FFMA R14, R27, R14, R10 ; /* 0x0000000e1b0e7223 */
/* 0x010fe4000000000a */
/*0610*/ LDS R13, [R0.X4+0x1e00] ; /* 0x001e0000000d7984 */
/* 0x000fe40000004800 */
/*0620*/ FFMA R26, R22, R15, R14 ; /* 0x0000000f161a7223 */
/* 0x020fc4000000000e */
/*0630*/ LDS.128 R8, [R19+0x70] ; /* 0x0000700013087984 */
/* 0x000ee80000000c00 */
/*0640*/ LDS R22, [R0.X4+0x1e80] ; /* 0x001e800000167984 */
/* 0x000f280000004800 */
/*0650*/ LDS R15, [R0.X4+0x1f00] ; /* 0x001f0000000f7984 */
/* 0x000f680000004800 */
/*0660*/ LDS R14, [R0.X4+0x1f80] ; /* 0x001f8000000e7984 */
/* 0x000f620000004800 */
/*0670*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x001fc8000000001a */
/*0680*/ FFMA R4, R24, R5, R4 ; /* 0x0000000518047223 */
/* 0x000fc80000000004 */
/*0690*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x002fc80000000004 */
/*06a0*/ FFMA R4, R12, R7, R4 ; /* 0x000000070c047223 */
/* 0x004fc80000000004 */
/*06b0*/ FFMA R4, R13, R8, R4 ; /* 0x000000080d047223 */
/* 0x008fc80000000004 */
/*06c0*/ FFMA R4, R22, R9, R4 ; /* 0x0000000916047223 */
/* 0x010fc80000000004 */
/*06d0*/ FFMA R4, R15, R10, R4 ; /* 0x0000000a0f047223 */
/* 0x020fc80000000004 */
/*06e0*/ FFMA R13, R14, R11, R4 ; /* 0x0000000b0e0d7223 */
/* 0x000fe20000000004 */
/*06f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0700*/ @!P0 BRA 0x1b0 ; /* 0xfffffaa000008947 */
/* 0x000fea000383ffff */
/*0710*/ STG.E [R20.64], R13 ; /* 0x0000000d14007986 */
/* 0x000fe2000c101906 */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ BRA 0x730; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4mmulPKfS0_Pfi
.globl _Z4mmulPKfS0_Pfi
.p2align 8
.type _Z4mmulPKfS0_Pfi,@function
_Z4mmulPKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
v_mad_u64_u32 v[0:1], null, s14, s4, v[6:7]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v2, v0, v1
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
s_cmp_lt_i32 s2, 32
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v6
v_lshlrev_b32_e32 v7, 7, v3
s_ashr_i32 s3, s2, 31
s_mov_b32 s8, 0
s_lshr_b32 s3, s3, 27
v_or_b32_e32 v8, 0x1000, v2
v_mad_u64_u32 v[4:5], null, v1, s2, v[6:7]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v7, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v6, v8, v7
s_add_i32 s3, s2, s3
s_ashr_i32 s3, s3, 5
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_lshl_b32 s9, s8, 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v13, s9, v3
v_add_nc_u32_e32 v9, s9, v4
s_mov_b32 s9, 0
v_mad_u64_u32 v[11:12], null, v13, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mov_b32_e32 v12, v10
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[11:12], 2, v[11:12]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v5, v10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_4:
v_add_nc_u32_e32 v10, s9, v7
s_add_i32 s9, s9, 4
ds_load_b32 v11, v9
ds_load_b32 v10, v10
v_add_nc_u32_e32 v9, 0x80, v9
s_cmpk_eq_i32 s9, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v2, v10, v11
s_cbranch_scc0 .LBB0_4
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s3
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_3
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4mmulPKfS0_Pfi
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4mmulPKfS0_Pfi, .Lfunc_end0-_Z4mmulPKfS0_Pfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4mmulPKfS0_Pfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4mmulPKfS0_Pfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00177159_00000000-6_mmul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z4mmulPKfS0_PfiPKfS0_Pfi
.type _Z30__device_stub__Z4mmulPKfS0_PfiPKfS0_Pfi, @function
_Z30__device_stub__Z4mmulPKfS0_PfiPKfS0_Pfi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4mmulPKfS0_Pfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z4mmulPKfS0_PfiPKfS0_Pfi, .-_Z30__device_stub__Z4mmulPKfS0_PfiPKfS0_Pfi
.globl _Z4mmulPKfS0_Pfi
.type _Z4mmulPKfS0_Pfi, @function
_Z4mmulPKfS0_Pfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z4mmulPKfS0_PfiPKfS0_Pfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4mmulPKfS0_Pfi, .-_Z4mmulPKfS0_Pfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4mmulPKfS0_Pfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4mmulPKfS0_Pfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mmul.hip"
.globl _Z19__device_stub__mmulPKfS0_Pfi # -- Begin function _Z19__device_stub__mmulPKfS0_Pfi
.p2align 4, 0x90
.type _Z19__device_stub__mmulPKfS0_Pfi,@function
_Z19__device_stub__mmulPKfS0_Pfi: # @_Z19__device_stub__mmulPKfS0_Pfi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4mmulPKfS0_Pfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__mmulPKfS0_Pfi, .Lfunc_end0-_Z19__device_stub__mmulPKfS0_Pfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4mmulPKfS0_Pfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4mmulPKfS0_Pfi,@object # @_Z4mmulPKfS0_Pfi
.section .rodata,"a",@progbits
.globl _Z4mmulPKfS0_Pfi
.p2align 3, 0x0
_Z4mmulPKfS0_Pfi:
.quad _Z19__device_stub__mmulPKfS0_Pfi
.size _Z4mmulPKfS0_Pfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4mmulPKfS0_Pfi"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__mmulPKfS0_Pfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4mmulPKfS0_Pfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
int main(int argc, char* argv[])
{
cudaDeviceProp dev_prop;
int dev_cnt = 0;
cudaGetDeviceCount(&dev_cnt);
for(int i=0; i < dev_cnt; ++i)
{
cudaGetDeviceProperties(&dev_prop, i);
std::cout << "Device : " << i << " has compute capability " << dev_prop.major << "." << dev_prop.minor << std::endl;
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
int main(int argc, char* argv[])
{
cudaDeviceProp dev_prop;
int dev_cnt = 0;
cudaGetDeviceCount(&dev_cnt);
for(int i=0; i < dev_cnt; ++i)
{
cudaGetDeviceProperties(&dev_prop, i);
std::cout << "Device : " << i << " has compute capability " << dev_prop.major << "." << dev_prop.minor << std::endl;
}
return 0;
} | .file "tmpxft_000dc180_00000000-6_get_compute_capability.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device : "
.LC1:
.string " has compute capability "
.LC2:
.string "."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebp
leaq .LC0(%rip), %r15
leaq _ZSt4cout(%rip), %r13
leaq .LC1(%rip), %r14
jmp .L9
.L14:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L13
call _ZSt16__throw_bad_castv@PLT
.L13:
call __stack_chk_fail@PLT
.L7:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L8:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L4
.L9:
leaq 16(%rsp), %rdi
movl %ebp, %esi
call cudaGetDeviceProperties_v2@PLT
movl $9, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $24, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L14
cmpb $0, 56(%r12)
je .L7
movzbl 67(%r12), %esi
jmp .L8
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
int main(int argc, char* argv[])
{
cudaDeviceProp dev_prop;
int dev_cnt = 0;
cudaGetDeviceCount(&dev_cnt);
for(int i=0; i < dev_cnt; ++i)
{
cudaGetDeviceProperties(&dev_prop, i);
std::cout << "Device : " << i << " has compute capability " << dev_prop.major << "." << dev_prop.minor << std::endl;
}
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
int main(int argc, char* argv[])
{
hipDeviceProp_t dev_prop;
int dev_cnt = 0;
hipGetDeviceCount(&dev_cnt);
for(int i=0; i < dev_cnt; ++i)
{
hipGetDeviceProperties(&dev_prop, i);
std::cout << "Device : " << i << " has compute capability " << dev_prop.major << "." << dev_prop.minor << std::endl;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
int main(int argc, char* argv[])
{
hipDeviceProp_t dev_prop;
int dev_cnt = 0;
hipGetDeviceCount(&dev_cnt);
for(int i=0; i < dev_cnt; ++i)
{
hipGetDeviceProperties(&dev_prop, i);
std::cout << "Device : " << i << " has compute capability " << dev_prop.major << "." << dev_prop.minor << std::endl;
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
int main(int argc, char* argv[])
{
hipDeviceProp_t dev_prop;
int dev_cnt = 0;
hipGetDeviceCount(&dev_cnt);
for(int i=0; i < dev_cnt; ++i)
{
hipGetDeviceProperties(&dev_prop, i);
std::cout << "Device : " << i << " has compute capability " << dev_prop.major << "." << dev_prop.minor << std::endl;
}
return 0;
} | .text
.file "get_compute_capability.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_7
# %bb.1: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB0_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_7
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $24, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_8
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_2 Depth=1
cmpb $0, 56(%r15)
je .LBB0_5
# %bb.4: # in Loop: Header=BB0_2 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_6
.LBB0_7: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device : "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " has compute capability "
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "."
.size .L.str.2, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000dc180_00000000-6_get_compute_capability.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Device : "
.LC1:
.string " has compute capability "
.LC2:
.string "."
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
movl $0, 12(%rsp)
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebp
leaq .LC0(%rip), %r15
leaq _ZSt4cout(%rip), %r13
leaq .LC1(%rip), %r14
jmp .L9
.L14:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L13
call _ZSt16__throw_bad_castv@PLT
.L13:
call __stack_chk_fail@PLT
.L7:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L8:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %ebp
cmpl %ebp, 12(%rsp)
jle .L4
.L9:
leaq 16(%rsp), %rdi
movl %ebp, %esi
call cudaGetDeviceProperties_v2@PLT
movl $9, %edx
movq %r15, %rsi
movq %r13, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $24, %edx
movq %r14, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 376(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $1, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 380(%rsp), %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r12
testq %r12, %r12
je .L14
cmpb $0, 56(%r12)
je .L7
movzbl 67(%r12), %esi
jmp .L8
.L4:
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L15
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "get_compute_capability.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $0, 4(%rsp)
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 4(%rsp)
jle .LBB0_7
# %bb.1: # %.lr.ph
xorl %ebx, %ebx
leaq 8(%rsp), %r14
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # in Loop: Header=BB0_2 Depth=1
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB0_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB0_2 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %ebx
cmpl 4(%rsp), %ebx
jge .LBB0_7
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.1, %esi
movl $24, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 368(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 372(%rsp), %esi
movq %r15, %rdi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB0_8
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB0_2 Depth=1
cmpb $0, 56(%r15)
je .LBB0_5
# %bb.4: # in Loop: Header=BB0_2 Depth=1
movzbl 67(%r15), %ecx
jmp .LBB0_6
.LBB0_7: # %._crit_edge
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB0_8:
.cfi_def_cfa_offset 1520
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Device : "
.size .L.str, 10
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " has compute capability "
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "."
.size .L.str.2, 2
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sum(int *dest, int a, int b)
{
// Assuming a single thread, 1x1x1 block, 1x1 grid
*dest = a + b;
} | code for sm_80
Function : _Z3sumPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sum(int *dest, int a, int b)
{
// Assuming a single thread, 1x1x1 block, 1x1 grid
*dest = a + b;
} | .file "tmpxft_0002183a_00000000-6_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3sumPiiiPiii
.type _Z24__device_stub__Z3sumPiiiPiii, @function
_Z24__device_stub__Z3sumPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z3sumPiiiPiii, .-_Z24__device_stub__Z3sumPiiiPiii
.globl _Z3sumPiii
.type _Z3sumPiii, @function
_Z3sumPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3sumPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3sumPiii, .-_Z3sumPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3sumPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sum(int *dest, int a, int b)
{
// Assuming a single thread, 1x1x1 block, 1x1 grid
*dest = a + b;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum(int *dest, int a, int b)
{
// Assuming a single thread, 1x1x1 block, 1x1 grid
*dest = a + b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum(int *dest, int a, int b)
{
// Assuming a single thread, 1x1x1 block, 1x1 grid
*dest = a + b;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiii
.globl _Z3sumPiii
.p2align 8
.type _Z3sumPiii,@function
_Z3sumPiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiii, .Lfunc_end0-_Z3sumPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3sumPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sum(int *dest, int a, int b)
{
// Assuming a single thread, 1x1x1 block, 1x1 grid
*dest = a + b;
} | .text
.file "sum.hip"
.globl _Z18__device_stub__sumPiii # -- Begin function _Z18__device_stub__sumPiii
.p2align 4, 0x90
.type _Z18__device_stub__sumPiii,@function
_Z18__device_stub__sumPiii: # @_Z18__device_stub__sumPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3sumPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPiii, .Lfunc_end0-_Z18__device_stub__sumPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPiii,@object # @_Z3sumPiii
.section .rodata,"a",@progbits
.globl _Z3sumPiii
.p2align 3, 0x0
_Z3sumPiii:
.quad _Z18__device_stub__sumPiii
.size _Z3sumPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3sumPiii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3sumPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x168], RZ ; /* 0x00005a0005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3sumPiii
.globl _Z3sumPiii
.p2align 8
.type _Z3sumPiii,@function
_Z3sumPiii:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3sumPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3sumPiii, .Lfunc_end0-_Z3sumPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3sumPiii
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3sumPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002183a_00000000-6_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3sumPiiiPiii
.type _Z24__device_stub__Z3sumPiiiPiii, @function
_Z24__device_stub__Z3sumPiiiPiii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3sumPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z3sumPiiiPiii, .-_Z24__device_stub__Z3sumPiiiPiii
.globl _Z3sumPiii
.type _Z3sumPiii, @function
_Z3sumPiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3sumPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3sumPiii, .-_Z3sumPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3sumPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3sumPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sum.hip"
.globl _Z18__device_stub__sumPiii # -- Begin function _Z18__device_stub__sumPiii
.p2align 4, 0x90
.type _Z18__device_stub__sumPiii,@function
_Z18__device_stub__sumPiii: # @_Z18__device_stub__sumPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3sumPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__sumPiii, .Lfunc_end0-_Z18__device_stub__sumPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3sumPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3sumPiii,@object # @_Z3sumPiii
.section .rodata,"a",@progbits
.globl _Z3sumPiii
.p2align 3, 0x0
_Z3sumPiii:
.quad _Z18__device_stub__sumPiii
.size _Z3sumPiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3sumPiii"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__sumPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3sumPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <iostream>
#include <ctime>
#include "device_launch_parameters.h"
#include <limits.h>
#define PRINT_MATRIX true
#define CHECK(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
cout<< "Error:" << cudaGetErrorString(_m_cudaStat) \
<< " at line " << __LINE__ << " in file " << __FILE__ << "\n"; \
exit(1);\
} }
#define MAX_MEMORY_VECTOR 104857600 //100 Mb
#define COUNT_OF_ELEMENTS_IN_SYSTEM 1024 //Count of elements in system of vectors
#define COUNT_OF_VECTORS_IN_SYSTEM 12 //Count of vectors in system
#define COUNT_OF_ELEMENTS_IN_VECTOR (COUNT_OF_ELEMENTS_IN_SYSTEM / COUNT_OF_VECTORS_IN_SYSTEM) //Count of elements in one vector
#define SIZE_GRAM_MATRIX (COUNT_OF_VECTORS_IN_SYSTEM * COUNT_OF_VECTORS_IN_SYSTEM)
using namespace std;
inline void Info()
{
cout << "Size of system: " << COUNT_OF_ELEMENTS_IN_SYSTEM
<< "\nCount of vectors: " << COUNT_OF_VECTORS_IN_SYSTEM
<< "\nCount of elements in one vector: " << COUNT_OF_ELEMENTS_IN_VECTOR << endl;
}
void InfoResult(unsigned char*, unsigned char*);
void PrintSystemOfVectors(unsigned char*);
void PrintVector(unsigned char*, size_t);
unsigned char* GetRandomSystemOfVectors();
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time);
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time);
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size);
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device);
__global__ void calculate_GramMatrix_GPU(unsigned char* systemOfVectors, unsigned char* gramMatrix)
{
__shared__ unsigned char cache[1024];
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= SIZE_GRAM_MATRIX) return;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
{
cache[threadIdx.x] +=
systemOfVectors[(index / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(index % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
}
__syncthreads();
gramMatrix[index] = cache[threadIdx.x];
}
int main()
{
Info();
float timeCPU = 0.0f, timeGPU = 0.0f;
unsigned char* systemOfVectors = GetRandomSystemOfVectors();
bool isForPrint = COUNT_OF_ELEMENTS_IN_SYSTEM <= 2048;
if (isForPrint) PrintSystemOfVectors(systemOfVectors);
cout << "\nSize Gram matrix: " << SIZE_GRAM_MATRIX << "\n\n";
unsigned char* matrixGramCPU = GetGramMatrixCPU(systemOfVectors, timeCPU);
unsigned char* matrixGramGPU = GetGramMatrixGPU(systemOfVectors, timeGPU);
Check(matrixGramCPU, matrixGramGPU);
cout << "\n--------\n";
cout << "Time CPU: " << timeCPU << endl;
cout << "Time GPU: " << timeGPU << endl;
cout << "\n--------\n";
InfoResult(matrixGramCPU, matrixGramGPU);
cin.get();
return 0;
}
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time_d)
{
cout << "\n---------\n";
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
int memoryForGramMatrix = sizeof(unsigned char) * SIZE_GRAM_MATRIX;
int memoryForBigVector = sizeof(unsigned char) * COUNT_OF_ELEMENTS_IN_SYSTEM;
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
matrixGram[i] = 0;
unsigned char* systemOfVectors_GPU;
unsigned char* matrixGram_GPU;
cudaEvent_t startCUDA, stopCUDA;
CHECK(cudaEventCreate(&startCUDA));
CHECK(cudaEventCreate(&stopCUDA));
CHECK(cudaMalloc(&systemOfVectors_GPU, memoryForBigVector));
CHECK(cudaMalloc(&matrixGram_GPU, memoryForGramMatrix));
CHECK(cudaMemcpy(systemOfVectors_GPU, systemOfVectors, memoryForBigVector, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(matrixGram_GPU, matrixGram, memoryForGramMatrix, cudaMemcpyHostToDevice));
CHECK(cudaEventRecord(startCUDA, 0));
cout << "Calculate on DEVICE...\n";
int countOfBlocks = (SIZE_GRAM_MATRIX + 1023) / 1024;
calculate_GramMatrix_GPU<<<countOfBlocks, 1024>>>(systemOfVectors_GPU, matrixGram_GPU);
cout << "Count of blocks: " << countOfBlocks << endl;
cudaEventRecord(stopCUDA, 0);
cudaEventSynchronize(stopCUDA);
cudaEventElapsedTime(&time_d, startCUDA, stopCUDA);
time_d /= 1000;
CHECK(cudaMemcpy(matrixGram, matrixGram_GPU, memoryForGramMatrix, cudaMemcpyDeviceToHost));
cout << "Done\n";
cudaFree(systemOfVectors_GPU);
cudaFree(matrixGram_GPU);
return matrixGram;
}
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time_h)
{
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
for (int i = 0; i < SIZE_GRAM_MATRIX; i++) matrixGram[i] = 0;
cout << "Calculate on HOST...\n";
time_h = clock();
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
{
int currentRow = (i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_VECTORS_IN_SYSTEM;
int shiftCol = (i / COUNT_OF_VECTORS_IN_SYSTEM);
int currentIndexMainDiag = currentRow + shiftCol;
if (i < currentIndexMainDiag) continue;
unsigned char temp = 0;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
temp +=
systemOfVectors[(i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(i % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
matrixGram[currentIndexMainDiag + (i - currentIndexMainDiag) * COUNT_OF_VECTORS_IN_SYSTEM] = matrixGram[i] = temp;
}
cout << "Done\n";
time_h /= CLOCKS_PER_SEC;
return matrixGram;
}
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nCheck...\n";
if (IsEqual(matrix_Host, matrix_Device, SIZE_GRAM_MATRIX))
cout << "That's right! :)\n";
else cout << "Wrong! :(\n";
}
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size)
{
for (int i = 0; i < size; i++)
if (firstVector[i] != secondVector[i])
return false;
return true;
}
unsigned char* GetRandomSystemOfVectors()
{
unsigned char* vector = new unsigned char[COUNT_OF_ELEMENTS_IN_SYSTEM];
for (int i = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++)
vector[i] = rand() % 9 + 1;
return vector;
}
void InfoResult(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nGram matrix CPU: " << endl;
PrintVector(matrix_Host, SIZE_GRAM_MATRIX);
cout << "\nGram matrix GPU: " << endl;
PrintVector(matrix_Device, SIZE_GRAM_MATRIX);
}
void PrintSystemOfVectors(unsigned char* systemOfVectors)
{
bool step = COUNT_OF_ELEMENTS_IN_SYSTEM < 10;
cout << "\nBig vector:\n\n";
for (int i = 0, j = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++, j++)
{
if (j == COUNT_OF_ELEMENTS_IN_VECTOR && step)
{
cout << endl;
j = 0;
}
cout << (int)systemOfVectors[i] << " ";
}
cout << endl;
}
void PrintVector(unsigned char* vector, size_t size)
{
if (PRINT_MATRIX)
{
for (int i = 0; i < COUNT_OF_VECTORS_IN_SYSTEM; i++)
{
for (int j = 0; j < COUNT_OF_VECTORS_IN_SYSTEM; j++)
{
cout << (int)vector[i * COUNT_OF_VECTORS_IN_SYSTEM + j] << "\t";
}
cout << endl;
}
}
else
{
for (int i = 0; i < size; i++)
cout << (int)vector[i] << " ";
cout << endl;
}
} | code for sm_80
Function : _Z24calculate_GramMatrix_GPUPhS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R0 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x8f, PT ; /* 0x0000008f0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.HI R2, R6, 0x2aaaaaab, RZ ; /* 0x2aaaaaab06027827 */
/* 0x000fe200078e02ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LDS.U8 R4, [R0] ; /* 0x0000000000047984 */
/* 0x000e220000000000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff037819 */
/* 0x000fc80000011402 */
/*00b0*/ LEA.HI R3, R2, R3, RZ, 0x1 ; /* 0x0000000302037211 */
/* 0x000fca00078f08ff */
/*00c0*/ IMAD R7, R3.reuse, 0x55, RZ ; /* 0x0000005503077824 */
/* 0x040fe400078e02ff */
/*00d0*/ IMAD R8, R3, -0xc, R6 ; /* 0xfffffff403087824 */
/* 0x000fc600078e0206 */
/*00e0*/ SHF.R.S32.HI R16, RZ, 0x1f, R7 ; /* 0x0000001fff107819 */
/* 0x000fe20000011407 */
/*00f0*/ IMAD R8, R8, 0x55, RZ ; /* 0x0000005508087824 */
/* 0x000fe200078e02ff */
/*0100*/ IADD3 R10, P1, R7, c[0x0][0x160], RZ ; /* 0x00005800070a7a10 */
/* 0x000fc80007f3e0ff */
/*0110*/ IADD3.X R11, R16, c[0x0][0x164], RZ, P1, !PT ; /* 0x00005900100b7a10 */
/* 0x000fe40000ffe4ff */
/*0120*/ SHF.R.S32.HI R17, RZ, 0x1f, R8 ; /* 0x0000001fff117819 */
/* 0x000fe40000011408 */
/*0130*/ IADD3 R14, P0, R8, c[0x0][0x160], RZ ; /* 0x00005800080e7a10 */
/* 0x000fe40007f1e0ff */
/*0140*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0160*/ IADD3.X R13, R17, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900110d7a10 */
/* 0x000fc600007fe4ff */
/*0170*/ LDG.E.U8 R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000224000c1e1100 */
/*0180*/ MOV R2, R14 ; /* 0x0000000e00027202 */
/* 0x002fe40000000f00 */
/*0190*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fca0000000f00 */
/*01a0*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000e24000c1e1100 */
/*01b0*/ IMAD R4, R5, R9, R4 ; /* 0x0000000905047224 */
/* 0x001fe200078e0204 */
/*01c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fc800000001ff */
/*01d0*/ PRMT R15, R4, 0x7610, R15 ; /* 0x00007610040f7816 */
/* 0x000fe4000000000f */
/*01e0*/ MOV R12, R14 ; /* 0x0000000e000c7202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E.U8 R19, [R10.64+0x1] ; /* 0x000001040a137981 */
/* 0x0000a8000c1e1100 */
/*0200*/ LDG.E.U8 R18, [R12.64+0x1] ; /* 0x000001040c127981 */
/* 0x0002a8000c1e1100 */
/*0210*/ LDG.E.U8 R21, [R12.64+0x2] ; /* 0x000002040c157981 */
/* 0x0002e8000c1e1100 */
/*0220*/ LDG.E.U8 R20, [R10.64+0x2] ; /* 0x000002040a147981 */
/* 0x0000e2000c1e1100 */
/*0230*/ IADD3 R2, P0, R8, UR6, RZ ; /* 0x0000000608027c10 */
/* 0x000fc4000ff1e0ff */
/*0240*/ IADD3 R4, P1, R7, UR6, RZ ; /* 0x0000000607047c10 */
/* 0x000fe2000ff3e0ff */
/*0250*/ LDG.E.U8 R14, [R12.64+0x3] ; /* 0x000003040c0e7981 */
/* 0x000322000c1e1100 */
/*0260*/ IADD3.X R3, R17, UR7, RZ, P0, !PT ; /* 0x0000000711037c10 */
/* 0x000fe400087fe4ff */
/*0270*/ IADD3.X R5, R16, UR7, RZ, P1, !PT ; /* 0x0000000710057c10 */
/* 0x000fe20008ffe4ff */
/*0280*/ LDG.E.U8 R22, [R10.64+0x3] ; /* 0x000003040a167981 */
/* 0x000128000c1e1100 */
/*0290*/ LDG.E.U8 R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000f68000c1e1100 */
/*02a0*/ LDG.E.U8 R24, [R4.64+0x4] ; /* 0x0000040404187981 */
/* 0x000f68000c1e1100 */
/*02b0*/ LDG.E.U8 R25, [R4.64+0x5] ; /* 0x0000050404197981 */
/* 0x000f68000c1e1100 */
/*02c0*/ LDG.E.U8 R27, [R2.64+0x6] ; /* 0x00000604021b7981 */
/* 0x000f68000c1e1100 */
/*02d0*/ LDG.E.U8 R12, [R4.64+0x7] ; /* 0x00000704040c7981 */
/* 0x002f68000c1e1100 */
/*02e0*/ LDG.E.U8 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x001f68000c1e1100 */
/*02f0*/ LDG.E.U8 R11, [R4.64+0x8] ; /* 0x00000804040b7981 */
/* 0x000f68000c1e1100 */
/*0300*/ LDG.E.U8 R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000f62000c1e1100 */
/*0310*/ IMAD R18, R18, R19, R15 ; /* 0x0000001312127224 */
/* 0x004fc600078e020f */
/*0320*/ LDG.E.U8 R19, [R2.64+0x5] ; /* 0x0000050402137981 */
/* 0x000ea8000c1e1100 */
/*0330*/ LDG.E.U8 R15, [R2.64+0x7] ; /* 0x00000704020f7981 */
/* 0x000ea2000c1e1100 */
/*0340*/ IMAD R21, R21, R20, R18 ; /* 0x0000001415157224 */
/* 0x008fc600078e0212 */
/*0350*/ LDG.E.U8 R18, [R4.64+0x6] ; /* 0x0000060404127981 */
/* 0x000ee8000c1e1100 */
/*0360*/ LDG.E.U8 R20, [R4.64+0x9] ; /* 0x0000090404147981 */
/* 0x000ee2000c1e1100 */
/*0370*/ IMAD R14, R14, R22, R21 ; /* 0x000000160e0e7224 */
/* 0x010fc600078e0215 */
/*0380*/ LDG.E.U8 R21, [R4.64+0xa] ; /* 0x00000a0404157981 */
/* 0x000f28000c1e1100 */
/*0390*/ LDG.E.U8 R22, [R4.64+0xb] ; /* 0x00000b0404167981 */
/* 0x000f22000c1e1100 */
/*03a0*/ IMAD R14, R23, R24, R14 ; /* 0x00000018170e7224 */
/* 0x020fc600078e020e */
/*03b0*/ LDG.E.U8 R23, [R2.64+0x10] ; /* 0x0000100402177981 */
/* 0x000f62000c1e1100 */
/*03c0*/ IMAD R14, R19, R25, R14 ; /* 0x00000019130e7224 */
/* 0x004fc600078e020e */
/*03d0*/ LDG.E.U8 R19, [R2.64+0x9] ; /* 0x0000090402137981 */
/* 0x000ea2000c1e1100 */
/*03e0*/ IMAD R14, R27, R18, R14 ; /* 0x000000121b0e7224 */
/* 0x008fc600078e020e */
/*03f0*/ LDG.E.U8 R18, [R2.64+0xa] ; /* 0x00000a0402127981 */
/* 0x000f22000c1e1100 */
/*0400*/ IMAD R14, R15, R12, R14 ; /* 0x0000000c0f0e7224 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E.U8 R15, [R2.64+0xb] ; /* 0x00000b04020f7981 */
/* 0x000ee8000c1e1100 */
/*0420*/ LDG.E.U8 R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000f62000c1e1100 */
/*0430*/ IMAD R10, R10, R11, R14 ; /* 0x0000000b0a0a7224 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E.U8 R11, [R4.64+0xd] ; /* 0x00000d04040b7981 */
/* 0x000f68000c1e1100 */
/*0450*/ LDG.E.U8 R14, [R4.64+0xe] ; /* 0x00000e04040e7981 */
/* 0x000f62000c1e1100 */
/*0460*/ IMAD R19, R19, R20, R10 ; /* 0x0000001413137224 */
/* 0x004fc600078e020a */
/*0470*/ LDG.E.U8 R10, [R2.64+0xd] ; /* 0x00000d04020a7981 */
/* 0x000ea8000c1e1100 */
/*0480*/ LDG.E.U8 R20, [R4.64+0x10] ; /* 0x0000100404147981 */
/* 0x000ea2000c1e1100 */
/*0490*/ IMAD R18, R18, R21, R19 ; /* 0x0000001512127224 */
/* 0x010fc600078e0213 */
/*04a0*/ LDG.E.U8 R19, [R2.64+0xe] ; /* 0x00000e0402137981 */
/* 0x000f22000c1e1100 */
/*04b0*/ IMAD R15, R15, R22, R18 ; /* 0x000000160f0f7224 */
/* 0x008fc600078e0212 */
/*04c0*/ LDG.E.U8 R21, [R2.64+0xf] ; /* 0x00000f0402157981 */
/* 0x000ee8000c1e1100 */
/*04d0*/ LDG.E.U8 R18, [R4.64+0xf] ; /* 0x00000f0404127981 */
/* 0x000ee2000c1e1100 */
/*04e0*/ IMAD R15, R13, R12, R15 ; /* 0x0000000c0d0f7224 */
/* 0x020fc600078e020f */
/*04f0*/ LDG.E.U8 R13, [R2.64+0x11] ; /* 0x00001104020d7981 */
/* 0x000f68000c1e1100 */
/*0500*/ LDG.E.U8 R12, [R4.64+0x11] ; /* 0x00001104040c7981 */
/* 0x000f68000c1e1100 */
/*0510*/ LDG.E.U8 R22, [R2.64+0x15] ; /* 0x0000150402167981 */
/* 0x000f62000c1e1100 */
/*0520*/ IMAD R10, R10, R11, R15 ; /* 0x0000000b0a0a7224 */
/* 0x004fc600078e020f */
/*0530*/ LDG.E.U8 R11, [R2.64+0x12] ; /* 0x00001204020b7981 */
/* 0x000ea8000c1e1100 */
/*0540*/ LDG.E.U8 R15, [R2.64+0x13] ; /* 0x00001304020f7981 */
/* 0x000ea2000c1e1100 */
/*0550*/ IMAD R14, R19, R14, R10 ; /* 0x0000000e130e7224 */
/* 0x010fc600078e020a */
/*0560*/ LDG.E.U8 R10, [R4.64+0x12] ; /* 0x00001204040a7981 */
/* 0x000ea8000c1e1100 */
/*0570*/ LDG.E.U8 R19, [R4.64+0x14] ; /* 0x0000140404137981 */
/* 0x000f22000c1e1100 */
/*0580*/ IMAD R14, R21, R18, R14 ; /* 0x00000012150e7224 */
/* 0x008fc600078e020e */
/*0590*/ LDG.E.U8 R18, [R4.64+0x13] ; /* 0x0000130404127981 */
/* 0x000ee2000c1e1100 */
/*05a0*/ IMAD R14, R23, R20, R14 ; /* 0x00000014170e7224 */
/* 0x000fc600078e020e */
/*05b0*/ LDG.E.U8 R20, [R2.64+0x14] ; /* 0x0000140402147981 */
/* 0x000f28000c1e1100 */
/*05c0*/ LDG.E.U8 R21, [R4.64+0x15] ; /* 0x0000150404157981 */
/* 0x000f22000c1e1100 */
/*05d0*/ IMAD R14, R13, R12, R14 ; /* 0x0000000c0d0e7224 */
/* 0x020fc600078e020e */
/*05e0*/ LDG.E.U8 R12, [R2.64+0x16] ; /* 0x00001604020c7981 */
/* 0x000f68000c1e1100 */
/*05f0*/ LDG.E.U8 R13, [R4.64+0x16] ; /* 0x00001604040d7981 */
/* 0x000f68000c1e1100 */
/*0600*/ LDG.E.U8 R23, [R2.64+0x1c] ; /* 0x00001c0402177981 */
/* 0x000f62000c1e1100 */
/*0610*/ IMAD R10, R11, R10, R14 ; /* 0x0000000a0b0a7224 */
/* 0x004fc600078e020e */
/*0620*/ LDG.E.U8 R11, [R4.64+0x17] ; /* 0x00001704040b7981 */
/* 0x000ea8000c1e1100 */
/*0630*/ LDG.E.U8 R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x000ea2000c1e1100 */
/*0640*/ IMAD R15, R15, R18, R10 ; /* 0x000000120f0f7224 */
/* 0x008fc600078e020a */
/*0650*/ LDG.E.U8 R10, [R2.64+0x17] ; /* 0x00001704020a7981 */
/* 0x000ea2000c1e1100 */
/*0660*/ IMAD R19, R20, R19, R15 ; /* 0x0000001314137224 */
/* 0x010fc600078e020f */
/*0670*/ LDG.E.U8 R15, [R2.64+0x18] ; /* 0x00001804020f7981 */
/* 0x000ee2000c1e1100 */
/*0680*/ IMAD R21, R22, R21, R19 ; /* 0x0000001516157224 */
/* 0x000fc600078e0213 */
/*0690*/ LDG.E.U8 R18, [R2.64+0x19] ; /* 0x0000190402127981 */
/* 0x000f28000c1e1100 */
/*06a0*/ LDG.E.U8 R19, [R4.64+0x19] ; /* 0x0000190404137981 */
/* 0x000f22000c1e1100 */
/*06b0*/ IMAD R24, R12, R13, R21 ; /* 0x0000000d0c187224 */
/* 0x020fc600078e0215 */
/*06c0*/ LDG.E.U8 R13, [R2.64+0x1a] ; /* 0x00001a04020d7981 */
/* 0x000f68000c1e1100 */
/*06d0*/ LDG.E.U8 R12, [R4.64+0x1a] ; /* 0x00001a04040c7981 */
/* 0x000f68000c1e1100 */
/*06e0*/ LDG.E.U8 R21, [R2.64+0x1b] ; /* 0x00001b0402157981 */
/* 0x000f68000c1e1100 */
/*06f0*/ LDG.E.U8 R20, [R4.64+0x1b] ; /* 0x00001b0404147981 */
/* 0x000f68000c1e1100 */
/*0700*/ LDG.E.U8 R22, [R4.64+0x1c] ; /* 0x00001c0404167981 */
/* 0x000f62000c1e1100 */
/*0710*/ IADD3 R9, R9, 0x1c, RZ ; /* 0x0000001c09097810 */
/* 0x000fc80007ffe0ff */
/*0720*/ ISETP.NE.AND P0, PT, R9, 0x54, PT ; /* 0x000000540900780c */
/* 0x000fe20003f05270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x1c, URZ ; /* 0x0000001c06067890 */
/* 0x000fc8000ff1e03f */
/*0740*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0750*/ IMAD R10, R10, R11, R24 ; /* 0x0000000b0a0a7224 */
/* 0x004fc800078e0218 */
/*0760*/ IMAD R10, R15, R14, R10 ; /* 0x0000000e0f0a7224 */
/* 0x008fc800078e020a */
/*0770*/ IMAD R18, R18, R19, R10 ; /* 0x0000001312127224 */
/* 0x010fc800078e020a */
/*0780*/ IMAD R12, R13, R12, R18 ; /* 0x0000000c0d0c7224 */
/* 0x020fe200078e0212 */
/*0790*/ IADD3 R14, P1, R2, 0x1c, RZ ; /* 0x0000001c020e7810 */
/* 0x000fe40007f3e0ff */
/*07a0*/ IADD3 R10, P2, R4, 0x1c, RZ ; /* 0x0000001c040a7810 */
/* 0x000fe20007f5e0ff */
/*07b0*/ IMAD R12, R21, R20, R12 ; /* 0x00000014150c7224 */
/* 0x000fc800078e020c */
/*07c0*/ IMAD R12, R23, R22, R12 ; /* 0x00000016170c7224 */
/* 0x000fe200078e020c */
/*07d0*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fe40000ffe4ff */
/*07e0*/ IADD3.X R11, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0b7210 */
/* 0x000fe400017fe4ff */
/*07f0*/ PRMT R15, R12, 0x7610, R15 ; /* 0x000076100c0f7816 */
/* 0x000fe2000000000f */
/*0800*/ @P0 BRA 0x1e0 ; /* 0xfffff9d000000947 */
/* 0x000fea000383ffff */
/*0810*/ STS.U8 [R0], R15 ; /* 0x0000000f00007388 */
/* 0x000fe80000000000 */
/*0820*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0830*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fc80007f1e0ff */
/*0840*/ LEA.HI.X.SX32 R3, R6, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0006037a11 */
/* 0x000fe200000f0eff */
/*0850*/ LDS.U8 R5, [R0] ; /* 0x0000000000057984 */
/* 0x000e280000000000 */
/*0860*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101104 */
/*0870*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <iostream>
#include <ctime>
#include "device_launch_parameters.h"
#include <limits.h>
#define PRINT_MATRIX true
#define CHECK(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
cout<< "Error:" << cudaGetErrorString(_m_cudaStat) \
<< " at line " << __LINE__ << " in file " << __FILE__ << "\n"; \
exit(1);\
} }
#define MAX_MEMORY_VECTOR 104857600 //100 Mb
#define COUNT_OF_ELEMENTS_IN_SYSTEM 1024 //Count of elements in system of vectors
#define COUNT_OF_VECTORS_IN_SYSTEM 12 //Count of vectors in system
#define COUNT_OF_ELEMENTS_IN_VECTOR (COUNT_OF_ELEMENTS_IN_SYSTEM / COUNT_OF_VECTORS_IN_SYSTEM) //Count of elements in one vector
#define SIZE_GRAM_MATRIX (COUNT_OF_VECTORS_IN_SYSTEM * COUNT_OF_VECTORS_IN_SYSTEM)
using namespace std;
inline void Info()
{
cout << "Size of system: " << COUNT_OF_ELEMENTS_IN_SYSTEM
<< "\nCount of vectors: " << COUNT_OF_VECTORS_IN_SYSTEM
<< "\nCount of elements in one vector: " << COUNT_OF_ELEMENTS_IN_VECTOR << endl;
}
void InfoResult(unsigned char*, unsigned char*);
void PrintSystemOfVectors(unsigned char*);
void PrintVector(unsigned char*, size_t);
unsigned char* GetRandomSystemOfVectors();
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time);
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time);
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size);
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device);
__global__ void calculate_GramMatrix_GPU(unsigned char* systemOfVectors, unsigned char* gramMatrix)
{
__shared__ unsigned char cache[1024];
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= SIZE_GRAM_MATRIX) return;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
{
cache[threadIdx.x] +=
systemOfVectors[(index / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(index % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
}
__syncthreads();
gramMatrix[index] = cache[threadIdx.x];
}
int main()
{
Info();
float timeCPU = 0.0f, timeGPU = 0.0f;
unsigned char* systemOfVectors = GetRandomSystemOfVectors();
bool isForPrint = COUNT_OF_ELEMENTS_IN_SYSTEM <= 2048;
if (isForPrint) PrintSystemOfVectors(systemOfVectors);
cout << "\nSize Gram matrix: " << SIZE_GRAM_MATRIX << "\n\n";
unsigned char* matrixGramCPU = GetGramMatrixCPU(systemOfVectors, timeCPU);
unsigned char* matrixGramGPU = GetGramMatrixGPU(systemOfVectors, timeGPU);
Check(matrixGramCPU, matrixGramGPU);
cout << "\n--------\n";
cout << "Time CPU: " << timeCPU << endl;
cout << "Time GPU: " << timeGPU << endl;
cout << "\n--------\n";
InfoResult(matrixGramCPU, matrixGramGPU);
cin.get();
return 0;
}
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time_d)
{
cout << "\n---------\n";
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
int memoryForGramMatrix = sizeof(unsigned char) * SIZE_GRAM_MATRIX;
int memoryForBigVector = sizeof(unsigned char) * COUNT_OF_ELEMENTS_IN_SYSTEM;
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
matrixGram[i] = 0;
unsigned char* systemOfVectors_GPU;
unsigned char* matrixGram_GPU;
cudaEvent_t startCUDA, stopCUDA;
CHECK(cudaEventCreate(&startCUDA));
CHECK(cudaEventCreate(&stopCUDA));
CHECK(cudaMalloc(&systemOfVectors_GPU, memoryForBigVector));
CHECK(cudaMalloc(&matrixGram_GPU, memoryForGramMatrix));
CHECK(cudaMemcpy(systemOfVectors_GPU, systemOfVectors, memoryForBigVector, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(matrixGram_GPU, matrixGram, memoryForGramMatrix, cudaMemcpyHostToDevice));
CHECK(cudaEventRecord(startCUDA, 0));
cout << "Calculate on DEVICE...\n";
int countOfBlocks = (SIZE_GRAM_MATRIX + 1023) / 1024;
calculate_GramMatrix_GPU<<<countOfBlocks, 1024>>>(systemOfVectors_GPU, matrixGram_GPU);
cout << "Count of blocks: " << countOfBlocks << endl;
cudaEventRecord(stopCUDA, 0);
cudaEventSynchronize(stopCUDA);
cudaEventElapsedTime(&time_d, startCUDA, stopCUDA);
time_d /= 1000;
CHECK(cudaMemcpy(matrixGram, matrixGram_GPU, memoryForGramMatrix, cudaMemcpyDeviceToHost));
cout << "Done\n";
cudaFree(systemOfVectors_GPU);
cudaFree(matrixGram_GPU);
return matrixGram;
}
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time_h)
{
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
for (int i = 0; i < SIZE_GRAM_MATRIX; i++) matrixGram[i] = 0;
cout << "Calculate on HOST...\n";
time_h = clock();
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
{
int currentRow = (i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_VECTORS_IN_SYSTEM;
int shiftCol = (i / COUNT_OF_VECTORS_IN_SYSTEM);
int currentIndexMainDiag = currentRow + shiftCol;
if (i < currentIndexMainDiag) continue;
unsigned char temp = 0;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
temp +=
systemOfVectors[(i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(i % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
matrixGram[currentIndexMainDiag + (i - currentIndexMainDiag) * COUNT_OF_VECTORS_IN_SYSTEM] = matrixGram[i] = temp;
}
cout << "Done\n";
time_h /= CLOCKS_PER_SEC;
return matrixGram;
}
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nCheck...\n";
if (IsEqual(matrix_Host, matrix_Device, SIZE_GRAM_MATRIX))
cout << "That's right! :)\n";
else cout << "Wrong! :(\n";
}
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size)
{
for (int i = 0; i < size; i++)
if (firstVector[i] != secondVector[i])
return false;
return true;
}
unsigned char* GetRandomSystemOfVectors()
{
unsigned char* vector = new unsigned char[COUNT_OF_ELEMENTS_IN_SYSTEM];
for (int i = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++)
vector[i] = rand() % 9 + 1;
return vector;
}
void InfoResult(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nGram matrix CPU: " << endl;
PrintVector(matrix_Host, SIZE_GRAM_MATRIX);
cout << "\nGram matrix GPU: " << endl;
PrintVector(matrix_Device, SIZE_GRAM_MATRIX);
}
void PrintSystemOfVectors(unsigned char* systemOfVectors)
{
bool step = COUNT_OF_ELEMENTS_IN_SYSTEM < 10;
cout << "\nBig vector:\n\n";
for (int i = 0, j = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++, j++)
{
if (j == COUNT_OF_ELEMENTS_IN_VECTOR && step)
{
cout << endl;
j = 0;
}
cout << (int)systemOfVectors[i] << " ";
}
cout << endl;
}
void PrintVector(unsigned char* vector, size_t size)
{
if (PRINT_MATRIX)
{
for (int i = 0; i < COUNT_OF_VECTORS_IN_SYSTEM; i++)
{
for (int j = 0; j < COUNT_OF_VECTORS_IN_SYSTEM; j++)
{
cout << (int)vector[i * COUNT_OF_VECTORS_IN_SYSTEM + j] << "\t";
}
cout << endl;
}
}
else
{
for (int i = 0; i < size; i++)
cout << (int)vector[i] << " ";
cout << endl;
}
} | .file "tmpxft_00091712_00000000-6_GramMatrixOptimizeCPU.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3681:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3681:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z4Infov.str1.1,"aMS",@progbits,1
.LC0:
.string "Size of system: "
.LC1:
.string "\nCount of vectors: "
.section .rodata._Z4Infov.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "\nCount of elements in one vector: "
.section .text._Z4Infov,"axG",@progbits,_Z4Infov,comdat
.weak _Z4Infov
.type _Z4Infov, @function
_Z4Infov:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl $16, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1024, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $19, %edx
leaq .LC1(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $12, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $34, %edx
leaq .LC2(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $85, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L8
cmpb $0, 56(%rbp)
je .L5
movzbl 67(%rbp), %esi
.L6:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L5:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L6
.cfi_endproc
.LFE3669:
.size _Z4Infov, .-_Z4Infov
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "Calculate on HOST...\n"
.LC4:
.string "Done\n"
.text
.globl _Z16GetGramMatrixCPUPhRf
.type _Z16GetGramMatrixCPUPhRf, @function
_Z16GetGramMatrixCPUPhRf:
.LFB3672:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movq %rsi, %r12
movl $144, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 144(%rax), %rdx
.L10:
movb $0, (%rax)
addq $1, %rax
cmpq %rdx, %rax
jne .L10
movl $21, %edx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movss %xmm0, (%r12)
movl $0, %r9d
leaq 85(%rbp), %r13
jmp .L13
.L19:
movb %cl, (%rbx,%r9)
subl %r10d, %r11d
leal (%r11,%r11,2), %eax
leal (%r10,%rax,4), %eax
cltq
movb %cl, (%rbx,%rax)
.L11:
addq $1, %r9
cmpq $144, %r9
je .L18
.L13:
movl %r9d, %r11d
movslq %r9d, %rax
imulq $715827883, %rax, %rax
sarq $33, %rax
movl %r9d, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %edx
leal (%rax,%rdx,4), %r10d
cmpl %r9d, %r10d
jg .L11
imull $85, %eax, %edi
movslq %edi, %rdi
leaq 0(%rbp,%rdi), %rdx
addq %r13, %rdi
cltq
imulq $-85, %rax, %rsi
movslq %r9d, %rax
imulq $715827883, %rax, %rax
sarq $33, %rax
movl %r9d, %ecx
sarl $31, %ecx
subl %ecx, %eax
leal (%rax,%rax,2), %ecx
sall $2, %ecx
movl %r9d, %eax
subl %ecx, %eax
cltq
leaq (%rax,%rax,4), %r8
movq %r8, %rax
salq $4, %rax
addq %rax, %r8
movl $0, %ecx
.L12:
leaq (%rdx,%rsi), %rax
movzbl (%rax,%r8), %eax
mulb (%rdx)
addl %eax, %ecx
addq $1, %rdx
cmpq %rdi, %rdx
jne .L12
jmp .L19
.L18:
movl $5, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss (%r12), %xmm0
divss .LC5(%rip), %xmm0
movss %xmm0, (%r12)
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _Z16GetGramMatrixCPUPhRf, .-_Z16GetGramMatrixCPUPhRf
.globl _Z7IsEqualPhS_m
.type _Z7IsEqualPhS_m, @function
_Z7IsEqualPhS_m:
.LFB3674:
.cfi_startproc
endbr64
testq %rdx, %rdx
je .L23
movl $0, %eax
.L22:
movzbl (%rsi,%rax), %ecx
cmpb %cl, (%rdi,%rax)
jne .L24
addq $1, %rax
cmpq %rax, %rdx
jne .L22
movl $1, %eax
ret
.L23:
movl $1, %eax
ret
.L24:
movl $0, %eax
ret
.cfi_endproc
.LFE3674:
.size _Z7IsEqualPhS_m, .-_Z7IsEqualPhS_m
.section .rodata.str1.1
.LC6:
.string "\nCheck...\n"
.LC7:
.string "That's right! :)\n"
.LC8:
.string "Wrong! :(\n"
.text
.globl _Z5CheckPhS_
.type _Z5CheckPhS_, @function
_Z5CheckPhS_:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %rsi, %rbp
movl $10, %edx
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $144, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z7IsEqualPhS_m
testb %al, %al
je .L27
movl $17, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L26:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
movl $10, %edx
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
jmp .L26
.cfi_endproc
.LFE3673:
.size _Z5CheckPhS_, .-_Z5CheckPhS_
.globl _Z24GetRandomSystemOfVectorsv
.type _Z24GetRandomSystemOfVectorsv, @function
_Z24GetRandomSystemOfVectorsv:
.LFB3675:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movl $1024, %edi
call _Znam@PLT
movq %rax, %r12
movq %rax, %rbx
leaq 1024(%rax), %rbp
.L31:
call rand@PLT
movslq %eax, %rdx
imulq $954437177, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,8), %edx
subl %edx, %eax
addl $1, %eax
movb %al, (%rbx)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L31
movq %r12, %rax
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _Z24GetRandomSystemOfVectorsv, .-_Z24GetRandomSystemOfVectorsv
.section .rodata.str1.1
.LC9:
.string "\nBig vector:\n\n"
.LC10:
.string " "
.text
.globl _Z20PrintSystemOfVectorsPh
.type _Z20PrintSystemOfVectorsPh, @function
_Z20PrintSystemOfVectorsPh:
.LFB3677:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl $14, %edx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbp, %rbx
addq $1024, %rbp
leaq _ZSt4cout(%rip), %r13
leaq .LC10(%rip), %r12
.L35:
movzbl (%rbx), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r12, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L35
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %rbx
testq %rbx, %rbx
je .L41
cmpb $0, 56(%rbx)
je .L37
movzbl 67(%rbx), %eax
.L38:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L37:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L38
.cfi_endproc
.LFE3677:
.size _Z20PrintSystemOfVectorsPh, .-_Z20PrintSystemOfVectorsPh
.section .rodata.str1.1
.LC11:
.string "\t"
.text
.globl _Z11PrintVectorPhm
.type _Z11PrintVectorPhm, @function
_Z11PrintVectorPhm:
.LFB3678:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq 12(%rdi), %rbp
leaq 156(%rdi), %r14
leaq _ZSt4cout(%rip), %r12
leaq .LC11(%rip), %r13
jmp .L43
.L51:
call _ZSt16__throw_bad_castv@PLT
.L46:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L47:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $12, %rbp
cmpq %r14, %rbp
je .L42
.L43:
leaq -12(%rbp), %rbx
.L44:
movzbl (%rbx), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L44
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L51
cmpb $0, 56(%rbx)
je .L46
movzbl 67(%rbx), %esi
jmp .L47
.L42:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3678:
.size _Z11PrintVectorPhm, .-_Z11PrintVectorPhm
.section .rodata.str1.1
.LC12:
.string "\nGram matrix CPU: "
.LC13:
.string "\nGram matrix GPU: "
.text
.globl _Z10InfoResultPhS_
.type _Z10InfoResultPhS_, @function
_Z10InfoResultPhS_:
.LFB3676:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
movl $18, %edx
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L60
cmpb $0, 56(%rbx)
je .L54
movzbl 67(%rbx), %esi
.L55:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $144, %esi
movq %r12, %rdi
call _Z11PrintVectorPhm
movl $18, %edx
leaq .LC13(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L61
cmpb $0, 56(%rbx)
je .L57
movzbl 67(%rbx), %esi
.L58:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $144, %esi
movq %rbp, %rdi
call _Z11PrintVectorPhm
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call _ZSt16__throw_bad_castv@PLT
.L54:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L55
.L61:
call _ZSt16__throw_bad_castv@PLT
.L57:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L58
.cfi_endproc
.LFE3676:
.size _Z10InfoResultPhS_, .-_Z10InfoResultPhS_
.globl _Z46__device_stub__Z24calculate_GramMatrix_GPUPhS_PhS_
.type _Z46__device_stub__Z24calculate_GramMatrix_GPUPhS_PhS_, @function
_Z46__device_stub__Z24calculate_GramMatrix_GPUPhS_PhS_:
.LFB3703:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L66
.L62:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z24calculate_GramMatrix_GPUPhS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L62
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3703:
.size _Z46__device_stub__Z24calculate_GramMatrix_GPUPhS_PhS_, .-_Z46__device_stub__Z24calculate_GramMatrix_GPUPhS_PhS_
.globl _Z24calculate_GramMatrix_GPUPhS_
.type _Z24calculate_GramMatrix_GPUPhS_, @function
_Z24calculate_GramMatrix_GPUPhS_:
.LFB3704:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z24calculate_GramMatrix_GPUPhS_PhS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3704:
.size _Z24calculate_GramMatrix_GPUPhS_, .-_Z24calculate_GramMatrix_GPUPhS_
.section .rodata.str1.1
.LC14:
.string "\n---------\n"
.LC15:
.string "Error:"
.LC16:
.string " at line "
.LC17:
.string " in file "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC18:
.string "/home/ubuntu/Datasets/stackv2/train-structured/Tessecrack/CUDA_DEV/main/GramMatrix/GramMatrixOptimizeCPU.cu"
.section .rodata.str1.1
.LC19:
.string "\n"
.LC20:
.string "Calculate on DEVICE...\n"
.LC21:
.string "Count of blocks: "
.text
.globl _Z16GetGramMatrixGPUPhRf
.type _Z16GetGramMatrixGPUPhRf, @function
_Z16GetGramMatrixGPUPhRf:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r13
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $11, %edx
leaq .LC14(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $144, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 144(%rax), %rdx
.L71:
movb $0, (%rax)
addq $1, %rax
cmpq %rax, %rdx
jne .L71
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L88
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L89
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L90
leaq 8(%rsp), %rdi
movl $144, %esi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L91
movl $1, %ecx
movl $1024, %edx
movq %r13, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L92
movl $1, %ecx
movl $144, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L93
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L94
movl $23, %edx
leaq .LC20(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L95
.L79:
movl $17, %edx
leaq .LC21(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $1, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L96
cmpb $0, 56(%r13)
je .L82
movzbl 67(%r13), %eax
.L83:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaEventElapsedTime@PLT
movss 0(%rbp), %xmm0
divss .LC22(%rip), %xmm0
movss %xmm0, 0(%rbp)
movl $2, %ecx
movl $144, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L97
movl $5, %edx
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L98
movq %rbx, %rax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L88:
.cfi_restore_state
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $100, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L89:
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $101, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L90:
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $103, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L91:
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $104, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L92:
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $106, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L93:
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $107, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L94:
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $109, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L95:
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z46__device_stub__Z24calculate_GramMatrix_GPUPhS_PhS_
jmp .L79
.L96:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L99
call _ZSt16__throw_bad_castv@PLT
.L99:
call __stack_chk_fail@PLT
.L82:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
jmp .L83
.L97:
leaq .LC15(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC16(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $122, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC17(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC18(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC19(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $1, %edi
call exit@PLT
.L98:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3671:
.size _Z16GetGramMatrixGPUPhRf, .-_Z16GetGramMatrixGPUPhRf
.section .rodata.str1.1
.LC24:
.string "\nSize Gram matrix: "
.LC25:
.string "\n\n"
.LC26:
.string "\n--------\n"
.LC27:
.string "Time CPU: "
.LC28:
.string "Time GPU: "
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
call _Z4Infov
movl $0x00000000, (%rsp)
movl $0x00000000, 4(%rsp)
call _Z24GetRandomSystemOfVectorsv
movq %rax, %rbp
movq %rax, %rdi
call _Z20PrintSystemOfVectorsPh
leaq .LC24(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $144, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC25(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rsp, %rsi
movq %rbp, %rdi
call _Z16GetGramMatrixCPUPhRf
movq %rax, %r12
leaq 4(%rsp), %rsi
movq %rbp, %rdi
call _Z16GetGramMatrixGPUPhRf
movq %rax, %rbp
movq %rax, %rsi
movq %r12, %rdi
call _Z5CheckPhS_
leaq .LC26(%rip), %r13
movq %r13, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC27(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC28(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rbp, %rsi
movq %r12, %rdi
call _Z10InfoResultPhS_
leaq _ZSt3cin(%rip), %rdi
call _ZNSi3getEv@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L103
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L103:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC29:
.string "_Z24calculate_GramMatrix_GPUPhS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3706:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z24calculate_GramMatrix_GPUPhS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3706:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1232348160
.align 4
.LC22:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <iostream>
#include <ctime>
#include "device_launch_parameters.h"
#include <limits.h>
#define PRINT_MATRIX true
#define CHECK(value) {\
cudaError_t _m_cudaStat = value;\
if (_m_cudaStat != cudaSuccess) {\
cout<< "Error:" << cudaGetErrorString(_m_cudaStat) \
<< " at line " << __LINE__ << " in file " << __FILE__ << "\n"; \
exit(1);\
} }
#define MAX_MEMORY_VECTOR 104857600 //100 Mb
#define COUNT_OF_ELEMENTS_IN_SYSTEM 1024 //Count of elements in system of vectors
#define COUNT_OF_VECTORS_IN_SYSTEM 12 //Count of vectors in system
#define COUNT_OF_ELEMENTS_IN_VECTOR (COUNT_OF_ELEMENTS_IN_SYSTEM / COUNT_OF_VECTORS_IN_SYSTEM) //Count of elements in one vector
#define SIZE_GRAM_MATRIX (COUNT_OF_VECTORS_IN_SYSTEM * COUNT_OF_VECTORS_IN_SYSTEM)
using namespace std;
inline void Info()
{
cout << "Size of system: " << COUNT_OF_ELEMENTS_IN_SYSTEM
<< "\nCount of vectors: " << COUNT_OF_VECTORS_IN_SYSTEM
<< "\nCount of elements in one vector: " << COUNT_OF_ELEMENTS_IN_VECTOR << endl;
}
void InfoResult(unsigned char*, unsigned char*);
void PrintSystemOfVectors(unsigned char*);
void PrintVector(unsigned char*, size_t);
unsigned char* GetRandomSystemOfVectors();
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time);
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time);
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size);
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device);
__global__ void calculate_GramMatrix_GPU(unsigned char* systemOfVectors, unsigned char* gramMatrix)
{
__shared__ unsigned char cache[1024];
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= SIZE_GRAM_MATRIX) return;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
{
cache[threadIdx.x] +=
systemOfVectors[(index / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(index % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
}
__syncthreads();
gramMatrix[index] = cache[threadIdx.x];
}
int main()
{
Info();
float timeCPU = 0.0f, timeGPU = 0.0f;
unsigned char* systemOfVectors = GetRandomSystemOfVectors();
bool isForPrint = COUNT_OF_ELEMENTS_IN_SYSTEM <= 2048;
if (isForPrint) PrintSystemOfVectors(systemOfVectors);
cout << "\nSize Gram matrix: " << SIZE_GRAM_MATRIX << "\n\n";
unsigned char* matrixGramCPU = GetGramMatrixCPU(systemOfVectors, timeCPU);
unsigned char* matrixGramGPU = GetGramMatrixGPU(systemOfVectors, timeGPU);
Check(matrixGramCPU, matrixGramGPU);
cout << "\n--------\n";
cout << "Time CPU: " << timeCPU << endl;
cout << "Time GPU: " << timeGPU << endl;
cout << "\n--------\n";
InfoResult(matrixGramCPU, matrixGramGPU);
cin.get();
return 0;
}
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time_d)
{
cout << "\n---------\n";
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
int memoryForGramMatrix = sizeof(unsigned char) * SIZE_GRAM_MATRIX;
int memoryForBigVector = sizeof(unsigned char) * COUNT_OF_ELEMENTS_IN_SYSTEM;
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
matrixGram[i] = 0;
unsigned char* systemOfVectors_GPU;
unsigned char* matrixGram_GPU;
cudaEvent_t startCUDA, stopCUDA;
CHECK(cudaEventCreate(&startCUDA));
CHECK(cudaEventCreate(&stopCUDA));
CHECK(cudaMalloc(&systemOfVectors_GPU, memoryForBigVector));
CHECK(cudaMalloc(&matrixGram_GPU, memoryForGramMatrix));
CHECK(cudaMemcpy(systemOfVectors_GPU, systemOfVectors, memoryForBigVector, cudaMemcpyHostToDevice));
CHECK(cudaMemcpy(matrixGram_GPU, matrixGram, memoryForGramMatrix, cudaMemcpyHostToDevice));
CHECK(cudaEventRecord(startCUDA, 0));
cout << "Calculate on DEVICE...\n";
int countOfBlocks = (SIZE_GRAM_MATRIX + 1023) / 1024;
calculate_GramMatrix_GPU<<<countOfBlocks, 1024>>>(systemOfVectors_GPU, matrixGram_GPU);
cout << "Count of blocks: " << countOfBlocks << endl;
cudaEventRecord(stopCUDA, 0);
cudaEventSynchronize(stopCUDA);
cudaEventElapsedTime(&time_d, startCUDA, stopCUDA);
time_d /= 1000;
CHECK(cudaMemcpy(matrixGram, matrixGram_GPU, memoryForGramMatrix, cudaMemcpyDeviceToHost));
cout << "Done\n";
cudaFree(systemOfVectors_GPU);
cudaFree(matrixGram_GPU);
return matrixGram;
}
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time_h)
{
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
for (int i = 0; i < SIZE_GRAM_MATRIX; i++) matrixGram[i] = 0;
cout << "Calculate on HOST...\n";
time_h = clock();
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
{
int currentRow = (i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_VECTORS_IN_SYSTEM;
int shiftCol = (i / COUNT_OF_VECTORS_IN_SYSTEM);
int currentIndexMainDiag = currentRow + shiftCol;
if (i < currentIndexMainDiag) continue;
unsigned char temp = 0;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
temp +=
systemOfVectors[(i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(i % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
matrixGram[currentIndexMainDiag + (i - currentIndexMainDiag) * COUNT_OF_VECTORS_IN_SYSTEM] = matrixGram[i] = temp;
}
cout << "Done\n";
time_h /= CLOCKS_PER_SEC;
return matrixGram;
}
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nCheck...\n";
if (IsEqual(matrix_Host, matrix_Device, SIZE_GRAM_MATRIX))
cout << "That's right! :)\n";
else cout << "Wrong! :(\n";
}
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size)
{
for (int i = 0; i < size; i++)
if (firstVector[i] != secondVector[i])
return false;
return true;
}
unsigned char* GetRandomSystemOfVectors()
{
unsigned char* vector = new unsigned char[COUNT_OF_ELEMENTS_IN_SYSTEM];
for (int i = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++)
vector[i] = rand() % 9 + 1;
return vector;
}
void InfoResult(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nGram matrix CPU: " << endl;
PrintVector(matrix_Host, SIZE_GRAM_MATRIX);
cout << "\nGram matrix GPU: " << endl;
PrintVector(matrix_Device, SIZE_GRAM_MATRIX);
}
void PrintSystemOfVectors(unsigned char* systemOfVectors)
{
bool step = COUNT_OF_ELEMENTS_IN_SYSTEM < 10;
cout << "\nBig vector:\n\n";
for (int i = 0, j = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++, j++)
{
if (j == COUNT_OF_ELEMENTS_IN_VECTOR && step)
{
cout << endl;
j = 0;
}
cout << (int)systemOfVectors[i] << " ";
}
cout << endl;
}
void PrintVector(unsigned char* vector, size_t size)
{
if (PRINT_MATRIX)
{
for (int i = 0; i < COUNT_OF_VECTORS_IN_SYSTEM; i++)
{
for (int j = 0; j < COUNT_OF_VECTORS_IN_SYSTEM; j++)
{
cout << (int)vector[i * COUNT_OF_VECTORS_IN_SYSTEM + j] << "\t";
}
cout << endl;
}
}
else
{
for (int i = 0; i < size; i++)
cout << (int)vector[i] << " ";
cout << endl;
}
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
#include <limits.h>
#define PRINT_MATRIX true
#define CHECK(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
cout<< "Error:" << hipGetErrorString(_m_cudaStat) \
<< " at line " << __LINE__ << " in file " << __FILE__ << "\n"; \
exit(1);\
} }
#define MAX_MEMORY_VECTOR 104857600 //100 Mb
#define COUNT_OF_ELEMENTS_IN_SYSTEM 1024 //Count of elements in system of vectors
#define COUNT_OF_VECTORS_IN_SYSTEM 12 //Count of vectors in system
#define COUNT_OF_ELEMENTS_IN_VECTOR (COUNT_OF_ELEMENTS_IN_SYSTEM / COUNT_OF_VECTORS_IN_SYSTEM) //Count of elements in one vector
#define SIZE_GRAM_MATRIX (COUNT_OF_VECTORS_IN_SYSTEM * COUNT_OF_VECTORS_IN_SYSTEM)
using namespace std;
inline void Info()
{
cout << "Size of system: " << COUNT_OF_ELEMENTS_IN_SYSTEM
<< "\nCount of vectors: " << COUNT_OF_VECTORS_IN_SYSTEM
<< "\nCount of elements in one vector: " << COUNT_OF_ELEMENTS_IN_VECTOR << endl;
}
void InfoResult(unsigned char*, unsigned char*);
void PrintSystemOfVectors(unsigned char*);
void PrintVector(unsigned char*, size_t);
unsigned char* GetRandomSystemOfVectors();
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time);
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time);
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size);
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device);
__global__ void calculate_GramMatrix_GPU(unsigned char* systemOfVectors, unsigned char* gramMatrix)
{
__shared__ unsigned char cache[1024];
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= SIZE_GRAM_MATRIX) return;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
{
cache[threadIdx.x] +=
systemOfVectors[(index / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(index % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
}
__syncthreads();
gramMatrix[index] = cache[threadIdx.x];
}
int main()
{
Info();
float timeCPU = 0.0f, timeGPU = 0.0f;
unsigned char* systemOfVectors = GetRandomSystemOfVectors();
bool isForPrint = COUNT_OF_ELEMENTS_IN_SYSTEM <= 2048;
if (isForPrint) PrintSystemOfVectors(systemOfVectors);
cout << "\nSize Gram matrix: " << SIZE_GRAM_MATRIX << "\n\n";
unsigned char* matrixGramCPU = GetGramMatrixCPU(systemOfVectors, timeCPU);
unsigned char* matrixGramGPU = GetGramMatrixGPU(systemOfVectors, timeGPU);
Check(matrixGramCPU, matrixGramGPU);
cout << "\n--------\n";
cout << "Time CPU: " << timeCPU << endl;
cout << "Time GPU: " << timeGPU << endl;
cout << "\n--------\n";
InfoResult(matrixGramCPU, matrixGramGPU);
cin.get();
return 0;
}
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time_d)
{
cout << "\n---------\n";
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
int memoryForGramMatrix = sizeof(unsigned char) * SIZE_GRAM_MATRIX;
int memoryForBigVector = sizeof(unsigned char) * COUNT_OF_ELEMENTS_IN_SYSTEM;
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
matrixGram[i] = 0;
unsigned char* systemOfVectors_GPU;
unsigned char* matrixGram_GPU;
hipEvent_t startCUDA, stopCUDA;
CHECK(hipEventCreate(&startCUDA));
CHECK(hipEventCreate(&stopCUDA));
CHECK(hipMalloc(&systemOfVectors_GPU, memoryForBigVector));
CHECK(hipMalloc(&matrixGram_GPU, memoryForGramMatrix));
CHECK(hipMemcpy(systemOfVectors_GPU, systemOfVectors, memoryForBigVector, hipMemcpyHostToDevice));
CHECK(hipMemcpy(matrixGram_GPU, matrixGram, memoryForGramMatrix, hipMemcpyHostToDevice));
CHECK(hipEventRecord(startCUDA, 0));
cout << "Calculate on DEVICE...\n";
int countOfBlocks = (SIZE_GRAM_MATRIX + 1023) / 1024;
calculate_GramMatrix_GPU<<<countOfBlocks, 1024>>>(systemOfVectors_GPU, matrixGram_GPU);
cout << "Count of blocks: " << countOfBlocks << endl;
hipEventRecord(stopCUDA, 0);
hipEventSynchronize(stopCUDA);
hipEventElapsedTime(&time_d, startCUDA, stopCUDA);
time_d /= 1000;
CHECK(hipMemcpy(matrixGram, matrixGram_GPU, memoryForGramMatrix, hipMemcpyDeviceToHost));
cout << "Done\n";
hipFree(systemOfVectors_GPU);
hipFree(matrixGram_GPU);
return matrixGram;
}
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time_h)
{
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
for (int i = 0; i < SIZE_GRAM_MATRIX; i++) matrixGram[i] = 0;
cout << "Calculate on HOST...\n";
time_h = clock();
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
{
int currentRow = (i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_VECTORS_IN_SYSTEM;
int shiftCol = (i / COUNT_OF_VECTORS_IN_SYSTEM);
int currentIndexMainDiag = currentRow + shiftCol;
if (i < currentIndexMainDiag) continue;
unsigned char temp = 0;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
temp +=
systemOfVectors[(i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(i % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
matrixGram[currentIndexMainDiag + (i - currentIndexMainDiag) * COUNT_OF_VECTORS_IN_SYSTEM] = matrixGram[i] = temp;
}
cout << "Done\n";
time_h /= CLOCKS_PER_SEC;
return matrixGram;
}
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nCheck...\n";
if (IsEqual(matrix_Host, matrix_Device, SIZE_GRAM_MATRIX))
cout << "That's right! :)\n";
else cout << "Wrong! :(\n";
}
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size)
{
for (int i = 0; i < size; i++)
if (firstVector[i] != secondVector[i])
return false;
return true;
}
unsigned char* GetRandomSystemOfVectors()
{
unsigned char* vector = new unsigned char[COUNT_OF_ELEMENTS_IN_SYSTEM];
for (int i = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++)
vector[i] = rand() % 9 + 1;
return vector;
}
void InfoResult(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nGram matrix CPU: " << endl;
PrintVector(matrix_Host, SIZE_GRAM_MATRIX);
cout << "\nGram matrix GPU: " << endl;
PrintVector(matrix_Device, SIZE_GRAM_MATRIX);
}
void PrintSystemOfVectors(unsigned char* systemOfVectors)
{
bool step = COUNT_OF_ELEMENTS_IN_SYSTEM < 10;
cout << "\nBig vector:\n\n";
for (int i = 0, j = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++, j++)
{
if (j == COUNT_OF_ELEMENTS_IN_VECTOR && step)
{
cout << endl;
j = 0;
}
cout << (int)systemOfVectors[i] << " ";
}
cout << endl;
}
void PrintVector(unsigned char* vector, size_t size)
{
if (PRINT_MATRIX)
{
for (int i = 0; i < COUNT_OF_VECTORS_IN_SYSTEM; i++)
{
for (int j = 0; j < COUNT_OF_VECTORS_IN_SYSTEM; j++)
{
cout << (int)vector[i * COUNT_OF_VECTORS_IN_SYSTEM + j] << "\t";
}
cout << endl;
}
}
else
{
for (int i = 0; i < size; i++)
cout << (int)vector[i] << " ";
cout << endl;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
#include <limits.h>
#define PRINT_MATRIX true
#define CHECK(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
cout<< "Error:" << hipGetErrorString(_m_cudaStat) \
<< " at line " << __LINE__ << " in file " << __FILE__ << "\n"; \
exit(1);\
} }
#define MAX_MEMORY_VECTOR 104857600 //100 Mb
#define COUNT_OF_ELEMENTS_IN_SYSTEM 1024 //Count of elements in system of vectors
#define COUNT_OF_VECTORS_IN_SYSTEM 12 //Count of vectors in system
#define COUNT_OF_ELEMENTS_IN_VECTOR (COUNT_OF_ELEMENTS_IN_SYSTEM / COUNT_OF_VECTORS_IN_SYSTEM) //Count of elements in one vector
#define SIZE_GRAM_MATRIX (COUNT_OF_VECTORS_IN_SYSTEM * COUNT_OF_VECTORS_IN_SYSTEM)
using namespace std;
inline void Info()
{
cout << "Size of system: " << COUNT_OF_ELEMENTS_IN_SYSTEM
<< "\nCount of vectors: " << COUNT_OF_VECTORS_IN_SYSTEM
<< "\nCount of elements in one vector: " << COUNT_OF_ELEMENTS_IN_VECTOR << endl;
}
void InfoResult(unsigned char*, unsigned char*);
void PrintSystemOfVectors(unsigned char*);
void PrintVector(unsigned char*, size_t);
unsigned char* GetRandomSystemOfVectors();
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time);
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time);
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size);
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device);
__global__ void calculate_GramMatrix_GPU(unsigned char* systemOfVectors, unsigned char* gramMatrix)
{
__shared__ unsigned char cache[1024];
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= SIZE_GRAM_MATRIX) return;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
{
cache[threadIdx.x] +=
systemOfVectors[(index / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(index % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
}
__syncthreads();
gramMatrix[index] = cache[threadIdx.x];
}
int main()
{
Info();
float timeCPU = 0.0f, timeGPU = 0.0f;
unsigned char* systemOfVectors = GetRandomSystemOfVectors();
bool isForPrint = COUNT_OF_ELEMENTS_IN_SYSTEM <= 2048;
if (isForPrint) PrintSystemOfVectors(systemOfVectors);
cout << "\nSize Gram matrix: " << SIZE_GRAM_MATRIX << "\n\n";
unsigned char* matrixGramCPU = GetGramMatrixCPU(systemOfVectors, timeCPU);
unsigned char* matrixGramGPU = GetGramMatrixGPU(systemOfVectors, timeGPU);
Check(matrixGramCPU, matrixGramGPU);
cout << "\n--------\n";
cout << "Time CPU: " << timeCPU << endl;
cout << "Time GPU: " << timeGPU << endl;
cout << "\n--------\n";
InfoResult(matrixGramCPU, matrixGramGPU);
cin.get();
return 0;
}
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time_d)
{
cout << "\n---------\n";
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
int memoryForGramMatrix = sizeof(unsigned char) * SIZE_GRAM_MATRIX;
int memoryForBigVector = sizeof(unsigned char) * COUNT_OF_ELEMENTS_IN_SYSTEM;
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
matrixGram[i] = 0;
unsigned char* systemOfVectors_GPU;
unsigned char* matrixGram_GPU;
hipEvent_t startCUDA, stopCUDA;
CHECK(hipEventCreate(&startCUDA));
CHECK(hipEventCreate(&stopCUDA));
CHECK(hipMalloc(&systemOfVectors_GPU, memoryForBigVector));
CHECK(hipMalloc(&matrixGram_GPU, memoryForGramMatrix));
CHECK(hipMemcpy(systemOfVectors_GPU, systemOfVectors, memoryForBigVector, hipMemcpyHostToDevice));
CHECK(hipMemcpy(matrixGram_GPU, matrixGram, memoryForGramMatrix, hipMemcpyHostToDevice));
CHECK(hipEventRecord(startCUDA, 0));
cout << "Calculate on DEVICE...\n";
int countOfBlocks = (SIZE_GRAM_MATRIX + 1023) / 1024;
calculate_GramMatrix_GPU<<<countOfBlocks, 1024>>>(systemOfVectors_GPU, matrixGram_GPU);
cout << "Count of blocks: " << countOfBlocks << endl;
hipEventRecord(stopCUDA, 0);
hipEventSynchronize(stopCUDA);
hipEventElapsedTime(&time_d, startCUDA, stopCUDA);
time_d /= 1000;
CHECK(hipMemcpy(matrixGram, matrixGram_GPU, memoryForGramMatrix, hipMemcpyDeviceToHost));
cout << "Done\n";
hipFree(systemOfVectors_GPU);
hipFree(matrixGram_GPU);
return matrixGram;
}
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time_h)
{
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
for (int i = 0; i < SIZE_GRAM_MATRIX; i++) matrixGram[i] = 0;
cout << "Calculate on HOST...\n";
time_h = clock();
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
{
int currentRow = (i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_VECTORS_IN_SYSTEM;
int shiftCol = (i / COUNT_OF_VECTORS_IN_SYSTEM);
int currentIndexMainDiag = currentRow + shiftCol;
if (i < currentIndexMainDiag) continue;
unsigned char temp = 0;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
temp +=
systemOfVectors[(i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(i % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
matrixGram[currentIndexMainDiag + (i - currentIndexMainDiag) * COUNT_OF_VECTORS_IN_SYSTEM] = matrixGram[i] = temp;
}
cout << "Done\n";
time_h /= CLOCKS_PER_SEC;
return matrixGram;
}
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nCheck...\n";
if (IsEqual(matrix_Host, matrix_Device, SIZE_GRAM_MATRIX))
cout << "That's right! :)\n";
else cout << "Wrong! :(\n";
}
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size)
{
for (int i = 0; i < size; i++)
if (firstVector[i] != secondVector[i])
return false;
return true;
}
unsigned char* GetRandomSystemOfVectors()
{
unsigned char* vector = new unsigned char[COUNT_OF_ELEMENTS_IN_SYSTEM];
for (int i = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++)
vector[i] = rand() % 9 + 1;
return vector;
}
void InfoResult(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nGram matrix CPU: " << endl;
PrintVector(matrix_Host, SIZE_GRAM_MATRIX);
cout << "\nGram matrix GPU: " << endl;
PrintVector(matrix_Device, SIZE_GRAM_MATRIX);
}
void PrintSystemOfVectors(unsigned char* systemOfVectors)
{
bool step = COUNT_OF_ELEMENTS_IN_SYSTEM < 10;
cout << "\nBig vector:\n\n";
for (int i = 0, j = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++, j++)
{
if (j == COUNT_OF_ELEMENTS_IN_VECTOR && step)
{
cout << endl;
j = 0;
}
cout << (int)systemOfVectors[i] << " ";
}
cout << endl;
}
void PrintVector(unsigned char* vector, size_t size)
{
if (PRINT_MATRIX)
{
for (int i = 0; i < COUNT_OF_VECTORS_IN_SYSTEM; i++)
{
for (int j = 0; j < COUNT_OF_VECTORS_IN_SYSTEM; j++)
{
cout << (int)vector[i * COUNT_OF_VECTORS_IN_SYSTEM + j] << "\t";
}
cout << endl;
}
}
else
{
for (int i = 0; i < size; i++)
cout << (int)vector[i] << " ";
cout << endl;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24calculate_GramMatrix_GPUPhS_
.globl _Z24calculate_GramMatrix_GPUPhS_
.p2align 8
.type _Z24calculate_GramMatrix_GPUPhS_,@function
_Z24calculate_GramMatrix_GPUPhS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x90, v1
s_cbranch_execz .LBB0_4
v_mul_hi_i32 v2, v1, 0x2aaaaaab
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b64 s[4:5], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v3, 31, v2
v_ashrrev_i32_e32 v2, 1, v2
v_add_nc_u32_e32 v3, v2, v3
ds_load_u8 v2, v0
v_mul_lo_u32 v4, v3, 12
v_mul_lo_u32 v5, v3, 0x55
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v1, v4
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, v3, 0x55
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v8, s4, v3
v_add_co_u32 v6, vcc_lo, v4, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v8, vcc_lo, s2, v8
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_cmpk_eq_i32 s4, 0x55
s_clause 0x1
global_load_u8 v6, v[6:7], off
global_load_u8 v7, v[8:9], off
s_waitcnt vmcnt(0)
v_mad_u16 v2, v7, v6, v2
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
ds_store_b8 v0, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_u8 v2, v0
v_ashrrev_i32_e32 v3, 31, v1
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b8 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24calculate_GramMatrix_GPUPhS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24calculate_GramMatrix_GPUPhS_, .Lfunc_end0-_Z24calculate_GramMatrix_GPUPhS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24calculate_GramMatrix_GPUPhS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24calculate_GramMatrix_GPUPhS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <ctime>
#include <limits.h>
#define PRINT_MATRIX true
#define CHECK(value) {\
hipError_t _m_cudaStat = value;\
if (_m_cudaStat != hipSuccess) {\
cout<< "Error:" << hipGetErrorString(_m_cudaStat) \
<< " at line " << __LINE__ << " in file " << __FILE__ << "\n"; \
exit(1);\
} }
#define MAX_MEMORY_VECTOR 104857600 //100 Mb
#define COUNT_OF_ELEMENTS_IN_SYSTEM 1024 //Count of elements in system of vectors
#define COUNT_OF_VECTORS_IN_SYSTEM 12 //Count of vectors in system
#define COUNT_OF_ELEMENTS_IN_VECTOR (COUNT_OF_ELEMENTS_IN_SYSTEM / COUNT_OF_VECTORS_IN_SYSTEM) //Count of elements in one vector
#define SIZE_GRAM_MATRIX (COUNT_OF_VECTORS_IN_SYSTEM * COUNT_OF_VECTORS_IN_SYSTEM)
using namespace std;
inline void Info()
{
cout << "Size of system: " << COUNT_OF_ELEMENTS_IN_SYSTEM
<< "\nCount of vectors: " << COUNT_OF_VECTORS_IN_SYSTEM
<< "\nCount of elements in one vector: " << COUNT_OF_ELEMENTS_IN_VECTOR << endl;
}
void InfoResult(unsigned char*, unsigned char*);
void PrintSystemOfVectors(unsigned char*);
void PrintVector(unsigned char*, size_t);
unsigned char* GetRandomSystemOfVectors();
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time);
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time);
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size);
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device);
__global__ void calculate_GramMatrix_GPU(unsigned char* systemOfVectors, unsigned char* gramMatrix)
{
__shared__ unsigned char cache[1024];
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index >= SIZE_GRAM_MATRIX) return;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
{
cache[threadIdx.x] +=
systemOfVectors[(index / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(index % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
}
__syncthreads();
gramMatrix[index] = cache[threadIdx.x];
}
int main()
{
Info();
float timeCPU = 0.0f, timeGPU = 0.0f;
unsigned char* systemOfVectors = GetRandomSystemOfVectors();
bool isForPrint = COUNT_OF_ELEMENTS_IN_SYSTEM <= 2048;
if (isForPrint) PrintSystemOfVectors(systemOfVectors);
cout << "\nSize Gram matrix: " << SIZE_GRAM_MATRIX << "\n\n";
unsigned char* matrixGramCPU = GetGramMatrixCPU(systemOfVectors, timeCPU);
unsigned char* matrixGramGPU = GetGramMatrixGPU(systemOfVectors, timeGPU);
Check(matrixGramCPU, matrixGramGPU);
cout << "\n--------\n";
cout << "Time CPU: " << timeCPU << endl;
cout << "Time GPU: " << timeGPU << endl;
cout << "\n--------\n";
InfoResult(matrixGramCPU, matrixGramGPU);
cin.get();
return 0;
}
unsigned char* GetGramMatrixGPU(unsigned char* systemOfVectors, float& time_d)
{
cout << "\n---------\n";
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
int memoryForGramMatrix = sizeof(unsigned char) * SIZE_GRAM_MATRIX;
int memoryForBigVector = sizeof(unsigned char) * COUNT_OF_ELEMENTS_IN_SYSTEM;
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
matrixGram[i] = 0;
unsigned char* systemOfVectors_GPU;
unsigned char* matrixGram_GPU;
hipEvent_t startCUDA, stopCUDA;
CHECK(hipEventCreate(&startCUDA));
CHECK(hipEventCreate(&stopCUDA));
CHECK(hipMalloc(&systemOfVectors_GPU, memoryForBigVector));
CHECK(hipMalloc(&matrixGram_GPU, memoryForGramMatrix));
CHECK(hipMemcpy(systemOfVectors_GPU, systemOfVectors, memoryForBigVector, hipMemcpyHostToDevice));
CHECK(hipMemcpy(matrixGram_GPU, matrixGram, memoryForGramMatrix, hipMemcpyHostToDevice));
CHECK(hipEventRecord(startCUDA, 0));
cout << "Calculate on DEVICE...\n";
int countOfBlocks = (SIZE_GRAM_MATRIX + 1023) / 1024;
calculate_GramMatrix_GPU<<<countOfBlocks, 1024>>>(systemOfVectors_GPU, matrixGram_GPU);
cout << "Count of blocks: " << countOfBlocks << endl;
hipEventRecord(stopCUDA, 0);
hipEventSynchronize(stopCUDA);
hipEventElapsedTime(&time_d, startCUDA, stopCUDA);
time_d /= 1000;
CHECK(hipMemcpy(matrixGram, matrixGram_GPU, memoryForGramMatrix, hipMemcpyDeviceToHost));
cout << "Done\n";
hipFree(systemOfVectors_GPU);
hipFree(matrixGram_GPU);
return matrixGram;
}
unsigned char* GetGramMatrixCPU(unsigned char* systemOfVectors, float& time_h)
{
unsigned char* matrixGram = new unsigned char[SIZE_GRAM_MATRIX];
for (int i = 0; i < SIZE_GRAM_MATRIX; i++) matrixGram[i] = 0;
cout << "Calculate on HOST...\n";
time_h = clock();
for (int i = 0; i < SIZE_GRAM_MATRIX; i++)
{
int currentRow = (i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_VECTORS_IN_SYSTEM;
int shiftCol = (i / COUNT_OF_VECTORS_IN_SYSTEM);
int currentIndexMainDiag = currentRow + shiftCol;
if (i < currentIndexMainDiag) continue;
unsigned char temp = 0;
for (int j = 0; j < COUNT_OF_ELEMENTS_IN_VECTOR; j++)
temp +=
systemOfVectors[(i / COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j] *
systemOfVectors[(i % COUNT_OF_VECTORS_IN_SYSTEM) * COUNT_OF_ELEMENTS_IN_VECTOR + j];
matrixGram[currentIndexMainDiag + (i - currentIndexMainDiag) * COUNT_OF_VECTORS_IN_SYSTEM] = matrixGram[i] = temp;
}
cout << "Done\n";
time_h /= CLOCKS_PER_SEC;
return matrixGram;
}
void Check(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nCheck...\n";
if (IsEqual(matrix_Host, matrix_Device, SIZE_GRAM_MATRIX))
cout << "That's right! :)\n";
else cout << "Wrong! :(\n";
}
bool IsEqual(unsigned char* firstVector, unsigned char* secondVector, size_t size)
{
for (int i = 0; i < size; i++)
if (firstVector[i] != secondVector[i])
return false;
return true;
}
unsigned char* GetRandomSystemOfVectors()
{
unsigned char* vector = new unsigned char[COUNT_OF_ELEMENTS_IN_SYSTEM];
for (int i = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++)
vector[i] = rand() % 9 + 1;
return vector;
}
void InfoResult(unsigned char* matrix_Host, unsigned char* matrix_Device)
{
cout << "\nGram matrix CPU: " << endl;
PrintVector(matrix_Host, SIZE_GRAM_MATRIX);
cout << "\nGram matrix GPU: " << endl;
PrintVector(matrix_Device, SIZE_GRAM_MATRIX);
}
void PrintSystemOfVectors(unsigned char* systemOfVectors)
{
bool step = COUNT_OF_ELEMENTS_IN_SYSTEM < 10;
cout << "\nBig vector:\n\n";
for (int i = 0, j = 0; i < COUNT_OF_ELEMENTS_IN_SYSTEM; i++, j++)
{
if (j == COUNT_OF_ELEMENTS_IN_VECTOR && step)
{
cout << endl;
j = 0;
}
cout << (int)systemOfVectors[i] << " ";
}
cout << endl;
}
void PrintVector(unsigned char* vector, size_t size)
{
if (PRINT_MATRIX)
{
for (int i = 0; i < COUNT_OF_VECTORS_IN_SYSTEM; i++)
{
for (int j = 0; j < COUNT_OF_VECTORS_IN_SYSTEM; j++)
{
cout << (int)vector[i * COUNT_OF_VECTORS_IN_SYSTEM + j] << "\t";
}
cout << endl;
}
}
else
{
for (int i = 0; i < size; i++)
cout << (int)vector[i] << " ";
cout << endl;
}
} | .text
.file "GramMatrixOptimizeCPU.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__calculate_GramMatrix_GPUPhS_ # -- Begin function _Z39__device_stub__calculate_GramMatrix_GPUPhS_
.p2align 4, 0x90
.type _Z39__device_stub__calculate_GramMatrix_GPUPhS_,@function
_Z39__device_stub__calculate_GramMatrix_GPUPhS_: # @_Z39__device_stub__calculate_GramMatrix_GPUPhS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z24calculate_GramMatrix_GPUPhS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z39__device_stub__calculate_GramMatrix_GPUPhS_, .Lfunc_end0-_Z39__device_stub__calculate_GramMatrix_GPUPhS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _Z4Infov
movl $0, 4(%rsp)
movl $0, (%rsp)
movl $1024, %edi # imm = 0x400
callq _Znam
movq %rax, %r14
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $954437177, %rax, %rcx # imm = 0x38E38E39
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,8), %ecx
subl %ecx, %eax
incb %al
movb %al, (%r14,%rbx)
incq %rbx
cmpq $1024, %rbx # imm = 0x400
jne .LBB1_1
# %bb.2: # %_Z24GetRandomSystemOfVectorsv.exit
movq %r14, %rdi
callq _Z20PrintSystemOfVectorsPh
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $144, %esi
callq _ZNSolsEi
movl $.L.str.1, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 4(%rsp), %rsi
movq %r14, %rdi
callq _Z16GetGramMatrixCPUPhRf
movq %rax, %rbx
movq %rsp, %rsi
movq %r14, %rdi
callq _Z16GetGramMatrixGPUPhRf
movq %rax, %r14
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movzbl (%rbx), %eax
cmpb (%r14), %al
jne .LBB1_9
# %bb.3: # %.lr.ph.i.preheader
movq $-1, %rax
.p2align 4, 0x90
.LBB1_4: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
cmpq $142, %rax
je .LBB1_5
# %bb.6: # %.lr.ph.i.i
# in Loop: Header=BB1_4 Depth=1
movzbl 2(%rbx,%rax), %edx
leaq 1(%rax), %rcx
cmpb 2(%r14,%rax), %dl
movq %rcx, %rax
je .LBB1_4
# %bb.7: # %_Z7IsEqualPhS_m.exit.i
cmpq $143, %rcx
jb .LBB1_9
.LBB1_8:
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $17, %edx
jmp .LBB1_10
.LBB1_5:
movl $143, %ecx
cmpq $143, %rcx
jae .LBB1_8
.LBB1_9: # %.critedge.i
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $10, %edx
.LBB1_10: # %_Z5CheckPhS_.exit
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_19
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_13
# %bb.12:
movzbl 67(%r15), %ecx
jmp .LBB1_14
.LBB1_13:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB1_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i8
cmpb $0, 56(%r15)
je .LBB1_17
# %bb.16:
movzbl 67(%r15), %ecx
jmp .LBB1_18
.LBB1_17:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB1_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit11
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movq %r14, %rsi
callq _Z10InfoResultPhS_
movl $_ZSt3cin, %edi
callq _ZNSi3getEv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_19:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .text._Z4Infov,"axG",@progbits,_Z4Infov,comdat
.weak _Z4Infov # -- Begin function _Z4Infov
.p2align 4, 0x90
.type _Z4Infov,@function
_Z4Infov: # @_Z4Infov
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str.23, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1024, %esi # imm = 0x400
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.24, %esi
movl $19, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $12, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.25, %esi
movl $34, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $85, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_5
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB2_4
.LBB2_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB2_5:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z4Infov, .Lfunc_end2-_Z4Infov
.cfi_endproc
# -- End function
.text
.globl _Z24GetRandomSystemOfVectorsv # -- Begin function _Z24GetRandomSystemOfVectorsv
.p2align 4, 0x90
.type _Z24GetRandomSystemOfVectorsv,@function
_Z24GetRandomSystemOfVectorsv: # @_Z24GetRandomSystemOfVectorsv
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $1024, %edi # imm = 0x400
callq _Znam
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $954437177, %rax, %rcx # imm = 0x38E38E39
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,8), %ecx
subl %ecx, %eax
incb %al
movb %al, (%rbx,%r14)
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB3_1
# %bb.2:
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z24GetRandomSystemOfVectorsv, .Lfunc_end3-_Z24GetRandomSystemOfVectorsv
.cfi_endproc
# -- End function
.globl _Z20PrintSystemOfVectorsPh # -- Begin function _Z20PrintSystemOfVectorsPh
.p2align 4, 0x90
.type _Z20PrintSystemOfVectorsPh,@function
_Z20PrintSystemOfVectorsPh: # @_Z20PrintSystemOfVectorsPh
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
movl $_ZSt4cout, %edi
movl $.L.str.20, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
movzbl (%rbx,%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.21, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB4_1
# %bb.2:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_7
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_5
# %bb.4:
movzbl 67(%rbx), %eax
jmp .LBB4_6
.LBB4_5:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB4_7:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size _Z20PrintSystemOfVectorsPh, .Lfunc_end4-_Z20PrintSystemOfVectorsPh
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z16GetGramMatrixCPUPhRf
.LCPI5_0:
.long 0x49742400 # float 1.0E+6
.text
.globl _Z16GetGramMatrixCPUPhRf
.p2align 4, 0x90
.type _Z16GetGramMatrixCPUPhRf,@function
_Z16GetGramMatrixCPUPhRf: # @_Z16GetGramMatrixCPUPhRf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r15
movl $144, %edi
callq _Znam
movq %rax, %r14
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
movl $_ZSt4cout, %edi
movl $.L.str.14, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq clock
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movss %xmm0, (%rbx)
xorl %esi, %esi
movl $2863311531, %edi # imm = 0xAAAAAAAB
movabsq $-6148914691236517205, %r8 # imm = 0xAAAAAAAAAAAAAAAB
xorl %ecx, %ecx
jmp .LBB5_1
.p2align 4, 0x90
.LBB5_5: # in Loop: Header=BB5_1 Depth=1
incq %rcx
addl $85, %esi
cmpq $144, %rcx
je .LBB5_6
.LBB5_1: # =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
movl %ecx, %r10d
imulq %rdi, %r10
shrq $35, %r10
movq %rcx, %rax
mulq %r8
leal (%r10,%r10,2), %eax
leal (%r10,%rax,4), %r9d
cmpq %r9, %rcx
jb .LBB5_5
# %bb.2: # %.preheader
# in Loop: Header=BB5_1 Depth=1
imull $1020, %r10d, %eax # imm = 0x3FC
movl %esi, %r10d
subl %eax, %r10d
addq %r15, %r10
shrq $3, %rdx
imulq $85, %rdx, %r11
addq %r15, %r11
xorl %r12d, %r12d
xorl %edx, %edx
.p2align 4, 0x90
.LBB5_3: # Parent Loop BB5_1 Depth=1
# => This Inner Loop Header: Depth=2
movzbl (%r10,%r12), %eax
mulb (%r11,%r12)
addb %al, %dl
incq %r12
cmpq $85, %r12
jne .LBB5_3
# %bb.4: # in Loop: Header=BB5_1 Depth=1
movb %dl, (%r14,%rcx)
movl %ecx, %eax
subl %r9d, %eax
leal (%rax,%rax,2), %eax
leal (%r9,%rax,4), %eax
cltq
movb %dl, (%r14,%rax)
jmp .LBB5_5
.LBB5_6:
movl $_ZSt4cout, %edi
movl $.L.str.13, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI5_0(%rip), %xmm0
movss %xmm0, (%rbx)
movq %r14, %rax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z16GetGramMatrixCPUPhRf, .Lfunc_end5-_Z16GetGramMatrixCPUPhRf
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z16GetGramMatrixGPUPhRf
.LCPI6_0:
.long 0x447a0000 # float 1000
.text
.globl _Z16GetGramMatrixGPUPhRf
.p2align 4, 0x90
.type _Z16GetGramMatrixGPUPhRf,@function
_Z16GetGramMatrixGPUPhRf: # @_Z16GetGramMatrixGPUPhRf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r14
movq %rdi, %r15
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $144, %edi
callq _Znam
movq %rax, %rbx
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movups %xmm0, 32(%rax)
movups %xmm0, 48(%rax)
movups %xmm0, 64(%rax)
movups %xmm0, 80(%rax)
movups %xmm0, 96(%rax)
movups %xmm0, 112(%rax)
movups %xmm0, 128(%rax)
leaq 24(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB6_1
# %bb.3:
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB6_4
# %bb.5:
leaq 16(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
testl %eax, %eax
jne .LBB6_6
# %bb.7:
movq %rsp, %rdi
movl $144, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB6_8
# %bb.9:
movq 16(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_10
# %bb.11:
movq (%rsp), %rdi
movl $144, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB6_12
# %bb.13:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $_ZSt4cout, %edi
testl %eax, %eax
jne .LBB6_14
# %bb.15:
movl $.L.str.11, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_17
# %bb.16:
movq 16(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z24calculate_GramMatrix_GPUPhS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_17:
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r15
testq %r15, %r15
je .LBB6_24
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB6_20
# %bb.19:
movzbl 67(%r15), %ecx
jmp .LBB6_21
.LBB6_20:
movq %r15, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB6_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
movq %r14, %rdi
callq hipEventElapsedTime
movss (%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI6_0(%rip), %xmm0
movss %xmm0, (%r14)
movq (%rsp), %rsi
movl $144, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
testl %eax, %eax
jne .LBB6_22
# %bb.23:
movl $.L.str.13, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 16(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_1:
.cfi_def_cfa_offset 160
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.7, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $100, %esi
jmp .LBB6_2
.LBB6_4:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.7, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $101, %esi
jmp .LBB6_2
.LBB6_6:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.7, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $103, %esi
jmp .LBB6_2
.LBB6_8:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.7, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $104, %esi
jmp .LBB6_2
.LBB6_10:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.7, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $106, %esi
jmp .LBB6_2
.LBB6_12:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.7, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $107, %esi
jmp .LBB6_2
.LBB6_14:
movl $.L.str.6, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.7, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $109, %esi
jmp .LBB6_2
.LBB6_24:
callq _ZSt16__throw_bad_castv
.LBB6_22:
movl $.L.str.6, %esi
movl %eax, %ebx
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %r14
movl %ebx, %edi
callq hipGetErrorString
movq %r14, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.7, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $122, %esi
.LBB6_2:
callq _ZNSolsEi
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.9, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.10, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $1, %edi
callq exit
.Lfunc_end6:
.size _Z16GetGramMatrixGPUPhRf, .Lfunc_end6-_Z16GetGramMatrixGPUPhRf
.cfi_endproc
# -- End function
.globl _Z5CheckPhS_ # -- Begin function _Z5CheckPhS_
.p2align 4, 0x90
.type _Z5CheckPhS_,@function
_Z5CheckPhS_: # @_Z5CheckPhS_
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $_ZSt4cout, %edi
movl $.L.str.15, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movzbl (%r14), %eax
cmpb (%rbx), %al
jne .LBB7_7
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %rcx, %rax
cmpq $143, %rcx
je .LBB7_4
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB7_2 Depth=1
movzbl 1(%r14,%rax), %edx
leaq 1(%rax), %rcx
cmpb 1(%rbx,%rax), %dl
je .LBB7_2
.LBB7_4: # %_Z7IsEqualPhS_m.exit
cmpq $143, %rax
jb .LBB7_7
# %bb.5:
movl $_ZSt4cout, %edi
movl $.L.str.16, %esi
movl $17, %edx
jmp .LBB7_6
.LBB7_7: # %.critedge
movl $_ZSt4cout, %edi
movl $.L.str.17, %esi
movl $10, %edx
.LBB7_6:
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l # TAILCALL
.Lfunc_end7:
.size _Z5CheckPhS_, .Lfunc_end7-_Z5CheckPhS_
.cfi_endproc
# -- End function
.globl _Z10InfoResultPhS_ # -- Begin function _Z10InfoResultPhS_
.p2align 4, 0x90
.type _Z10InfoResultPhS_,@function
_Z10InfoResultPhS_: # @_Z10InfoResultPhS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl $_ZSt4cout, %edi
movl $.L.str.18, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB8_9
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB8_3
# %bb.2:
movzbl 67(%r15), %eax
jmp .LBB8_4
.LBB8_3:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r14, %rdi
callq _Z11PrintVectorPhm
movl $_ZSt4cout, %edi
movl $.L.str.19, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB8_9
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i3
cmpb $0, 56(%r14)
je .LBB8_7
# %bb.6:
movzbl 67(%r14), %eax
jmp .LBB8_8
.LBB8_7:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB8_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit6
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp _Z11PrintVectorPhm # TAILCALL
.LBB8_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end8:
.size _Z10InfoResultPhS_, .Lfunc_end8-_Z10InfoResultPhS_
.cfi_endproc
# -- End function
.globl _Z7IsEqualPhS_m # -- Begin function _Z7IsEqualPhS_m
.p2align 4, 0x90
.type _Z7IsEqualPhS_m,@function
_Z7IsEqualPhS_m: # @_Z7IsEqualPhS_m
.cfi_startproc
# %bb.0:
testq %rdx, %rdx
sete %al
je .LBB9_6
# %bb.1: # %.lr.ph.preheader
movzbl (%rdi), %ecx
cmpb (%rsi), %cl
jne .LBB9_6
# %bb.2: # %.lr.ph16.preheader
movl $1, %ecx
.p2align 4, 0x90
.LBB9_3: # %.lr.ph16
# =>This Inner Loop Header: Depth=1
movq %rcx, %rax
cmpq %rcx, %rdx
je .LBB9_5
# %bb.4: # %.lr.ph
# in Loop: Header=BB9_3 Depth=1
movzbl (%rdi,%rax), %r8d
leaq 1(%rax), %rcx
cmpb (%rsi,%rax), %r8b
je .LBB9_3
.LBB9_5: # %._crit_edge.loopexit
cmpq %rdx, %rax
setae %al
.LBB9_6: # %._crit_edge
retq
.Lfunc_end9:
.size _Z7IsEqualPhS_m, .Lfunc_end9-_Z7IsEqualPhS_m
.cfi_endproc
# -- End function
.globl _Z11PrintVectorPhm # -- Begin function _Z11PrintVectorPhm
.p2align 4, 0x90
.type _Z11PrintVectorPhm,@function
_Z11PrintVectorPhm: # @_Z11PrintVectorPhm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
jmp .LBB10_1
.p2align 4, 0x90
.LBB10_6: # in Loop: Header=BB10_1 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB10_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB10_1 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $12, %rbx
cmpq $12, %r15
je .LBB10_8
.LBB10_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB10_2 Depth 2
movq $-12, %r14
.p2align 4, 0x90
.LBB10_2: # Parent Loop BB10_1 Depth=1
# => This Inner Loop Header: Depth=2
movzbl 12(%rbx,%r14), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.22, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
jne .LBB10_2
# %bb.3: # in Loop: Header=BB10_1 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB10_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB10_1 Depth=1
cmpb $0, 56(%r14)
je .LBB10_6
# %bb.5: # in Loop: Header=BB10_1 Depth=1
movzbl 67(%r14), %eax
jmp .LBB10_7
.LBB10_8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB10_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end10:
.size _Z11PrintVectorPhm, .Lfunc_end10-_Z11PrintVectorPhm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24calculate_GramMatrix_GPUPhS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24calculate_GramMatrix_GPUPhS_,@object # @_Z24calculate_GramMatrix_GPUPhS_
.section .rodata,"a",@progbits
.globl _Z24calculate_GramMatrix_GPUPhS_
.p2align 3, 0x0
_Z24calculate_GramMatrix_GPUPhS_:
.quad _Z39__device_stub__calculate_GramMatrix_GPUPhS_
.size _Z24calculate_GramMatrix_GPUPhS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nSize Gram matrix: "
.size .L.str, 20
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n\n"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n--------\n"
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time CPU: "
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time GPU: "
.size .L.str.4, 11
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\n---------\n"
.size .L.str.5, 12
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error:"
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " at line "
.size .L.str.7, 10
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " in file "
.size .L.str.8, 10
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/Tessecrack/CUDA_DEV/main/GramMatrix/GramMatrixOptimizeCPU.hip"
.size .L.str.9, 119
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\n"
.size .L.str.10, 2
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Calculate on DEVICE...\n"
.size .L.str.11, 24
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Count of blocks: "
.size .L.str.12, 18
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Done\n"
.size .L.str.13, 6
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Calculate on HOST...\n"
.size .L.str.14, 22
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "\nCheck...\n"
.size .L.str.15, 11
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "That's right! :)\n"
.size .L.str.16, 18
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Wrong! :(\n"
.size .L.str.17, 11
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "\nGram matrix CPU: "
.size .L.str.18, 19
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "\nGram matrix GPU: "
.size .L.str.19, 19
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "\nBig vector:\n\n"
.size .L.str.20, 15
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " "
.size .L.str.21, 2
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "\t"
.size .L.str.22, 2
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "Size of system: "
.size .L.str.23, 17
.type .L.str.24,@object # @.str.24
.L.str.24:
.asciz "\nCount of vectors: "
.size .L.str.24, 20
.type .L.str.25,@object # @.str.25
.L.str.25:
.asciz "\nCount of elements in one vector: "
.size .L.str.25, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24calculate_GramMatrix_GPUPhS_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__calculate_GramMatrix_GPUPhS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z24calculate_GramMatrix_GPUPhS_
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z24calculate_GramMatrix_GPUPhS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R0 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x8f, PT ; /* 0x0000008f0600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.HI R2, R6, 0x2aaaaaab, RZ ; /* 0x2aaaaaab06027827 */
/* 0x000fe200078e02ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LDS.U8 R4, [R0] ; /* 0x0000000000047984 */
/* 0x000e220000000000 */
/*0090*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff037819 */
/* 0x000fc80000011402 */
/*00b0*/ LEA.HI R3, R2, R3, RZ, 0x1 ; /* 0x0000000302037211 */
/* 0x000fca00078f08ff */
/*00c0*/ IMAD R7, R3.reuse, 0x55, RZ ; /* 0x0000005503077824 */
/* 0x040fe400078e02ff */
/*00d0*/ IMAD R8, R3, -0xc, R6 ; /* 0xfffffff403087824 */
/* 0x000fc600078e0206 */
/*00e0*/ SHF.R.S32.HI R16, RZ, 0x1f, R7 ; /* 0x0000001fff107819 */
/* 0x000fe20000011407 */
/*00f0*/ IMAD R8, R8, 0x55, RZ ; /* 0x0000005508087824 */
/* 0x000fe200078e02ff */
/*0100*/ IADD3 R10, P1, R7, c[0x0][0x160], RZ ; /* 0x00005800070a7a10 */
/* 0x000fc80007f3e0ff */
/*0110*/ IADD3.X R11, R16, c[0x0][0x164], RZ, P1, !PT ; /* 0x00005900100b7a10 */
/* 0x000fe40000ffe4ff */
/*0120*/ SHF.R.S32.HI R17, RZ, 0x1f, R8 ; /* 0x0000001fff117819 */
/* 0x000fe40000011408 */
/*0130*/ IADD3 R14, P0, R8, c[0x0][0x160], RZ ; /* 0x00005800080e7a10 */
/* 0x000fe40007f1e0ff */
/*0140*/ MOV R2, R10 ; /* 0x0000000a00027202 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R3, R11 ; /* 0x0000000b00037202 */
/* 0x000fe40000000f00 */
/*0160*/ IADD3.X R13, R17, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900110d7a10 */
/* 0x000fc600007fe4ff */
/*0170*/ LDG.E.U8 R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000224000c1e1100 */
/*0180*/ MOV R2, R14 ; /* 0x0000000e00027202 */
/* 0x002fe40000000f00 */
/*0190*/ MOV R3, R13 ; /* 0x0000000d00037202 */
/* 0x000fca0000000f00 */
/*01a0*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000e24000c1e1100 */
/*01b0*/ IMAD R4, R5, R9, R4 ; /* 0x0000000905047224 */
/* 0x001fe200078e0204 */
/*01c0*/ HFMA2.MMA R9, -RZ, RZ, 0, 0 ; /* 0x00000000ff097435 */
/* 0x000fc800000001ff */
/*01d0*/ PRMT R15, R4, 0x7610, R15 ; /* 0x00007610040f7816 */
/* 0x000fe4000000000f */
/*01e0*/ MOV R12, R14 ; /* 0x0000000e000c7202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E.U8 R19, [R10.64+0x1] ; /* 0x000001040a137981 */
/* 0x0000a8000c1e1100 */
/*0200*/ LDG.E.U8 R18, [R12.64+0x1] ; /* 0x000001040c127981 */
/* 0x0002a8000c1e1100 */
/*0210*/ LDG.E.U8 R21, [R12.64+0x2] ; /* 0x000002040c157981 */
/* 0x0002e8000c1e1100 */
/*0220*/ LDG.E.U8 R20, [R10.64+0x2] ; /* 0x000002040a147981 */
/* 0x0000e2000c1e1100 */
/*0230*/ IADD3 R2, P0, R8, UR6, RZ ; /* 0x0000000608027c10 */
/* 0x000fc4000ff1e0ff */
/*0240*/ IADD3 R4, P1, R7, UR6, RZ ; /* 0x0000000607047c10 */
/* 0x000fe2000ff3e0ff */
/*0250*/ LDG.E.U8 R14, [R12.64+0x3] ; /* 0x000003040c0e7981 */
/* 0x000322000c1e1100 */
/*0260*/ IADD3.X R3, R17, UR7, RZ, P0, !PT ; /* 0x0000000711037c10 */
/* 0x000fe400087fe4ff */
/*0270*/ IADD3.X R5, R16, UR7, RZ, P1, !PT ; /* 0x0000000710057c10 */
/* 0x000fe20008ffe4ff */
/*0280*/ LDG.E.U8 R22, [R10.64+0x3] ; /* 0x000003040a167981 */
/* 0x000128000c1e1100 */
/*0290*/ LDG.E.U8 R23, [R2.64+0x4] ; /* 0x0000040402177981 */
/* 0x000f68000c1e1100 */
/*02a0*/ LDG.E.U8 R24, [R4.64+0x4] ; /* 0x0000040404187981 */
/* 0x000f68000c1e1100 */
/*02b0*/ LDG.E.U8 R25, [R4.64+0x5] ; /* 0x0000050404197981 */
/* 0x000f68000c1e1100 */
/*02c0*/ LDG.E.U8 R27, [R2.64+0x6] ; /* 0x00000604021b7981 */
/* 0x000f68000c1e1100 */
/*02d0*/ LDG.E.U8 R12, [R4.64+0x7] ; /* 0x00000704040c7981 */
/* 0x002f68000c1e1100 */
/*02e0*/ LDG.E.U8 R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x001f68000c1e1100 */
/*02f0*/ LDG.E.U8 R11, [R4.64+0x8] ; /* 0x00000804040b7981 */
/* 0x000f68000c1e1100 */
/*0300*/ LDG.E.U8 R13, [R2.64+0xc] ; /* 0x00000c04020d7981 */
/* 0x000f62000c1e1100 */
/*0310*/ IMAD R18, R18, R19, R15 ; /* 0x0000001312127224 */
/* 0x004fc600078e020f */
/*0320*/ LDG.E.U8 R19, [R2.64+0x5] ; /* 0x0000050402137981 */
/* 0x000ea8000c1e1100 */
/*0330*/ LDG.E.U8 R15, [R2.64+0x7] ; /* 0x00000704020f7981 */
/* 0x000ea2000c1e1100 */
/*0340*/ IMAD R21, R21, R20, R18 ; /* 0x0000001415157224 */
/* 0x008fc600078e0212 */
/*0350*/ LDG.E.U8 R18, [R4.64+0x6] ; /* 0x0000060404127981 */
/* 0x000ee8000c1e1100 */
/*0360*/ LDG.E.U8 R20, [R4.64+0x9] ; /* 0x0000090404147981 */
/* 0x000ee2000c1e1100 */
/*0370*/ IMAD R14, R14, R22, R21 ; /* 0x000000160e0e7224 */
/* 0x010fc600078e0215 */
/*0380*/ LDG.E.U8 R21, [R4.64+0xa] ; /* 0x00000a0404157981 */
/* 0x000f28000c1e1100 */
/*0390*/ LDG.E.U8 R22, [R4.64+0xb] ; /* 0x00000b0404167981 */
/* 0x000f22000c1e1100 */
/*03a0*/ IMAD R14, R23, R24, R14 ; /* 0x00000018170e7224 */
/* 0x020fc600078e020e */
/*03b0*/ LDG.E.U8 R23, [R2.64+0x10] ; /* 0x0000100402177981 */
/* 0x000f62000c1e1100 */
/*03c0*/ IMAD R14, R19, R25, R14 ; /* 0x00000019130e7224 */
/* 0x004fc600078e020e */
/*03d0*/ LDG.E.U8 R19, [R2.64+0x9] ; /* 0x0000090402137981 */
/* 0x000ea2000c1e1100 */
/*03e0*/ IMAD R14, R27, R18, R14 ; /* 0x000000121b0e7224 */
/* 0x008fc600078e020e */
/*03f0*/ LDG.E.U8 R18, [R2.64+0xa] ; /* 0x00000a0402127981 */
/* 0x000f22000c1e1100 */
/*0400*/ IMAD R14, R15, R12, R14 ; /* 0x0000000c0f0e7224 */
/* 0x000fc600078e020e */
/*0410*/ LDG.E.U8 R15, [R2.64+0xb] ; /* 0x00000b04020f7981 */
/* 0x000ee8000c1e1100 */
/*0420*/ LDG.E.U8 R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000f62000c1e1100 */
/*0430*/ IMAD R10, R10, R11, R14 ; /* 0x0000000b0a0a7224 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E.U8 R11, [R4.64+0xd] ; /* 0x00000d04040b7981 */
/* 0x000f68000c1e1100 */
/*0450*/ LDG.E.U8 R14, [R4.64+0xe] ; /* 0x00000e04040e7981 */
/* 0x000f62000c1e1100 */
/*0460*/ IMAD R19, R19, R20, R10 ; /* 0x0000001413137224 */
/* 0x004fc600078e020a */
/*0470*/ LDG.E.U8 R10, [R2.64+0xd] ; /* 0x00000d04020a7981 */
/* 0x000ea8000c1e1100 */
/*0480*/ LDG.E.U8 R20, [R4.64+0x10] ; /* 0x0000100404147981 */
/* 0x000ea2000c1e1100 */
/*0490*/ IMAD R18, R18, R21, R19 ; /* 0x0000001512127224 */
/* 0x010fc600078e0213 */
/*04a0*/ LDG.E.U8 R19, [R2.64+0xe] ; /* 0x00000e0402137981 */
/* 0x000f22000c1e1100 */
/*04b0*/ IMAD R15, R15, R22, R18 ; /* 0x000000160f0f7224 */
/* 0x008fc600078e0212 */
/*04c0*/ LDG.E.U8 R21, [R2.64+0xf] ; /* 0x00000f0402157981 */
/* 0x000ee8000c1e1100 */
/*04d0*/ LDG.E.U8 R18, [R4.64+0xf] ; /* 0x00000f0404127981 */
/* 0x000ee2000c1e1100 */
/*04e0*/ IMAD R15, R13, R12, R15 ; /* 0x0000000c0d0f7224 */
/* 0x020fc600078e020f */
/*04f0*/ LDG.E.U8 R13, [R2.64+0x11] ; /* 0x00001104020d7981 */
/* 0x000f68000c1e1100 */
/*0500*/ LDG.E.U8 R12, [R4.64+0x11] ; /* 0x00001104040c7981 */
/* 0x000f68000c1e1100 */
/*0510*/ LDG.E.U8 R22, [R2.64+0x15] ; /* 0x0000150402167981 */
/* 0x000f62000c1e1100 */
/*0520*/ IMAD R10, R10, R11, R15 ; /* 0x0000000b0a0a7224 */
/* 0x004fc600078e020f */
/*0530*/ LDG.E.U8 R11, [R2.64+0x12] ; /* 0x00001204020b7981 */
/* 0x000ea8000c1e1100 */
/*0540*/ LDG.E.U8 R15, [R2.64+0x13] ; /* 0x00001304020f7981 */
/* 0x000ea2000c1e1100 */
/*0550*/ IMAD R14, R19, R14, R10 ; /* 0x0000000e130e7224 */
/* 0x010fc600078e020a */
/*0560*/ LDG.E.U8 R10, [R4.64+0x12] ; /* 0x00001204040a7981 */
/* 0x000ea8000c1e1100 */
/*0570*/ LDG.E.U8 R19, [R4.64+0x14] ; /* 0x0000140404137981 */
/* 0x000f22000c1e1100 */
/*0580*/ IMAD R14, R21, R18, R14 ; /* 0x00000012150e7224 */
/* 0x008fc600078e020e */
/*0590*/ LDG.E.U8 R18, [R4.64+0x13] ; /* 0x0000130404127981 */
/* 0x000ee2000c1e1100 */
/*05a0*/ IMAD R14, R23, R20, R14 ; /* 0x00000014170e7224 */
/* 0x000fc600078e020e */
/*05b0*/ LDG.E.U8 R20, [R2.64+0x14] ; /* 0x0000140402147981 */
/* 0x000f28000c1e1100 */
/*05c0*/ LDG.E.U8 R21, [R4.64+0x15] ; /* 0x0000150404157981 */
/* 0x000f22000c1e1100 */
/*05d0*/ IMAD R14, R13, R12, R14 ; /* 0x0000000c0d0e7224 */
/* 0x020fc600078e020e */
/*05e0*/ LDG.E.U8 R12, [R2.64+0x16] ; /* 0x00001604020c7981 */
/* 0x000f68000c1e1100 */
/*05f0*/ LDG.E.U8 R13, [R4.64+0x16] ; /* 0x00001604040d7981 */
/* 0x000f68000c1e1100 */
/*0600*/ LDG.E.U8 R23, [R2.64+0x1c] ; /* 0x00001c0402177981 */
/* 0x000f62000c1e1100 */
/*0610*/ IMAD R10, R11, R10, R14 ; /* 0x0000000a0b0a7224 */
/* 0x004fc600078e020e */
/*0620*/ LDG.E.U8 R11, [R4.64+0x17] ; /* 0x00001704040b7981 */
/* 0x000ea8000c1e1100 */
/*0630*/ LDG.E.U8 R14, [R4.64+0x18] ; /* 0x00001804040e7981 */
/* 0x000ea2000c1e1100 */
/*0640*/ IMAD R15, R15, R18, R10 ; /* 0x000000120f0f7224 */
/* 0x008fc600078e020a */
/*0650*/ LDG.E.U8 R10, [R2.64+0x17] ; /* 0x00001704020a7981 */
/* 0x000ea2000c1e1100 */
/*0660*/ IMAD R19, R20, R19, R15 ; /* 0x0000001314137224 */
/* 0x010fc600078e020f */
/*0670*/ LDG.E.U8 R15, [R2.64+0x18] ; /* 0x00001804020f7981 */
/* 0x000ee2000c1e1100 */
/*0680*/ IMAD R21, R22, R21, R19 ; /* 0x0000001516157224 */
/* 0x000fc600078e0213 */
/*0690*/ LDG.E.U8 R18, [R2.64+0x19] ; /* 0x0000190402127981 */
/* 0x000f28000c1e1100 */
/*06a0*/ LDG.E.U8 R19, [R4.64+0x19] ; /* 0x0000190404137981 */
/* 0x000f22000c1e1100 */
/*06b0*/ IMAD R24, R12, R13, R21 ; /* 0x0000000d0c187224 */
/* 0x020fc600078e0215 */
/*06c0*/ LDG.E.U8 R13, [R2.64+0x1a] ; /* 0x00001a04020d7981 */
/* 0x000f68000c1e1100 */
/*06d0*/ LDG.E.U8 R12, [R4.64+0x1a] ; /* 0x00001a04040c7981 */
/* 0x000f68000c1e1100 */
/*06e0*/ LDG.E.U8 R21, [R2.64+0x1b] ; /* 0x00001b0402157981 */
/* 0x000f68000c1e1100 */
/*06f0*/ LDG.E.U8 R20, [R4.64+0x1b] ; /* 0x00001b0404147981 */
/* 0x000f68000c1e1100 */
/*0700*/ LDG.E.U8 R22, [R4.64+0x1c] ; /* 0x00001c0404167981 */
/* 0x000f62000c1e1100 */
/*0710*/ IADD3 R9, R9, 0x1c, RZ ; /* 0x0000001c09097810 */
/* 0x000fc80007ffe0ff */
/*0720*/ ISETP.NE.AND P0, PT, R9, 0x54, PT ; /* 0x000000540900780c */
/* 0x000fe20003f05270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x1c, URZ ; /* 0x0000001c06067890 */
/* 0x000fc8000ff1e03f */
/*0740*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0750*/ IMAD R10, R10, R11, R24 ; /* 0x0000000b0a0a7224 */
/* 0x004fc800078e0218 */
/*0760*/ IMAD R10, R15, R14, R10 ; /* 0x0000000e0f0a7224 */
/* 0x008fc800078e020a */
/*0770*/ IMAD R18, R18, R19, R10 ; /* 0x0000001312127224 */
/* 0x010fc800078e020a */
/*0780*/ IMAD R12, R13, R12, R18 ; /* 0x0000000c0d0c7224 */
/* 0x020fe200078e0212 */
/*0790*/ IADD3 R14, P1, R2, 0x1c, RZ ; /* 0x0000001c020e7810 */
/* 0x000fe40007f3e0ff */
/*07a0*/ IADD3 R10, P2, R4, 0x1c, RZ ; /* 0x0000001c040a7810 */
/* 0x000fe20007f5e0ff */
/*07b0*/ IMAD R12, R21, R20, R12 ; /* 0x00000014150c7224 */
/* 0x000fc800078e020c */
/*07c0*/ IMAD R12, R23, R22, R12 ; /* 0x00000016170c7224 */
/* 0x000fe200078e020c */
/*07d0*/ IADD3.X R13, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0d7210 */
/* 0x000fe40000ffe4ff */
/*07e0*/ IADD3.X R11, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0b7210 */
/* 0x000fe400017fe4ff */
/*07f0*/ PRMT R15, R12, 0x7610, R15 ; /* 0x000076100c0f7816 */
/* 0x000fe2000000000f */
/*0800*/ @P0 BRA 0x1e0 ; /* 0xfffff9d000000947 */
/* 0x000fea000383ffff */
/*0810*/ STS.U8 [R0], R15 ; /* 0x0000000f00007388 */
/* 0x000fe80000000000 */
/*0820*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0830*/ IADD3 R2, P0, R6, c[0x0][0x168], RZ ; /* 0x00005a0006027a10 */
/* 0x000fc80007f1e0ff */
/*0840*/ LEA.HI.X.SX32 R3, R6, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0006037a11 */
/* 0x000fe200000f0eff */
/*0850*/ LDS.U8 R5, [R0] ; /* 0x0000000000057984 */
/* 0x000e280000000000 */
/*0860*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101104 */
/*0870*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0880*/ BRA 0x880; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24calculate_GramMatrix_GPUPhS_
.globl _Z24calculate_GramMatrix_GPUPhS_
.p2align 8
.type _Z24calculate_GramMatrix_GPUPhS_,@function
_Z24calculate_GramMatrix_GPUPhS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x90, v1
s_cbranch_execz .LBB0_4
v_mul_hi_i32 v2, v1, 0x2aaaaaab
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b64 s[4:5], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v3, 31, v2
v_ashrrev_i32_e32 v2, 1, v2
v_add_nc_u32_e32 v3, v2, v3
ds_load_u8 v2, v0
v_mul_lo_u32 v4, v3, 12
v_mul_lo_u32 v5, v3, 0x55
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v1, v4
v_ashrrev_i32_e32 v6, 31, v5
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v3, v3, 0x55
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v8, s4, v3
v_add_co_u32 v6, vcc_lo, v4, s4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
v_ashrrev_i32_e32 v9, 31, v8
v_add_co_u32 v8, vcc_lo, s2, v8
s_add_u32 s4, s4, 1
s_addc_u32 s5, s5, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
s_cmpk_eq_i32 s4, 0x55
s_clause 0x1
global_load_u8 v6, v[6:7], off
global_load_u8 v7, v[8:9], off
s_waitcnt vmcnt(0)
v_mad_u16 v2, v7, v6, v2
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
ds_store_b8 v0, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_u8 v2, v0
v_ashrrev_i32_e32 v3, 31, v1
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt lgkmcnt(0)
global_store_b8 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24calculate_GramMatrix_GPUPhS_
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24calculate_GramMatrix_GPUPhS_, .Lfunc_end0-_Z24calculate_GramMatrix_GPUPhS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24calculate_GramMatrix_GPUPhS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24calculate_GramMatrix_GPUPhS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void fill_one(float * prp_0,int sz)
{
// Thread index
int tx = threadIdx.x + blockIdx.x * blockDim.x;
int ty = threadIdx.y + blockIdx.y * blockDim.y;
int tz = threadIdx.z + blockIdx.z * blockDim.z;
prp_0[tz*sz*sz + ty*sz + tx] = 1.0f;
} | code for sm_80
Function : _Z8fill_onePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0040*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e680000002300 */
/*0050*/ S2R R7, SR_CTAID.Z ; /* 0x0000000000077919 */
/* 0x000e680000002700 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000ea80000002100 */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002500 */
/*0080*/ IMAD R2, R3, c[0x0][0x4], R2 ; /* 0x0000010003027a24 */
/* 0x001fc400078e0202 */
/*0090*/ IMAD R3, R7, c[0x0][0x8], R4 ; /* 0x0000020007037a24 */
/* 0x002fc800078e0204 */
/*00a0*/ IMAD R3, R3, c[0x0][0x168], R2 ; /* 0x00005a0003037a24 */
/* 0x000fe200078e0202 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x004fe200078e0200 */
/*00d0*/ MOV R5, 0x3f800000 ; /* 0x3f80000000057802 */
/* 0x000fc60000000f00 */
/*00e0*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*00f0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void fill_one(float * prp_0,int sz)
{
// Thread index
int tx = threadIdx.x + blockIdx.x * blockDim.x;
int ty = threadIdx.y + blockIdx.y * blockDim.y;
int tz = threadIdx.z + blockIdx.z * blockDim.z;
prp_0[tz*sz*sz + ty*sz + tx] = 1.0f;
} | .file "tmpxft_0018063c_00000000-6_fill_one.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8fill_onePfiPfi
.type _Z28__device_stub__Z8fill_onePfiPfi, @function
_Z28__device_stub__Z8fill_onePfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8fill_onePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z8fill_onePfiPfi, .-_Z28__device_stub__Z8fill_onePfiPfi
.globl _Z8fill_onePfi
.type _Z8fill_onePfi, @function
_Z8fill_onePfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8fill_onePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8fill_onePfi, .-_Z8fill_onePfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8fill_onePfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8fill_onePfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void fill_one(float * prp_0,int sz)
{
// Thread index
int tx = threadIdx.x + blockIdx.x * blockDim.x;
int ty = threadIdx.y + blockIdx.y * blockDim.y;
int tz = threadIdx.z + blockIdx.z * blockDim.z;
prp_0[tz*sz*sz + ty*sz + tx] = 1.0f;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill_one(float * prp_0,int sz)
{
// Thread index
int tx = threadIdx.x + blockIdx.x * blockDim.x;
int ty = threadIdx.y + blockIdx.y * blockDim.y;
int tz = threadIdx.z + blockIdx.z * blockDim.z;
prp_0[tz*sz*sz + ty*sz + tx] = 1.0f;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill_one(float * prp_0,int sz)
{
// Thread index
int tx = threadIdx.x + blockIdx.x * blockDim.x;
int ty = threadIdx.y + blockIdx.y * blockDim.y;
int tz = threadIdx.z + blockIdx.z * blockDim.z;
prp_0[tz*sz*sz + ty*sz + tx] = 1.0f;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8fill_onePfi
.globl _Z8fill_onePfi
.p2align 8
.type _Z8fill_onePfi,@function
_Z8fill_onePfi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
v_bfe_u32 v1, v0, 20, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s14, s14, s3
s_mul_i32 s13, s13, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v2, s4
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_add3_u32 v1, s14, v2, v1
v_mov_b32_e32 v2, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s4
v_add3_u32 v0, s13, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8fill_onePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8fill_onePfi, .Lfunc_end0-_Z8fill_onePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8fill_onePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8fill_onePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void fill_one(float * prp_0,int sz)
{
// Thread index
int tx = threadIdx.x + blockIdx.x * blockDim.x;
int ty = threadIdx.y + blockIdx.y * blockDim.y;
int tz = threadIdx.z + blockIdx.z * blockDim.z;
prp_0[tz*sz*sz + ty*sz + tx] = 1.0f;
} | .text
.file "fill_one.hip"
.globl _Z23__device_stub__fill_onePfi # -- Begin function _Z23__device_stub__fill_onePfi
.p2align 4, 0x90
.type _Z23__device_stub__fill_onePfi,@function
_Z23__device_stub__fill_onePfi: # @_Z23__device_stub__fill_onePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8fill_onePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__fill_onePfi, .Lfunc_end0-_Z23__device_stub__fill_onePfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8fill_onePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8fill_onePfi,@object # @_Z8fill_onePfi
.section .rodata,"a",@progbits
.globl _Z8fill_onePfi
.p2align 3, 0x0
_Z8fill_onePfi:
.quad _Z23__device_stub__fill_onePfi
.size _Z8fill_onePfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8fill_onePfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__fill_onePfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8fill_onePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8fill_onePfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0040*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e680000002300 */
/*0050*/ S2R R7, SR_CTAID.Z ; /* 0x0000000000077919 */
/* 0x000e680000002700 */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000ea80000002100 */
/*0070*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000ea20000002500 */
/*0080*/ IMAD R2, R3, c[0x0][0x4], R2 ; /* 0x0000010003027a24 */
/* 0x001fc400078e0202 */
/*0090*/ IMAD R3, R7, c[0x0][0x8], R4 ; /* 0x0000020007037a24 */
/* 0x002fc800078e0204 */
/*00a0*/ IMAD R3, R3, c[0x0][0x168], R2 ; /* 0x00005a0003037a24 */
/* 0x000fe200078e0202 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x004fe200078e0200 */
/*00d0*/ MOV R5, 0x3f800000 ; /* 0x3f80000000057802 */
/* 0x000fc60000000f00 */
/*00e0*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fca00078e0200 */
/*00f0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8fill_onePfi
.globl _Z8fill_onePfi
.p2align 8
.type _Z8fill_onePfi,@function
_Z8fill_onePfi:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x8
v_bfe_u32 v1, v0, 20, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_mul_i32 s14, s14, s3
s_mul_i32 s13, s13, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mul_lo_u32 v1, v2, s4
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
v_add3_u32 v1, s14, v2, v1
v_mov_b32_e32 v2, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v1, s4
v_add3_u32 v0, s13, v0, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8fill_onePfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8fill_onePfi, .Lfunc_end0-_Z8fill_onePfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8fill_onePfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8fill_onePfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018063c_00000000-6_fill_one.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z8fill_onePfiPfi
.type _Z28__device_stub__Z8fill_onePfiPfi, @function
_Z28__device_stub__Z8fill_onePfiPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8fill_onePfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z8fill_onePfiPfi, .-_Z28__device_stub__Z8fill_onePfiPfi
.globl _Z8fill_onePfi
.type _Z8fill_onePfi, @function
_Z8fill_onePfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z8fill_onePfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8fill_onePfi, .-_Z8fill_onePfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8fill_onePfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8fill_onePfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "fill_one.hip"
.globl _Z23__device_stub__fill_onePfi # -- Begin function _Z23__device_stub__fill_onePfi
.p2align 4, 0x90
.type _Z23__device_stub__fill_onePfi,@function
_Z23__device_stub__fill_onePfi: # @_Z23__device_stub__fill_onePfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8fill_onePfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z23__device_stub__fill_onePfi, .Lfunc_end0-_Z23__device_stub__fill_onePfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8fill_onePfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8fill_onePfi,@object # @_Z8fill_onePfi
.section .rodata,"a",@progbits
.globl _Z8fill_onePfi
.p2align 3, 0x0
_Z8fill_onePfi:
.quad _Z23__device_stub__fill_onePfi
.size _Z8fill_onePfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8fill_onePfi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__fill_onePfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8fill_onePfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "stdio.h"
#define DIM 8
const int THREADS_PER_BLOCK = 8;
const int NUM_BLOCKS = 8;
__global__ void add(int *a, int *c)
{
__shared__ int cache[THREADS_PER_BLOCK];
int tid = threadIdx.x + (blockIdx.x * blockDim.x);
int cacheIndex = threadIdx.x;
int temp = 0;
temp = a[tid];
cache[cacheIndex] = temp;
int i = blockDim.x / 2;
while (i > 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (threadIdx.x == 0) // if at thread 0 in this block
c[blockIdx.x] = cache[0]; // save the sum in global memory
}
int main()
{
int a[DIM][DIM], c[DIM];
int *dev_a, *dev_c;
cudaMalloc((void **)&dev_a, DIM * DIM * sizeof(int));
cudaMalloc((void **)&dev_c, DIM * sizeof(int));
for (int y = 0; y < DIM; y++) // Fill Arrays
for (int x = 0; x < DIM; x++)
a[y][x] = 7;
for (int i = 0; i < DIM; ++i)
{
c[i] = 0;
}
cudaMemcpy(dev_a, a, DIM * DIM * sizeof(int), cudaMemcpyHostToDevice);
add<<<NUM_BLOCKS, THREADS_PER_BLOCK>>>(dev_a, dev_c);
cudaMemcpy(c, dev_c, DIM * sizeof(int), cudaMemcpyDeviceToHost);
int total = 0;
for (int i = 0; i < DIM; ++i)
{
total += c[i];
}
printf("Total sum of all elements is: %d\n", total);
cudaFree(dev_a);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041d80000004800 */
/*00d0*/ @!P1 BRA 0x1a0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0100*/ ISETP.GE.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26270 */
/*0110*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x001fe200078e0200 */
/*0120*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0130*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0140*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0150*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0160*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0190*/ @P1 BRA 0x100 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*01c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fca00078e0003 */
/*01e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "stdio.h"
#define DIM 8
const int THREADS_PER_BLOCK = 8;
const int NUM_BLOCKS = 8;
__global__ void add(int *a, int *c)
{
__shared__ int cache[THREADS_PER_BLOCK];
int tid = threadIdx.x + (blockIdx.x * blockDim.x);
int cacheIndex = threadIdx.x;
int temp = 0;
temp = a[tid];
cache[cacheIndex] = temp;
int i = blockDim.x / 2;
while (i > 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (threadIdx.x == 0) // if at thread 0 in this block
c[blockIdx.x] = cache[0]; // save the sum in global memory
}
int main()
{
int a[DIM][DIM], c[DIM];
int *dev_a, *dev_c;
cudaMalloc((void **)&dev_a, DIM * DIM * sizeof(int));
cudaMalloc((void **)&dev_c, DIM * sizeof(int));
for (int y = 0; y < DIM; y++) // Fill Arrays
for (int x = 0; x < DIM; x++)
a[y][x] = 7;
for (int i = 0; i < DIM; ++i)
{
c[i] = 0;
}
cudaMemcpy(dev_a, a, DIM * DIM * sizeof(int), cudaMemcpyHostToDevice);
add<<<NUM_BLOCKS, THREADS_PER_BLOCK>>>(dev_a, dev_c);
cudaMemcpy(c, dev_c, DIM * sizeof(int), cudaMemcpyDeviceToHost);
int total = 0;
for (int i = 0; i < DIM; ++i)
{
total += c[i];
}
printf("Total sum of all elements is: %d\n", total);
cudaFree(dev_a);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_000d7c9e_00000000-6_gjtalotta_prob4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addPiS_PiS_
.type _Z24__device_stub__Z3addPiS_PiS_, @function
_Z24__device_stub__Z3addPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addPiS_PiS_, .-_Z24__device_stub__Z3addPiS_PiS_
.globl _Z3addPiS_
.type _Z3addPiS_, @function
_Z3addPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_, .-_Z3addPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Total sum of all elements is: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $352, %rsp
.cfi_def_cfa_offset 368
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rax
leaq 336(%rsp), %rdx
.L12:
movl $7, (%rax)
movl $7, 4(%rax)
movl $7, 8(%rax)
movl $7, 12(%rax)
movl $7, 16(%rax)
movl $7, 20(%rax)
movl $7, 24(%rax)
movl $7, 28(%rax)
addq $32, %rax
cmpq %rax, %rdx
jne .L12
movl $0, 48(%rsp)
movl $0, 52(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
movl $0, 64(%rsp)
movl $0, 68(%rsp)
movl $0, 72(%rsp)
movl $0, 76(%rsp)
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 80(%rsp), %rsi
movl $0, %ecx
.L14:
addl (%rax), %ecx
movl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L14
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $352, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3addPiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z3addPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "stdio.h"
#define DIM 8
const int THREADS_PER_BLOCK = 8;
const int NUM_BLOCKS = 8;
__global__ void add(int *a, int *c)
{
__shared__ int cache[THREADS_PER_BLOCK];
int tid = threadIdx.x + (blockIdx.x * blockDim.x);
int cacheIndex = threadIdx.x;
int temp = 0;
temp = a[tid];
cache[cacheIndex] = temp;
int i = blockDim.x / 2;
while (i > 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (threadIdx.x == 0) // if at thread 0 in this block
c[blockIdx.x] = cache[0]; // save the sum in global memory
}
int main()
{
int a[DIM][DIM], c[DIM];
int *dev_a, *dev_c;
cudaMalloc((void **)&dev_a, DIM * DIM * sizeof(int));
cudaMalloc((void **)&dev_c, DIM * sizeof(int));
for (int y = 0; y < DIM; y++) // Fill Arrays
for (int x = 0; x < DIM; x++)
a[y][x] = 7;
for (int i = 0; i < DIM; ++i)
{
c[i] = 0;
}
cudaMemcpy(dev_a, a, DIM * DIM * sizeof(int), cudaMemcpyHostToDevice);
add<<<NUM_BLOCKS, THREADS_PER_BLOCK>>>(dev_a, dev_c);
cudaMemcpy(c, dev_c, DIM * sizeof(int), cudaMemcpyDeviceToHost);
int total = 0;
for (int i = 0; i < DIM; ++i)
{
total += c[i];
}
printf("Total sum of all elements is: %d\n", total);
cudaFree(dev_a);
cudaFree(dev_c);
return 0;
} | #include <hip/hip_runtime.h>
#include "stdio.h"
#define DIM 8
const int THREADS_PER_BLOCK = 8;
const int NUM_BLOCKS = 8;
__global__ void add(int *a, int *c)
{
__shared__ int cache[THREADS_PER_BLOCK];
int tid = threadIdx.x + (blockIdx.x * blockDim.x);
int cacheIndex = threadIdx.x;
int temp = 0;
temp = a[tid];
cache[cacheIndex] = temp;
int i = blockDim.x / 2;
while (i > 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (threadIdx.x == 0) // if at thread 0 in this block
c[blockIdx.x] = cache[0]; // save the sum in global memory
}
int main()
{
int a[DIM][DIM], c[DIM];
int *dev_a, *dev_c;
hipMalloc((void **)&dev_a, DIM * DIM * sizeof(int));
hipMalloc((void **)&dev_c, DIM * sizeof(int));
for (int y = 0; y < DIM; y++) // Fill Arrays
for (int x = 0; x < DIM; x++)
a[y][x] = 7;
for (int i = 0; i < DIM; ++i)
{
c[i] = 0;
}
hipMemcpy(dev_a, a, DIM * DIM * sizeof(int), hipMemcpyHostToDevice);
add<<<NUM_BLOCKS, THREADS_PER_BLOCK>>>(dev_a, dev_c);
hipMemcpy(c, dev_c, DIM * sizeof(int), hipMemcpyDeviceToHost);
int total = 0;
for (int i = 0; i < DIM; ++i)
{
total += c[i];
}
printf("Total sum of all elements is: %d\n", total);
hipFree(dev_a);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define DIM 8
const int THREADS_PER_BLOCK = 8;
const int NUM_BLOCKS = 8;
__global__ void add(int *a, int *c)
{
__shared__ int cache[THREADS_PER_BLOCK];
int tid = threadIdx.x + (blockIdx.x * blockDim.x);
int cacheIndex = threadIdx.x;
int temp = 0;
temp = a[tid];
cache[cacheIndex] = temp;
int i = blockDim.x / 2;
while (i > 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (threadIdx.x == 0) // if at thread 0 in this block
c[blockIdx.x] = cache[0]; // save the sum in global memory
}
int main()
{
int a[DIM][DIM], c[DIM];
int *dev_a, *dev_c;
hipMalloc((void **)&dev_a, DIM * DIM * sizeof(int));
hipMalloc((void **)&dev_c, DIM * sizeof(int));
for (int y = 0; y < DIM; y++) // Fill Arrays
for (int x = 0; x < DIM; x++)
a[y][x] = 7;
for (int i = 0; i < DIM; ++i)
{
c[i] = 0;
}
hipMemcpy(dev_a, a, DIM * DIM * sizeof(int), hipMemcpyHostToDevice);
add<<<NUM_BLOCKS, THREADS_PER_BLOCK>>>(dev_a, dev_c);
hipMemcpy(c, dev_c, DIM * sizeof(int), hipMemcpyDeviceToHost);
int total = 0;
for (int i = 0; i < DIM; ++i)
{
total += c[i];
}
printf("Total sum of all elements is: %d\n", total);
hipFree(dev_a);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_
.globl _Z3addPiS_
.p2align 8
.type _Z3addPiS_,@function
_Z3addPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_cbranch_scc0 .LBB0_5
.LBB0_1:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_4
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_, .Lfunc_end0-_Z3addPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "stdio.h"
#define DIM 8
const int THREADS_PER_BLOCK = 8;
const int NUM_BLOCKS = 8;
__global__ void add(int *a, int *c)
{
__shared__ int cache[THREADS_PER_BLOCK];
int tid = threadIdx.x + (blockIdx.x * blockDim.x);
int cacheIndex = threadIdx.x;
int temp = 0;
temp = a[tid];
cache[cacheIndex] = temp;
int i = blockDim.x / 2;
while (i > 0)
{
if (cacheIndex < i)
cache[cacheIndex] += cache[cacheIndex + i];
__syncthreads();
i /= 2;
}
if (threadIdx.x == 0) // if at thread 0 in this block
c[blockIdx.x] = cache[0]; // save the sum in global memory
}
int main()
{
int a[DIM][DIM], c[DIM];
int *dev_a, *dev_c;
hipMalloc((void **)&dev_a, DIM * DIM * sizeof(int));
hipMalloc((void **)&dev_c, DIM * sizeof(int));
for (int y = 0; y < DIM; y++) // Fill Arrays
for (int x = 0; x < DIM; x++)
a[y][x] = 7;
for (int i = 0; i < DIM; ++i)
{
c[i] = 0;
}
hipMemcpy(dev_a, a, DIM * DIM * sizeof(int), hipMemcpyHostToDevice);
add<<<NUM_BLOCKS, THREADS_PER_BLOCK>>>(dev_a, dev_c);
hipMemcpy(c, dev_c, DIM * sizeof(int), hipMemcpyDeviceToHost);
int total = 0;
for (int i = 0; i < DIM; ++i)
{
total += c[i];
}
printf("Total sum of all elements is: %d\n", total);
hipFree(dev_a);
hipFree(dev_c);
return 0;
} | .text
.file "gjtalotta_prob4.hip"
.globl _Z18__device_stub__addPiS_ # -- Begin function _Z18__device_stub__addPiS_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_,@function
_Z18__device_stub__addPiS_: # @_Z18__device_stub__addPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_, .Lfunc_end0-_Z18__device_stub__addPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $384, %rsp # imm = 0x180
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
leaq 128(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader24
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $7, (%rax,%rdx,4)
incq %rdx
cmpq $8, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $32, %rax
cmpq $8, %rcx
jne .LBB1_1
# %bb.4: # %.preheader.preheader
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
addl 96(%rsp,%rax,4), %ebx
incq %rax
cmpq $8, %rax
jne .LBB1_7
# %bb.8:
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $384, %rsp # imm = 0x180
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_,@object # @_Z3addPiS_
.section .rodata,"a",@progbits
.globl _Z3addPiS_
.p2align 3, 0x0
_Z3addPiS_:
.quad _Z18__device_stub__addPiS_
.size _Z3addPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Total sum of all elements is: %d\n"
.size .L.str, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0090*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00a0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00b0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf25270 */
/*00c0*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041d80000004800 */
/*00d0*/ @!P1 BRA 0x1a0 ; /* 0x000000c000009947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0100*/ ISETP.GE.AND P1, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f26270 */
/*0110*/ @!P1 IMAD R2, R3, 0x4, R0 ; /* 0x0000000403029824 */
/* 0x001fe200078e0200 */
/*0120*/ @!P1 LDS R4, [R7.X4] ; /* 0x0000000007049984 */
/* 0x000fe20000004800 */
/*0130*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fc60000011603 */
/*0140*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0150*/ @!P1 IADD3 R4, R4, R5, RZ ; /* 0x0000000504049210 */
/* 0x001fca0007ffe0ff */
/*0160*/ @!P1 STS [R7.X4], R4 ; /* 0x0000000407009388 */
/* 0x0001e80000004800 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0180*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f25270 */
/*0190*/ @P1 BRA 0x100 ; /* 0xffffff6000001947 */
/* 0x001fea000383ffff */
/*01a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e620000000800 */
/*01c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*01d0*/ IMAD.WIDE.U32 R2, R6, R3, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x001fca00078e0003 */
/*01e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x002fe2000c101906 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_
.globl _Z3addPiS_
.p2align 8
.type _Z3addPiS_,@function
_Z3addPiS_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_cmp_lt_u32 s3, 2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_cbranch_scc0 .LBB0_5
.LBB0_1:
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v0, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_b32 v1, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v0, v1, s[0:1]
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_gt_u32 s3, 3
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v2, s4, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
ds_store_b32 v1, v2
s_branch .LBB0_4
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_, .Lfunc_end0-_Z3addPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d7c9e_00000000-6_gjtalotta_prob4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addPiS_PiS_
.type _Z24__device_stub__Z3addPiS_PiS_, @function
_Z24__device_stub__Z3addPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addPiS_PiS_, .-_Z24__device_stub__Z3addPiS_PiS_
.globl _Z3addPiS_
.type _Z3addPiS_, @function
_Z3addPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_, .-_Z3addPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Total sum of all elements is: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $352, %rsp
.cfi_def_cfa_offset 368
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 80(%rsp), %rax
leaq 336(%rsp), %rdx
.L12:
movl $7, (%rax)
movl $7, 4(%rax)
movl $7, 8(%rax)
movl $7, 12(%rax)
movl $7, 16(%rax)
movl $7, 20(%rax)
movl $7, 24(%rax)
movl $7, 28(%rax)
addq $32, %rax
cmpq %rax, %rdx
jne .L12
movl $0, 48(%rsp)
movl $0, 52(%rsp)
movl $0, 56(%rsp)
movl $0, 60(%rsp)
movl $0, 64(%rsp)
movl $0, 68(%rsp)
movl $0, 72(%rsp)
movl $0, 76(%rsp)
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $256, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $8, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $8, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 48(%rsp), %rbx
movl $2, %ecx
movl $32, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
leaq 80(%rsp), %rsi
movl $0, %ecx
.L14:
addl (%rax), %ecx
movl %ecx, %edx
addq $4, %rax
cmpq %rsi, %rax
jne .L14
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $352, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z24__device_stub__Z3addPiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z3addPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gjtalotta_prob4.hip"
.globl _Z18__device_stub__addPiS_ # -- Begin function _Z18__device_stub__addPiS_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_,@function
_Z18__device_stub__addPiS_: # @_Z18__device_stub__addPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_, .Lfunc_end0-_Z18__device_stub__addPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $384, %rsp # imm = 0x180
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movq %rsp, %rdi
movl $32, %esi
callq hipMalloc
leaq 128(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # %.preheader24
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $7, (%rax,%rdx,4)
incq %rdx
cmpq $8, %rdx
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %rcx
addq $32, %rax
cmpq $8, %rcx
jne .LBB1_1
# %bb.4: # %.preheader.preheader
xorps %xmm0, %xmm0
movaps %xmm0, 112(%rsp)
movaps %xmm0, 96(%rsp)
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $256, %edx # imm = 0x100
movl $1, %ecx
callq hipMemcpy
xorl %ebx, %ebx
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $32, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
addl 96(%rsp,%rax,4), %ebx
incq %rax
cmpq $8, %rax
jne .LBB1_7
# %bb.8:
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $384, %rsp # imm = 0x180
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_,@object # @_Z3addPiS_
.section .rodata,"a",@progbits
.globl _Z3addPiS_
.p2align 3, 0x0
_Z3addPiS_:
.quad _Z18__device_stub__addPiS_
.size _Z3addPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Total sum of all elements is: %d\n"
.size .L.str, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
*Developed by Karan Bhagat
*March 2017
**/
#include <stdio.h>
#include <stdlib.h>
#define BLK_ROWS 2
#define BLK_COLS 2
//size of the share memory tile in the device
#define TILE_SIZE BLK_ROWS
//cuda kernel for multiplying two matrices using tiling
__global__ void matrix_mul_kernel(int* a, int* b, int* c, int a_rows, int a_columns, int b_columns)
{
//declare shared memory matrices for A and B matrices
__shared__ int shared_a_tile[TILE_SIZE][TILE_SIZE];
__shared__ int shared_b_tile[TILE_SIZE][TILE_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
//check if thread directly maps to the dimensions of the resulting matrix
if (row < a_rows && col < b_columns)
{
int result = 0;
int k;
int phase;
//calculate C matrix indexes in phases. Each phase shares
//TILE_SIZE * TILE_SIZE data copied to the shared matrix A
//and matrix B.
for (phase = 0; phase <= a_columns/TILE_SIZE; phase++)
{
shared_a_tile[ty][tx] = a[row * a_columns + phase * TILE_SIZE + tx];
shared_b_tile[ty][tx] = b[(phase * TILE_SIZE + ty) * b_columns + col];
__syncthreads();
for (k = 0; k < TILE_SIZE; k++)
{
if (k + (phase * TILE_SIZE) < a_columns)
{
result += (shared_a_tile[ty][k] * shared_b_tile[k][tx]);
}
}
__syncthreads();
}
c[row * b_columns + col] = result;
}
}
void build_matrix(FILE *file, int* mat, int rows, int columns);
int main(int argc, char **argv)
{
//check for filenames and matrices' dimensions
if (argc != 6)
{
printf("Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>");
exit(1);
}
char* fileA_name = argv[1];//matrix A filename
char* fileB_name = argv[2];//matrix B filename
// a_columns can also be perceived as b_rows
int a_rows, a_columns, b_columns;
//read matrix A and B's dimensions
sscanf(argv[3], "%d", &a_rows);
sscanf(argv[4], "%d", &a_columns);
sscanf(argv[5], "%d", &b_columns);
FILE *fileA = fopen(fileA_name, "r");
FILE *fileB = fopen(fileB_name, "r");
//declare host and device matrices pointers
int* mat_a;
int* mat_b;
int* mat_c;
int* d_mat_a;
int* d_mat_b;
int* d_mat_c;
//allocate memory for host matrices
mat_a = (int*)malloc(a_rows * a_columns * sizeof(int));
mat_b = (int*)malloc(a_columns * b_columns * sizeof(int));
mat_c = (int*)malloc(a_rows * b_columns * sizeof(int));
int i, j;
build_matrix(fileA, mat_a, a_rows, a_columns);
build_matrix(fileB, mat_b, a_columns, b_columns);
//declare dimensions for the grid and block
dim3 dimBlock(BLK_COLS,BLK_ROWS);
dim3 dimGrid((int)ceil(b_columns/BLK_COLS),(int)ceil(a_rows/BLK_ROWS));
const size_t size_a = a_rows * a_columns * sizeof(int);
const size_t size_b = a_columns * b_columns * sizeof(int);
const size_t size_c = a_rows * b_columns * sizeof(int);
//allocate matrices memeory on device
cudaMalloc((void **)&d_mat_a, size_a);
cudaMalloc((void **)&d_mat_b, size_b);
cudaMalloc((void **)&d_mat_c, size_c);
//copy A and B matrices from host to device
cudaMemcpy(d_mat_a, mat_a, size_a, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat_b, mat_b, size_b, cudaMemcpyHostToDevice);
//execute cuda kernel
matrix_mul_kernel<<<dimGrid, dimBlock>>>(d_mat_a, d_mat_b, d_mat_c, a_rows, a_columns, b_columns);
//copy the compute matrix C from device to host
cudaMemcpy(mat_c, d_mat_c, size_c, cudaMemcpyDeviceToHost);
//print the resulting matrix
for (i = 0; i < a_rows; i++)
{
for (j = 0; j < b_columns; j++)
{
printf("%d ", mat_c[i * b_columns + j]);
}
printf("\n");
}
//free cuda memory
cudaFree(d_mat_a);
cudaFree(d_mat_b);
cudaFree(d_mat_c);
}
//build matrix from the file
void build_matrix(FILE *file, int* mat, int rows, int columns)
{
int i, j;
for (i = 0; i < rows; i++)
{
for (j = 0; j < columns; j++)
{
fscanf(file, "%d", &mat[i * columns + j]);
}
}
} | code for sm_80
Function : _Z17matrix_mul_kernelPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; /* 0x0000600009007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R10, R3, c[0x0][0x4], R8 ; /* 0x00000100030a7a24 */
/* 0x002fca00078e0208 */
/*0080*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x178], P0 ; /* 0x00005e000a007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fc600000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x900 ; /* 0x0000081000008947 */
/* 0x000fea0003800000 */
/*00f0*/ LEA.HI R2, R2, c[0x0][0x17c], RZ, 0x1 ; /* 0x00005f0002027a11 */
/* 0x000fe200078f08ff */
/*0100*/ IMAD.SHL.U32 R3, R8, 0x8, RZ ; /* 0x0000000808037824 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD R13, R10, c[0x0][0x17c], R0 ; /* 0x00005f000a0d7a24 */
/* 0x000fe200078e0200 */
/*0130*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0140*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD R14, R0, 0x4, R3 ; /* 0x00000004000e7824 */
/* 0x000fe200078e0203 */
/*0160*/ ISETP.GE.U32.AND P1, PT, R2.reuse, 0x3, PT ; /* 0x000000030200780c */
/* 0x040fe40003f26070 */
/*0170*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fc80007ffe0ff */
/*0180*/ LOP3.LUT R12, R5, 0x3, RZ, 0xc0, !PT ; /* 0x00000003050c7812 */
/* 0x000fc800078ec0ff */
/*0190*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc60003f05270 */
/*01a0*/ @!P1 BRA 0x6c0 ; /* 0x0000051000009947 */
/* 0x000ff40003800000 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0f7624 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R18, R5, -R12, RZ ; /* 0x8000000c05127210 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.SHL.U32 R15, R15, 0x2, RZ ; /* 0x000000020f0f7824 */
/* 0x000fc600078e00ff */
/*01f0*/ SHF.L.U32 R17, R16, 0x1, RZ ; /* 0x0000000110117819 */
/* 0x000fe200000006ff */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0210*/ IADD3 R2, R13, R17, RZ ; /* 0x000000110d027210 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.IADD R4, R17, 0x1, R8 ; /* 0x0000000111047824 */
/* 0x000fc800078e0208 */
/*0230*/ IMAD R4, R4, c[0x0][0x180], R9 ; /* 0x0000600004047a24 */
/* 0x000fe400078e0209 */
/*0240*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0207 */
/*0250*/ IMAD.WIDE R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fe200078e0207 */
/*0260*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R23, [R6.64] ; /* 0x0000000406177981 */
/* 0x000ee2000c1e1900 */
/*0280*/ IADD3 R4, R17.reuse, 0x1, RZ ; /* 0x0000000111047810 */
/* 0x040fe40007ffe0ff */
/*0290*/ ISETP.GE.AND P1, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fe40003f26270 */
/*02a0*/ ISETP.GE.AND P6, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003fc6270 */
/*02b0*/ IMAD.WIDE R4, R15, 0x4, R6 ; /* 0x000000040f047825 */
/* 0x000fe200078e0206 */
/*02c0*/ STS [R14], R21 ; /* 0x000000150e007388 */
/* 0x004fe80000000800 */
/*02d0*/ STS [R14+0x10], R23 ; /* 0x000010170e007388 */
/* 0x008fe80000000800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @!P1 LDS R25, [R8.X8] ; /* 0x0000000008199984 */
/* 0x000fe80000008800 */
/*0300*/ @!P1 LDS R26, [R0.X4+0x10] ; /* 0x00001000001a9984 */
/* 0x000e280000004800 */
/*0310*/ @!P6 LDS R19, [R0.X4+0x18] ; /* 0x000018000013e984 */
/* 0x000fe80000004800 */
/*0320*/ @!P6 LDS R20, [R8.X8+0x4] ; /* 0x000004000814e984 */
/* 0x000e680000008800 */
/*0330*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0340*/ LDG.E R27, [R2.64+0x8] ; /* 0x00000804021b7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R29, [R4.64] ; /* 0x00000004041d7981 */
/* 0x000ee2000c1e1900 */
/*0360*/ IADD3 R6, R17, 0x2, RZ ; /* 0x0000000211067810 */
/* 0x000fc40007ffe0ff */
/*0370*/ IADD3 R7, R17, 0x3, RZ ; /* 0x0000000311077810 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.GE.AND P5, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fe40003fa6270 */
/*0390*/ ISETP.GE.AND P4, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe20003f86270 */
/*03a0*/ IMAD.WIDE R6, R15, 0x4, R4 ; /* 0x000000040f067825 */
/* 0x000fe200078e0204 */
/*03b0*/ STS [R14], R27 ; /* 0x0000001b0e007388 */
/* 0x004fe80000000800 */
/*03c0*/ STS [R14+0x10], R29 ; /* 0x0000101d0e007388 */
/* 0x008fe80000000800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03e0*/ @!P5 LDS R22, [R8.X8] ; /* 0x000000000816d984 */
/* 0x000fe80000008800 */
/*03f0*/ @!P5 LDS R21, [R0.X4+0x10] ; /* 0x000010000015d984 */
/* 0x000ea80000004800 */
/*0400*/ @!P4 LDS R24, [R0.X4+0x18] ; /* 0x000018000018c984 */
/* 0x000fe80000004800 */
/*0410*/ @!P4 LDS R23, [R8.X8+0x4] ; /* 0x000004000817c984 */
/* 0x000ee80000008800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ LDG.E R28, [R2.64+0x10] ; /* 0x00001004021c7981 */
/* 0x000f28000c1e1900 */
/*0440*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x000f62000c1e1900 */
/*0450*/ IADD3 R4, R17, 0x4, RZ ; /* 0x0000000411047810 */
/* 0x000fe20007ffe0ff */
/*0460*/ @!P1 IMAD R11, R25, R26, R11 ; /* 0x0000001a190b9224 */
/* 0x001fc600078e020b */
/*0470*/ ISETP.GE.AND P3, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe40003f66270 */
/*0480*/ IADD3 R4, R17, 0x5, RZ ; /* 0x0000000511047810 */
/* 0x000fc80007ffe0ff */
/*0490*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f46270 */
/*04a0*/ STS [R14], R28 ; /* 0x0000001c0e007388 */
/* 0x010fe80000000800 */
/*04b0*/ STS [R14+0x10], R5 ; /* 0x000010050e007388 */
/* 0x0201e80000000800 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ IMAD.WIDE R4, R15, 0x4, R6 ; /* 0x000000040f047825 */
/* 0x001fca00078e0206 */
/*04e0*/ @!P3 LDS R26, [R8.X8] ; /* 0x00000000081ab984 */
/* 0x000fe80000008800 */
/*04f0*/ @!P3 LDS R25, [R0.X4+0x10] ; /* 0x000010000019b984 */
/* 0x000e280000004800 */
/*0500*/ @!P2 LDS R7, [R0.X4+0x18] ; /* 0x000018000007a984 */
/* 0x000fe80000004800 */
/*0510*/ @!P2 LDS R6, [R8.X8+0x4] ; /* 0x000004000806a984 */
/* 0x000f280000008800 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ LDG.E R3, [R2.64+0x18] ; /* 0x0000180402037981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R27, [R4.64] ; /* 0x00000004041b7981 */
/* 0x000f62000c1e1900 */
/*0550*/ IADD3 R28, R17, 0x6, RZ ; /* 0x00000006111c7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ @!P6 IMAD R11, R19, R20, R11 ; /* 0x00000014130be224 */
/* 0x002fe200078e020b */
/*0570*/ IADD3 R17, R17, 0x7, RZ ; /* 0x0000000711117810 */
/* 0x000fc40007ffe0ff */
/*0580*/ ISETP.GE.AND P1, PT, R28, c[0x0][0x17c], PT ; /* 0x00005f001c007a0c */
/* 0x000fe20003f26270 */
/*0590*/ @!P5 IMAD R11, R22, R21, R11 ; /* 0x00000015160bd224 */
/* 0x004fe200078e020b */
/*05a0*/ ISETP.GE.AND P6, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fe40003fc6270 */
/*05b0*/ IADD3 R18, R18, -0x4, RZ ; /* 0xfffffffc12127810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ @!P4 IMAD R11, R24, R23, R11 ; /* 0x00000017180bc224 */
/* 0x008fe200078e020b */
/*05d0*/ IADD3 R16, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ @!P3 IMAD R11, R26, R25, R11 ; /* 0x000000191a0bb224 */
/* 0x001fc800078e020b */
/*05f0*/ @!P2 IMAD R11, R7, R6, R11 ; /* 0x00000006070ba224 */
/* 0x010fe200078e020b */
/*0600*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f45270 */
/*0610*/ STS [R14], R3 ; /* 0x000000030e007388 */
/* 0x020fe80000000800 */
/*0620*/ STS [R14+0x10], R27 ; /* 0x0000101b0e007388 */
/* 0x000fe80000000800 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ @!P1 LDS R20, [R8.X8] ; /* 0x0000000008149984 */
/* 0x000fe80000008800 */
/*0650*/ @!P1 LDS R2, [R0.X4+0x10] ; /* 0x0000100000029984 */
/* 0x000e280000004800 */
/*0660*/ @!P6 LDS R4, [R0.X4+0x18] ; /* 0x000018000004e984 */
/* 0x000fe80000004800 */
/*0670*/ @!P6 LDS R5, [R8.X8+0x4] ; /* 0x000004000805e984 */
/* 0x000e620000008800 */
/*0680*/ @!P1 IMAD R11, R20, R2, R11 ; /* 0x00000002140b9224 */
/* 0x001fc800078e020b */
/*0690*/ @!P6 IMAD R11, R4, R5, R11 ; /* 0x00000005040be224 */
/* 0x002fe200078e020b */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ @P2 BRA 0x1f0 ; /* 0xfffffb3000002947 */
/* 0x000fea000383ffff */
/*06c0*/ @!P0 BRA 0x900 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD R2, R16.reuse, 0x2, R13 ; /* 0x0000000210027824 */
/* 0x040fe200078e020d */
/*06e0*/ LEA R4, R16.reuse, R8, 0x1 ; /* 0x0000000810047211 */
/* 0x040fe200078e08ff */
/*06f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0700*/ LEA R16, R16, 0x1, 0x1 ; /* 0x0000000110107811 */
/* 0x000fe200078e08ff */
/*0710*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fc400078e00ff */
/*0720*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*0730*/ IMAD R4, R4, c[0x0][0x180], R9 ; /* 0x0000600004047a24 */
/* 0x000fe200078e0209 */
/*0740*/ MOV R20, R3 ; /* 0x0000000300147202 */
/* 0x000fe20000000f00 */
/*0750*/ IMAD.MOV.U32 R15, RZ, RZ, R2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0002 */
/*0760*/ IMAD.SHL.U32 R17, R6, 0x2, RZ ; /* 0x0000000206117824 */
/* 0x000fe400078e00ff */
/*0770*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0780*/ MOV R5, R20 ; /* 0x0000001400057202 */
/* 0x000fe20000000f00 */
/*0790*/ IMAD.MOV.U32 R4, RZ, RZ, R15 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000f */
/*07a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x0000a8000c1e1900 */
/*07b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee2000c1e1900 */
/*07c0*/ IADD3 R6, R16, -0x1, RZ ; /* 0xffffffff10067810 */
/* 0x000fc80007ffe0ff */
/*07d0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fe40003f06270 */
/*07e0*/ ISETP.GE.AND P1, PT, R16, c[0x0][0x17c], PT ; /* 0x00005f0010007a0c */
/* 0x000fe40003f26270 */
/*07f0*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fc80007ffe0ff */
/*0800*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f45270 */
/*0810*/ IMAD.WIDE R2, R17, 0x4, R2 ; /* 0x0000000411027825 */
/* 0x001fe200078e0202 */
/*0820*/ IADD3 R16, R16, 0x2, RZ ; /* 0x0000000210107810 */
/* 0x000fe20007ffe0ff */
/*0830*/ STS [R14+0x10], R7 ; /* 0x000010070e007388 */
/* 0x004fe80000000800 */
/*0840*/ STS [R14], R5 ; /* 0x000000050e007388 */
/* 0x008fe80000000800 */
/*0850*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0860*/ @!P0 LDS R6, [R8.X8] ; /* 0x0000000008068984 */
/* 0x000fe80000008800 */
/*0870*/ @!P0 LDS R13, [R0.X4+0x10] ; /* 0x00001000000d8984 */
/* 0x000e280000004800 */
/*0880*/ @!P1 LDS R18, [R0.X4+0x18] ; /* 0x0000180000129984 */
/* 0x000fe80000004800 */
/*0890*/ @!P1 LDS R4, [R8.X8+0x4] ; /* 0x0000040008049984 */
/* 0x000e620000008800 */
/*08a0*/ @!P0 IMAD R11, R6, R13, R11 ; /* 0x0000000d060b8224 */
/* 0x001fc600078e020b */
/*08b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08c0*/ IADD3 R15, P0, R15, 0x8, RZ ; /* 0x000000080f0f7810 */
/* 0x000fca0007f1e0ff */
/*08d0*/ IMAD.X R20, RZ, RZ, R20, P0 ; /* 0x000000ffff147224 */
/* 0x000fe400000e0614 */
/*08e0*/ @!P1 IMAD R11, R18, R4, R11 ; /* 0x00000004120b9224 */
/* 0x002fe200078e020b */
/*08f0*/ @P2 BRA 0x780 ; /* 0xfffffe8000002947 */
/* 0x000fea000383ffff */
/*0900*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0910*/ IMAD R2, R10, c[0x0][0x180], R9 ; /* 0x000060000a027a24 */
/* 0x000fc800078e0209 */
/*0920*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0930*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0940*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0950*/ BRA 0x950; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
*Developed by Karan Bhagat
*March 2017
**/
#include <stdio.h>
#include <stdlib.h>
#define BLK_ROWS 2
#define BLK_COLS 2
//size of the share memory tile in the device
#define TILE_SIZE BLK_ROWS
//cuda kernel for multiplying two matrices using tiling
__global__ void matrix_mul_kernel(int* a, int* b, int* c, int a_rows, int a_columns, int b_columns)
{
//declare shared memory matrices for A and B matrices
__shared__ int shared_a_tile[TILE_SIZE][TILE_SIZE];
__shared__ int shared_b_tile[TILE_SIZE][TILE_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
//check if thread directly maps to the dimensions of the resulting matrix
if (row < a_rows && col < b_columns)
{
int result = 0;
int k;
int phase;
//calculate C matrix indexes in phases. Each phase shares
//TILE_SIZE * TILE_SIZE data copied to the shared matrix A
//and matrix B.
for (phase = 0; phase <= a_columns/TILE_SIZE; phase++)
{
shared_a_tile[ty][tx] = a[row * a_columns + phase * TILE_SIZE + tx];
shared_b_tile[ty][tx] = b[(phase * TILE_SIZE + ty) * b_columns + col];
__syncthreads();
for (k = 0; k < TILE_SIZE; k++)
{
if (k + (phase * TILE_SIZE) < a_columns)
{
result += (shared_a_tile[ty][k] * shared_b_tile[k][tx]);
}
}
__syncthreads();
}
c[row * b_columns + col] = result;
}
}
void build_matrix(FILE *file, int* mat, int rows, int columns);
int main(int argc, char **argv)
{
//check for filenames and matrices' dimensions
if (argc != 6)
{
printf("Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>");
exit(1);
}
char* fileA_name = argv[1];//matrix A filename
char* fileB_name = argv[2];//matrix B filename
// a_columns can also be perceived as b_rows
int a_rows, a_columns, b_columns;
//read matrix A and B's dimensions
sscanf(argv[3], "%d", &a_rows);
sscanf(argv[4], "%d", &a_columns);
sscanf(argv[5], "%d", &b_columns);
FILE *fileA = fopen(fileA_name, "r");
FILE *fileB = fopen(fileB_name, "r");
//declare host and device matrices pointers
int* mat_a;
int* mat_b;
int* mat_c;
int* d_mat_a;
int* d_mat_b;
int* d_mat_c;
//allocate memory for host matrices
mat_a = (int*)malloc(a_rows * a_columns * sizeof(int));
mat_b = (int*)malloc(a_columns * b_columns * sizeof(int));
mat_c = (int*)malloc(a_rows * b_columns * sizeof(int));
int i, j;
build_matrix(fileA, mat_a, a_rows, a_columns);
build_matrix(fileB, mat_b, a_columns, b_columns);
//declare dimensions for the grid and block
dim3 dimBlock(BLK_COLS,BLK_ROWS);
dim3 dimGrid((int)ceil(b_columns/BLK_COLS),(int)ceil(a_rows/BLK_ROWS));
const size_t size_a = a_rows * a_columns * sizeof(int);
const size_t size_b = a_columns * b_columns * sizeof(int);
const size_t size_c = a_rows * b_columns * sizeof(int);
//allocate matrices memeory on device
cudaMalloc((void **)&d_mat_a, size_a);
cudaMalloc((void **)&d_mat_b, size_b);
cudaMalloc((void **)&d_mat_c, size_c);
//copy A and B matrices from host to device
cudaMemcpy(d_mat_a, mat_a, size_a, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat_b, mat_b, size_b, cudaMemcpyHostToDevice);
//execute cuda kernel
matrix_mul_kernel<<<dimGrid, dimBlock>>>(d_mat_a, d_mat_b, d_mat_c, a_rows, a_columns, b_columns);
//copy the compute matrix C from device to host
cudaMemcpy(mat_c, d_mat_c, size_c, cudaMemcpyDeviceToHost);
//print the resulting matrix
for (i = 0; i < a_rows; i++)
{
for (j = 0; j < b_columns; j++)
{
printf("%d ", mat_c[i * b_columns + j]);
}
printf("\n");
}
//free cuda memory
cudaFree(d_mat_a);
cudaFree(d_mat_b);
cudaFree(d_mat_c);
}
//build matrix from the file
void build_matrix(FILE *file, int* mat, int rows, int columns)
{
int i, j;
for (i = 0; i < rows; i++)
{
for (j = 0; j < columns; j++)
{
fscanf(file, "%d", &mat[i * columns + j]);
}
}
} | .file "tmpxft_00084e05_00000000-6_matrix_mul_tiling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.text
.globl _Z12build_matrixP8_IO_FILEPiii
.type _Z12build_matrixP8_IO_FILEPiii, @function
_Z12build_matrixP8_IO_FILEPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
testl %edx, %edx
jle .L3
movq %rdi, %r12
movl %ecx, %r14d
movl $0, (%rsp)
movl $0, %r15d
leaq .LC0(%rip), %r13
jmp .L5
.L7:
movslq (%rsp), %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r14d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
addl $1, %r15d
addl %r14d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L3
.L5:
testl %r14d, %r14d
jg .L7
jmp .L8
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12build_matrixP8_IO_FILEPiii, .-_Z12build_matrixP8_IO_FILEPiii
.globl _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
.type _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii, @function
_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17matrix_mul_kernelPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii, .-_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
.globl _Z17matrix_mul_kernelPiS_S_iii
.type _Z17matrix_mul_kernelPiS_S_iii, @function
_Z17matrix_mul_kernelPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17matrix_mul_kernelPiS_S_iii, .-_Z17matrix_mul_kernelPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>"
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "%d "
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $6, %edi
jne .L33
movq %rsi, %rbx
movq 8(%rsi), %r13
movq 16(%rsi), %r12
leaq 28(%rsp), %rdx
movq 24(%rsi), %rdi
leaq .LC0(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 32(%rsp), %rdx
movq 32(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 36(%rsp), %rdx
movq 40(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, %r13
movq %rbx, %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, 8(%rsp)
movl 28(%rsp), %r14d
movl 32(%rsp), %r15d
movl %r14d, %ecx
imull %r15d, %ecx
movslq %ecx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl 36(%rsp), %ebx
movl %r15d, %ecx
imull %ebx, %ecx
movslq %ecx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
imull %r14d, %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r15d, %ecx
movl %r14d, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z12build_matrixP8_IO_FILEPiii
movl 36(%rsp), %ecx
movl 32(%rsp), %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call _Z12build_matrixP8_IO_FILEPiii
movl $2, 64(%rsp)
movl $2, 68(%rsp)
movl $1, 72(%rsp)
movl 28(%rsp), %eax
movl 36(%rsp), %ecx
movl %ecx, %edx
shrl $31, %edx
addl %ecx, %edx
sarl %edx
movl %edx, 76(%rsp)
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
movl %edx, 80(%rsp)
movl $1, 84(%rsp)
movl 32(%rsp), %edx
movl %eax, %r14d
imull %edx, %r14d
movslq %r14d, %r14
salq $2, %r14
imull %ecx, %edx
movslq %edx, %r13
salq $2, %r13
imull %ecx, %eax
movslq %eax, %r15
salq $2, %r15
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L21:
movl $2, %ecx
movq %r15, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r14
cmpl $0, 28(%rsp)
jg .L22
.L23:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl 36(%rsp), %r9d
movl 32(%rsp), %r8d
movl 28(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
jmp .L21
.L24:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 36(%rsp), %eax
cmpl %ebp, %eax
jg .L24
.L25:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 28(%rsp)
jle .L23
.L22:
movl 36(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L24
jmp .L25
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z17matrix_mul_kernelPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrix_mul_kernelPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
*Developed by Karan Bhagat
*March 2017
**/
#include <stdio.h>
#include <stdlib.h>
#define BLK_ROWS 2
#define BLK_COLS 2
//size of the share memory tile in the device
#define TILE_SIZE BLK_ROWS
//cuda kernel for multiplying two matrices using tiling
__global__ void matrix_mul_kernel(int* a, int* b, int* c, int a_rows, int a_columns, int b_columns)
{
//declare shared memory matrices for A and B matrices
__shared__ int shared_a_tile[TILE_SIZE][TILE_SIZE];
__shared__ int shared_b_tile[TILE_SIZE][TILE_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
//check if thread directly maps to the dimensions of the resulting matrix
if (row < a_rows && col < b_columns)
{
int result = 0;
int k;
int phase;
//calculate C matrix indexes in phases. Each phase shares
//TILE_SIZE * TILE_SIZE data copied to the shared matrix A
//and matrix B.
for (phase = 0; phase <= a_columns/TILE_SIZE; phase++)
{
shared_a_tile[ty][tx] = a[row * a_columns + phase * TILE_SIZE + tx];
shared_b_tile[ty][tx] = b[(phase * TILE_SIZE + ty) * b_columns + col];
__syncthreads();
for (k = 0; k < TILE_SIZE; k++)
{
if (k + (phase * TILE_SIZE) < a_columns)
{
result += (shared_a_tile[ty][k] * shared_b_tile[k][tx]);
}
}
__syncthreads();
}
c[row * b_columns + col] = result;
}
}
void build_matrix(FILE *file, int* mat, int rows, int columns);
int main(int argc, char **argv)
{
//check for filenames and matrices' dimensions
if (argc != 6)
{
printf("Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>");
exit(1);
}
char* fileA_name = argv[1];//matrix A filename
char* fileB_name = argv[2];//matrix B filename
// a_columns can also be perceived as b_rows
int a_rows, a_columns, b_columns;
//read matrix A and B's dimensions
sscanf(argv[3], "%d", &a_rows);
sscanf(argv[4], "%d", &a_columns);
sscanf(argv[5], "%d", &b_columns);
FILE *fileA = fopen(fileA_name, "r");
FILE *fileB = fopen(fileB_name, "r");
//declare host and device matrices pointers
int* mat_a;
int* mat_b;
int* mat_c;
int* d_mat_a;
int* d_mat_b;
int* d_mat_c;
//allocate memory for host matrices
mat_a = (int*)malloc(a_rows * a_columns * sizeof(int));
mat_b = (int*)malloc(a_columns * b_columns * sizeof(int));
mat_c = (int*)malloc(a_rows * b_columns * sizeof(int));
int i, j;
build_matrix(fileA, mat_a, a_rows, a_columns);
build_matrix(fileB, mat_b, a_columns, b_columns);
//declare dimensions for the grid and block
dim3 dimBlock(BLK_COLS,BLK_ROWS);
dim3 dimGrid((int)ceil(b_columns/BLK_COLS),(int)ceil(a_rows/BLK_ROWS));
const size_t size_a = a_rows * a_columns * sizeof(int);
const size_t size_b = a_columns * b_columns * sizeof(int);
const size_t size_c = a_rows * b_columns * sizeof(int);
//allocate matrices memeory on device
cudaMalloc((void **)&d_mat_a, size_a);
cudaMalloc((void **)&d_mat_b, size_b);
cudaMalloc((void **)&d_mat_c, size_c);
//copy A and B matrices from host to device
cudaMemcpy(d_mat_a, mat_a, size_a, cudaMemcpyHostToDevice);
cudaMemcpy(d_mat_b, mat_b, size_b, cudaMemcpyHostToDevice);
//execute cuda kernel
matrix_mul_kernel<<<dimGrid, dimBlock>>>(d_mat_a, d_mat_b, d_mat_c, a_rows, a_columns, b_columns);
//copy the compute matrix C from device to host
cudaMemcpy(mat_c, d_mat_c, size_c, cudaMemcpyDeviceToHost);
//print the resulting matrix
for (i = 0; i < a_rows; i++)
{
for (j = 0; j < b_columns; j++)
{
printf("%d ", mat_c[i * b_columns + j]);
}
printf("\n");
}
//free cuda memory
cudaFree(d_mat_a);
cudaFree(d_mat_b);
cudaFree(d_mat_c);
}
//build matrix from the file
void build_matrix(FILE *file, int* mat, int rows, int columns)
{
int i, j;
for (i = 0; i < rows; i++)
{
for (j = 0; j < columns; j++)
{
fscanf(file, "%d", &mat[i * columns + j]);
}
}
} | /**
*Developed by Karan Bhagat
*March 2017
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLK_ROWS 2
#define BLK_COLS 2
//size of the share memory tile in the device
#define TILE_SIZE BLK_ROWS
//cuda kernel for multiplying two matrices using tiling
__global__ void matrix_mul_kernel(int* a, int* b, int* c, int a_rows, int a_columns, int b_columns)
{
//declare shared memory matrices for A and B matrices
__shared__ int shared_a_tile[TILE_SIZE][TILE_SIZE];
__shared__ int shared_b_tile[TILE_SIZE][TILE_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
//check if thread directly maps to the dimensions of the resulting matrix
if (row < a_rows && col < b_columns)
{
int result = 0;
int k;
int phase;
//calculate C matrix indexes in phases. Each phase shares
//TILE_SIZE * TILE_SIZE data copied to the shared matrix A
//and matrix B.
for (phase = 0; phase <= a_columns/TILE_SIZE; phase++)
{
shared_a_tile[ty][tx] = a[row * a_columns + phase * TILE_SIZE + tx];
shared_b_tile[ty][tx] = b[(phase * TILE_SIZE + ty) * b_columns + col];
__syncthreads();
for (k = 0; k < TILE_SIZE; k++)
{
if (k + (phase * TILE_SIZE) < a_columns)
{
result += (shared_a_tile[ty][k] * shared_b_tile[k][tx]);
}
}
__syncthreads();
}
c[row * b_columns + col] = result;
}
}
void build_matrix(FILE *file, int* mat, int rows, int columns);
int main(int argc, char **argv)
{
//check for filenames and matrices' dimensions
if (argc != 6)
{
printf("Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>");
exit(1);
}
char* fileA_name = argv[1];//matrix A filename
char* fileB_name = argv[2];//matrix B filename
// a_columns can also be perceived as b_rows
int a_rows, a_columns, b_columns;
//read matrix A and B's dimensions
sscanf(argv[3], "%d", &a_rows);
sscanf(argv[4], "%d", &a_columns);
sscanf(argv[5], "%d", &b_columns);
FILE *fileA = fopen(fileA_name, "r");
FILE *fileB = fopen(fileB_name, "r");
//declare host and device matrices pointers
int* mat_a;
int* mat_b;
int* mat_c;
int* d_mat_a;
int* d_mat_b;
int* d_mat_c;
//allocate memory for host matrices
mat_a = (int*)malloc(a_rows * a_columns * sizeof(int));
mat_b = (int*)malloc(a_columns * b_columns * sizeof(int));
mat_c = (int*)malloc(a_rows * b_columns * sizeof(int));
int i, j;
build_matrix(fileA, mat_a, a_rows, a_columns);
build_matrix(fileB, mat_b, a_columns, b_columns);
//declare dimensions for the grid and block
dim3 dimBlock(BLK_COLS,BLK_ROWS);
dim3 dimGrid((int)ceil(b_columns/BLK_COLS),(int)ceil(a_rows/BLK_ROWS));
const size_t size_a = a_rows * a_columns * sizeof(int);
const size_t size_b = a_columns * b_columns * sizeof(int);
const size_t size_c = a_rows * b_columns * sizeof(int);
//allocate matrices memeory on device
hipMalloc((void **)&d_mat_a, size_a);
hipMalloc((void **)&d_mat_b, size_b);
hipMalloc((void **)&d_mat_c, size_c);
//copy A and B matrices from host to device
hipMemcpy(d_mat_a, mat_a, size_a, hipMemcpyHostToDevice);
hipMemcpy(d_mat_b, mat_b, size_b, hipMemcpyHostToDevice);
//execute cuda kernel
matrix_mul_kernel<<<dimGrid, dimBlock>>>(d_mat_a, d_mat_b, d_mat_c, a_rows, a_columns, b_columns);
//copy the compute matrix C from device to host
hipMemcpy(mat_c, d_mat_c, size_c, hipMemcpyDeviceToHost);
//print the resulting matrix
for (i = 0; i < a_rows; i++)
{
for (j = 0; j < b_columns; j++)
{
printf("%d ", mat_c[i * b_columns + j]);
}
printf("\n");
}
//free cuda memory
hipFree(d_mat_a);
hipFree(d_mat_b);
hipFree(d_mat_c);
}
//build matrix from the file
void build_matrix(FILE *file, int* mat, int rows, int columns)
{
int i, j;
for (i = 0; i < rows; i++)
{
for (j = 0; j < columns; j++)
{
fscanf(file, "%d", &mat[i * columns + j]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
*Developed by Karan Bhagat
*March 2017
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLK_ROWS 2
#define BLK_COLS 2
//size of the share memory tile in the device
#define TILE_SIZE BLK_ROWS
//cuda kernel for multiplying two matrices using tiling
__global__ void matrix_mul_kernel(int* a, int* b, int* c, int a_rows, int a_columns, int b_columns)
{
//declare shared memory matrices for A and B matrices
__shared__ int shared_a_tile[TILE_SIZE][TILE_SIZE];
__shared__ int shared_b_tile[TILE_SIZE][TILE_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
//check if thread directly maps to the dimensions of the resulting matrix
if (row < a_rows && col < b_columns)
{
int result = 0;
int k;
int phase;
//calculate C matrix indexes in phases. Each phase shares
//TILE_SIZE * TILE_SIZE data copied to the shared matrix A
//and matrix B.
for (phase = 0; phase <= a_columns/TILE_SIZE; phase++)
{
shared_a_tile[ty][tx] = a[row * a_columns + phase * TILE_SIZE + tx];
shared_b_tile[ty][tx] = b[(phase * TILE_SIZE + ty) * b_columns + col];
__syncthreads();
for (k = 0; k < TILE_SIZE; k++)
{
if (k + (phase * TILE_SIZE) < a_columns)
{
result += (shared_a_tile[ty][k] * shared_b_tile[k][tx]);
}
}
__syncthreads();
}
c[row * b_columns + col] = result;
}
}
void build_matrix(FILE *file, int* mat, int rows, int columns);
int main(int argc, char **argv)
{
//check for filenames and matrices' dimensions
if (argc != 6)
{
printf("Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>");
exit(1);
}
char* fileA_name = argv[1];//matrix A filename
char* fileB_name = argv[2];//matrix B filename
// a_columns can also be perceived as b_rows
int a_rows, a_columns, b_columns;
//read matrix A and B's dimensions
sscanf(argv[3], "%d", &a_rows);
sscanf(argv[4], "%d", &a_columns);
sscanf(argv[5], "%d", &b_columns);
FILE *fileA = fopen(fileA_name, "r");
FILE *fileB = fopen(fileB_name, "r");
//declare host and device matrices pointers
int* mat_a;
int* mat_b;
int* mat_c;
int* d_mat_a;
int* d_mat_b;
int* d_mat_c;
//allocate memory for host matrices
mat_a = (int*)malloc(a_rows * a_columns * sizeof(int));
mat_b = (int*)malloc(a_columns * b_columns * sizeof(int));
mat_c = (int*)malloc(a_rows * b_columns * sizeof(int));
int i, j;
build_matrix(fileA, mat_a, a_rows, a_columns);
build_matrix(fileB, mat_b, a_columns, b_columns);
//declare dimensions for the grid and block
dim3 dimBlock(BLK_COLS,BLK_ROWS);
dim3 dimGrid((int)ceil(b_columns/BLK_COLS),(int)ceil(a_rows/BLK_ROWS));
const size_t size_a = a_rows * a_columns * sizeof(int);
const size_t size_b = a_columns * b_columns * sizeof(int);
const size_t size_c = a_rows * b_columns * sizeof(int);
//allocate matrices memeory on device
hipMalloc((void **)&d_mat_a, size_a);
hipMalloc((void **)&d_mat_b, size_b);
hipMalloc((void **)&d_mat_c, size_c);
//copy A and B matrices from host to device
hipMemcpy(d_mat_a, mat_a, size_a, hipMemcpyHostToDevice);
hipMemcpy(d_mat_b, mat_b, size_b, hipMemcpyHostToDevice);
//execute cuda kernel
matrix_mul_kernel<<<dimGrid, dimBlock>>>(d_mat_a, d_mat_b, d_mat_c, a_rows, a_columns, b_columns);
//copy the compute matrix C from device to host
hipMemcpy(mat_c, d_mat_c, size_c, hipMemcpyDeviceToHost);
//print the resulting matrix
for (i = 0; i < a_rows; i++)
{
for (j = 0; j < b_columns; j++)
{
printf("%d ", mat_c[i * b_columns + j]);
}
printf("\n");
}
//free cuda memory
hipFree(d_mat_a);
hipFree(d_mat_b);
hipFree(d_mat_c);
}
//build matrix from the file
void build_matrix(FILE *file, int* mat, int rows, int columns)
{
int i, j;
for (i = 0; i < rows; i++)
{
for (j = 0; j < columns; j++)
{
fscanf(file, "%d", &mat[i * columns + j]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17matrix_mul_kernelPiS_S_iii
.globl _Z17matrix_mul_kernelPiS_S_iii
.p2align 8
.type _Z17matrix_mul_kernelPiS_S_iii,@function
_Z17matrix_mul_kernelPiS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s5, v[6:7]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_10
s_load_b32 s2, s[0:1], 0x1c
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, -1
s_cbranch_scc1 .LBB0_9
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v6
v_lshlrev_b32_e32 v7, 3, v3
s_lshr_b32 s8, s2, 31
s_mov_b32 s9, 0
s_add_i32 s8, s2, s8
v_add_nc_u32_e32 v8, 16, v2
v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v7, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v6, v8, v7
s_ashr_i32 s8, s8, 1
s_mov_b32 s10, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_lshl_b32 s11, s10, 1
s_mov_b32 s12, 0
v_add_nc_u32_e32 v10, s11, v3
v_add_nc_u32_e32 v9, s11, v4
s_mov_b32 s11, s9
v_mad_u64_u32 v[11:12], null, v10, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v5, v10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_5
.LBB0_4:
v_add_nc_u32_e32 v9, 8, v9
s_add_i32 s12, s12, 4
s_add_i32 s11, s11, 1
s_cmp_eq_u32 s12, 4
s_cbranch_scc0 .LBB0_7
.LBB0_5:
s_cmp_ge_i32 s11, s2
s_cbranch_scc1 .LBB0_4
v_add_nc_u32_e32 v10, s12, v7
ds_load_b32 v12, v10
ds_load_b32 v13, v9
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[10:11], null, v13, v12, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v10
s_branch .LBB0_4
.LBB0_7:
s_add_i32 s11, s10, 1
s_add_i32 s9, s9, 2
s_cmp_lg_u32 s10, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
s_mov_b32 s10, s11
s_branch .LBB0_3
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matrix_mul_kernelPiS_S_iii
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17matrix_mul_kernelPiS_S_iii, .Lfunc_end0-_Z17matrix_mul_kernelPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matrix_mul_kernelPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matrix_mul_kernelPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
*Developed by Karan Bhagat
*March 2017
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define BLK_ROWS 2
#define BLK_COLS 2
//size of the share memory tile in the device
#define TILE_SIZE BLK_ROWS
//cuda kernel for multiplying two matrices using tiling
__global__ void matrix_mul_kernel(int* a, int* b, int* c, int a_rows, int a_columns, int b_columns)
{
//declare shared memory matrices for A and B matrices
__shared__ int shared_a_tile[TILE_SIZE][TILE_SIZE];
__shared__ int shared_b_tile[TILE_SIZE][TILE_SIZE];
int tx = threadIdx.x;
int ty = threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int row = blockIdx.y * blockDim.y + threadIdx.y;
//check if thread directly maps to the dimensions of the resulting matrix
if (row < a_rows && col < b_columns)
{
int result = 0;
int k;
int phase;
//calculate C matrix indexes in phases. Each phase shares
//TILE_SIZE * TILE_SIZE data copied to the shared matrix A
//and matrix B.
for (phase = 0; phase <= a_columns/TILE_SIZE; phase++)
{
shared_a_tile[ty][tx] = a[row * a_columns + phase * TILE_SIZE + tx];
shared_b_tile[ty][tx] = b[(phase * TILE_SIZE + ty) * b_columns + col];
__syncthreads();
for (k = 0; k < TILE_SIZE; k++)
{
if (k + (phase * TILE_SIZE) < a_columns)
{
result += (shared_a_tile[ty][k] * shared_b_tile[k][tx]);
}
}
__syncthreads();
}
c[row * b_columns + col] = result;
}
}
void build_matrix(FILE *file, int* mat, int rows, int columns);
int main(int argc, char **argv)
{
//check for filenames and matrices' dimensions
if (argc != 6)
{
printf("Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>");
exit(1);
}
char* fileA_name = argv[1];//matrix A filename
char* fileB_name = argv[2];//matrix B filename
// a_columns can also be perceived as b_rows
int a_rows, a_columns, b_columns;
//read matrix A and B's dimensions
sscanf(argv[3], "%d", &a_rows);
sscanf(argv[4], "%d", &a_columns);
sscanf(argv[5], "%d", &b_columns);
FILE *fileA = fopen(fileA_name, "r");
FILE *fileB = fopen(fileB_name, "r");
//declare host and device matrices pointers
int* mat_a;
int* mat_b;
int* mat_c;
int* d_mat_a;
int* d_mat_b;
int* d_mat_c;
//allocate memory for host matrices
mat_a = (int*)malloc(a_rows * a_columns * sizeof(int));
mat_b = (int*)malloc(a_columns * b_columns * sizeof(int));
mat_c = (int*)malloc(a_rows * b_columns * sizeof(int));
int i, j;
build_matrix(fileA, mat_a, a_rows, a_columns);
build_matrix(fileB, mat_b, a_columns, b_columns);
//declare dimensions for the grid and block
dim3 dimBlock(BLK_COLS,BLK_ROWS);
dim3 dimGrid((int)ceil(b_columns/BLK_COLS),(int)ceil(a_rows/BLK_ROWS));
const size_t size_a = a_rows * a_columns * sizeof(int);
const size_t size_b = a_columns * b_columns * sizeof(int);
const size_t size_c = a_rows * b_columns * sizeof(int);
//allocate matrices memeory on device
hipMalloc((void **)&d_mat_a, size_a);
hipMalloc((void **)&d_mat_b, size_b);
hipMalloc((void **)&d_mat_c, size_c);
//copy A and B matrices from host to device
hipMemcpy(d_mat_a, mat_a, size_a, hipMemcpyHostToDevice);
hipMemcpy(d_mat_b, mat_b, size_b, hipMemcpyHostToDevice);
//execute cuda kernel
matrix_mul_kernel<<<dimGrid, dimBlock>>>(d_mat_a, d_mat_b, d_mat_c, a_rows, a_columns, b_columns);
//copy the compute matrix C from device to host
hipMemcpy(mat_c, d_mat_c, size_c, hipMemcpyDeviceToHost);
//print the resulting matrix
for (i = 0; i < a_rows; i++)
{
for (j = 0; j < b_columns; j++)
{
printf("%d ", mat_c[i * b_columns + j]);
}
printf("\n");
}
//free cuda memory
hipFree(d_mat_a);
hipFree(d_mat_b);
hipFree(d_mat_c);
}
//build matrix from the file
void build_matrix(FILE *file, int* mat, int rows, int columns)
{
int i, j;
for (i = 0; i < rows; i++)
{
for (j = 0; j < columns; j++)
{
fscanf(file, "%d", &mat[i * columns + j]);
}
}
} | .text
.file "matrix_mul_tiling.hip"
.globl _Z32__device_stub__matrix_mul_kernelPiS_S_iii # -- Begin function _Z32__device_stub__matrix_mul_kernelPiS_S_iii
.p2align 4, 0x90
.type _Z32__device_stub__matrix_mul_kernelPiS_S_iii,@function
_Z32__device_stub__matrix_mul_kernelPiS_S_iii: # @_Z32__device_stub__matrix_mul_kernelPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17matrix_mul_kernelPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__matrix_mul_kernelPiS_S_iii, .Lfunc_end0-_Z32__device_stub__matrix_mul_kernelPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $6, %edi
jne .LBB1_22
# %bb.1:
movq %rsi, %r15
movq 8(%rsi), %r14
movq 16(%rsi), %rbx
movq 24(%rsi), %rdi
leaq 16(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 32(%r15), %rdi
leaq 20(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 40(%r15), %rdi
leaq 12(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movl $.L.str.2, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r13
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r12
movl 16(%rsp), %r14d
movl 20(%rsp), %ebp
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movl 12(%rsp), %ebx
movl %ebx, %eax
imull %ebp, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
imull %r14d, %ebx
movslq %ebx, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movq %r14, 96(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB1_7
# %bb.2: # %.preheader.lr.ph.i
xorl %r14d, %r14d
xorl %r15d, %r15d
movq %rbp, 24(%rsp) # 8-byte Spill
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_6: # %._crit_edge.i
# in Loop: Header=BB1_3 Depth=1
incq %r15
movq 24(%rsp), %rbp # 8-byte Reload
addl %ebp, %r14d
cmpq 96(%rsp), %r15 # 8-byte Folded Reload
je .LBB1_7
.LBB1_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
testl %ebp, %ebp
jle .LBB1_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB1_3 Depth=1
movl %r14d, %eax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movq 24(%rsp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %esi
movq %r13, %rdi
movq %rbp, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %rbp
decq %rbx
jne .LBB1_5
jmp .LBB1_6
.LBB1_7: # %_Z12build_matrixP8_IO_FILEPiii.exit
movl 20(%rsp), %eax
movq %rax, 24(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB1_13
# %bb.8: # %.preheader.lr.ph.i37
movl 12(%rsp), %r15d
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # %._crit_edge.i41
# in Loop: Header=BB1_9 Depth=1
incq %r14
addl %r15d, %ebp
cmpq 24(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_13
.LBB1_9: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
testl %r15d, %r15d
jle .LBB1_12
# %bb.10: # %.lr.ph.i44
# in Loop: Header=BB1_9 Depth=1
movl %ebp, %eax
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movq %r15, %rbx
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r13
decq %rbx
jne .LBB1_11
jmp .LBB1_12
.LBB1_13: # %_Z12build_matrixP8_IO_FILEPiii.exit49
movl 12(%rsp), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movl 16(%rsp), %edx
movl %edx, %r13d
shrl $31, %r13d
addl %edx, %r13d
sarl %r13d
shlq $32, %r13
orq %rcx, %r13
movl 20(%rsp), %ecx
movl %ecx, %esi
imull %edx, %esi
movslq %esi, %r12
shlq $2, %r12
imull %eax, %ecx
movslq %ecx, %rbp
shlq $2, %rbp
imull %eax, %edx
movslq %edx, %r14
shlq $2, %r14
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdx # imm = 0x200000002
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl 16(%rsp), %esi
movl 20(%rsp), %edi
movl 12(%rsp), %r8d
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 68(%rsp)
movl %edi, 64(%rsp)
movl %r8d, 60(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 68(%rsp), %rax
movq %rax, 200(%rsp)
leaq 64(%rsp), %rax
movq %rax, 208(%rsp)
leaq 60(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z17matrix_mul_kernelPiS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
movq 32(%rsp), %rsi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 16(%rsp)
jle .LBB1_21
# %bb.16: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_20: # %._crit_edge
# in Loop: Header=BB1_17 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 16(%rsp), %ebp
jge .LBB1_21
.LBB1_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_19 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_20
# %bb.18: # %.lr.ph.preheader
# in Loop: Header=BB1_17 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_19: # %.lr.ph
# Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_19
jmp .LBB1_20
.LBB1_21: # %._crit_edge56
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 288
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z12build_matrixP8_IO_FILEPiii # -- Begin function _Z12build_matrixP8_IO_FILEPiii
.p2align 4, 0x90
.type _Z12build_matrixP8_IO_FILEPiii,@function
_Z12build_matrixP8_IO_FILEPiii: # @_Z12build_matrixP8_IO_FILEPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %ecx, %ebx
movq %rdi, %r15
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ecx, %eax
movq %rax, (%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %ebp, %ebp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rbp
addl %ebx, %r14d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movq (%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
decq %r13
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge14
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12build_matrixP8_IO_FILEPiii, .Lfunc_end2-_Z12build_matrixP8_IO_FILEPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrix_mul_kernelPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17matrix_mul_kernelPiS_S_iii,@object # @_Z17matrix_mul_kernelPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z17matrix_mul_kernelPiS_S_iii
.p2align 3, 0x0
_Z17matrix_mul_kernelPiS_S_iii:
.quad _Z32__device_stub__matrix_mul_kernelPiS_S_iii
.size _Z17matrix_mul_kernelPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>"
.size .L.str, 77
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17matrix_mul_kernelPiS_S_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__matrix_mul_kernelPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17matrix_mul_kernelPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17matrix_mul_kernelPiS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R8, SR_TID.Y ; /* 0x0000000000087919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x180], PT ; /* 0x0000600009007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R10, R3, c[0x0][0x4], R8 ; /* 0x00000100030a7a24 */
/* 0x002fca00078e0208 */
/*0080*/ ISETP.GE.OR P0, PT, R10, c[0x0][0x178], P0 ; /* 0x00005e000a007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff027624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fc600000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x900 ; /* 0x0000081000008947 */
/* 0x000fea0003800000 */
/*00f0*/ LEA.HI R2, R2, c[0x0][0x17c], RZ, 0x1 ; /* 0x00005f0002027a11 */
/* 0x000fe200078f08ff */
/*0100*/ IMAD.SHL.U32 R3, R8, 0x8, RZ ; /* 0x0000000808037824 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD R13, R10, c[0x0][0x17c], R0 ; /* 0x00005f000a0d7a24 */
/* 0x000fe200078e0200 */
/*0130*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0140*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD R14, R0, 0x4, R3 ; /* 0x00000004000e7824 */
/* 0x000fe200078e0203 */
/*0160*/ ISETP.GE.U32.AND P1, PT, R2.reuse, 0x3, PT ; /* 0x000000030200780c */
/* 0x040fe40003f26070 */
/*0170*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fc80007ffe0ff */
/*0180*/ LOP3.LUT R12, R5, 0x3, RZ, 0xc0, !PT ; /* 0x00000003050c7812 */
/* 0x000fc800078ec0ff */
/*0190*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc60003f05270 */
/*01a0*/ @!P1 BRA 0x6c0 ; /* 0x0000051000009947 */
/* 0x000ff40003800000 */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0f7624 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R18, R5, -R12, RZ ; /* 0x8000000c05127210 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*01e0*/ IMAD.SHL.U32 R15, R15, 0x2, RZ ; /* 0x000000020f0f7824 */
/* 0x000fc600078e00ff */
/*01f0*/ SHF.L.U32 R17, R16, 0x1, RZ ; /* 0x0000000110117819 */
/* 0x000fe200000006ff */
/*0200*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fc600078e00ff */
/*0210*/ IADD3 R2, R13, R17, RZ ; /* 0x000000110d027210 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.IADD R4, R17, 0x1, R8 ; /* 0x0000000111047824 */
/* 0x000fc800078e0208 */
/*0230*/ IMAD R4, R4, c[0x0][0x180], R9 ; /* 0x0000600004047a24 */
/* 0x000fe400078e0209 */
/*0240*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0207 */
/*0250*/ IMAD.WIDE R6, R4, R7, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x000fe200078e0207 */
/*0260*/ LDG.E R21, [R2.64] ; /* 0x0000000402157981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R23, [R6.64] ; /* 0x0000000406177981 */
/* 0x000ee2000c1e1900 */
/*0280*/ IADD3 R4, R17.reuse, 0x1, RZ ; /* 0x0000000111047810 */
/* 0x040fe40007ffe0ff */
/*0290*/ ISETP.GE.AND P1, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fe40003f26270 */
/*02a0*/ ISETP.GE.AND P6, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003fc6270 */
/*02b0*/ IMAD.WIDE R4, R15, 0x4, R6 ; /* 0x000000040f047825 */
/* 0x000fe200078e0206 */
/*02c0*/ STS [R14], R21 ; /* 0x000000150e007388 */
/* 0x004fe80000000800 */
/*02d0*/ STS [R14+0x10], R23 ; /* 0x000010170e007388 */
/* 0x008fe80000000800 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ @!P1 LDS R25, [R8.X8] ; /* 0x0000000008199984 */
/* 0x000fe80000008800 */
/*0300*/ @!P1 LDS R26, [R0.X4+0x10] ; /* 0x00001000001a9984 */
/* 0x000e280000004800 */
/*0310*/ @!P6 LDS R19, [R0.X4+0x18] ; /* 0x000018000013e984 */
/* 0x000fe80000004800 */
/*0320*/ @!P6 LDS R20, [R8.X8+0x4] ; /* 0x000004000814e984 */
/* 0x000e680000008800 */
/*0330*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0340*/ LDG.E R27, [R2.64+0x8] ; /* 0x00000804021b7981 */
/* 0x000ea8000c1e1900 */
/*0350*/ LDG.E R29, [R4.64] ; /* 0x00000004041d7981 */
/* 0x000ee2000c1e1900 */
/*0360*/ IADD3 R6, R17, 0x2, RZ ; /* 0x0000000211067810 */
/* 0x000fc40007ffe0ff */
/*0370*/ IADD3 R7, R17, 0x3, RZ ; /* 0x0000000311077810 */
/* 0x000fe40007ffe0ff */
/*0380*/ ISETP.GE.AND P5, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fe40003fa6270 */
/*0390*/ ISETP.GE.AND P4, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe20003f86270 */
/*03a0*/ IMAD.WIDE R6, R15, 0x4, R4 ; /* 0x000000040f067825 */
/* 0x000fe200078e0204 */
/*03b0*/ STS [R14], R27 ; /* 0x0000001b0e007388 */
/* 0x004fe80000000800 */
/*03c0*/ STS [R14+0x10], R29 ; /* 0x0000101d0e007388 */
/* 0x008fe80000000800 */
/*03d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03e0*/ @!P5 LDS R22, [R8.X8] ; /* 0x000000000816d984 */
/* 0x000fe80000008800 */
/*03f0*/ @!P5 LDS R21, [R0.X4+0x10] ; /* 0x000010000015d984 */
/* 0x000ea80000004800 */
/*0400*/ @!P4 LDS R24, [R0.X4+0x18] ; /* 0x000018000018c984 */
/* 0x000fe80000004800 */
/*0410*/ @!P4 LDS R23, [R8.X8+0x4] ; /* 0x000004000817c984 */
/* 0x000ee80000008800 */
/*0420*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0430*/ LDG.E R28, [R2.64+0x10] ; /* 0x00001004021c7981 */
/* 0x000f28000c1e1900 */
/*0440*/ LDG.E R5, [R6.64] ; /* 0x0000000406057981 */
/* 0x000f62000c1e1900 */
/*0450*/ IADD3 R4, R17, 0x4, RZ ; /* 0x0000000411047810 */
/* 0x000fe20007ffe0ff */
/*0460*/ @!P1 IMAD R11, R25, R26, R11 ; /* 0x0000001a190b9224 */
/* 0x001fc600078e020b */
/*0470*/ ISETP.GE.AND P3, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe40003f66270 */
/*0480*/ IADD3 R4, R17, 0x5, RZ ; /* 0x0000000511047810 */
/* 0x000fc80007ffe0ff */
/*0490*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x17c], PT ; /* 0x00005f0004007a0c */
/* 0x000fe20003f46270 */
/*04a0*/ STS [R14], R28 ; /* 0x0000001c0e007388 */
/* 0x010fe80000000800 */
/*04b0*/ STS [R14+0x10], R5 ; /* 0x000010050e007388 */
/* 0x0201e80000000800 */
/*04c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*04d0*/ IMAD.WIDE R4, R15, 0x4, R6 ; /* 0x000000040f047825 */
/* 0x001fca00078e0206 */
/*04e0*/ @!P3 LDS R26, [R8.X8] ; /* 0x00000000081ab984 */
/* 0x000fe80000008800 */
/*04f0*/ @!P3 LDS R25, [R0.X4+0x10] ; /* 0x000010000019b984 */
/* 0x000e280000004800 */
/*0500*/ @!P2 LDS R7, [R0.X4+0x18] ; /* 0x000018000007a984 */
/* 0x000fe80000004800 */
/*0510*/ @!P2 LDS R6, [R8.X8+0x4] ; /* 0x000004000806a984 */
/* 0x000f280000008800 */
/*0520*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0530*/ LDG.E R3, [R2.64+0x18] ; /* 0x0000180402037981 */
/* 0x000f68000c1e1900 */
/*0540*/ LDG.E R27, [R4.64] ; /* 0x00000004041b7981 */
/* 0x000f62000c1e1900 */
/*0550*/ IADD3 R28, R17, 0x6, RZ ; /* 0x00000006111c7810 */
/* 0x000fe20007ffe0ff */
/*0560*/ @!P6 IMAD R11, R19, R20, R11 ; /* 0x00000014130be224 */
/* 0x002fe200078e020b */
/*0570*/ IADD3 R17, R17, 0x7, RZ ; /* 0x0000000711117810 */
/* 0x000fc40007ffe0ff */
/*0580*/ ISETP.GE.AND P1, PT, R28, c[0x0][0x17c], PT ; /* 0x00005f001c007a0c */
/* 0x000fe20003f26270 */
/*0590*/ @!P5 IMAD R11, R22, R21, R11 ; /* 0x00000015160bd224 */
/* 0x004fe200078e020b */
/*05a0*/ ISETP.GE.AND P6, PT, R17, c[0x0][0x17c], PT ; /* 0x00005f0011007a0c */
/* 0x000fe40003fc6270 */
/*05b0*/ IADD3 R18, R18, -0x4, RZ ; /* 0xfffffffc12127810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ @!P4 IMAD R11, R24, R23, R11 ; /* 0x00000017180bc224 */
/* 0x008fe200078e020b */
/*05d0*/ IADD3 R16, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fc60007ffe0ff */
/*05e0*/ @!P3 IMAD R11, R26, R25, R11 ; /* 0x000000191a0bb224 */
/* 0x001fc800078e020b */
/*05f0*/ @!P2 IMAD R11, R7, R6, R11 ; /* 0x00000006070ba224 */
/* 0x010fe200078e020b */
/*0600*/ ISETP.NE.AND P2, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f45270 */
/*0610*/ STS [R14], R3 ; /* 0x000000030e007388 */
/* 0x020fe80000000800 */
/*0620*/ STS [R14+0x10], R27 ; /* 0x0000101b0e007388 */
/* 0x000fe80000000800 */
/*0630*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0640*/ @!P1 LDS R20, [R8.X8] ; /* 0x0000000008149984 */
/* 0x000fe80000008800 */
/*0650*/ @!P1 LDS R2, [R0.X4+0x10] ; /* 0x0000100000029984 */
/* 0x000e280000004800 */
/*0660*/ @!P6 LDS R4, [R0.X4+0x18] ; /* 0x000018000004e984 */
/* 0x000fe80000004800 */
/*0670*/ @!P6 LDS R5, [R8.X8+0x4] ; /* 0x000004000805e984 */
/* 0x000e620000008800 */
/*0680*/ @!P1 IMAD R11, R20, R2, R11 ; /* 0x00000002140b9224 */
/* 0x001fc800078e020b */
/*0690*/ @!P6 IMAD R11, R4, R5, R11 ; /* 0x00000005040be224 */
/* 0x002fe200078e020b */
/*06a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*06b0*/ @P2 BRA 0x1f0 ; /* 0xfffffb3000002947 */
/* 0x000fea000383ffff */
/*06c0*/ @!P0 BRA 0x900 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD R2, R16.reuse, 0x2, R13 ; /* 0x0000000210027824 */
/* 0x040fe200078e020d */
/*06e0*/ LEA R4, R16.reuse, R8, 0x1 ; /* 0x0000000810047211 */
/* 0x040fe200078e08ff */
/*06f0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0700*/ LEA R16, R16, 0x1, 0x1 ; /* 0x0000000110107811 */
/* 0x000fe200078e08ff */
/*0710*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff067624 */
/* 0x000fc400078e00ff */
/*0720*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e0205 */
/*0730*/ IMAD R4, R4, c[0x0][0x180], R9 ; /* 0x0000600004047a24 */
/* 0x000fe200078e0209 */
/*0740*/ MOV R20, R3 ; /* 0x0000000300147202 */
/* 0x000fe20000000f00 */
/*0750*/ IMAD.MOV.U32 R15, RZ, RZ, R2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0002 */
/*0760*/ IMAD.SHL.U32 R17, R6, 0x2, RZ ; /* 0x0000000206117824 */
/* 0x000fe400078e00ff */
/*0770*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0780*/ MOV R5, R20 ; /* 0x0000001400057202 */
/* 0x000fe20000000f00 */
/*0790*/ IMAD.MOV.U32 R4, RZ, RZ, R15 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000f */
/*07a0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x0000a8000c1e1900 */
/*07b0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee2000c1e1900 */
/*07c0*/ IADD3 R6, R16, -0x1, RZ ; /* 0xffffffff10067810 */
/* 0x000fc80007ffe0ff */
/*07d0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fe40003f06270 */
/*07e0*/ ISETP.GE.AND P1, PT, R16, c[0x0][0x17c], PT ; /* 0x00005f0010007a0c */
/* 0x000fe40003f26270 */
/*07f0*/ IADD3 R12, R12, -0x1, RZ ; /* 0xffffffff0c0c7810 */
/* 0x000fc80007ffe0ff */
/*0800*/ ISETP.NE.AND P2, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fe20003f45270 */
/*0810*/ IMAD.WIDE R2, R17, 0x4, R2 ; /* 0x0000000411027825 */
/* 0x001fe200078e0202 */
/*0820*/ IADD3 R16, R16, 0x2, RZ ; /* 0x0000000210107810 */
/* 0x000fe20007ffe0ff */
/*0830*/ STS [R14+0x10], R7 ; /* 0x000010070e007388 */
/* 0x004fe80000000800 */
/*0840*/ STS [R14], R5 ; /* 0x000000050e007388 */
/* 0x008fe80000000800 */
/*0850*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0860*/ @!P0 LDS R6, [R8.X8] ; /* 0x0000000008068984 */
/* 0x000fe80000008800 */
/*0870*/ @!P0 LDS R13, [R0.X4+0x10] ; /* 0x00001000000d8984 */
/* 0x000e280000004800 */
/*0880*/ @!P1 LDS R18, [R0.X4+0x18] ; /* 0x0000180000129984 */
/* 0x000fe80000004800 */
/*0890*/ @!P1 LDS R4, [R8.X8+0x4] ; /* 0x0000040008049984 */
/* 0x000e620000008800 */
/*08a0*/ @!P0 IMAD R11, R6, R13, R11 ; /* 0x0000000d060b8224 */
/* 0x001fc600078e020b */
/*08b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*08c0*/ IADD3 R15, P0, R15, 0x8, RZ ; /* 0x000000080f0f7810 */
/* 0x000fca0007f1e0ff */
/*08d0*/ IMAD.X R20, RZ, RZ, R20, P0 ; /* 0x000000ffff147224 */
/* 0x000fe400000e0614 */
/*08e0*/ @!P1 IMAD R11, R18, R4, R11 ; /* 0x00000004120b9224 */
/* 0x002fe200078e020b */
/*08f0*/ @P2 BRA 0x780 ; /* 0xfffffe8000002947 */
/* 0x000fea000383ffff */
/*0900*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0910*/ IMAD R2, R10, c[0x0][0x180], R9 ; /* 0x000060000a027a24 */
/* 0x000fc800078e0209 */
/*0920*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*0930*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*0940*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0950*/ BRA 0x950; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17matrix_mul_kernelPiS_S_iii
.globl _Z17matrix_mul_kernelPiS_S_iii
.p2align 8
.type _Z17matrix_mul_kernelPiS_S_iii,@function
_Z17matrix_mul_kernelPiS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v6, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
v_mad_u64_u32 v[1:2], null, s14, s5, v[6:7]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_10
s_load_b32 s2, s[0:1], 0x1c
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, -1
s_cbranch_scc1 .LBB0_9
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v2, 2, v6
v_lshlrev_b32_e32 v7, 3, v3
s_lshr_b32 s8, s2, 31
s_mov_b32 s9, 0
s_add_i32 s8, s2, s8
v_add_nc_u32_e32 v8, 16, v2
v_mad_u64_u32 v[4:5], null, v0, s2, v[6:7]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v5, v7, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v6, v8, v7
s_ashr_i32 s8, s8, 1
s_mov_b32 s10, 0
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
s_lshl_b32 s11, s10, 1
s_mov_b32 s12, 0
v_add_nc_u32_e32 v10, s11, v3
v_add_nc_u32_e32 v9, s11, v4
s_mov_b32 s11, s9
v_mad_u64_u32 v[11:12], null, v10, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v12, 31, v11
s_waitcnt lgkmcnt(0)
v_add_co_u32 v9, vcc_lo, s4, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v10, v[9:10], off
global_load_b32 v11, v[11:12], off
v_mov_b32_e32 v9, v8
s_waitcnt vmcnt(1)
ds_store_b32 v5, v10
s_waitcnt vmcnt(0)
ds_store_b32 v6, v11
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_5
.LBB0_4:
v_add_nc_u32_e32 v9, 8, v9
s_add_i32 s12, s12, 4
s_add_i32 s11, s11, 1
s_cmp_eq_u32 s12, 4
s_cbranch_scc0 .LBB0_7
.LBB0_5:
s_cmp_ge_i32 s11, s2
s_cbranch_scc1 .LBB0_4
v_add_nc_u32_e32 v10, s12, v7
ds_load_b32 v12, v10
ds_load_b32 v13, v9
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[10:11], null, v13, v12, v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mov_b32_e32 v2, v10
s_branch .LBB0_4
.LBB0_7:
s_add_i32 s11, s10, 1
s_add_i32 s9, s9, 2
s_cmp_lg_u32 s10, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_9
s_mov_b32 s10, s11
s_branch .LBB0_3
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[3:4], null, v0, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matrix_mul_kernelPiS_S_iii
.amdhsa_group_segment_fixed_size 32
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17matrix_mul_kernelPiS_S_iii, .Lfunc_end0-_Z17matrix_mul_kernelPiS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 32
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matrix_mul_kernelPiS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matrix_mul_kernelPiS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00084e05_00000000-6_matrix_mul_tiling.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.text
.globl _Z12build_matrixP8_IO_FILEPiii
.type _Z12build_matrixP8_IO_FILEPiii, @function
_Z12build_matrixP8_IO_FILEPiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, 8(%rsp)
movl %edx, 4(%rsp)
testl %edx, %edx
jle .L3
movq %rdi, %r12
movl %ecx, %r14d
movl $0, (%rsp)
movl $0, %r15d
leaq .LC0(%rip), %r13
jmp .L5
.L7:
movslq (%rsp), %rdx
movq 8(%rsp), %rcx
leaq (%rcx,%rdx,4), %rbx
movslq %r14d, %rax
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L6:
movq %rbx, %rdx
movq %r13, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
addl $1, %r15d
addl %r14d, (%rsp)
cmpl %r15d, 4(%rsp)
je .L3
.L5:
testl %r14d, %r14d
jg .L7
jmp .L8
.L3:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12build_matrixP8_IO_FILEPiii, .-_Z12build_matrixP8_IO_FILEPiii
.globl _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
.type _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii, @function
_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17matrix_mul_kernelPiS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii, .-_Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
.globl _Z17matrix_mul_kernelPiS_S_iii
.type _Z17matrix_mul_kernelPiS_S_iii, @function
_Z17matrix_mul_kernelPiS_S_iii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z17matrix_mul_kernelPiS_S_iii, .-_Z17matrix_mul_kernelPiS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>"
.section .rodata.str1.1
.LC2:
.string "r"
.LC3:
.string "%d "
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
cmpl $6, %edi
jne .L33
movq %rsi, %rbx
movq 8(%rsi), %r13
movq 16(%rsi), %r12
leaq 28(%rsp), %rdx
movq 24(%rsi), %rdi
leaq .LC0(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 32(%rsp), %rdx
movq 32(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 36(%rsp), %rdx
movq 40(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq .LC2(%rip), %rbx
movq %rbx, %rsi
movq %r13, %rdi
call fopen@PLT
movq %rax, %r13
movq %rbx, %rsi
movq %r12, %rdi
call fopen@PLT
movq %rax, 8(%rsp)
movl 28(%rsp), %r14d
movl 32(%rsp), %r15d
movl %r14d, %ecx
imull %r15d, %ecx
movslq %ecx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %r12
movl 36(%rsp), %ebx
movl %r15d, %ecx
imull %ebx, %ecx
movslq %ecx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbp
imull %r14d, %ebx
movslq %ebx, %rdi
salq $2, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r15d, %ecx
movl %r14d, %edx
movq %r12, %rsi
movq %r13, %rdi
call _Z12build_matrixP8_IO_FILEPiii
movl 36(%rsp), %ecx
movl 32(%rsp), %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call _Z12build_matrixP8_IO_FILEPiii
movl $2, 64(%rsp)
movl $2, 68(%rsp)
movl $1, 72(%rsp)
movl 28(%rsp), %eax
movl 36(%rsp), %ecx
movl %ecx, %edx
shrl $31, %edx
addl %ecx, %edx
sarl %edx
movl %edx, 76(%rsp)
movl %eax, %edx
shrl $31, %edx
addl %eax, %edx
sarl %edx
movl %edx, 80(%rsp)
movl $1, 84(%rsp)
movl 32(%rsp), %edx
movl %eax, %r14d
imull %edx, %r14d
movslq %r14d, %r14
salq $2, %r14
imull %ecx, %edx
movslq %edx, %r13
salq $2, %r13
imull %ecx, %eax
movslq %eax, %r15
salq $2, %r15
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r13, %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L21:
movl $2, %ecx
movq %r15, %rdx
movq 56(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl $0, %r12d
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r14
cmpl $0, 28(%rsp)
jg .L22
.L23:
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl 36(%rsp), %r9d
movl 32(%rsp), %r8d
movl 28(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z44__device_stub__Z17matrix_mul_kernelPiS_S_iiiPiS_S_iii
jmp .L21
.L24:
imull %r12d, %eax
addl %ebp, %eax
cltq
movl (%rbx,%rax,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
movl 36(%rsp), %eax
cmpl %ebp, %eax
jg .L24
.L25:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r12d
cmpl %r12d, 28(%rsp)
jle .L23
.L22:
movl 36(%rsp), %eax
movl $0, %ebp
testl %eax, %eax
jg .L24
jmp .L25
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z17matrix_mul_kernelPiS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matrix_mul_kernelPiS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mul_tiling.hip"
.globl _Z32__device_stub__matrix_mul_kernelPiS_S_iii # -- Begin function _Z32__device_stub__matrix_mul_kernelPiS_S_iii
.p2align 4, 0x90
.type _Z32__device_stub__matrix_mul_kernelPiS_S_iii,@function
_Z32__device_stub__matrix_mul_kernelPiS_S_iii: # @_Z32__device_stub__matrix_mul_kernelPiS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17matrix_mul_kernelPiS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__matrix_mul_kernelPiS_S_iii, .Lfunc_end0-_Z32__device_stub__matrix_mul_kernelPiS_S_iii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $6, %edi
jne .LBB1_22
# %bb.1:
movq %rsi, %r15
movq 8(%rsi), %r14
movq 16(%rsi), %rbx
movq 24(%rsi), %rdi
leaq 16(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 32(%r15), %rdi
leaq 20(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 40(%r15), %rdi
leaq 12(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movl $.L.str.2, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r13
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %r12
movl 16(%rsp), %r14d
movl 20(%rsp), %ebp
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 80(%rsp) # 8-byte Spill
movl 12(%rsp), %ebx
movl %ebx, %eax
imull %ebp, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 72(%rsp) # 8-byte Spill
imull %r14d, %ebx
movslq %ebx, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
movq %r14, 96(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB1_7
# %bb.2: # %.preheader.lr.ph.i
xorl %r14d, %r14d
xorl %r15d, %r15d
movq %rbp, 24(%rsp) # 8-byte Spill
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_6: # %._crit_edge.i
# in Loop: Header=BB1_3 Depth=1
incq %r15
movq 24(%rsp), %rbp # 8-byte Reload
addl %ebp, %r14d
cmpq 96(%rsp), %r15 # 8-byte Folded Reload
je .LBB1_7
.LBB1_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB1_5 Depth 2
testl %ebp, %ebp
jle .LBB1_6
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB1_3 Depth=1
movl %r14d, %eax
movq 80(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
movq 24(%rsp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB1_5: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %esi
movq %r13, %rdi
movq %rbp, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %rbp
decq %rbx
jne .LBB1_5
jmp .LBB1_6
.LBB1_7: # %_Z12build_matrixP8_IO_FILEPiii.exit
movl 20(%rsp), %eax
movq %rax, 24(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB1_13
# %bb.8: # %.preheader.lr.ph.i37
movl 12(%rsp), %r15d
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_12: # %._crit_edge.i41
# in Loop: Header=BB1_9 Depth=1
incq %r14
addl %r15d, %ebp
cmpq 24(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_13
.LBB1_9: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB1_11 Depth 2
testl %r15d, %r15d
jle .LBB1_12
# %bb.10: # %.lr.ph.i44
# in Loop: Header=BB1_9 Depth=1
movl %ebp, %eax
movq 72(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r13
movq %r15, %rbx
.p2align 4, 0x90
.LBB1_11: # Parent Loop BB1_9 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %esi
movq %r12, %rdi
movq %r13, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r13
decq %rbx
jne .LBB1_11
jmp .LBB1_12
.LBB1_13: # %_Z12build_matrixP8_IO_FILEPiii.exit49
movl 12(%rsp), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movl 16(%rsp), %edx
movl %edx, %r13d
shrl $31, %r13d
addl %edx, %r13d
sarl %r13d
shlq $32, %r13
orq %rcx, %r13
movl 20(%rsp), %ecx
movl %ecx, %esi
imull %edx, %esi
movslq %esi, %r12
shlq $2, %r12
imull %eax, %ecx
movslq %ecx, %rbp
shlq $2, %rbp
imull %eax, %edx
movslq %edx, %r14
shlq $2, %r14
leaq 48(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq 72(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $8589934594, %rdx # imm = 0x200000002
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_15
# %bb.14:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl 16(%rsp), %esi
movl 20(%rsp), %edi
movl 12(%rsp), %r8d
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 68(%rsp)
movl %edi, 64(%rsp)
movl %r8d, 60(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 68(%rsp), %rax
movq %rax, 200(%rsp)
leaq 64(%rsp), %rax
movq %rax, 208(%rsp)
leaq 60(%rsp), %rax
movq %rax, 216(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z17matrix_mul_kernelPiS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_15:
movq 32(%rsp), %rsi
movq 88(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $0, 16(%rsp)
jle .LBB1_21
# %bb.16: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB1_17
.p2align 4, 0x90
.LBB1_20: # %._crit_edge
# in Loop: Header=BB1_17 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 16(%rsp), %ebp
jge .LBB1_21
.LBB1_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_19 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_20
# %bb.18: # %.lr.ph.preheader
# in Loop: Header=BB1_17 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_19: # %.lr.ph
# Parent Loop BB1_17 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r14, %rax
movl (%rbx,%rax,4), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r14
cmpl %eax, %r14d
jl .LBB1_19
jmp .LBB1_20
.LBB1_21: # %._crit_edge56
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 288
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z12build_matrixP8_IO_FILEPiii # -- Begin function _Z12build_matrixP8_IO_FILEPiii
.p2align 4, 0x90
.type _Z12build_matrixP8_IO_FILEPiii,@function
_Z12build_matrixP8_IO_FILEPiii: # @_Z12build_matrixP8_IO_FILEPiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 8(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %ecx, %ebx
movq %rdi, %r15
movl %edx, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ecx, %eax
movq %rax, (%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %ebp, %ebp
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %rbp
addl %ebx, %r14d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %ebx, %ebx
jle .LBB2_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB2_2 Depth=1
movl %r14d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
movq (%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %esi
movq %r15, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r12
decq %r13
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge14
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z12build_matrixP8_IO_FILEPiii, .Lfunc_end2-_Z12build_matrixP8_IO_FILEPiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matrix_mul_kernelPiS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17matrix_mul_kernelPiS_S_iii,@object # @_Z17matrix_mul_kernelPiS_S_iii
.section .rodata,"a",@progbits
.globl _Z17matrix_mul_kernelPiS_S_iii
.p2align 3, 0x0
_Z17matrix_mul_kernelPiS_S_iii:
.quad _Z32__device_stub__matrix_mul_kernelPiS_S_iii
.size _Z17matrix_mul_kernelPiS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage : ./matrix_mul_tiling <fileA> <fileB> <A_rows> <A_columns> <B_columns>"
.size .L.str, 77
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d "
.size .L.str.3, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z17matrix_mul_kernelPiS_S_iii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__matrix_mul_kernelPiS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17matrix_mul_kernelPiS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__device__ int x;
__global__ void unaligned_kernel(void) { *(int*) ((char*)&x + 1) = 42; }
__device__ void out_of_bounds_function(void) { *(int*) 0x87654320 = 42; }
__global__ void out_of_bounds_kernel(void) { out_of_bounds_function(); }
void run_unaligned(void) { printf("Running unaligned_kernel\n"); unaligned_kernel<<<1,1>>>(); printf("Ran unaligned_kernel: %s\n", cudaGetErrorString(cudaGetLastError())); printf("Sync: %s\n", cudaGetErrorString(cudaThreadSynchronize())); }
void run_out_of_bounds(void) { printf("Running out_of_bounds_kernel\n"); out_of_bounds_kernel<<<1,1>>>(); printf("Ran out_of_bounds_kernel: %s\n", cudaGetErrorString(cudaGetLastError())); printf("Sync: %s\n", cudaGetErrorString(cudaThreadSynchronize())); }
int main() { int *devMem; printf("Mallocing memory\n"); cudaMalloc((void**)&devMem, 1024); run_unaligned(); run_out_of_bounds(); cudaDeviceReset(); cudaFree(devMem); return 0; } | code for sm_80
Function : _Z20out_of_bounds_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ UMOV UR4, 0x80000000 ; /* 0x8000000000047882 */
/* 0x000fe20000000000 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.50339508056640625e-06 ; /* 0x0000002aff057435 */
/* 0x000fe200000001ff */
/*0030*/ UIADD3 UR5, UP0, UR4, 0x7000000, URZ ; /* 0x0700000004057890 */
/* 0x000fc6000ff1e03f */
/*0040*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0050*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe200087fe43f */
/*0060*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fca000f8e00ff */
/*0070*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe20008000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ ST.E [R2.64+0x654320], R5 ; /* 0x6543200502007985 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16unaligned_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; /* 0x0000002aff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x4][0x4] ; /* 0x0100010000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64+0x1], R5 ; /* 0x0000010502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__device__ int x;
__global__ void unaligned_kernel(void) { *(int*) ((char*)&x + 1) = 42; }
__device__ void out_of_bounds_function(void) { *(int*) 0x87654320 = 42; }
__global__ void out_of_bounds_kernel(void) { out_of_bounds_function(); }
void run_unaligned(void) { printf("Running unaligned_kernel\n"); unaligned_kernel<<<1,1>>>(); printf("Ran unaligned_kernel: %s\n", cudaGetErrorString(cudaGetLastError())); printf("Sync: %s\n", cudaGetErrorString(cudaThreadSynchronize())); }
void run_out_of_bounds(void) { printf("Running out_of_bounds_kernel\n"); out_of_bounds_kernel<<<1,1>>>(); printf("Ran out_of_bounds_kernel: %s\n", cudaGetErrorString(cudaGetLastError())); printf("Sync: %s\n", cudaGetErrorString(cudaThreadSynchronize())); }
int main() { int *devMem; printf("Mallocing memory\n"); cudaMalloc((void**)&devMem, 1024); run_unaligned(); run_out_of_bounds(); cudaDeviceReset(); cudaFree(devMem); return 0; } | .file "tmpxft_000e25d0_00000000-6_memcheck_demo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22out_of_bounds_functionv
.type _Z22out_of_bounds_functionv, @function
_Z22out_of_bounds_functionv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z22out_of_bounds_functionv, .-_Z22out_of_bounds_functionv
.globl _Z35__device_stub__Z16unaligned_kernelvv
.type _Z35__device_stub__Z16unaligned_kernelvv, @function
_Z35__device_stub__Z16unaligned_kernelvv:
.LFB2085:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z16unaligned_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z16unaligned_kernelvv, .-_Z35__device_stub__Z16unaligned_kernelvv
.globl _Z16unaligned_kernelv
.type _Z16unaligned_kernelv, @function
_Z16unaligned_kernelv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z16unaligned_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z16unaligned_kernelv, .-_Z16unaligned_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Running unaligned_kernel\n"
.LC1:
.string "Ran unaligned_kernel: %s\n"
.LC2:
.string "Sync: %s\n"
.text
.globl _Z13run_unalignedv
.type _Z13run_unalignedv, @function
_Z13run_unalignedv:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _Z35__device_stub__Z16unaligned_kernelvv
jmp .L14
.cfi_endproc
.LFE2058:
.size _Z13run_unalignedv, .-_Z13run_unalignedv
.globl _Z39__device_stub__Z20out_of_bounds_kernelvv
.type _Z39__device_stub__Z20out_of_bounds_kernelvv, @function
_Z39__device_stub__Z20out_of_bounds_kernelvv:
.LFB2087:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z20out_of_bounds_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z39__device_stub__Z20out_of_bounds_kernelvv, .-_Z39__device_stub__Z20out_of_bounds_kernelvv
.globl _Z20out_of_bounds_kernelv
.type _Z20out_of_bounds_kernelv, @function
_Z20out_of_bounds_kernelv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z20out_of_bounds_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z20out_of_bounds_kernelv, .-_Z20out_of_bounds_kernelv
.section .rodata.str1.1
.LC3:
.string "Running out_of_bounds_kernel\n"
.LC4:
.string "Ran out_of_bounds_kernel: %s\n"
.text
.globl _Z17run_out_of_boundsv
.type _Z17run_out_of_boundsv, @function
_Z17run_out_of_boundsv:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L26:
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call _Z39__device_stub__Z20out_of_bounds_kernelvv
jmp .L26
.cfi_endproc
.LFE2059:
.size _Z17run_out_of_boundsv, .-_Z17run_out_of_boundsv
.section .rodata.str1.1
.LC5:
.string "Mallocing memory\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
call _Z13run_unalignedv
call _Z17run_out_of_boundsv
call cudaDeviceReset@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z20out_of_bounds_kernelv"
.LC7:
.string "_Z16unaligned_kernelv"
.LC8:
.string "x"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z20out_of_bounds_kernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16unaligned_kernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1x(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1x
.comm _ZL1x,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__device__ int x;
__global__ void unaligned_kernel(void) { *(int*) ((char*)&x + 1) = 42; }
__device__ void out_of_bounds_function(void) { *(int*) 0x87654320 = 42; }
__global__ void out_of_bounds_kernel(void) { out_of_bounds_function(); }
void run_unaligned(void) { printf("Running unaligned_kernel\n"); unaligned_kernel<<<1,1>>>(); printf("Ran unaligned_kernel: %s\n", cudaGetErrorString(cudaGetLastError())); printf("Sync: %s\n", cudaGetErrorString(cudaThreadSynchronize())); }
void run_out_of_bounds(void) { printf("Running out_of_bounds_kernel\n"); out_of_bounds_kernel<<<1,1>>>(); printf("Ran out_of_bounds_kernel: %s\n", cudaGetErrorString(cudaGetLastError())); printf("Sync: %s\n", cudaGetErrorString(cudaThreadSynchronize())); }
int main() { int *devMem; printf("Mallocing memory\n"); cudaMalloc((void**)&devMem, 1024); run_unaligned(); run_out_of_bounds(); cudaDeviceReset(); cudaFree(devMem); return 0; } | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ int x;
__global__ void unaligned_kernel(void) { *(int*) ((char*)&x + 1) = 42; }
__device__ void out_of_bounds_function(void) { *(int*) 0x87654320 = 42; }
__global__ void out_of_bounds_kernel(void) { out_of_bounds_function(); }
void run_unaligned(void) { printf("Running unaligned_kernel\n"); unaligned_kernel<<<1,1>>>(); printf("Ran unaligned_kernel: %s\n", hipGetErrorString(hipGetLastError())); printf("Sync: %s\n", hipGetErrorString(hipDeviceSynchronize())); }
void run_out_of_bounds(void) { printf("Running out_of_bounds_kernel\n"); out_of_bounds_kernel<<<1,1>>>(); printf("Ran out_of_bounds_kernel: %s\n", hipGetErrorString(hipGetLastError())); printf("Sync: %s\n", hipGetErrorString(hipDeviceSynchronize())); }
int main() { int *devMem; printf("Mallocing memory\n"); hipMalloc((void**)&devMem, 1024); run_unaligned(); run_out_of_bounds(); hipDeviceReset(); hipFree(devMem); return 0; } |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ int x;
__global__ void unaligned_kernel(void) { *(int*) ((char*)&x + 1) = 42; }
__device__ void out_of_bounds_function(void) { *(int*) 0x87654320 = 42; }
__global__ void out_of_bounds_kernel(void) { out_of_bounds_function(); }
void run_unaligned(void) { printf("Running unaligned_kernel\n"); unaligned_kernel<<<1,1>>>(); printf("Ran unaligned_kernel: %s\n", hipGetErrorString(hipGetLastError())); printf("Sync: %s\n", hipGetErrorString(hipDeviceSynchronize())); }
void run_out_of_bounds(void) { printf("Running out_of_bounds_kernel\n"); out_of_bounds_kernel<<<1,1>>>(); printf("Ran out_of_bounds_kernel: %s\n", hipGetErrorString(hipGetLastError())); printf("Sync: %s\n", hipGetErrorString(hipDeviceSynchronize())); }
int main() { int *devMem; printf("Mallocing memory\n"); hipMalloc((void**)&devMem, 1024); run_unaligned(); run_out_of_bounds(); hipDeviceReset(); hipFree(devMem); return 0; } | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16unaligned_kernelv
.globl _Z16unaligned_kernelv
.p2align 8
.type _Z16unaligned_kernelv,@function
_Z16unaligned_kernelv:
v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, x@rel32@lo+5
s_addc_u32 s1, s1, x@rel32@hi+13
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16unaligned_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16unaligned_kernelv, .Lfunc_end0-_Z16unaligned_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20out_of_bounds_kernelv
.globl _Z20out_of_bounds_kernelv
.p2align 8
.type _Z20out_of_bounds_kernelv,@function
_Z20out_of_bounds_kernelv:
v_mov_b32_e32 v0, 0x87654320
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 42
flat_store_b32 v[0:1], v2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20out_of_bounds_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20out_of_bounds_kernelv, .Lfunc_end1-_Z20out_of_bounds_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected x
.type x,@object
.section .bss,"aw",@nobits
.globl x
.p2align 2, 0x0
x:
.long 0
.size x, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym x
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16unaligned_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z16unaligned_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20out_of_bounds_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z20out_of_bounds_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ int x;
__global__ void unaligned_kernel(void) { *(int*) ((char*)&x + 1) = 42; }
__device__ void out_of_bounds_function(void) { *(int*) 0x87654320 = 42; }
__global__ void out_of_bounds_kernel(void) { out_of_bounds_function(); }
void run_unaligned(void) { printf("Running unaligned_kernel\n"); unaligned_kernel<<<1,1>>>(); printf("Ran unaligned_kernel: %s\n", hipGetErrorString(hipGetLastError())); printf("Sync: %s\n", hipGetErrorString(hipDeviceSynchronize())); }
void run_out_of_bounds(void) { printf("Running out_of_bounds_kernel\n"); out_of_bounds_kernel<<<1,1>>>(); printf("Ran out_of_bounds_kernel: %s\n", hipGetErrorString(hipGetLastError())); printf("Sync: %s\n", hipGetErrorString(hipDeviceSynchronize())); }
int main() { int *devMem; printf("Mallocing memory\n"); hipMalloc((void**)&devMem, 1024); run_unaligned(); run_out_of_bounds(); hipDeviceReset(); hipFree(devMem); return 0; } | .text
.file "memcheck_demo.hip"
.globl _Z31__device_stub__unaligned_kernelv # -- Begin function _Z31__device_stub__unaligned_kernelv
.p2align 4, 0x90
.type _Z31__device_stub__unaligned_kernelv,@function
_Z31__device_stub__unaligned_kernelv: # @_Z31__device_stub__unaligned_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z16unaligned_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z31__device_stub__unaligned_kernelv, .Lfunc_end0-_Z31__device_stub__unaligned_kernelv
.cfi_endproc
# -- End function
.globl _Z35__device_stub__out_of_bounds_kernelv # -- Begin function _Z35__device_stub__out_of_bounds_kernelv
.p2align 4, 0x90
.type _Z35__device_stub__out_of_bounds_kernelv,@function
_Z35__device_stub__out_of_bounds_kernelv: # @_Z35__device_stub__out_of_bounds_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z20out_of_bounds_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z35__device_stub__out_of_bounds_kernelv, .Lfunc_end1-_Z35__device_stub__out_of_bounds_kernelv
.cfi_endproc
# -- End function
.globl _Z13run_unalignedv # -- Begin function _Z13run_unalignedv
.p2align 4, 0x90
.type _Z13run_unalignedv,@function
_Z13run_unalignedv: # @_Z13run_unalignedv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z16unaligned_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13run_unalignedv, .Lfunc_end2-_Z13run_unalignedv
.cfi_endproc
# -- End function
.globl _Z17run_out_of_boundsv # -- Begin function _Z17run_out_of_boundsv
.p2align 4, 0x90
.type _Z17run_out_of_boundsv,@function
_Z17run_out_of_boundsv: # @_Z17run_out_of_boundsv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr.1, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z20out_of_bounds_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17run_out_of_boundsv, .Lfunc_end3-_Z17run_out_of_boundsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.2, %edi
callq puts@PLT
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
callq _Z13run_unalignedv
callq _Z17run_out_of_boundsv
callq hipDeviceReset
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16unaligned_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20out_of_bounds_kernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $x, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type x,@object # @x
.local x
.comm x,4,4
.type _Z16unaligned_kernelv,@object # @_Z16unaligned_kernelv
.section .rodata,"a",@progbits
.globl _Z16unaligned_kernelv
.p2align 3, 0x0
_Z16unaligned_kernelv:
.quad _Z31__device_stub__unaligned_kernelv
.size _Z16unaligned_kernelv, 8
.type _Z20out_of_bounds_kernelv,@object # @_Z20out_of_bounds_kernelv
.globl _Z20out_of_bounds_kernelv
.p2align 3, 0x0
_Z20out_of_bounds_kernelv:
.quad _Z35__device_stub__out_of_bounds_kernelv
.size _Z20out_of_bounds_kernelv, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Ran unaligned_kernel: %s\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Sync: %s\n"
.size .L.str.2, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Ran out_of_bounds_kernel: %s\n"
.size .L.str.4, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16unaligned_kernelv"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20out_of_bounds_kernelv"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "x"
.size .L__unnamed_3, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running unaligned_kernel"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Running out_of_bounds_kernel"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Mallocing memory"
.size .Lstr.2, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__unaligned_kernelv
.addrsig_sym _Z35__device_stub__out_of_bounds_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym x
.addrsig_sym _Z16unaligned_kernelv
.addrsig_sym _Z20out_of_bounds_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20out_of_bounds_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ UMOV UR4, 0x80000000 ; /* 0x8000000000047882 */
/* 0x000fe20000000000 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.50339508056640625e-06 ; /* 0x0000002aff057435 */
/* 0x000fe200000001ff */
/*0030*/ UIADD3 UR5, UP0, UR4, 0x7000000, URZ ; /* 0x0700000004057890 */
/* 0x000fc6000ff1e03f */
/*0040*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0050*/ UIADD3.X UR4, URZ, UR4, URZ, UP0, !UPT ; /* 0x000000043f047290 */
/* 0x000fe200087fe43f */
/*0060*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fca000f8e00ff */
/*0070*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fe20008000f00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ ST.E [R2.64+0x654320], R5 ; /* 0x6543200502007985 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16unaligned_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x2a ; /* 0x0000002aff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x4][0x4] ; /* 0x0100010000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64+0x1], R5 ; /* 0x0000010502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16unaligned_kernelv
.globl _Z16unaligned_kernelv
.p2align 8
.type _Z16unaligned_kernelv,@function
_Z16unaligned_kernelv:
v_dual_mov_b32 v0, 42 :: v_dual_mov_b32 v1, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, x@rel32@lo+5
s_addc_u32 s1, s1, x@rel32@hi+13
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16unaligned_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16unaligned_kernelv, .Lfunc_end0-_Z16unaligned_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20out_of_bounds_kernelv
.globl _Z20out_of_bounds_kernelv
.p2align 8
.type _Z20out_of_bounds_kernelv,@function
_Z20out_of_bounds_kernelv:
v_mov_b32_e32 v0, 0x87654320
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 42
flat_store_b32 v[0:1], v2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20out_of_bounds_kernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z20out_of_bounds_kernelv, .Lfunc_end1-_Z20out_of_bounds_kernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected x
.type x,@object
.section .bss,"aw",@nobits
.globl x
.p2align 2, 0x0
x:
.long 0
.size x, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym x
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16unaligned_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z16unaligned_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20out_of_bounds_kernelv
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z20out_of_bounds_kernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e25d0_00000000-6_memcheck_demo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22out_of_bounds_functionv
.type _Z22out_of_bounds_functionv, @function
_Z22out_of_bounds_functionv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z22out_of_bounds_functionv, .-_Z22out_of_bounds_functionv
.globl _Z35__device_stub__Z16unaligned_kernelvv
.type _Z35__device_stub__Z16unaligned_kernelvv, @function
_Z35__device_stub__Z16unaligned_kernelvv:
.LFB2085:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z16unaligned_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z16unaligned_kernelvv, .-_Z35__device_stub__Z16unaligned_kernelvv
.globl _Z16unaligned_kernelv
.type _Z16unaligned_kernelv, @function
_Z16unaligned_kernelv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z16unaligned_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z16unaligned_kernelv, .-_Z16unaligned_kernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Running unaligned_kernel\n"
.LC1:
.string "Ran unaligned_kernel: %s\n"
.LC2:
.string "Sync: %s\n"
.text
.globl _Z13run_unalignedv
.type _Z13run_unalignedv, @function
_Z13run_unalignedv:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L14:
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call _Z35__device_stub__Z16unaligned_kernelvv
jmp .L14
.cfi_endproc
.LFE2058:
.size _Z13run_unalignedv, .-_Z13run_unalignedv
.globl _Z39__device_stub__Z20out_of_bounds_kernelvv
.type _Z39__device_stub__Z20out_of_bounds_kernelvv, @function
_Z39__device_stub__Z20out_of_bounds_kernelvv:
.LFB2087:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z20out_of_bounds_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z39__device_stub__Z20out_of_bounds_kernelvv, .-_Z39__device_stub__Z20out_of_bounds_kernelvv
.globl _Z20out_of_bounds_kernelv
.type _Z20out_of_bounds_kernelv, @function
_Z20out_of_bounds_kernelv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z20out_of_bounds_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z20out_of_bounds_kernelv, .-_Z20out_of_bounds_kernelv
.section .rodata.str1.1
.LC3:
.string "Running out_of_bounds_kernel\n"
.LC4:
.string "Ran out_of_bounds_kernel: %s\n"
.text
.globl _Z17run_out_of_boundsv
.type _Z17run_out_of_boundsv, @function
_Z17run_out_of_boundsv:
.LFB2059:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L26:
call cudaGetLastError@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaThreadSynchronize@PLT
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call _Z39__device_stub__Z20out_of_bounds_kernelvv
jmp .L26
.cfi_endproc
.LFE2059:
.size _Z17run_out_of_boundsv, .-_Z17run_out_of_boundsv
.section .rodata.str1.1
.LC5:
.string "Mallocing memory\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq %rsp, %rdi
movl $1024, %esi
call cudaMalloc@PLT
call _Z13run_unalignedv
call _Z17run_out_of_boundsv
call cudaDeviceReset@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z20out_of_bounds_kernelv"
.LC7:
.string "_Z16unaligned_kernelv"
.LC8:
.string "x"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z20out_of_bounds_kernelv(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z16unaligned_kernelv(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1x(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1x
.comm _ZL1x,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memcheck_demo.hip"
.globl _Z31__device_stub__unaligned_kernelv # -- Begin function _Z31__device_stub__unaligned_kernelv
.p2align 4, 0x90
.type _Z31__device_stub__unaligned_kernelv,@function
_Z31__device_stub__unaligned_kernelv: # @_Z31__device_stub__unaligned_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z16unaligned_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z31__device_stub__unaligned_kernelv, .Lfunc_end0-_Z31__device_stub__unaligned_kernelv
.cfi_endproc
# -- End function
.globl _Z35__device_stub__out_of_bounds_kernelv # -- Begin function _Z35__device_stub__out_of_bounds_kernelv
.p2align 4, 0x90
.type _Z35__device_stub__out_of_bounds_kernelv,@function
_Z35__device_stub__out_of_bounds_kernelv: # @_Z35__device_stub__out_of_bounds_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z20out_of_bounds_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z35__device_stub__out_of_bounds_kernelv, .Lfunc_end1-_Z35__device_stub__out_of_bounds_kernelv
.cfi_endproc
# -- End function
.globl _Z13run_unalignedv # -- Begin function _Z13run_unalignedv
.p2align 4, 0x90
.type _Z13run_unalignedv,@function
_Z13run_unalignedv: # @_Z13run_unalignedv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z16unaligned_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13run_unalignedv, .Lfunc_end2-_Z13run_unalignedv
.cfi_endproc
# -- End function
.globl _Z17run_out_of_boundsv # -- Begin function _Z17run_out_of_boundsv
.p2align 4, 0x90
.type _Z17run_out_of_boundsv,@function
_Z17run_out_of_boundsv: # @_Z17run_out_of_boundsv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $.Lstr.1, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z20out_of_bounds_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
callq hipGetLastError
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
callq hipDeviceSynchronize
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17run_out_of_boundsv, .Lfunc_end3-_Z17run_out_of_boundsv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr.2, %edi
callq puts@PLT
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
callq _Z13run_unalignedv
callq _Z17run_out_of_boundsv
callq hipDeviceReset
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16unaligned_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20out_of_bounds_kernelv, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $x, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type x,@object # @x
.local x
.comm x,4,4
.type _Z16unaligned_kernelv,@object # @_Z16unaligned_kernelv
.section .rodata,"a",@progbits
.globl _Z16unaligned_kernelv
.p2align 3, 0x0
_Z16unaligned_kernelv:
.quad _Z31__device_stub__unaligned_kernelv
.size _Z16unaligned_kernelv, 8
.type _Z20out_of_bounds_kernelv,@object # @_Z20out_of_bounds_kernelv
.globl _Z20out_of_bounds_kernelv
.p2align 3, 0x0
_Z20out_of_bounds_kernelv:
.quad _Z35__device_stub__out_of_bounds_kernelv
.size _Z20out_of_bounds_kernelv, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Ran unaligned_kernel: %s\n"
.size .L.str.1, 26
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Sync: %s\n"
.size .L.str.2, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Ran out_of_bounds_kernel: %s\n"
.size .L.str.4, 30
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16unaligned_kernelv"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20out_of_bounds_kernelv"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "x"
.size .L__unnamed_3, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running unaligned_kernel"
.size .Lstr, 25
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Running out_of_bounds_kernel"
.size .Lstr.1, 29
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Mallocing memory"
.size .Lstr.2, 17
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__unaligned_kernelv
.addrsig_sym _Z35__device_stub__out_of_bounds_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym x
.addrsig_sym _Z16unaligned_kernelv
.addrsig_sym _Z20out_of_bounds_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
extern "C" {
}
#define ROTATE_DOWN(val,MAX) ((val-1==-1)?MAX-1:val-1)
#define ROTATE_UP(val,MAX) ((val+1)%MAX)
/**
* GPU Device kernel for the for 2D stencil
* First attempt during hackaton
* M = Rows, N = Cols INCLUDING HALOS
* In this version now we replace the size of the shared memory to be just 3 rows (actually 1+HALO*2) rows
*/
__global__ void gpu_stencil2D_4pt_hack2(double * dst, double * src, int M, int N)
{
// printf("kernel begin!\n");
//Declaring the shared memory array for source
__shared__ double shared_mem[ 1 + HALO*2 ] [ GRID_TILE_X + HALO*2]; //1 is the row I am modifying
//double * shSrc = shared_mem;
//indexes
int i, j, curRow;
//Cols * numRows/Tile * tileIndex
int base_global_idx = ( N ) * ( GRID_TILE_Y * blockIdx.y ) + GRID_TILE_X*blockIdx.x;
int center = 1,north = 0,south = 2; //indexes for the current location in the shared memory
//copy the shared memory to fill the pipeline
for (i = 0 ; i < 1+HALO*2 ; i ++ )
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [i][j] = src[base_global_idx + i*N + j];
}
__syncthreads();
//Pipelined copy one row and process it
for ( curRow = HALO; curRow < GRID_TILE_Y; curRow+=1 )
{
//Stencil computation
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
//We are copying from dst to shared memory.
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [north][j] = src[base_global_idx + (curRow+2)*N + j];
}
center = ROTATE_UP(center,3);
south = ROTATE_UP(south,3);
north = ROTATE_UP(north,3);
__syncthreads();
}
//Dranning the pipeline
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
// printf("kernel finish!\n");
} | code for sm_80
Function : _Z23gpu_stencil2D_4pt_hack2PdS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x2b0 ; /* 0x0000027000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000ea20000002500 */
/*0060*/ ISETP.GT.AND P1, PT, R2, 0x1f5, PT ; /* 0x000001f50200780c */
/* 0x001fe20003f24270 */
/*0070*/ IMAD R3, R3, 0x32, RZ ; /* 0x0000003203037824 */
/* 0x002fc400078e02ff */
/*0080*/ IMAD R0, R0, 0x1f4, RZ ; /* 0x000001f400007824 */
/* 0x004fc800078e02ff */
/*0090*/ IMAD R3, R3, c[0x0][0x174], R0 ; /* 0x00005d0003037a24 */
/* 0x000fcc00078e0200 */
/*00a0*/ @P1 BRA 0x2a0 ; /* 0x000001f000001947 */
/* 0x000fea0003800000 */
/*00b0*/ BSSY B1, 0x160 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0002 */
/*00d0*/ IMAD.IADD R4, R3, 0x1, R0 ; /* 0x0000000103047824 */
/* 0x000fe400078e0200 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0209 */
/*0100*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0110*/ STS.64 [R0.X8], R4 ; /* 0x0000000400007388 */
/* 0x0041e40000008a00 */
/*0120*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x001fc80007ffe0ff */
/*0130*/ ISETP.GE.AND P0, PT, R0, 0x1f6, PT ; /* 0x000001f60000780c */
/* 0x000fda0003f06270 */
/*0140*/ @!P0 BRA 0xd0 ; /* 0xffffff8000008947 */
/* 0x000fea000383ffff */
/*0150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0160*/ BSSY B1, 0x210 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*0170*/ IADD3 R0, R3, c[0x0][0x174], RZ ; /* 0x00005d0003007a10 */
/* 0x000fe20007ffe0ff */
/*0180*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0002 */
/*0190*/ IMAD.IADD R4, R0, 0x1, R7 ; /* 0x0000000100047824 */
/* 0x000fc800078e0207 */
/*01a0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0209 */
/*01b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*01c0*/ STS.64 [R7.X8+0xfb0], R4 ; /* 0x000fb00407007388 */
/* 0x0041e40000008a00 */
/*01d0*/ IADD3 R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a10 */
/* 0x001fc80007ffe0ff */
/*01e0*/ ISETP.GE.AND P0, PT, R7, 0x1f6, PT ; /* 0x000001f60700780c */
/* 0x000fda0003f06270 */
/*01f0*/ @!P0 BRA 0x190 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0200*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0210*/ IADD3 R0, R0, c[0x0][0x174], RZ ; /* 0x00005d0000007a10 */
/* 0x000fe20007ffe0ff */
/*0220*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0002 */
/*0230*/ IMAD.IADD R4, R0, 0x1, R7 ; /* 0x0000000100047824 */
/* 0x000fc800078e0207 */
/*0240*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fcc00078e0209 */
/*0250*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ STS.64 [R7.X8+0x1f60], R4 ; /* 0x001f600407007388 */
/* 0x0041e40000008a00 */
/*0270*/ IADD3 R7, R7, c[0x0][0x0], RZ ; /* 0x0000000007077a10 */
/* 0x001fc80007ffe0ff */
/*0280*/ ISETP.GE.AND P0, PT, R7, 0x1f6, PT ; /* 0x000001f60700780c */
/* 0x000fda0003f06270 */
/*0290*/ @!P0 BRA 0x230 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*02a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02c0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*02d0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*02e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x2 ; /* 0x00000002ff077424 */
/* 0x000fe400078e00ff */
/*0300*/ IMAD.MOV.U32 R22, RZ, RZ, 0x1 ; /* 0x00000001ff167424 */
/* 0x000fe400078e00ff */
/*0310*/ ISETP.GT.AND P2, PT, R4, 0x1f4, PT ; /* 0x000001f40400780c */
/* 0x000fe20003f44270 */
/*0320*/ BSSY B0, 0x610 ; /* 0x000002e000007945 */
/* 0x000fd80003800000 */
/*0330*/ @P2 BRA 0x600 ; /* 0x000002c000002947 */
/* 0x000fea0003800000 */
/*0340*/ IMAD R23, R22, c[0x0][0x174], R3 ; /* 0x00005d0016177a24 */
/* 0x000fe400078e0203 */
/*0350*/ IMAD.MOV.U32 R24, RZ, RZ, R4 ; /* 0x000000ffff187224 */
/* 0x000fc800078e0004 */
/*0360*/ IMAD.SHL.U32 R0, R24, 0x8, RZ ; /* 0x0000000818007824 */
/* 0x000fe200078e00ff */
/*0370*/ MUFU.RCP64H R11, 5.5 ; /* 0x40160000000b7908 */
/* 0x001e220000001800 */
/*0380*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe200078e00ff */
/*0390*/ BSSY B1, 0x590 ; /* 0x000001f000017945 */
/* 0x000fe20003800000 */
/*03a0*/ IMAD R20, R7, 0xfb0, R0.reuse ; /* 0x00000fb007147824 */
/* 0x100fe400078e0200 */
/*03b0*/ IMAD R25, R6, 0xfb0, R0.reuse ; /* 0x00000fb006197824 */
/* 0x100fe400078e0200 */
/*03c0*/ IMAD R0, R5, 0xfb0, R0 ; /* 0x00000fb005007824 */
/* 0x000fc400078e0200 */
/*03d0*/ LDS.64 R20, [R20] ; /* 0x0000000014147984 */
/* 0x000fe20000000a00 */
/*03e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x40160000 ; /* 0x40160000ff0f7424 */
/* 0x000fe400078e00ff */
/*03f0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x1 ; /* 0x00000001ff0a7424 */
/* 0x000fe200078e00ff */
/*0400*/ LDS.64 R18, [R25] ; /* 0x0000000019127984 */
/* 0x000e680000000a00 */
/*0410*/ LDS.64 R8, [R0+-0x8] ; /* 0xfffff80000087984 */
/* 0x000ea20000000a00 */
/*0420*/ DFMA R16, R10, -R14, 1 ; /* 0x3ff000000a10742b */
/* 0x001e06000000080e */
/*0430*/ LDS.64 R12, [R0+0x8] ; /* 0x00000800000c7984 */
/* 0x000ee60000000a00 */
/*0440*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0450*/ DFMA R16, R10, R16, R10 ; /* 0x000000100a10722b */
/* 0x001e0c000000000a */
/*0460*/ DFMA R14, R16, -R14, 1 ; /* 0x3ff00000100e742b */
/* 0x001e0c000000080e */
/*0470*/ DFMA R14, R16, R14, R16 ; /* 0x0000000e100e722b */
/* 0x001fc80000000010 */
/*0480*/ DADD R18, R20, R18 ; /* 0x0000000014127229 */
/* 0x002e8c0000000012 */
/*0490*/ DADD R8, R18, R8 ; /* 0x0000000012087229 */
/* 0x004ecc0000000008 */
/*04a0*/ DADD R12, R8, R12 ; /* 0x00000000080c7229 */
/* 0x008e0c000000000c */
/*04b0*/ DMUL R8, R12, R14 ; /* 0x0000000e0c087228 */
/* 0x001e080000000000 */
/*04c0*/ FSETP.GEU.AND P3, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f6e200 */
/*04d0*/ DFMA R10, R8, -5.5, R12 ; /* 0xc0160000080a782b */
/* 0x001e0c000000000c */
/*04e0*/ DFMA R8, R14, R10, R8 ; /* 0x0000000a0e08722b */
/* 0x001e140000000008 */
/*04f0*/ FFMA R0, RZ, 2.34375, R9 ; /* 0x40160000ff007823 */
/* 0x001fca0000000009 */
/*0500*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0510*/ @P0 BRA P3, 0x580 ; /* 0x0000006000000947 */
/* 0x000fea0001800000 */
/*0520*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0530*/ MOV R11, 0x40160000 ; /* 0x40160000000b7802 */
/* 0x000fe40000000f00 */
/*0540*/ MOV R0, 0x560 ; /* 0x0000056000007802 */
/* 0x000fe40000000f00 */
/*0550*/ CALL.REL.NOINC 0xb10 ; /* 0x000005b000007944 */
/* 0x000fea0003c00000 */
/*0560*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0010 */
/*0570*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0011 */
/*0580*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0590*/ IMAD.IADD R10, R23, 0x1, R24 ; /* 0x00000001170a7824 */
/* 0x000fe200078e0218 */
/*05a0*/ IADD3 R24, R24, c[0x0][0x0], RZ ; /* 0x0000000018187a10 */
/* 0x000fe20007ffe0ff */
/*05b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc600078e00ff */
/*05c0*/ ISETP.GE.AND P0, PT, R24, 0x1f5, PT ; /* 0x000001f51800780c */
/* 0x000fe20003f06270 */
/*05d0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e020b */
/*05e0*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0001ee000c101b04 */
/*05f0*/ @!P0 BRA 0x360 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*0600*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0610*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0620*/ BSSY B0, 0x710 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0630*/ @P1 BRA 0x700 ; /* 0x000000c000001947 */
/* 0x000fea0003800000 */
/*0640*/ IADD3 R0, R22, 0x2, RZ ; /* 0x0000000216007810 */
/* 0x000fe20007ffe0ff */
/*0650*/ IMAD.MOV.U32 R11, RZ, RZ, R2 ; /* 0x000000ffff0b7224 */
/* 0x001fc800078e0002 */
/*0660*/ IMAD R0, R0, c[0x0][0x174], R3 ; /* 0x00005d0000007a24 */
/* 0x000fc800078e0203 */
/*0670*/ IMAD.IADD R8, R0, 0x1, R11 ; /* 0x0000000100087824 */
/* 0x001fe400078e020b */
/*0680*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fc800078e00ff */
/*0690*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fcc00078e0209 */
/*06a0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*06b0*/ IMAD R13, R6, 0x1f6, R11 ; /* 0x000001f6060d7824 */
/* 0x000fe200078e020b */
/*06c0*/ IADD3 R11, R11, c[0x0][0x0], RZ ; /* 0x000000000b0b7a10 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.GE.AND P0, PT, R11, 0x1f6, PT ; /* 0x000001f60b00780c */
/* 0x000fe20003f06270 */
/*06e0*/ STS.64 [R13.X8], R8 ; /* 0x000000080d007388 */
/* 0x0041d80000008a00 */
/*06f0*/ @!P0 BRA 0x670 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0700*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R22, R22, 0x1, RZ ; /* 0x0000000116167810 */
/* 0x000fe20007ffe0ff */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0730*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0740*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe40007ffe0ff */
/*0750*/ IADD3 R8, R6, 0x1, RZ ; /* 0x0000000106087810 */
/* 0x001fe20007ffe0ff */
/*0760*/ IMAD.HI R6, R7, 0x55555556, RZ ; /* 0x5555555607067827 */
/* 0x000fe200078e02ff */
/*0770*/ ISETP.GE.U32.AND P0, PT, R22, 0x32, PT ; /* 0x000000321600780c */
/* 0x000fc60003f06070 */
/*0780*/ IMAD.HI R0, R5, 0x55555556, RZ ; /* 0x5555555605007827 */
/* 0x000fe200078e02ff */
/*0790*/ LEA.HI R6, R6, R6, RZ, 0x1 ; /* 0x0000000606067211 */
/* 0x000fc600078f08ff */
/*07a0*/ IMAD.HI R9, R8, 0x55555556, RZ ; /* 0x5555555608097827 */
/* 0x000fe200078e02ff */
/*07b0*/ LEA.HI R0, R0, R0, RZ, 0x1 ; /* 0x0000000000007211 */
/* 0x000fc600078f08ff */
/*07c0*/ IMAD R7, R6, -0x3, R7 ; /* 0xfffffffd06077824 */
/* 0x000fe200078e0207 */
/*07d0*/ LEA.HI R9, R9, R9, RZ, 0x1 ; /* 0x0000000909097211 */
/* 0x000fe200078f08ff */
/*07e0*/ IMAD R5, R0, -0x3, R5 ; /* 0xfffffffd00057824 */
/* 0x000fc800078e0205 */
/*07f0*/ IMAD R6, R9, -0x3, R8 ; /* 0xfffffffd09067824 */
/* 0x000fe200078e0208 */
/*0800*/ @!P0 BRA 0x310 ; /* 0xfffffb0000008947 */
/* 0x000fea000383ffff */
/*0810*/ BSSY B0, 0xaf0 ; /* 0x000002d000007945 */
/* 0x000fe20003800000 */
/*0820*/ @P2 BRA 0xae0 ; /* 0x000002b000002947 */
/* 0x000fea0003800000 */
/*0830*/ IMAD R3, R22, c[0x0][0x174], R3 ; /* 0x00005d0016037a24 */
/* 0x000fe400078e0203 */
/*0840*/ SHF.L.U32 R0, R4, 0x3, RZ ; /* 0x0000000304007819 */
/* 0x000fe200000006ff */
/*0850*/ MUFU.RCP64H R19, 5.5 ; /* 0x4016000000137908 */
/* 0x001e220000001800 */
/*0860*/ IMAD.MOV.U32 R10, RZ, RZ, 0x0 ; /* 0x00000000ff0a7424 */
/* 0x000fe200078e00ff */
/*0870*/ BSSY B1, 0xa70 ; /* 0x000001f000017945 */
/* 0x000fe20003800000 */
/*0880*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40160000 ; /* 0x40160000ff0b7424 */
/* 0x000fe400078e00ff */
/*0890*/ IMAD R16, R6, 0xfb0, R0.reuse ; /* 0x00000fb006107824 */
/* 0x100fe400078e0200 */
/*08a0*/ IMAD R2, R7, 0xfb0, R0 ; /* 0x00000fb007027824 */
/* 0x000fc400078e0200 */
/*08b0*/ IMAD R0, R5, 0xfb0, R0 ; /* 0x00000fb005007824 */
/* 0x000fe400078e0200 */
/*08c0*/ LDS.64 R16, [R16] ; /* 0x0000000010107984 */
/* 0x000fe20000000a00 */
/*08d0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fc600078e00ff */
/*08e0*/ LDS.64 R14, [R2] ; /* 0x00000000020e7984 */
/* 0x000e660000000a00 */
/*08f0*/ DFMA R20, R18, -R10, 1 ; /* 0x3ff000001214742b */
/* 0x001e22000000080a */
/*0900*/ LDS.64 R12, [R0+-0x8] ; /* 0xfffff800000c7984 */
/* 0x000ea80000000a00 */
/*0910*/ LDS.64 R8, [R0+0x8] ; /* 0x0000080000087984 */
/* 0x000ee20000000a00 */
/*0920*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e0c0000000014 */
/*0930*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x001e0c0000000012 */
/*0940*/ DFMA R10, R20, -R10, 1 ; /* 0x3ff00000140a742b */
/* 0x001e0c000000080a */
/*0950*/ DFMA R20, R20, R10, R20 ; /* 0x0000000a1414722b */
/* 0x001fc80000000014 */
/*0960*/ DADD R14, R14, R16 ; /* 0x000000000e0e7229 */
/* 0x002e8c0000000010 */
/*0970*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x004ecc000000000c */
/*0980*/ DADD R12, R12, R8 ; /* 0x000000000c0c7229 */
/* 0x008e0c0000000008 */
/*0990*/ DMUL R8, R20, R12 ; /* 0x0000000c14087228 */
/* 0x001e080000000000 */
/*09a0*/ FSETP.GEU.AND P1, PT, |R13|, 6.5827683646048100446e-37, PT ; /* 0x036000000d00780b */
/* 0x000fe40003f2e200 */
/*09b0*/ DFMA R10, R8, -5.5, R12 ; /* 0xc0160000080a782b */
/* 0x001e0c000000000c */
/*09c0*/ DFMA R8, R20, R10, R8 ; /* 0x0000000a1408722b */
/* 0x001e140000000008 */
/*09d0*/ FFMA R0, RZ, 2.34375, R9 ; /* 0x40160000ff007823 */
/* 0x001fca0000000009 */
/*09e0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*09f0*/ @P0 BRA P1, 0xa60 ; /* 0x0000006000000947 */
/* 0x000fea0000800000 */
/*0a00*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*0a10*/ MOV R0, 0xa40 ; /* 0x00000a4000007802 */
/* 0x000fe20000000f00 */
/*0a20*/ IMAD.MOV.U32 R11, RZ, RZ, 0x40160000 ; /* 0x40160000ff0b7424 */
/* 0x000fe400078e00ff */
/*0a30*/ CALL.REL.NOINC 0xb10 ; /* 0x000000d000007944 */
/* 0x000fea0003c00000 */
/*0a40*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0010 */
/*0a50*/ IMAD.MOV.U32 R9, RZ, RZ, R17 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0011 */
/*0a60*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0a70*/ IADD3 R10, R3, R4, RZ ; /* 0x00000004030a7210 */
/* 0x000fe20007ffe0ff */
/*0a80*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fe200078e00ff */
/*0a90*/ IADD3 R4, R4, c[0x0][0x0], RZ ; /* 0x0000000004047a10 */
/* 0x000fc60007ffe0ff */
/*0aa0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e020b */
/*0ab0*/ ISETP.GE.AND P0, PT, R4, 0x1f5, PT ; /* 0x000001f50400780c */
/* 0x000fc80003f06270 */
/*0ac0*/ STG.E.64 [R10.64], R8 ; /* 0x000000080a007986 */
/* 0x0001f2000c101b04 */
/*0ad0*/ @!P0 BRA 0x840 ; /* 0xfffffd6000008947 */
/* 0x000fea000383ffff */
/*0ae0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0af0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0b00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b10*/ FSETP.GEU.AND P0, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f0e200 */
/*0b20*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0b30*/ LOP3.LUT R8, R11, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0b087812 */
/* 0x000fe200078ec0ff */
/*0b40*/ IMAD.MOV.U32 R26, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff1a7424 */
/* 0x000fe200078e00ff */
/*0b50*/ FSETP.GEU.AND P4, PT, |R13|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x040fe20003f8e200 */
/*0b60*/ BSSY B2, 0x10a0 ; /* 0x0000053000027945 */
/* 0x000fe20003800000 */
/*0b70*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*0b80*/ IMAD.MOV.U32 R8, RZ, RZ, R10 ; /* 0x000000ffff087224 */
/* 0x000fe200078e000a */
/*0b90*/ LOP3.LUT R25, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d197812 */
/* 0x000fc400078ec0ff */
/*0ba0*/ LOP3.LUT R28, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b1c7812 */
/* 0x000fc600078ec0ff */
/*0bb0*/ @!P0 DMUL R8, R10, 8.98846567431157953865e+307 ; /* 0x7fe000000a088828 */
/* 0x000e220000000000 */
/*0bc0*/ ISETP.GE.U32.AND P3, PT, R25, R28, PT ; /* 0x0000001c1900720c */
/* 0x000fc60003f66070 */
/*0bd0*/ @!P4 LOP3.LUT R14, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0ec812 */
/* 0x000fe200078ec0ff */
/*0be0*/ @!P4 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14c224 */
/* 0x000fe200078e00ff */
/*0bf0*/ MUFU.RCP64H R19, R9 ; /* 0x0000000900137308 */
/* 0x001e220000001800 */
/*0c00*/ SEL R15, R26.reuse, 0x63400000, !P3 ; /* 0x634000001a0f7807 */
/* 0x040fe40005800000 */
/*0c10*/ @!P4 ISETP.GE.U32.AND P5, PT, R25, R14, PT ; /* 0x0000000e1900c20c */
/* 0x000fe20003fa6070 */
/*0c20*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0c30*/ LOP3.LUT R15, R15, 0x800fffff, R13, 0xf8, !PT ; /* 0x800fffff0f0f7812 */
/* 0x000fe400078ef80d */
/*0c40*/ @!P4 SEL R21, R26, 0x63400000, !P5 ; /* 0x634000001a15c807 */
/* 0x000fe40006800000 */
/*0c50*/ @!P0 LOP3.LUT R28, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000091c8812 */
/* 0x000fc400078ec0ff */
/*0c60*/ @!P4 LOP3.LUT R21, R21, 0x80000000, R13, 0xf8, !PT ; /* 0x800000001515c812 */
/* 0x000fc800078ef80d */
/*0c70*/ @!P4 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515c812 */
/* 0x000fe200078efcff */
/*0c80*/ DFMA R16, R18, -R8, 1 ; /* 0x3ff000001210742b */
/* 0x001e0a0000000808 */
/*0c90*/ @!P4 DFMA R14, R14, 2, -R20 ; /* 0x400000000e0ec82b */
/* 0x000fc80000000814 */
/*0ca0*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0cb0*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e0c0000000012 */
/*0cc0*/ DFMA R18, R16, -R8, 1 ; /* 0x3ff000001012742b */
/* 0x001e0c0000000808 */
/*0cd0*/ DFMA R16, R16, R18, R16 ; /* 0x000000121010722b */
/* 0x001e0c0000000010 */
/*0ce0*/ DMUL R18, R16, R14 ; /* 0x0000000e10127228 */
/* 0x001e0c0000000000 */
/*0cf0*/ DFMA R20, R18, -R8, R14 ; /* 0x800000081214722b */
/* 0x001e0c000000000e */
/*0d00*/ DFMA R20, R16, R20, R18 ; /* 0x000000141014722b */
/* 0x0010640000000012 */
/*0d10*/ IMAD.MOV.U32 R18, RZ, RZ, R25 ; /* 0x000000ffff127224 */
/* 0x001fe200078e0019 */
/*0d20*/ @!P4 LOP3.LUT R18, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f12c812 */
/* 0x000fc800078ec0ff */
/*0d30*/ IADD3 R16, R18, -0x1, RZ ; /* 0xffffffff12107810 */
/* 0x000fc80007ffe0ff */
/*0d40*/ ISETP.GT.U32.AND P0, PT, R16, 0x7feffffe, PT ; /* 0x7feffffe1000780c */
/* 0x000fe40003f04070 */
/*0d50*/ IADD3 R16, R28, -0x1, RZ ; /* 0xffffffff1c107810 */
/* 0x000fc80007ffe0ff */
/*0d60*/ ISETP.GT.U32.OR P0, PT, R16, 0x7feffffe, P0 ; /* 0x7feffffe1000780c */
/* 0x000fda0000704470 */
/*0d70*/ @P0 BRA 0xf40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0d80*/ LOP3.LUT R16, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b107812 */
/* 0x002fc800078ec0ff */
/*0d90*/ IADD3 R12, R25.reuse, -R16.reuse, RZ ; /* 0x80000010190c7210 */
/* 0x0c0fe40007ffe0ff */
/*0da0*/ ISETP.GE.U32.AND P0, PT, R25, R16, PT ; /* 0x000000101900720c */
/* 0x000fe40003f06070 */
/*0db0*/ IMNMX R12, R12, -0x46a00000, !PT ; /* 0xb96000000c0c7817 */
/* 0x000fe40007800200 */
/*0dc0*/ SEL R13, R26, 0x63400000, !P0 ; /* 0x634000001a0d7807 */
/* 0x000fe40004000000 */
/*0dd0*/ IMNMX R12, R12, 0x46a00000, PT ; /* 0x46a000000c0c7817 */
/* 0x000fca0003800200 */
/*0de0*/ IMAD.IADD R18, R12, 0x1, -R13 ; /* 0x000000010c127824 */
/* 0x000fe400078e0a0d */
/*0df0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e00ff */
/*0e00*/ IADD3 R13, R18, 0x7fe00000, RZ ; /* 0x7fe00000120d7810 */
/* 0x000fcc0007ffe0ff */
/*0e10*/ DMUL R16, R20, R12 ; /* 0x0000000c14107228 */
/* 0x000e140000000000 */
/*0e20*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*0e30*/ @P0 BRA 0x1090 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0e40*/ DFMA R8, R20, -R8, R14 ; /* 0x800000081408722b */
/* 0x000e22000000000e */
/*0e50*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fd200078e00ff */
/*0e60*/ FSETP.NEU.AND P0, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720b */
/* 0x041fe40003f0d000 */
/*0e70*/ LOP3.LUT R11, R9, 0x80000000, R11, 0x48, !PT ; /* 0x80000000090b7812 */
/* 0x000fc800078e480b */
/*0e80*/ LOP3.LUT R13, R11, R13, RZ, 0xfc, !PT ; /* 0x0000000d0b0d7212 */
/* 0x000fce00078efcff */
/*0e90*/ @!P0 BRA 0x1090 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ IMAD.MOV R9, RZ, RZ, -R18 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a12 */
/*0eb0*/ DMUL.RP R12, R20, R12 ; /* 0x0000000c140c7228 */
/* 0x000e220000008000 */
/*0ec0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fcc00078e00ff */
/*0ed0*/ DFMA R8, R16, -R8, R20 ; /* 0x800000081008722b */
/* 0x000e460000000014 */
/*0ee0*/ LOP3.LUT R11, R13, R11, RZ, 0x3c, !PT ; /* 0x0000000b0d0b7212 */
/* 0x001fc600078e3cff */
/*0ef0*/ IADD3 R8, -R18, -0x43300000, RZ ; /* 0xbcd0000012087810 */
/* 0x002fc80007ffe1ff */
/*0f00*/ FSETP.NEU.AND P0, PT, |R9|, R8, PT ; /* 0x000000080900720b */
/* 0x000fc80003f0d200 */
/*0f10*/ FSEL R16, R12, R16, !P0 ; /* 0x000000100c107208 */
/* 0x000fe40004000000 */
/*0f20*/ FSEL R17, R11, R17, !P0 ; /* 0x000000110b117208 */
/* 0x000fe20004000000 */
/*0f30*/ BRA 0x1090 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0f40*/ DSETP.NAN.AND P0, PT, R12, R12, PT ; /* 0x0000000c0c00722a */
/* 0x002e1c0003f08000 */
/*0f50*/ @P0 BRA 0x1070 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0f60*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x000e1c0003f08000 */
/*0f70*/ @P0 BRA 0x1040 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0f80*/ ISETP.NE.AND P0, PT, R18, R28, PT ; /* 0x0000001c1200720c */
/* 0x000fe20003f05270 */
/*0f90*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*0fa0*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*0fb0*/ @!P0 BRA 0x1090 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0fc0*/ ISETP.NE.AND P0, PT, R18, 0x7ff00000, PT ; /* 0x7ff000001200780c */
/* 0x000fe40003f05270 */
/*0fd0*/ LOP3.LUT R17, R13, 0x80000000, R11, 0x48, !PT ; /* 0x800000000d117812 */
/* 0x000fe400078e480b */
/*0fe0*/ ISETP.EQ.OR P0, PT, R28, RZ, !P0 ; /* 0x000000ff1c00720c */
/* 0x000fda0004702670 */
/*0ff0*/ @P0 LOP3.LUT R8, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011080812 */
/* 0x000fe400078efcff */
/*1000*/ @!P0 MOV R16, RZ ; /* 0x000000ff00108202 */
/* 0x000fe20000000f00 */
/*1010*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*1020*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R8 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0008 */
/*1030*/ BRA 0x1090 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1040*/ LOP3.LUT R17, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b117812 */
/* 0x000fe200078efcff */
/*1050*/ IMAD.MOV.U32 R16, RZ, RZ, R10 ; /* 0x000000ffff107224 */
/* 0x000fe200078e000a */
/*1060*/ BRA 0x1090 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1070*/ LOP3.LUT R17, R13, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000d117812 */
/* 0x000fe200078efcff */
/*1080*/ IMAD.MOV.U32 R16, RZ, RZ, R12 ; /* 0x000000ffff107224 */
/* 0x000fe400078e000c */
/*1090*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*10a0*/ IMAD.MOV.U32 R8, RZ, RZ, R0 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0000 */
/*10b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*10c0*/ RET.REL.NODEC R8 0x0 ; /* 0xffffef3008007950 */
/* 0x000fea0003c3ffff */
/*10d0*/ BRA 0x10d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
extern "C" {
}
#define ROTATE_DOWN(val,MAX) ((val-1==-1)?MAX-1:val-1)
#define ROTATE_UP(val,MAX) ((val+1)%MAX)
/**
* GPU Device kernel for the for 2D stencil
* First attempt during hackaton
* M = Rows, N = Cols INCLUDING HALOS
* In this version now we replace the size of the shared memory to be just 3 rows (actually 1+HALO*2) rows
*/
__global__ void gpu_stencil2D_4pt_hack2(double * dst, double * src, int M, int N)
{
// printf("kernel begin!\n");
//Declaring the shared memory array for source
__shared__ double shared_mem[ 1 + HALO*2 ] [ GRID_TILE_X + HALO*2]; //1 is the row I am modifying
//double * shSrc = shared_mem;
//indexes
int i, j, curRow;
//Cols * numRows/Tile * tileIndex
int base_global_idx = ( N ) * ( GRID_TILE_Y * blockIdx.y ) + GRID_TILE_X*blockIdx.x;
int center = 1,north = 0,south = 2; //indexes for the current location in the shared memory
//copy the shared memory to fill the pipeline
for (i = 0 ; i < 1+HALO*2 ; i ++ )
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [i][j] = src[base_global_idx + i*N + j];
}
__syncthreads();
//Pipelined copy one row and process it
for ( curRow = HALO; curRow < GRID_TILE_Y; curRow+=1 )
{
//Stencil computation
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
//We are copying from dst to shared memory.
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [north][j] = src[base_global_idx + (curRow+2)*N + j];
}
center = ROTATE_UP(center,3);
south = ROTATE_UP(south,3);
north = ROTATE_UP(north,3);
__syncthreads();
}
//Dranning the pipeline
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
// printf("kernel finish!\n");
} | .file "tmpxft_0001b10c_00000000-6_gpu_stencil2D_4pt_hack2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii
.type _Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii, @function
_Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23gpu_stencil2D_4pt_hack2PdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii, .-_Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii
.globl _Z23gpu_stencil2D_4pt_hack2PdS_ii
.type _Z23gpu_stencil2D_4pt_hack2PdS_ii, @function
_Z23gpu_stencil2D_4pt_hack2PdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23gpu_stencil2D_4pt_hack2PdS_ii, .-_Z23gpu_stencil2D_4pt_hack2PdS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23gpu_stencil2D_4pt_hack2PdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23gpu_stencil2D_4pt_hack2PdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
extern "C" {
}
#define ROTATE_DOWN(val,MAX) ((val-1==-1)?MAX-1:val-1)
#define ROTATE_UP(val,MAX) ((val+1)%MAX)
/**
* GPU Device kernel for the for 2D stencil
* First attempt during hackaton
* M = Rows, N = Cols INCLUDING HALOS
* In this version now we replace the size of the shared memory to be just 3 rows (actually 1+HALO*2) rows
*/
__global__ void gpu_stencil2D_4pt_hack2(double * dst, double * src, int M, int N)
{
// printf("kernel begin!\n");
//Declaring the shared memory array for source
__shared__ double shared_mem[ 1 + HALO*2 ] [ GRID_TILE_X + HALO*2]; //1 is the row I am modifying
//double * shSrc = shared_mem;
//indexes
int i, j, curRow;
//Cols * numRows/Tile * tileIndex
int base_global_idx = ( N ) * ( GRID_TILE_Y * blockIdx.y ) + GRID_TILE_X*blockIdx.x;
int center = 1,north = 0,south = 2; //indexes for the current location in the shared memory
//copy the shared memory to fill the pipeline
for (i = 0 ; i < 1+HALO*2 ; i ++ )
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [i][j] = src[base_global_idx + i*N + j];
}
__syncthreads();
//Pipelined copy one row and process it
for ( curRow = HALO; curRow < GRID_TILE_Y; curRow+=1 )
{
//Stencil computation
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
//We are copying from dst to shared memory.
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [north][j] = src[base_global_idx + (curRow+2)*N + j];
}
center = ROTATE_UP(center,3);
south = ROTATE_UP(south,3);
north = ROTATE_UP(north,3);
__syncthreads();
}
//Dranning the pipeline
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
// printf("kernel finish!\n");
} | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define ROTATE_DOWN(val,MAX) ((val-1==-1)?MAX-1:val-1)
#define ROTATE_UP(val,MAX) ((val+1)%MAX)
/**
* GPU Device kernel for the for 2D stencil
* First attempt during hackaton
* M = Rows, N = Cols INCLUDING HALOS
* In this version now we replace the size of the shared memory to be just 3 rows (actually 1+HALO*2) rows
*/
__global__ void gpu_stencil2D_4pt_hack2(double * dst, double * src, int M, int N)
{
// printf("kernel begin!\n");
//Declaring the shared memory array for source
__shared__ double shared_mem[ 1 + HALO*2 ] [ GRID_TILE_X + HALO*2]; //1 is the row I am modifying
//double * shSrc = shared_mem;
//indexes
int i, j, curRow;
//Cols * numRows/Tile * tileIndex
int base_global_idx = ( N ) * ( GRID_TILE_Y * blockIdx.y ) + GRID_TILE_X*blockIdx.x;
int center = 1,north = 0,south = 2; //indexes for the current location in the shared memory
//copy the shared memory to fill the pipeline
for (i = 0 ; i < 1+HALO*2 ; i ++ )
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [i][j] = src[base_global_idx + i*N + j];
}
__syncthreads();
//Pipelined copy one row and process it
for ( curRow = HALO; curRow < GRID_TILE_Y; curRow+=1 )
{
//Stencil computation
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
//We are copying from dst to shared memory.
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [north][j] = src[base_global_idx + (curRow+2)*N + j];
}
center = ROTATE_UP(center,3);
south = ROTATE_UP(south,3);
north = ROTATE_UP(north,3);
__syncthreads();
}
//Dranning the pipeline
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
// printf("kernel finish!\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define ROTATE_DOWN(val,MAX) ((val-1==-1)?MAX-1:val-1)
#define ROTATE_UP(val,MAX) ((val+1)%MAX)
/**
* GPU Device kernel for the for 2D stencil
* First attempt during hackaton
* M = Rows, N = Cols INCLUDING HALOS
* In this version now we replace the size of the shared memory to be just 3 rows (actually 1+HALO*2) rows
*/
__global__ void gpu_stencil2D_4pt_hack2(double * dst, double * src, int M, int N)
{
// printf("kernel begin!\n");
//Declaring the shared memory array for source
__shared__ double shared_mem[ 1 + HALO*2 ] [ GRID_TILE_X + HALO*2]; //1 is the row I am modifying
//double * shSrc = shared_mem;
//indexes
int i, j, curRow;
//Cols * numRows/Tile * tileIndex
int base_global_idx = ( N ) * ( GRID_TILE_Y * blockIdx.y ) + GRID_TILE_X*blockIdx.x;
int center = 1,north = 0,south = 2; //indexes for the current location in the shared memory
//copy the shared memory to fill the pipeline
for (i = 0 ; i < 1+HALO*2 ; i ++ )
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [i][j] = src[base_global_idx + i*N + j];
}
__syncthreads();
//Pipelined copy one row and process it
for ( curRow = HALO; curRow < GRID_TILE_Y; curRow+=1 )
{
//Stencil computation
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
//We are copying from dst to shared memory.
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [north][j] = src[base_global_idx + (curRow+2)*N + j];
}
center = ROTATE_UP(center,3);
south = ROTATE_UP(south,3);
north = ROTATE_UP(north,3);
__syncthreads();
}
//Dranning the pipeline
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
// printf("kernel finish!\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23gpu_stencil2D_4pt_hack2PdS_ii
.globl _Z23gpu_stencil2D_4pt_hack2PdS_ii
.p2align 8
.type _Z23gpu_stencil2D_4pt_hack2PdS_ii,@function
_Z23gpu_stencil2D_4pt_hack2PdS_ii:
s_clause 0x1
s_load_b32 s12, s[0:1], 0x14
s_load_b64 s[6:7], s[0:1], 0x8
s_mulk_i32 s14, 0x1f4
v_cmp_gt_u32_e32 vcc_lo, 0x1f6, v0
v_lshlrev_b32_e32 v4, 3, v0
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
s_mov_b32 s8, 0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s13, s15, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s13, s13, 50
v_add3_u32 v1, s14, s13, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s10
v_add_nc_u32_e32 v1, s12, v1
v_add_nc_u32_e32 v4, 0xfb0, v4
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s9, 3
s_cbranch_scc0 .LBB0_5
.LBB0_2:
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_1
s_load_b32 s3, s[4:5], 0xc
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v5, v4
v_mov_b32_e32 v6, v0
s_mov_b32 s17, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_co_u32 v2, s2, s6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s2, s7, v3, s2
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s3, 0xffff
s_lshl_b32 s16, s11, 3
.p2align 6
.LBB0_4:
global_load_b64 v[7:8], v[2:3], off
v_add_nc_u32_e32 v6, s11, v6
v_add_co_u32 v2, s2, v2, s16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s2, s8, v3, s2
v_cmp_lt_u32_e64 s3, 0x1f5, v6
s_delay_alu instid0(VALU_DEP_1)
s_or_b32 s17, s3, s17
s_waitcnt vmcnt(0)
ds_store_b64 v5, v[7:8]
v_add_nc_u32_e32 v5, s16, v5
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_4
s_branch .LBB0_1
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[8:9], s[0:1], 0x0
s_mul_i32 s4, s15, 50
v_add_nc_u32_e32 v8, 1, v0
s_add_u32 s10, s0, 24
s_addc_u32 s11, s1, 0
s_or_b32 s15, s4, 1
s_add_i32 s4, s4, 3
s_mul_i32 s15, s12, s15
s_mul_i32 s4, s12, s4
v_cmp_gt_u32_e64 s2, 0x1f4, v0
v_cmp_gt_u32_e64 s3, 0x1f6, v0
v_add3_u32 v1, s14, s15, v8
v_lshlrev_b32_e32 v3, 3, v0
v_add3_u32 v4, s14, s4, v0
s_mov_b32 s5, 1
s_mov_b32 s15, 0
s_mov_b32 s16, 2
s_mov_b32 s18, 0
s_mov_b32 s17, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_branch .LBB0_7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s19
s_add_i32 s4, s5, 1
v_add_nc_u32_e32 v1, s12, v1
s_cmp_lg_u32 s4, 3
v_add_nc_u32_e32 v4, s12, v4
s_cselect_b32 s5, s4, 0
s_add_i32 s4, s16, 1
s_waitcnt lgkmcnt(0)
s_cmp_lg_u32 s4, 3
s_barrier
s_cselect_b32 s16, s4, 0
s_add_i32 s4, s18, 1
buffer_gl0_inv
s_cmp_lg_u32 s4, 3
s_cselect_b32 s18, s4, 0
s_add_i32 s17, s17, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s17, 50
s_cbranch_scc0 .LBB0_13
.LBB0_7:
s_and_saveexec_b32 s19, s2
s_cbranch_execz .LBB0_10
s_load_b32 s4, s[10:11], 0xc
v_ashrrev_i32_e32 v2, 31, v1
s_mul_i32 s20, s5, 0xfb0
s_mul_i32 s21, s18, 0xfb0
s_mul_i32 s23, s16, 0xfb0
v_mov_b32_e32 v7, v8
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_mov_b32_e32 v2, v3
s_mov_b32 s25, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s22, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s24, s22, 3
.LBB0_9:
v_add_nc_u32_e32 v9, s21, v2
v_add_nc_u32_e32 v11, s23, v2
v_add_nc_u32_e32 v7, s22, v7
ds_load_b64 v[9:10], v9 offset:8
ds_load_b64 v[11:12], v11 offset:8
s_waitcnt lgkmcnt(0)
v_add_f64 v[13:14], v[9:10], v[11:12]
v_add_nc_u32_e32 v9, s20, v2
v_add_nc_u32_e32 v2, s24, v2
ds_load_2addr_b64 v[9:12], v9 offset1:2
s_waitcnt lgkmcnt(0)
v_add_f64 v[9:10], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[9:10], v[9:10], v[11:12]
v_div_scale_f64 v[11:12], null, 0x40160000, 0x40160000, v[9:10]
v_div_scale_f64 v[17:18], vcc_lo, v[9:10], 0x40160000, v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[13:14], v[11:12]
s_waitcnt_depctr 0xfff
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[17:18], v[13:14]
v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
v_cmp_lt_u32_e32 vcc_lo, 0x1f4, v7
s_or_b32 s25, vcc_lo, s25
v_div_fixup_f64 v[9:10], v[11:12], 0x40160000, v[9:10]
global_store_b64 v[5:6], v[9:10], off
v_add_co_u32 v5, s4, v5, s24
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s4, s15, v6, s4
s_and_not1_b32 exec_lo, exec_lo, s25
s_cbranch_execnz .LBB0_9
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s19
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s19, s3
s_cbranch_execz .LBB0_6
s_load_b32 s4, s[10:11], 0xc
v_ashrrev_i32_e32 v5, 31, v4
v_mov_b32_e32 v2, v0
s_mov_b32 s22, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 3, v[4:5]
v_mad_u64_u32 v[5:6], null, s18, 0xfb0, v[3:4]
v_add_co_u32 v6, vcc_lo, s6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v10, vcc_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s20, s4, 0xffff
s_lshl_b32 s21, s20, 3
.LBB0_12:
global_load_b64 v[9:10], v[6:7], off
v_add_nc_u32_e32 v2, s20, v2
v_add_co_u32 v6, vcc_lo, v6, s21
v_add_co_ci_u32_e32 v7, vcc_lo, s15, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s4, 0x1f5, v2
s_or_b32 s22, s4, s22
s_waitcnt vmcnt(0)
ds_store_b64 v5, v[9:10]
v_add_nc_u32_e32 v5, s21, v5
s_and_not1_b32 exec_lo, exec_lo, s22
s_cbranch_execnz .LBB0_12
s_branch .LBB0_6
.LBB0_13:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x1f4, v0
s_cbranch_execz .LBB0_16
s_load_b32 s0, s[0:1], 0x24
v_add_nc_u32_e32 v1, 1, v0
v_lshl_add_u32 v0, v0, 3, 8
s_add_i32 s13, s13, s14
s_mul_i32 s3, s12, 50
s_mov_b32 s5, 0
s_add_i32 s3, s3, s13
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b32 s4, s1, 3
.LBB0_15:
ds_load_b64 v[2:3], v0 offset:4016
ds_load_b64 v[4:5], v0
s_movk_i32 s0, 0x1800
s_waitcnt lgkmcnt(0)
v_add_f64 v[6:7], v[2:3], v[4:5]
v_add_nc_u32_e32 v2, s0, v0
v_add_nc_u32_e32 v0, s4, v0
ds_load_2addr_b64 v[2:5], v2 offset0:235 offset1:237
s_waitcnt lgkmcnt(0)
v_add_f64 v[2:3], v[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[4:5], null, 0x40160000, 0x40160000, v[2:3]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], 0x40160000, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[10:11], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
v_div_fixup_f64 v[2:3], v[4:5], 0x40160000, v[2:3]
v_add_nc_u32_e32 v4, s3, v1
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v5, 31, v4
v_cmp_lt_u32_e32 vcc_lo, 0x1f4, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
s_or_b32 s5, vcc_lo, s5
v_add_co_u32 v4, s0, s8, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
global_store_b64 v[4:5], v[2:3], off
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_15
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23gpu_stencil2D_4pt_hack2PdS_ii
.amdhsa_group_segment_fixed_size 12048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 19
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23gpu_stencil2D_4pt_hack2PdS_ii, .Lfunc_end0-_Z23gpu_stencil2D_4pt_hack2PdS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 12048
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23gpu_stencil2D_4pt_hack2PdS_ii
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z23gpu_stencil2D_4pt_hack2PdS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 19
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}
#define ROTATE_DOWN(val,MAX) ((val-1==-1)?MAX-1:val-1)
#define ROTATE_UP(val,MAX) ((val+1)%MAX)
/**
* GPU Device kernel for the for 2D stencil
* First attempt during hackaton
* M = Rows, N = Cols INCLUDING HALOS
* In this version now we replace the size of the shared memory to be just 3 rows (actually 1+HALO*2) rows
*/
__global__ void gpu_stencil2D_4pt_hack2(double * dst, double * src, int M, int N)
{
// printf("kernel begin!\n");
//Declaring the shared memory array for source
__shared__ double shared_mem[ 1 + HALO*2 ] [ GRID_TILE_X + HALO*2]; //1 is the row I am modifying
//double * shSrc = shared_mem;
//indexes
int i, j, curRow;
//Cols * numRows/Tile * tileIndex
int base_global_idx = ( N ) * ( GRID_TILE_Y * blockIdx.y ) + GRID_TILE_X*blockIdx.x;
int center = 1,north = 0,south = 2; //indexes for the current location in the shared memory
//copy the shared memory to fill the pipeline
for (i = 0 ; i < 1+HALO*2 ; i ++ )
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [i][j] = src[base_global_idx + i*N + j];
}
__syncthreads();
//Pipelined copy one row and process it
for ( curRow = HALO; curRow < GRID_TILE_Y; curRow+=1 )
{
//Stencil computation
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
//We are copying from dst to shared memory.
for (j = threadIdx.x ; j < GRID_TILE_X+2*HALO ; j+=blockDim.x)
{
shared_mem [north][j] = src[base_global_idx + (curRow+2)*N + j];
}
center = ROTATE_UP(center,3);
south = ROTATE_UP(south,3);
north = ROTATE_UP(north,3);
__syncthreads();
}
//Dranning the pipeline
for (j = threadIdx.x + HALO ; j < GRID_TILE_X+HALO ; j+=blockDim.x)
{
//top + bottom + left + right
dst[base_global_idx + curRow*N + j] = (shared_mem[north][j] + shared_mem[south][j] + shared_mem[center][j-1] + shared_mem[center][j+1] )/5.5;
}
__syncthreads();
// printf("kernel finish!\n");
} | .text
.file "gpu_stencil2D_4pt_hack2.hip"
.globl _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii # -- Begin function _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.p2align 4, 0x90
.type _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii,@function
_Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii: # @_Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23gpu_stencil2D_4pt_hack2PdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii, .Lfunc_end0-_Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23gpu_stencil2D_4pt_hack2PdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23gpu_stencil2D_4pt_hack2PdS_ii,@object # @_Z23gpu_stencil2D_4pt_hack2PdS_ii
.section .rodata,"a",@progbits
.globl _Z23gpu_stencil2D_4pt_hack2PdS_ii
.p2align 3, 0x0
_Z23gpu_stencil2D_4pt_hack2PdS_ii:
.quad _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.size _Z23gpu_stencil2D_4pt_hack2PdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23gpu_stencil2D_4pt_hack2PdS_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23gpu_stencil2D_4pt_hack2PdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001b10c_00000000-6_gpu_stencil2D_4pt_hack2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii
.type _Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii, @function
_Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23gpu_stencil2D_4pt_hack2PdS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii, .-_Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii
.globl _Z23gpu_stencil2D_4pt_hack2PdS_ii
.type _Z23gpu_stencil2D_4pt_hack2PdS_ii, @function
_Z23gpu_stencil2D_4pt_hack2PdS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23gpu_stencil2D_4pt_hack2PdS_iiPdS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23gpu_stencil2D_4pt_hack2PdS_ii, .-_Z23gpu_stencil2D_4pt_hack2PdS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23gpu_stencil2D_4pt_hack2PdS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23gpu_stencil2D_4pt_hack2PdS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_stencil2D_4pt_hack2.hip"
.globl _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii # -- Begin function _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.p2align 4, 0x90
.type _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii,@function
_Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii: # @_Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23gpu_stencil2D_4pt_hack2PdS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii, .Lfunc_end0-_Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23gpu_stencil2D_4pt_hack2PdS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23gpu_stencil2D_4pt_hack2PdS_ii,@object # @_Z23gpu_stencil2D_4pt_hack2PdS_ii
.section .rodata,"a",@progbits
.globl _Z23gpu_stencil2D_4pt_hack2PdS_ii
.p2align 3, 0x0
_Z23gpu_stencil2D_4pt_hack2PdS_ii:
.quad _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.size _Z23gpu_stencil2D_4pt_hack2PdS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23gpu_stencil2D_4pt_hack2PdS_ii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__gpu_stencil2D_4pt_hack2PdS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23gpu_stencil2D_4pt_hack2PdS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
} | code for sm_80
Function : _Z21cudaMultVectorsKerneliPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
} | .file "tmpxft_000b3781_00000000-6_vecmult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
.type _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21cudaMultVectorsKerneliPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_, .-_Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
.globl _Z21cudaMultVectorsKerneliPfS_S_
.type _Z21cudaMultVectorsKerneliPfS_S_, @function
_Z21cudaMultVectorsKerneliPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z21cudaMultVectorsKerneliPfS_S_, .-_Z21cudaMultVectorsKerneliPfS_S_
.globl runKernel
.type runKernel, @function
runKernel:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movl $512, 20(%rsp)
movl $1, 24(%rsp)
leal 1022(%rdi), %eax
movl %edi, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
jmp .L11
.cfi_endproc
.LFE2057:
.size runKernel, .-runKernel
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21cudaMultVectorsKerneliPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21cudaMultVectorsKerneliPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21cudaMultVectorsKerneliPfS_S_
.globl _Z21cudaMultVectorsKerneliPfS_S_
.p2align 8
.type _Z21cudaMultVectorsKerneliPfS_S_,@function
_Z21cudaMultVectorsKerneliPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21cudaMultVectorsKerneliPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21cudaMultVectorsKerneliPfS_S_, .Lfunc_end0-_Z21cudaMultVectorsKerneliPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21cudaMultVectorsKerneliPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21cudaMultVectorsKerneliPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__
void cudaMultVectorsKernel(int N, float *x, float *y, float *z)
{
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < N) {
z[idx] = x[idx] * y[idx];
}
// idx = idx + blockDim.x * gridDim.x; // we will discuss this later...
}
// extern "C" is necessary because nvcc uses c++ compiler to compile cuda code
// hence applies name mangling. Because we use gcc for linking, we should
// prevent name mangling.
extern "C"
void runKernel(int N, float *x, float *y, float *z) {
cudaMultVectorsKernel<<<(N+511)/512, 512>>>(N, x, y, z);
} | .text
.file "vecmult.hip"
.globl _Z36__device_stub__cudaMultVectorsKerneliPfS_S_ # -- Begin function _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.p2align 4, 0x90
.type _Z36__device_stub__cudaMultVectorsKerneliPfS_S_,@function
_Z36__device_stub__cudaMultVectorsKerneliPfS_S_: # @_Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21cudaMultVectorsKerneliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__cudaMultVectorsKerneliPfS_S_, .Lfunc_end0-_Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.cfi_endproc
# -- End function
.globl runKernel # -- Begin function runKernel
.p2align 4, 0x90
.type runKernel,@function
runKernel: # @runKernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movl %edi, %r12d
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl %r12d, 4(%rsp)
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21cudaMultVectorsKerneliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size runKernel, .Lfunc_end1-runKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21cudaMultVectorsKerneliPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21cudaMultVectorsKerneliPfS_S_,@object # @_Z21cudaMultVectorsKerneliPfS_S_
.section .rodata,"a",@progbits
.globl _Z21cudaMultVectorsKerneliPfS_S_
.p2align 3, 0x0
_Z21cudaMultVectorsKerneliPfS_S_:
.quad _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.size _Z21cudaMultVectorsKerneliPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21cudaMultVectorsKerneliPfS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21cudaMultVectorsKerneliPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21cudaMultVectorsKerneliPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21cudaMultVectorsKerneliPfS_S_
.globl _Z21cudaMultVectorsKerneliPfS_S_
.p2align 8
.type _Z21cudaMultVectorsKerneliPfS_S_,@function
_Z21cudaMultVectorsKerneliPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21cudaMultVectorsKerneliPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21cudaMultVectorsKerneliPfS_S_, .Lfunc_end0-_Z21cudaMultVectorsKerneliPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21cudaMultVectorsKerneliPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21cudaMultVectorsKerneliPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b3781_00000000-6_vecmult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
.type _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_, @function
_Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21cudaMultVectorsKerneliPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_, .-_Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
.globl _Z21cudaMultVectorsKerneliPfS_S_
.type _Z21cudaMultVectorsKerneliPfS_S_, @function
_Z21cudaMultVectorsKerneliPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z21cudaMultVectorsKerneliPfS_S_, .-_Z21cudaMultVectorsKerneliPfS_S_
.globl runKernel
.type runKernel, @function
runKernel:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movl $512, 20(%rsp)
movl $1, 24(%rsp)
leal 1022(%rdi), %eax
movl %edi, %edx
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z46__device_stub__Z21cudaMultVectorsKerneliPfS_S_iPfS_S_
jmp .L11
.cfi_endproc
.LFE2057:
.size runKernel, .-runKernel
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21cudaMultVectorsKerneliPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21cudaMultVectorsKerneliPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vecmult.hip"
.globl _Z36__device_stub__cudaMultVectorsKerneliPfS_S_ # -- Begin function _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.p2align 4, 0x90
.type _Z36__device_stub__cudaMultVectorsKerneliPfS_S_,@function
_Z36__device_stub__cudaMultVectorsKerneliPfS_S_: # @_Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21cudaMultVectorsKerneliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__cudaMultVectorsKerneliPfS_S_, .Lfunc_end0-_Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.cfi_endproc
# -- End function
.globl runKernel # -- Begin function runKernel
.p2align 4, 0x90
.type runKernel,@function
runKernel: # @runKernel
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, %r15
movl %edi, %r12d
leal 511(%r12), %eax
leal 1022(%r12), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl %r12d, 4(%rsp)
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movq %rbx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21cudaMultVectorsKerneliPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size runKernel, .Lfunc_end1-runKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21cudaMultVectorsKerneliPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21cudaMultVectorsKerneliPfS_S_,@object # @_Z21cudaMultVectorsKerneliPfS_S_
.section .rodata,"a",@progbits
.globl _Z21cudaMultVectorsKerneliPfS_S_
.p2align 3, 0x0
_Z21cudaMultVectorsKerneliPfS_S_:
.quad _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.size _Z21cudaMultVectorsKerneliPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21cudaMultVectorsKerneliPfS_S_"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__cudaMultVectorsKerneliPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21cudaMultVectorsKerneliPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <vector>
#include <algorithm>
#define num 10000000
__global__ void gpuSquare(int *d_a, int *d_b, int N=num)
{
int tid = blockIdx.x;
if(tid < N)
d_b[tid] = d_a[tid] * d_a[tid];
}
void cpuSquare(std::vector<int> &h_a, std::vector<int> &h_b)
{
for(int i=0; i<h_a.size(); i++)
h_b[i] = h_a[i]*h_a[i];
}
int main(void)
{
// int N;
// std::cout << "N?";
// std::cin >> N;
int N=num;
std::cout << "N is " << num << "\n";
int *d_a, *d_b;//device pointer to store answer
std::cout <<"Device allocate.. ";
cudaMalloc((void**)&d_a, N*sizeof(int));
cudaMalloc((void**)&d_b, N*sizeof(int));
std::vector<int> h_a(N), h_b(N);
std::cout << "Allocated\n";
for(int i=0; i<N; i++)
{
h_a[i] = i;
}
std::cout << "Finished!!!\n";
//copy host to device
cudaMemcpy(&d_a, h_a.data(), N*sizeof(int), cudaMemcpyHostToDevice);
std::cout << "Ported to device\n";
clock_t start,end;
start = clock();
cpuSquare(h_a, h_b);
end = clock();
std:: cout << "CPU time: " << (double)(end-start)/ CLOCKS_PER_SEC << "\n";
start = clock();
gpuSquare <<<N, 1>>> (d_a, d_b);
// cudaDeviceSynchronize();
cudaThreadSynchronize();
end = clock();
std:: cout << "GPU time: " << (double)(end-start)/ CLOCKS_PER_SEC <<'\n';
// free(h_a);
// free(h_b);
// free(h_c);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z9gpuSquarePiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <vector>
#include <algorithm>
#define num 10000000
__global__ void gpuSquare(int *d_a, int *d_b, int N=num)
{
int tid = blockIdx.x;
if(tid < N)
d_b[tid] = d_a[tid] * d_a[tid];
}
void cpuSquare(std::vector<int> &h_a, std::vector<int> &h_b)
{
for(int i=0; i<h_a.size(); i++)
h_b[i] = h_a[i]*h_a[i];
}
int main(void)
{
// int N;
// std::cout << "N?";
// std::cin >> N;
int N=num;
std::cout << "N is " << num << "\n";
int *d_a, *d_b;//device pointer to store answer
std::cout <<"Device allocate.. ";
cudaMalloc((void**)&d_a, N*sizeof(int));
cudaMalloc((void**)&d_b, N*sizeof(int));
std::vector<int> h_a(N), h_b(N);
std::cout << "Allocated\n";
for(int i=0; i<N; i++)
{
h_a[i] = i;
}
std::cout << "Finished!!!\n";
//copy host to device
cudaMemcpy(&d_a, h_a.data(), N*sizeof(int), cudaMemcpyHostToDevice);
std::cout << "Ported to device\n";
clock_t start,end;
start = clock();
cpuSquare(h_a, h_b);
end = clock();
std:: cout << "CPU time: " << (double)(end-start)/ CLOCKS_PER_SEC << "\n";
start = clock();
gpuSquare <<<N, 1>>> (d_a, d_b);
// cudaDeviceSynchronize();
cudaThreadSynchronize();
end = clock();
std:: cout << "GPU time: " << (double)(end-start)/ CLOCKS_PER_SEC <<'\n';
// free(h_a);
// free(h_b);
// free(h_c);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | .file "tmpxft_0008224c_00000000-6_5_elementwise_squaring.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4290:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4290:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSquareRSt6vectorIiSaIiEES2_
.type _Z9cpuSquareRSt6vectorIiSaIiEES2_, @function
_Z9cpuSquareRSt6vectorIiSaIiEES2_:
.LFB4286:
.cfi_startproc
endbr64
movq (%rdi), %rcx
cmpq %rcx, 8(%rdi)
je .L3
movl $0, %edx
.L5:
movl (%rcx,%rdx,4), %eax
movq (%rsi), %rcx
imull %eax, %eax
movl %eax, (%rcx,%rdx,4)
movq (%rdi), %rcx
addq $1, %rdx
movq 8(%rdi), %rax
subq %rcx, %rax
sarq $2, %rax
cmpq %rax, %rdx
jb .L5
.L3:
ret
.cfi_endproc
.LFE4286:
.size _Z9cpuSquareRSt6vectorIiSaIiEES2_, .-_Z9cpuSquareRSt6vectorIiSaIiEES2_
.globl _Z31__device_stub__Z9gpuSquarePiS_iPiS_i
.type _Z31__device_stub__Z9gpuSquarePiS_iPiS_i, @function
_Z31__device_stub__Z9gpuSquarePiS_iPiS_i:
.LFB4312:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9gpuSquarePiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4312:
.size _Z31__device_stub__Z9gpuSquarePiS_iPiS_i, .-_Z31__device_stub__Z9gpuSquarePiS_iPiS_i
.globl _Z9gpuSquarePiS_i
.type _Z9gpuSquarePiS_i, @function
_Z9gpuSquarePiS_i:
.LFB4313:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9gpuSquarePiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4313:
.size _Z9gpuSquarePiS_i, .-_Z9gpuSquarePiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9gpuSquarePiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4315:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpuSquarePiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4315:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4628:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4628:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC1:
.string "N is "
.LC2:
.string "\n"
.LC3:
.string "Device allocate.. "
.LC4:
.string "Allocated\n"
.LC5:
.string "Finished!!!\n"
.LC6:
.string "Ported to device\n"
.LC7:
.string "CPU time: "
.LC9:
.string "GPU time: "
.text
.globl main
.type main, @function
main:
.LFB4287:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4287
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10000000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $40000000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 40000000(%rax), %rdx
movq %rdx, 64(%rsp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L24:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L24
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $40000000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, 80(%rsp)
leaq 40000000(%rax), %rdx
movq %rdx, 96(%rsp)
movl $0, (%rax)
addq $4, %rax
.L25:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L25
movq %rdx, 88(%rsp)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %eax
.L26:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $10000000, %rax
jne .L26
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 8(%rsp), %rdi
movl $1, %ecx
movl $40000000, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq %rax, %rbp
leaq 80(%rsp), %rsi
leaq 48(%rsp), %rdi
call _Z9cpuSquareRSt6vectorIiSaIiEES2_
call clock@PLT
movq %rax, %rbx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %rbp, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC8(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq %rax, %rbp
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $10000000, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
movl $10000000, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z9gpuSquarePiS_iPiS_i
.L27:
call cudaThreadSynchronize@PLT
call clock@PLT
movq %rax, %rbx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %rbp, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC8(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE2:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L29:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L32:
endbr64
movq %rax, %rbx
jmp .L29
.L30:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4287:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4287:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4287-.LLSDACSB4287
.LLSDACSB4287:
.uleb128 .LEHB0-.LFB4287
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4287
.uleb128 .LEHE1-.LEHB1
.uleb128 .L32-.LFB4287
.uleb128 0
.uleb128 .LEHB2-.LFB4287
.uleb128 .LEHE2-.LEHB2
.uleb128 .L33-.LFB4287
.uleb128 0
.uleb128 .LEHB3-.LFB4287
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4287:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <vector>
#include <algorithm>
#define num 10000000
__global__ void gpuSquare(int *d_a, int *d_b, int N=num)
{
int tid = blockIdx.x;
if(tid < N)
d_b[tid] = d_a[tid] * d_a[tid];
}
void cpuSquare(std::vector<int> &h_a, std::vector<int> &h_b)
{
for(int i=0; i<h_a.size(); i++)
h_b[i] = h_a[i]*h_a[i];
}
int main(void)
{
// int N;
// std::cout << "N?";
// std::cin >> N;
int N=num;
std::cout << "N is " << num << "\n";
int *d_a, *d_b;//device pointer to store answer
std::cout <<"Device allocate.. ";
cudaMalloc((void**)&d_a, N*sizeof(int));
cudaMalloc((void**)&d_b, N*sizeof(int));
std::vector<int> h_a(N), h_b(N);
std::cout << "Allocated\n";
for(int i=0; i<N; i++)
{
h_a[i] = i;
}
std::cout << "Finished!!!\n";
//copy host to device
cudaMemcpy(&d_a, h_a.data(), N*sizeof(int), cudaMemcpyHostToDevice);
std::cout << "Ported to device\n";
clock_t start,end;
start = clock();
cpuSquare(h_a, h_b);
end = clock();
std:: cout << "CPU time: " << (double)(end-start)/ CLOCKS_PER_SEC << "\n";
start = clock();
gpuSquare <<<N, 1>>> (d_a, d_b);
// cudaDeviceSynchronize();
cudaThreadSynchronize();
end = clock();
std:: cout << "GPU time: " << (double)(end-start)/ CLOCKS_PER_SEC <<'\n';
// free(h_a);
// free(h_b);
// free(h_c);
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <algorithm>
#define num 10000000
__global__ void gpuSquare(int *d_a, int *d_b, int N=num)
{
int tid = blockIdx.x;
if(tid < N)
d_b[tid] = d_a[tid] * d_a[tid];
}
void cpuSquare(std::vector<int> &h_a, std::vector<int> &h_b)
{
for(int i=0; i<h_a.size(); i++)
h_b[i] = h_a[i]*h_a[i];
}
int main(void)
{
// int N;
// std::cout << "N?";
// std::cin >> N;
int N=num;
std::cout << "N is " << num << "\n";
int *d_a, *d_b;//device pointer to store answer
std::cout <<"Device allocate.. ";
hipMalloc((void**)&d_a, N*sizeof(int));
hipMalloc((void**)&d_b, N*sizeof(int));
std::vector<int> h_a(N), h_b(N);
std::cout << "Allocated\n";
for(int i=0; i<N; i++)
{
h_a[i] = i;
}
std::cout << "Finished!!!\n";
//copy host to device
hipMemcpy(&d_a, h_a.data(), N*sizeof(int), hipMemcpyHostToDevice);
std::cout << "Ported to device\n";
clock_t start,end;
start = clock();
cpuSquare(h_a, h_b);
end = clock();
std:: cout << "CPU time: " << (double)(end-start)/ CLOCKS_PER_SEC << "\n";
start = clock();
gpuSquare <<<N, 1>>> (d_a, d_b);
// cudaDeviceSynchronize();
hipDeviceSynchronize();
end = clock();
std:: cout << "GPU time: " << (double)(end-start)/ CLOCKS_PER_SEC <<'\n';
// free(h_a);
// free(h_b);
// free(h_c);
hipFree(d_a);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <algorithm>
#define num 10000000
__global__ void gpuSquare(int *d_a, int *d_b, int N=num)
{
int tid = blockIdx.x;
if(tid < N)
d_b[tid] = d_a[tid] * d_a[tid];
}
void cpuSquare(std::vector<int> &h_a, std::vector<int> &h_b)
{
for(int i=0; i<h_a.size(); i++)
h_b[i] = h_a[i]*h_a[i];
}
int main(void)
{
// int N;
// std::cout << "N?";
// std::cin >> N;
int N=num;
std::cout << "N is " << num << "\n";
int *d_a, *d_b;//device pointer to store answer
std::cout <<"Device allocate.. ";
hipMalloc((void**)&d_a, N*sizeof(int));
hipMalloc((void**)&d_b, N*sizeof(int));
std::vector<int> h_a(N), h_b(N);
std::cout << "Allocated\n";
for(int i=0; i<N; i++)
{
h_a[i] = i;
}
std::cout << "Finished!!!\n";
//copy host to device
hipMemcpy(&d_a, h_a.data(), N*sizeof(int), hipMemcpyHostToDevice);
std::cout << "Ported to device\n";
clock_t start,end;
start = clock();
cpuSquare(h_a, h_b);
end = clock();
std:: cout << "CPU time: " << (double)(end-start)/ CLOCKS_PER_SEC << "\n";
start = clock();
gpuSquare <<<N, 1>>> (d_a, d_b);
// cudaDeviceSynchronize();
hipDeviceSynchronize();
end = clock();
std:: cout << "GPU time: " << (double)(end-start)/ CLOCKS_PER_SEC <<'\n';
// free(h_a);
// free(h_b);
// free(h_c);
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9gpuSquarePiS_i
.globl _Z9gpuSquarePiS_i
.p2align 8
.type _Z9gpuSquarePiS_i,@function
_Z9gpuSquarePiS_i:
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_load_b32 s2, s[2:3], 0x0
s_addc_u32 s1, s7, s1
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9gpuSquarePiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9gpuSquarePiS_i, .Lfunc_end0-_Z9gpuSquarePiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9gpuSquarePiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9gpuSquarePiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <vector>
#include <algorithm>
#define num 10000000
__global__ void gpuSquare(int *d_a, int *d_b, int N=num)
{
int tid = blockIdx.x;
if(tid < N)
d_b[tid] = d_a[tid] * d_a[tid];
}
void cpuSquare(std::vector<int> &h_a, std::vector<int> &h_b)
{
for(int i=0; i<h_a.size(); i++)
h_b[i] = h_a[i]*h_a[i];
}
int main(void)
{
// int N;
// std::cout << "N?";
// std::cin >> N;
int N=num;
std::cout << "N is " << num << "\n";
int *d_a, *d_b;//device pointer to store answer
std::cout <<"Device allocate.. ";
hipMalloc((void**)&d_a, N*sizeof(int));
hipMalloc((void**)&d_b, N*sizeof(int));
std::vector<int> h_a(N), h_b(N);
std::cout << "Allocated\n";
for(int i=0; i<N; i++)
{
h_a[i] = i;
}
std::cout << "Finished!!!\n";
//copy host to device
hipMemcpy(&d_a, h_a.data(), N*sizeof(int), hipMemcpyHostToDevice);
std::cout << "Ported to device\n";
clock_t start,end;
start = clock();
cpuSquare(h_a, h_b);
end = clock();
std:: cout << "CPU time: " << (double)(end-start)/ CLOCKS_PER_SEC << "\n";
start = clock();
gpuSquare <<<N, 1>>> (d_a, d_b);
// cudaDeviceSynchronize();
hipDeviceSynchronize();
end = clock();
std:: cout << "GPU time: " << (double)(end-start)/ CLOCKS_PER_SEC <<'\n';
// free(h_a);
// free(h_b);
// free(h_c);
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.file "5_elementwise_squaring.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__gpuSquarePiS_i # -- Begin function _Z24__device_stub__gpuSquarePiS_i
.p2align 4, 0x90
.type _Z24__device_stub__gpuSquarePiS_i,@function
_Z24__device_stub__gpuSquarePiS_i: # @_Z24__device_stub__gpuSquarePiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9gpuSquarePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__gpuSquarePiS_i, .Lfunc_end0-_Z24__device_stub__gpuSquarePiS_i
.cfi_endproc
# -- End function
.globl _Z9cpuSquareRSt6vectorIiSaIiEES2_ # -- Begin function _Z9cpuSquareRSt6vectorIiSaIiEES2_
.p2align 4, 0x90
.type _Z9cpuSquareRSt6vectorIiSaIiEES2_,@function
_Z9cpuSquareRSt6vectorIiSaIiEES2_: # @_Z9cpuSquareRSt6vectorIiSaIiEES2_
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
movq 8(%rdi), %rcx
subq %rax, %rcx
je .LBB1_3
# %bb.1: # %.lr.ph
sarq $2, %rcx
movq (%rsi), %rdx
cmpq $1, %rcx
adcq $0, %rcx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl (%rax,%rsi,4), %edi
imull %edi, %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq %rsi, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z9cpuSquareRSt6vectorIiSaIiEES2_, .Lfunc_end1-_Z9cpuSquareRSt6vectorIiSaIiEES2_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $10000000, %esi # imm = 0x989680
callq _ZNSolsEi
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl $40000000, %edi # imm = 0x2625A00
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $40000000, %edx # imm = 0x2625A00
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.1: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB2_2
# %bb.3:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp3:
# %bb.4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit27
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp5:
# %bb.5:
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit28
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r14
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r15
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit29
subq %r14, %r15
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
.Ltmp11:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp12:
# %bb.8: # %_ZNSolsEd.exit
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp14:
# %bb.9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit30
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r14
.Ltmp15:
.cfi_escape 0x2e, 0x00
movabsq $4304967296, %rdi # imm = 0x100989680
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp16:
# %bb.10:
testl %eax, %eax
jne .LBB2_13
# %bb.11:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $10000000, 20(%rsp) # imm = 0x989680
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
.Ltmp17:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp18:
# %bb.12: # %.noexc
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp19:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z9gpuSquarePiS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp20:
.LBB2_13:
.Ltmp21:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp22:
# %bb.14:
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r15
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp24:
# %bb.15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit33
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
.Ltmp25:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp26:
# %bb.16: # %_ZNSolsEd.exit35
movb $10, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_18
# %bb.17:
.Ltmp27:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
jmp .LBB2_19
.LBB2_18:
.Ltmp29:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp30:
.LBB2_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 8(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp32:
# %bb.20:
movq 24(%rsp), %rdi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp34:
# %bb.21: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_22:
.cfi_def_cfa_offset 160
.Ltmp8:
jmp .LBB2_23
.LBB2_24:
.Ltmp35:
.LBB2_23: # %_ZNSt6vectorIiSaIiEED2Ev.exit44
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp7-.Ltmp0 # Call between .Ltmp0 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp34-.Ltmp9 # Call between .Ltmp9 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end2-.Ltmp34 # Call between .Ltmp34 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpuSquarePiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpuSquarePiS_i,@object # @_Z9gpuSquarePiS_i
.section .rodata,"a",@progbits
.globl _Z9gpuSquarePiS_i
.p2align 3, 0x0
_Z9gpuSquarePiS_i:
.quad _Z24__device_stub__gpuSquarePiS_i
.size _Z9gpuSquarePiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "N is "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device allocate.. "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocated\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Finished!!!\n"
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Ported to device\n"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU time: "
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU time: "
.size .L.str.7, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9gpuSquarePiS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpuSquarePiS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9gpuSquarePiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9gpuSquarePiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD R7, R2, R2, RZ ; /* 0x0000000202077224 */
/* 0x004fca00078e02ff */
/*00a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9gpuSquarePiS_i
.globl _Z9gpuSquarePiS_i
.p2align 8
.type _Z9gpuSquarePiS_i,@function
_Z9gpuSquarePiS_i:
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s3
s_cbranch_scc1 .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
s_ashr_i32 s3, s15, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_load_b32 s2, s[2:3], 0x0
s_addc_u32 s1, s7, s1
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s2
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9gpuSquarePiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9gpuSquarePiS_i, .Lfunc_end0-_Z9gpuSquarePiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9gpuSquarePiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z9gpuSquarePiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008224c_00000000-6_5_elementwise_squaring.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4290:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4290:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSquareRSt6vectorIiSaIiEES2_
.type _Z9cpuSquareRSt6vectorIiSaIiEES2_, @function
_Z9cpuSquareRSt6vectorIiSaIiEES2_:
.LFB4286:
.cfi_startproc
endbr64
movq (%rdi), %rcx
cmpq %rcx, 8(%rdi)
je .L3
movl $0, %edx
.L5:
movl (%rcx,%rdx,4), %eax
movq (%rsi), %rcx
imull %eax, %eax
movl %eax, (%rcx,%rdx,4)
movq (%rdi), %rcx
addq $1, %rdx
movq 8(%rdi), %rax
subq %rcx, %rax
sarq $2, %rax
cmpq %rax, %rdx
jb .L5
.L3:
ret
.cfi_endproc
.LFE4286:
.size _Z9cpuSquareRSt6vectorIiSaIiEES2_, .-_Z9cpuSquareRSt6vectorIiSaIiEES2_
.globl _Z31__device_stub__Z9gpuSquarePiS_iPiS_i
.type _Z31__device_stub__Z9gpuSquarePiS_iPiS_i, @function
_Z31__device_stub__Z9gpuSquarePiS_iPiS_i:
.LFB4312:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9gpuSquarePiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4312:
.size _Z31__device_stub__Z9gpuSquarePiS_iPiS_i, .-_Z31__device_stub__Z9gpuSquarePiS_iPiS_i
.globl _Z9gpuSquarePiS_i
.type _Z9gpuSquarePiS_i, @function
_Z9gpuSquarePiS_i:
.LFB4313:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9gpuSquarePiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4313:
.size _Z9gpuSquarePiS_i, .-_Z9gpuSquarePiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9gpuSquarePiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4315:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpuSquarePiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4315:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIiSaIiEED2Ev,"axG",@progbits,_ZNSt6vectorIiSaIiEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIiSaIiEED2Ev
.type _ZNSt6vectorIiSaIiEED2Ev, @function
_ZNSt6vectorIiSaIiEED2Ev:
.LFB4628:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L20
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L20:
ret
.cfi_endproc
.LFE4628:
.size _ZNSt6vectorIiSaIiEED2Ev, .-_ZNSt6vectorIiSaIiEED2Ev
.weak _ZNSt6vectorIiSaIiEED1Ev
.set _ZNSt6vectorIiSaIiEED1Ev,_ZNSt6vectorIiSaIiEED2Ev
.section .rodata.str1.1
.LC1:
.string "N is "
.LC2:
.string "\n"
.LC3:
.string "Device allocate.. "
.LC4:
.string "Allocated\n"
.LC5:
.string "Finished!!!\n"
.LC6:
.string "Ported to device\n"
.LC7:
.string "CPU time: "
.LC9:
.string "GPU time: "
.text
.globl main
.type main, @function
main:
.LFB4287:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4287
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $120, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
.LEHB0:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10000000, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC3(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 8(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40000000, %esi
call cudaMalloc@PLT
movl $40000000, %edi
call _Znwm@PLT
.LEHE0:
movq %rax, %rbx
movq %rax, 48(%rsp)
leaq 40000000(%rax), %rdx
movq %rdx, 64(%rsp)
movl $0, (%rax)
leaq 4(%rax), %rax
.L24:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L24
movq %rdx, 56(%rsp)
movq $0, 88(%rsp)
movq $0, 96(%rsp)
movl $40000000, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, 80(%rsp)
leaq 40000000(%rax), %rdx
movq %rdx, 96(%rsp)
movl $0, (%rax)
addq $4, %rax
.L25:
movl $0, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L25
movq %rdx, 88(%rsp)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB2:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $0, %eax
.L26:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $10000000, %rax
jne .L26
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 8(%rsp), %rdi
movl $1, %ecx
movl $40000000, %edx
movq %rbx, %rsi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq %rax, %rbp
leaq 80(%rsp), %rsi
leaq 48(%rsp), %rdi
call _Z9cpuSquareRSt6vectorIiSaIiEES2_
call clock@PLT
movq %rax, %rbx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %rbp, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC8(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call clock@PLT
movq %rax, %rbp
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $10000000, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L27
movl $10000000, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z9gpuSquarePiS_iPiS_i
.L27:
call cudaThreadSynchronize@PLT
call clock@PLT
movq %rax, %rbx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
subq %rbp, %rbx
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
divsd .LC8(%rip), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
.LEHE2:
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq 80(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
.L29:
leaq 48(%rsp), %rdi
call _ZNSt6vectorIiSaIiEED1Ev
movq 104(%rsp), %rax
subq %fs:40, %rax
je .L30
call __stack_chk_fail@PLT
.L32:
endbr64
movq %rax, %rbx
jmp .L29
.L30:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4287:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4287:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4287-.LLSDACSB4287
.LLSDACSB4287:
.uleb128 .LEHB0-.LFB4287
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4287
.uleb128 .LEHE1-.LEHB1
.uleb128 .L32-.LFB4287
.uleb128 0
.uleb128 .LEHB2-.LFB4287
.uleb128 .LEHE2-.LEHB2
.uleb128 .L33-.LFB4287
.uleb128 0
.uleb128 .LEHB3-.LFB4287
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4287:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC8:
.long 0
.long 1093567616
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "5_elementwise_squaring.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__gpuSquarePiS_i # -- Begin function _Z24__device_stub__gpuSquarePiS_i
.p2align 4, 0x90
.type _Z24__device_stub__gpuSquarePiS_i,@function
_Z24__device_stub__gpuSquarePiS_i: # @_Z24__device_stub__gpuSquarePiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9gpuSquarePiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__gpuSquarePiS_i, .Lfunc_end0-_Z24__device_stub__gpuSquarePiS_i
.cfi_endproc
# -- End function
.globl _Z9cpuSquareRSt6vectorIiSaIiEES2_ # -- Begin function _Z9cpuSquareRSt6vectorIiSaIiEES2_
.p2align 4, 0x90
.type _Z9cpuSquareRSt6vectorIiSaIiEES2_,@function
_Z9cpuSquareRSt6vectorIiSaIiEES2_: # @_Z9cpuSquareRSt6vectorIiSaIiEES2_
.cfi_startproc
# %bb.0:
movq (%rdi), %rax
movq 8(%rdi), %rcx
subq %rax, %rcx
je .LBB1_3
# %bb.1: # %.lr.ph
sarq $2, %rcx
movq (%rsi), %rdx
cmpq $1, %rcx
adcq $0, %rcx
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movl (%rax,%rsi,4), %edi
imull %edi, %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpq %rsi, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z9cpuSquareRSt6vectorIiSaIiEES2_, .Lfunc_end1-_Z9cpuSquareRSt6vectorIiSaIiEES2_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $10000000, %esi # imm = 0x989680
callq _ZNSolsEi
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $18, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movl $40000000, %esi # imm = 0x2625A00
callq hipMalloc
.cfi_escape 0x2e, 0x00
movl $40000000, %edi # imm = 0x2625A00
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
movl $40000000, %edx # imm = 0x2625A00
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp1:
# %bb.1: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_2: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $10000000, %rax # imm = 0x989680
jne .LBB2_2
# %bb.3:
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp3:
# %bb.4: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit27
.Ltmp4:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $40000000, %edx # imm = 0x2625A00
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp5:
# %bb.5:
.Ltmp6:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp7:
# %bb.6: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit28
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r14
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r15
.Ltmp9:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp10:
# %bb.7: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit29
subq %r14, %r15
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
.Ltmp11:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp12:
# %bb.8: # %_ZNSolsEd.exit
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $.L.str.1, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp14:
# %bb.9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit30
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r14
.Ltmp15:
.cfi_escape 0x2e, 0x00
movabsq $4304967296, %rdi # imm = 0x100989680
movabsq $4294967297, %rdx # imm = 0x100000001
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp16:
# %bb.10:
testl %eax, %eax
jne .LBB2_13
# %bb.11:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $10000000, 20(%rsp) # imm = 0x989680
leaq 120(%rsp), %rax
movq %rax, 32(%rsp)
leaq 112(%rsp), %rax
movq %rax, 40(%rsp)
leaq 20(%rsp), %rax
movq %rax, 48(%rsp)
.Ltmp17:
.cfi_escape 0x2e, 0x00
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp18:
# %bb.12: # %.noexc
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
.Ltmp19:
.cfi_escape 0x2e, 0x10
leaq 32(%rsp), %r9
movl $_Z9gpuSquarePiS_i, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp20:
.LBB2_13:
.Ltmp21:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp22:
# %bb.14:
.cfi_escape 0x2e, 0x00
callq clock
movq %rax, %r15
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp24:
# %bb.15: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit33
subq %r14, %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
divsd .LCPI2_0(%rip), %xmm0
.Ltmp25:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp26:
# %bb.16: # %_ZNSolsEd.exit35
movb $10, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB2_18
# %bb.17:
.Ltmp27:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp28:
jmp .LBB2_19
.LBB2_18:
.Ltmp29:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.Ltmp30:
.LBB2_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq 8(%rsp), %rdi
.Ltmp31:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp32:
# %bb.20:
movq 24(%rsp), %rdi
.Ltmp33:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp34:
# %bb.21: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_22:
.cfi_def_cfa_offset 160
.Ltmp8:
jmp .LBB2_23
.LBB2_24:
.Ltmp35:
.LBB2_23: # %_ZNSt6vectorIiSaIiEED2Ev.exit44
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table2:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp7-.Ltmp0 # Call between .Ltmp0 and .Ltmp7
.uleb128 .Ltmp8-.Lfunc_begin0 # jumps to .Ltmp8
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp34-.Ltmp9 # Call between .Ltmp9 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp34-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Lfunc_end2-.Ltmp34 # Call between .Ltmp34 and .Lfunc_end2
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpuSquarePiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpuSquarePiS_i,@object # @_Z9gpuSquarePiS_i
.section .rodata,"a",@progbits
.globl _Z9gpuSquarePiS_i
.p2align 3, 0x0
_Z9gpuSquarePiS_i:
.quad _Z24__device_stub__gpuSquarePiS_i
.size _Z9gpuSquarePiS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "N is "
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\n"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device allocate.. "
.size .L.str.2, 19
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Allocated\n"
.size .L.str.3, 11
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Finished!!!\n"
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Ported to device\n"
.size .L.str.5, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU time: "
.size .L.str.6, 11
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU time: "
.size .L.str.7, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9gpuSquarePiS_i"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpuSquarePiS_i
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9gpuSquarePiS_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_looping(float *point, unsigned int num) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
for (int iloop = 0; iloop < NLOOPS; ++iloop) {
for (size_t offset = idx; offset < num; offset += gridDim.x * blockDim.x) {
point[offset] += 1;
}
}
} | code for sm_80
Function : _Z14kernel_loopingPfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x430 ; /* 0x000003f000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*00b0*/ @P0 BRA 0x420 ; /* 0x0000036000000947 */
/* 0x000fea0003800000 */
/*00c0*/ BSSY B1, 0x1a0 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*00f0*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0100*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0110*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0130*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0150*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0160*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0180*/ @!P0 BRA 0xf0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01a0*/ BSSY B1, 0x280 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*01d0*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*01e0*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*01f0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0210*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0230*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0240*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0250*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0260*/ @!P0 BRA 0x1d0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0270*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0280*/ BSSY B1, 0x360 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*02a0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*02b0*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*02c0*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*02d0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*02f0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0310*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0320*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0330*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0340*/ @!P0 BRA 0x2b0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0350*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0360*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0370*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0380*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0390*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*03a0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*03c0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*03e0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*03f0*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0410*/ @!P0 BRA 0x380 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f26070 */
/*0440*/ BSSY B0, 0x7d0 ; /* 0x0000038000007945 */
/* 0x000fd80003800000 */
/*0450*/ @P1 BRA 0x7c0 ; /* 0x0000036000001947 */
/* 0x000fea0003800000 */
/*0460*/ BSSY B1, 0x540 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0480*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0490*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*04a0*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*04b0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*04d0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*04f0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0500*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0510*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0520*/ @!P0 BRA 0x490 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0530*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0540*/ BSSY B1, 0x620 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0550*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0560*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0570*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0580*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0590*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*05b0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*05d0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*05e0*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*05f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0600*/ @!P0 BRA 0x570 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0610*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0620*/ BSSY B1, 0x700 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0630*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0640*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0650*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0660*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0670*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0690*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*06b0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*06c0*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*06d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*06e0*/ @!P0 BRA 0x650 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0710*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0720*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0730*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0740*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0760*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0770*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0780*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0790*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*07a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*07b0*/ @!P0 BRA 0x720 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*07c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07d0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*07e0*/ BSSY B0, 0x8c0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*07f0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0800*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0810*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0820*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0830*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0840*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0850*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0860*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0870*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0880*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0890*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*08a0*/ @!P0 BRA 0x810 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*08b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08c0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x001fc800078010ff */
/*08d0*/ LEA.HI.X R5, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1403 */
/*08e0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IADD3 R0, P0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fca000ff1e0ff */
/*0900*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*0910*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0920*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe20003f06100 */
/*0930*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0940*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0950*/ @!P0 BRA 0x8c0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0960*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0970*/ BRA 0x970; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_looping(float *point, unsigned int num) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
for (int iloop = 0; iloop < NLOOPS; ++iloop) {
for (size_t offset = idx; offset < num; offset += gridDim.x * blockDim.x) {
point[offset] += 1;
}
}
} | .file "tmpxft_00115d0f_00000000-6_kernel_looping.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14kernel_loopingPfjPfj
.type _Z35__device_stub__Z14kernel_loopingPfjPfj, @function
_Z35__device_stub__Z14kernel_loopingPfjPfj:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14kernel_loopingPfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z14kernel_loopingPfjPfj, .-_Z35__device_stub__Z14kernel_loopingPfjPfj
.globl _Z14kernel_loopingPfj
.type _Z14kernel_loopingPfj, @function
_Z14kernel_loopingPfj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14kernel_loopingPfjPfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14kernel_loopingPfj, .-_Z14kernel_loopingPfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14kernel_loopingPfj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_loopingPfj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_looping(float *point, unsigned int num) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
for (int iloop = 0; iloop < NLOOPS; ++iloop) {
for (size_t offset = idx; offset < num; offset += gridDim.x * blockDim.x) {
point[offset] += 1;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_looping(float *point, unsigned int num) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
for (int iloop = 0; iloop < NLOOPS; ++iloop) {
for (size_t offset = idx; offset < num; offset += gridDim.x * blockDim.x) {
point[offset] += 1;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_looping(float *point, unsigned int num) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
for (int iloop = 0; iloop < NLOOPS; ++iloop) {
for (size_t offset = idx; offset < num; offset += gridDim.x * blockDim.x) {
point[offset] += 1;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14kernel_loopingPfj
.globl _Z14kernel_loopingPfj
.p2align 8
.type _Z14kernel_loopingPfj,@function
_Z14kernel_loopingPfj:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s3, 0xffff
s_mov_b32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s5, s3
s_mul_i32 s4, s4, s6
s_mov_b32 s8, s3
s_lshl_b64 s[6:7], s[4:5], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_cmp_gt_u32_e32 vcc_lo, s2, v1
v_add_co_u32 v3, s0, s0, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s1, v4, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 10
s_cbranch_scc1 .LBB0_5
.LBB0_2:
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_1
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v7, v1
s_mov_b32 s10, 0
.p2align 6
.LBB0_4:
global_load_b32 v0, v[5:6], off
v_add_co_u32 v7, s0, v7, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
v_cmp_le_u64_e64 s0, s[2:3], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_or_b32 s10, s0, s10
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, 1.0, v0
global_store_b32 v[5:6], v0, off
v_add_co_u32 v5, s1, v5, s6
v_add_co_ci_u32_e64 v6, s1, s7, v6, s1
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_4
s_branch .LBB0_1
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernel_loopingPfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14kernel_loopingPfj, .Lfunc_end0-_Z14kernel_loopingPfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernel_loopingPfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14kernel_loopingPfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_looping(float *point, unsigned int num) {
unsigned int idx = threadIdx.x + blockIdx.x * blockDim.x;
for (int iloop = 0; iloop < NLOOPS; ++iloop) {
for (size_t offset = idx; offset < num; offset += gridDim.x * blockDim.x) {
point[offset] += 1;
}
}
} | .text
.file "kernel_looping.hip"
.globl _Z29__device_stub__kernel_loopingPfj # -- Begin function _Z29__device_stub__kernel_loopingPfj
.p2align 4, 0x90
.type _Z29__device_stub__kernel_loopingPfj,@function
_Z29__device_stub__kernel_loopingPfj: # @_Z29__device_stub__kernel_loopingPfj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14kernel_loopingPfj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__kernel_loopingPfj, .Lfunc_end0-_Z29__device_stub__kernel_loopingPfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_loopingPfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14kernel_loopingPfj,@object # @_Z14kernel_loopingPfj
.section .rodata,"a",@progbits
.globl _Z14kernel_loopingPfj
.p2align 3, 0x0
_Z14kernel_loopingPfj:
.quad _Z29__device_stub__kernel_loopingPfj
.size _Z14kernel_loopingPfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14kernel_loopingPfj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__kernel_loopingPfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14kernel_loopingPfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14kernel_loopingPfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x430 ; /* 0x000003f000007945 */
/* 0x000fe20003800000 */
/*0040*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0090*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*00b0*/ @P0 BRA 0x420 ; /* 0x0000036000000947 */
/* 0x000fea0003800000 */
/*00c0*/ BSSY B1, 0x1a0 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*00d0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*00e0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*00f0*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0100*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0110*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0130*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0150*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0160*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0170*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0180*/ @!P0 BRA 0xf0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0190*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*01a0*/ BSSY B1, 0x280 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*01b0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*01d0*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*01e0*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*01f0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0210*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0220*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0230*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0240*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0250*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0260*/ @!P0 BRA 0x1d0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0270*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0280*/ BSSY B1, 0x360 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*02a0*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*02b0*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*02c0*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*02d0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*02e0*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*02f0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0300*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0310*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0320*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0330*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0340*/ @!P0 BRA 0x2b0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0350*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0360*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0370*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0380*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0390*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*03a0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*03c0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*03d0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*03e0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*03f0*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0400*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0410*/ @!P0 BRA 0x380 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.GE.U32.AND P1, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f26070 */
/*0440*/ BSSY B0, 0x7d0 ; /* 0x0000038000007945 */
/* 0x000fd80003800000 */
/*0450*/ @P1 BRA 0x7c0 ; /* 0x0000036000001947 */
/* 0x000fea0003800000 */
/*0460*/ BSSY B1, 0x540 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0470*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0480*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0490*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*04a0*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*04b0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*04c0*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*04d0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*04e0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*04f0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0500*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0510*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0520*/ @!P0 BRA 0x490 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0530*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0540*/ BSSY B1, 0x620 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0550*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0560*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0570*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0580*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0590*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*05b0*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*05d0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*05e0*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*05f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0600*/ @!P0 BRA 0x570 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0610*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0620*/ BSSY B1, 0x700 ; /* 0x000000d000017945 */
/* 0x000fe20003800000 */
/*0630*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0640*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0650*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0660*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0670*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0690*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*06b0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*06c0*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*06d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*06e0*/ @!P0 BRA 0x650 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0700*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0710*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0720*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0730*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0740*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0750*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0760*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0770*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0780*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0790*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*07a0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*07b0*/ @!P0 BRA 0x720 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*07c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07d0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*07e0*/ BSSY B0, 0x8c0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*07f0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0000 */
/*0800*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc600078e0003 */
/*0810*/ LEA R4, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006047a11 */
/* 0x001fc800078010ff */
/*0820*/ LEA.HI.X R5, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f1409 */
/*0830*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*0840*/ IADD3 R6, P0, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fca000ff1e0ff */
/*0850*/ IMAD.X R9, RZ, RZ, R9, P0 ; /* 0x000000ffff097224 */
/* 0x000fe200000e0609 */
/*0860*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fc80003f06070 */
/*0870*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0880*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0890*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*08a0*/ @!P0 BRA 0x810 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*08b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08c0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x001fc800078010ff */
/*08d0*/ LEA.HI.X R5, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f1403 */
/*08e0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e1900 */
/*08f0*/ IADD3 R0, P0, R0, UR4, RZ ; /* 0x0000000400007c10 */
/* 0x000fca000ff1e0ff */
/*0900*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*0910*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0920*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe20003f06100 */
/*0930*/ FADD R7, R2, 1 ; /* 0x3f80000002077421 */
/* 0x004fca0000000000 */
/*0940*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001ee000c101906 */
/*0950*/ @!P0 BRA 0x8c0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0960*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0970*/ BRA 0x970; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14kernel_loopingPfj
.globl _Z14kernel_loopingPfj
.p2align 8
.type _Z14kernel_loopingPfj,@function
_Z14kernel_loopingPfj:
s_clause 0x3
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x10
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s3, 0xffff
s_mov_b32 s3, 0
v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s5, s3
s_mul_i32 s4, s4, s6
s_mov_b32 s8, s3
s_lshl_b64 s[6:7], s[4:5], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_cmp_gt_u32_e32 vcc_lo, s2, v1
v_add_co_u32 v3, s0, s0, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s0, s1, v4, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s9
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 10
s_cbranch_scc1 .LBB0_5
.LBB0_2:
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB0_1
v_dual_mov_b32 v6, v4 :: v_dual_mov_b32 v5, v3
v_dual_mov_b32 v8, v2 :: v_dual_mov_b32 v7, v1
s_mov_b32 s10, 0
.p2align 6
.LBB0_4:
global_load_b32 v0, v[5:6], off
v_add_co_u32 v7, s0, v7, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s0, s5, v8, s0
v_cmp_le_u64_e64 s0, s[2:3], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_or_b32 s10, s0, s10
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, 1.0, v0
global_store_b32 v[5:6], v0, off
v_add_co_u32 v5, s1, v5, s6
v_add_co_ci_u32_e64 v6, s1, s7, v6, s1
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execnz .LBB0_4
s_branch .LBB0_1
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14kernel_loopingPfj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14kernel_loopingPfj, .Lfunc_end0-_Z14kernel_loopingPfj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14kernel_loopingPfj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14kernel_loopingPfj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00115d0f_00000000-6_kernel_looping.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z14kernel_loopingPfjPfj
.type _Z35__device_stub__Z14kernel_loopingPfjPfj, @function
_Z35__device_stub__Z14kernel_loopingPfjPfj:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14kernel_loopingPfj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z14kernel_loopingPfjPfj, .-_Z35__device_stub__Z14kernel_loopingPfjPfj
.globl _Z14kernel_loopingPfj
.type _Z14kernel_loopingPfj, @function
_Z14kernel_loopingPfj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z14kernel_loopingPfjPfj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14kernel_loopingPfj, .-_Z14kernel_loopingPfj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14kernel_loopingPfj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14kernel_loopingPfj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_looping.hip"
.globl _Z29__device_stub__kernel_loopingPfj # -- Begin function _Z29__device_stub__kernel_loopingPfj
.p2align 4, 0x90
.type _Z29__device_stub__kernel_loopingPfj,@function
_Z29__device_stub__kernel_loopingPfj: # @_Z29__device_stub__kernel_loopingPfj
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14kernel_loopingPfj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__kernel_loopingPfj, .Lfunc_end0-_Z29__device_stub__kernel_loopingPfj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14kernel_loopingPfj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14kernel_loopingPfj,@object # @_Z14kernel_loopingPfj
.section .rodata,"a",@progbits
.globl _Z14kernel_loopingPfj
.p2align 3, 0x0
_Z14kernel_loopingPfj:
.quad _Z29__device_stub__kernel_loopingPfj
.size _Z14kernel_loopingPfj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14kernel_loopingPfj"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__kernel_loopingPfj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14kernel_loopingPfj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void max_pool3d_backward(int B, int N, int M, int C, const int* maxIndex, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M*C;j+=blockDim.x)
{
int c = j%C;
int n = maxIndex[i*M*C+j];
atomicAdd(&gradInput[i*N*C+n*C+c],gradOutput[i*M*C+j]);
}
}
} | code for sm_80
Function : _Z19max_pool3d_backwardiiiiPKiPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0080*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf06270 */
/*0090*/ BSSY B0, 0x330 ; /* 0x0000029000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x320 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IABS R3, c[0x0][0x16c] ; /* 0x00005b0000037a13 */
/* 0x000fe40000000000 */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f05270 */
/*00d0*/ I2F.RP R8, R3 ; /* 0x0000000300087306 */
/* 0x000e220000209400 */
/*00e0*/ LOP3.LUT R13, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff0d7a12 */
/* 0x000fce00078e33ff */
/*00f0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV R4, RZ, RZ, -R7 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a07 */
/*0140*/ IMAD R5, R4, R3, RZ ; /* 0x0000000304057224 */
/* 0x000fe400078e02ff */
/*0150*/ IMAD R4, R2, UR4, RZ ; /* 0x0000000402047c24 */
/* 0x000fe4000f8e02ff */
/*0160*/ IMAD.HI.U32 R10, R7, R5, R6 ; /* 0x00000005070a7227 */
/* 0x000fe200078e0006 */
/*0170*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fca0000000f00 */
/*0180*/ IMAD.IADD R8, R4, 0x1, R5 ; /* 0x0000000104087824 */
/* 0x000fe400078e0205 */
/*0190*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R6, R8, R15, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x001fcc00078e020f */
/*01b0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.WIDE R8, R8, R15, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fcc00078e020f */
/*01d0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee2000c1e1900 */
/*01e0*/ IABS R17, R5 ; /* 0x0000000500117213 */
/* 0x000fe20000000000 */
/*01f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0200*/ IABS R19, c[0x0][0x16c] ; /* 0x00005b0000137a13 */
/* 0x000fe40000000000 */
/*0210*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f46270 */
/*0220*/ IMAD.HI.U32 R11, R10, R17, RZ ; /* 0x000000110a0b7227 */
/* 0x000fca00078e00ff */
/*0230*/ IADD3 R12, -R11, RZ, RZ ; /* 0x000000ff0b0c7210 */
/* 0x000fca0007ffe1ff */
/*0240*/ IMAD R12, R19, R12, R17 ; /* 0x0000000c130c7224 */
/* 0x000fca00078e0211 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IMAD.IADD R12, R12, 0x1, -R19 ; /* 0x000000010c0c9824 */
/* 0x000fca00078e0a13 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe40003f24070 */
/*0280*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x000fd60007ffe0ff */
/*0290*/ @!P1 IMAD.IADD R12, R12, 0x1, -R19 ; /* 0x000000010c0c9824 */
/* 0x000fca00078e0a13 */
/*02a0*/ @!P2 IADD3 R12, -R12, RZ, RZ ; /* 0x000000ff0c0ca210 */
/* 0x000fe40007ffe1ff */
/*02b0*/ ISETP.GE.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe4000bf26270 */
/*02c0*/ SEL R12, R13, R12, !P0 ; /* 0x0000000c0d0c7207 */
/* 0x000fe20004000000 */
/*02d0*/ IMAD R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a24 */
/* 0x004fc800078e0207 */
/*02e0*/ IMAD R6, R7, c[0x0][0x16c], R12 ; /* 0x00005b0007067a24 */
/* 0x000fc800078e020c */
/*02f0*/ IMAD.WIDE R6, R6, R15, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fca00078e020f */
/*0300*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0081e2000c10e786 */
/*0310*/ @!P1 BRA 0x180 ; /* 0xfffffe6000009947 */
/* 0x000fea000383ffff */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R2, R2, c[0x0][0xc], RZ ; /* 0x0000030002027a10 */
/* 0x000fc80007ffe0ff */
/*0340*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0350*/ @!P0 BRA 0x80 ; /* 0xfffffd2000008947 */
/* 0x000fea000383ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void max_pool3d_backward(int B, int N, int M, int C, const int* maxIndex, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M*C;j+=blockDim.x)
{
int c = j%C;
int n = maxIndex[i*M*C+j];
atomicAdd(&gradInput[i*N*C+n*C+c],gradOutput[i*M*C+j]);
}
}
} | .file "tmpxft_0009954f_00000000-6_max_pool3d_backward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf
.type _Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf, @function
_Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19max_pool3d_backwardiiiiPKiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf, .-_Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf
.globl _Z19max_pool3d_backwardiiiiPKiPKfPf
.type _Z19max_pool3d_backwardiiiiPKiPKfPf, @function
_Z19max_pool3d_backwardiiiiPKiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19max_pool3d_backwardiiiiPKiPKfPf, .-_Z19max_pool3d_backwardiiiiPKiPKfPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19max_pool3d_backwardiiiiPKiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19max_pool3d_backwardiiiiPKiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void max_pool3d_backward(int B, int N, int M, int C, const int* maxIndex, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M*C;j+=blockDim.x)
{
int c = j%C;
int n = maxIndex[i*M*C+j];
atomicAdd(&gradInput[i*N*C+n*C+c],gradOutput[i*M*C+j]);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void max_pool3d_backward(int B, int N, int M, int C, const int* maxIndex, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M*C;j+=blockDim.x)
{
int c = j%C;
int n = maxIndex[i*M*C+j];
atomicAdd(&gradInput[i*N*C+n*C+c],gradOutput[i*M*C+j]);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void max_pool3d_backward(int B, int N, int M, int C, const int* maxIndex, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M*C;j+=blockDim.x)
{
int c = j%C;
int n = maxIndex[i*M*C+j];
atomicAdd(&gradInput[i*N*C+n*C+c],gradOutput[i*M*C+j]);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19max_pool3d_backwardiiiiPKiPKfPf
.globl _Z19max_pool3d_backwardiiiiPKiPKfPf
.p2align 8
.type _Z19max_pool3d_backwardiiiiPKiPKfPf,@function
_Z19max_pool3d_backwardiiiiPKiPKfPf:
s_load_b32 s12, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_8
s_clause 0x1
s_load_b32 s13, s[0:1], 0xc
s_load_b64 s[8:9], s[0:1], 0x4
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s13, 31
s_mul_i32 s9, s13, s9
s_add_i32 s5, s13, s4
v_cmp_gt_i32_e32 vcc_lo, s9, v0
s_xor_b32 s14, s5, s4
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x20
s_load_b32 s1, s[0:1], 0x28
v_cvt_f32_u32_e32 v1, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v5, v1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s16
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s1, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_and_saveexec_b32 s16, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s0, s[2:3], 0xc
v_mov_b32_e32 v6, v0
s_mul_i32 s17, s9, s15
s_mul_i32 s18, s15, s8
s_mov_b32 s20, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s0, 0xffff
.LBB0_5:
v_add_nc_u32_e32 v1, s17, v6
v_ashrrev_i32_e32 v7, 31, v6
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v8, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_xor_b32_e32 v8, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s4, v1
v_add_co_ci_u32_e64 v4, s0, s5, v2, s0
s_sub_i32 s0, 0, s14
global_load_b32 v4, v[3:4], off
v_mul_lo_u32 v3, s0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v5, v3
v_add_nc_u32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v8, v3
v_mul_lo_u32 v3, v3, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v8, v3
v_subrev_nc_u32_e32 v8, s14, v3
v_cmp_le_u32_e64 s0, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v8, s0
v_subrev_nc_u32_e32 v8, s14, v3
v_cmp_le_u32_e64 s0, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v8, s0
v_xor_b32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v7
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, s18, v4
v_mad_u64_u32 v[7:8], null, v4, s13, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[3:4], 2, v[7:8]
v_add_co_u32 v7, s0, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, s7, v2, s0
v_add_co_u32 v1, s0, s10, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s11, v4, s0
global_load_b32 v7, v[7:8], off
global_load_b32 v4, v[1:2], off
.LBB0_6:
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v4, v7
global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v3, v4
v_mov_b32_e32 v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s21, s0, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s21
v_add_nc_u32_e32 v6, s19, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s9, v6
s_or_b32 s20, s0, s20
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19max_pool3d_backwardiiiiPKiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19max_pool3d_backwardiiiiPKiPKfPf, .Lfunc_end0-_Z19max_pool3d_backwardiiiiPKiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19max_pool3d_backwardiiiiPKiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z19max_pool3d_backwardiiiiPKiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void max_pool3d_backward(int B, int N, int M, int C, const int* maxIndex, const float* gradOutput, float* gradInput)
{
for(int i=blockIdx.x;i<B;i+=gridDim.x)
{
for(int j=threadIdx.x;j<M*C;j+=blockDim.x)
{
int c = j%C;
int n = maxIndex[i*M*C+j];
atomicAdd(&gradInput[i*N*C+n*C+c],gradOutput[i*M*C+j]);
}
}
} | .text
.file "max_pool3d_backward.hip"
.globl _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf # -- Begin function _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.p2align 4, 0x90
.type _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf,@function
_Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf: # @_Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19max_pool3d_backwardiiiiPKiPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf, .Lfunc_end0-_Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19max_pool3d_backwardiiiiPKiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19max_pool3d_backwardiiiiPKiPKfPf,@object # @_Z19max_pool3d_backwardiiiiPKiPKfPf
.section .rodata,"a",@progbits
.globl _Z19max_pool3d_backwardiiiiPKiPKfPf
.p2align 3, 0x0
_Z19max_pool3d_backwardiiiiPKiPKfPf:
.quad _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.size _Z19max_pool3d_backwardiiiiPKiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19max_pool3d_backwardiiiiPKiPKfPf"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19max_pool3d_backwardiiiiPKiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z19max_pool3d_backwardiiiiPKiPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x001fda0003f06270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ ULDC.64 UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0080*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf06270 */
/*0090*/ BSSY B0, 0x330 ; /* 0x0000029000007945 */
/* 0x000fd80003800000 */
/*00a0*/ @P0 BRA 0x320 ; /* 0x0000027000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IABS R3, c[0x0][0x16c] ; /* 0x00005b0000037a13 */
/* 0x000fe40000000000 */
/*00c0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0c */
/* 0x000fe40003f05270 */
/*00d0*/ I2F.RP R8, R3 ; /* 0x0000000300087306 */
/* 0x000e220000209400 */
/*00e0*/ LOP3.LUT R13, RZ, c[0x0][0x16c], RZ, 0x33, !PT ; /* 0x00005b00ff0d7a12 */
/* 0x000fce00078e33ff */
/*00f0*/ MUFU.RCP R8, R8 ; /* 0x0000000800087308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R6, R8, 0xffffffe, RZ ; /* 0x0ffffffe08067810 */
/* 0x001fcc0007ffe0ff */
/*0110*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0120*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0130*/ IMAD.MOV R4, RZ, RZ, -R7 ; /* 0x000000ffff047224 */
/* 0x002fc800078e0a07 */
/*0140*/ IMAD R5, R4, R3, RZ ; /* 0x0000000304057224 */
/* 0x000fe400078e02ff */
/*0150*/ IMAD R4, R2, UR4, RZ ; /* 0x0000000402047c24 */
/* 0x000fe4000f8e02ff */
/*0160*/ IMAD.HI.U32 R10, R7, R5, R6 ; /* 0x00000005070a7227 */
/* 0x000fe200078e0006 */
/*0170*/ MOV R5, R0 ; /* 0x0000000000057202 */
/* 0x000fca0000000f00 */
/*0180*/ IMAD.IADD R8, R4, 0x1, R5 ; /* 0x0000000104087824 */
/* 0x000fe400078e0205 */
/*0190*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R6, R8, R15, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x001fcc00078e020f */
/*01b0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*01c0*/ IMAD.WIDE R8, R8, R15, c[0x0][0x178] ; /* 0x00005e0008087625 */
/* 0x000fcc00078e020f */
/*01d0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000ee2000c1e1900 */
/*01e0*/ IABS R17, R5 ; /* 0x0000000500117213 */
/* 0x000fe20000000000 */
/*01f0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*0200*/ IABS R19, c[0x0][0x16c] ; /* 0x00005b0000137a13 */
/* 0x000fe40000000000 */
/*0210*/ ISETP.GE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f46270 */
/*0220*/ IMAD.HI.U32 R11, R10, R17, RZ ; /* 0x000000110a0b7227 */
/* 0x000fca00078e00ff */
/*0230*/ IADD3 R12, -R11, RZ, RZ ; /* 0x000000ff0b0c7210 */
/* 0x000fca0007ffe1ff */
/*0240*/ IMAD R12, R19, R12, R17 ; /* 0x0000000c130c7224 */
/* 0x000fca00078e0211 */
/*0250*/ ISETP.GT.U32.AND P1, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fda0003f24070 */
/*0260*/ @!P1 IMAD.IADD R12, R12, 0x1, -R19 ; /* 0x000000010c0c9824 */
/* 0x000fca00078e0a13 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R3, R12, PT ; /* 0x0000000c0300720c */
/* 0x000fe40003f24070 */
/*0280*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x000fd60007ffe0ff */
/*0290*/ @!P1 IMAD.IADD R12, R12, 0x1, -R19 ; /* 0x000000010c0c9824 */
/* 0x000fca00078e0a13 */
/*02a0*/ @!P2 IADD3 R12, -R12, RZ, RZ ; /* 0x000000ff0c0ca210 */
/* 0x000fe40007ffe1ff */
/*02b0*/ ISETP.GE.AND P1, PT, R5, UR4, PT ; /* 0x0000000405007c0c */
/* 0x000fe4000bf26270 */
/*02c0*/ SEL R12, R13, R12, !P0 ; /* 0x0000000c0d0c7207 */
/* 0x000fe20004000000 */
/*02d0*/ IMAD R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a24 */
/* 0x004fc800078e0207 */
/*02e0*/ IMAD R6, R7, c[0x0][0x16c], R12 ; /* 0x00005b0007067a24 */
/* 0x000fc800078e020c */
/*02f0*/ IMAD.WIDE R6, R6, R15, c[0x0][0x180] ; /* 0x0000600006067625 */
/* 0x000fca00078e020f */
/*0300*/ RED.E.ADD.F32.FTZ.RN.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0081e2000c10e786 */
/*0310*/ @!P1 BRA 0x180 ; /* 0xfffffe6000009947 */
/* 0x000fea000383ffff */
/*0320*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R2, R2, c[0x0][0xc], RZ ; /* 0x0000030002027a10 */
/* 0x000fc80007ffe0ff */
/*0340*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0350*/ @!P0 BRA 0x80 ; /* 0xfffffd2000008947 */
/* 0x000fea000383ffff */
/*0360*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0370*/ BRA 0x370; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z19max_pool3d_backwardiiiiPKiPKfPf
.globl _Z19max_pool3d_backwardiiiiPKiPKfPf
.p2align 8
.type _Z19max_pool3d_backwardiiiiPKiPKfPf,@function
_Z19max_pool3d_backwardiiiiPKiPKfPf:
s_load_b32 s12, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_8
s_clause 0x1
s_load_b32 s13, s[0:1], 0xc
s_load_b64 s[8:9], s[0:1], 0x4
s_add_u32 s2, s0, 40
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s13, 31
s_mul_i32 s9, s13, s9
s_add_i32 s5, s13, s4
v_cmp_gt_i32_e32 vcc_lo, s9, v0
s_xor_b32 s14, s5, s4
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x20
s_load_b32 s1, s[0:1], 0x28
v_cvt_f32_u32_e32 v1, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v5, v1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s16
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s1, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s15, s12
s_cbranch_scc1 .LBB0_8
.LBB0_3:
s_and_saveexec_b32 s16, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b32 s0, s[2:3], 0xc
v_mov_b32_e32 v6, v0
s_mul_i32 s17, s9, s15
s_mul_i32 s18, s15, s8
s_mov_b32 s20, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s19, s0, 0xffff
.LBB0_5:
v_add_nc_u32_e32 v1, s17, v6
v_ashrrev_i32_e32 v7, 31, v6
s_mov_b32 s21, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v8, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_xor_b32_e32 v8, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s0, s4, v1
v_add_co_ci_u32_e64 v4, s0, s5, v2, s0
s_sub_i32 s0, 0, s14
global_load_b32 v4, v[3:4], off
v_mul_lo_u32 v3, s0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v5, v3
v_add_nc_u32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v8, v3
v_mul_lo_u32 v3, v3, s14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v8, v3
v_subrev_nc_u32_e32 v8, s14, v3
v_cmp_le_u32_e64 s0, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v8, s0
v_subrev_nc_u32_e32 v8, s14, v3
v_cmp_le_u32_e64 s0, s14, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v8, s0
v_xor_b32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v3, v7
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, s18, v4
v_mad_u64_u32 v[7:8], null, v4, s13, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[3:4], 2, v[7:8]
v_add_co_u32 v7, s0, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s0, s7, v2, s0
v_add_co_u32 v1, s0, s10, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, s0, s11, v4, s0
global_load_b32 v7, v[7:8], off
global_load_b32 v4, v[1:2], off
.LBB0_6:
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v4, v7
global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e64 s0, v3, v4
v_mov_b32_e32 v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s21, s0, s21
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s21
v_add_nc_u32_e32 v6, s19, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s0, s9, v6
s_or_b32 s20, s0, s20
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s20
s_cbranch_execnz .LBB0_5
s_branch .LBB0_2
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z19max_pool3d_backwardiiiiPKiPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 22
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z19max_pool3d_backwardiiiiPKiPKfPf, .Lfunc_end0-_Z19max_pool3d_backwardiiiiPKiPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z19max_pool3d_backwardiiiiPKiPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 24
.sgpr_spill_count: 0
.symbol: _Z19max_pool3d_backwardiiiiPKiPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009954f_00000000-6_max_pool3d_backward.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf
.type _Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf, @function
_Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 192(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19max_pool3d_backwardiiiiPKiPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf, .-_Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf
.globl _Z19max_pool3d_backwardiiiiPKiPKfPf
.type _Z19max_pool3d_backwardiiiiPKiPKfPf, @function
_Z19max_pool3d_backwardiiiiPKiPKfPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z19max_pool3d_backwardiiiiPKiPKfPfiiiiPKiPKfPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19max_pool3d_backwardiiiiPKiPKfPf, .-_Z19max_pool3d_backwardiiiiPKiPKfPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z19max_pool3d_backwardiiiiPKiPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19max_pool3d_backwardiiiiPKiPKfPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "max_pool3d_backward.hip"
.globl _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf # -- Begin function _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.p2align 4, 0x90
.type _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf,@function
_Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf: # @_Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19max_pool3d_backwardiiiiPKiPKfPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf, .Lfunc_end0-_Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19max_pool3d_backwardiiiiPKiPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19max_pool3d_backwardiiiiPKiPKfPf,@object # @_Z19max_pool3d_backwardiiiiPKiPKfPf
.section .rodata,"a",@progbits
.globl _Z19max_pool3d_backwardiiiiPKiPKfPf
.p2align 3, 0x0
_Z19max_pool3d_backwardiiiiPKiPKfPf:
.quad _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.size _Z19max_pool3d_backwardiiiiPKiPKfPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19max_pool3d_backwardiiiiPKiPKfPf"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__max_pool3d_backwardiiiiPKiPKfPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19max_pool3d_backwardiiiiPKiPKfPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //¾ùÖµÂ˲¨±»³ÆΪboxfilter
#define TILE_DIM 16
#define BLOCKSIZE 128
__global__ void d_boxfilter_x_global(float *src, float *dst, int width, int height, int r)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
int num = (width + 2 * r + 2 * BLOCKSIZE - 1) / (2 * BLOCKSIZE); //ÿһ¸öÏ߳̿鱻BLOCKSIZE*2·Ö¸î³ÉÁËnum¸ösegment
int len = num * 2 * BLOCKSIZE;
int extra = len - r - width;
float scale = 1.0f / (float)((r << 1) + 1);
__shared__ float sum[35]; sum[0] = 0;
extern __shared__ float temp[];
if (bid < height)
{
for (int i = tid; i < r; i += BLOCKSIZE)
{
temp[i] = src[bid*width + 0];
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
temp[r + i] = src[bid * width + i];
}
for (int i = tid; i < extra; i += BLOCKSIZE)
{
temp[r + width + i] = src[(bid + 1) * width - 1];
}
__syncthreads();
for (int cnt = 0; cnt < num; ++cnt)
{
int bias = cnt * BLOCKSIZE * 2;
for (int j = BLOCKSIZE; j > 0; j >>= 1)
{
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
temp[bi] += temp[ai];
}
offset *= 2;
__syncthreads();
}
if (tid == 0)
{
sum[cnt + 1] = temp[(cnt + 1) * BLOCKSIZE * 2 - 1] + sum[cnt];
temp[(cnt + 1) * BLOCKSIZE * 2 - 1] = 0;
}
__syncthreads();
for (int j = 1; j < (BLOCKSIZE * 2); j *= 2)
{
offset >>= 1;
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
float t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
__syncthreads();
}
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
float sum_box = temp[i + 2 * r + 1] + sum[(i + 2 * r + 1) / (BLOCKSIZE * 2)] - temp[i] - sum[i / (BLOCKSIZE * 2)]; //sumÖ»ÊǵÚi + 2 * r + 1֮ǰµÄËùÓÐÔªËØÖ®ºÍ²»°üÀ¨µÚi + 2 * r + 1¸öÔªËØ
dst[bid * width + i] = sum_box * scale;
}
}
} | .file "tmpxft_000c1101_00000000-6_boxfilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii
.type _Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii, @function
_Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20d_boxfilter_x_globalPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii, .-_Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii
.globl _Z20d_boxfilter_x_globalPfS_iii
.type _Z20d_boxfilter_x_globalPfS_iii, @function
_Z20d_boxfilter_x_globalPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20d_boxfilter_x_globalPfS_iii, .-_Z20d_boxfilter_x_globalPfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20d_boxfilter_x_globalPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20d_boxfilter_x_globalPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //¾ùÖµÂ˲¨±»³ÆΪboxfilter
#define TILE_DIM 16
#define BLOCKSIZE 128
__global__ void d_boxfilter_x_global(float *src, float *dst, int width, int height, int r)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
int num = (width + 2 * r + 2 * BLOCKSIZE - 1) / (2 * BLOCKSIZE); //ÿһ¸öÏ߳̿鱻BLOCKSIZE*2·Ö¸î³ÉÁËnum¸ösegment
int len = num * 2 * BLOCKSIZE;
int extra = len - r - width;
float scale = 1.0f / (float)((r << 1) + 1);
__shared__ float sum[35]; sum[0] = 0;
extern __shared__ float temp[];
if (bid < height)
{
for (int i = tid; i < r; i += BLOCKSIZE)
{
temp[i] = src[bid*width + 0];
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
temp[r + i] = src[bid * width + i];
}
for (int i = tid; i < extra; i += BLOCKSIZE)
{
temp[r + width + i] = src[(bid + 1) * width - 1];
}
__syncthreads();
for (int cnt = 0; cnt < num; ++cnt)
{
int bias = cnt * BLOCKSIZE * 2;
for (int j = BLOCKSIZE; j > 0; j >>= 1)
{
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
temp[bi] += temp[ai];
}
offset *= 2;
__syncthreads();
}
if (tid == 0)
{
sum[cnt + 1] = temp[(cnt + 1) * BLOCKSIZE * 2 - 1] + sum[cnt];
temp[(cnt + 1) * BLOCKSIZE * 2 - 1] = 0;
}
__syncthreads();
for (int j = 1; j < (BLOCKSIZE * 2); j *= 2)
{
offset >>= 1;
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
float t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
__syncthreads();
}
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
float sum_box = temp[i + 2 * r + 1] + sum[(i + 2 * r + 1) / (BLOCKSIZE * 2)] - temp[i] - sum[i / (BLOCKSIZE * 2)]; //sumÖ»ÊǵÚi + 2 * r + 1֮ǰµÄËùÓÐÔªËØÖ®ºÍ²»°üÀ¨µÚi + 2 * r + 1¸öÔªËØ
dst[bid * width + i] = sum_box * scale;
}
}
} | #include <hip/hip_runtime.h>
//¾ùÖµÂ˲¨±»³ÆΪboxfilter
#define TILE_DIM 16
#define BLOCKSIZE 128
__global__ void d_boxfilter_x_global(float *src, float *dst, int width, int height, int r)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
int num = (width + 2 * r + 2 * BLOCKSIZE - 1) / (2 * BLOCKSIZE); //ÿһ¸öÏ߳̿鱻BLOCKSIZE*2·Ö¸î³ÉÁËnum¸ösegment
int len = num * 2 * BLOCKSIZE;
int extra = len - r - width;
float scale = 1.0f / (float)((r << 1) + 1);
__shared__ float sum[35]; sum[0] = 0;
extern __shared__ float temp[];
if (bid < height)
{
for (int i = tid; i < r; i += BLOCKSIZE)
{
temp[i] = src[bid*width + 0];
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
temp[r + i] = src[bid * width + i];
}
for (int i = tid; i < extra; i += BLOCKSIZE)
{
temp[r + width + i] = src[(bid + 1) * width - 1];
}
__syncthreads();
for (int cnt = 0; cnt < num; ++cnt)
{
int bias = cnt * BLOCKSIZE * 2;
for (int j = BLOCKSIZE; j > 0; j >>= 1)
{
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
temp[bi] += temp[ai];
}
offset *= 2;
__syncthreads();
}
if (tid == 0)
{
sum[cnt + 1] = temp[(cnt + 1) * BLOCKSIZE * 2 - 1] + sum[cnt];
temp[(cnt + 1) * BLOCKSIZE * 2 - 1] = 0;
}
__syncthreads();
for (int j = 1; j < (BLOCKSIZE * 2); j *= 2)
{
offset >>= 1;
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
float t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
__syncthreads();
}
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
float sum_box = temp[i + 2 * r + 1] + sum[(i + 2 * r + 1) / (BLOCKSIZE * 2)] - temp[i] - sum[i / (BLOCKSIZE * 2)]; //sumÖ»ÊǵÚi + 2 * r + 1֮ǰµÄËùÓÐÔªËØÖ®ºÍ²»°üÀ¨µÚi + 2 * r + 1¸öÔªËØ
dst[bid * width + i] = sum_box * scale;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//¾ùÖµÂ˲¨±»³ÆΪboxfilter
#define TILE_DIM 16
#define BLOCKSIZE 128
__global__ void d_boxfilter_x_global(float *src, float *dst, int width, int height, int r)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
int num = (width + 2 * r + 2 * BLOCKSIZE - 1) / (2 * BLOCKSIZE); //ÿһ¸öÏ߳̿鱻BLOCKSIZE*2·Ö¸î³ÉÁËnum¸ösegment
int len = num * 2 * BLOCKSIZE;
int extra = len - r - width;
float scale = 1.0f / (float)((r << 1) + 1);
__shared__ float sum[35]; sum[0] = 0;
extern __shared__ float temp[];
if (bid < height)
{
for (int i = tid; i < r; i += BLOCKSIZE)
{
temp[i] = src[bid*width + 0];
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
temp[r + i] = src[bid * width + i];
}
for (int i = tid; i < extra; i += BLOCKSIZE)
{
temp[r + width + i] = src[(bid + 1) * width - 1];
}
__syncthreads();
for (int cnt = 0; cnt < num; ++cnt)
{
int bias = cnt * BLOCKSIZE * 2;
for (int j = BLOCKSIZE; j > 0; j >>= 1)
{
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
temp[bi] += temp[ai];
}
offset *= 2;
__syncthreads();
}
if (tid == 0)
{
sum[cnt + 1] = temp[(cnt + 1) * BLOCKSIZE * 2 - 1] + sum[cnt];
temp[(cnt + 1) * BLOCKSIZE * 2 - 1] = 0;
}
__syncthreads();
for (int j = 1; j < (BLOCKSIZE * 2); j *= 2)
{
offset >>= 1;
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
float t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
__syncthreads();
}
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
float sum_box = temp[i + 2 * r + 1] + sum[(i + 2 * r + 1) / (BLOCKSIZE * 2)] - temp[i] - sum[i / (BLOCKSIZE * 2)]; //sumÖ»ÊǵÚi + 2 * r + 1֮ǰµÄËùÓÐÔªËØÖ®ºÍ²»°üÀ¨µÚi + 2 * r + 1¸öÔªËØ
dst[bid * width + i] = sum_box * scale;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20d_boxfilter_x_globalPfS_iii
.globl _Z20d_boxfilter_x_globalPfS_iii
.p2align 8
.type _Z20d_boxfilter_x_globalPfS_iii,@function
_Z20d_boxfilter_x_globalPfS_iii:
s_load_b32 s2, s[0:1], 0x14
v_mov_b32_e32 v1, 0
ds_store_b32 v1, v1
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s2
s_cbranch_scc1 .LBB0_28
s_clause 0x2
s_load_b32 s6, s[0:1], 0x18
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s3, s[0:1], 0x10
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB0_4
s_mul_i32 s8, s15, s3
v_lshl_add_u32 v1, v0, 2, 0x8c
s_ashr_i32 s9, s8, 31
v_mov_b32_e32 v3, v0
s_lshl_b64 s[8:9], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s8, s4, s8
s_addc_u32 s9, s5, s9
s_load_b32 s7, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s7
s_mov_b32 s7, 0
.LBB0_3:
v_add_nc_u32_e32 v3, 0x80, v3
ds_store_b32 v1, v2
v_add_nc_u32_e32 v1, 0x200, v1
v_cmp_le_i32_e32 vcc_lo, s6, v3
s_or_b32 s7, vcc_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s7
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s7, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_7
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_dual_mov_b32 v4, v0 :: v_dual_add_nc_u32 v3, s6, v0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshl_add_u32 v3, v3, 2, 0x8c
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
.p2align 6
.LBB0_6:
global_load_b32 v5, v[1:2], off
v_add_nc_u32_e32 v4, 0x80, v4
v_add_co_u32 v1, vcc_lo, v1, 0x200
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, s3, v4
s_or_b32 s8, s2, s8
s_waitcnt vmcnt(0)
ds_store_b32 v3, v5
v_add_nc_u32_e32 v3, 0x200, v3
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s7, s6, 1
s_add_i32 s10, s6, s3
s_add_i32 s2, s3, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_addk_i32 s2, 0xff
s_ashr_i32 s8, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s8, s8, 24
s_add_i32 s8, s2, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s9, s8, 0xffffff00
s_sub_i32 s9, s9, s10
s_mov_b32 s10, exec_lo
v_cmpx_gt_i32_e64 s9, v0
s_cbranch_execz .LBB0_10
s_add_i32 s11, s15, 1
v_add3_u32 v1, s3, s6, v0
s_mul_i32 s12, s11, s3
v_mov_b32_e32 v3, v0
s_ashr_i32 s13, s12, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[12:13], 2
v_lshl_add_u32 v1, v1, 2, 0x8c
s_add_u32 s4, s4, s12
s_addc_u32 s5, s5, s13
s_add_u32 s4, s4, -4
s_addc_u32 s5, s5, -1
s_load_b32 s4, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s4
s_mov_b32 s4, 0
.LBB0_9:
v_add_nc_u32_e32 v3, 0x80, v3
ds_store_b32 v1, v2
v_add_nc_u32_e32 v1, 0x200, v1
v_cmp_le_i32_e32 vcc_lo, s9, v3
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_9
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s10
s_ashr_i32 s5, s8, 8
s_cmpk_lt_i32 s2, 0x100
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_25
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 1, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_mov_b32 s8, 1
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v1, 1, v2
v_add_nc_u32_e32 v2, 2, v2
s_branch .LBB0_13
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_add_i32 s9, s9, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s9, s5
s_cbranch_scc1 .LBB0_25
.LBB0_13:
s_lshl_b32 s2, s9, 8
s_movk_i32 s10, 0x80
s_add_i32 s4, s2, -1
.p2align 6
.LBB0_14:
s_mov_b32 s11, exec_lo
v_cmpx_gt_u32_e64 s10, v0
s_cbranch_execz .LBB0_16
v_mad_u64_u32 v[4:5], null, s8, v1, s[4:5]
v_mad_u64_u32 v[5:6], null, s8, v2, s[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v4, v4, 2, 0x8c
v_lshl_add_u32 v5, v5, 2, 0x8c
ds_load_b32 v4, v4
ds_load_b32 v6, v5
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v4, v6
ds_store_b32 v5, v4
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b32 s8, s8, 1
s_lshr_b32 s2, s10, 1
s_cmp_lt_u32 s10, 2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_18
s_mov_b32 s10, s2
s_branch .LBB0_14
.LBB0_18:
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_20
s_lshl_b32 s10, s9, 10
s_lshl_b32 s11, s9, 2
s_addk_i32 s10, 0x8c
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v4, s11 :: v_dual_mov_b32 v5, s10
ds_load_b32 v6, v4
ds_load_b32 v7, v5 offset:1020
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v6, v7, v6
ds_store_b32 v4, v6 offset:4
ds_store_b32 v5, v3 offset:1020
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s2
s_mov_b32 s10, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_21:
s_ashr_i32 s8, s8, 1
s_mov_b32 s11, exec_lo
v_cmpx_gt_u32_e64 s10, v0
s_cbranch_execz .LBB0_23
v_mad_u64_u32 v[4:5], null, s8, v2, s[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v6, v4, 2, 0x8c
v_mad_u64_u32 v[4:5], null, s8, v1, s[4:5]
ds_load_b32 v7, v6
v_lshl_add_u32 v4, v4, 2, 0x8c
ds_load_b32 v5, v4
s_waitcnt lgkmcnt(1)
ds_store_b32 v4, v7
ds_load_b32 v4, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v4, v5, v4
ds_store_b32 v6, v4
.LBB0_23:
s_or_b32 exec_lo, exec_lo, s11
s_lshl_b32 s2, s10, 1
s_cmpk_gt_u32 s10, 0x7f
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_12
s_mov_b32 s10, s2
s_branch .LBB0_21
.LBB0_25:
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v0
s_cbranch_execz .LBB0_28
s_or_b32 s2, s7, 1
s_load_b64 s[0:1], s[0:1], 0x8
v_cvt_f32_i32_e32 v3, s2
s_add_i32 s7, s7, 1
s_mov_b32 s2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v4, null, v3, v3, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v3, 1.0
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v1, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v5, v1, v5
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v2, -v4, v7, v6
v_fmac_f32_e32 v7, v2, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_div_fmas_f32 v4, v4, v5, v7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v3, v4, v3, 1.0
v_lshl_add_u32 v4, v0, 2, 0x8c
s_lshl_b32 s1, s6, 3
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_27:
v_add_nc_u32_e32 v5, s7, v0
ds_load_b32 v7, v4
v_add_nc_u32_e32 v6, s1, v4
v_lshrrev_b32_e32 v8, 6, v0
v_add_nc_u32_e32 v4, 0x200, v4
v_ashrrev_i32_e32 v9, 31, v5
ds_load_b32 v6, v6 offset:4
v_lshrrev_b32_e32 v9, 24, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v9
v_ashrrev_i32_e32 v5, 8, v5
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v5, v6, v5 :: v_dual_and_b32 v8, 0x3fffffc, v8
ds_load_b32 v8, v8
v_sub_f32_e32 v5, v5, v7
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v8
v_dual_mul_f32 v5, v3, v5 :: v_dual_add_nc_u32 v0, 0x80, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, s3, v0
global_store_b32 v[1:2], v5, off
v_add_co_u32 v1, s0, v1, 0x200
v_add_co_ci_u32_e64 v2, s0, 0, v2, s0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_27
.LBB0_28:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20d_boxfilter_x_globalPfS_iii
.amdhsa_group_segment_fixed_size 140
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20d_boxfilter_x_globalPfS_iii, .Lfunc_end0-_Z20d_boxfilter_x_globalPfS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 140
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20d_boxfilter_x_globalPfS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20d_boxfilter_x_globalPfS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//¾ùÖµÂ˲¨±»³ÆΪboxfilter
#define TILE_DIM 16
#define BLOCKSIZE 128
__global__ void d_boxfilter_x_global(float *src, float *dst, int width, int height, int r)
{
int tid = threadIdx.x;
int bid = blockIdx.x;
int offset = 1;
int num = (width + 2 * r + 2 * BLOCKSIZE - 1) / (2 * BLOCKSIZE); //ÿһ¸öÏ߳̿鱻BLOCKSIZE*2·Ö¸î³ÉÁËnum¸ösegment
int len = num * 2 * BLOCKSIZE;
int extra = len - r - width;
float scale = 1.0f / (float)((r << 1) + 1);
__shared__ float sum[35]; sum[0] = 0;
extern __shared__ float temp[];
if (bid < height)
{
for (int i = tid; i < r; i += BLOCKSIZE)
{
temp[i] = src[bid*width + 0];
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
temp[r + i] = src[bid * width + i];
}
for (int i = tid; i < extra; i += BLOCKSIZE)
{
temp[r + width + i] = src[(bid + 1) * width - 1];
}
__syncthreads();
for (int cnt = 0; cnt < num; ++cnt)
{
int bias = cnt * BLOCKSIZE * 2;
for (int j = BLOCKSIZE; j > 0; j >>= 1)
{
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
temp[bi] += temp[ai];
}
offset *= 2;
__syncthreads();
}
if (tid == 0)
{
sum[cnt + 1] = temp[(cnt + 1) * BLOCKSIZE * 2 - 1] + sum[cnt];
temp[(cnt + 1) * BLOCKSIZE * 2 - 1] = 0;
}
__syncthreads();
for (int j = 1; j < (BLOCKSIZE * 2); j *= 2)
{
offset >>= 1;
if (tid < j)
{
int ai = bias + offset * (2 * tid + 1) - 1;
int bi = bias + offset * (2 * tid + 2) - 1;
float t = temp[ai];
temp[ai] = temp[bi];
temp[bi] += t;
}
__syncthreads();
}
}
for (int i = tid; i < width; i += BLOCKSIZE)
{
float sum_box = temp[i + 2 * r + 1] + sum[(i + 2 * r + 1) / (BLOCKSIZE * 2)] - temp[i] - sum[i / (BLOCKSIZE * 2)]; //sumÖ»ÊǵÚi + 2 * r + 1֮ǰµÄËùÓÐÔªËØÖ®ºÍ²»°üÀ¨µÚi + 2 * r + 1¸öÔªËØ
dst[bid * width + i] = sum_box * scale;
}
}
} | .text
.file "boxfilter.hip"
.globl _Z35__device_stub__d_boxfilter_x_globalPfS_iii # -- Begin function _Z35__device_stub__d_boxfilter_x_globalPfS_iii
.p2align 4, 0x90
.type _Z35__device_stub__d_boxfilter_x_globalPfS_iii,@function
_Z35__device_stub__d_boxfilter_x_globalPfS_iii: # @_Z35__device_stub__d_boxfilter_x_globalPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20d_boxfilter_x_globalPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__d_boxfilter_x_globalPfS_iii, .Lfunc_end0-_Z35__device_stub__d_boxfilter_x_globalPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20d_boxfilter_x_globalPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20d_boxfilter_x_globalPfS_iii,@object # @_Z20d_boxfilter_x_globalPfS_iii
.section .rodata,"a",@progbits
.globl _Z20d_boxfilter_x_globalPfS_iii
.p2align 3, 0x0
_Z20d_boxfilter_x_globalPfS_iii:
.quad _Z35__device_stub__d_boxfilter_x_globalPfS_iii
.size _Z20d_boxfilter_x_globalPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20d_boxfilter_x_globalPfS_iii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__d_boxfilter_x_globalPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20d_boxfilter_x_globalPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c1101_00000000-6_boxfilter.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii
.type _Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii, @function
_Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20d_boxfilter_x_globalPfS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii, .-_Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii
.globl _Z20d_boxfilter_x_globalPfS_iii
.type _Z20d_boxfilter_x_globalPfS_iii, @function
_Z20d_boxfilter_x_globalPfS_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z20d_boxfilter_x_globalPfS_iiiPfS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20d_boxfilter_x_globalPfS_iii, .-_Z20d_boxfilter_x_globalPfS_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20d_boxfilter_x_globalPfS_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20d_boxfilter_x_globalPfS_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "boxfilter.hip"
.globl _Z35__device_stub__d_boxfilter_x_globalPfS_iii # -- Begin function _Z35__device_stub__d_boxfilter_x_globalPfS_iii
.p2align 4, 0x90
.type _Z35__device_stub__d_boxfilter_x_globalPfS_iii,@function
_Z35__device_stub__d_boxfilter_x_globalPfS_iii: # @_Z35__device_stub__d_boxfilter_x_globalPfS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20d_boxfilter_x_globalPfS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z35__device_stub__d_boxfilter_x_globalPfS_iii, .Lfunc_end0-_Z35__device_stub__d_boxfilter_x_globalPfS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20d_boxfilter_x_globalPfS_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20d_boxfilter_x_globalPfS_iii,@object # @_Z20d_boxfilter_x_globalPfS_iii
.section .rodata,"a",@progbits
.globl _Z20d_boxfilter_x_globalPfS_iii
.p2align 3, 0x0
_Z20d_boxfilter_x_globalPfS_iii:
.quad _Z35__device_stub__d_boxfilter_x_globalPfS_iii
.size _Z20d_boxfilter_x_globalPfS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20d_boxfilter_x_globalPfS_iii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__d_boxfilter_x_globalPfS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20d_boxfilter_x_globalPfS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void normalization(int *glcm,float *norm,int Max,int sum){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * Max + ix;
__syncthreads();
if(idx<(Max+1)*(Max+1)){
norm[idx]=float(glcm[idx])/float(sum);
}
} | code for sm_80
Function : _Z13normalizationPiPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e260000002500 */
/*0050*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*00a0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fca00078e0200 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0100*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ I2F R5, c[0x0][0x174] ; /* 0x00005d0000057b06 */
/* 0x000e220000201400 */
/*0130*/ BSSY B0, 0x200 ; /* 0x000000c000007945 */
/* 0x000fee0003800000 */
/*0140*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x001e240000001000 */
/*0150*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*0160*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fe40000000006 */
/*0170*/ I2F R4, R2 ; /* 0x0000000200047306 */
/* 0x004e300000201400 */
/*0180*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x001e220000000000 */
/*0190*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R8, -R5, R6, R4 ; /* 0x0000000605087223 */
/* 0x000fc80000000104 */
/*01b0*/ FFMA R7, R7, R8, R6 ; /* 0x0000000807077223 */
/* 0x000fe20000000006 */
/*01c0*/ @!P0 BRA 0x1f0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*01d0*/ MOV R2, 0x1f0 ; /* 0x000001f000027802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x240 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0220*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011605 */
/*0250*/ BSSY B1, 0x8a0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0260*/ SHF.R.U32.HI R3, RZ, 0x17, R4.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011604 */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0280*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*02a0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*02b0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ IADD3 R10, R3, -0x1, RZ ; /* 0xffffffff030a7810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*02e0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*02f0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0300*/ @!P0 BRA 0x480 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0320*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0330*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0340*/ @P0 BRA 0x880 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0350*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0360*/ @!P0 BRA 0x860 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0380*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0390*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*03a0*/ @!P1 BRA !P2, 0x860 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03b0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*03c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03d0*/ @P1 BRA 0x840 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03e0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*03f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0400*/ @P0 BRA 0x810 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0420*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0430*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0440*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0450*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*0460*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0470*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LEA R5, R6, 0xc0800000, 0x17 ; /* 0xc080000006057811 */
/* 0x000fe200078eb8ff */
/*0490*/ BSSY B2, 0x800 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*04a0*/ IADD3 R4, R3, -0x7f, RZ ; /* 0xffffff8103047810 */
/* 0x000fc60007ffe0ff */
/*04b0*/ IMAD.IADD R5, R8, 0x1, -R5 ; /* 0x0000000108057824 */
/* 0x000fe200078e0a05 */
/*04c0*/ IADD3 R6, R4.reuse, 0x7f, -R6 ; /* 0x0000007f04067810 */
/* 0x040fe20007ffe806 */
/*04d0*/ IMAD R7, R4, -0x800000, R7 ; /* 0xff80000004077824 */
/* 0x000fe400078e0207 */
/*04e0*/ MUFU.RCP R8, R5 ; /* 0x0000000500087308 */
/* 0x000e220000001000 */
/*04f0*/ FADD.FTZ R10, -R5, -RZ ; /* 0x800000ff050a7221 */
/* 0x000fe40000010100 */
/*0500*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0510*/ FFMA R3, R8, R10, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000a */
/*0520*/ FFMA R12, R8, R3, R8 ; /* 0x00000003080c7223 */
/* 0x000fc80000000008 */
/*0530*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0540*/ FFMA R8, R10, R3, R7 ; /* 0x000000030a087223 */
/* 0x000fc80000000007 */
/*0550*/ FFMA R11, R12, R8, R3 ; /* 0x000000080c0b7223 */
/* 0x000fc80000000003 */
/*0560*/ FFMA R7, R10, R11, R7 ; /* 0x0000000b0a077223 */
/* 0x000fc80000000007 */
/*0570*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0580*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0590*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*05a0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*05b0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*05d0*/ @!P0 BRA 0x7e0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*05f0*/ @P0 BRA 0x7b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0610*/ @P0 BRA 0x7f0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0630*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0640*/ @!P0 BRA 0x7f0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0650*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0660*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0670*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0680*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0690*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*06a0*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*06b0*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*06d0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*06f0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0700*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0710*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0720*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0740*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0750*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0760*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0770*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0780*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0790*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x7f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*07c0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x7f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07e0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*07f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x890 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0820*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0830*/ BRA 0x890 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0850*/ BRA 0x890 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0860*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0870*/ BRA 0x890 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0880*/ FADD.FTZ R3, R4, R5 ; /* 0x0000000504037221 */
/* 0x000fe40000010000 */
/*0890*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*08b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08c0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff73002007950 */
/* 0x000fea0003c3ffff */
/*08d0*/ BRA 0x8d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void normalization(int *glcm,float *norm,int Max,int sum){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * Max + ix;
__syncthreads();
if(idx<(Max+1)*(Max+1)){
norm[idx]=float(glcm[idx])/float(sum);
}
} | .file "tmpxft_001ade15_00000000-6_normalization.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13normalizationPiPfiiPiPfii
.type _Z37__device_stub__Z13normalizationPiPfiiPiPfii, @function
_Z37__device_stub__Z13normalizationPiPfiiPiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13normalizationPiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13normalizationPiPfiiPiPfii, .-_Z37__device_stub__Z13normalizationPiPfiiPiPfii
.globl _Z13normalizationPiPfii
.type _Z13normalizationPiPfii, @function
_Z13normalizationPiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13normalizationPiPfiiPiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13normalizationPiPfii, .-_Z13normalizationPiPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13normalizationPiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13normalizationPiPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void normalization(int *glcm,float *norm,int Max,int sum){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * Max + ix;
__syncthreads();
if(idx<(Max+1)*(Max+1)){
norm[idx]=float(glcm[idx])/float(sum);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void normalization(int *glcm,float *norm,int Max,int sum){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * Max + ix;
__syncthreads();
if(idx<(Max+1)*(Max+1)){
norm[idx]=float(glcm[idx])/float(sum);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void normalization(int *glcm,float *norm,int Max,int sum){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * Max + ix;
__syncthreads();
if(idx<(Max+1)*(Max+1)){
norm[idx]=float(glcm[idx])/float(sum);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13normalizationPiPfii
.globl _Z13normalizationPiPfii
.p2align 8
.type _Z13normalizationPiPfii,@function
_Z13normalizationPiPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
s_add_i32 s2, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s2
v_mul_lo_u32 v1, v2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s0
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, v2
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13normalizationPiPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13normalizationPiPfii, .Lfunc_end0-_Z13normalizationPiPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13normalizationPiPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13normalizationPiPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void normalization(int *glcm,float *norm,int Max,int sum){
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy * Max + ix;
__syncthreads();
if(idx<(Max+1)*(Max+1)){
norm[idx]=float(glcm[idx])/float(sum);
}
} | .text
.file "normalization.hip"
.globl _Z28__device_stub__normalizationPiPfii # -- Begin function _Z28__device_stub__normalizationPiPfii
.p2align 4, 0x90
.type _Z28__device_stub__normalizationPiPfii,@function
_Z28__device_stub__normalizationPiPfii: # @_Z28__device_stub__normalizationPiPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13normalizationPiPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__normalizationPiPfii, .Lfunc_end0-_Z28__device_stub__normalizationPiPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13normalizationPiPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13normalizationPiPfii,@object # @_Z13normalizationPiPfii
.section .rodata,"a",@progbits
.globl _Z13normalizationPiPfii
.p2align 3, 0x0
_Z13normalizationPiPfii:
.quad _Z28__device_stub__normalizationPiPfii
.size _Z13normalizationPiPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13normalizationPiPfii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__normalizationPiPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13normalizationPiPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13normalizationPiPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e260000002500 */
/*0050*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0060*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0070*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0090*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fc400078e0200 */
/*00a0*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fc800078e0205 */
/*00b0*/ IMAD R0, R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a24 */
/* 0x000fca00078e0200 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0100*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0003 */
/*0110*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ I2F R5, c[0x0][0x174] ; /* 0x00005d0000057b06 */
/* 0x000e220000201400 */
/*0130*/ BSSY B0, 0x200 ; /* 0x000000c000007945 */
/* 0x000fee0003800000 */
/*0140*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x001e240000001000 */
/*0150*/ FFMA R7, -R5, R6, 1 ; /* 0x3f80000005077423 */
/* 0x001fc80000000106 */
/*0160*/ FFMA R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fe40000000006 */
/*0170*/ I2F R4, R2 ; /* 0x0000000200047306 */
/* 0x004e300000201400 */
/*0180*/ FCHK P0, R4, R5 ; /* 0x0000000504007302 */
/* 0x001e220000000000 */
/*0190*/ FFMA R6, R4, R7, RZ ; /* 0x0000000704067223 */
/* 0x000fc800000000ff */
/*01a0*/ FFMA R8, -R5, R6, R4 ; /* 0x0000000605087223 */
/* 0x000fc80000000104 */
/*01b0*/ FFMA R7, R7, R8, R6 ; /* 0x0000000807077223 */
/* 0x000fe20000000006 */
/*01c0*/ @!P0 BRA 0x1f0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*01d0*/ MOV R2, 0x1f0 ; /* 0x000001f000027802 */
/* 0x000fe40000000f00 */
/*01e0*/ CALL.REL.NOINC 0x240 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0210*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0003 */
/*0220*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ SHF.R.U32.HI R6, RZ, 0x17, R5.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011605 */
/*0250*/ BSSY B1, 0x8a0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0260*/ SHF.R.U32.HI R3, RZ, 0x17, R4.reuse ; /* 0x00000017ff037819 */
/* 0x100fe20000011604 */
/*0270*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0280*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*02a0*/ LOP3.LUT R3, R3, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff03037812 */
/* 0x000fe400078ec0ff */
/*02b0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*02c0*/ IADD3 R10, R3, -0x1, RZ ; /* 0xffffffff030a7810 */
/* 0x000fc40007ffe0ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*02e0*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*02f0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0300*/ @!P0 BRA 0x480 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0310*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*0320*/ FSETP.GTU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fc80003f3c200 */
/*0330*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0340*/ @P0 BRA 0x880 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0350*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0360*/ @!P0 BRA 0x860 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0380*/ FSETP.NEU.FTZ.AND P1, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f3d200 */
/*0390*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*03a0*/ @!P1 BRA !P2, 0x860 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03b0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*03c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03d0*/ @P1 BRA 0x840 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*03e0*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*03f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0400*/ @P0 BRA 0x810 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0410*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0420*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0430*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0440*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0450*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*0460*/ @!P1 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005089823 */
/* 0x000fe200000000ff */
/*0470*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LEA R5, R6, 0xc0800000, 0x17 ; /* 0xc080000006057811 */
/* 0x000fe200078eb8ff */
/*0490*/ BSSY B2, 0x800 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*04a0*/ IADD3 R4, R3, -0x7f, RZ ; /* 0xffffff8103047810 */
/* 0x000fc60007ffe0ff */
/*04b0*/ IMAD.IADD R5, R8, 0x1, -R5 ; /* 0x0000000108057824 */
/* 0x000fe200078e0a05 */
/*04c0*/ IADD3 R6, R4.reuse, 0x7f, -R6 ; /* 0x0000007f04067810 */
/* 0x040fe20007ffe806 */
/*04d0*/ IMAD R7, R4, -0x800000, R7 ; /* 0xff80000004077824 */
/* 0x000fe400078e0207 */
/*04e0*/ MUFU.RCP R8, R5 ; /* 0x0000000500087308 */
/* 0x000e220000001000 */
/*04f0*/ FADD.FTZ R10, -R5, -RZ ; /* 0x800000ff050a7221 */
/* 0x000fe40000010100 */
/*0500*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0510*/ FFMA R3, R8, R10, 1 ; /* 0x3f80000008037423 */
/* 0x001fc8000000000a */
/*0520*/ FFMA R12, R8, R3, R8 ; /* 0x00000003080c7223 */
/* 0x000fc80000000008 */
/*0530*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0540*/ FFMA R8, R10, R3, R7 ; /* 0x000000030a087223 */
/* 0x000fc80000000007 */
/*0550*/ FFMA R11, R12, R8, R3 ; /* 0x000000080c0b7223 */
/* 0x000fc80000000003 */
/*0560*/ FFMA R7, R10, R11, R7 ; /* 0x0000000b0a077223 */
/* 0x000fc80000000007 */
/*0570*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0580*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0590*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*05a0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*05b0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*05d0*/ @!P0 BRA 0x7e0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*05e0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*05f0*/ @P0 BRA 0x7b0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0610*/ @P0 BRA 0x7f0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0630*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0640*/ @!P0 BRA 0x7f0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0650*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0660*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0670*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0680*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0690*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*06a0*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*06b0*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*06c0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*06d0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*06e0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*06f0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0700*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0710*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0720*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0730*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0740*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0750*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0760*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0770*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0780*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0790*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*07a0*/ BRA 0x7f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*07c0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07d0*/ BRA 0x7f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*07e0*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*07f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0800*/ BRA 0x890 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0820*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0830*/ BRA 0x890 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0840*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0850*/ BRA 0x890 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0860*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0870*/ BRA 0x890 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0880*/ FADD.FTZ R3, R4, R5 ; /* 0x0000000504037221 */
/* 0x000fe40000010000 */
/*0890*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08a0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0003 */
/*08b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*08c0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff73002007950 */
/* 0x000fea0003c3ffff */
/*08d0*/ BRA 0x8d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13normalizationPiPfii
.globl _Z13normalizationPiPfii
.p2align 8
.type _Z13normalizationPiPfii,@function
_Z13normalizationPiPfii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_mul_i32 s14, s14, s2
s_add_i32 s2, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s2, s2, s2
v_mul_lo_u32 v1, v2, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, s14, v0, v1
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s0
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v2, v2
v_div_scale_f32 v4, null, v3, v3, v2
v_div_scale_f32 v7, vcc_lo, v2, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v2, v4, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13normalizationPiPfii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13normalizationPiPfii, .Lfunc_end0-_Z13normalizationPiPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13normalizationPiPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13normalizationPiPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ade15_00000000-6_normalization.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13normalizationPiPfiiPiPfii
.type _Z37__device_stub__Z13normalizationPiPfiiPiPfii, @function
_Z37__device_stub__Z13normalizationPiPfiiPiPfii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13normalizationPiPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13normalizationPiPfiiPiPfii, .-_Z37__device_stub__Z13normalizationPiPfiiPiPfii
.globl _Z13normalizationPiPfii
.type _Z13normalizationPiPfii, @function
_Z13normalizationPiPfii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13normalizationPiPfiiPiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13normalizationPiPfii, .-_Z13normalizationPiPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13normalizationPiPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13normalizationPiPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "normalization.hip"
.globl _Z28__device_stub__normalizationPiPfii # -- Begin function _Z28__device_stub__normalizationPiPfii
.p2align 4, 0x90
.type _Z28__device_stub__normalizationPiPfii,@function
_Z28__device_stub__normalizationPiPfii: # @_Z28__device_stub__normalizationPiPfii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13normalizationPiPfii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z28__device_stub__normalizationPiPfii, .Lfunc_end0-_Z28__device_stub__normalizationPiPfii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13normalizationPiPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13normalizationPiPfii,@object # @_Z13normalizationPiPfii
.section .rodata,"a",@progbits
.globl _Z13normalizationPiPfii
.p2align 3, 0x0
_Z13normalizationPiPfii:
.quad _Z28__device_stub__normalizationPiPfii
.size _Z13normalizationPiPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13normalizationPiPfii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__normalizationPiPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13normalizationPiPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Simulation overview:
1. Define the information contained within a point in space as a c++ struct.
2. Generate multiple copies of this point in a GPU array, each with unique parameters.
3. Calculate a quantity at each point due to the given parameters within a CUDA kernel.
4. Advance in time, and repeat.
*/
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
#include <cuda.h>
int numPoints = 4096, // number of points to generate (multiples of 32 are best)
maxSteps = 250000, // total iterations
saveSteps = 1000; // data will be written to file when current step % saveSteps = 0
__device__ __constant__ float dt = 0.0005, // Time step size.
A, k, w, c, dk;
const float pi = 3.14159265358979f;
const float plotBoundary = 4 * pi;
typedef struct
{
// Represents a point in space with its associated fields, as well
// as any information we wish to carry along with each point.
float x, y, // position data
psi; // wave height
} point;
// HOST FUNCTIONS //////////////////////////////////////////////////////////////////////////////////
//
// Get GPU debugging mesagges.
inline void check_cuda_errors( const char *filename, const int line_number )
{
#ifdef DEBUG
cudaThreadSynchronize();
cudaError_t error = cudaGetLastError();
if( error != cudaSuccess )
{
printf( "CUDA error at %s:%i: %s\n", filename, line_number, cudaGetErrorString( error ) );
exit( -1 );
}
#endif
}
// Get the current timestamp.
char *date_and_time()
{
time_t time_raw_format;
struct tm * ptr_time;
time ( &time_raw_format);
ptr_time = localtime ( &time_raw_format );
return asctime(ptr_time);
}
// Store simulation data into the directory specified by *path.
void writeDataToFile( char *path, point *p, int numPoints, float simTime, float plotLimit )
{
// Initialize data file and write common parameters:
FILE *file;
char filename[ strlen( path )+24 ];
sprintf( filename,"%s/%.16f.dat", path, simTime );
file = fopen( filename,"w" );
char sp[10] = " ";
fprintf( file,"# limit = %g\n#\n# x%s y%s psi\n", plotLimit, sp, sp);
// Write data to file:
for( int i = 0; i < numPoints; i++ )
{
fprintf( file,"% .4e % .4e % .4e\n",
p[i].x, p[i].y, p[i].psi );
}
fclose(file);
}
// Calculate constants used in device kernels.
void initializeDeviceConstants()
{
float a = 1,
lambda = 2 * pi,
K = 2 * pi / lambda,
hBar = 1 / ( 2 * pi ), // letting h = 1
m = 1,
W = 0.5 * hBar * K * K / m,
C = W / K,
DK = K / 8; // determines the "tightness" of the wave packet
cudaMemcpyToSymbol( A, &a, sizeof( float ) );
cudaMemcpyToSymbol( k, &K, sizeof( float ) );
cudaMemcpyToSymbol( w, &W, sizeof( float ) );
cudaMemcpyToSymbol( c, &C, sizeof( float ) );
cudaMemcpyToSymbol( dk, &DK, sizeof( float ) );
}
// Populate the point array on the host.
void initializePoints( point *p, int N )
{
// Define the boudaries of the point-space.
float dR = plotBoundary / sqrt( (float)N ),
dTheta = 2 * pi / sqrt( (float)N );
// Assign each point a specific location in space.
int i = 0;
for( float r = 0; r <= plotBoundary; r += dR )
{
for( float theta = 0; theta <= 2 * pi; theta += dTheta )
{
if( i > N )
continue;
p[i].x = r * cos( theta ); // position vector
p[i].y = r * sin( theta ); //
i++;
}
}
}
//
// END HOST FUNTIONS ///////////////////////////////////////////////////////////////////////////////
// DEVICE KERNELS //////////////////////////////////////////////////////////////////////////////////
//
__device__ int getGlobalIndex( void ) { return blockIdx.x * blockDim.x + threadIdx.x; }
__device__ float t = 0;
__device__ void updateTime() { t += dt; }
// Calcutate the new point values in time and space at each timestep.
__global__ void incrementPoint( point *p, int numPoints )
{
int i = getGlobalIndex();
float r = sqrt( p[i].x*p[i].x + p[i].y*p[i].y );
//p[i].psi = A * cos( k * r - w * t ); // simple circular wave
// Disbursive Wave Packet
// From A. C. Philips: Intro to Quantum Mechanics, problem 2.2 and fig. 2.1, with c = w/k.
float alpha = r - c * t;
p[i].psi = 2 * A * dk * sin( dk * alpha ) * cos( k * alpha ) / ( dk * alpha );
updateTime();
}
//
// END DEVICE KERNELS //////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[])
{
////////////////////////////////////////////////////////////////////////////////////////////////////
// SELECT DEVICE
// Get the number of CUDA enabled devices.
int deviceCount;
cudaGetDeviceCount( &deviceCount );
if( deviceCount < 1 )
{
printf( "No CUDA-capable devices were detected.\n" );
return 1;
}
// Get properties, select device, and display info.
int device, useDevice;
float computeCapability, cudaVersion = 0;
cudaDeviceProp deviceProp;
for( device = 0; device < deviceCount; device++ )
{
// Display info for each device.
cudaGetDeviceProperties( &deviceProp, device );
computeCapability = deviceProp.major + deviceProp.minor * 0.1;
// Select the device with the greatest compute capability. If multiple devices
// with this capability are found, the first encountered will be used.
if( computeCapability > cudaVersion )
{
cudaVersion = computeCapability;
useDevice = device;
}
}
device = useDevice;
cudaGetDevice(&device);
cudaGetDeviceProperties( &deviceProp, device );
printf( "# Using %s, device number: %d, compute capability: %g.\n",
deviceProp.name, device, cudaVersion );
// Check for kernel timeout.
if( deviceProp.kernelExecTimeoutEnabled == 1 )
{
printf( "#\n" );
printf( "# Warning: Timeout enabled. Using this device without a display \n" );
printf( "# may lift kernel timeout restrictions.\n" );
}
// END SELECT DEVICE
////////////////////////////////////////////////////////////////////////////////////////////////////
// Allocate memory:
int threadsPerBlock = ( deviceProp.major >= 2 ? 512 : 256 ),
numBlocks = ceil( (float)numPoints / (float)threadsPerBlock ),
numBytes = numPoints * sizeof( point );
point *cpuPointArray, *gpuPointArray;
cpuPointArray = (point*)malloc( numBytes );
cudaMalloc( (void**)&gpuPointArray, numBytes );
check_cuda_errors( __FILE__, __LINE__ );
////////////////////////////////////////////////////////////////////////////////////////////////////
// BEGIN SIMULATION
// Begin simulation:
for( int s = 0; s < maxSteps; s++ )
{
// Perform setup tasks before the first iteration.
if( s == 0 )
{
// Initialize point array and device constants.
srand( time( NULL ) );
initializePoints( cpuPointArray, numPoints );
initializeDeviceConstants();
cudaMemcpy( gpuPointArray, cpuPointArray, numBytes, cudaMemcpyHostToDevice );
// Write simulation info to stdout.
float stepSize;
cudaMemcpyFromSymbol( &stepSize, dt, sizeof(float) );
printf( "#\n#\n" );
printf( "# Started %s#\n# numPoints = %d\n# maxSteps = %d\n# dt = %g\n#\n",
date_and_time(), numPoints, maxSteps, stepSize );
printf( "# Steps | Seconds | Sim. Time\n# ------------------------------\n" );
check_cuda_errors(__FILE__, __LINE__);
}
// Execute portion of simulation on GPU:
incrementPoint<<<numBlocks,threadsPerBlock>>>( gpuPointArray, numPoints );
// Retrieve results:
float simTime;
cudaMemcpyFromSymbol( &simTime, t, sizeof( float ) );
cudaMemcpy( cpuPointArray, gpuPointArray, numBytes, cudaMemcpyDeviceToHost );
// Output data every [saveSteps] steps.
if( s % saveSteps == 0 )
{
// Write to file if save paths specified in argument to main().
if( argc > 1 )
writeDataToFile( argv[1], cpuPointArray, numPoints, simTime, plotBoundary );
// Print data to stdout.
printf( "%.4e %.4e %.4e\n", (float)s, (float)( clock() / CLOCKS_PER_SEC ), simTime );
}
}
// END SIMULATION
////////////////////////////////////////////////////////////////////////////////////////////////////
// Deallocate memory and exit.
free( cpuPointArray );
cudaFree( gpuPointArray );
check_cuda_errors( __FILE__, __LINE__ );
printf( "\n# Completed %s", date_and_time() );
return 0;
} // end main | .file "tmpxft_000f80ac_00000000-6_nPoint.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13date_and_timev
.type _Z13date_and_timev, @function
_Z13date_and_timev:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movq %rbx, %rdi
call time@PLT
movq %rbx, %rdi
call localtime@PLT
movq %rax, %rdi
call asctime@PLT
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z13date_and_timev, .-_Z13date_and_timev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s/%.16f.dat"
.LC1:
.string "w"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "# limit = %g\n#\n# x%s y%s psi\n"
.section .rodata.str1.1
.LC3:
.string "% .4e % .4e % .4e\n"
.text
.globl _Z15writeDataToFilePcP5pointiff
.type _Z15writeDataToFilePcP5pointiff, @function
_Z15writeDataToFilePcP5pointiff:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $48, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %rdi, %rbx
movq %rsi, %r14
movl %edx, %r13d
movss %xmm0, -68(%rbp)
movss %xmm1, -72(%rbp)
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
call strlen@PLT
leaq 24(%rax), %rsi
addq $39, %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L8:
cmpq %rdx, %rsp
je .L9
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L8
.L9:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L10
orq $0, -8(%rsp,%rax)
.L10:
pxor %xmm0, %xmm0
cvtss2sd -68(%rbp), %xmm0
movq %rbx, %r8
leaq .LC0(%rip), %rcx
movq %rsi, %rdx
movl $2, %esi
movq %rsp, %rdi
movl $1, %eax
call __sprintf_chk@PLT
leaq .LC1(%rip), %rsi
movq %rsp, %rdi
call fopen@PLT
movq %rax, %r12
movabsq $2314885530818453536, %rax
movq %rax, -50(%rbp)
movw $32, -42(%rbp)
leaq -50(%rbp), %rcx
pxor %xmm0, %xmm0
cvtss2sd -72(%rbp), %xmm0
movq %rcx, %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq %r12, %rdi
movl $1, %eax
call __fprintf_chk@PLT
testl %r13d, %r13d
jle .L11
movq %r14, %rbx
movslq %r13d, %r13
leaq 0(%r13,%r13,2), %rax
leaq (%r14,%rax,4), %r14
leaq .LC3(%rip), %r13
.L12:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
pxor %xmm2, %xmm2
cvtss2sd 8(%rbx), %xmm2
pxor %xmm1, %xmm1
cvtss2sd 4(%rbx), %xmm1
movq %r13, %rdx
movl $2, %esi
movq %r12, %rdi
movl $3, %eax
call __fprintf_chk@PLT
addq $12, %rbx
cmpq %r14, %rbx
jne .L12
.L11:
movq %r12, %rdi
call fclose@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L16
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z15writeDataToFilePcP5pointiff, .-_Z15writeDataToFilePcP5pointiff
.globl _Z25initializeDeviceConstantsv
.type _Z25initializeDeviceConstantsv, @function
_Z25initializeDeviceConstantsv:
.LFB2060:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movss .LC4(%rip), %xmm0
movss %xmm0, 4(%rsp)
movss %xmm0, 8(%rsp)
movss .LC5(%rip), %xmm0
movss %xmm0, 12(%rsp)
movss %xmm0, 16(%rsp)
movl $0x3e000000, 20(%rsp)
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1A(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 8(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1k(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 12(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1w(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 16(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1c(%rip), %rdi
call cudaMemcpyToSymbol@PLT
leaq 20(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL2dk(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z25initializeDeviceConstantsv, .-_Z25initializeDeviceConstantsv
.globl _Z16initializePointsP5pointi
.type _Z16initializePointsP5pointi, @function
_Z16initializePointsP5pointi:
.LFB2061:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebp
pxor %xmm7, %xmm7
cvtsi2ssl %esi, %xmm7
movss %xmm7, 8(%rsp)
pxor %xmm0, %xmm0
ucomiss %xmm7, %xmm0
ja .L32
sqrtss %xmm7, %xmm7
movaps %xmm7, %xmm0
movss .LC8(%rip), %xmm1
divss %xmm7, %xmm1
movss %xmm1, 20(%rsp)
.L24:
movss .LC9(%rip), %xmm1
divss %xmm0, %xmm1
movss %xmm1, 12(%rsp)
movl $0x00000000, 16(%rsp)
movl $0, %ebx
leaq 28(%rsp), %r14
leaq 24(%rsp), %r13
jmp .L25
.L32:
movss 8(%rsp), %xmm0
call sqrtf@PLT
movss .LC8(%rip), %xmm1
divss %xmm0, %xmm1
movss %xmm1, 20(%rsp)
movss 8(%rsp), %xmm0
call sqrtf@PLT
jmp .L24
.L36:
movq %r13, %rsi
movq %r14, %rdi
movss 8(%rsp), %xmm0
call sincosf@PLT
movslq %ebx, %rax
leaq (%rax,%rax,2), %rax
leaq (%r12,%rax,4), %rax
movss 16(%rsp), %xmm3
movaps %xmm3, %xmm0
mulss 24(%rsp), %xmm0
movss %xmm0, (%rax)
mulss 28(%rsp), %xmm3
movss %xmm3, 4(%rax)
addl $1, %ebx
.L26:
movss 8(%rsp), %xmm2
addss 12(%rsp), %xmm2
movss %xmm2, 8(%rsp)
movss .LC9(%rip), %xmm5
comiss %xmm2, %xmm5
jb .L35
.L27:
cmpl %ebx, %ebp
jge .L36
jmp .L26
.L35:
movss 16(%rsp), %xmm6
addss 20(%rsp), %xmm6
movss %xmm6, 16(%rsp)
movss .LC8(%rip), %xmm1
comiss %xmm6, %xmm1
jb .L33
.L25:
movl $0x00000000, 8(%rsp)
jmp .L27
.L33:
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z16initializePointsP5pointi, .-_Z16initializePointsP5pointi
.globl _Z14getGlobalIndexv
.type _Z14getGlobalIndexv, @function
_Z14getGlobalIndexv:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z14getGlobalIndexv, .-_Z14getGlobalIndexv
.globl _Z10updateTimev
.type _Z10updateTimev, @function
_Z10updateTimev:
.LFB2063:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2063:
.size _Z10updateTimev, .-_Z10updateTimev
.globl _Z40__device_stub__Z14incrementPointP5pointiP5pointi
.type _Z40__device_stub__Z14incrementPointP5pointiP5pointi, @function
_Z40__device_stub__Z14incrementPointP5pointiP5pointi:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14incrementPointP5pointi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z40__device_stub__Z14incrementPointP5pointiP5pointi, .-_Z40__device_stub__Z14incrementPointP5pointiP5pointi
.globl _Z14incrementPointP5pointi
.type _Z14incrementPointP5pointi, @function
_Z14incrementPointP5pointi:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14incrementPointP5pointiP5pointi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z14incrementPointP5pointi, .-_Z14incrementPointP5pointi
.section .rodata.str1.8
.align 8
.LC10:
.string "No CUDA-capable devices were detected.\n"
.align 8
.LC12:
.string "# Using %s, device number: %d, compute capability: %g.\n"
.section .rodata.str1.1
.LC13:
.string "#\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "# Warning: Timeout enabled. Using this device without a display \n"
.align 8
.LC15:
.string "# may lift kernel timeout restrictions.\n"
.section .rodata.str1.1
.LC18:
.string "#\n#\n"
.section .rodata.str1.8
.align 8
.LC19:
.string "# Started %s#\n# numPoints = %d\n# maxSteps = %d\n# dt = %g\n#\n"
.align 8
.LC20:
.string "# Steps | Seconds | Sim. Time\n# ------------------------------\n"
.section .rodata.str1.1
.LC21:
.string "%.4e %.4e %.4e\n"
.LC22:
.string "\n# Completed %s"
.text
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1128, %rsp
.cfi_def_cfa_offset 1184
movl %edi, 20(%rsp)
movq %rsi, 24(%rsp)
movq %fs:40, %rax
movq %rax, 1112(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 40(%rsp)
jle .L70
movl $0, 44(%rsp)
movl $0x00000000, (%rsp)
movl $0, %esi
jmp .L54
.L70:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L49
.L52:
movl 44(%rsp), %eax
leal 1(%rax), %esi
movl %esi, 44(%rsp)
cmpl 40(%rsp), %esi
jge .L71
.L54:
leaq 80(%rsp), %rdi
call cudaGetDeviceProperties_v2@PLT
pxor %xmm0, %xmm0
cvtsi2sdl 444(%rsp), %xmm0
mulsd .LC11(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl 440(%rsp), %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
comiss (%rsp), %xmm0
jbe .L52
movl 44(%rsp), %ebx
movss %xmm0, (%rsp)
jmp .L52
.L71:
movl %ebx, 44(%rsp)
leaq 44(%rsp), %rdi
call cudaGetDevice@PLT
leaq 80(%rsp), %rbx
movl 44(%rsp), %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
movl 44(%rsp), %ecx
movq %rbx, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
cmpl $1, 472(%rsp)
je .L72
.L55:
cmpl $2, 440(%rsp)
movl $256, %edx
movl $512, %eax
cmovl %edx, %eax
movl %eax, %r13d
movl numPoints(%rip), %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %r13d, %xmm1
divss %xmm1, %xmm0
movaps %xmm0, %xmm3
movss .LC23(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC16(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L57
cvttss2sil %xmm0, %edx
pxor %xmm1, %xmm1
cvtsi2ssl %edx, %xmm1
cmpnless %xmm1, %xmm3
movss .LC4(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L57:
cvttss2sil %xmm3, %r14d
leal (%rax,%rax,2), %r12d
sall $2, %r12d
movslq %r12d, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
cmpl $0, maxSteps(%rip)
jle .L58
movl $0, %ebx
leaq 68(%rsp), %r15
movq %r15, %rax
movq %r12, %r15
movl %r13d, %r12d
movq %rax, %r13
jmp .L63
.L72:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L55
.L73:
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl numPoints(%rip), %esi
movq %rbp, %rdi
call _Z16initializePointsP5pointi
call _Z25initializeDeviceConstantsv
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL2dt(%rip), %rsi
movq %r13, %rdi
call cudaMemcpyFromSymbol@PLT
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm7, %xmm7
cvtss2sd 68(%rsp), %xmm7
movsd %xmm7, (%rsp)
movl maxSteps(%rip), %eax
movl %eax, 12(%rsp)
movl numPoints(%rip), %ecx
movl %ecx, 16(%rsp)
call _Z13date_and_timev
movq %rax, %rdx
movsd (%rsp), %xmm0
movl 12(%rsp), %r8d
movl 16(%rsp), %ecx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L59
.L74:
movl numPoints(%rip), %esi
movq 48(%rsp), %rdi
call _Z40__device_stub__Z14incrementPointP5pointiP5pointi
jmp .L60
.L62:
pxor %xmm6, %xmm6
cvtss2sd 68(%rsp), %xmm6
movsd %xmm6, (%rsp)
call clock@PLT
movq %rax, %rcx
movabsq $4835703278458516699, %rdx
imulq %rdx
sarq $18, %rdx
sarq $63, %rcx
subq %rcx, %rdx
pxor %xmm1, %xmm1
cvtsi2ssq %rdx, %xmm1
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
cvtss2sd %xmm0, %xmm0
movsd (%rsp), %xmm2
cvtss2sd %xmm1, %xmm1
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
.L61:
addl $1, %ebx
cmpl %ebx, maxSteps(%rip)
jle .L58
.L63:
testl %ebx, %ebx
je .L73
.L59:
movl %r12d, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %r14d, 56(%rsp)
movl $1, 60(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L74
.L60:
movl $2, %r8d
movl $0, %ecx
movl $4, %edx
leaq _ZL1t(%rip), %rsi
movq %r13, %rdi
call cudaMemcpyFromSymbol@PLT
movl $2, %ecx
movq %r15, %rdx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %ebx, %eax
cltd
idivl saveSteps(%rip)
testl %edx, %edx
jne .L61
cmpl $1, 20(%rsp)
jle .L62
movq 24(%rsp), %rax
movq 8(%rax), %rdi
movss .LC8(%rip), %xmm1
movss 68(%rsp), %xmm0
movl numPoints(%rip), %edx
movq %rbp, %rsi
call _Z15writeDataToFilePcP5pointiff
jmp .L62
.L58:
movq %rbp, %rdi
call free@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
call _Z13date_and_timev
movq %rax, %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
.L49:
movq 1112(%rsp), %rdx
subq %fs:40, %rdx
jne .L75
addq $1128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.1
.LC24:
.string "_Z14incrementPointP5pointi"
.LC25:
.string "dt"
.LC26:
.string "A"
.LC27:
.string "k"
.LC28:
.string "c"
.LC29:
.string "dk"
.LC30:
.string "t"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z14incrementPointP5pointi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC25(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2dt(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC26(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1A(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1k(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1w(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC28(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1c(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2dk(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1t(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1t
.comm _ZL1t,4,4
.local _ZL2dk
.comm _ZL2dk,4,4
.local _ZL1c
.comm _ZL1c,4,4
.local _ZL1w
.comm _ZL1w,4,4
.local _ZL1k
.comm _ZL1k,4,4
.local _ZL1A
.comm _ZL1A,4,4
.local _ZL2dt
.comm _ZL2dt,4,4
.globl saveSteps
.data
.align 4
.type saveSteps, @object
.size saveSteps, 4
saveSteps:
.long 1000
.globl maxSteps
.align 4
.type maxSteps, @object
.size maxSteps, 4
maxSteps:
.long 250000
.globl numPoints
.align 4
.type numPoints, @object
.size numPoints, 4
numPoints:
.long 4096
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1065353216
.align 4
.LC5:
.long 1034090883
.align 4
.LC8:
.long 1095307227
.align 4
.LC9:
.long 1086918619
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC11:
.long -1717986918
.long 1069128089
.section .rodata.cst4
.align 4
.LC16:
.long 1258291200
.align 4
.LC23:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Simulation overview:
1. Define the information contained within a point in space as a c++ struct.
2. Generate multiple copies of this point in a GPU array, each with unique parameters.
3. Calculate a quantity at each point due to the given parameters within a CUDA kernel.
4. Advance in time, and repeat.
*/
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
#include <cuda.h>
int numPoints = 4096, // number of points to generate (multiples of 32 are best)
maxSteps = 250000, // total iterations
saveSteps = 1000; // data will be written to file when current step % saveSteps = 0
__device__ __constant__ float dt = 0.0005, // Time step size.
A, k, w, c, dk;
const float pi = 3.14159265358979f;
const float plotBoundary = 4 * pi;
typedef struct
{
// Represents a point in space with its associated fields, as well
// as any information we wish to carry along with each point.
float x, y, // position data
psi; // wave height
} point;
// HOST FUNCTIONS //////////////////////////////////////////////////////////////////////////////////
//
// Get GPU debugging mesagges.
inline void check_cuda_errors( const char *filename, const int line_number )
{
#ifdef DEBUG
cudaThreadSynchronize();
cudaError_t error = cudaGetLastError();
if( error != cudaSuccess )
{
printf( "CUDA error at %s:%i: %s\n", filename, line_number, cudaGetErrorString( error ) );
exit( -1 );
}
#endif
}
// Get the current timestamp.
char *date_and_time()
{
time_t time_raw_format;
struct tm * ptr_time;
time ( &time_raw_format);
ptr_time = localtime ( &time_raw_format );
return asctime(ptr_time);
}
// Store simulation data into the directory specified by *path.
void writeDataToFile( char *path, point *p, int numPoints, float simTime, float plotLimit )
{
// Initialize data file and write common parameters:
FILE *file;
char filename[ strlen( path )+24 ];
sprintf( filename,"%s/%.16f.dat", path, simTime );
file = fopen( filename,"w" );
char sp[10] = " ";
fprintf( file,"# limit = %g\n#\n# x%s y%s psi\n", plotLimit, sp, sp);
// Write data to file:
for( int i = 0; i < numPoints; i++ )
{
fprintf( file,"% .4e % .4e % .4e\n",
p[i].x, p[i].y, p[i].psi );
}
fclose(file);
}
// Calculate constants used in device kernels.
void initializeDeviceConstants()
{
float a = 1,
lambda = 2 * pi,
K = 2 * pi / lambda,
hBar = 1 / ( 2 * pi ), // letting h = 1
m = 1,
W = 0.5 * hBar * K * K / m,
C = W / K,
DK = K / 8; // determines the "tightness" of the wave packet
cudaMemcpyToSymbol( A, &a, sizeof( float ) );
cudaMemcpyToSymbol( k, &K, sizeof( float ) );
cudaMemcpyToSymbol( w, &W, sizeof( float ) );
cudaMemcpyToSymbol( c, &C, sizeof( float ) );
cudaMemcpyToSymbol( dk, &DK, sizeof( float ) );
}
// Populate the point array on the host.
void initializePoints( point *p, int N )
{
// Define the boudaries of the point-space.
float dR = plotBoundary / sqrt( (float)N ),
dTheta = 2 * pi / sqrt( (float)N );
// Assign each point a specific location in space.
int i = 0;
for( float r = 0; r <= plotBoundary; r += dR )
{
for( float theta = 0; theta <= 2 * pi; theta += dTheta )
{
if( i > N )
continue;
p[i].x = r * cos( theta ); // position vector
p[i].y = r * sin( theta ); //
i++;
}
}
}
//
// END HOST FUNTIONS ///////////////////////////////////////////////////////////////////////////////
// DEVICE KERNELS //////////////////////////////////////////////////////////////////////////////////
//
__device__ int getGlobalIndex( void ) { return blockIdx.x * blockDim.x + threadIdx.x; }
__device__ float t = 0;
__device__ void updateTime() { t += dt; }
// Calcutate the new point values in time and space at each timestep.
__global__ void incrementPoint( point *p, int numPoints )
{
int i = getGlobalIndex();
float r = sqrt( p[i].x*p[i].x + p[i].y*p[i].y );
//p[i].psi = A * cos( k * r - w * t ); // simple circular wave
// Disbursive Wave Packet
// From A. C. Philips: Intro to Quantum Mechanics, problem 2.2 and fig. 2.1, with c = w/k.
float alpha = r - c * t;
p[i].psi = 2 * A * dk * sin( dk * alpha ) * cos( k * alpha ) / ( dk * alpha );
updateTime();
}
//
// END DEVICE KERNELS //////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[])
{
////////////////////////////////////////////////////////////////////////////////////////////////////
// SELECT DEVICE
// Get the number of CUDA enabled devices.
int deviceCount;
cudaGetDeviceCount( &deviceCount );
if( deviceCount < 1 )
{
printf( "No CUDA-capable devices were detected.\n" );
return 1;
}
// Get properties, select device, and display info.
int device, useDevice;
float computeCapability, cudaVersion = 0;
cudaDeviceProp deviceProp;
for( device = 0; device < deviceCount; device++ )
{
// Display info for each device.
cudaGetDeviceProperties( &deviceProp, device );
computeCapability = deviceProp.major + deviceProp.minor * 0.1;
// Select the device with the greatest compute capability. If multiple devices
// with this capability are found, the first encountered will be used.
if( computeCapability > cudaVersion )
{
cudaVersion = computeCapability;
useDevice = device;
}
}
device = useDevice;
cudaGetDevice(&device);
cudaGetDeviceProperties( &deviceProp, device );
printf( "# Using %s, device number: %d, compute capability: %g.\n",
deviceProp.name, device, cudaVersion );
// Check for kernel timeout.
if( deviceProp.kernelExecTimeoutEnabled == 1 )
{
printf( "#\n" );
printf( "# Warning: Timeout enabled. Using this device without a display \n" );
printf( "# may lift kernel timeout restrictions.\n" );
}
// END SELECT DEVICE
////////////////////////////////////////////////////////////////////////////////////////////////////
// Allocate memory:
int threadsPerBlock = ( deviceProp.major >= 2 ? 512 : 256 ),
numBlocks = ceil( (float)numPoints / (float)threadsPerBlock ),
numBytes = numPoints * sizeof( point );
point *cpuPointArray, *gpuPointArray;
cpuPointArray = (point*)malloc( numBytes );
cudaMalloc( (void**)&gpuPointArray, numBytes );
check_cuda_errors( __FILE__, __LINE__ );
////////////////////////////////////////////////////////////////////////////////////////////////////
// BEGIN SIMULATION
// Begin simulation:
for( int s = 0; s < maxSteps; s++ )
{
// Perform setup tasks before the first iteration.
if( s == 0 )
{
// Initialize point array and device constants.
srand( time( NULL ) );
initializePoints( cpuPointArray, numPoints );
initializeDeviceConstants();
cudaMemcpy( gpuPointArray, cpuPointArray, numBytes, cudaMemcpyHostToDevice );
// Write simulation info to stdout.
float stepSize;
cudaMemcpyFromSymbol( &stepSize, dt, sizeof(float) );
printf( "#\n#\n" );
printf( "# Started %s#\n# numPoints = %d\n# maxSteps = %d\n# dt = %g\n#\n",
date_and_time(), numPoints, maxSteps, stepSize );
printf( "# Steps | Seconds | Sim. Time\n# ------------------------------\n" );
check_cuda_errors(__FILE__, __LINE__);
}
// Execute portion of simulation on GPU:
incrementPoint<<<numBlocks,threadsPerBlock>>>( gpuPointArray, numPoints );
// Retrieve results:
float simTime;
cudaMemcpyFromSymbol( &simTime, t, sizeof( float ) );
cudaMemcpy( cpuPointArray, gpuPointArray, numBytes, cudaMemcpyDeviceToHost );
// Output data every [saveSteps] steps.
if( s % saveSteps == 0 )
{
// Write to file if save paths specified in argument to main().
if( argc > 1 )
writeDataToFile( argv[1], cpuPointArray, numPoints, simTime, plotBoundary );
// Print data to stdout.
printf( "%.4e %.4e %.4e\n", (float)s, (float)( clock() / CLOCKS_PER_SEC ), simTime );
}
}
// END SIMULATION
////////////////////////////////////////////////////////////////////////////////////////////////////
// Deallocate memory and exit.
free( cpuPointArray );
cudaFree( gpuPointArray );
check_cuda_errors( __FILE__, __LINE__ );
printf( "\n# Completed %s", date_and_time() );
return 0;
} // end main | /* Simulation overview:
1. Define the information contained within a point in space as a c++ struct.
2. Generate multiple copies of this point in a GPU array, each with unique parameters.
3. Calculate a quantity at each point due to the given parameters within a CUDA kernel.
4. Advance in time, and repeat.
*/
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
#include <hip/hip_runtime.h>
int numPoints = 4096, // number of points to generate (multiples of 32 are best)
maxSteps = 250000, // total iterations
saveSteps = 1000; // data will be written to file when current step % saveSteps = 0
__device__ __constant__ float dt = 0.0005, // Time step size.
A, k, w, c, dk;
const float pi = 3.14159265358979f;
const float plotBoundary = 4 * pi;
typedef struct
{
// Represents a point in space with its associated fields, as well
// as any information we wish to carry along with each point.
float x, y, // position data
psi; // wave height
} point;
// HOST FUNCTIONS //////////////////////////////////////////////////////////////////////////////////
//
// Get GPU debugging mesagges.
inline void check_cuda_errors( const char *filename, const int line_number )
{
#ifdef DEBUG
hipDeviceSynchronize();
hipError_t error = hipGetLastError();
if( error != hipSuccess )
{
printf( "CUDA error at %s:%i: %s\n", filename, line_number, hipGetErrorString( error ) );
exit( -1 );
}
#endif
}
// Get the current timestamp.
char *date_and_time()
{
time_t time_raw_format;
struct tm * ptr_time;
time ( &time_raw_format);
ptr_time = localtime ( &time_raw_format );
return asctime(ptr_time);
}
// Store simulation data into the directory specified by *path.
void writeDataToFile( char *path, point *p, int numPoints, float simTime, float plotLimit )
{
// Initialize data file and write common parameters:
FILE *file;
char filename[ strlen( path )+24 ];
sprintf( filename,"%s/%.16f.dat", path, simTime );
file = fopen( filename,"w" );
char sp[10] = " ";
fprintf( file,"# limit = %g\n#\n# x%s y%s psi\n", plotLimit, sp, sp);
// Write data to file:
for( int i = 0; i < numPoints; i++ )
{
fprintf( file,"% .4e % .4e % .4e\n",
p[i].x, p[i].y, p[i].psi );
}
fclose(file);
}
// Calculate constants used in device kernels.
void initializeDeviceConstants()
{
float a = 1,
lambda = 2 * pi,
K = 2 * pi / lambda,
hBar = 1 / ( 2 * pi ), // letting h = 1
m = 1,
W = 0.5 * hBar * K * K / m,
C = W / K,
DK = K / 8; // determines the "tightness" of the wave packet
hipMemcpyToSymbol( HIP_SYMBOL(A), &a, sizeof( float ) );
hipMemcpyToSymbol( HIP_SYMBOL(k), &K, sizeof( float ) );
hipMemcpyToSymbol( HIP_SYMBOL(w), &W, sizeof( float ) );
hipMemcpyToSymbol( HIP_SYMBOL(c), &C, sizeof( float ) );
hipMemcpyToSymbol( HIP_SYMBOL(dk), &DK, sizeof( float ) );
}
// Populate the point array on the host.
void initializePoints( point *p, int N )
{
// Define the boudaries of the point-space.
float dR = plotBoundary / sqrt( (float)N ),
dTheta = 2 * pi / sqrt( (float)N );
// Assign each point a specific location in space.
int i = 0;
for( float r = 0; r <= plotBoundary; r += dR )
{
for( float theta = 0; theta <= 2 * pi; theta += dTheta )
{
if( i > N )
continue;
p[i].x = r * cos( theta ); // position vector
p[i].y = r * sin( theta ); //
i++;
}
}
}
//
// END HOST FUNTIONS ///////////////////////////////////////////////////////////////////////////////
// DEVICE KERNELS //////////////////////////////////////////////////////////////////////////////////
//
__device__ int getGlobalIndex( void ) { return blockIdx.x * blockDim.x + threadIdx.x; }
__device__ float t = 0;
__device__ void updateTime() { t += dt; }
// Calcutate the new point values in time and space at each timestep.
__global__ void incrementPoint( point *p, int numPoints )
{
int i = getGlobalIndex();
float r = sqrt( p[i].x*p[i].x + p[i].y*p[i].y );
//p[i].psi = A * cos( k * r - w * t ); // simple circular wave
// Disbursive Wave Packet
// From A. C. Philips: Intro to Quantum Mechanics, problem 2.2 and fig. 2.1, with c = w/k.
float alpha = r - c * t;
p[i].psi = 2 * A * dk * sin( dk * alpha ) * cos( k * alpha ) / ( dk * alpha );
updateTime();
}
//
// END DEVICE KERNELS //////////////////////////////////////////////////////////////////////////////
int main(int argc, char *argv[])
{
////////////////////////////////////////////////////////////////////////////////////////////////////
// SELECT DEVICE
// Get the number of CUDA enabled devices.
int deviceCount;
hipGetDeviceCount( &deviceCount );
if( deviceCount < 1 )
{
printf( "No CUDA-capable devices were detected.\n" );
return 1;
}
// Get properties, select device, and display info.
int device, useDevice;
float computeCapability, cudaVersion = 0;
hipDeviceProp_t deviceProp;
for( device = 0; device < deviceCount; device++ )
{
// Display info for each device.
hipGetDeviceProperties( &deviceProp, device );
computeCapability = deviceProp.major + deviceProp.minor * 0.1;
// Select the device with the greatest compute capability. If multiple devices
// with this capability are found, the first encountered will be used.
if( computeCapability > cudaVersion )
{
cudaVersion = computeCapability;
useDevice = device;
}
}
device = useDevice;
hipGetDevice(&device);
hipGetDeviceProperties( &deviceProp, device );
printf( "# Using %s, device number: %d, compute capability: %g.\n",
deviceProp.name, device, cudaVersion );
// Check for kernel timeout.
if( deviceProp.kernelExecTimeoutEnabled == 1 )
{
printf( "#\n" );
printf( "# Warning: Timeout enabled. Using this device without a display \n" );
printf( "# may lift kernel timeout restrictions.\n" );
}
// END SELECT DEVICE
////////////////////////////////////////////////////////////////////////////////////////////////////
// Allocate memory:
int threadsPerBlock = ( deviceProp.major >= 2 ? 512 : 256 ),
numBlocks = ceil( (float)numPoints / (float)threadsPerBlock ),
numBytes = numPoints * sizeof( point );
point *cpuPointArray, *gpuPointArray;
cpuPointArray = (point*)malloc( numBytes );
hipMalloc( (void**)&gpuPointArray, numBytes );
check_cuda_errors( __FILE__, __LINE__ );
////////////////////////////////////////////////////////////////////////////////////////////////////
// BEGIN SIMULATION
// Begin simulation:
for( int s = 0; s < maxSteps; s++ )
{
// Perform setup tasks before the first iteration.
if( s == 0 )
{
// Initialize point array and device constants.
srand( time( NULL ) );
initializePoints( cpuPointArray, numPoints );
initializeDeviceConstants();
hipMemcpy( gpuPointArray, cpuPointArray, numBytes, hipMemcpyHostToDevice );
// Write simulation info to stdout.
float stepSize;
hipMemcpyFromSymbol( &stepSize, HIP_SYMBOL(dt), sizeof(float) );
printf( "#\n#\n" );
printf( "# Started %s#\n# numPoints = %d\n# maxSteps = %d\n# dt = %g\n#\n",
date_and_time(), numPoints, maxSteps, stepSize );
printf( "# Steps | Seconds | Sim. Time\n# ------------------------------\n" );
check_cuda_errors(__FILE__, __LINE__);
}
// Execute portion of simulation on GPU:
incrementPoint<<<numBlocks,threadsPerBlock>>>( gpuPointArray, numPoints );
// Retrieve results:
float simTime;
hipMemcpyFromSymbol( &simTime, HIP_SYMBOL(t), sizeof( float ) );
hipMemcpy( cpuPointArray, gpuPointArray, numBytes, hipMemcpyDeviceToHost );
// Output data every [saveSteps] steps.
if( s % saveSteps == 0 )
{
// Write to file if save paths specified in argument to main().
if( argc > 1 )
writeDataToFile( argv[1], cpuPointArray, numPoints, simTime, plotBoundary );
// Print data to stdout.
printf( "%.4e %.4e %.4e\n", (float)s, (float)( clock() / CLOCKS_PER_SEC ), simTime );
}
}
// END SIMULATION
////////////////////////////////////////////////////////////////////////////////////////////////////
// Deallocate memory and exit.
free( cpuPointArray );
hipFree( gpuPointArray );
check_cuda_errors( __FILE__, __LINE__ );
printf( "\n# Completed %s", date_and_time() );
return 0;
} // end main |
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