system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_CYCLEPARITY_H
#define AXONBITS_CYCLEPARITY_H
/**
* All threads working on a cycle have the same cycle parity. This parity is used to identify the activity variable
* in the neuron that is to be updated (the next activity) versus the one that must be used ... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_CYCLEPARITY_H
#define AXONBITS_CYCLEPARITY_H
/**
* All threads working on a cycle have the same cycle parity. This parity is used to identify the activity variable
* in the neuron that is to be updated (the next activity) versus the one that must be used ... | .file "tmpxft_0003dc45_00000000-6_CycleParity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_CYCLEPARITY_H
#define AXONBITS_CYCLEPARITY_H
/**
* All threads working on a cycle have the same cycle parity. This parity is used to identify the activity variable
* in the neuron that is to be updated (the next activity) versus the one that must be used ... | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_CYCLEPARITY_H
#define AXONBITS_CYCLEPARITY_H
/**
* All threads working on a cycle have the same cycle parity. This parity is used to identify the activity variable
* in the neuron that is to be updated (the next activity) versus the one that must be used ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_CYCLEPARITY_H
#define AXONBITS_CYCLEPARITY_H
/**
* All threads working on a cycle have the same cycle parity. This parity is used to identify the activity variable
* in the neuron that is to be updated (the next activity) versus the one that must be used ... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by Peter Rigole on 2019-04-26.
//
#ifndef AXONBITS_CYCLEPARITY_H
#define AXONBITS_CYCLEPARITY_H
/**
* All threads working on a cycle have the same cycle parity. This parity is used to identify the activity variable
* in the neuron that is to be updated (the next activity) versus the one that must be used ... | .text
.file "CycleParity.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-proj... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003dc45_00000000-6_CycleParity.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "CycleParity.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-proj... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Multiply two matrices A * B = C
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define WA 3 // Matrix A width
#define HA 3 // Matrix A height
#define WB 3 // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Allocates a matrix with random ... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Multiply two matrices A * B = C
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define WA 3 // Matrix A width
#define HA 3 // Matrix A height
#define WB 3 // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Allocates a matrix with random ... | .file "tmpxft_00143dae_00000000-6_matrixMultOnHost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Multiply two matrices A * B = C
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define WA 3 // Matrix A width
#define HA 3 // Matrix A height
#define WB 3 // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Allocates a matrix with random ... | // Multiply two matrices A * B = C
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define WA 3 // Matrix A width
#define HA 3 // Matrix A height
#define WB 3 // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Al... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Multiply two matrices A * B = C
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define WA 3 // Matrix A width
#define HA 3 // Matrix A height
#define WB 3 // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Al... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Multiply two matrices A * B = C
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define WA 3 // Matrix A width
#define HA 3 // Matrix A height
#define WB 3 // Matrix B width
#define HB WA // Matrix B height
#define WC WB // Matrix C width
#define HC HA // Matrix C height
// Al... | .text
.file "matrixMultOnHost.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10randomInitPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInit... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00143dae_00000000-6_matrixMultOnHost.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... | .text
.file "matrixMultOnHost.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z10randomInitPfi
.LCPI0_0:
.long 0x30000000 # float 4.65661287E-10
.text
.globl _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInit... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include <stdio.h>
//# define num 10
__global__ void add1(int* a, int* b, int* c, int nu) {
int i = threadIdx.x;
if (i < nu) {
c[i] = b[i] + a[i];
//__syncthreads();
}
//__syncthreads();
}
int main(void) {
const int num = 10;... | code for sm_80
Function : _Z4add1PiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ IS... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include <stdio.h>
//# define num 10
__global__ void add1(int* a, int* b, int* c, int nu) {
int i = threadIdx.x;
if (i < nu) {
c[i] = b[i] + a[i];
//__syncthreads();
}
//__syncthreads();
}
int main(void) {
const int num = 10;... | .file "tmpxft_0010bb55_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include "device_functions.h"
#include <stdio.h>
//# define num 10
__global__ void add1(int* a, int* b, int* c, int nu) {
int i = threadIdx.x;
if (i < nu) {
c[i] = b[i] + a[i];
//__syncthreads();
}
//__syncthreads();
}
int main(void) {
const int num = 10;... | #include "hip/hip_runtime.h"
#include "hip/device_functions.h"
#include <stdio.h>
//# define num 10
__global__ void add1(int* a, int* b, int* c, int nu) {
int i = threadIdx.x;
if (i < nu) {
c[i] = b[i] + a[i];
//__syncthreads();
}
//__syncthreads();
}
int main(void) {
const int num = 10;//ûÓдÓÉÏͼ±¨´í £º ±í´ïʽ±ØÐëÓ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include "hip/device_functions.h"
#include <stdio.h>
//# define num 10
__global__ void add1(int* a, int* b, int* c, int nu) {
int i = threadIdx.x;
if (i < nu) {
c[i] = b[i] + a[i];
//__syncthreads();
}
//__syncthreads();
}
int main(void) {
const int num = 10;//ûÓдÓÉÏͼ±¨´í £º ±í´ïʽ±ØÐëÓ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4add1PiS_S_i
.globl _Z4add1PiS_S_i
.p2align 8
.type _Z4add1PiS_S_i,@function
_Z4add1PiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .L... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include "hip/device_functions.h"
#include <stdio.h>
//# define num 10
__global__ void add1(int* a, int* b, int* c, int nu) {
int i = threadIdx.x;
if (i < nu) {
c[i] = b[i] + a[i];
//__syncthreads();
}
//__syncthreads();
}
int main(void) {
const int num = 10;//ûÓдÓÉÏͼ±¨´í £º ±í´ïʽ±ØÐëÓ... | .text
.file "kernel.hip"
.globl _Z19__device_stub__add1PiS_S_i # -- Begin function _Z19__device_stub__add1PiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__add1PiS_S_i,@function
_Z19__device_stub__add1PiS_S_i: # @_Z19__device_stub__add1PiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
mov... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4add1PiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e240000002100 */
/*0020*/ IS... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4add1PiS_S_i
.globl _Z4add1PiS_S_i
.p2align 8
.type _Z4add1PiS_S_i,@function
_Z4add1PiS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .L... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010bb55_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "kernel.hip"
.globl _Z19__device_stub__add1PiS_S_i # -- Begin function _Z19__device_stub__add1PiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__add1PiS_S_i,@function
_Z19__device_stub__add1PiS_S_i: # @_Z19__device_stub__add1PiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
mov... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de cudaMallocHost() para alocar memoria paginada no host e
o uso de cudaFreeHost para desalocar()
Para compilar: nvcc 01-soma-vet-pinned.cu -o 01-soma-vet-pinned
Para executar: ./01-soma-vet-pinned
OBS: os valores de tamanho do vetor e o conteudo do vetor
... | code for sm_80
Function : _Z4somaPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de cudaMallocHost() para alocar memoria paginada no host e
o uso de cudaFreeHost para desalocar()
Para compilar: nvcc 01-soma-vet-pinned.cu -o 01-soma-vet-pinned
Para executar: ./01-soma-vet-pinned
OBS: os valores de tamanho do vetor e o conteudo do vetor
... | .file "tmpxft_0012bfeb_00000000-6_01-soma-vet-pinned.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
add... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de cudaMallocHost() para alocar memoria paginada no host e
o uso de cudaFreeHost para desalocar()
Para compilar: nvcc 01-soma-vet-pinned.cu -o 01-soma-vet-pinned
Para executar: ./01-soma-vet-pinned
OBS: os valores de tamanho do vetor e o conteudo do vetor
... | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de cudaMallocHost() para alocar memoria paginada no host e
o uso de cudaFreeHost para desalocar()
Para compilar: nvcc 01-soma-vet-pinned.cu -o 01-soma-vet-pinned
Para executar: ./01-soma-vet-pinned
OBS: os valores de tamanho do vetor e o conteudo do vetor
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de cudaMallocHost() para alocar memoria paginada no host e
o uso de cudaFreeHost para desalocar()
Para compilar: nvcc 01-soma-vet-pinned.cu -o 01-soma-vet-pinned
Para executar: ./01-soma-vet-pinned
OBS: os valores de tamanho do vetor e o conteudo do vetor
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4somaPiS_S_i
.globl _Z4somaPiS_S_i
.p2align 8
.type _Z4somaPiS_S_i,@function
_Z4somaPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu in... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Faz a soma dos elementos de dois vetores
Exemplifica o uso de cudaMallocHost() para alocar memoria paginada no host e
o uso de cudaFreeHost para desalocar()
Para compilar: nvcc 01-soma-vet-pinned.cu -o 01-soma-vet-pinned
Para executar: ./01-soma-vet-pinned
OBS: os valores de tamanho do vetor e o conteudo do vetor
... | .text
.file "01-soma-vet-pinned.hip"
.globl _Z19__device_stub__somaPiS_S_i # -- Begin function _Z19__device_stub__somaPiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__somaPiS_S_i,@function
_Z19__device_stub__somaPiS_S_i: # @_Z19__device_stub__somaPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_of... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4somaPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4somaPiS_S_i
.globl _Z4somaPiS_S_i
.p2align 8
.type _Z4somaPiS_S_i,@function
_Z4somaPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu in... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012bfeb_00000000-6_01-soma-vet-pinned.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
add... | .text
.file "01-soma-vet-pinned.hip"
.globl _Z19__device_stub__somaPiS_S_i # -- Begin function _Z19__device_stub__somaPiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__somaPiS_S_i,@function
_Z19__device_stub__somaPiS_S_i: # @_Z19__device_stub__somaPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_of... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void apply_lifter_and_floor_energy( int num_frames, int num_cols, float cepstral_lifter, bool use_energy, float energy_floor, float *log_energy, float *lifter_coeffs, float *features, int32_t ldf) {
int thread_id = threadIdx.x;
int frame = blockIdx.x;
float *feats = features + frame * l... | code for sm_80
Function : _Z29apply_lifter_and_floor_energyiifbfPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x00000000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void apply_lifter_and_floor_energy( int num_frames, int num_cols, float cepstral_lifter, bool use_energy, float energy_floor, float *log_energy, float *lifter_coeffs, float *features, int32_t ldf) {
int thread_id = threadIdx.x;
int frame = blockIdx.x;
float *feats = features + frame * l... | .file "tmpxft_00153415_00000000-6_apply_lifter_and_floor_energy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBin... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void apply_lifter_and_floor_energy( int num_frames, int num_cols, float cepstral_lifter, bool use_energy, float energy_floor, float *log_energy, float *lifter_coeffs, float *features, int32_t ldf) {
int thread_id = threadIdx.x;
int frame = blockIdx.x;
float *feats = features + frame * l... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void apply_lifter_and_floor_energy( int num_frames, int num_cols, float cepstral_lifter, bool use_energy, float energy_floor, float *log_energy, float *lifter_coeffs, float *features, int32_t ldf) {
int thread_id = threadIdx.x;
int frame = blockIdx.x;
float ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void apply_lifter_and_floor_energy( int num_frames, int num_cols, float cepstral_lifter, bool use_energy, float energy_floor, float *log_energy, float *lifter_coeffs, float *features, int32_t ldf) {
int thread_id = threadIdx.x;
int frame = blockIdx.x;
float ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29apply_lifter_and_floor_energyiifbfPfS_S_i
.globl _Z29apply_lifter_and_floor_energyiifbfPfS_S_i
.p2align 8
.type _Z29apply_lifter_and_floor_energyiifbfPfS_S_i,@function
_Z29apply_lifter_and_floor_energyiifbfPfS_S_i:
s_clause 0x2
s_load_b64 s[10:11], s[0:... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void apply_lifter_and_floor_energy( int num_frames, int num_cols, float cepstral_lifter, bool use_energy, float energy_floor, float *log_energy, float *lifter_coeffs, float *features, int32_t ldf) {
int thread_id = threadIdx.x;
int frame = blockIdx.x;
float ... | .text
.file "apply_lifter_and_floor_energy.hip"
.globl _Z44__device_stub__apply_lifter_and_floor_energyiifbfPfS_S_i # -- Begin function _Z44__device_stub__apply_lifter_and_floor_energyiifbfPfS_S_i
.p2align 4, 0x90
.type _Z44__device_stub__apply_lifter_and_floor_energyiifbfPfS_S_i,@function
_Z44__device_stub__apply_lift... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z29apply_lifter_and_floor_energyiifbfPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x00000000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z29apply_lifter_and_floor_energyiifbfPfS_S_i
.globl _Z29apply_lifter_and_floor_energyiifbfPfS_S_i
.p2align 8
.type _Z29apply_lifter_and_floor_energyiifbfPfS_S_i,@function
_Z29apply_lifter_and_floor_energyiifbfPfS_S_i:
s_clause 0x2
s_load_b64 s[10:11], s[0:... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00153415_00000000-6_apply_lifter_and_floor_energy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBin... | .text
.file "apply_lifter_and_floor_energy.hip"
.globl _Z44__device_stub__apply_lifter_and_floor_energyiifbfPfS_S_i # -- Begin function _Z44__device_stub__apply_lifter_and_floor_energyiifbfPfS_S_i
.p2align 4, 0x90
.type _Z44__device_stub__apply_lifter_and_floor_energyiifbfPfS_S_i,@function
_Z44__device_stub__apply_lift... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | extern "C"
__global__
void contrastiveDivergence(float* positive, float* negative, float* weights, float learningRate, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
weights[i] = weights[i] + (positive[i] - negative[i]) * learningRate;
}
} | code for sm_80
Function : contrastiveDivergence
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
__global__
void contrastiveDivergence(float* positive, float* negative, float* weights, float learningRate, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
weights[i] = weights[i] + (positive[i] - negative[i]) * learningRate;
}
} | .file "tmpxft_000a0b0c_00000000-6_contrastive_divergence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
__global__
void contrastiveDivergence(float* positive, float* negative, float* weights, float learningRate, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
weights[i] = weights[i] + (positive[i] - negative[i]) * learningRate;
}
} | #include <hip/hip_runtime.h>
extern "C"
__global__
void contrastiveDivergence(float* positive, float* negative, float* weights, float learningRate, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
weights[i] = weights[i] + (positive[i] - negative[i]) * learningRate;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void contrastiveDivergence(float* positive, float* negative, float* weights, float learningRate, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
weights[i] = weights[i] + (positive[i] - negative[i]) * learningRate;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected contrastiveDivergence
.globl contrastiveDivergence
.p2align 8
.type contrastiveDivergence,@function
contrastiveDivergence:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
__global__
void contrastiveDivergence(float* positive, float* negative, float* weights, float learningRate, int n)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
if (i < n)
{
weights[i] = weights[i] + (positive[i] - negative[i]) * learningRate;
}
} | .text
.file "contrastive_divergence.hip"
.globl __device_stub__contrastiveDivergence # -- Begin function __device_stub__contrastiveDivergence
.p2align 4, 0x90
.type __device_stub__contrastiveDivergence,@function
__device_stub__contrastiveDivergence: # @__device_stub__contrastiveDivergence
.cfi_startproc
# %bb.0:
subq... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : contrastiveDivergence
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected contrastiveDivergence
.globl contrastiveDivergence
.p2align 8
.type contrastiveDivergence,@function
contrastiveDivergence:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a0b0c_00000000-6_contrastive_divergence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT... | .text
.file "contrastive_divergence.hip"
.globl __device_stub__contrastiveDivergence # -- Begin function __device_stub__contrastiveDivergence
.p2align 4, 0x90
.type __device_stub__contrastiveDivergence,@function
__device_stub__contrastiveDivergence: # @__device_stub__contrastiveDivergence
.cfi_startproc
# %bb.0:
subq... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void sum_atomic(int nx, int *sum, int *data){
const int x = blockDim.x * blockIdx.x + threadIdx.x;
if (x < nx){
atomicAdd(sum, data[x]);
}
} | code for sm_80
Function : _Z10sum_atomiciPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*00... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void sum_atomic(int nx, int *sum, int *data){
const int x = blockDim.x * blockIdx.x + threadIdx.x;
if (x < nx){
atomicAdd(sum, data[x]);
}
} | .file "tmpxft_000c8f46_00000000-6_kernel_functions_for_atomic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinar... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void sum_atomic(int nx, int *sum, int *data){
const int x = blockDim.x * blockIdx.x + threadIdx.x;
if (x < nx){
atomicAdd(sum, data[x]);
}
} | #include <hip/hip_runtime.h>
__global__ void sum_atomic(int nx, int *sum, int *data){
const int x = blockDim.x * blockIdx.x + threadIdx.x;
if (x < nx){
atomicAdd(sum, data[x]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void sum_atomic(int nx, int *sum, int *data){
const int x = blockDim.x * blockIdx.x + threadIdx.x;
if (x < nx){
atomicAdd(sum, data[x]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sum_atomiciPiS_
.globl _Z10sum_atomiciPiS_
.p2align 8
.type _Z10sum_atomiciPiS_,@function
_Z10sum_atomiciPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_del... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void sum_atomic(int nx, int *sum, int *data){
const int x = blockDim.x * blockIdx.x + threadIdx.x;
if (x < nx){
atomicAdd(sum, data[x]);
}
} | .text
.file "kernel_functions_for_atomic.hip"
.globl _Z25__device_stub__sum_atomiciPiS_ # -- Begin function _Z25__device_stub__sum_atomiciPiS_
.p2align 4, 0x90
.type _Z25__device_stub__sum_atomiciPiS_,@function
_Z25__device_stub__sum_atomiciPiS_: # @_Z25__device_stub__sum_atomiciPiS_
.cfi_startproc
# %bb.0:
subq $1... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10sum_atomiciPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10sum_atomiciPiS_
.globl _Z10sum_atomiciPiS_
.p2align 8
.type _Z10sum_atomiciPiS_,@function
_Z10sum_atomiciPiS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_del... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c8f46_00000000-6_kernel_functions_for_atomic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinar... | .text
.file "kernel_functions_for_atomic.hip"
.globl _Z25__device_stub__sum_atomiciPiS_ # -- Begin function _Z25__device_stub__sum_atomiciPiS_
.p2align 4, 0x90
.type _Z25__device_stub__sum_atomiciPiS_,@function
_Z25__device_stub__sum_atomiciPiS_: # @_Z25__device_stub__sum_atomiciPiS_
.cfi_startproc
# %bb.0:
subq $1... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <algorithm>
#include <iostream>
#include <vector>
#define CHECK_ERROR(FUNC) checkCudaErrorMsg(FUNC, " " #FUNC)
void inline checkCudaErrorMsg(cudaError status, const char *msg) {
if (status != cudaSuccess) {
std::cout << msg << " - " << status << std::endl;
exit(EXIT_FAILURE);
}
}
/* A... | code for sm_80
Function : _Z6matmulPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*002... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <algorithm>
#include <iostream>
#include <vector>
#define CHECK_ERROR(FUNC) checkCudaErrorMsg(FUNC, " " #FUNC)
void inline checkCudaErrorMsg(cudaError status, const char *msg) {
if (status != cudaSuccess) {
std::cout << msg << " - " << status << std::endl;
exit(EXIT_FAILURE);
}
}
/* A... | .file "tmpxft_000843cb_00000000-6_cuda_matmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4290:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cu... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <algorithm>
#include <iostream>
#include <vector>
#define CHECK_ERROR(FUNC) checkCudaErrorMsg(FUNC, " " #FUNC)
void inline checkCudaErrorMsg(cudaError status, const char *msg) {
if (status != cudaSuccess) {
std::cout << msg << " - " << status << std::endl;
exit(EXIT_FAILURE);
}
}
/* A... | #include <hip/hip_runtime.h>
#include <algorithm>
#include <iostream>
#include <vector>
#define CHECK_ERROR(FUNC) checkCudaErrorMsg(FUNC, " " #FUNC)
void inline checkCudaErrorMsg(hipError_t status, const char *msg) {
if (status != hipSuccess) {
std::cout << msg << " - " << status << std::endl;
exit(EXIT_FAILURE);
}
}
/... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <iostream>
#include <vector>
#define CHECK_ERROR(FUNC) checkCudaErrorMsg(FUNC, " " #FUNC)
void inline checkCudaErrorMsg(hipError_t status, const char *msg) {
if (status != hipSuccess) {
std::cout << msg << " - " << status << std::endl;
exit(EXIT_FAILURE);
}
}
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPKfS0_Pfi
.globl _Z6matmulPKfS0_Pfi
.p2align 8
.type _Z6matmulPKfS0_Pfi,@function
_Z6matmulPKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <algorithm>
#include <iostream>
#include <vector>
#define CHECK_ERROR(FUNC) checkCudaErrorMsg(FUNC, " " #FUNC)
void inline checkCudaErrorMsg(hipError_t status, const char *msg) {
if (status != hipSuccess) {
std::cout << msg << " - " << status << std::endl;
exit(EXIT_FAILURE);
}
}
/... | .text
.file "cuda_matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matmulPKfS0_Pfi # -- Begin function _Z21__device_stub__matmulPKfS0_Pfi
.p2al... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matmulPKfS0_Pfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*002... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPKfS0_Pfi
.globl _Z6matmulPKfS0_Pfi
.p2align 8
.type _Z6matmulPKfS0_Pfi,@function
_Z6matmulPKfS0_Pfi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000843cb_00000000-6_cuda_matmul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4290:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cu... | .text
.file "cuda_matmul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__matmulPKfS0_Pfi # -- Begin function _Z21__device_stub__matmulPKfS0_Pfi
.p2al... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void add( double * v1, const double * v2, int chunksize )
{
int chunkstart = threadIdx.x*chunksize;
int chunkend = (threadIdx.x+1)*chunksize;
int i = 0;
for (i = chunkstart; i < chunkend; ++i) {
v1[i] += v2[i];
}
} | code for sm_80
Function : _Z3addPdPKdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void add( double * v1, const double * v2, int chunksize )
{
int chunkstart = threadIdx.x*chunksize;
int chunkend = (threadIdx.x+1)*chunksize;
int i = 0;
for (i = chunkstart; i < chunkend; ++i) {
v1[i] += v2[i];
}
} | .file "tmpxft_000cb479_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void add( double * v1, const double * v2, int chunksize )
{
int chunkstart = threadIdx.x*chunksize;
int chunkend = (threadIdx.x+1)*chunksize;
int i = 0;
for (i = chunkstart; i < chunkend; ++i) {
v1[i] += v2[i];
}
} | #include <hip/hip_runtime.h>
__global__ void add( double * v1, const double * v2, int chunksize )
{
int chunkstart = threadIdx.x*chunksize;
int chunkend = (threadIdx.x+1)*chunksize;
int i = 0;
for (i = chunkstart; i < chunkend; ++i) {
v1[i] += v2[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void add( double * v1, const double * v2, int chunksize )
{
int chunkstart = threadIdx.x*chunksize;
int chunkend = (threadIdx.x+1)*chunksize;
int i = 0;
for (i = chunkstart; i < chunkend; ++i) {
v1[i] += v2[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdPKdi
.globl _Z3addPdPKdi
.p2align 8
.type _Z3addPdPKdi,@function
_Z3addPdPKdi:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_1) | inst... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void add( double * v1, const double * v2, int chunksize )
{
int chunkstart = threadIdx.x*chunksize;
int chunkend = (threadIdx.x+1)*chunksize;
int i = 0;
for (i = chunkstart; i < chunkend; ++i) {
v1[i] += v2[i];
}
} | .text
.file "add.hip"
.globl _Z18__device_stub__addPdPKdi # -- Begin function _Z18__device_stub__addPdPKdi
.p2align 4, 0x90
.type _Z18__device_stub__addPdPKdi,@function
_Z18__device_stub__addPdPKdi: # @_Z18__device_stub__addPdPKdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 7... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPdPKdi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdPKdi
.globl _Z3addPdPKdi
.p2align 8
.type _Z3addPdPKdi,@function
_Z3addPdPKdi:
s_load_b32 s2, s[0:1], 0x10
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v0, v0, s2
s_delay_alu instid0(VALU_DEP_1) | inst... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cb479_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi... | .text
.file "add.hip"
.globl _Z18__device_stub__addPdPKdi # -- Begin function _Z18__device_stub__addPdPKdi
.p2align 4, 0x90
.type _Z18__device_stub__addPdPKdi,@function
_Z18__device_stub__addPdPKdi: # @_Z18__device_stub__addPdPKdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 7... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <math.h>
int main(int argc, char **argv)
{
printf("%s Starting...\n", argv[0]);
// Check how many cuda devices in the system.
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess)
{
printf("cudaGetDeviceCount re... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <stdio.h>
#include <math.h>
int main(int argc, char **argv)
{
printf("%s Starting...\n", argv[0]);
// Check how many cuda devices in the system.
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess)
{
printf("cudaGetDeviceCount re... | .file "tmpxft_001789f0_00000000-6_checkDeviceInfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <stdio.h>
#include <math.h>
int main(int argc, char **argv)
{
printf("%s Starting...\n", argv[0]);
// Check how many cuda devices in the system.
int deviceCount = 0;
cudaError_t error_id = cudaGetDeviceCount(&deviceCount);
if (error_id != cudaSuccess)
{
printf("cudaGetDeviceCount re... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
int main(int argc, char **argv)
{
printf("%s Starting...\n", argv[0]);
// Check how many cuda devices in the system.
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess)
{
printf("hipGetDeviceCount ret... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
int main(int argc, char **argv)
{
printf("%s Starting...\n", argv[0]);
// Check how many cuda devices in the system.
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess)
{
printf("hipGetDeviceCount ret... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
int main(int argc, char **argv)
{
printf("%s Starting...\n", argv[0]);
// Check how many cuda devices in the system.
int deviceCount = 0;
hipError_t error_id = hipGetDeviceCount(&deviceCount);
if (error_id != hipSuccess)
{
printf("hipGetDeviceCount ret... | .text
.file "checkDeviceInfo.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_1:
.long 0x3a83126f ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001789f0_00000000-6_checkDeviceInfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... | .text
.file "checkDeviceInfo.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3e10000000000000 # double 9.3132257461547852E-10
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI0_1:
.long 0x3a83126f ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cuda_runtime.h>
#include<math.h>
#define SIZE 1024
#define TILE_WIDTH 16
float h_M[SIZE*SIZE],h_N[SIZE*SIZE],h_P[SIZE*SIZE];
__global__ void multiplication_kernel(float *d_M,float *d_N,float *d_P)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
... | code for sm_80
Function : _Z21multiplication_kernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e2200000021... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cuda_runtime.h>
#include<math.h>
#define SIZE 1024
#define TILE_WIDTH 16
float h_M[SIZE*SIZE],h_N[SIZE*SIZE],h_P[SIZE*SIZE];
__global__ void multiplication_kernel(float *d_M,float *d_N,float *d_P)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
... | .file "tmpxft_001b0550_00000000-6_Q6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cuda_runtime.h>
#include<math.h>
#define SIZE 1024
#define TILE_WIDTH 16
float h_M[SIZE*SIZE],h_N[SIZE*SIZE],h_P[SIZE*SIZE];
__global__ void multiplication_kernel(float *d_M,float *d_N,float *d_P)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH];
... | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#define SIZE 1024
#define TILE_WIDTH 16
float h_M[SIZE*SIZE],h_N[SIZE*SIZE],h_P[SIZE*SIZE];
__global__ void multiplication_kernel(float *d_M,float *d_N,float *d_P)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#define SIZE 1024
#define TILE_WIDTH 16
float h_M[SIZE*SIZE],h_N[SIZE*SIZE],h_P[SIZE*SIZE];
__global__ void multiplication_kernel(float *d_M,float *d_N,float *d_P)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21multiplication_kernelPfS_S_
.globl _Z21multiplication_kernelPfS_S_
.p2align 8
.type _Z21multiplication_kernelPfS_S_,@function
_Z21multiplication_kernelPfS_S_:
v_and_b32_e32 v2, 0x3ff, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<hip/hip_runtime.h>
#include<math.h>
#define SIZE 1024
#define TILE_WIDTH 16
float h_M[SIZE*SIZE],h_N[SIZE*SIZE],h_P[SIZE*SIZE];
__global__ void multiplication_kernel(float *d_M,float *d_N,float *d_P)
{
__shared__ float ds_M[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_N[TILE_WIDTH][TILE_WIDTH... | .text
.file "Q6.hip"
.globl _Z36__device_stub__multiplication_kernelPfS_S_ # -- Begin function _Z36__device_stub__multiplication_kernelPfS_S_
.p2align 4, 0x90
.type _Z36__device_stub__multiplication_kernelPfS_S_,@function
_Z36__device_stub__multiplication_kernelPfS_S_: # @_Z36__device_stub__multiplication_kernelPfS_S_
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21multiplication_kernelPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e2200000021... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21multiplication_kernelPfS_S_
.globl _Z21multiplication_kernelPfS_S_
.p2align 8
.type _Z21multiplication_kernelPfS_S_,@function
_Z21multiplication_kernelPfS_S_:
v_and_b32_e32 v2, 0x3ff, v0
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b0550_00000000-6_Q6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_... | .text
.file "Q6.hip"
.globl _Z36__device_stub__multiplication_kernelPfS_S_ # -- Begin function _Z36__device_stub__multiplication_kernelPfS_S_
.p2align 4, 0x90
.type _Z36__device_stub__multiplication_kernelPfS_S_,@function
_Z36__device_stub__multiplication_kernelPfS_S_: # @_Z36__device_stub__multiplication_kernelPfS_S_
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <time.h>
#define N 512
/*
void Matriz_CPU_Mult(int A[N][N], int B[N][N], int C[N][N]) {
int n,m;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int sum = 0;
for (int k = 0; k < N; k++) {
m = A[i][k];
n = B[k][j];
sum += m * n;
}
C[i][j] = sum;
}
}
}
*/
__global__ void Matriz_GPU... | code for sm_80
Function : _Z15Matriz_GPU_MultPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <time.h>
#define N 512
/*
void Matriz_CPU_Mult(int A[N][N], int B[N][N], int C[N][N]) {
int n,m;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int sum = 0;
for (int k = 0; k < N; k++) {
m = A[i][k];
n = B[k][j];
sum += m * n;
}
C[i][j] = sum;
}
}
}
*/
__global__ void Matriz_GPU... | .file "tmpxft_001a91be_00000000-6_matmult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <time.h>
#define N 512
/*
void Matriz_CPU_Mult(int A[N][N], int B[N][N], int C[N][N]) {
int n,m;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int sum = 0;
for (int k = 0; k < N; k++) {
m = A[i][k];
n = B[k][j];
sum += m * n;
}
C[i][j] = sum;
}
}
}
*/
__global__ void Matriz_GPU... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define N 512
/*
void Matriz_CPU_Mult(int A[N][N], int B[N][N], int C[N][N]) {
int n,m;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int sum = 0;
for (int k = 0; k < N; k++) {
m = A[i][k];
n = B[k][j];
sum += m * n;
}
C[i][j] = sum;
}
}
}
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define N 512
/*
void Matriz_CPU_Mult(int A[N][N], int B[N][N], int C[N][N]) {
int n,m;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int sum = 0;
for (int k = 0; k < N; k++) {
m = A[i][k];
n = B[k][j];
sum += m * n;
}
C[i][j] = sum;
}
}
}
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Matriz_GPU_MultPdS_S_
.globl _Z15Matriz_GPU_MultPdS_S_
.p2align 8
.type _Z15Matriz_GPU_MultPdS_S_,@function
_Z15Matriz_GPU_MultPdS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_a... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>
#define N 512
/*
void Matriz_CPU_Mult(int A[N][N], int B[N][N], int C[N][N]) {
int n,m;
for (int i = 0; i < N; i++) {
for (int j = 0; j < N; j++) {
int sum = 0;
for (int k = 0; k < N; k++) {
m = A[i][k];
n = B[k][j];
sum += m * n;
}
C[i][j] = sum;
}
}
}
... | .text
.file "matmult.hip"
.globl _Z30__device_stub__Matriz_GPU_MultPdS_S_ # -- Begin function _Z30__device_stub__Matriz_GPU_MultPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__Matriz_GPU_MultPdS_S_,@function
_Z30__device_stub__Matriz_GPU_MultPdS_S_: # @_Z30__device_stub__Matriz_GPU_MultPdS_S_
.cfi_startproc
# %bb.0:
s... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15Matriz_GPU_MultPdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15Matriz_GPU_MultPdS_S_
.globl _Z15Matriz_GPU_MultPdS_S_
.p2align 8
.type _Z15Matriz_GPU_MultPdS_S_,@function
_Z15Matriz_GPU_MultPdS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_a... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a91be_00000000-6_matmult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "matmult.hip"
.globl _Z30__device_stub__Matriz_GPU_MultPdS_S_ # -- Begin function _Z30__device_stub__Matriz_GPU_MultPdS_S_
.p2align 4, 0x90
.type _Z30__device_stub__Matriz_GPU_MultPdS_S_,@function
_Z30__device_stub__Matriz_GPU_MultPdS_S_: # @_Z30__device_stub__Matriz_GPU_MultPdS_S_
.cfi_startproc
# %bb.0:
s... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuComplex.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#define BLOCK_SIZE 16 // Threads per block supported by the GPU
__global__ void dtpmv_kernel ( char UPLO, char TRANS, char DIAG,int N,double * A, double *X , double *T) {
int elementId = blockIdx.x * BLOC... | .file "tmpxft_00016269_00000000-6_dtpmv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuComplex.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#define BLOCK_SIZE 16 // Threads per block supported by the GPU
__global__ void dtpmv_kernel ( char UPLO, char TRANS, char DIAG,int N,double * A, double *X , double *T) {
int elementId = blockIdx.x * BLOC... | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
#include <hip/hip_runtime_api.h>
#define BLOCK_SIZE 16 // Threads per block supported by the GPU
__global__ void dtpmv_kernel ( char UPLO, char TRANS, char DIAG,int N,double * A, double *X , double *T) {
int elementId = blockIdx.x * BLOCK_SIZE... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
#include <hip/hip_runtime_api.h>
#define BLOCK_SIZE 16 // Threads per block supported by the GPU
__global__ void dtpmv_kernel ( char UPLO, char TRANS, char DIAG,int N,double * A, double *X , double *T) {
int elementId = blockIdx.x * BLOCK_SIZE... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12dtpmv_kernelccciPdS_S_
.globl _Z12dtpmv_kernelccciPdS_S_
.p2align 8
.type _Z12dtpmv_kernelccciPdS_S_,@function
_Z12dtpmv_kernelccciPdS_S_:
s_load_b32 s10, s[0:1], 0x4
s_lshl_b32 s8, s15, 4
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v1, s8, v0
s_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>
#include <hip/hip_runtime_api.h>
#define BLOCK_SIZE 16 // Threads per block supported by the GPU
__global__ void dtpmv_kernel ( char UPLO, char TRANS, char DIAG,int N,double * A, double *X , double *T) {
int elementId = blockIdx.x * BLOCK_SIZE... | .text
.file "dtpmv.hip"
.globl _Z27__device_stub__dtpmv_kernelccciPdS_S_ # -- Begin function _Z27__device_stub__dtpmv_kernelccciPdS_S_
.p2align 4, 0x90
.type _Z27__device_stub__dtpmv_kernelccciPdS_S_,@function
_Z27__device_stub__dtpmv_kernelccciPdS_S_: # @_Z27__device_stub__dtpmv_kernelccciPdS_S_
.cfi_startproc
# %bb.0... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00016269_00000000-6_dtpmv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... | .text
.file "dtpmv.hip"
.globl _Z27__device_stub__dtpmv_kernelccciPdS_S_ # -- Begin function _Z27__device_stub__dtpmv_kernelccciPdS_S_
.p2align 4, 0x90
.type _Z27__device_stub__dtpmv_kernelccciPdS_S_,@function
_Z27__device_stub__dtpmv_kernelccciPdS_S_: # @_Z27__device_stub__dtpmv_kernelccciPdS_S_
.cfi_startproc
# %bb.0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void histogram_equalization( int * lut, unsigned char * img_out, unsigned char * img_in, int * hist_in, int img_size, int nbr_bin){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
__shared__ int smem[256];
smem[ threadIdx.x ] = lut[ threadIdx.x ];
__syncthr... | code for sm_80
Function : _Z22histogram_equalizationPiPhS0_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void histogram_equalization( int * lut, unsigned char * img_out, unsigned char * img_in, int * hist_in, int img_size, int nbr_bin){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
__shared__ int smem[256];
smem[ threadIdx.x ] = lut[ threadIdx.x ];
__syncthr... | .file "tmpxft_000039fb_00000000-6_histogram_equalization.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void histogram_equalization( int * lut, unsigned char * img_out, unsigned char * img_in, int * hist_in, int img_size, int nbr_bin){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
__shared__ int smem[256];
smem[ threadIdx.x ] = lut[ threadIdx.x ];
__syncthr... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_equalization( int * lut, unsigned char * img_out, unsigned char * img_in, int * hist_in, int img_size, int nbr_bin){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
__shared__ int smem[256];
smem[ threadIdx.x ] = ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_equalization( int * lut, unsigned char * img_out, unsigned char * img_in, int * hist_in, int img_size, int nbr_bin){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
__shared__ int smem[256];
smem[ threadIdx.x ] = ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22histogram_equalizationPiPhS0_S_ii
.globl _Z22histogram_equalizationPiPhS0_S_ii
.p2align 8
.type _Z22histogram_equalizationPiPhS0_S_ii,@function
_Z22histogram_equalizationPiPhS0_S_ii:
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
s_clause 0... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histogram_equalization( int * lut, unsigned char * img_out, unsigned char * img_in, int * hist_in, int img_size, int nbr_bin){
int tx=threadIdx.x;
int ty=threadIdx.y;
int bx=blockIdx.x;
int by=blockIdx.y;
__shared__ int smem[256];
smem[ threadIdx.x ] = ... | .text
.file "histogram_equalization.hip"
.globl _Z37__device_stub__histogram_equalizationPiPhS0_S_ii # -- Begin function _Z37__device_stub__histogram_equalizationPiPhS0_S_ii
.p2align 4, 0x90
.type _Z37__device_stub__histogram_equalizationPiPhS0_S_ii,@function
_Z37__device_stub__histogram_equalizationPiPhS0_S_ii: # @_Z3... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22histogram_equalizationPiPhS0_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22histogram_equalizationPiPhS0_S_ii
.globl _Z22histogram_equalizationPiPhS0_S_ii
.p2align 8
.type _Z22histogram_equalizationPiPhS0_S_ii,@function
_Z22histogram_equalizationPiPhS0_S_ii:
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
s_clause 0... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000039fb_00000000-6_histogram_equalization.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT... | .text
.file "histogram_equalization.hip"
.globl _Z37__device_stub__histogram_equalizationPiPhS0_S_ii # -- Begin function _Z37__device_stub__histogram_equalizationPiPhS0_S_ii
.p2align 4, 0x90
.type _Z37__device_stub__histogram_equalizationPiPhS0_S_ii,@function
_Z37__device_stub__histogram_equalizationPiPhS0_S_ii: # @_Z3... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ================================================================================================
// Tim Backus
// CIS 450 - High Performance Computing
// 3D Game of Life - CUDA Version
// ================================================================================================
#define GOL_IO_FILENAME "gol3DOu... | .file "tmpxft_000563b6_00000000-6_Cuda3DLife.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ================================================================================================
// Tim Backus
// CIS 450 - High Performance Computing
// 3D Game of Life - CUDA Version
// ================================================================================================
#define GOL_IO_FILENAME "gol3DOu... | // ================================================================================================
// Tim Backus
// CIS 450 - High Performance Computing
// 3D Game of Life - CUDA Version
// ================================================================================================
#define GOL_IO_FILENAME "gol3DOu... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // ================================================================================================
// Tim Backus
// CIS 450 - High Performance Computing
// 3D Game of Life - CUDA Version
// ================================================================================================
#define GOL_IO_FILENAME "gol3DOu... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13lifeItrKernelPKcPcjjjjj
.globl _Z13lifeItrKernelPKcPcjjjjj
.p2align 8
.type _Z13lifeItrKernelPKcPcjjjjj,@function
_Z13lifeItrKernelPKcPcjjjjj:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x34
s_load_b64 s[6:7], s[0:1], 0x10
s_load_b32 s5, s[0:1],... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // ================================================================================================
// Tim Backus
// CIS 450 - High Performance Computing
// 3D Game of Life - CUDA Version
// ================================================================================================
#define GOL_IO_FILENAME "gol3DOu... | .text
.file "Cuda3DLife.hip"
.globl _Z28__device_stub__lifeItrKernelPKcPcjjjjj # -- Begin function _Z28__device_stub__lifeItrKernelPKcPcjjjjj
.p2align 4, 0x90
.type _Z28__device_stub__lifeItrKernelPKcPcjjjjj,@function
_Z28__device_stub__lifeItrKernelPKcPcjjjjj: # @_Z28__device_stub__lifeItrKernelPKcPcjjjjj
.cfi_startpr... |
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