system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* gesummv.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#inclu... | code for sm_80
Function : _Z14gesummv_kernelPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e28000000250... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* gesummv.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#inclu... | .file "tmpxft_0017e208_00000000-6_gesummv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* gesummv.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#inclu... | /**
* gesummv.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#inclu... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* gesummv.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#inclu... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14gesummv_kernelPfS_S_S_S_
.globl _Z14gesummv_kernelPfS_S_S_S_
.p2align 8
.type _Z14gesummv_kernelPfS_S_S_S_,@function
_Z14gesummv_kernelPfS_S_S_S_:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SA... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* gesummv.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <unistd.h>
#include <stdio.h>
#include <time.h>
#inclu... | .text
.file "gesummv.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14gesummv_kernelPfS_S_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e28000000250... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14gesummv_kernelPfS_S_S_S_
.globl _Z14gesummv_kernelPfS_S_S_S_
.p2align 8
.type _Z14gesummv_kernelPfS_S_S_S_,@function
_Z14gesummv_kernelPfS_S_S_S_:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SA... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017e208_00000000-6_gesummv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "gesummv.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <iomanip>
#include <cstdlib>
#include <cmath>
#include <cuda_runtime_api.h>
#define SQ(x) ((x) * (x))
static const float A = -4.0, B = 4.0; // limites de integración
static const int N = 1 << 22; // número de intervalos = 2^22
static const float H = (B - A) / N; // tamaño del intervalo de i... | .file "tmpxft_001b4c44_00000000-6_integral.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3958:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <iomanip>
#include <cstdlib>
#include <cmath>
#include <cuda_runtime_api.h>
#define SQ(x) ((x) * (x))
static const float A = -4.0, B = 4.0; // limites de integración
static const int N = 1 << 22; // número de intervalos = 2^22
static const float H = (B - A) / N; // tamaño del intervalo de i... | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <cmath>
#include <hip/hip_runtime_api.h>
#define SQ(x) ((x) * (x))
static const float A = -4.0, B = 4.0; // limites de integración
static const int N = 1 << 22; // número de intervalos = 2^22
static const float H = (B - A) /... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <cstdlib>
#include <cmath>
#include <hip/hip_runtime_api.h>
#define SQ(x) ((x) * (x))
static const float A = -4.0, B = 4.0; // limites de integración
static const int N = 1 << 22; // número de intervalos = 2^22
static const float H = (B - A) /... | .text
.file "integral.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6ho... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b4c44_00000000-6_integral.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3958:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaU... | .text
.file "integral.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z6ho... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Copyright (c) 2017 Darius Rückert
* Licensed under the MIT License.
* See LICENSE file for more information.
*/
#include <iostream>
#include <vector>
#include <cuda_runtime.h>
#include <thrust/device_vector.h>
template <unsigned int BLOCK_SIZE>
__global__ static void oob(int* data, int size)
{
auto id = threadId... | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUD... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Copyright (c) 2017 Darius Rückert
* Licensed under the MIT License.
* See LICENSE file for more information.
*/
#include <iostream>
#include <vector>
#include <cuda_runtime.h>
#include <thrust/device_vector.h>
template <unsigned int BLOCK_SIZE>
__global__ static void oob(int* data, int size)
{
auto id = threadId... | /**
* Copyright (c) 2017 Darius Rückert
* Licensed under the MIT License.
* See LICENSE file for more information.
*/
#include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
template <unsigned int BLOCK_SIZE>
__global__ static void oob(int* data, int size)
{
auto id = threa... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Copyright (c) 2017 Darius Rückert
* Licensed under the MIT License.
* See LICENSE file for more information.
*/
#include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
template <unsigned int BLOCK_SIZE>
__global__ static void oob(int* data, int size)
{
auto id = threa... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEm... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUD... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEm... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void complement(int* a , int* b,int n)
{
int id = threadIdx.x;
int m = blockDim.x;
int j = 0;
if(id!=0 && id!=(m-1))
{
for(j=1;j<n-1;j++)
{
int rem = 0,p=0;
int d = a[id*m+j];
for(p=1;d>0;... | code for sm_80
Function : _Z10complementPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e22000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void complement(int* a , int* b,int n)
{
int id = threadIdx.x;
int m = blockDim.x;
int j = 0;
if(id!=0 && id!=(m-1))
{
for(j=1;j<n-1;j++)
{
int rem = 0,p=0;
int d = a[id*m+j];
for(p=1;d>0;... | .file "tmpxft_000436dc_00000000-6_forth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void complement(int* a , int* b,int n)
{
int id = threadIdx.x;
int m = blockDim.x;
int j = 0;
if(id!=0 && id!=(m-1))
{
for(j=1;j<n-1;j++)
{
int rem = 0,p=0;
int d = a[id*m+j];
for(p=1;d>0;... | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void complement(int* a , int* b,int n)
{
int id = threadIdx.x;
int m = blockDim.x;
int j = 0;
if(id!=0 && id!=(m-1))
{
for(j=1;j<n-1;j++)
{
int rem = 0,p=0;
int d = a[id*m+j];
for(p=1;d>0;p = p*10)
{
rem = d%2;
if(rem == 0)... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void complement(int* a , int* b,int n)
{
int id = threadIdx.x;
int m = blockDim.x;
int j = 0;
if(id!=0 && id!=(m-1))
{
for(j=1;j<n-1;j++)
{
int rem = 0,p=0;
int d = a[id*m+j];
for(p=1;d>0;p = p*10)
{
rem = d%2;
if(rem == 0)... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10complementPiS_i
.globl _Z10complementPiS_i
.p2align 8
.type _Z10complementPiS_i,@function
_Z10complementPiS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x10
v_cmp_ne_u32_e32 v... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void complement(int* a , int* b,int n)
{
int id = threadIdx.x;
int m = blockDim.x;
int j = 0;
if(id!=0 && id!=(m-1))
{
for(j=1;j<n-1;j++)
{
int rem = 0,p=0;
int d = a[id*m+j];
for(p=1;d>0;p = p*10)
{
rem = d%2;
if(rem == 0)... | .text
.file "forth.hip"
.globl _Z25__device_stub__complementPiS_i # -- Begin function _Z25__device_stub__complementPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__complementPiS_i,@function
_Z25__device_stub__complementPiS_i: # @_Z25__device_stub__complementPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10complementPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e22000... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10complementPiS_i
.globl _Z10complementPiS_i
.p2align 8
.type _Z10complementPiS_i,@function
_Z10complementPiS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s1, s[0:1], 0x10
v_cmp_ne_u32_e32 v... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000436dc_00000000-6_forth.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... | .text
.file "forth.hip"
.globl _Z25__device_stub__complementPiS_i # -- Begin function _Z25__device_stub__complementPiS_i
.p2align 4, 0x90
.type _Z25__device_stub__complementPiS_i,@function
_Z25__device_stub__complementPiS_i: # @_Z25__device_stub__complementPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include "cuda.h"
__device__ void f(int x) {
}
__global__ void foo() {
f(2);
} | code for sm_80
Function : _Z3foov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xffffff... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include "cuda.h"
__device__ void f(int x) {
}
__global__ void foo() {
f(2);
} | .file "tmpxft_000800cc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include "cuda.h"
__device__ void f(int x) {
}
__global__ void foo() {
f(2);
} | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include "hip/hip_runtime.h"
__device__ void f(int x) {
}
__global__ void foo() {
f(2);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include "hip/hip_runtime.h"
__device__ void f(int x) {
}
__global__ void foo() {
f(2);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3foov
.globl _Z3foov
.p2align 8
.type _Z3foov,@function
_Z3foov:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3foov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fix... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=64 --gridDim=64 --no-inline
#include "hip/hip_runtime.h"
__device__ void f(int x) {
}
__global__ void foo() {
f(2);
} | .text
.file "kernel.hip"
.globl _Z18__device_stub__foov # -- Begin function _Z18__device_stub__foov
.p2align 4, 0x90
.type _Z18__device_stub__foov,@function
_Z18__device_stub__foov: # @_Z18__device_stub__foov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 1... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3foov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xffffff... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3foov
.globl _Z3foov
.p2align 8
.type _Z3foov,@function
_Z3foov:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3foov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fix... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000800cc_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "kernel.hip"
.globl _Z18__device_stub__foov # -- Begin function _Z18__device_stub__foov
.p2align 4, 0x90
.type _Z18__device_stub__foov,@function
_Z18__device_stub__foov: # @_Z18__device_stub__foov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 1... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include <chrono>
#include <iostream>
#include <sstream>
#define arraySize 31 // 35 max
#define def_div 10 // 5<=X<=15
//#define W 100
//#define threads_per_block 32
//#define max_blocks 32
using namespace std;
__constant__ float coefs[arraySize * 2 + 1];
__global__ void hybrid(float *sh_sum_d... | .file "tmpxft_0007a6a3_00000000-6_Hybrid-Horviz.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3838:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include <chrono>
#include <iostream>
#include <sstream>
#define arraySize 31 // 35 max
#define def_div 10 // 5<=X<=15
//#define W 100
//#define threads_per_block 32
//#define max_blocks 32
using namespace std;
__constant__ float coefs[arraySize * 2 + 1];
__global__ void hybrid(float *sh_sum_d... | #include "hip/hip_runtime.h"
#include <chrono>
#include <iostream>
#include <sstream>
#define arraySize 31 // 35 max
#define def_div 10 // 5<=X<=15
//#define W 100
//#define threads_per_block 32
//#define max_blocks 32
using namespace std;
__constant__ float coefs[arraySize * 2 + 1];
__global__ void hybrid(float *sh_su... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <chrono>
#include <iostream>
#include <sstream>
#define arraySize 31 // 35 max
#define def_div 10 // 5<=X<=15
//#define W 100
//#define threads_per_block 32
//#define max_blocks 32
using namespace std;
__constant__ float coefs[arraySize * 2 + 1];
__global__ void hybrid(float *sh_su... | .text
.file "Hybrid-Horviz.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__hybridPfPlfPiS1_i # -- Begin function _Z21__device_stub__hybridPfPlfPiS1_i... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sub_i32 (int* left_op, int* right_op, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = left_op[idx] - right_op[idx];
}
} | code for sm_80
Function : _Z7sub_i32PiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sub_i32 (int* left_op, int* right_op, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = left_op[idx] - right_op[idx];
}
} | .file "tmpxft_0006fd88_00000000-6_sub_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sub_i32 (int* left_op, int* right_op, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = left_op[idx] - right_op[idx];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sub_i32 (int* left_op, int* right_op, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = left_op[idx] - right_op[idx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sub_i32 (int* left_op, int* right_op, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = left_op[idx] - right_op[idx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sub_i32PiS_S_i
.globl _Z7sub_i32PiS_S_i
.p2align 8
.type _Z7sub_i32PiS_S_i,@function
_Z7sub_i32PiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sub_i32 (int* left_op, int* right_op, int* output, int len) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < len) {
output[idx] = left_op[idx] - right_op[idx];
}
} | .text
.file "sub_i32.hip"
.globl _Z22__device_stub__sub_i32PiS_S_i # -- Begin function _Z22__device_stub__sub_i32PiS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__sub_i32PiS_S_i,@function
_Z22__device_stub__sub_i32PiS_S_i: # @_Z22__device_stub__sub_i32PiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_of... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7sub_i32PiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7sub_i32PiS_S_i
.globl _Z7sub_i32PiS_S_i
.p2align 8
.type _Z7sub_i32PiS_S_i,@function
_Z7sub_i32PiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006fd88_00000000-6_sub_i32.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "sub_i32.hip"
.globl _Z22__device_stub__sub_i32PiS_S_i # -- Begin function _Z22__device_stub__sub_i32PiS_S_i
.p2align 4, 0x90
.type _Z22__device_stub__sub_i32PiS_S_i,@function
_Z22__device_stub__sub_i32PiS_S_i: # @_Z22__device_stub__sub_i32PiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_of... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ void recover_results(short *results, const int search_depth, const int total_dl_matrix_row_num) {
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
if (results[i] == search_depth) {
results[i] = 0;
}
}
}
__global__ void recover_results(int *results, const int ... | code for sm_80
Function : _Z15recover_resultsPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e2... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ void recover_results(short *results, const int search_depth, const int total_dl_matrix_row_num) {
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
if (results[i] == search_depth) {
results[i] = 0;
}
}
}
__global__ void recover_results(int *results, const int ... | .file "tmpxft_00008d94_00000000-6_recover_results.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ void recover_results(short *results, const int search_depth, const int total_dl_matrix_row_num) {
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
if (results[i] == search_depth) {
results[i] = 0;
}
}
}
__global__ void recover_results(int *results, const int ... | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void recover_results(short *results, const int search_depth, const int total_dl_matrix_row_num) {
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
if (results[i] == search_depth) {
results[i] = 0;
}
}
}
__global__ void recover_res... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void recover_results(short *results, const int search_depth, const int total_dl_matrix_row_num) {
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
if (results[i] == search_depth) {
results[i] = 0;
}
}
}
__global__ void recover_res... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15recover_resultsPiii
.globl _Z15recover_resultsPiii
.p2align 8
.type _Z15recover_resultsPiii,@function
_Z15recover_resultsPiii:
s_load_b32 s4, s[0:1], 0xc
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ void recover_results(short *results, const int search_depth, const int total_dl_matrix_row_num) {
for (int i = threadIdx.x; i < total_dl_matrix_row_num; i = i + blockDim.x) {
if (results[i] == search_depth) {
results[i] = 0;
}
}
}
__global__ void recover_res... | .text
.file "recover_results.hip"
.globl _Z30__device_stub__recover_resultsPiii # -- Begin function _Z30__device_stub__recover_resultsPiii
.p2align 4, 0x90
.type _Z30__device_stub__recover_resultsPiii,@function
_Z30__device_stub__recover_resultsPiii: # @_Z30__device_stub__recover_resultsPiii
.cfi_startproc
# %bb.0:
sub... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15recover_resultsPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e2... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15recover_resultsPiii
.globl _Z15recover_resultsPiii
.p2align 8
.type _Z15recover_resultsPiii,@function
_Z15recover_resultsPiii:
s_load_b32 s4, s[0:1], 0xc
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz ... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00008d94_00000000-6_recover_results.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $... | .text
.file "recover_results.hip"
.globl _Z30__device_stub__recover_resultsPiii # -- Begin function _Z30__device_stub__recover_resultsPiii
.p2align 4, 0x90
.type _Z30__device_stub__recover_resultsPiii,@function
_Z30__device_stub__recover_resultsPiii: # @_Z30__device_stub__recover_resultsPiii
.cfi_startproc
# %bb.0:
sub... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <math.h>
#define THREAD_COUNT 1024
__global__ void init(float *input, float *map, int w, int h)
{
unsigned int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < w * h)
{
int x = index % w;
int y = index / w;
if (input... | .file "tmpxft_0013205c_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <math.h>
#define THREAD_COUNT 1024
__global__ void init(float *input, float *map, int w, int h)
{
unsigned int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < w * h)
{
int x = index % w;
int y = index / w;
if (input... | #include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define THREAD_COUNT 1024
__global__ void init(float *input, float *map, int w, int h)
{
unsigned int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < w * h)
{
int x = index % w;
int y = index / w;
if (in... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <math.h>
#define THREAD_COUNT 1024
__global__ void init(float *input, float *map, int w, int h)
{
unsigned int index = threadIdx.x + blockIdx.x * blockDim.x;
if (index < w * h)
{
int x = index % w;
int y = index / w;
if (in... | .text
.file "main.hip"
.globl _Z19__device_stub__initPfS_ii # -- Begin function _Z19__device_stub__initPfS_ii
.p2align 4, 0x90
.type _Z19__device_stub__initPfS_ii,@function
_Z19__device_stub__initPfS_ii: # @_Z19__device_stub__initPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rd... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013205c_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "main.hip"
.globl _Z19__device_stub__initPfS_ii # -- Begin function _Z19__device_stub__initPfS_ii
.p2align 4, 0x90
.type _Z19__device_stub__initPfS_ii,@function
_Z19__device_stub__initPfS_ii: # @_Z19__device_stub__initPfS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rd... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <limits>
#include <sys/time.h>
#include <time.h>
#include <cuda_runtime.h>
using namespace std;
__global__ void assignmentKernel(float* d_in, float* d_out, int threads_num) {
const unsigned int tid = blockIdx.x * blockDim.x + threadId... | code for sm_80
Function : _Z16assignmentKernelPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x0... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <limits>
#include <sys/time.h>
#include <time.h>
#include <cuda_runtime.h>
using namespace std;
__global__ void assignmentKernel(float* d_in, float* d_out, int threads_num) {
const unsigned int tid = blockIdx.x * blockDim.x + threadId... | .file "tmpxft_000876cc_00000000-6_task4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <limits>
#include <sys/time.h>
#include <time.h>
#include <cuda_runtime.h>
using namespace std;
__global__ void assignmentKernel(float* d_in, float* d_out, int threads_num) {
const unsigned int tid = blockIdx.x * blockDim.x + threadId... | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <limits>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void assignmentKernel(float* d_in, float* d_out, int threads_num) {
const unsigned int tid = blockIdx.x * blockDim.x + threa... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <limits>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void assignmentKernel(float* d_in, float* d_out, int threads_num) {
const unsigned int tid = blockIdx.x * blockDim.x + threa... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16assignmentKernelPfS_i
.globl _Z16assignmentKernelPfS_i
.p2align 8
.type _Z16assignmentKernelPfS_i,@function
_Z16assignmentKernelPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <limits>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
using namespace std;
__global__ void assignmentKernel(float* d_in, float* d_out, int threads_num) {
const unsigned int tid = blockIdx.x * blockDim.x + threa... | .text
.file "task4.hip"
.globl _Z31__device_stub__assignmentKernelPfS_i # -- Begin function _Z31__device_stub__assignmentKernelPfS_i
.p2align 4, 0x90
.type _Z31__device_stub__assignmentKernelPfS_i,@function
_Z31__device_stub__assignmentKernelPfS_i: # @_Z31__device_stub__assignmentKernelPfS_i
.cfi_startproc
# %bb.0:
sub... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000876cc_00000000-6_task4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... | .text
.file "task4.hip"
.globl _Z31__device_stub__assignmentKernelPfS_i # -- Begin function _Z31__device_stub__assignmentKernelPfS_i
.p2align 4, 0x90
.type _Z31__device_stub__assignmentKernelPfS_i,@function
_Z31__device_stub__assignmentKernelPfS_i: # @_Z31__device_stub__assignmentKernelPfS_i
.cfi_startproc
# %bb.0:
sub... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "phong_implement.h"
#include "brdf_common.h"
__global__ void
phong_kernel(float3* pos, unsigned int width, float3 V, float3 N, float exposure, int divideByNdotL)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 L = calculateL(pos, width, x, y... | .file "tmpxft_0017a259_00000000-6_phong.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2041:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "phong_implement.h"
#include "brdf_common.h"
__global__ void
phong_kernel(float3* pos, unsigned int width, float3 V, float3 N, float exposure, int divideByNdotL)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 L = calculateL(pos, width, x, y... | #include <hip/hip_runtime.h>
#include "phong_implement.h"
#include "brdf_common.h"
__global__ void
phong_kernel(float3* pos, unsigned int width, float3 V, float3 N, float exposure, int divideByNdotL)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 L ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "phong_implement.h"
#include "brdf_common.h"
__global__ void
phong_kernel(float3* pos, unsigned int width, float3 V, float3 N, float exposure, int divideByNdotL)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 L ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi
.globl _Z12phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi
.p2align 8
.type _Z12phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi,@function
_Z12phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi:
s_clause 0x1
s_loa... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "phong_implement.h"
#include "brdf_common.h"
__global__ void
phong_kernel(float3* pos, unsigned int width, float3 V, float3 N, float exposure, int divideByNdotL)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y*blockDim.y + threadIdx.y;
float3 L ... | .text
.file "phong.hip"
.globl _Z27__device_stub__phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi # -- Begin function _Z27__device_stub__phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi
.p2align 4, 0x90
.type _Z27__device_stub__phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi,@function
_Z27__device_stub__phong_kernelP15HIP_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017a259_00000000-6_phong.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2041:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... | .text
.file "phong.hip"
.globl _Z27__device_stub__phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi # -- Begin function _Z27__device_stub__phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi
.p2align 4, 0x90
.type _Z27__device_stub__phong_kernelP15HIP_vector_typeIfLj3EEjS0_S0_fi,@function
_Z27__device_stub__phong_kernelP15HIP_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the... | .file "tmpxft_000c9cf0_00000000-6_Sigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the... | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* NiuTrans.Tensor - an open-source tensor library
* Copyright (C) 2017, Natural Language Processing Lab, Northeastern University.
* All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the... | .text
.file "Sigmoid.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c9cf0_00000000-6_Sigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3094:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
... | .text
.file "Sigmoid.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define z11 0
#define z12 6
#define z13 12
#define z21 13
#define z22 19
#define z23 25
#include <iostream>
void update(double R[6][6], double Rt[6][6], double zeta1[], double zeta2[], int n, int bodynum, int zetanum);
void MSsetup(double Minv[6][6],double S[6][6],double m, double I[3][3]);
void makeSt(double S[6][6], ... | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define z11 0
#define z12 6
#define z13 12
#define z21 13
#define z22 19
#define z23 25
#include <iostream>
void update(double R[6][6], double Rt[6][6], double zeta1[], double zeta2[], int n, int bodynum, int zetanum);
void MSsetup(double Minv[6][6],double S[6][6],double m, double I[3][3]);
void makeSt(double S[6][6], ... | .file "tmpxft_000a4faf_00000000-6_updatezetas.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cu... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define z11 0
#define z12 6
#define z13 12
#define z21 13
#define z22 19
#define z23 25
#include <iostream>
void update(double R[6][6], double Rt[6][6], double zeta1[], double zeta2[], int n, int bodynum, int zetanum);
void MSsetup(double Minv[6][6],double S[6][6],double m, double I[3][3]);
void makeSt(double S[6][6], ... | #define z11 0
#define z12 6
#define z13 12
#define z21 13
#define z22 19
#define z23 25
#include <hip/hip_runtime.h>
#include <iostream>
void update(double R[6][6], double Rt[6][6], double zeta1[], double zeta2[], int n, int bodynum, int zetanum);
void MSsetup(double Minv[6][6],double S[6][6],double m, double I[3][3]);... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define z11 0
#define z12 6
#define z13 12
#define z21 13
#define z22 19
#define z23 25
#include <hip/hip_runtime.h>
#include <iostream>
void update(double R[6][6], double Rt[6][6], double zeta1[], double zeta2[], int n, int bodynum, int zetanum);
void MSsetup(double Minv[6][6],double S[6][6],double m, double I[3][3]);... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define z11 0
#define z12 6
#define z13 12
#define z21 13
#define z22 19
#define z23 25
#include <hip/hip_runtime.h>
#include <iostream>
void update(double R[6][6], double Rt[6][6], double zeta1[], double zeta2[], int n, int bodynum, int zetanum);
void MSsetup(double Minv[6][6],double S[6][6],double m, double I[3][3]);... | .text
.file "updatezetas.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a4faf_00000000-6_updatezetas.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cu... | .text
.file "updatezetas.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
using namespace std;
#define CUDA_CHECK(condition) \
/* Code block avoids redefinition of cudaError_t error */ \
do { \
cudaError_t error = condition; \
if (error != cudaSuccess) { \
cout << cudaGetErrorString(error) << endl; \
} \
} while (0)
__global__
void add_vecs(int n, float *x, float *y, floa... | code for sm_80
Function : _Z8add_vecsiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*002... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
using namespace std;
#define CUDA_CHECK(condition) \
/* Code block avoids redefinition of cudaError_t error */ \
do { \
cudaError_t error = condition; \
if (error != cudaSuccess) { \
cout << cudaGetErrorString(error) << endl; \
} \
} while (0)
__global__
void add_vecs(int n, float *x, float *y, floa... | .file "tmpxft_0019a07d_00000000-6_testing_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
using namespace std;
#define CUDA_CHECK(condition) \
/* Code block avoids redefinition of cudaError_t error */ \
do { \
cudaError_t error = condition; \
if (error != cudaSuccess) { \
cout << cudaGetErrorString(error) << endl; \
} \
} while (0)
__global__
void add_vecs(int n, float *x, float *y, floa... | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define CUDA_CHECK(condition) \
/* Code block avoids redefinition of cudaError_t error */ \
do { \
hipError_t error = condition; \
if (error != hipSuccess) { \
cout << hipGetErrorString(error) << endl; \
} \
} while (0)
__global__
void add_vecs(int n... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define CUDA_CHECK(condition) \
/* Code block avoids redefinition of cudaError_t error */ \
do { \
hipError_t error = condition; \
if (error != hipSuccess) { \
cout << hipGetErrorString(error) << endl; \
} \
} while (0)
__global__
void add_vecs(int n... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_vecsiPfS_S_
.globl _Z8add_vecsiPfS_S_
.p2align 8
.type _Z8add_vecsiPfS_S_,@function
_Z8add_vecsiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
using namespace std;
#define CUDA_CHECK(condition) \
/* Code block avoids redefinition of cudaError_t error */ \
do { \
hipError_t error = condition; \
if (error != hipSuccess) { \
cout << hipGetErrorString(error) << endl; \
} \
} while (0)
__global__
void add_vecs(int n... | .text
.file "testing_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__add_vecsiPfS_S_ # -- Begin function _Z23__device_stub__add_vecsiPfS_S_
.p2a... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8add_vecsiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*002... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8add_vecsiPfS_S_
.globl _Z8add_vecsiPfS_S_
.p2align 8
.type _Z8add_vecsiPfS_S_,@function
_Z8add_vecsiPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019a07d_00000000-6_testing_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __c... | .text
.file "testing_cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__add_vecsiPfS_S_ # -- Begin function _Z23__device_stub__add_vecsiPfS_S_
.p2a... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// listPrimes - shows the prime numbers between a fixed range.
// Eric McCreath 2019 - GPL
// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number
long intsquroot(long n) {
long shift = 2;
long nShifted = n >> shift;
while (nShifted != 0 && nShifted != n) {
shift +=... | code for sm_80
Function : _Z12checkFactorsll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e2800... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// listPrimes - shows the prime numbers between a fixed range.
// Eric McCreath 2019 - GPL
// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number
long intsquroot(long n) {
long shift = 2;
long nShifted = n >> shift;
while (nShifted != 0 && nShifted != n) {
shift +=... | .file "tmpxft_00121b9b_00000000-6_listprimesCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// listPrimes - shows the prime numbers between a fixed range.
// Eric McCreath 2019 - GPL
// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number
long intsquroot(long n) {
long shift = 2;
long nShifted = n >> shift;
while (nShifted != 0 && nShifted != n) {
shift +=... | #include <hip/hip_runtime.h>
#include <stdio.h>
// listPrimes - shows the prime numbers between a fixed range.
// Eric McCreath 2019 - GPL
// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number
long intsquroot(long n) {
long shift = 2;
long nShifted = n >> shift;
while (nShifted != 0... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// listPrimes - shows the prime numbers between a fixed range.
// Eric McCreath 2019 - GPL
// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number
long intsquroot(long n) {
long shift = 2;
long nShifted = n >> shift;
while (nShifted != 0... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12checkFactorsll
.globl _Z12checkFactorsll
.p2align 8
.type _Z12checkFactorsll,@function
_Z12checkFactorsll:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitc... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// listPrimes - shows the prime numbers between a fixed range.
// Eric McCreath 2019 - GPL
// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number
long intsquroot(long n) {
long shift = 2;
long nShifted = n >> shift;
while (nShifted != 0... | .text
.file "listprimesCUDA.hip"
.globl _Z10intsqurootl # -- Begin function _Z10intsqurootl
.p2align 4, 0x90
.type _Z10intsqurootl,@function
_Z10intsqurootl: # @_Z10intsqurootl
.cfi_startproc
# %bb.0:
movl $2, %edx
cmpq $4, %rdi
jb .LBB0_4
# %bb.1:
movq %rdi, %rax
sarq $2, %rax
.p... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12checkFactorsll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e2800... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12checkFactorsll
.globl _Z12checkFactorsll
.p2align 8
.type _Z12checkFactorsll,@function
_Z12checkFactorsll:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 16
s_addc_u32 s5, s1, 0
s_waitc... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00121b9b_00000000-6_listprimesCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "listprimesCUDA.hip"
.globl _Z10intsqurootl # -- Begin function _Z10intsqurootl
.p2align 4, 0x90
.type _Z10intsqurootl,@function
_Z10intsqurootl: # @_Z10intsqurootl
.cfi_startproc
# %bb.0:
movl $2, %edx
cmpq $4, %rdi
jb .LBB0_4
# %bb.1:
movq %rdi, %rax
sarq $2, %rax
.p... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ComputeDerivativesKernel(int width, int height, int stride, float* Ix, float* Iy, float* Iz, cudaTextureObject_t texSource, cudaTextureObject_t texTarget)
{
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
const int iy = threadIdx.y + blockIdx.y * blockDim.y;
if (ix >= width |... | .file "tmpxft_001a4a98_00000000-6_ComputeDerivativesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@P... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ComputeDerivativesKernel(int width, int height, int stride, float* Ix, float* Iy, float* Iz, cudaTextureObject_t texSource, cudaTextureObject_t texTarget)
{
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
const int iy = threadIdx.y + blockIdx.y * blockDim.y;
if (ix >= width |... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeDerivativesKernel(int width, int height, int stride, float* Ix, float* Iy, float* Iz, hipTextureObject_t texSource, hipTextureObject_t texTarget)
{
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
const int iy = threadIdx.y + blockIdx.y * bl... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeDerivativesKernel(int width, int height, int stride, float* Ix, float* Iy, float* Iz, hipTextureObject_t texSource, hipTextureObject_t texTarget)
{
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
const int iy = threadIdx.y + blockIdx.y * bl... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_
.globl _Z24ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_
.p2align 8
.type _Z24ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_,@function
_Z24ComputeDerivativesKerneliiiPfS_S_P13__hip_texture... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeDerivativesKernel(int width, int height, int stride, float* Ix, float* Iy, float* Iz, hipTextureObject_t texSource, hipTextureObject_t texTarget)
{
const int ix = threadIdx.x + blockIdx.x * blockDim.x;
const int iy = threadIdx.y + blockIdx.y * bl... | .text
.file "ComputeDerivativesKernel.hip"
.globl _Z39__device_stub__ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_ # -- Begin function _Z39__device_stub__ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_
.p2align 4, 0x90
.type _Z39__device_stub__ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_,@function
_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a4a98_00000000-6_ComputeDerivativesKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@P... | .text
.file "ComputeDerivativesKernel.hip"
.globl _Z39__device_stub__ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_ # -- Begin function _Z39__device_stub__ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_
.p2align 4, 0x90
.type _Z39__device_stub__ComputeDerivativesKerneliiiPfS_S_P13__hip_textureS1_,@function
_... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //------------------------------------------------------------------------------
//
// Name: vadd.cu
//
// Purpose: CUDA implementation of VADD
//
// HISTORY: Written by Tom Deakin and Simon McIntosh-Smith, August 2013
//
//------------------------------------------------------------------------------
#include <stdio.h... | code for sm_80
Function : _Z4vaddPKfS0_Pfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //------------------------------------------------------------------------------
//
// Name: vadd.cu
//
// Purpose: CUDA implementation of VADD
//
// HISTORY: Written by Tom Deakin and Simon McIntosh-Smith, August 2013
//
//------------------------------------------------------------------------------
#include <stdio.h... | .file "tmpxft_00123527_00000000-6_vadd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //------------------------------------------------------------------------------
//
// Name: vadd.cu
//
// Purpose: CUDA implementation of VADD
//
// HISTORY: Written by Tom Deakin and Simon McIntosh-Smith, August 2013
//
//------------------------------------------------------------------------------
#include <stdio.h... | //------------------------------------------------------------------------------
//
// Name: vadd.cu
//
// Purpose: CUDA implementation of VADD
//
// HISTORY: Written by Tom Deakin and Simon McIntosh-Smith, August 2013
//
//------------------------------------------------------------------------------
#include <stdio.h... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //------------------------------------------------------------------------------
//
// Name: vadd.cu
//
// Purpose: CUDA implementation of VADD
//
// HISTORY: Written by Tom Deakin and Simon McIntosh-Smith, August 2013
//
//------------------------------------------------------------------------------
#include <stdio.h... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4vaddPKfS0_Pfj
.globl _Z4vaddPKfS0_Pfj
.p2align 8
.type _Z4vaddPKfS0_Pfj,@function
_Z4vaddPKfS0_Pfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_al... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //------------------------------------------------------------------------------
//
// Name: vadd.cu
//
// Purpose: CUDA implementation of VADD
//
// HISTORY: Written by Tom Deakin and Simon McIntosh-Smith, August 2013
//
//------------------------------------------------------------------------------
#include <stdio.h... | .text
.file "vadd.hip"
.globl _Z19__device_stub__vaddPKfS0_Pfj # -- Begin function _Z19__device_stub__vaddPKfS0_Pfj
.p2align 4, 0x90
.type _Z19__device_stub__vaddPKfS0_Pfj,@function
_Z19__device_stub__vaddPKfS0_Pfj: # @_Z19__device_stub__vaddPKfS0_Pfj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 12... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4vaddPKfS0_Pfj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4vaddPKfS0_Pfj
.globl _Z4vaddPKfS0_Pfj
.p2align 8
.type _Z4vaddPKfS0_Pfj,@function
_Z4vaddPKfS0_Pfj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_al... |
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