system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
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You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;
const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);
void block_FW_2GPU(int B);
int ceil(int a, int b);
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);
int realn;
int n, m; // Number of vertices, edges
int* Dist; // n * n, on host
int* dDist[2]; // n * n, on device
int streamSize[2];
vector<cudaStream_t> streams[2];
int getGPUId ()
{
int gpuId;
cudaGetDevice(&gpuId);
return gpuId;
}
cudaStream_t getIdleStream (int gpuId)
{
cudaSetDevice(gpuId);
if(streams[gpuId].size() == streamSize[gpuId])
{
cudaStream_t stm;
cudaStreamCreate(&stm);
streams[gpuId].push_back(stm);
streamSize[gpuId]++;
return stm;
}
else
return streams[gpuId][streamSize[gpuId]++];
}
void syncAllStreams ()
{
cudaThreadSynchronize();
streamSize[0] = 0;
streamSize[1] = 0;
}
void blockCopyAsync (int gpuId, int* dst, const int* src, cudaMemcpyKind kind, cudaStream_t stream, int B, int bi0, int bi1, int bj0, int bj1)
{
cudaSetDevice(gpuId);
for(int i = bi0 * B; i < bi1 * B; ++i)
{
int offset = i * n + bj0 * B;
int size = (bj1 - bj0) * B * sizeof(int);
cudaMemcpyAsync(dst + offset, src + offset, size, kind, stream);
}
}
int main(int argc, char* argv[])
{
int B = atoi(argv[3]);
input(argv[1], B);
block_FW_2GPU(B);
output(argv[2]);
return 0;
}
void input(char *inFileName, int B)
{
FILE *infile = fopen(inFileName, "r");
fscanf(infile, "%d %d", &realn, &m);
n = ceil(realn, B) * B;
cudaMallocManaged(&Dist, n * n * sizeof(int));
for (int i = 0, k = 0; i < n; ++i) {
for (int j = 0; j < n; ++j, ++k) {
if (i == j) Dist[k] = 0;
else Dist[k] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
--a, --b;
Dist[a * n + b] = v;
}
}
void output(char *outFileName)
{
FILE *outfile = fopen(outFileName, "w");
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", d);
}
fprintf(outfile, "\n");
}
cudaFree(Dist);
}
void print ()
{
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(stderr, "INF ");
else fprintf(stderr, "%d ", d);
}
fprintf(stderr, "\n");
}
fprintf(stderr, "\n");
}
int ceil(int a, int b)
{
return (a + b -1)/b;
}
void block_FW_2GPU(int B)
{
int round = ceil(n, B);
for (int r = 0; r < round; ++r) {
/* Phase 1*/
fprintf(stderr, "Round: %d\n", r);
calAsync(0, B, r, r, r, 1, 1);
syncAllStreams();
/* Phase 2*/
calAsync(0, B, r, r, 0, r, 1); // L 0
calAsync(0, B, r, r, r +1, round - r -1, 1); // R 0
calAsync(1, B, r, 0, r, 1, r); // U 1
calAsync(1, B, r, r +1, r, 1, round - r -1); // D 1
syncAllStreams();
/* Phase 3*/
calAsync(0, B, r, 0, 0, r, r); // <^
calAsync(1, B, r, 0, r +1, round -r -1, r); // ^>
calAsync(1, B, r, r +1, 0, r, round - r -1); // <v
calAsync(0, B, r, r +1, r +1, round -r -1, round - r -1); // v>
syncAllStreams();
}
}
__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
if(i >= i1 || j >= j1)
return;
int Dik = D(i, k);
int Dkj = D(k, j);
int D1 = Dik + Dkj;
if (D1 < D(i, j))
D(i, j) = D1;
}
__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int di = blockDim.x * blockIdx.x + tx;
int dj = blockDim.y * blockIdx.y + ty;
int i = i0 + di;
int j = j0 + dj;
bool valid = i < i1 && j < j1;
__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
const int cacheSize = MAX_THREAD_DIM2;
int Dij = valid? D(i, j): 0;
int dkmod = 0;
for(int k = k0; k < k1; ++k)
{
if(dkmod == 0)
{
__syncthreads();
if(i < i1 && k+ty < k1)
Si[ty][tx] = D(i, k+ty);
if(j < j1 && k+tx < k1)
Sj[tx][ty] = D(k+tx, j);
__syncthreads();
}
if(valid)
{
// assert(Si[tx][dkmod] == D(i,k));
// assert(Sj[dkmod][ty] == D(k,j));
// int Dik = D(i, k);
// int Dkj = D(k, j);
int Dik = Si[dkmod][tx];
int Dkj = Sj[dkmod][ty];
int D1 = Dik + Dkj;
if (D1 < Dij)
Dij = D1;
}
dkmod = (dkmod + 1) % cacheSize;
}
if(valid)
D(i, j) = Dij;
}
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
cudaSetDevice(gpuId);
int block_end_x = block_start_x + block_height;
int block_end_y = block_start_y + block_width;
for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
// To calculate B*B elements in the block (b_i, b_j)
// For each block, it need to compute B times
// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
// To calculate original index of elements in the block (b_i, b_j)
// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
int i0 = b_i * B;
int i1 = min((b_i +1) * B, n);
int j0 = b_j * B;
int j1 = min((b_j +1) * B, n);
int k0 = Round * B;
int k1 = min((Round +1) * B, n);
bool iDepends = i0 == k0;
bool jDepends = j0 == k0;
int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
cudaStream_t stm = getIdleStream(gpuId);
if(iDepends || jDepends)
{
for(int k=k0; k<k1; ++k)
Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, Dist, n);
}
else
UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, Dist, n);
// for (int i = i0; i < i1; ++i) {
// for (int j = j0; j < j1; ++j) {
// if (Dist[i][k] + Dist[k][j] < Dist[i][j])
// Dist[i][j] = Dist[i][k] + Dist[k][j];
// }
// }
// }
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;
const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);
void block_FW_2GPU(int B);
int ceil(int a, int b);
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);
int realn;
int n, m; // Number of vertices, edges
int* Dist; // n * n, on host
int* dDist[2]; // n * n, on device
int streamSize[2];
vector<hipStream_t> streams[2];
int getGPUId ()
{
int gpuId;
hipGetDevice(&gpuId);
return gpuId;
}
hipStream_t getIdleStream (int gpuId)
{
hipSetDevice(gpuId);
if(streams[gpuId].size() == streamSize[gpuId])
{
hipStream_t stm;
hipStreamCreate(&stm);
streams[gpuId].push_back(stm);
streamSize[gpuId]++;
return stm;
}
else
return streams[gpuId][streamSize[gpuId]++];
}
void syncAllStreams ()
{
hipDeviceSynchronize();
streamSize[0] = 0;
streamSize[1] = 0;
}
void blockCopyAsync (int gpuId, int* dst, const int* src, hipMemcpyKind kind, hipStream_t stream, int B, int bi0, int bi1, int bj0, int bj1)
{
hipSetDevice(gpuId);
for(int i = bi0 * B; i < bi1 * B; ++i)
{
int offset = i * n + bj0 * B;
int size = (bj1 - bj0) * B * sizeof(int);
hipMemcpyAsync(dst + offset, src + offset, size, kind, stream);
}
}
int main(int argc, char* argv[])
{
int B = atoi(argv[3]);
input(argv[1], B);
block_FW_2GPU(B);
output(argv[2]);
return 0;
}
void input(char *inFileName, int B)
{
FILE *infile = fopen(inFileName, "r");
fscanf(infile, "%d %d", &realn, &m);
n = ceil(realn, B) * B;
hipMallocManaged(&Dist, n * n * sizeof(int));
for (int i = 0, k = 0; i < n; ++i) {
for (int j = 0; j < n; ++j, ++k) {
if (i == j) Dist[k] = 0;
else Dist[k] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
--a, --b;
Dist[a * n + b] = v;
}
}
void output(char *outFileName)
{
FILE *outfile = fopen(outFileName, "w");
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", d);
}
fprintf(outfile, "\n");
}
hipFree(Dist);
}
void print ()
{
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(stderr, "INF ");
else fprintf(stderr, "%d ", d);
}
fprintf(stderr, "\n");
}
fprintf(stderr, "\n");
}
int ceil(int a, int b)
{
return (a + b -1)/b;
}
void block_FW_2GPU(int B)
{
int round = ceil(n, B);
for (int r = 0; r < round; ++r) {
/* Phase 1*/
fprintf(stderr, "Round: %d\n", r);
calAsync(0, B, r, r, r, 1, 1);
syncAllStreams();
/* Phase 2*/
calAsync(0, B, r, r, 0, r, 1); // L 0
calAsync(0, B, r, r, r +1, round - r -1, 1); // R 0
calAsync(1, B, r, 0, r, 1, r); // U 1
calAsync(1, B, r, r +1, r, 1, round - r -1); // D 1
syncAllStreams();
/* Phase 3*/
calAsync(0, B, r, 0, 0, r, r); // <^
calAsync(1, B, r, 0, r +1, round -r -1, r); // ^>
calAsync(1, B, r, r +1, 0, r, round - r -1); // <v
calAsync(0, B, r, r +1, r +1, round -r -1, round - r -1); // v>
syncAllStreams();
}
}
__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
if(i >= i1 || j >= j1)
return;
int Dik = D(i, k);
int Dkj = D(k, j);
int D1 = Dik + Dkj;
if (D1 < D(i, j))
D(i, j) = D1;
}
__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int di = blockDim.x * blockIdx.x + tx;
int dj = blockDim.y * blockIdx.y + ty;
int i = i0 + di;
int j = j0 + dj;
bool valid = i < i1 && j < j1;
__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
const int cacheSize = MAX_THREAD_DIM2;
int Dij = valid? D(i, j): 0;
int dkmod = 0;
for(int k = k0; k < k1; ++k)
{
if(dkmod == 0)
{
__syncthreads();
if(i < i1 && k+ty < k1)
Si[ty][tx] = D(i, k+ty);
if(j < j1 && k+tx < k1)
Sj[tx][ty] = D(k+tx, j);
__syncthreads();
}
if(valid)
{
// assert(Si[tx][dkmod] == D(i,k));
// assert(Sj[dkmod][ty] == D(k,j));
// int Dik = D(i, k);
// int Dkj = D(k, j);
int Dik = Si[dkmod][tx];
int Dkj = Sj[dkmod][ty];
int D1 = Dik + Dkj;
if (D1 < Dij)
Dij = D1;
}
dkmod = (dkmod + 1) % cacheSize;
}
if(valid)
D(i, j) = Dij;
}
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
hipSetDevice(gpuId);
int block_end_x = block_start_x + block_height;
int block_end_y = block_start_y + block_width;
for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
// To calculate B*B elements in the block (b_i, b_j)
// For each block, it need to compute B times
// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
// To calculate original index of elements in the block (b_i, b_j)
// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
int i0 = b_i * B;
int i1 = min((b_i +1) * B, n);
int j0 = b_j * B;
int j1 = min((b_j +1) * B, n);
int k0 = Round * B;
int k1 = min((Round +1) * B, n);
bool iDepends = i0 == k0;
bool jDepends = j0 == k0;
int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
hipStream_t stm = getIdleStream(gpuId);
if(iDepends || jDepends)
{
for(int k=k0; k<k1; ++k)
Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, Dist, n);
}
else
UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, Dist, n);
// for (int i = i0; i < i1; ++i) {
// for (int j = j0; j < j1; ++j) {
// if (Dist[i][k] + Dist[k][j] < Dist[i][j])
// Dist[i][j] = Dist[i][k] + Dist[k][j];
// }
// }
// }
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;
const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);
void block_FW_2GPU(int B);
int ceil(int a, int b);
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);
int realn;
int n, m; // Number of vertices, edges
int* Dist; // n * n, on host
int* dDist[2]; // n * n, on device
int streamSize[2];
vector<hipStream_t> streams[2];
int getGPUId ()
{
int gpuId;
hipGetDevice(&gpuId);
return gpuId;
}
hipStream_t getIdleStream (int gpuId)
{
hipSetDevice(gpuId);
if(streams[gpuId].size() == streamSize[gpuId])
{
hipStream_t stm;
hipStreamCreate(&stm);
streams[gpuId].push_back(stm);
streamSize[gpuId]++;
return stm;
}
else
return streams[gpuId][streamSize[gpuId]++];
}
void syncAllStreams ()
{
hipDeviceSynchronize();
streamSize[0] = 0;
streamSize[1] = 0;
}
void blockCopyAsync (int gpuId, int* dst, const int* src, hipMemcpyKind kind, hipStream_t stream, int B, int bi0, int bi1, int bj0, int bj1)
{
hipSetDevice(gpuId);
for(int i = bi0 * B; i < bi1 * B; ++i)
{
int offset = i * n + bj0 * B;
int size = (bj1 - bj0) * B * sizeof(int);
hipMemcpyAsync(dst + offset, src + offset, size, kind, stream);
}
}
int main(int argc, char* argv[])
{
int B = atoi(argv[3]);
input(argv[1], B);
block_FW_2GPU(B);
output(argv[2]);
return 0;
}
void input(char *inFileName, int B)
{
FILE *infile = fopen(inFileName, "r");
fscanf(infile, "%d %d", &realn, &m);
n = ceil(realn, B) * B;
hipMallocManaged(&Dist, n * n * sizeof(int));
for (int i = 0, k = 0; i < n; ++i) {
for (int j = 0; j < n; ++j, ++k) {
if (i == j) Dist[k] = 0;
else Dist[k] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
--a, --b;
Dist[a * n + b] = v;
}
}
void output(char *outFileName)
{
FILE *outfile = fopen(outFileName, "w");
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", d);
}
fprintf(outfile, "\n");
}
hipFree(Dist);
}
void print ()
{
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(stderr, "INF ");
else fprintf(stderr, "%d ", d);
}
fprintf(stderr, "\n");
}
fprintf(stderr, "\n");
}
int ceil(int a, int b)
{
return (a + b -1)/b;
}
void block_FW_2GPU(int B)
{
int round = ceil(n, B);
for (int r = 0; r < round; ++r) {
/* Phase 1*/
fprintf(stderr, "Round: %d\n", r);
calAsync(0, B, r, r, r, 1, 1);
syncAllStreams();
/* Phase 2*/
calAsync(0, B, r, r, 0, r, 1); // L 0
calAsync(0, B, r, r, r +1, round - r -1, 1); // R 0
calAsync(1, B, r, 0, r, 1, r); // U 1
calAsync(1, B, r, r +1, r, 1, round - r -1); // D 1
syncAllStreams();
/* Phase 3*/
calAsync(0, B, r, 0, 0, r, r); // <^
calAsync(1, B, r, 0, r +1, round -r -1, r); // ^>
calAsync(1, B, r, r +1, 0, r, round - r -1); // <v
calAsync(0, B, r, r +1, r +1, round -r -1, round - r -1); // v>
syncAllStreams();
}
}
__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
if(i >= i1 || j >= j1)
return;
int Dik = D(i, k);
int Dkj = D(k, j);
int D1 = Dik + Dkj;
if (D1 < D(i, j))
D(i, j) = D1;
}
__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int di = blockDim.x * blockIdx.x + tx;
int dj = blockDim.y * blockIdx.y + ty;
int i = i0 + di;
int j = j0 + dj;
bool valid = i < i1 && j < j1;
__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
const int cacheSize = MAX_THREAD_DIM2;
int Dij = valid? D(i, j): 0;
int dkmod = 0;
for(int k = k0; k < k1; ++k)
{
if(dkmod == 0)
{
__syncthreads();
if(i < i1 && k+ty < k1)
Si[ty][tx] = D(i, k+ty);
if(j < j1 && k+tx < k1)
Sj[tx][ty] = D(k+tx, j);
__syncthreads();
}
if(valid)
{
// assert(Si[tx][dkmod] == D(i,k));
// assert(Sj[dkmod][ty] == D(k,j));
// int Dik = D(i, k);
// int Dkj = D(k, j);
int Dik = Si[dkmod][tx];
int Dkj = Sj[dkmod][ty];
int D1 = Dik + Dkj;
if (D1 < Dij)
Dij = D1;
}
dkmod = (dkmod + 1) % cacheSize;
}
if(valid)
D(i, j) = Dij;
}
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
hipSetDevice(gpuId);
int block_end_x = block_start_x + block_height;
int block_end_y = block_start_y + block_width;
for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
// To calculate B*B elements in the block (b_i, b_j)
// For each block, it need to compute B times
// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
// To calculate original index of elements in the block (b_i, b_j)
// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
int i0 = b_i * B;
int i1 = min((b_i +1) * B, n);
int j0 = b_j * B;
int j1 = min((b_j +1) * B, n);
int k0 = Round * B;
int k1 = min((Round +1) * B, n);
bool iDepends = i0 == k0;
bool jDepends = j0 == k0;
int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
hipStream_t stm = getIdleStream(gpuId);
if(iDepends || jDepends)
{
for(int k=k0; k<k1; ++k)
Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, Dist, n);
}
else
UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, Dist, n);
// for (int i = i0; i < i1; ++i) {
// for (int j = j0; j < j1; ++j) {
// if (Dist[i][k] + Dist[k][j] < Dist[i][j])
// Dist[i][j] = Dist[i][k] + Dist[k][j];
// }
// }
// }
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6UpdateiiiiiPii
.globl _Z6UpdateiiiiiPii
.p2align 8
.type _Z6UpdateiiiiiPii,@function
_Z6UpdateiiiiiPii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x4
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add3_u32 v1, s14, s4, v1
v_add3_u32 v0, s15, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v1
v_cmp_gt_i32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_clause 0x2
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v5, v1, s2
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s3, v5
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[5:6], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_clause 0x1
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v2, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6UpdateiiiiiPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6UpdateiiiiiPii, .Lfunc_end0-_Z6UpdateiiiiiPii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17UpdateIndependentiiiiiiPii
.globl _Z17UpdateIndependentiiiiiiPii
.p2align 8
.type _Z17UpdateIndependentiiiiiiPii,@function
_Z17UpdateIndependentiiiiiiPii:
s_clause 0x3
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x8
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x20
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v7, 0x3ff, v0
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s14, s14, s3
s_mul_i32 s15, s15, s2
v_add3_u32 v5, s14, s8, v7
v_add3_u32 v0, s15, s9, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v5
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s8, vcc_lo, s2
s_and_saveexec_b32 s4, s8
s_cbranch_execz .LBB1_2
v_mad_u64_u32 v[2:3], null, v5, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s3, s6, v2
v_add_co_ci_u32_e64 v3, s3, s7, v3, s3
global_load_b32 v6, v[2:3], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s4, s5
s_cbranch_scc1 .LBB1_15
v_add_nc_u32_e32 v2, s4, v7
v_lshlrev_b32_e32 v4, 2, v7
v_lshlrev_b32_e32 v9, 2, v1
v_lshlrev_b32_e32 v11, 7, v7
v_add_nc_u32_e32 v12, s9, v1
v_mul_lo_u32 v10, s10, v2
v_mad_u64_u32 v[2:3], null, v5, s10, v[1:2]
v_lshl_add_u32 v8, v1, 7, v4
v_add3_u32 v9, v11, v9, 0x1000
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_4)
v_add3_u32 v3, v12, v10, s15
s_branch .LBB1_5
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s0
s_add_i32 s0, s1, 1
v_add_nc_u32_e32 v3, s10, v3
s_ashr_i32 s1, s0, 31
s_add_i32 s4, s4, 1
s_lshr_b32 s1, s1, 27
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s1, s0, s1
s_and_not1_b32 s1, s1, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s1, s0, s1
s_cmp_ge_i32 s4, s5
s_cbranch_scc1 .LBB1_15
.LBB1_5:
s_cmp_lg_u32 s1, 0
s_cbranch_scc0 .LBB1_7
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB1_4
s_branch .LBB1_14
.LBB1_7:
s_waitcnt vmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_10
v_add_nc_u32_e32 v4, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s5, v4
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_10
v_add_nc_u32_e32 v10, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s6, v10
v_add_co_ci_u32_e64 v11, s0, s7, v11, s0
global_load_b32 v4, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
.LBB1_10:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_13
v_add_nc_u32_e32 v4, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s5, v4
s_and_b32 exec_lo, exec_lo, s0
s_cbranch_execz .LBB1_13
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[3:4]
v_add_co_u32 v10, s0, s6, v10
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v11, s0, s7, v11, s0
global_load_b32 v4, v[10:11], off
s_waitcnt vmcnt(0)
ds_store_b32 v9, v4
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB1_4
.LBB1_14:
s_lshl_b32 s3, s1, 7
s_delay_alu instid0(SALU_CYCLE_1)
v_lshl_add_u32 v4, v7, 2, s3
v_lshl_add_u32 v10, v1, 2, s3
ds_load_b32 v4, v4
ds_load_b32 v10, v10 offset:4096
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v4, v10, v4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_i32_e32 v6, v4, v6
s_branch .LBB1_4
.LBB1_15:
s_and_saveexec_b32 s0, s8
s_cbranch_execz .LBB1_17
v_mad_u64_u32 v[1:2], null, v5, s10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v6, off
.LBB1_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17UpdateIndependentiiiiiiPii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17UpdateIndependentiiiiiiPii, .Lfunc_end1-_Z17UpdateIndependentiiiiiiPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6UpdateiiiiiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6UpdateiiiiiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17UpdateIndependentiiiiiiPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17UpdateIndependentiiiiiiPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;
const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);
void block_FW_2GPU(int B);
int ceil(int a, int b);
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);
int realn;
int n, m; // Number of vertices, edges
int* Dist; // n * n, on host
int* dDist[2]; // n * n, on device
int streamSize[2];
vector<hipStream_t> streams[2];
int getGPUId ()
{
int gpuId;
hipGetDevice(&gpuId);
return gpuId;
}
hipStream_t getIdleStream (int gpuId)
{
hipSetDevice(gpuId);
if(streams[gpuId].size() == streamSize[gpuId])
{
hipStream_t stm;
hipStreamCreate(&stm);
streams[gpuId].push_back(stm);
streamSize[gpuId]++;
return stm;
}
else
return streams[gpuId][streamSize[gpuId]++];
}
void syncAllStreams ()
{
hipDeviceSynchronize();
streamSize[0] = 0;
streamSize[1] = 0;
}
void blockCopyAsync (int gpuId, int* dst, const int* src, hipMemcpyKind kind, hipStream_t stream, int B, int bi0, int bi1, int bj0, int bj1)
{
hipSetDevice(gpuId);
for(int i = bi0 * B; i < bi1 * B; ++i)
{
int offset = i * n + bj0 * B;
int size = (bj1 - bj0) * B * sizeof(int);
hipMemcpyAsync(dst + offset, src + offset, size, kind, stream);
}
}
int main(int argc, char* argv[])
{
int B = atoi(argv[3]);
input(argv[1], B);
block_FW_2GPU(B);
output(argv[2]);
return 0;
}
void input(char *inFileName, int B)
{
FILE *infile = fopen(inFileName, "r");
fscanf(infile, "%d %d", &realn, &m);
n = ceil(realn, B) * B;
hipMallocManaged(&Dist, n * n * sizeof(int));
for (int i = 0, k = 0; i < n; ++i) {
for (int j = 0; j < n; ++j, ++k) {
if (i == j) Dist[k] = 0;
else Dist[k] = INF;
}
}
while (--m >= 0) {
int a, b, v;
fscanf(infile, "%d %d %d", &a, &b, &v);
--a, --b;
Dist[a * n + b] = v;
}
}
void output(char *outFileName)
{
FILE *outfile = fopen(outFileName, "w");
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(outfile, "INF ");
else fprintf(outfile, "%d ", d);
}
fprintf(outfile, "\n");
}
hipFree(Dist);
}
void print ()
{
for (int i = 0; i < realn; ++i) {
for (int j = 0; j < realn; ++j) {
int d = Dist[i * n + j];
if (d >= INF) fprintf(stderr, "INF ");
else fprintf(stderr, "%d ", d);
}
fprintf(stderr, "\n");
}
fprintf(stderr, "\n");
}
int ceil(int a, int b)
{
return (a + b -1)/b;
}
void block_FW_2GPU(int B)
{
int round = ceil(n, B);
for (int r = 0; r < round; ++r) {
/* Phase 1*/
fprintf(stderr, "Round: %d\n", r);
calAsync(0, B, r, r, r, 1, 1);
syncAllStreams();
/* Phase 2*/
calAsync(0, B, r, r, 0, r, 1); // L 0
calAsync(0, B, r, r, r +1, round - r -1, 1); // R 0
calAsync(1, B, r, 0, r, 1, r); // U 1
calAsync(1, B, r, r +1, r, 1, round - r -1); // D 1
syncAllStreams();
/* Phase 3*/
calAsync(0, B, r, 0, 0, r, r); // <^
calAsync(1, B, r, 0, r +1, round -r -1, r); // ^>
calAsync(1, B, r, r +1, 0, r, round - r -1); // <v
calAsync(0, B, r, r +1, r +1, round -r -1, round - r -1); // v>
syncAllStreams();
}
}
__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
if(i >= i1 || j >= j1)
return;
int Dik = D(i, k);
int Dkj = D(k, j);
int D1 = Dik + Dkj;
if (D1 < D(i, j))
D(i, j) = D1;
}
__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
#define D(i,j) (dDist[(i) * n + (j)])
int tx = threadIdx.x;
int ty = threadIdx.y;
int di = blockDim.x * blockIdx.x + tx;
int dj = blockDim.y * blockIdx.y + ty;
int i = i0 + di;
int j = j0 + dj;
bool valid = i < i1 && j < j1;
__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
const int cacheSize = MAX_THREAD_DIM2;
int Dij = valid? D(i, j): 0;
int dkmod = 0;
for(int k = k0; k < k1; ++k)
{
if(dkmod == 0)
{
__syncthreads();
if(i < i1 && k+ty < k1)
Si[ty][tx] = D(i, k+ty);
if(j < j1 && k+tx < k1)
Sj[tx][ty] = D(k+tx, j);
__syncthreads();
}
if(valid)
{
// assert(Si[tx][dkmod] == D(i,k));
// assert(Sj[dkmod][ty] == D(k,j));
// int Dik = D(i, k);
// int Dkj = D(k, j);
int Dik = Si[dkmod][tx];
int Dkj = Sj[dkmod][ty];
int D1 = Dik + Dkj;
if (D1 < Dij)
Dij = D1;
}
dkmod = (dkmod + 1) % cacheSize;
}
if(valid)
D(i, j) = Dij;
}
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
hipSetDevice(gpuId);
int block_end_x = block_start_x + block_height;
int block_end_y = block_start_y + block_width;
for (int b_i = block_start_x; b_i < block_end_x; ++b_i) {
for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
// To calculate B*B elements in the block (b_i, b_j)
// For each block, it need to compute B times
// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
// To calculate original index of elements in the block (b_i, b_j)
// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
int i0 = b_i * B;
int i1 = min((b_i +1) * B, n);
int j0 = b_j * B;
int j1 = min((b_j +1) * B, n);
int k0 = Round * B;
int k1 = min((Round +1) * B, n);
bool iDepends = i0 == k0;
bool jDepends = j0 == k0;
int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
hipStream_t stm = getIdleStream(gpuId);
if(iDepends || jDepends)
{
for(int k=k0; k<k1; ++k)
Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, Dist, n);
}
else
UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, Dist, n);
// for (int i = i0; i < i1; ++i) {
// for (int j = j0; j < j1; ++j) {
// if (Dist[i][k] + Dist[k][j] < Dist[i][j])
// Dist[i][j] = Dist[i][k] + Dist[k][j];
// }
// }
// }
}
}
} | .text
.file "HW4_x1054037_2GPU_Unified_bug.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function __cxx_global_array_dtor
.type __cxx_global_array_dtor,@function
__cxx_global_array_dtor: # @__cxx_global_array_dtor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl $48, %ebx
jmp .LBB0_1
.p2align 4, 0x90
.LBB0_3: # %_ZNSt6vectorIP12ihipStream_tSaIS1_EED2Ev.exit
# in Loop: Header=BB0_1 Depth=1
addq $-24, %rbx
je .LBB0_4
.LBB0_1: # =>This Inner Loop Header: Depth=1
movq streams-24(%rbx), %rdi
testq %rdi, %rdi
je .LBB0_3
# %bb.2: # in Loop: Header=BB0_1 Depth=1
callq _ZdlPv
jmp .LBB0_3
.LBB0_4:
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size __cxx_global_array_dtor, .Lfunc_end0-__cxx_global_array_dtor
.cfi_endproc
# -- End function
.text
.globl _Z8getGPUIdv # -- Begin function _Z8getGPUIdv
.p2align 4, 0x90
.type _Z8getGPUIdv,@function
_Z8getGPUIdv: # @_Z8getGPUIdv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
leaq 4(%rsp), %rdi
callq hipGetDevice
movl 4(%rsp), %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8getGPUIdv, .Lfunc_end1-_Z8getGPUIdv
.cfi_endproc
# -- End function
.globl _Z13getIdleStreami # -- Begin function _Z13getIdleStreami
.p2align 4, 0x90
.type _Z13getIdleStreami,@function
_Z13getIdleStreami: # @_Z13getIdleStreami
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
callq hipSetDevice
movslq %ebx, %r12
leaq (,%r12,8), %rcx
movq streams+8(%rcx,%rcx,2), %rsi
movq streams(%rcx,%rcx,2), %rax
subq %rax, %rsi
sarq $3, %rsi
movslq streamSize(,%r12,4), %rdx
cmpq %rdx, %rsi
jne .LBB2_13
# %bb.1:
leaq (%rcx,%rcx,2), %r13
addq $streams, %r13
leaq 8(%rsp), %rdi
callq hipStreamCreate
movq 8(%r13), %rbx
cmpq 16(%r13), %rbx
je .LBB2_3
# %bb.2:
movq 8(%rsp), %rax
movq %rax, (%rbx)
addq $8, 8(%r13)
jmp .LBB2_12
.LBB2_13:
leal 1(%rdx), %ecx
movl %ecx, streamSize(,%r12,4)
movq (%rax,%rdx,8), %rax
jmp .LBB2_14
.LBB2_3:
movq (%r13), %rax
movq %rax, 16(%rsp) # 8-byte Spill
subq %rax, %rbx
movabsq $9223372036854775800, %rax # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rax, %rbx
je .LBB2_15
# %bb.4: # %_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc.exit.i.i
movq %rbx, %r14
sarq $3, %r14
cmpq $1, %r14
movq %r14, %rax
adcq $0, %rax
leaq (%rax,%r14), %rbp
movabsq $1152921504606846975, %rcx # imm = 0xFFFFFFFFFFFFFFF
cmpq %rcx, %rbp
cmovaeq %rcx, %rbp
addq %r14, %rax
cmovbq %rcx, %rbp
testq %rbp, %rbp
je .LBB2_5
# %bb.6:
leaq (,%rbp,8), %rdi
callq _Znwm
movq %rax, %r15
jmp .LBB2_7
.LBB2_5:
xorl %r15d, %r15d
.LBB2_7: # %_ZNSt12_Vector_baseIP12ihipStream_tSaIS1_EE11_M_allocateEm.exit.i.i
movq 8(%rsp), %rax
movq %rax, (%r15,%r14,8)
testq %rbx, %rbx
movq 16(%rsp), %r14 # 8-byte Reload
jle .LBB2_9
# %bb.8:
movq %r15, %rdi
movq %r14, %rsi
movq %rbx, %rdx
callq memmove@PLT
.LBB2_9: # %_ZNSt6vectorIP12ihipStream_tSaIS1_EE11_S_relocateEPS1_S4_S4_RS2_.exit.i.i
addq %r15, %rbx
addq $8, %rbx
testq %r14, %r14
je .LBB2_11
# %bb.10:
movq %r14, %rdi
callq _ZdlPv
.LBB2_11: # %_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_.exit.i
movq %r15, (%r13)
movq %rbx, 8(%r13)
leaq (%r15,%rbp,8), %rax
movq %rax, 16(%r13)
.LBB2_12: # %_ZNSt6vectorIP12ihipStream_tSaIS1_EE9push_backERKS1_.exit
incl streamSize(,%r12,4)
movq 8(%rsp), %rax
.LBB2_14:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_15:
.cfi_def_cfa_offset 80
movl $.L.str.8, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end2:
.size _Z13getIdleStreami, .Lfunc_end2-_Z13getIdleStreami
.cfi_endproc
# -- End function
.globl _Z14syncAllStreamsv # -- Begin function _Z14syncAllStreamsv
.p2align 4, 0x90
.type _Z14syncAllStreamsv,@function
_Z14syncAllStreamsv: # @_Z14syncAllStreamsv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq hipDeviceSynchronize
movq $0, streamSize(%rip)
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z14syncAllStreamsv, .Lfunc_end3-_Z14syncAllStreamsv
.cfi_endproc
# -- End function
.globl _Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii # -- Begin function _Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii
.p2align 4, 0x90
.type _Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii,@function
_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii: # @_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %r12d
movq %r8, 16(%rsp) # 8-byte Spill
movl %ecx, 12(%rsp) # 4-byte Spill
movq %rdx, %r14
movq %rsi, %r15
movl 88(%rsp), %r13d
movl 80(%rsp), %ebx
callq hipSetDevice
movl %ebx, %edx
imull %r12d, %ebx
movl %r13d, %eax
imull %r12d, %eax
cmpl %eax, %ebx
jge .LBB4_3
# %bb.1: # %.lr.ph
movl 104(%rsp), %eax
movl 96(%rsp), %ebp
subl %ebp, %eax
imull %r12d, %ebp
imull %r12d, %eax
shll $2, %eax
movl %r12d, %ecx
movslq %eax, %r12
subl %edx, %r13d
imull %ecx, %r13d
.p2align 4, 0x90
.LBB4_2: # =>This Inner Loop Header: Depth=1
movl n(%rip), %eax
imull %ebx, %eax
addl %ebp, %eax
cltq
leaq (%r15,%rax,4), %rdi
leaq (%r14,%rax,4), %rsi
movq %r12, %rdx
movl 12(%rsp), %ecx # 4-byte Reload
movq 16(%rsp), %r8 # 8-byte Reload
callq hipMemcpyAsync
incl %ebx
decl %r13d
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii, .Lfunc_end4-_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq 24(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 8(%rbx), %rdi
movl %r14d, %esi
callq _Z5inputPci
movl %r14d, %edi
callq _Z13block_FW_2GPUi
movq 16(%rbx), %rdi
callq _Z6outputPc
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.globl _Z5inputPci # -- Begin function _Z5inputPci
.p2align 4, 0x90
.type _Z5inputPci,@function
_Z5inputPci: # @_Z5inputPci
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $24, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r14d
movl $.L.str, %esi
callq fopen
movq %rax, %rbx
xorl %r15d, %r15d
movl $.L.str.1, %esi
movl $realn, %edx
movl $m, %ecx
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl realn(%rip), %eax
leal (%r14,%rax), %esi
decl %esi
movl %esi, %eax
cltd
idivl %r14d
subl %edx, %esi
movl %esi, n(%rip)
imull %esi, %esi
shlq $2, %rsi
movl $Dist, %edi
movl $1, %edx
callq hipMallocManaged
cmpl $0, n(%rip)
jle .LBB6_7
# %bb.1: # %.preheader16.preheader
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_6: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %rax
cmpl n(%rip), %eax
jge .LBB6_7
.LBB6_2: # %.preheader16
# =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
cmpl $0, n(%rip)
jle .LBB6_6
# %bb.3: # %.lr.ph
# in Loop: Header=BB6_2 Depth=1
movslq %ecx, %rdx
shlq $2, %rdx
addq Dist(%rip), %rdx
xorl %esi, %esi
.p2align 4, 0x90
.LBB6_4: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
cmpl %esi, %eax
movl $10000000, %edi # imm = 0x989680
cmovel %r15d, %edi
movl %edi, (%rdx,%rsi,4)
incq %rsi
cmpl n(%rip), %esi
jl .LBB6_4
# %bb.5: # %._crit_edge.loopexit
# in Loop: Header=BB6_2 Depth=1
addl %esi, %ecx
jmp .LBB6_6
.LBB6_7: # %.preheader
movl m(%rip), %eax
leal -1(%rax), %ecx
movl %ecx, m(%rip)
testl %eax, %eax
jle .LBB6_10
# %bb.8:
leaq 16(%rsp), %r14
leaq 12(%rsp), %r15
leaq 20(%rsp), %r12
.p2align 4, 0x90
.LBB6_9: # %.lr.ph21
# =>This Inner Loop Header: Depth=1
movl $.L.str.2, %esi
movq %rbx, %rdi
movq %r14, %rdx
movq %r15, %rcx
movq %r12, %r8
xorl %eax, %eax
callq __isoc23_fscanf
movslq 16(%rsp), %rax
decq %rax
movl %eax, 16(%rsp)
movslq 12(%rsp), %rcx
leaq -1(%rcx), %rdx
movl %edx, 12(%rsp)
movl 20(%rsp), %edx
movq Dist(%rip), %rsi
movslq n(%rip), %rdi
imulq %rax, %rdi
leaq (%rdi,%rcx), %rax
decq %rax
movl %edx, (%rsi,%rax,4)
movl m(%rip), %eax
leal -1(%rax), %ecx
movl %ecx, m(%rip)
testl %eax, %eax
jg .LBB6_9
.LBB6_10: # %._crit_edge22
addq $24, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z5inputPci, .Lfunc_end6-_Z5inputPci
.cfi_endproc
# -- End function
.globl _Z13block_FW_2GPUi # -- Begin function _Z13block_FW_2GPUi
.p2align 4, 0x90
.type _Z13block_FW_2GPUi,@function
_Z13block_FW_2GPUi: # @_Z13block_FW_2GPUi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebx
movl n(%rip), %eax
addl %ebx, %eax
decl %eax
cltd
idivl %edi
testl %eax, %eax
jle .LBB7_3
# %bb.1: # %.lr.ph.preheader
movl %eax, %r14d
leal -1(%r14), %ebp
xorl %r15d, %r15d
.LBB7_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq stderr(%rip), %rdi
movl $.L.str.7, %esi
movl %r15d, %edx
xorl %eax, %eax
callq fprintf
movl $1, (%rsp)
xorl %edi, %edi
movl %ebx, %esi
movl %r15d, %edx
movl %r15d, %ecx
movl %r15d, %r8d
movl $1, %r9d
callq _Z8calAsynciiiiiii
callq hipDeviceSynchronize
movq $0, streamSize(%rip)
movl $1, (%rsp)
xorl %edi, %edi
movl %ebx, %esi
movl %r15d, %edx
movl %r15d, %ecx
xorl %r8d, %r8d
movl %r15d, %r9d
callq _Z8calAsynciiiiiii
leal 1(%r15), %r12d
movl $1, (%rsp)
xorl %edi, %edi
movl %ebx, %esi
movl %r15d, %edx
movl %r15d, %ecx
movl %r12d, %r8d
movl %ebp, %r9d
callq _Z8calAsynciiiiiii
movl %r15d, (%rsp)
movl $1, %edi
movl %ebx, %esi
movl %r15d, %edx
xorl %ecx, %ecx
movl %r15d, %r8d
movl $1, %r9d
callq _Z8calAsynciiiiiii
movl %ebp, (%rsp)
movl $1, %edi
movl %ebx, %esi
movl %r15d, %edx
movl %r12d, %ecx
movl %r15d, %r8d
movl $1, %r9d
callq _Z8calAsynciiiiiii
callq hipDeviceSynchronize
movq $0, streamSize(%rip)
movl %r15d, (%rsp)
xorl %edi, %edi
movl %ebx, %esi
movl %r15d, %edx
xorl %ecx, %ecx
xorl %r8d, %r8d
movl %r15d, %r9d
callq _Z8calAsynciiiiiii
movl %r15d, (%rsp)
movl $1, %edi
movl %ebx, %esi
movl %r15d, %edx
xorl %ecx, %ecx
movl %r12d, %r8d
movl %ebp, %r9d
callq _Z8calAsynciiiiiii
movl %ebp, (%rsp)
movl $1, %edi
movl %ebx, %esi
movl %r15d, %edx
movl %r12d, %ecx
xorl %r8d, %r8d
movl %r15d, %r9d
callq _Z8calAsynciiiiiii
movl %ebp, (%rsp)
xorl %edi, %edi
movl %ebx, %esi
movl %r15d, %edx
movl %r12d, %ecx
movl %r12d, %r8d
movl %ebp, %r9d
callq _Z8calAsynciiiiiii
callq hipDeviceSynchronize
movq $0, streamSize(%rip)
decl %ebp
movl %r12d, %r15d
cmpl %r14d, %r12d
jne .LBB7_2
.LBB7_3: # %._crit_edge
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z13block_FW_2GPUi, .Lfunc_end7-_Z13block_FW_2GPUi
.cfi_endproc
# -- End function
.globl _Z6outputPc # -- Begin function _Z6outputPc
.p2align 4, 0x90
.type _Z6outputPc,@function
_Z6outputPc: # @_Z6outputPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str.3, %esi
callq fopen
cmpl $0, realn(%rip)
jle .LBB8_7
# %bb.1: # %.preheader.preheader
movq %rax, %rbx
xorl %ebp, %ebp
jmp .LBB8_2
.p2align 4, 0x90
.LBB8_6: # %._crit_edge
# in Loop: Header=BB8_2 Depth=1
movl $10, %edi
movq %rbx, %rsi
callq fputc@PLT
incl %ebp
cmpl realn(%rip), %ebp
jge .LBB8_7
.LBB8_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
cmpl $0, realn(%rip)
jle .LBB8_6
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB8_2 Depth=1
movslq %ebp, %r14
xorl %r15d, %r15d
jmp .LBB8_4
.p2align 4, 0x90
.LBB8_8: # in Loop: Header=BB8_4 Depth=2
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
.LBB8_9: # in Loop: Header=BB8_4 Depth=2
incq %r15
cmpl realn(%rip), %r15d
jge .LBB8_6
.LBB8_4: # %.lr.ph
# Parent Loop BB8_2 Depth=1
# => This Inner Loop Header: Depth=2
movq Dist(%rip), %rax
movslq n(%rip), %rcx
imulq %r14, %rcx
addq %r15, %rcx
movl (%rax,%rcx,4), %edx
cmpl $10000000, %edx # imm = 0x989680
jl .LBB8_8
# %bb.5: # in Loop: Header=BB8_4 Depth=2
movl $.L.str.4, %edi
movl $4, %esi
movl $1, %edx
movq %rbx, %rcx
callq fwrite@PLT
jmp .LBB8_9
.LBB8_7: # %._crit_edge15
movq Dist(%rip), %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end8:
.size _Z6outputPc, .Lfunc_end8-_Z6outputPc
.cfi_endproc
# -- End function
.globl _Z4ceilii # -- Begin function _Z4ceilii
.p2align 4, 0x90
.type _Z4ceilii,@function
_Z4ceilii: # @_Z4ceilii
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
# kill: def $edi killed $edi def $rdi
leal (%rdi,%rsi), %eax
decl %eax
cltd
idivl %esi
retq
.Lfunc_end9:
.size _Z4ceilii, .Lfunc_end9-_Z4ceilii
.cfi_endproc
# -- End function
.globl _Z5printv # -- Begin function _Z5printv
.p2align 4, 0x90
.type _Z5printv,@function
_Z5printv: # @_Z5printv
.cfi_startproc
# %bb.0:
cmpl $0, realn(%rip)
jle .LBB10_10
# %bb.1: # %.preheader.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %ebx, %ebx
jmp .LBB10_2
.p2align 4, 0x90
.LBB10_8: # %._crit_edge
# in Loop: Header=BB10_2 Depth=1
movq stderr(%rip), %rsi
movl $10, %edi
callq fputc@PLT
incl %ebx
cmpl realn(%rip), %ebx
jge .LBB10_9
.LBB10_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB10_4 Depth 2
cmpl $0, realn(%rip)
jle .LBB10_8
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB10_2 Depth=1
movslq %ebx, %r14
xorl %r15d, %r15d
.LBB10_4: # %.lr.ph
# Parent Loop BB10_2 Depth=1
# => This Inner Loop Header: Depth=2
movq Dist(%rip), %rax
movslq n(%rip), %rcx
imulq %r14, %rcx
addq %r15, %rcx
movl (%rax,%rcx,4), %edx
movq stderr(%rip), %rcx
cmpl $10000000, %edx # imm = 0x989680
jl .LBB10_6
# %bb.5: # in Loop: Header=BB10_4 Depth=2
movl $.L.str.4, %edi
movl $4, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB10_7
.p2align 4, 0x90
.LBB10_6: # in Loop: Header=BB10_4 Depth=2
movl $.L.str.5, %esi
movq %rcx, %rdi
xorl %eax, %eax
callq fprintf
.LBB10_7: # in Loop: Header=BB10_4 Depth=2
incq %r15
cmpl realn(%rip), %r15d
jl .LBB10_4
jmp .LBB10_8
.LBB10_9:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB10_10: # %._crit_edge13
movq stderr(%rip), %rsi
movl $10, %edi
jmp fputc@PLT # TAILCALL
.Lfunc_end10:
.size _Z5printv, .Lfunc_end10-_Z5printv
.cfi_endproc
# -- End function
.globl _Z8calAsynciiiiiii # -- Begin function _Z8calAsynciiiiiii
.p2align 4, 0x90
.type _Z8calAsynciiiiiii,@function
_Z8calAsynciiiiiii: # @_Z8calAsynciiiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
# kill: def $r9d killed $r9d def $r9
movq %r9, 144(%rsp) # 8-byte Spill
# kill: def $r8d killed $r8d def $r8
movq %r8, 136(%rsp) # 8-byte Spill
# kill: def $ecx killed $ecx def $rcx
movq %rcx, 40(%rsp) # 8-byte Spill
movl %edx, %ebx
# kill: def $esi killed $esi def $rsi
movq %rsi, 48(%rsp) # 8-byte Spill
movl 288(%rsp), %ebp
movl %edi, 120(%rsp) # 4-byte Spill
callq hipSetDevice
movl %ebp, 4(%rsp) # 4-byte Spill
testl %ebp, %ebp
jle .LBB11_12
# %bb.1: # %.preheader85.lr.ph
movl 4(%rsp), %eax # 4-byte Reload
addl 40(%rsp), %eax # 4-byte Folded Reload
movl %eax, 4(%rsp) # 4-byte Spill
movq 144(%rsp), %rax # 8-byte Reload
movq 136(%rsp), %rcx # 8-byte Reload
addl %ecx, %eax
movl %eax, 112(%rsp) # 4-byte Spill
movl %ebx, %eax
movq 48(%rsp), %rcx # 8-byte Reload
imull %ecx, %eax
movl %eax, 8(%rsp) # 4-byte Spill
incl %ebx
imull %ecx, %ebx
movl %ebx, 116(%rsp) # 4-byte Spill
leal 31(%rcx), %eax
addl $62, %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
movq %rcx, %rax
shlq $32, %rax
orq %rcx, %rax
movq %rax, 152(%rsp) # 8-byte Spill
jmp .LBB11_2
.p2align 4, 0x90
.LBB11_11: # %._crit_edge
# in Loop: Header=BB11_2 Depth=1
movq 40(%rsp), %rax # 8-byte Reload
incl %eax
movq %rax, 40(%rsp) # 8-byte Spill
cmpl 4(%rsp), %eax # 4-byte Folded Reload
jge .LBB11_12
.LBB11_2: # %.preheader85
# =>This Loop Header: Depth=1
# Child Loop BB11_4 Depth 2
# Child Loop BB11_8 Depth 3
cmpl $0, 144(%rsp) # 4-byte Folded Reload
jle .LBB11_11
# %bb.3: # %.lr.ph88
# in Loop: Header=BB11_2 Depth=1
movq 40(%rsp), %rax # 8-byte Reload
movl %eax, %edx
movq 48(%rsp), %rcx # 8-byte Reload
imull %ecx, %edx
movl %edx, 12(%rsp) # 4-byte Spill
incl %eax
imull %ecx, %eax
movl %eax, 124(%rsp) # 4-byte Spill
movq 136(%rsp), %rax # 8-byte Reload
movl %eax, %r15d
jmp .LBB11_4
.p2align 4, 0x90
.LBB11_15: # %.loopexit
# in Loop: Header=BB11_4 Depth=2
movl 128(%rsp), %r15d # 4-byte Reload
cmpl 112(%rsp), %r15d # 4-byte Folded Reload
jge .LBB11_11
.LBB11_4: # Parent Loop BB11_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB11_8 Depth 3
movl n(%rip), %ebp
movl 124(%rsp), %eax # 4-byte Reload
cmpl %ebp, %eax
movl %ebp, %r14d
cmovll %eax, %r14d
movl %r15d, %r12d
movq 48(%rsp), %rax # 8-byte Reload
imull %eax, %r12d
incl %r15d
movl %r15d, 128(%rsp) # 4-byte Spill
imull %eax, %r15d
cmpl %ebp, %r15d
cmovgel %ebp, %r15d
movl 116(%rsp), %eax # 4-byte Reload
cmpl %ebp, %eax
cmovll %eax, %ebp
movl 120(%rsp), %edi # 4-byte Reload
callq _Z13getIdleStreami
movq %rax, %r13
movl 8(%rsp), %eax # 4-byte Reload
cmpl %eax, 12(%rsp) # 4-byte Folded Reload
je .LBB11_6
# %bb.5: # in Loop: Header=BB11_4 Depth=2
cmpl %eax, %r12d
je .LBB11_6
# %bb.13: # in Loop: Header=BB11_4 Depth=2
movq 152(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
movq %r13, %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB11_15
# %bb.14: # in Loop: Header=BB11_4 Depth=2
movl %ebp, 32(%rsp)
movl %r12d, 24(%rsp)
movl %r14d, 20(%rsp)
movl %r15d, 16(%rsp)
movq Dist(%rip), %rax
movq %rax, 104(%rsp)
movl n(%rip), %eax
movl %eax, 132(%rsp)
movl 8(%rsp), %eax # 4-byte Reload
movl %eax, 36(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 28(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 28(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 20(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 104(%rsp), %rax
movq %rax, 208(%rsp)
leaq 132(%rsp), %rax
movq %rax, 216(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z17UpdateIndependentiiiiiiPii, %edi
leaq 160(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB11_15
.p2align 4, 0x90
.LBB11_6: # %.preheader
# in Loop: Header=BB11_4 Depth=2
cmpl %ebp, %eax
jge .LBB11_15
# %bb.7: # %.lr.ph.preheader
# in Loop: Header=BB11_4 Depth=2
movl 8(%rsp), %ebx # 4-byte Reload
jmp .LBB11_8
.p2align 4, 0x90
.LBB11_10: # in Loop: Header=BB11_8 Depth=3
incl %ebx
cmpl %ebx, %ebp
je .LBB11_15
.LBB11_8: # %.lr.ph
# Parent Loop BB11_2 Depth=1
# Parent Loop BB11_4 Depth=2
# => This Inner Loop Header: Depth=3
movq 152(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %ecx
xorl %r8d, %r8d
movq %r13, %r9
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB11_10
# %bb.9: # in Loop: Header=BB11_8 Depth=3
movq Dist(%rip), %rax
movl n(%rip), %ecx
movl %ebx, 36(%rsp)
movl 12(%rsp), %edx # 4-byte Reload
movl %edx, 32(%rsp)
movl %r12d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %r15d, 20(%rsp)
movq %rax, 104(%rsp)
movl %ecx, 16(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 28(%rsp), %rax
movq %rax, 176(%rsp)
leaq 24(%rsp), %rax
movq %rax, 184(%rsp)
leaq 20(%rsp), %rax
movq %rax, 192(%rsp)
leaq 104(%rsp), %rax
movq %rax, 200(%rsp)
leaq 16(%rsp), %rax
movq %rax, 208(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
movl $_Z6UpdateiiiiiPii, %edi
leaq 160(%rsp), %r9
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB11_10
.LBB11_12: # %._crit_edge90
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end11:
.size _Z8calAsynciiiiiii, .Lfunc_end11-_Z8calAsynciiiiiii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__UpdateiiiiiPii # -- Begin function _Z21__device_stub__UpdateiiiiiPii
.p2align 4, 0x90
.type _Z21__device_stub__UpdateiiiiiPii,@function
_Z21__device_stub__UpdateiiiiiPii: # @_Z21__device_stub__UpdateiiiiiPii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %r9, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 80(%rsp)
leaq 16(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6UpdateiiiiiPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end12:
.size _Z21__device_stub__UpdateiiiiiPii, .Lfunc_end12-_Z21__device_stub__UpdateiiiiiPii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__UpdateIndependentiiiiiiPii # -- Begin function _Z32__device_stub__UpdateIndependentiiiiiiPii
.p2align 4, 0x90
.type _Z32__device_stub__UpdateIndependentiiiiiiPii,@function
_Z32__device_stub__UpdateIndependentiiiiiiPii: # @_Z32__device_stub__UpdateIndependentiiiiiiPii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17UpdateIndependentiiiiiiPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end13:
.size _Z32__device_stub__UpdateIndependentiiiiiiPii, .Lfunc_end13-_Z32__device_stub__UpdateIndependentiiiiiiPii
.cfi_endproc
# -- End function
.section .text.startup,"ax",@progbits
.p2align 4, 0x90 # -- Begin function _GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
.type _GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip,@function
_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip: # @_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
.cfi_startproc
# %bb.0:
movl $__cxx_global_array_dtor, %edi
movl $__dso_handle, %edx
xorl %esi, %esi
jmp __cxa_atexit # TAILCALL
.Lfunc_end14:
.size _GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip, .Lfunc_end14-_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB15_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB15_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6UpdateiiiiiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17UpdateIndependentiiiiiiPii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end15:
.size __hip_module_ctor, .Lfunc_end15-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB16_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB16_2:
retq
.Lfunc_end16:
.size __hip_module_dtor, .Lfunc_end16-__hip_module_dtor
.cfi_endproc
# -- End function
.type realn,@object # @realn
.bss
.globl realn
.p2align 2, 0x0
realn:
.long 0 # 0x0
.size realn, 4
.type n,@object # @n
.globl n
.p2align 2, 0x0
n:
.long 0 # 0x0
.size n, 4
.type m,@object # @m
.globl m
.p2align 2, 0x0
m:
.long 0 # 0x0
.size m, 4
.type Dist,@object # @Dist
.globl Dist
.p2align 3, 0x0
Dist:
.quad 0
.size Dist, 8
.type dDist,@object # @dDist
.globl dDist
.p2align 4, 0x0
dDist:
.zero 16
.size dDist, 16
.type streamSize,@object # @streamSize
.globl streamSize
.p2align 2, 0x0
streamSize:
.zero 8
.size streamSize, 8
.type streams,@object # @streams
.globl streams
.p2align 4, 0x0
streams:
.zero 48
.size streams, 48
.hidden __dso_handle
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d %d"
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d %d %d"
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "INF "
.size .L.str.4, 5
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d "
.size .L.str.5, 4
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Round: %d\n"
.size .L.str.7, 11
.type _Z6UpdateiiiiiPii,@object # @_Z6UpdateiiiiiPii
.section .rodata,"a",@progbits
.globl _Z6UpdateiiiiiPii
.p2align 3, 0x0
_Z6UpdateiiiiiPii:
.quad _Z21__device_stub__UpdateiiiiiPii
.size _Z6UpdateiiiiiPii, 8
.type _Z17UpdateIndependentiiiiiiPii,@object # @_Z17UpdateIndependentiiiiiiPii
.globl _Z17UpdateIndependentiiiiiiPii
.p2align 3, 0x0
_Z17UpdateIndependentiiiiiiPii:
.quad _Z32__device_stub__UpdateIndependentiiiiiiPii
.size _Z17UpdateIndependentiiiiiiPii, 8
.type .L.str.8,@object # @.str.8
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.8:
.asciz "vector::_M_realloc_insert"
.size .L.str.8, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6UpdateiiiiiPii"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17UpdateIndependentiiiiiiPii"
.size .L__unnamed_2, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad _GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __cxx_global_array_dtor
.addrsig_sym _Z21__device_stub__UpdateiiiiiPii
.addrsig_sym _Z32__device_stub__UpdateIndependentiiiiiiPii
.addrsig_sym __gxx_personality_v0
.addrsig_sym _GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym realn
.addrsig_sym m
.addrsig_sym Dist
.addrsig_sym streams
.addrsig_sym __dso_handle
.addrsig_sym _Z6UpdateiiiiiPii
.addrsig_sym _Z17UpdateIndependentiiiiiiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
extern "C" void initialData(float *ip, int size) {
for (int i=0; i < size; i++) {
ip[i] = (float)rand()/(float)(RAND_MAX/10.0);
}
}
extern "C" void printHello(void) {
printf("HELLO from C\n");
}
extern "C" void print_matrix(float *c, const int nx, const int ny) {
float *ic = c;
for (int iy=0; iy<ny; iy++) {
for (int ix=0; ix<nx; ix++) {
printf("%6.2f", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void print_thread_index(float* a, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d, %d) block_id (%d, %d) coordinate (%d, %d)"
"global index %2d ival %2d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, a[idx]);
}
extern "C" void test() {
int dev = 0;
cudaSetDevice(dev);
int nx = 4;
int ny = 4;
int nxy = nx*ny;
int nbytes = nxy * sizeof(float);
float *h_A;
h_A = (float *) malloc(nbytes);
initialData(h_A, nx*ny);
print_matrix(h_A, nx, ny);
float *d_A;
cudaMalloc((void **) &d_A, nbytes);
cudaMemcpy(d_A, h_A, nbytes, cudaMemcpyHostToDevice);
dim3 block(4, 2);
dim3 grid ((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
print_thread_index <<< grid, block >>>(d_A, nx, ny);
cudaDeviceSynchronize();
cudaFree(d_A);
free(h_A);
cudaDeviceReset();
} | code for sm_80
Function : _Z18print_thread_indexPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R15, SR_TID.Y ; /* 0x00000000000f7919 */
/* 0x000e220000002200 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x28, RZ ; /* 0xffffffd801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R14, SR_TID.X ; /* 0x00000000000e7919 */
/* 0x000e680000002100 */
/*0060*/ S2R R17, SR_CTAID.Y ; /* 0x0000000000117919 */
/* 0x000e280000002600 */
/*0070*/ S2R R16, SR_CTAID.X ; /* 0x0000000000107919 */
/* 0x000e620000002500 */
/*0080*/ IMAD R3, R17, c[0x0][0x4], R15 ; /* 0x0000010011037a24 */
/* 0x001fc400078e020f */
/*0090*/ IMAD R2, R16, c[0x0][0x0], R14 ; /* 0x0000000010027a24 */
/* 0x002fc800078e020e */
/*00a0*/ IMAD R0, R3, c[0x0][0x168], R2 ; /* 0x00005a0003007a24 */
/* 0x000fc800078e0202 */
/*00b0*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fcc00078e0009 */
/*00c0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ MOV R12, 0x0 ; /* 0x00000000000c7802 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00f0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0100*/ STL.64 [R1], R14 ; /* 0x0000000e01007387 */
/* 0x0001e20000100a00 */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0120*/ LDC.64 R12, c[0x4][R12] ; /* 0x010000000c0c7b82 */
/* 0x000e620000000a00 */
/*0130*/ STL.64 [R1+0x8], R16 ; /* 0x0000081001007387 */
/* 0x0001e20000100a00 */
/*0140*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fc600000e06ff */
/*0150*/ STL.64 [R1+0x10], R2 ; /* 0x0000100201007387 */
/* 0x0001e80000100a00 */
/*0160*/ STL [R1+0x18], R0 ; /* 0x0000180001007387 */
/* 0x0001e20000100800 */
/*0170*/ F2F.F64.F32 R10, R8 ; /* 0x00000008000a7310 */
/* 0x004ea60000201800 */
/*0180*/ STL.64 [R1+0x20], R10 ; /* 0x0000200a01007387 */
/* 0x0041e40000100a00 */
/*0190*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*01a0*/ MOV R9, 0x210 ; /* 0x0000021000097802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R20, 0x190 ; /* 0x0000019000147802 */
/* 0x000fc40000000f00 */
/*01c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01e0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*01f0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0200*/ CALL.ABS.NOINC R12 ; /* 0x000000000c007343 */
/* 0x000fea0003c00000 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
extern "C" void initialData(float *ip, int size) {
for (int i=0; i < size; i++) {
ip[i] = (float)rand()/(float)(RAND_MAX/10.0);
}
}
extern "C" void printHello(void) {
printf("HELLO from C\n");
}
extern "C" void print_matrix(float *c, const int nx, const int ny) {
float *ic = c;
for (int iy=0; iy<ny; iy++) {
for (int ix=0; ix<nx; ix++) {
printf("%6.2f", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void print_thread_index(float* a, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d, %d) block_id (%d, %d) coordinate (%d, %d)"
"global index %2d ival %2d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, a[idx]);
}
extern "C" void test() {
int dev = 0;
cudaSetDevice(dev);
int nx = 4;
int ny = 4;
int nxy = nx*ny;
int nbytes = nxy * sizeof(float);
float *h_A;
h_A = (float *) malloc(nbytes);
initialData(h_A, nx*ny);
print_matrix(h_A, nx, ny);
float *d_A;
cudaMalloc((void **) &d_A, nbytes);
cudaMemcpy(d_A, h_A, nbytes, cudaMemcpyHostToDevice);
dim3 block(4, 2);
dim3 grid ((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
print_thread_index <<< grid, block >>>(d_A, nx, ny);
cudaDeviceSynchronize();
cudaFree(d_A);
free(h_A);
cudaDeviceReset();
} | .file "tmpxft_00032b3a_00000000-6_matrixIndex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl initialData
.type initialData, @function
initialData:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size initialData, .-initialData
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "HELLO from C\n"
.text
.globl printHello
.type printHello, @function
printHello:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size printHello, .-printHello
.section .rodata.str1.1
.LC2:
.string "%6.2f"
.LC3:
.string "\n"
.text
.globl print_matrix
.type print_matrix, @function
print_matrix:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
testl %edx, %edx
jle .L14
movq %rdi, %r13
movslq %esi, %r15
salq $2, %r15
leaq (%rdi,%r15), %rbp
movl $0, %r14d
leaq .LC2(%rip), %r12
jmp .L15
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L16
.L18:
addq %r15, %r13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 12(%rsp)
je .L14
.L15:
movq %r13, %rbx
cmpl $0, 8(%rsp)
jg .L16
jmp .L18
.L14:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size print_matrix, .-print_matrix
.globl _Z40__device_stub__Z18print_thread_indexPfiiPfii
.type _Z40__device_stub__Z18print_thread_indexPfiiPfii, @function
_Z40__device_stub__Z18print_thread_indexPfiiPfii:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18print_thread_indexPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z40__device_stub__Z18print_thread_indexPfiiPfii, .-_Z40__device_stub__Z18print_thread_indexPfiiPfii
.globl _Z18print_thread_indexPfii
.type _Z18print_thread_indexPfii, @function
_Z18print_thread_indexPfii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18print_thread_indexPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18print_thread_indexPfii, .-_Z18print_thread_indexPfii
.globl test
.type test, @function
test:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $16, %esi
movq %rax, %rdi
call initialData
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call print_matrix
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $2, 32(%rsp)
movl $4, 16(%rsp)
movl $2, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L31:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl $4, %edx
movl $4, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z18print_thread_indexPfiiPfii
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size test, .-test
.section .rodata.str1.1
.LC4:
.string "_Z18print_thread_indexPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18print_thread_indexPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1296878797
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
#include <math.h>
extern "C" void initialData(float *ip, int size) {
for (int i=0; i < size; i++) {
ip[i] = (float)rand()/(float)(RAND_MAX/10.0);
}
}
extern "C" void printHello(void) {
printf("HELLO from C\n");
}
extern "C" void print_matrix(float *c, const int nx, const int ny) {
float *ic = c;
for (int iy=0; iy<ny; iy++) {
for (int ix=0; ix<nx; ix++) {
printf("%6.2f", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void print_thread_index(float* a, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d, %d) block_id (%d, %d) coordinate (%d, %d)"
"global index %2d ival %2d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, a[idx]);
}
extern "C" void test() {
int dev = 0;
cudaSetDevice(dev);
int nx = 4;
int ny = 4;
int nxy = nx*ny;
int nbytes = nxy * sizeof(float);
float *h_A;
h_A = (float *) malloc(nbytes);
initialData(h_A, nx*ny);
print_matrix(h_A, nx, ny);
float *d_A;
cudaMalloc((void **) &d_A, nbytes);
cudaMemcpy(d_A, h_A, nbytes, cudaMemcpyHostToDevice);
dim3 block(4, 2);
dim3 grid ((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
print_thread_index <<< grid, block >>>(d_A, nx, ny);
cudaDeviceSynchronize();
cudaFree(d_A);
free(h_A);
cudaDeviceReset();
} | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <math.h>
extern "C" void initialData(float *ip, int size) {
for (int i=0; i < size; i++) {
ip[i] = (float)rand()/(float)(RAND_MAX/10.0);
}
}
extern "C" void printHello(void) {
printf("HELLO from C\n");
}
extern "C" void print_matrix(float *c, const int nx, const int ny) {
float *ic = c;
for (int iy=0; iy<ny; iy++) {
for (int ix=0; ix<nx; ix++) {
printf("%6.2f", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void print_thread_index(float* a, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d, %d) block_id (%d, %d) coordinate (%d, %d)"
"global index %2d ival %2d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, a[idx]);
}
extern "C" void test() {
int dev = 0;
hipSetDevice(dev);
int nx = 4;
int ny = 4;
int nxy = nx*ny;
int nbytes = nxy * sizeof(float);
float *h_A;
h_A = (float *) malloc(nbytes);
initialData(h_A, nx*ny);
print_matrix(h_A, nx, ny);
float *d_A;
hipMalloc((void **) &d_A, nbytes);
hipMemcpy(d_A, h_A, nbytes, hipMemcpyHostToDevice);
dim3 block(4, 2);
dim3 grid ((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
print_thread_index <<< grid, block >>>(d_A, nx, ny);
hipDeviceSynchronize();
hipFree(d_A);
free(h_A);
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include <math.h>
extern "C" void initialData(float *ip, int size) {
for (int i=0; i < size; i++) {
ip[i] = (float)rand()/(float)(RAND_MAX/10.0);
}
}
extern "C" void printHello(void) {
printf("HELLO from C\n");
}
extern "C" void print_matrix(float *c, const int nx, const int ny) {
float *ic = c;
for (int iy=0; iy<ny; iy++) {
for (int ix=0; ix<nx; ix++) {
printf("%6.2f", ic[ix]);
}
ic += nx;
printf("\n");
}
printf("\n");
}
__global__ void print_thread_index(float* a, const int nx, const int ny) {
int ix = threadIdx.x + blockIdx.x * blockDim.x;
int iy = threadIdx.y + blockIdx.y * blockDim.y;
unsigned int idx = iy*nx + ix;
printf("thread_id (%d, %d) block_id (%d, %d) coordinate (%d, %d)"
"global index %2d ival %2d\n",
threadIdx.x, threadIdx.y, blockIdx.x, blockIdx.y, ix, iy, idx, a[idx]);
}
extern "C" void test() {
int dev = 0;
hipSetDevice(dev);
int nx = 4;
int ny = 4;
int nxy = nx*ny;
int nbytes = nxy * sizeof(float);
float *h_A;
h_A = (float *) malloc(nbytes);
initialData(h_A, nx*ny);
print_matrix(h_A, nx, ny);
float *d_A;
hipMalloc((void **) &d_A, nbytes);
hipMemcpy(d_A, h_A, nbytes, hipMemcpyHostToDevice);
dim3 block(4, 2);
dim3 grid ((nx+block.x-1)/block.x, (ny+block.y-1)/block.y);
print_thread_index <<< grid, block >>>(d_A, nx, ny);
hipDeviceSynchronize();
hipFree(d_A);
free(h_A);
hipDeviceReset();
} | .text
.file "matrixIndex.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function initialData
.LCPI0_0:
.long 0x4d4ccccd # float 214748368
.text
.globl initialData
.p2align 4, 0x90
.type initialData,@function
initialData: # @initialData
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size initialData, .Lfunc_end0-initialData
.cfi_endproc
# -- End function
.globl printHello # -- Begin function printHello
.p2align 4, 0x90
.type printHello,@function
printHello: # @printHello
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size printHello, .Lfunc_end1-printHello
.cfi_endproc
# -- End function
.globl print_matrix # -- Begin function print_matrix
.p2align 4, 0x90
.type print_matrix,@function
print_matrix: # @print_matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 4(%rsp) # 4-byte Spill
testl %edx, %edx
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movq %rdi, %r14
movslq 4(%rsp), %r15 # 4-byte Folded Reload
movl %r15d, %r12d
shlq $2, %r15
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r13d
addq %r15, %r14
cmpl %ebx, %r13d
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbp
cmpq %rbp, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge17
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size print_matrix, .Lfunc_end2-print_matrix
.cfi_endproc
# -- End function
.globl _Z33__device_stub__print_thread_indexPfii # -- Begin function _Z33__device_stub__print_thread_indexPfii
.p2align 4, 0x90
.type _Z33__device_stub__print_thread_indexPfii,@function
_Z33__device_stub__print_thread_indexPfii: # @_Z33__device_stub__print_thread_indexPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18print_thread_indexPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z33__device_stub__print_thread_indexPfii, .Lfunc_end3-_Z33__device_stub__print_thread_indexPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function test
.LCPI4_0:
.long 0x4d4ccccd # float 214748368
.text
.globl test
.p2align 4, 0x90
.type test,@function
test: # @test
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq hipSetDevice
movl $64, %edi
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $16, %r14
jne .LBB4_1
# %bb.2: # %.preheader.i.preheader
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB4_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph.i24
# Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB4_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB4_3 Depth=1
addq $16, %r15
movl $10, %edi
callq putchar@PLT
incl %r14d
cmpl $4, %r14d
jne .LBB4_3
# %bb.6: # %print_matrix.exit
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934593, %rdi # imm = 0x200000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $4, 20(%rsp)
movl $4, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18print_thread_indexPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
callq hipDeviceReset
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size test, .Lfunc_end4-test
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18print_thread_indexPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%6.2f"
.size .L.str.1, 6
.type _Z18print_thread_indexPfii,@object # @_Z18print_thread_indexPfii
.section .rodata,"a",@progbits
.globl _Z18print_thread_indexPfii
.p2align 3, 0x0
_Z18print_thread_indexPfii:
.quad _Z33__device_stub__print_thread_indexPfii
.size _Z18print_thread_indexPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18print_thread_indexPfii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "HELLO from C"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__print_thread_indexPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18print_thread_indexPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00032b3a_00000000-6_matrixIndex.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl initialData
.type initialData, @function
initialData:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L8
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movslq %esi, %rsi
leaq (%rdi,%rsi,4), %rbp
.L5:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss .LC0(%rip), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2057:
.size initialData, .-initialData
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "HELLO from C\n"
.text
.globl printHello
.type printHello, @function
printHello:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size printHello, .-printHello
.section .rodata.str1.1
.LC2:
.string "%6.2f"
.LC3:
.string "\n"
.text
.globl print_matrix
.type print_matrix, @function
print_matrix:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
testl %edx, %edx
jle .L14
movq %rdi, %r13
movslq %esi, %r15
salq $2, %r15
leaq (%rdi,%r15), %rbp
movl $0, %r14d
leaq .LC2(%rip), %r12
jmp .L15
.L16:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L16
.L18:
addq %r15, %r13
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
addq %r15, %rbp
cmpl %r14d, 12(%rsp)
je .L14
.L15:
movq %r13, %rbx
cmpl $0, 8(%rsp)
jg .L16
jmp .L18
.L14:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size print_matrix, .-print_matrix
.globl _Z40__device_stub__Z18print_thread_indexPfiiPfii
.type _Z40__device_stub__Z18print_thread_indexPfiiPfii, @function
_Z40__device_stub__Z18print_thread_indexPfiiPfii:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z18print_thread_indexPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z40__device_stub__Z18print_thread_indexPfiiPfii, .-_Z40__device_stub__Z18print_thread_indexPfiiPfii
.globl _Z18print_thread_indexPfii
.type _Z18print_thread_indexPfii, @function
_Z18print_thread_indexPfii:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z18print_thread_indexPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z18print_thread_indexPfii, .-_Z18print_thread_indexPfii
.globl test
.type test, @function
test:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $0, %edi
call cudaSetDevice@PLT
movl $64, %edi
call malloc@PLT
movq %rax, %rbx
movl $16, %esi
movq %rax, %rdi
call initialData
movl $4, %edx
movl $4, %esi
movq %rbx, %rdi
call print_matrix
leaq 8(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 28(%rsp)
movl $2, 32(%rsp)
movl $4, 16(%rsp)
movl $2, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L31:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movl $4, %edx
movl $4, %esi
movq 8(%rsp), %rdi
call _Z40__device_stub__Z18print_thread_indexPfiiPfii
jmp .L31
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size test, .-test
.section .rodata.str1.1
.LC4:
.string "_Z18print_thread_indexPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z18print_thread_indexPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1296878797
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixIndex.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function initialData
.LCPI0_0:
.long 0x4d4ccccd # float 214748368
.text
.globl initialData
.p2align 4, 0x90
.type initialData,@function
initialData: # @initialData
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI0_0(%rip), %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB0_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB0_4: # %._crit_edge
retq
.Lfunc_end0:
.size initialData, .Lfunc_end0-initialData
.cfi_endproc
# -- End function
.globl printHello # -- Begin function printHello
.p2align 4, 0x90
.type printHello,@function
printHello: # @printHello
.cfi_startproc
# %bb.0:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size printHello, .Lfunc_end1-printHello
.cfi_endproc
# -- End function
.globl print_matrix # -- Begin function print_matrix
.p2align 4, 0x90
.type print_matrix,@function
print_matrix: # @print_matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, 4(%rsp) # 4-byte Spill
testl %edx, %edx
jle .LBB2_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movq %rdi, %r14
movslq 4(%rsp), %r15 # 4-byte Folded Reload
movl %r15d, %r12d
shlq $2, %r15
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
movl $10, %edi
callq putchar@PLT
incl %r13d
addq %r15, %r14
cmpl %ebx, %r13d
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbp
cmpq %rbp, %r12
jne .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge17
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end2:
.size print_matrix, .Lfunc_end2-print_matrix
.cfi_endproc
# -- End function
.globl _Z33__device_stub__print_thread_indexPfii # -- Begin function _Z33__device_stub__print_thread_indexPfii
.p2align 4, 0x90
.type _Z33__device_stub__print_thread_indexPfii,@function
_Z33__device_stub__print_thread_indexPfii: # @_Z33__device_stub__print_thread_indexPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z18print_thread_indexPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z33__device_stub__print_thread_indexPfii, .Lfunc_end3-_Z33__device_stub__print_thread_indexPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function test
.LCPI4_0:
.long 0x4d4ccccd # float 214748368
.text
.globl test
.p2align 4, 0x90
.type test,@function
test: # @test
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
xorl %r14d, %r14d
xorl %edi, %edi
callq hipSetDevice
movl $64, %edi
callq malloc
movq %rax, %rbx
.p2align 4, 0x90
.LBB4_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
divss .LCPI4_0(%rip), %xmm0
movss %xmm0, (%rbx,%r14,4)
incq %r14
cmpq $16, %r14
jne .LBB4_1
# %bb.2: # %.preheader.i.preheader
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB4_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # %.lr.ph.i24
# Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB4_4
# %bb.5: # %._crit_edge.i
# in Loop: Header=BB4_3 Depth=1
addq $16, %r15
movl $10, %edi
callq putchar@PLT
incl %r14d
cmpl $4, %r14d
jne .LBB4_3
# %bb.6: # %print_matrix.exit
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $64, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $8589934593, %rdi # imm = 0x200000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_8
# %bb.7:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $4, 20(%rsp)
movl $4, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18print_thread_indexPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_8:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
callq hipDeviceReset
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size test, .Lfunc_end4-test
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18print_thread_indexPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%6.2f"
.size .L.str.1, 6
.type _Z18print_thread_indexPfii,@object # @_Z18print_thread_indexPfii
.section .rodata,"a",@progbits
.globl _Z18print_thread_indexPfii
.p2align 3, 0x0
_Z18print_thread_indexPfii:
.quad _Z33__device_stub__print_thread_indexPfii
.size _Z18print_thread_indexPfii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18print_thread_indexPfii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "HELLO from C"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__print_thread_indexPfii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18print_thread_indexPfii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <vector>
using namespace std;
__global__
void count_samples_in_circles(float* d_randNumsX, float* d_randNumsY, int* d_countInBlocks, int num_blocks, int nsamples)
{
__shared__ int shared_blocks[500];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * num_blocks;
int inCircle = 0;
for (int i = index; i < nsamples; i+= stride) {
float xValue = d_randNumsX[i];
float yValue = d_randNumsY[i];
if (xValue*xValue + yValue*yValue <= 1.0f) {
inCircle++;
}
}
shared_blocks[threadIdx.x] = inCircle;
__syncthreads();
if (threadIdx.x == 0)
{
int totalInCircleForABlock = 0;
for (int j = 0; j < blockDim.x; j++)
{
totalInCircleForABlock += shared_blocks[j];
}
d_countInBlocks[blockIdx.x] = totalInCircleForABlock;
}
}
int nsamples;
int main(int argc, char* argv[]) {
int nsamples = atoi(argv[1]);
printf("nsamples: %d\n", nsamples);
vector<float> h_randNumsX(nsamples);
vector<float> h_randNumsY(nsamples);
srand(time(NULL));
for (int i = 0; i < h_randNumsX.size(); ++i)
{
h_randNumsX[i] = float(rand()) / RAND_MAX;
h_randNumsY[i] = float(rand()) / RAND_MAX;
}
size_t size = nsamples * sizeof(float);
float* d_randNumsX;
float* d_randNumsY;
cudaMalloc(&d_randNumsX, size);
cudaMalloc(&d_randNumsY, size);
cudaMemcpy(d_randNumsX, &h_randNumsX.front(), size, cudaMemcpyHostToDevice);
cudaMemcpy(d_randNumsY, &h_randNumsY.front(), size, cudaMemcpyHostToDevice);
int threadsPerBlock = 500;
int num_blocks = nsamples / (1000 * threadsPerBlock);
size_t countBlocks = num_blocks * sizeof(int);
int* d_countInBlocks;
cudaMalloc(&d_countInBlocks, countBlocks);
count_samples_in_circles<<<num_blocks, threadsPerBlock>>>(d_randNumsX, d_randNumsY, d_countInBlocks, num_blocks, nsamples);
if ( cudaSuccess != cudaGetLastError() )
cout << "Error!\n";
int* h_countInBlocks = new int[num_blocks];
cudaMemcpy(h_countInBlocks, d_countInBlocks, countBlocks, cudaMemcpyDeviceToHost);
int nsamples_in_circle = 0;
for (int i = 0 ; i < num_blocks; i++) {
nsamples_in_circle = nsamples_in_circle + h_countInBlocks[i];
}
cudaFree(d_randNumsX);
cudaFree(d_randNumsY);
cudaFree(d_countInBlocks);
float estimatedValue = 4.0 * float(nsamples_in_circle) / nsamples;
cout << "Estimated Value: " << estimatedValue << endl;
} | .file "tmpxft_0014b59b_00000000-6_pi_monte_carlo.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii
.type _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii, @function
_Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24count_samples_in_circlesPfS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii, .-_Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii
.globl _Z24count_samples_in_circlesPfS_Piii
.type _Z24count_samples_in_circlesPfS_Piii, @function
_Z24count_samples_in_circlesPfS_Piii:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z24count_samples_in_circlesPfS_Piii, .-_Z24count_samples_in_circlesPfS_Piii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24count_samples_in_circlesPfS_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24count_samples_in_circlesPfS_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIfSaIfEEC2EmRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIfSaIfEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEEC2EmRKS0_
.type _ZNSt6vectorIfSaIfEEC2EmRKS0_, @function
_ZNSt6vectorIfSaIfEEC2EmRKS0_:
.LFB4367:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $61, %rax
jne .L23
movq %rdi, %rbx
movq %rsi, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L15
leaq 0(,%rsi,4), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
movq %rax, 8(%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movl $0x00000000, (%rax)
addq $4, %rax
cmpq $1, %rbp
je .L18
cmpq %rax, %rdx
je .L19
.L17:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L17
jmp .L16
.L23:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L18:
movq %rax, %rdx
jmp .L16
.L19:
movq %rax, %rdx
jmp .L16
.L15:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
.L16:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4367:
.size _ZNSt6vectorIfSaIfEEC2EmRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKS0_
.weak _ZNSt6vectorIfSaIfEEC1EmRKS0_
.set _ZNSt6vectorIfSaIfEEC1EmRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKS0_
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4370:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L27
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L27:
ret
.cfi_endproc
.LFE4370:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "nsamples: %d\n"
.LC5:
.string "Error!\n"
.LC7:
.string "Estimated Value: "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB0:
call __printf_chk@PLT
movslq %r13d, %r14
leaq 96(%rsp), %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rdx
movq %r14, %rsi
call _ZNSt6vectorIfSaIfEEC1EmRKS0_
.LEHE0:
leaq 52(%rsp), %rdx
movq %r14, %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt6vectorIfSaIfEEC1EmRKS0_
.LEHE1:
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq 72(%rsp), %rax
movq 64(%rsp), %rbp
movq %rax, %r12
subq %rbp, %r12
sarq $2, %r12
cmpq %rbp, %rax
je .L31
movl $0, %ebx
.L32:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movq 96(%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
addq $1, %rbx
cmpq %r12, %rbx
jb .L32
.L31:
salq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
.LEHB2:
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 96(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movslq %r13d, %rbp
imulq $1125899907, %rbp, %rbp
sarq $49, %rbp
movl %r13d, %eax
sarl $31, %eax
subl %eax, %ebp
movslq %ebp, %r12
leaq 0(,%r12,4), %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $500, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebp, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl %r13d, %r8d
movl %ebp, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii
.L33:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L52
.L34:
movabsq $2305843009213693950, %rax
cmpq %r12, %rax
jb .L35
movq %rbx, %rdi
call _Znam@PLT
jmp .L53
.L52:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L34
.L53:
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
jmp .L54
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call __cxa_throw_bad_array_new_length@PLT
.L46:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L41:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L54:
cmpl $499999, %r13d
jle .L44
movl $0, %eax
movl $0, %ebx
.L39:
addl (%r12,%rax,4), %ebx
addq $1, %rax
cmpl %eax, %ebp
jg .L39
.L38:
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L55
.L44:
movl $0, %ebx
jmp .L38
.L55:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC6(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
divsd %xmm1, %xmm0
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movss %xmm2, 12(%rsp)
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L41
.L42:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L46-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl nsamples
.bss
.align 4
.type nsamples, @object
.size nsamples, 4
nsamples:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1074790400
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
using namespace std;
__global__
void count_samples_in_circles(float* d_randNumsX, float* d_randNumsY, int* d_countInBlocks, int num_blocks, int nsamples)
{
__shared__ int shared_blocks[500];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * num_blocks;
int inCircle = 0;
for (int i = index; i < nsamples; i+= stride) {
float xValue = d_randNumsX[i];
float yValue = d_randNumsY[i];
if (xValue*xValue + yValue*yValue <= 1.0f) {
inCircle++;
}
}
shared_blocks[threadIdx.x] = inCircle;
__syncthreads();
if (threadIdx.x == 0)
{
int totalInCircleForABlock = 0;
for (int j = 0; j < blockDim.x; j++)
{
totalInCircleForABlock += shared_blocks[j];
}
d_countInBlocks[blockIdx.x] = totalInCircleForABlock;
}
}
int nsamples;
int main(int argc, char* argv[]) {
int nsamples = atoi(argv[1]);
printf("nsamples: %d\n", nsamples);
vector<float> h_randNumsX(nsamples);
vector<float> h_randNumsY(nsamples);
srand(time(NULL));
for (int i = 0; i < h_randNumsX.size(); ++i)
{
h_randNumsX[i] = float(rand()) / RAND_MAX;
h_randNumsY[i] = float(rand()) / RAND_MAX;
}
size_t size = nsamples * sizeof(float);
float* d_randNumsX;
float* d_randNumsY;
cudaMalloc(&d_randNumsX, size);
cudaMalloc(&d_randNumsY, size);
cudaMemcpy(d_randNumsX, &h_randNumsX.front(), size, cudaMemcpyHostToDevice);
cudaMemcpy(d_randNumsY, &h_randNumsY.front(), size, cudaMemcpyHostToDevice);
int threadsPerBlock = 500;
int num_blocks = nsamples / (1000 * threadsPerBlock);
size_t countBlocks = num_blocks * sizeof(int);
int* d_countInBlocks;
cudaMalloc(&d_countInBlocks, countBlocks);
count_samples_in_circles<<<num_blocks, threadsPerBlock>>>(d_randNumsX, d_randNumsY, d_countInBlocks, num_blocks, nsamples);
if ( cudaSuccess != cudaGetLastError() )
cout << "Error!\n";
int* h_countInBlocks = new int[num_blocks];
cudaMemcpy(h_countInBlocks, d_countInBlocks, countBlocks, cudaMemcpyDeviceToHost);
int nsamples_in_circle = 0;
for (int i = 0 ; i < num_blocks; i++) {
nsamples_in_circle = nsamples_in_circle + h_countInBlocks[i];
}
cudaFree(d_randNumsX);
cudaFree(d_randNumsY);
cudaFree(d_countInBlocks);
float estimatedValue = 4.0 * float(nsamples_in_circle) / nsamples;
cout << "Estimated Value: " << estimatedValue << endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
using namespace std;
__global__
void count_samples_in_circles(float* d_randNumsX, float* d_randNumsY, int* d_countInBlocks, int num_blocks, int nsamples)
{
__shared__ int shared_blocks[500];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * num_blocks;
int inCircle = 0;
for (int i = index; i < nsamples; i+= stride) {
float xValue = d_randNumsX[i];
float yValue = d_randNumsY[i];
if (xValue*xValue + yValue*yValue <= 1.0f) {
inCircle++;
}
}
shared_blocks[threadIdx.x] = inCircle;
__syncthreads();
if (threadIdx.x == 0)
{
int totalInCircleForABlock = 0;
for (int j = 0; j < blockDim.x; j++)
{
totalInCircleForABlock += shared_blocks[j];
}
d_countInBlocks[blockIdx.x] = totalInCircleForABlock;
}
}
int nsamples;
int main(int argc, char* argv[]) {
int nsamples = atoi(argv[1]);
printf("nsamples: %d\n", nsamples);
vector<float> h_randNumsX(nsamples);
vector<float> h_randNumsY(nsamples);
srand(time(NULL));
for (int i = 0; i < h_randNumsX.size(); ++i)
{
h_randNumsX[i] = float(rand()) / RAND_MAX;
h_randNumsY[i] = float(rand()) / RAND_MAX;
}
size_t size = nsamples * sizeof(float);
float* d_randNumsX;
float* d_randNumsY;
hipMalloc(&d_randNumsX, size);
hipMalloc(&d_randNumsY, size);
hipMemcpy(d_randNumsX, &h_randNumsX.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_randNumsY, &h_randNumsY.front(), size, hipMemcpyHostToDevice);
int threadsPerBlock = 500;
int num_blocks = nsamples / (1000 * threadsPerBlock);
size_t countBlocks = num_blocks * sizeof(int);
int* d_countInBlocks;
hipMalloc(&d_countInBlocks, countBlocks);
count_samples_in_circles<<<num_blocks, threadsPerBlock>>>(d_randNumsX, d_randNumsY, d_countInBlocks, num_blocks, nsamples);
if ( hipSuccess != hipGetLastError() )
cout << "Error!\n";
int* h_countInBlocks = new int[num_blocks];
hipMemcpy(h_countInBlocks, d_countInBlocks, countBlocks, hipMemcpyDeviceToHost);
int nsamples_in_circle = 0;
for (int i = 0 ; i < num_blocks; i++) {
nsamples_in_circle = nsamples_in_circle + h_countInBlocks[i];
}
hipFree(d_randNumsX);
hipFree(d_randNumsY);
hipFree(d_countInBlocks);
float estimatedValue = 4.0 * float(nsamples_in_circle) / nsamples;
cout << "Estimated Value: " << estimatedValue << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
using namespace std;
__global__
void count_samples_in_circles(float* d_randNumsX, float* d_randNumsY, int* d_countInBlocks, int num_blocks, int nsamples)
{
__shared__ int shared_blocks[500];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * num_blocks;
int inCircle = 0;
for (int i = index; i < nsamples; i+= stride) {
float xValue = d_randNumsX[i];
float yValue = d_randNumsY[i];
if (xValue*xValue + yValue*yValue <= 1.0f) {
inCircle++;
}
}
shared_blocks[threadIdx.x] = inCircle;
__syncthreads();
if (threadIdx.x == 0)
{
int totalInCircleForABlock = 0;
for (int j = 0; j < blockDim.x; j++)
{
totalInCircleForABlock += shared_blocks[j];
}
d_countInBlocks[blockIdx.x] = totalInCircleForABlock;
}
}
int nsamples;
int main(int argc, char* argv[]) {
int nsamples = atoi(argv[1]);
printf("nsamples: %d\n", nsamples);
vector<float> h_randNumsX(nsamples);
vector<float> h_randNumsY(nsamples);
srand(time(NULL));
for (int i = 0; i < h_randNumsX.size(); ++i)
{
h_randNumsX[i] = float(rand()) / RAND_MAX;
h_randNumsY[i] = float(rand()) / RAND_MAX;
}
size_t size = nsamples * sizeof(float);
float* d_randNumsX;
float* d_randNumsY;
hipMalloc(&d_randNumsX, size);
hipMalloc(&d_randNumsY, size);
hipMemcpy(d_randNumsX, &h_randNumsX.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_randNumsY, &h_randNumsY.front(), size, hipMemcpyHostToDevice);
int threadsPerBlock = 500;
int num_blocks = nsamples / (1000 * threadsPerBlock);
size_t countBlocks = num_blocks * sizeof(int);
int* d_countInBlocks;
hipMalloc(&d_countInBlocks, countBlocks);
count_samples_in_circles<<<num_blocks, threadsPerBlock>>>(d_randNumsX, d_randNumsY, d_countInBlocks, num_blocks, nsamples);
if ( hipSuccess != hipGetLastError() )
cout << "Error!\n";
int* h_countInBlocks = new int[num_blocks];
hipMemcpy(h_countInBlocks, d_countInBlocks, countBlocks, hipMemcpyDeviceToHost);
int nsamples_in_circle = 0;
for (int i = 0 ; i < num_blocks; i++) {
nsamples_in_circle = nsamples_in_circle + h_countInBlocks[i];
}
hipFree(d_randNumsX);
hipFree(d_randNumsY);
hipFree(d_countInBlocks);
float estimatedValue = 4.0 * float(nsamples_in_circle) / nsamples;
cout << "Estimated Value: " << estimatedValue << endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z24count_samples_in_circlesPfS_Piii
.globl _Z24count_samples_in_circlesPfS_Piii
.p2align 8
.type _Z24count_samples_in_circlesPfS_Piii,@function
_Z24count_samples_in_circlesPfS_Piii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s9, s[0:1], 0x1c
s_mov_b32 s8, s15
v_mov_b32_e32 v4, 0
s_mov_b32 s14, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s8, s3, v[0:1]
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB0_4
s_clause 0x1
s_load_b32 s2, s[0:1], 0x18
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s10, s3, s2
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[12:13], s[10:11], 2
s_mov_b32 s11, 0
.p2align 6
.LBB0_2:
v_add_co_u32 v5, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v7, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
v_add_nc_u32_e32 v1, s10, v1
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, s12
v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s9, v1
s_or_b32 s11, vcc_lo, s11
s_waitcnt vmcnt(1)
v_mul_f32_e32 v5, v5, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v6
v_cmp_ge_f32_e64 s2, 1.0, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, 0, v4, s2
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s11
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s14
v_lshlrev_b32_e32 v1, 2, v0
s_mov_b32 s2, exec_lo
ds_store_b32 v1, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v0, 0
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB0_8
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v1, s2
s_add_i32 s3, s3, -1
s_add_i32 s2, s2, 4
s_cmp_eq_u32 s3, 0
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v0, v1, v0
s_cbranch_scc0 .LBB0_7
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s9, 0
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z24count_samples_in_circlesPfS_Piii
.amdhsa_group_segment_fixed_size 2000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z24count_samples_in_circlesPfS_Piii, .Lfunc_end0-_Z24count_samples_in_circlesPfS_Piii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2000
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z24count_samples_in_circlesPfS_Piii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z24count_samples_in_circlesPfS_Piii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <vector>
using namespace std;
__global__
void count_samples_in_circles(float* d_randNumsX, float* d_randNumsY, int* d_countInBlocks, int num_blocks, int nsamples)
{
__shared__ int shared_blocks[500];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * num_blocks;
int inCircle = 0;
for (int i = index; i < nsamples; i+= stride) {
float xValue = d_randNumsX[i];
float yValue = d_randNumsY[i];
if (xValue*xValue + yValue*yValue <= 1.0f) {
inCircle++;
}
}
shared_blocks[threadIdx.x] = inCircle;
__syncthreads();
if (threadIdx.x == 0)
{
int totalInCircleForABlock = 0;
for (int j = 0; j < blockDim.x; j++)
{
totalInCircleForABlock += shared_blocks[j];
}
d_countInBlocks[blockIdx.x] = totalInCircleForABlock;
}
}
int nsamples;
int main(int argc, char* argv[]) {
int nsamples = atoi(argv[1]);
printf("nsamples: %d\n", nsamples);
vector<float> h_randNumsX(nsamples);
vector<float> h_randNumsY(nsamples);
srand(time(NULL));
for (int i = 0; i < h_randNumsX.size(); ++i)
{
h_randNumsX[i] = float(rand()) / RAND_MAX;
h_randNumsY[i] = float(rand()) / RAND_MAX;
}
size_t size = nsamples * sizeof(float);
float* d_randNumsX;
float* d_randNumsY;
hipMalloc(&d_randNumsX, size);
hipMalloc(&d_randNumsY, size);
hipMemcpy(d_randNumsX, &h_randNumsX.front(), size, hipMemcpyHostToDevice);
hipMemcpy(d_randNumsY, &h_randNumsY.front(), size, hipMemcpyHostToDevice);
int threadsPerBlock = 500;
int num_blocks = nsamples / (1000 * threadsPerBlock);
size_t countBlocks = num_blocks * sizeof(int);
int* d_countInBlocks;
hipMalloc(&d_countInBlocks, countBlocks);
count_samples_in_circles<<<num_blocks, threadsPerBlock>>>(d_randNumsX, d_randNumsY, d_countInBlocks, num_blocks, nsamples);
if ( hipSuccess != hipGetLastError() )
cout << "Error!\n";
int* h_countInBlocks = new int[num_blocks];
hipMemcpy(h_countInBlocks, d_countInBlocks, countBlocks, hipMemcpyDeviceToHost);
int nsamples_in_circle = 0;
for (int i = 0 ; i < num_blocks; i++) {
nsamples_in_circle = nsamples_in_circle + h_countInBlocks[i];
}
hipFree(d_randNumsX);
hipFree(d_randNumsY);
hipFree(d_countInBlocks);
float estimatedValue = 4.0 * float(nsamples_in_circle) / nsamples;
cout << "Estimated Value: " << estimatedValue << endl;
} | .text
.file "pi_monte_carlo.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__count_samples_in_circlesPfS_Piii # -- Begin function _Z39__device_stub__count_samples_in_circlesPfS_Piii
.p2align 4, 0x90
.type _Z39__device_stub__count_samples_in_circlesPfS_Piii,@function
_Z39__device_stub__count_samples_in_circlesPfS_Piii: # @_Z39__device_stub__count_samples_in_circlesPfS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24count_samples_in_circlesPfS_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__count_samples_in_circlesPfS_Piii, .Lfunc_end0-_Z39__device_stub__count_samples_in_circlesPfS_Piii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r12d, %ebp
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movslq %r12d, %rax
movq %rax, %rcx
movq %rax, 16(%rsp) # 8-byte Spill
shrq $61, %rax
jne .LBB1_64
# %bb.1: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i
shlq $32, %r12
je .LBB1_2
# %bb.3: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i
movq %r12, %rdi
sarq $30, %rdi
.cfi_escape 0x2e, 0x00
callq _Znwm
movq %rax, %rbx
jmp .LBB1_4
.LBB1_2:
xorl %ebx, %ebx
.LBB1_4: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movabsq $4294967296, %r15 # imm = 0x100000000
movq %rbx, %r13
testq %r12, %r12
je .LBB1_7
# %bb.5:
movl $0, (%rbx)
leaq 4(%rbx), %r13
cmpq %r15, %r12
je .LBB1_7
# %bb.6: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rbx,%rax,4), %r14
movq %r12, %rdx
sarq $30, %rdx
addq $-4, %rdx
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
movq %r14, %r13
.LBB1_7: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i55
testq %r12, %r12
je .LBB1_8
# %bb.9: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i57
movq %r12, %rdi
sarq $30, %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.10:
movq %rax, %r14
jmp .LBB1_11
.LBB1_8:
xorl %r14d, %r14d
.LBB1_11: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i58
movl %ebp, 12(%rsp) # 4-byte Spill
testq %r12, %r12
je .LBB1_14
# %bb.12:
movl $0, (%r14)
cmpq %r15, %r12
je .LBB1_14
# %bb.13: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i59
leaq 4(%r14), %rdi
movq %r12, %rdx
sarq $30, %rdx
addq $-4, %rdx
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq memset@PLT
.LBB1_14: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit63
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq time
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq srand
subq %rbx, %r13
je .LBB1_17
# %bb.15: # %.lr.ph.preheader
sarq $2, %r13
cmpq $1, %r13
adcq $0, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_16: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%rbp,4)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_16
.LBB1_17: # %._crit_edge
sarq $30, %r12
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp4:
# %bb.18: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp6:
# %bb.19: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit66
movq 40(%rsp), %rdi
.Ltmp7:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp8:
# %bb.20:
movq 32(%rsp), %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp10:
# %bb.21:
imulq $1125899907, 16(%rsp), %rbp # 8-byte Folded Reload
# imm = 0x431BDE83
movq %rbp, %rax
shrq $63, %rax
sarq $49, %rbp
addl %eax, %ebp
movslq %ebp, %r12
shlq $2, %r12
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp13:
# %bb.22: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movl %ebp, %r13d
orq %r13, %r15
.Ltmp14:
.cfi_escape 0x2e, 0x00
movabsq $4294967796, %rdx # imm = 0x1000001F4
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp15:
# %bb.23:
testl %eax, %eax
jne .LBB1_26
# %bb.24:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %ebp, 52(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp17:
# %bb.25: # %.noexc68
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp18:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z24count_samples_in_circlesPfS_Piii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp19:
.LBB1_26:
.Ltmp20:
.cfi_escape 0x2e, 0x00
callq hipGetLastError
.Ltmp21:
# %bb.27:
testl %eax, %eax
je .LBB1_29
# %bb.28:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
.LBB1_29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl 12(%rsp), %ebp # 4-byte Reload
cmpl $-499999, %ebp # imm = 0xFFF85EE1
movq $-1, %rdi
cmovgeq %r12, %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp26:
# %bb.30:
movq %rax, %r15
movq 24(%rsp), %rsi
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp28:
# %bb.31: # %.preheader
xorps %xmm0, %xmm0
cmpl $500000, %ebp # imm = 0x7A120
jl .LBB1_35
# %bb.32: # %.lr.ph104.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_33: # %.lr.ph104
# =>This Inner Loop Header: Depth=1
addl (%r15,%rax,4), %ecx
incq %rax
cmpq %rax, %r13
jne .LBB1_33
# %bb.34: # %._crit_edge105.loopexit
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
.LBB1_35: # %._crit_edge105
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
.Ltmp30:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp31:
# %bb.36:
movq 32(%rsp), %rdi
.Ltmp32:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp33:
# %bb.37:
movq 24(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp35:
# %bb.38:
.Ltmp37:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.39: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit72
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
.Ltmp39:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp40:
# %bb.40: # %_ZNSolsEf.exit
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_41
# %bb.46: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_48
# %bb.47:
movzbl 67(%r12), %eax
jmp .LBB1_50
.LBB1_48:
.Ltmp41:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp42:
# %bb.49: # %.noexc83
movq (%r12), %rax
.Ltmp43:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp44:
.LBB1_50: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp45:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp46:
# %bb.51: # %.noexc85
.Ltmp47:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp48:
# %bb.52: # %_ZNSolsEPFRSoS_E.exit
testq %r14, %r14
je .LBB1_54
# %bb.53:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_54: # %_ZNSt6vectorIfSaIfEED2Ev.exit
testq %rbx, %rbx
je .LBB1_56
# %bb.55:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_56: # %_ZNSt6vectorIfSaIfEED2Ev.exit76
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_64: # %.noexc
.cfi_def_cfa_offset 224
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.LBB1_41:
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp50:
# %bb.45: # %.noexc82
.LBB1_65:
.Ltmp2:
movq %rax, %r15
testq %rbx, %rbx
je .LBB1_63
jmp .LBB1_62
.LBB1_44:
.Ltmp29:
jmp .LBB1_59
.LBB1_57:
.Ltmp36:
jmp .LBB1_59
.LBB1_42:
.Ltmp11:
jmp .LBB1_59
.LBB1_43:
.Ltmp24:
jmp .LBB1_59
.LBB1_58:
.Ltmp51:
.LBB1_59:
movq %rax, %r15
testq %r14, %r14
jne .LBB1_60
# %bb.61: # %_ZNSt6vectorIfSaIfEED2Ev.exit78
testq %rbx, %rbx
jne .LBB1_62
.LBB1_63: # %_ZNSt6vectorIfSaIfEED2Ev.exit80
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.LBB1_60:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
testq %rbx, %rbx
je .LBB1_63
.LBB1_62:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp3 # Call between .Ltmp3 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp12 # Call between .Ltmp12 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp28-.Ltmp25 # Call between .Ltmp25 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp35-.Ltmp30 # Call between .Ltmp30 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp48-.Ltmp37 # Call between .Ltmp37 and .Ltmp48
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp49-.Ltmp48 # Call between .Ltmp48 and .Ltmp49
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp50-.Ltmp49 # Call between .Ltmp49 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Lfunc_end1-.Ltmp50 # Call between .Ltmp50 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24count_samples_in_circlesPfS_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24count_samples_in_circlesPfS_Piii,@object # @_Z24count_samples_in_circlesPfS_Piii
.section .rodata,"a",@progbits
.globl _Z24count_samples_in_circlesPfS_Piii
.p2align 3, 0x0
_Z24count_samples_in_circlesPfS_Piii:
.quad _Z39__device_stub__count_samples_in_circlesPfS_Piii
.size _Z24count_samples_in_circlesPfS_Piii, 8
.type nsamples,@object # @nsamples
.bss
.globl nsamples
.p2align 2, 0x0
nsamples:
.long 0 # 0x0
.size nsamples, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "nsamples: %d\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error!\n"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Estimated Value: "
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.3, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24count_samples_in_circlesPfS_Piii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__count_samples_in_circlesPfS_Piii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z24count_samples_in_circlesPfS_Piii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014b59b_00000000-6_pi_monte_carlo.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii
.type _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii, @function
_Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii:
.LFB4057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z24count_samples_in_circlesPfS_Piii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii, .-_Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii
.globl _Z24count_samples_in_circlesPfS_Piii
.type _Z24count_samples_in_circlesPfS_Piii, @function
_Z24count_samples_in_circlesPfS_Piii:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z24count_samples_in_circlesPfS_Piii, .-_Z24count_samples_in_circlesPfS_Piii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z24count_samples_in_circlesPfS_Piii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z24count_samples_in_circlesPfS_Piii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt6vectorIfSaIfEEC2EmRKS0_.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "cannot create std::vector larger than max_size()"
.section .text._ZNSt6vectorIfSaIfEEC2EmRKS0_,"axG",@progbits,_ZNSt6vectorIfSaIfEEC5EmRKS0_,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEEC2EmRKS0_
.type _ZNSt6vectorIfSaIfEEC2EmRKS0_, @function
_ZNSt6vectorIfSaIfEEC2EmRKS0_:
.LFB4367:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rax
shrq $61, %rax
jne .L23
movq %rdi, %rbx
movq %rsi, %rbp
movq $0, (%rdi)
movq $0, 8(%rdi)
movq $0, 16(%rdi)
testq %rsi, %rsi
je .L15
leaq 0(,%rsi,4), %r12
movq %r12, %rdi
call _Znwm@PLT
movq %rax, (%rbx)
movq %rax, 8(%rbx)
leaq (%rax,%r12), %rdx
movq %rdx, 16(%rbx)
movl $0x00000000, (%rax)
addq $4, %rax
cmpq $1, %rbp
je .L18
cmpq %rax, %rdx
je .L19
.L17:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rax, %rdx
jne .L17
jmp .L16
.L23:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L18:
movq %rax, %rdx
jmp .L16
.L19:
movq %rax, %rdx
jmp .L16
.L15:
movq $0, (%rdi)
movq $0, 16(%rdi)
movl $0, %edx
.L16:
movq %rdx, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4367:
.size _ZNSt6vectorIfSaIfEEC2EmRKS0_, .-_ZNSt6vectorIfSaIfEEC2EmRKS0_
.weak _ZNSt6vectorIfSaIfEEC1EmRKS0_
.set _ZNSt6vectorIfSaIfEEC1EmRKS0_,_ZNSt6vectorIfSaIfEEC2EmRKS0_
.section .text._ZNSt6vectorIfSaIfEED2Ev,"axG",@progbits,_ZNSt6vectorIfSaIfEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIfSaIfEED2Ev
.type _ZNSt6vectorIfSaIfEED2Ev, @function
_ZNSt6vectorIfSaIfEED2Ev:
.LFB4370:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L27
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L27:
ret
.cfi_endproc
.LFE4370:
.size _ZNSt6vectorIfSaIfEED2Ev, .-_ZNSt6vectorIfSaIfEED2Ev
.weak _ZNSt6vectorIfSaIfEED1Ev
.set _ZNSt6vectorIfSaIfEED1Ev,_ZNSt6vectorIfSaIfEED2Ev
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "nsamples: %d\n"
.LC5:
.string "Error!\n"
.LC7:
.string "Estimated Value: "
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
addq $-128, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
.LEHB0:
call __printf_chk@PLT
movslq %r13d, %r14
leaq 96(%rsp), %rbx
leaq 64(%rsp), %rdi
movq %rbx, %rdx
movq %r14, %rsi
call _ZNSt6vectorIfSaIfEEC1EmRKS0_
.LEHE0:
leaq 52(%rsp), %rdx
movq %r14, %rsi
movq %rbx, %rdi
.LEHB1:
call _ZNSt6vectorIfSaIfEEC1EmRKS0_
.LEHE1:
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq 72(%rsp), %rax
movq 64(%rsp), %rbp
movq %rax, %r12
subq %rbp, %r12
sarq $2, %r12
cmpq %rbp, %rax
je .L31
movl $0, %ebx
.L32:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, 0(%rbp,%rbx,4)
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC4(%rip), %xmm0
movq 96(%rsp), %rax
movss %xmm0, (%rax,%rbx,4)
addq $1, %rbx
cmpq %r12, %rbx
jb .L32
.L31:
salq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
.LEHB2:
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq 96(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movslq %r13d, %rbp
imulq $1125899907, %rbp, %rbp
sarq $49, %rbp
movl %r13d, %eax
sarl $31, %eax
subl %eax, %ebp
movslq %ebp, %r12
leaq 0(,%r12,4), %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $500, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebp, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L33
movl %r13d, %r8d
movl %ebp, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z50__device_stub__Z24count_samples_in_circlesPfS_PiiiPfS_Piii
.L33:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L52
.L34:
movabsq $2305843009213693950, %rax
cmpq %r12, %rax
jb .L35
movq %rbx, %rdi
call _Znam@PLT
jmp .L53
.L52:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L34
.L53:
movq %rax, %r12
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
jmp .L54
.L35:
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L37
call __stack_chk_fail@PLT
.L37:
call __cxa_throw_bad_array_new_length@PLT
.L46:
endbr64
movq %rax, %rbx
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
.L41:
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L42
call __stack_chk_fail@PLT
.L54:
cmpl $499999, %r13d
jle .L44
movl $0, %eax
movl $0, %ebx
.L39:
addl (%r12,%rax,4), %ebx
addq $1, %rax
cmpl %eax, %ebp
jg .L39
.L38:
movq 16(%rsp), %rdi
call cudaFree@PLT
jmp .L55
.L44:
movl $0, %ebx
jmp .L38
.L55:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LC6(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
divsd %xmm1, %xmm0
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
movss %xmm2, 12(%rsp)
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE2:
leaq 96(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
leaq 64(%rsp), %rdi
call _ZNSt6vectorIfSaIfEED1Ev
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L56
movl $0, %eax
subq $-128, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
endbr64
movq %rax, %rbx
jmp .L41
.L42:
movq %rbx, %rdi
.LEHB3:
call _Unwind_Resume@PLT
.LEHE3:
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L45-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 .L46-.LFB4032
.uleb128 0
.uleb128 .LEHB3-.LFB4032
.uleb128 .LEHE3-.LEHB3
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl nsamples
.bss
.align 4
.type nsamples, @object
.size nsamples, 4
nsamples:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 805306368
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1074790400
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pi_monte_carlo.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z39__device_stub__count_samples_in_circlesPfS_Piii # -- Begin function _Z39__device_stub__count_samples_in_circlesPfS_Piii
.p2align 4, 0x90
.type _Z39__device_stub__count_samples_in_circlesPfS_Piii,@function
_Z39__device_stub__count_samples_in_circlesPfS_Piii: # @_Z39__device_stub__count_samples_in_circlesPfS_Piii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z24count_samples_in_circlesPfS_Piii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z39__device_stub__count_samples_in_circlesPfS_Piii, .Lfunc_end0-_Z39__device_stub__count_samples_in_circlesPfS_Piii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x4010000000000000 # double 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %r12d, %ebp
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movslq %r12d, %rax
movq %rax, %rcx
movq %rax, 16(%rsp) # 8-byte Spill
shrq $61, %rax
jne .LBB1_64
# %bb.1: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i
shlq $32, %r12
je .LBB1_2
# %bb.3: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i
movq %r12, %rdi
sarq $30, %rdi
.cfi_escape 0x2e, 0x00
callq _Znwm
movq %rax, %rbx
jmp .LBB1_4
.LBB1_2:
xorl %ebx, %ebx
.LBB1_4: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i
movabsq $4294967296, %r15 # imm = 0x100000000
movq %rbx, %r13
testq %r12, %r12
je .LBB1_7
# %bb.5:
movl $0, (%rbx)
leaq 4(%rbx), %r13
cmpq %r15, %r12
je .LBB1_7
# %bb.6: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rbx,%rax,4), %r14
movq %r12, %rdx
sarq $30, %rdx
addq $-4, %rdx
.cfi_escape 0x2e, 0x00
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
movq %r14, %r13
.LBB1_7: # %_ZNSt6vectorIfSaIfEE17_S_check_init_lenEmRKS0_.exit.i55
testq %r12, %r12
je .LBB1_8
# %bb.9: # %_ZNSt16allocator_traitsISaIfEE8allocateERS0_m.exit.i.i.i.i57
movq %r12, %rdi
sarq $30, %rdi
.Ltmp0:
.cfi_escape 0x2e, 0x00
callq _Znwm
.Ltmp1:
# %bb.10:
movq %rax, %r14
jmp .LBB1_11
.LBB1_8:
xorl %r14d, %r14d
.LBB1_11: # %_ZNSt12_Vector_baseIfSaIfEEC2EmRKS0_.exit.i58
movl %ebp, 12(%rsp) # 4-byte Spill
testq %r12, %r12
je .LBB1_14
# %bb.12:
movl $0, (%r14)
cmpq %r15, %r12
je .LBB1_14
# %bb.13: # %_ZSt6fill_nIPfmfET_S1_T0_RKT1_.exit.loopexit.i.i.i.i.i59
leaq 4(%r14), %rdi
movq %r12, %rdx
sarq $30, %rdx
addq $-4, %rdx
.cfi_escape 0x2e, 0x00
xorl %esi, %esi
callq memset@PLT
.LBB1_14: # %_ZNSt6vectorIfSaIfEEC2EmRKS0_.exit63
.cfi_escape 0x2e, 0x00
xorl %edi, %edi
callq time
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq srand
subq %rbx, %r13
je .LBB1_17
# %bb.15: # %.lr.ph.preheader
sarq $2, %r13
cmpq $1, %r13
adcq $0, %r13
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_16: # %.lr.ph
# =>This Inner Loop Header: Depth=1
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%rbp,4)
.cfi_escape 0x2e, 0x00
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, (%r14,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB1_16
.LBB1_17: # %._crit_edge
sarq $30, %r12
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 40(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp4:
# %bb.18: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit
.Ltmp5:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp6:
# %bb.19: # %_ZL9hipMallocIfE10hipError_tPPT_m.exit66
movq 40(%rsp), %rdi
.Ltmp7:
.cfi_escape 0x2e, 0x00
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp8:
# %bb.20:
movq 32(%rsp), %rdi
.Ltmp9:
.cfi_escape 0x2e, 0x00
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
.Ltmp10:
# %bb.21:
imulq $1125899907, 16(%rsp), %rbp # 8-byte Folded Reload
# imm = 0x431BDE83
movq %rbp, %rax
shrq $63, %rax
sarq $49, %rbp
addl %eax, %ebp
movslq %ebp, %r12
shlq $2, %r12
.Ltmp12:
.cfi_escape 0x2e, 0x00
leaq 24(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
.Ltmp13:
# %bb.22: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movl %ebp, %r13d
orq %r13, %r15
.Ltmp14:
.cfi_escape 0x2e, 0x00
movabsq $4294967796, %rdx # imm = 0x1000001F4
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp15:
# %bb.23:
testl %eax, %eax
jne .LBB1_26
# %bb.24:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %ebp, 52(%rsp)
movl 12(%rsp), %eax # 4-byte Reload
movl %eax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
.Ltmp16:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp17:
# %bb.25: # %.noexc68
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
.Ltmp18:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z24count_samples_in_circlesPfS_Piii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp19:
.LBB1_26:
.Ltmp20:
.cfi_escape 0x2e, 0x00
callq hipGetLastError
.Ltmp21:
# %bb.27:
testl %eax, %eax
je .LBB1_29
# %bb.28:
.Ltmp22:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp23:
.LBB1_29: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl 12(%rsp), %ebp # 4-byte Reload
cmpl $-499999, %ebp # imm = 0xFFF85EE1
movq $-1, %rdi
cmovgeq %r12, %rdi
.Ltmp25:
.cfi_escape 0x2e, 0x00
callq _Znam
.Ltmp26:
# %bb.30:
movq %rax, %r15
movq 24(%rsp), %rsi
.Ltmp27:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
.Ltmp28:
# %bb.31: # %.preheader
xorps %xmm0, %xmm0
cmpl $500000, %ebp # imm = 0x7A120
jl .LBB1_35
# %bb.32: # %.lr.ph104.preheader
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_33: # %.lr.ph104
# =>This Inner Loop Header: Depth=1
addl (%r15,%rax,4), %ecx
incq %rax
cmpq %rax, %r13
jne .LBB1_33
# %bb.34: # %._crit_edge105.loopexit
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
.LBB1_35: # %._crit_edge105
movsd %xmm0, 16(%rsp) # 8-byte Spill
movq 40(%rsp), %rdi
.Ltmp30:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp31:
# %bb.36:
movq 32(%rsp), %rdi
.Ltmp32:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp33:
# %bb.37:
movq 24(%rsp), %rdi
.Ltmp34:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp35:
# %bb.38:
.Ltmp37:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp38:
# %bb.39: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit72
xorps %xmm0, %xmm0
cvtsi2sd %ebp, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
.Ltmp39:
.cfi_escape 0x2e, 0x00
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp40:
# %bb.40: # %_ZNSolsEf.exit
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_41
# %bb.46: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r12)
je .LBB1_48
# %bb.47:
movzbl 67(%r12), %eax
jmp .LBB1_50
.LBB1_48:
.Ltmp41:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp42:
# %bb.49: # %.noexc83
movq (%r12), %rax
.Ltmp43:
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp44:
.LBB1_50: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp45:
.cfi_escape 0x2e, 0x00
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp46:
# %bb.51: # %.noexc85
.Ltmp47:
.cfi_escape 0x2e, 0x00
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp48:
# %bb.52: # %_ZNSolsEPFRSoS_E.exit
testq %r14, %r14
je .LBB1_54
# %bb.53:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB1_54: # %_ZNSt6vectorIfSaIfEED2Ev.exit
testq %rbx, %rbx
je .LBB1_56
# %bb.55:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.LBB1_56: # %_ZNSt6vectorIfSaIfEED2Ev.exit76
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_64: # %.noexc
.cfi_def_cfa_offset 224
.cfi_escape 0x2e, 0x00
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.LBB1_41:
.Ltmp49:
.cfi_escape 0x2e, 0x00
callq _ZSt16__throw_bad_castv
.Ltmp50:
# %bb.45: # %.noexc82
.LBB1_65:
.Ltmp2:
movq %rax, %r15
testq %rbx, %rbx
je .LBB1_63
jmp .LBB1_62
.LBB1_44:
.Ltmp29:
jmp .LBB1_59
.LBB1_57:
.Ltmp36:
jmp .LBB1_59
.LBB1_42:
.Ltmp11:
jmp .LBB1_59
.LBB1_43:
.Ltmp24:
jmp .LBB1_59
.LBB1_58:
.Ltmp51:
.LBB1_59:
movq %rax, %r15
testq %r14, %r14
jne .LBB1_60
# %bb.61: # %_ZNSt6vectorIfSaIfEED2Ev.exit78
testq %rbx, %rbx
jne .LBB1_62
.LBB1_63: # %_ZNSt6vectorIfSaIfEED2Ev.exit80
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.LBB1_60:
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
testq %rbx, %rbx
je .LBB1_63
.LBB1_62:
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp10-.Ltmp3 # Call between .Ltmp3 and .Ltmp10
.uleb128 .Ltmp11-.Lfunc_begin0 # jumps to .Ltmp11
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp23-.Ltmp12 # Call between .Ltmp12 and .Ltmp23
.uleb128 .Ltmp24-.Lfunc_begin0 # jumps to .Ltmp24
.byte 0 # On action: cleanup
.uleb128 .Ltmp25-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp28-.Ltmp25 # Call between .Ltmp25 and .Ltmp28
.uleb128 .Ltmp29-.Lfunc_begin0 # jumps to .Ltmp29
.byte 0 # On action: cleanup
.uleb128 .Ltmp30-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp35-.Ltmp30 # Call between .Ltmp30 and .Ltmp35
.uleb128 .Ltmp36-.Lfunc_begin0 # jumps to .Ltmp36
.byte 0 # On action: cleanup
.uleb128 .Ltmp37-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp48-.Ltmp37 # Call between .Ltmp37 and .Ltmp48
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp48-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp49-.Ltmp48 # Call between .Ltmp48 and .Ltmp49
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp49-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp50-.Ltmp49 # Call between .Ltmp49 and .Ltmp50
.uleb128 .Ltmp51-.Lfunc_begin0 # jumps to .Ltmp51
.byte 0 # On action: cleanup
.uleb128 .Ltmp50-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Lfunc_end1-.Ltmp50 # Call between .Ltmp50 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z24count_samples_in_circlesPfS_Piii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z24count_samples_in_circlesPfS_Piii,@object # @_Z24count_samples_in_circlesPfS_Piii
.section .rodata,"a",@progbits
.globl _Z24count_samples_in_circlesPfS_Piii
.p2align 3, 0x0
_Z24count_samples_in_circlesPfS_Piii:
.quad _Z39__device_stub__count_samples_in_circlesPfS_Piii
.size _Z24count_samples_in_circlesPfS_Piii, 8
.type nsamples,@object # @nsamples
.bss
.globl nsamples
.p2align 2, 0x0
nsamples:
.long 0 # 0x0
.size nsamples, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "nsamples: %d\n"
.size .L.str, 14
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error!\n"
.size .L.str.1, 8
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Estimated Value: "
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "cannot create std::vector larger than max_size()"
.size .L.str.3, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z24count_samples_in_circlesPfS_Piii"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z39__device_stub__count_samples_in_circlesPfS_Piii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z24count_samples_in_circlesPfS_Piii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void no_divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
int warp_id = gid / 32;
if (warp_id % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
}
}
}
__global__ void divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
if (gid % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", gid, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", gid, a);
}
}
}
void initInput(int* input, int size) {
for (int index = 0; index < size; index++) {
input[index] = index;
}
}
int main(void) {
dim3 size(32, 0, 0);
dim3 block_dim(0);
dim3 grid_dim(0);
int* h_input = NULL;
int* d_input = NULL;
h_input = (int*)calloc(size.x, sizeof(int));
initInput(h_input, size.x);
cudaMalloc((void**)&d_input, size.x * sizeof(int));
cudaMemcpy(d_input, h_input, size.x * sizeof(int), cudaMemcpyHostToDevice);
block_dim.x = 32;
grid_dim.x = size.x / block_dim.x + 1;
printf("\nno warp divergence occurred:\n");
no_divergence<<<grid_dim, block_dim>>>(d_input, size);
cudaDeviceSynchronize();
printf("\nwarp divergence occurred:\n");
divergence<<<grid_dim, block_dim>>>(d_input, size);
cudaDeviceSynchronize();
cudaFree(d_input);
free(h_input);
//// reset
cudaDeviceReset();
} | code for sm_80
Function : _Z10divergencePi4dim3
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0001e20000100800 */
/*0080*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fe400078ec0ff */
/*0090*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f3e0ff */
/*00a0*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fc60003f05070 */
/*00b0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fd400008e06ff */
/*00c0*/ @P0 BRA 0x1d0 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x001fe200078e00ff */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40690000 ; /* 0x40690000ff097424 */
/* 0x000fe400078e00ff */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0130*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0001ec0000100a00 */
/*0140*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe20000000000 */
/*0150*/ MOV R11, 0x1c0 ; /* 0x000001c0000b7802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R20, 0x140 ; /* 0x0000014000147802 */
/* 0x000fc40000000f00 */
/*0170*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0180*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0190*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01a0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01b0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x001fe200078e00ff */
/*01e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*01f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x40590000 ; /* 0x40590000ff037424 */
/* 0x000fe400078e00ff */
/*0200*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0210*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0220*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0230*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001ec0000100a00 */
/*0240*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*0250*/ MOV R11, 0x2c0 ; /* 0x000002c0000b7802 */
/* 0x000fe40000000f00 */
/*0260*/ MOV R20, 0x240 ; /* 0x0000024000147802 */
/* 0x000fc40000000f00 */
/*0270*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0280*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0290*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*02a0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*02b0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13no_divergencePi4dim3
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0080*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f3e0ff */
/*0090*/ LEA.HI R0, R3, R0, RZ, 0x5 ; /* 0x0000000003007211 */
/* 0x000fc600078f28ff */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*00b0*/ SHF.R.S32.HI R0, RZ, 0x5, R0 ; /* 0x00000005ff007819 */
/* 0x000fc80000011400 */
/*00c0*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fe200078ec0ff */
/*00d0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0001e60000100800 */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f05070 */
/*00f0*/ @P0 BRA 0x200 ; /* 0x0000010000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, 0x0 ; /* 0x00000000ff087424 */
/* 0x001fe200078e00ff */
/*0110*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R9, RZ, RZ, 0x40690000 ; /* 0x40690000ff097424 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0140*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0160*/ STL.64 [R1+0x8], R8 ; /* 0x0000080801007387 */
/* 0x0001ec0000100a00 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe20000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fc40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x001fe200078e00ff */
/*0210*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, 0x40590000 ; /* 0x40590000ff037424 */
/* 0x000fe400078e00ff */
/*0230*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0240*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0260*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001ec0000100a00 */
/*0270*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*0280*/ MOV R11, 0x2f0 ; /* 0x000002f0000b7802 */
/* 0x000fe40000000f00 */
/*0290*/ MOV R20, 0x270 ; /* 0x0000027000147802 */
/* 0x000fc40000000f00 */
/*02a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*02c0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*02d0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*02e0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void no_divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
int warp_id = gid / 32;
if (warp_id % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
}
}
}
__global__ void divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
if (gid % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", gid, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", gid, a);
}
}
}
void initInput(int* input, int size) {
for (int index = 0; index < size; index++) {
input[index] = index;
}
}
int main(void) {
dim3 size(32, 0, 0);
dim3 block_dim(0);
dim3 grid_dim(0);
int* h_input = NULL;
int* d_input = NULL;
h_input = (int*)calloc(size.x, sizeof(int));
initInput(h_input, size.x);
cudaMalloc((void**)&d_input, size.x * sizeof(int));
cudaMemcpy(d_input, h_input, size.x * sizeof(int), cudaMemcpyHostToDevice);
block_dim.x = 32;
grid_dim.x = size.x / block_dim.x + 1;
printf("\nno warp divergence occurred:\n");
no_divergence<<<grid_dim, block_dim>>>(d_input, size);
cudaDeviceSynchronize();
printf("\nwarp divergence occurred:\n");
divergence<<<grid_dim, block_dim>>>(d_input, size);
cudaDeviceSynchronize();
cudaFree(d_input);
free(h_input);
//// reset
cudaDeviceReset();
} | .file "tmpxft_001ae7b0_00000000-6_warp_divergence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9initInputPii
.type _Z9initInputPii, @function
_Z9initInputPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9initInputPii, .-_Z9initInputPii
.globl _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3
.type _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3, @function
_Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsi, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13no_divergencePi4dim3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3, .-_Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3
.globl _Z13no_divergencePi4dim3
.type _Z13no_divergencePi4dim3, @function
_Z13no_divergencePi4dim3:
.LFB2084:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %rsp, %rsi
call _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13no_divergencePi4dim3, .-_Z13no_divergencePi4dim3
.globl _Z35__device_stub__Z10divergencePi4dim3PiR4dim3
.type _Z35__device_stub__Z10divergencePi4dim3PiR4dim3, @function
_Z35__device_stub__Z10divergencePi4dim3PiR4dim3:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsi, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10divergencePi4dim3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z10divergencePi4dim3PiR4dim3, .-_Z35__device_stub__Z10divergencePi4dim3PiR4dim3
.globl _Z10divergencePi4dim3
.type _Z10divergencePi4dim3, @function
_Z10divergencePi4dim3:
.LFB2086:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %rsp, %rsi
call _Z35__device_stub__Z10divergencePi4dim3PiR4dim3
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10divergencePi4dim3, .-_Z10divergencePi4dim3
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nno warp divergence occurred:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nwarp divergence occurred:\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq $0, 8(%rsp)
movl $4, %esi
movl $32, %edi
call calloc@PLT
movq %rax, %rbx
movl $32, %esi
movq %rax, %rdi
call _Z9initInputPii
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 32(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, 20(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $32, 44(%rsp)
movl $0, 48(%rsp)
movl $0, 52(%rsp)
leaq 44(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3
jmp .L24
.L29:
movl $32, 44(%rsp)
movl $0, 48(%rsp)
movl $0, 52(%rsp)
leaq 44(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10divergencePi4dim3PiR4dim3
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10divergencePi4dim3"
.LC3:
.string "_Z13no_divergencePi4dim3"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10divergencePi4dim3(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13no_divergencePi4dim3(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void no_divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
int warp_id = gid / 32;
if (warp_id % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
}
}
}
__global__ void divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
if (gid % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", gid, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", gid, a);
}
}
}
void initInput(int* input, int size) {
for (int index = 0; index < size; index++) {
input[index] = index;
}
}
int main(void) {
dim3 size(32, 0, 0);
dim3 block_dim(0);
dim3 grid_dim(0);
int* h_input = NULL;
int* d_input = NULL;
h_input = (int*)calloc(size.x, sizeof(int));
initInput(h_input, size.x);
cudaMalloc((void**)&d_input, size.x * sizeof(int));
cudaMemcpy(d_input, h_input, size.x * sizeof(int), cudaMemcpyHostToDevice);
block_dim.x = 32;
grid_dim.x = size.x / block_dim.x + 1;
printf("\nno warp divergence occurred:\n");
no_divergence<<<grid_dim, block_dim>>>(d_input, size);
cudaDeviceSynchronize();
printf("\nwarp divergence occurred:\n");
divergence<<<grid_dim, block_dim>>>(d_input, size);
cudaDeviceSynchronize();
cudaFree(d_input);
free(h_input);
//// reset
cudaDeviceReset();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void no_divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
int warp_id = gid / 32;
if (warp_id % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
}
}
}
__global__ void divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
if (gid % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", gid, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", gid, a);
}
}
}
void initInput(int* input, int size) {
for (int index = 0; index < size; index++) {
input[index] = index;
}
}
int main(void) {
dim3 size(32, 0, 0);
dim3 block_dim(0);
dim3 grid_dim(0);
int* h_input = NULL;
int* d_input = NULL;
h_input = (int*)calloc(size.x, sizeof(int));
initInput(h_input, size.x);
hipMalloc((void**)&d_input, size.x * sizeof(int));
hipMemcpy(d_input, h_input, size.x * sizeof(int), hipMemcpyHostToDevice);
block_dim.x = 32;
grid_dim.x = size.x / block_dim.x + 1;
printf("\nno warp divergence occurred:\n");
no_divergence<<<grid_dim, block_dim>>>(d_input, size);
hipDeviceSynchronize();
printf("\nwarp divergence occurred:\n");
divergence<<<grid_dim, block_dim>>>(d_input, size);
hipDeviceSynchronize();
hipFree(d_input);
free(h_input);
//// reset
hipDeviceReset();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void no_divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
int warp_id = gid / 32;
if (warp_id % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", warp_id, a);
}
}
}
__global__ void divergence(int* input, dim3 size) {
int gid = blockIdx.x * blockDim.x + threadIdx.x;
if (gid < size.x) {
float a = 0.0;
if (gid % 2 == 0) {
a = 100.0;
printf("warp(%d), a(%.0f)\n", gid, a);
} else {
a = 200.0;
printf("warp(%d), a(%.0f)\n", gid, a);
}
}
}
void initInput(int* input, int size) {
for (int index = 0; index < size; index++) {
input[index] = index;
}
}
int main(void) {
dim3 size(32, 0, 0);
dim3 block_dim(0);
dim3 grid_dim(0);
int* h_input = NULL;
int* d_input = NULL;
h_input = (int*)calloc(size.x, sizeof(int));
initInput(h_input, size.x);
hipMalloc((void**)&d_input, size.x * sizeof(int));
hipMemcpy(d_input, h_input, size.x * sizeof(int), hipMemcpyHostToDevice);
block_dim.x = 32;
grid_dim.x = size.x / block_dim.x + 1;
printf("\nno warp divergence occurred:\n");
no_divergence<<<grid_dim, block_dim>>>(d_input, size);
hipDeviceSynchronize();
printf("\nwarp divergence occurred:\n");
divergence<<<grid_dim, block_dim>>>(d_input, size);
hipDeviceSynchronize();
hipFree(d_input);
free(h_input);
//// reset
hipDeviceReset();
} | .text
.file "warp_divergence.hip"
.globl _Z28__device_stub__no_divergencePi4dim3 # -- Begin function _Z28__device_stub__no_divergencePi4dim3
.p2align 4, 0x90
.type _Z28__device_stub__no_divergencePi4dim3,@function
_Z28__device_stub__no_divergencePi4dim3: # @_Z28__device_stub__no_divergencePi4dim3
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsi, 64(%rsp)
movl %edx, 72(%rsp)
movq %rdi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13no_divergencePi4dim3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__no_divergencePi4dim3, .Lfunc_end0-_Z28__device_stub__no_divergencePi4dim3
.cfi_endproc
# -- End function
.globl _Z25__device_stub__divergencePi4dim3 # -- Begin function _Z25__device_stub__divergencePi4dim3
.p2align 4, 0x90
.type _Z25__device_stub__divergencePi4dim3,@function
_Z25__device_stub__divergencePi4dim3: # @_Z25__device_stub__divergencePi4dim3
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsi, 64(%rsp)
movl %edx, 72(%rsp)
movq %rdi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10divergencePi4dim3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__divergencePi4dim3, .Lfunc_end1-_Z25__device_stub__divergencePi4dim3
.cfi_endproc
# -- End function
.globl _Z9initInputPii # -- Begin function _Z9initInputPii
.p2align 4, 0x90
.type _Z9initInputPii,@function
_Z9initInputPii: # @_Z9initInputPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9initInputPii, .Lfunc_end2-_Z9initInputPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.preheader.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, (%rsp)
movl $32, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB3_1
# %bb.2: # %_Z9initInputPii.exit
movabsq $4294967298, %r14 # imm = 0x100000002
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
leaq 30(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq (%rsp), %rax
movq $32, 64(%rsp)
movl $0, 72(%rsp)
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13no_divergencePi4dim3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq (%rsp), %rax
movq $32, 64(%rsp)
movl $0, 72(%rsp)
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10divergencePi4dim3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13no_divergencePi4dim3, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10divergencePi4dim3, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13no_divergencePi4dim3,@object # @_Z13no_divergencePi4dim3
.section .rodata,"a",@progbits
.globl _Z13no_divergencePi4dim3
.p2align 3, 0x0
_Z13no_divergencePi4dim3:
.quad _Z28__device_stub__no_divergencePi4dim3
.size _Z13no_divergencePi4dim3, 8
.type _Z10divergencePi4dim3,@object # @_Z10divergencePi4dim3
.globl _Z10divergencePi4dim3
.p2align 3, 0x0
_Z10divergencePi4dim3:
.quad _Z25__device_stub__divergencePi4dim3
.size _Z10divergencePi4dim3, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13no_divergencePi4dim3"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10divergencePi4dim3"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nno warp divergence occurred:"
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nwarp divergence occurred:"
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__no_divergencePi4dim3
.addrsig_sym _Z25__device_stub__divergencePi4dim3
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13no_divergencePi4dim3
.addrsig_sym _Z10divergencePi4dim3
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ae7b0_00000000-6_warp_divergence.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9initInputPii
.type _Z9initInputPii, @function
_Z9initInputPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
movl %eax, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z9initInputPii, .-_Z9initInputPii
.globl _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3
.type _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3, @function
_Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsi, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13no_divergencePi4dim3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3, .-_Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3
.globl _Z13no_divergencePi4dim3
.type _Z13no_divergencePi4dim3, @function
_Z13no_divergencePi4dim3:
.LFB2084:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %rsp, %rsi
call _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z13no_divergencePi4dim3, .-_Z13no_divergencePi4dim3
.globl _Z35__device_stub__Z10divergencePi4dim3PiR4dim3
.type _Z35__device_stub__Z10divergencePi4dim3PiR4dim3, @function
_Z35__device_stub__Z10divergencePi4dim3PiR4dim3:
.LFB2085:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsi, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10divergencePi4dim3(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z10divergencePi4dim3PiR4dim3, .-_Z35__device_stub__Z10divergencePi4dim3PiR4dim3
.globl _Z10divergencePi4dim3
.type _Z10divergencePi4dim3, @function
_Z10divergencePi4dim3:
.LFB2086:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsi, (%rsp)
movl %edx, 8(%rsp)
movq %rsp, %rsi
call _Z35__device_stub__Z10divergencePi4dim3PiR4dim3
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z10divergencePi4dim3, .-_Z10divergencePi4dim3
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "\nno warp divergence occurred:\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nwarp divergence occurred:\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movq $0, 8(%rsp)
movl $4, %esi
movl $32, %edi
call calloc@PLT
movq %rax, %rbx
movl $32, %esi
movq %rax, %rdi
call _Z9initInputPii
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $128, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 32(%rsp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, 20(%rsp)
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L28
.L24:
call cudaDeviceSynchronize@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movq 32(%rsp), %rdi
movl 40(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
movl $32, 44(%rsp)
movl $0, 48(%rsp)
movl $0, 52(%rsp)
leaq 44(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z13no_divergencePi4dim3PiR4dim3
jmp .L24
.L29:
movl $32, 44(%rsp)
movl $0, 48(%rsp)
movl $0, 52(%rsp)
leaq 44(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z35__device_stub__Z10divergencePi4dim3PiR4dim3
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z10divergencePi4dim3"
.LC3:
.string "_Z13no_divergencePi4dim3"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z10divergencePi4dim3(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z13no_divergencePi4dim3(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "warp_divergence.hip"
.globl _Z28__device_stub__no_divergencePi4dim3 # -- Begin function _Z28__device_stub__no_divergencePi4dim3
.p2align 4, 0x90
.type _Z28__device_stub__no_divergencePi4dim3,@function
_Z28__device_stub__no_divergencePi4dim3: # @_Z28__device_stub__no_divergencePi4dim3
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsi, 64(%rsp)
movl %edx, 72(%rsp)
movq %rdi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13no_divergencePi4dim3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__no_divergencePi4dim3, .Lfunc_end0-_Z28__device_stub__no_divergencePi4dim3
.cfi_endproc
# -- End function
.globl _Z25__device_stub__divergencePi4dim3 # -- Begin function _Z25__device_stub__divergencePi4dim3
.p2align 4, 0x90
.type _Z25__device_stub__divergencePi4dim3,@function
_Z25__device_stub__divergencePi4dim3: # @_Z25__device_stub__divergencePi4dim3
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rsi, 64(%rsp)
movl %edx, 72(%rsp)
movq %rdi, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10divergencePi4dim3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__divergencePi4dim3, .Lfunc_end1-_Z25__device_stub__divergencePi4dim3
.cfi_endproc
# -- End function
.globl _Z9initInputPii # -- Begin function _Z9initInputPii
.p2align 4, 0x90
.type _Z9initInputPii,@function
_Z9initInputPii: # @_Z9initInputPii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB2_2
.LBB2_3: # %._crit_edge
retq
.Lfunc_end2:
.size _Z9initInputPii, .Lfunc_end2-_Z9initInputPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %.lr.ph.preheader.i
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $96, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq $0, (%rsp)
movl $32, %edi
movl $4, %esi
callq calloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
incq %rax
cmpq $32, %rax
jne .LBB3_1
# %bb.2: # %_Z9initInputPii.exit
movabsq $4294967298, %r14 # imm = 0x100000002
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movq (%rsp), %rdi
movl $128, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
leaq 30(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq (%rsp), %rax
movq $32, 64(%rsp)
movl $0, 72(%rsp)
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13no_divergencePi4dim3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_6
# %bb.5:
movq (%rsp), %rax
movq $32, 64(%rsp)
movl $0, 72(%rsp)
movq %rax, 56(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10divergencePi4dim3, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_6:
callq hipDeviceSynchronize
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $96, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13no_divergencePi4dim3, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10divergencePi4dim3, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13no_divergencePi4dim3,@object # @_Z13no_divergencePi4dim3
.section .rodata,"a",@progbits
.globl _Z13no_divergencePi4dim3
.p2align 3, 0x0
_Z13no_divergencePi4dim3:
.quad _Z28__device_stub__no_divergencePi4dim3
.size _Z13no_divergencePi4dim3, 8
.type _Z10divergencePi4dim3,@object # @_Z10divergencePi4dim3
.globl _Z10divergencePi4dim3
.p2align 3, 0x0
_Z10divergencePi4dim3:
.quad _Z25__device_stub__divergencePi4dim3
.size _Z10divergencePi4dim3, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13no_divergencePi4dim3"
.size .L__unnamed_1, 25
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10divergencePi4dim3"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nno warp divergence occurred:"
.size .Lstr, 30
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nwarp divergence occurred:"
.size .Lstr.1, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__no_divergencePi4dim3
.addrsig_sym _Z25__device_stub__divergencePi4dim3
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13no_divergencePi4dim3
.addrsig_sym _Z10divergencePi4dim3
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_i(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = src[bid * dpitch + tid];
if( tid < dpitch) dst[bid * spitch + tid] = res;
} | code for sm_80
Function : _Z8spread_iPdjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0080*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0090*/ IMAD R2, R0, c[0x0][0x178], R5 ; /* 0x00005e0000027a24 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0007 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD R4, R0, c[0x0][0x168], R5 ; /* 0x00005a0000047a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0007 */
/*00e0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_i(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = src[bid * dpitch + tid];
if( tid < dpitch) dst[bid * spitch + tid] = res;
} | .file "tmpxft_00041680_00000000-6_spread_i.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8spread_iPdjS_jPdjS_j
.type _Z31__device_stub__Z8spread_iPdjS_jPdjS_j, @function
_Z31__device_stub__Z8spread_iPdjS_jPdjS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8spread_iPdjS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z8spread_iPdjS_jPdjS_j, .-_Z31__device_stub__Z8spread_iPdjS_jPdjS_j
.globl _Z8spread_iPdjS_j
.type _Z8spread_iPdjS_j, @function
_Z8spread_iPdjS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8spread_iPdjS_jPdjS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8spread_iPdjS_j, .-_Z8spread_iPdjS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8spread_iPdjS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8spread_iPdjS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_i(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = src[bid * dpitch + tid];
if( tid < dpitch) dst[bid * spitch + tid] = res;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_i(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = src[bid * dpitch + tid];
if( tid < dpitch) dst[bid * spitch + tid] = res;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_i(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = src[bid * dpitch + tid];
if( tid < dpitch) dst[bid * spitch + tid] = res;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8spread_iPdjS_j
.globl _Z8spread_iPdjS_j
.p2align 8
.type _Z8spread_iPdjS_j,@function
_Z8spread_iPdjS_j:
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
v_mad_u64_u32 v[1:2], null, s3, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s3, s2, v[0:1]
v_mov_b32_e32 v6, v2
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8spread_iPdjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8spread_iPdjS_j, .Lfunc_end0-_Z8spread_iPdjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8spread_iPdjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8spread_iPdjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread_i(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = src[bid * dpitch + tid];
if( tid < dpitch) dst[bid * spitch + tid] = res;
} | .text
.file "spread_i.hip"
.globl _Z23__device_stub__spread_iPdjS_j # -- Begin function _Z23__device_stub__spread_iPdjS_j
.p2align 4, 0x90
.type _Z23__device_stub__spread_iPdjS_j,@function
_Z23__device_stub__spread_iPdjS_j: # @_Z23__device_stub__spread_iPdjS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8spread_iPdjS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__spread_iPdjS_j, .Lfunc_end0-_Z23__device_stub__spread_iPdjS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8spread_iPdjS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8spread_iPdjS_j,@object # @_Z8spread_iPdjS_j
.section .rodata,"a",@progbits
.globl _Z8spread_iPdjS_j
.p2align 3, 0x0
_Z8spread_iPdjS_j:
.quad _Z23__device_stub__spread_iPdjS_j
.size _Z8spread_iPdjS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8spread_iPdjS_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__spread_iPdjS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8spread_iPdjS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8spread_iPdjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002600 */
/*0080*/ IMAD R0, R3, c[0x0][0xc], R0 ; /* 0x0000030003007a24 */
/* 0x001fc800078e0200 */
/*0090*/ IMAD R2, R0, c[0x0][0x178], R5 ; /* 0x00005e0000027a24 */
/* 0x000fc800078e0205 */
/*00a0*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0007 */
/*00b0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD R4, R0, c[0x0][0x168], R5 ; /* 0x00005a0000047a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0007 */
/*00e0*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x004fe2000c101b04 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8spread_iPdjS_j
.globl _Z8spread_iPdjS_j
.p2align 8
.type _Z8spread_iPdjS_j,@function
_Z8spread_iPdjS_j:
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b64 s[4:5], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s14
v_mad_u64_u32 v[1:2], null, s3, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_clause 0x1
s_load_b32 s2, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[5:6], null, s3, s2, v[0:1]
v_mov_b32_e32 v6, v2
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[0:1], v[3:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8spread_iPdjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8spread_iPdjS_j, .Lfunc_end0-_Z8spread_iPdjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8spread_iPdjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8spread_iPdjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041680_00000000-6_spread_i.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8spread_iPdjS_jPdjS_j
.type _Z31__device_stub__Z8spread_iPdjS_jPdjS_j, @function
_Z31__device_stub__Z8spread_iPdjS_jPdjS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8spread_iPdjS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z8spread_iPdjS_jPdjS_j, .-_Z31__device_stub__Z8spread_iPdjS_jPdjS_j
.globl _Z8spread_iPdjS_j
.type _Z8spread_iPdjS_j, @function
_Z8spread_iPdjS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8spread_iPdjS_jPdjS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8spread_iPdjS_j, .-_Z8spread_iPdjS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8spread_iPdjS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8spread_iPdjS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "spread_i.hip"
.globl _Z23__device_stub__spread_iPdjS_j # -- Begin function _Z23__device_stub__spread_iPdjS_j
.p2align 4, 0x90
.type _Z23__device_stub__spread_iPdjS_j,@function
_Z23__device_stub__spread_iPdjS_j: # @_Z23__device_stub__spread_iPdjS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8spread_iPdjS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__spread_iPdjS_j, .Lfunc_end0-_Z23__device_stub__spread_iPdjS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8spread_iPdjS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8spread_iPdjS_j,@object # @_Z8spread_iPdjS_j
.section .rodata,"a",@progbits
.globl _Z8spread_iPdjS_j
.p2align 3, 0x0
_Z8spread_iPdjS_j:
.quad _Z23__device_stub__spread_iPdjS_j
.size _Z8spread_iPdjS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8spread_iPdjS_j"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__spread_iPdjS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8spread_iPdjS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // pi2.cu
/*
* A simple CUDA-enabled program that approximates \pi using monte-carlo
* sampling. This version generates random numbers on-the-fly within each
* kernel.
*/
#include <iostream>
#include <curand.h>
#include <curand_kernel.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdbool.h>
using namespace std;
__global__ void initThreads(float* d_out, curandState_t* states) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
curand_init(idx, idx, 0, &states[idx]);
d_out[idx] = 0.0;
}
__global__ void pi(float* d_out, curandState_t* states, int N_TRIALS) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
curandState_t tmp_state = states[idx];
int count = 0;
for(int i=1; i <= N_TRIALS; i++) {
float x = curand_uniform(&tmp_state);
float y = curand_uniform(&tmp_state);
if( x*x + y*y <= 1.0f ) {
count++;
}
}
states[idx] = tmp_state;
d_out[idx] += float(count)/float(N_TRIALS);
}
int main(int argc, char** argv) {
int GRID_SIZE = 256;
int BLOCK_SIZE = 256;
int N_TRIALS = 1000;
int N_RUNS = 10;
char x;
opterr = 0;
while((x = getopt(argc, argv, "g:b:t:r:")) != -1) {
switch(x) {
case 'g': GRID_SIZE = atoi(optarg); break;
case 'b': BLOCK_SIZE = atoi(optarg); break;
case 't': N_TRIALS = atoi(optarg); break;
case 'r': N_RUNS = atoi(optarg); break;
case '?':
if (optopt == 'g' || optopt == 'b' || optopt == 't' || optopt == 'r') {
fprintf (stderr, "Option -%c requires an argument.\n", optopt);
} else {
fprintf (stderr, "Unknown option `-%c'.\n", optopt);
}
abort();
default: abort();
}
}
int N_KERNELS = GRID_SIZE * BLOCK_SIZE;
float* h_pis = (float*) malloc(N_KERNELS*sizeof(float));
float* d_pis;
cudaMalloc(&d_pis, N_KERNELS * sizeof(float));
curandState_t* states;
cudaMalloc(&states, N_KERNELS * sizeof(curandState_t));
time_t start = clock();
initThreads<<<GRID_SIZE, BLOCK_SIZE>>>(d_pis, states);
for(int irun=1; irun <= N_RUNS; irun++) {
pi<<<GRID_SIZE, BLOCK_SIZE>>>(d_pis, states, N_TRIALS);
}
cudaMemcpy(h_pis, d_pis, N_KERNELS*sizeof(float), cudaMemcpyDeviceToHost);
float avg = 0.0;
for(int i=0; i < N_KERNELS; i++) {
avg += h_pis[i] / N_RUNS;
}
avg /= N_KERNELS;
time_t end = clock();
int64_t iters = int64_t(N_KERNELS)*int64_t(N_TRIALS)*int64_t(N_RUNS);
int elapsed = 1000*(end-start)/CLOCKS_PER_SEC;
cout << 4*avg << "\n";
cout << elapsed << "\n";
cout << float(iters)/float(elapsed) << " iters/ms\n";
free(h_pis);
cudaFree(d_pis);
cudaFree(states);
return 0;
} | .file "tmpxft_000290ff_00000000-6_pi2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3899:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3899:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW
.type _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW, @function
_Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW:
.LFB3921:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11initThreadsPfP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3921:
.size _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW, .-_Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW
.globl _Z11initThreadsPfP17curandStateXORWOW
.type _Z11initThreadsPfP17curandStateXORWOW, @function
_Z11initThreadsPfP17curandStateXORWOW:
.LFB3922:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3922:
.size _Z11initThreadsPfP17curandStateXORWOW, .-_Z11initThreadsPfP17curandStateXORWOW
.globl _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi
.type _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi, @function
_Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi:
.LFB3923:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2piPfP17curandStateXORWOWi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi, .-_Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi
.globl _Z2piPfP17curandStateXORWOWi
.type _Z2piPfP17curandStateXORWOWi, @function
_Z2piPfP17curandStateXORWOWi:
.LFB3924:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3924:
.size _Z2piPfP17curandStateXORWOWi, .-_Z2piPfP17curandStateXORWOWi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Option -%c requires an argument.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Unknown option `-%c'.\n"
.LC3:
.string "g:b:t:r:"
.LC5:
.string "\n"
.LC6:
.string " iters/ms\n"
.text
.globl main
.type main, @function
main:
.LFB3896:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %r13d
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, opterr(%rip)
movl $10, %ebx
movl $1000, 12(%rsp)
movl $256, %ebp
movl $256, %r15d
leaq .LC3(%rip), %r14
jmp .L20
.L44:
cmpb $63, %al
je .L23
cmpb $98, %al
jne .L25
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L20
.L21:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
.L20:
movq %r14, %rdx
movq %r12, %rsi
movl %r13d, %edi
call getopt@PLT
cmpb $-1, %al
je .L43
cmpb $103, %al
je .L21
jle .L44
cmpb $114, %al
je .L26
cmpb $116, %al
jne .L25
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 12(%rsp)
jmp .L20
.L26:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L20
.L23:
movl optopt(%rip), %ecx
leal -98(%rcx), %eax
cmpl $18, %eax
ja .L29
movl $327713, %edx
btq %rax, %rdx
jnc .L29
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L30:
call abort@PLT
.L29:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L25:
call abort@PLT
.L43:
movl %r15d, %r13d
imull %ebp, %r13d
movslq %r13d, %r14
leaq 0(,%r14,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq (%r14,%r14,2), %rsi
salq $4, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
call clock@PLT
movq %rax, 24(%rsp)
movl %ebp, %r14d
movl %ebp, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L32:
testl %ebx, %ebx
jle .L33
movl $1, %ebp
jmp .L35
.L45:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW
jmp .L32
.L34:
addl $1, %ebp
cmpl %ebp, %ebx
jl .L33
.L35:
movl %r14d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movl 12(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi
jmp .L34
.L33:
movl $2, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 16(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L39
movq %r15, %rax
addq %r15, %r12
pxor %xmm0, %xmm0
pxor %xmm2, %xmm2
cvtsi2ssl %ebx, %xmm2
.L37:
movss (%rax), %xmm1
divss %xmm2, %xmm1
addss %xmm1, %xmm0
addq $4, %rax
cmpq %r12, %rax
jne .L37
.L36:
pxor %xmm1, %xmm1
cvtsi2ssl %r13d, %xmm1
divss %xmm1, %xmm0
movd %xmm0, %ebp
call clock@PLT
movslq %r13d, %r13
movslq 12(%rsp), %rdx
imulq %rdx, %r13
movslq %ebx, %rbx
imulq %rbx, %r13
movq 24(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
movd %ebp, %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %r14
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %r13, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pxor %xmm0, %xmm0
jmp .L36
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3896:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z2piPfP17curandStateXORWOWi"
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z11initThreadsPfP17curandStateXORWOW"
.section .rodata.str1.1
.LC9:
.string "precalc_xorwow_matrix"
.LC10:
.string "precalc_xorwow_offset_matrix"
.LC11:
.string "mrg32k3aM1"
.LC12:
.string "mrg32k3aM2"
.LC13:
.string "mrg32k3aM1SubSeq"
.LC14:
.string "mrg32k3aM2SubSeq"
.LC15:
.string "mrg32k3aM1Seq"
.LC16:
.string "mrg32k3aM2Seq"
.LC17:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3926:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z2piPfP17curandStateXORWOWi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z11initThreadsPfP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3926:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // pi2.cu
/*
* A simple CUDA-enabled program that approximates \pi using monte-carlo
* sampling. This version generates random numbers on-the-fly within each
* kernel.
*/
#include <iostream>
#include <curand.h>
#include <curand_kernel.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdbool.h>
using namespace std;
__global__ void initThreads(float* d_out, curandState_t* states) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
curand_init(idx, idx, 0, &states[idx]);
d_out[idx] = 0.0;
}
__global__ void pi(float* d_out, curandState_t* states, int N_TRIALS) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
curandState_t tmp_state = states[idx];
int count = 0;
for(int i=1; i <= N_TRIALS; i++) {
float x = curand_uniform(&tmp_state);
float y = curand_uniform(&tmp_state);
if( x*x + y*y <= 1.0f ) {
count++;
}
}
states[idx] = tmp_state;
d_out[idx] += float(count)/float(N_TRIALS);
}
int main(int argc, char** argv) {
int GRID_SIZE = 256;
int BLOCK_SIZE = 256;
int N_TRIALS = 1000;
int N_RUNS = 10;
char x;
opterr = 0;
while((x = getopt(argc, argv, "g:b:t:r:")) != -1) {
switch(x) {
case 'g': GRID_SIZE = atoi(optarg); break;
case 'b': BLOCK_SIZE = atoi(optarg); break;
case 't': N_TRIALS = atoi(optarg); break;
case 'r': N_RUNS = atoi(optarg); break;
case '?':
if (optopt == 'g' || optopt == 'b' || optopt == 't' || optopt == 'r') {
fprintf (stderr, "Option -%c requires an argument.\n", optopt);
} else {
fprintf (stderr, "Unknown option `-%c'.\n", optopt);
}
abort();
default: abort();
}
}
int N_KERNELS = GRID_SIZE * BLOCK_SIZE;
float* h_pis = (float*) malloc(N_KERNELS*sizeof(float));
float* d_pis;
cudaMalloc(&d_pis, N_KERNELS * sizeof(float));
curandState_t* states;
cudaMalloc(&states, N_KERNELS * sizeof(curandState_t));
time_t start = clock();
initThreads<<<GRID_SIZE, BLOCK_SIZE>>>(d_pis, states);
for(int irun=1; irun <= N_RUNS; irun++) {
pi<<<GRID_SIZE, BLOCK_SIZE>>>(d_pis, states, N_TRIALS);
}
cudaMemcpy(h_pis, d_pis, N_KERNELS*sizeof(float), cudaMemcpyDeviceToHost);
float avg = 0.0;
for(int i=0; i < N_KERNELS; i++) {
avg += h_pis[i] / N_RUNS;
}
avg /= N_KERNELS;
time_t end = clock();
int64_t iters = int64_t(N_KERNELS)*int64_t(N_TRIALS)*int64_t(N_RUNS);
int elapsed = 1000*(end-start)/CLOCKS_PER_SEC;
cout << 4*avg << "\n";
cout << elapsed << "\n";
cout << float(iters)/float(elapsed) << " iters/ms\n";
free(h_pis);
cudaFree(d_pis);
cudaFree(states);
return 0;
} | // pi2.cu
/*
* A simple CUDA-enabled program that approximates \pi using monte-carlo
* sampling. This version generates random numbers on-the-fly within each
* kernel.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdbool.h>
using namespace std;
__global__ void initThreads(float* d_out, hiprandState_t* states) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
hiprand_init(idx, idx, 0, &states[idx]);
d_out[idx] = 0.0;
}
__global__ void pi(float* d_out, hiprandState_t* states, int N_TRIALS) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
hiprandState_t tmp_state = states[idx];
int count = 0;
for(int i=1; i <= N_TRIALS; i++) {
float x = hiprand_uniform(&tmp_state);
float y = hiprand_uniform(&tmp_state);
if( x*x + y*y <= 1.0f ) {
count++;
}
}
states[idx] = tmp_state;
d_out[idx] += float(count)/float(N_TRIALS);
}
int main(int argc, char** argv) {
int GRID_SIZE = 256;
int BLOCK_SIZE = 256;
int N_TRIALS = 1000;
int N_RUNS = 10;
char x;
opterr = 0;
while((x = getopt(argc, argv, "g:b:t:r:")) != -1) {
switch(x) {
case 'g': GRID_SIZE = atoi(optarg); break;
case 'b': BLOCK_SIZE = atoi(optarg); break;
case 't': N_TRIALS = atoi(optarg); break;
case 'r': N_RUNS = atoi(optarg); break;
case '?':
if (optopt == 'g' || optopt == 'b' || optopt == 't' || optopt == 'r') {
fprintf (stderr, "Option -%c requires an argument.\n", optopt);
} else {
fprintf (stderr, "Unknown option `-%c'.\n", optopt);
}
abort();
default: abort();
}
}
int N_KERNELS = GRID_SIZE * BLOCK_SIZE;
float* h_pis = (float*) malloc(N_KERNELS*sizeof(float));
float* d_pis;
hipMalloc(&d_pis, N_KERNELS * sizeof(float));
hiprandState_t* states;
hipMalloc(&states, N_KERNELS * sizeof(hiprandState_t));
time_t start = clock();
initThreads<<<GRID_SIZE, BLOCK_SIZE>>>(d_pis, states);
for(int irun=1; irun <= N_RUNS; irun++) {
pi<<<GRID_SIZE, BLOCK_SIZE>>>(d_pis, states, N_TRIALS);
}
hipMemcpy(h_pis, d_pis, N_KERNELS*sizeof(float), hipMemcpyDeviceToHost);
float avg = 0.0;
for(int i=0; i < N_KERNELS; i++) {
avg += h_pis[i] / N_RUNS;
}
avg /= N_KERNELS;
time_t end = clock();
int64_t iters = int64_t(N_KERNELS)*int64_t(N_TRIALS)*int64_t(N_RUNS);
int elapsed = 1000*(end-start)/CLOCKS_PER_SEC;
cout << 4*avg << "\n";
cout << elapsed << "\n";
cout << float(iters)/float(elapsed) << " iters/ms\n";
free(h_pis);
hipFree(d_pis);
hipFree(states);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // pi2.cu
/*
* A simple CUDA-enabled program that approximates \pi using monte-carlo
* sampling. This version generates random numbers on-the-fly within each
* kernel.
*/
#include <hip/hip_runtime.h>
#include <iostream>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#include <stdlib.h>
#include <unistd.h>
#include <stdbool.h>
using namespace std;
__global__ void initThreads(float* d_out, hiprandState_t* states) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
hiprand_init(idx, idx, 0, &states[idx]);
d_out[idx] = 0.0;
}
__global__ void pi(float* d_out, hiprandState_t* states, int N_TRIALS) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
hiprandState_t tmp_state = states[idx];
int count = 0;
for(int i=1; i <= N_TRIALS; i++) {
float x = hiprand_uniform(&tmp_state);
float y = hiprand_uniform(&tmp_state);
if( x*x + y*y <= 1.0f ) {
count++;
}
}
states[idx] = tmp_state;
d_out[idx] += float(count)/float(N_TRIALS);
}
int main(int argc, char** argv) {
int GRID_SIZE = 256;
int BLOCK_SIZE = 256;
int N_TRIALS = 1000;
int N_RUNS = 10;
char x;
opterr = 0;
while((x = getopt(argc, argv, "g:b:t:r:")) != -1) {
switch(x) {
case 'g': GRID_SIZE = atoi(optarg); break;
case 'b': BLOCK_SIZE = atoi(optarg); break;
case 't': N_TRIALS = atoi(optarg); break;
case 'r': N_RUNS = atoi(optarg); break;
case '?':
if (optopt == 'g' || optopt == 'b' || optopt == 't' || optopt == 'r') {
fprintf (stderr, "Option -%c requires an argument.\n", optopt);
} else {
fprintf (stderr, "Unknown option `-%c'.\n", optopt);
}
abort();
default: abort();
}
}
int N_KERNELS = GRID_SIZE * BLOCK_SIZE;
float* h_pis = (float*) malloc(N_KERNELS*sizeof(float));
float* d_pis;
hipMalloc(&d_pis, N_KERNELS * sizeof(float));
hiprandState_t* states;
hipMalloc(&states, N_KERNELS * sizeof(hiprandState_t));
time_t start = clock();
initThreads<<<GRID_SIZE, BLOCK_SIZE>>>(d_pis, states);
for(int irun=1; irun <= N_RUNS; irun++) {
pi<<<GRID_SIZE, BLOCK_SIZE>>>(d_pis, states, N_TRIALS);
}
hipMemcpy(h_pis, d_pis, N_KERNELS*sizeof(float), hipMemcpyDeviceToHost);
float avg = 0.0;
for(int i=0; i < N_KERNELS; i++) {
avg += h_pis[i] / N_RUNS;
}
avg /= N_KERNELS;
time_t end = clock();
int64_t iters = int64_t(N_KERNELS)*int64_t(N_TRIALS)*int64_t(N_RUNS);
int elapsed = 1000*(end-start)/CLOCKS_PER_SEC;
cout << 4*avg << "\n";
cout << elapsed << "\n";
cout << float(iters)/float(elapsed) << " iters/ms\n";
free(h_pis);
hipFree(d_pis);
hipFree(states);
return 0;
} | .text
.file "pi2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__initThreadsPfP12hiprandState # -- Begin function _Z26__device_stub__initThreadsPfP12hiprandState
.p2align 4, 0x90
.type _Z26__device_stub__initThreadsPfP12hiprandState,@function
_Z26__device_stub__initThreadsPfP12hiprandState: # @_Z26__device_stub__initThreadsPfP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11initThreadsPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__initThreadsPfP12hiprandState, .Lfunc_end0-_Z26__device_stub__initThreadsPfP12hiprandState
.cfi_endproc
# -- End function
.globl _Z17__device_stub__piPfP12hiprandStatei # -- Begin function _Z17__device_stub__piPfP12hiprandStatei
.p2align 4, 0x90
.type _Z17__device_stub__piPfP12hiprandStatei,@function
_Z17__device_stub__piPfP12hiprandStatei: # @_Z17__device_stub__piPfP12hiprandStatei
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2piPfP12hiprandStatei, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z17__device_stub__piPfP12hiprandStatei, .Lfunc_end1-_Z17__device_stub__piPfP12hiprandStatei
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %r13d
movl $0, opterr(%rip)
movl $.L.str, %edx
callq getopt
# kill: def $eax killed $eax def $rax
shll $24, %eax
cmpl $-16777216, %eax # imm = 0xFF000000
jne .LBB2_2
# %bb.1:
movl $256, %ebp # imm = 0x100
movl $1000, %eax # imm = 0x3E8
movq %rax, 16(%rsp) # 8-byte Spill
movl $10, %ebx
movl $256, %r12d # imm = 0x100
.LBB2_16: # %._crit_edge
movl %r12d, %eax
imull %ebp, %eax
movl %eax, 104(%rsp) # 4-byte Spill
movslq %eax, %r14
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movq %r13, 144(%rsp) # 8-byte Spill
movq %r13, %rsi
callq hipMalloc
movq %r14, 160(%rsp) # 8-byte Spill
movq %r14, %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
callq clock
movq %rax, 152(%rsp) # 8-byte Spill
movl %r12d, %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movl %ebp, %ebp
orq %rax, %rbp
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.17:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11initThreadsPfP12hiprandState, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_18:
movq %rbx, 8(%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB2_23
# %bb.19:
leaq 40(%rsp), %r13
leaq 112(%rsp), %rbx
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %r14d
jmp .LBB2_20
.p2align 4, 0x90
.LBB2_22: # in Loop: Header=BB2_20 Depth=1
decl %r14d
je .LBB2_23
.LBB2_20: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_22
# %bb.21: # in Loop: Header=BB2_20 Depth=1
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 108(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 108(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z2piPfP12hiprandStatei, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_22
.LBB2_23: # %._crit_edge99
movq 24(%rsp), %rsi
movq %r15, %rdi
movq 144(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl 104(%rsp), %edx # 4-byte Reload
testl %edx, %edx
jle .LBB2_24
# %bb.26: # %.lr.ph103
movq 8(%rsp), %rbx # 8-byte Reload
cvtsi2ss %ebx, %xmm0
movl %edx, %eax
xorps %xmm2, %xmm2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_27: # =>This Inner Loop Header: Depth=1
movss (%r15,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
addss %xmm1, %xmm2
incq %rcx
cmpq %rcx, %rax
jne .LBB2_27
jmp .LBB2_25
.LBB2_2: # %.lr.ph.preheader
movl $10, %ebx
movl $1000, %ecx # imm = 0x3E8
movq %rcx, 16(%rsp) # 8-byte Spill
movl $256, %r12d # imm = 0x100
movl $256, %ebp # imm = 0x100
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_3 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB2_15: # in Loop: Header=BB2_3 Depth=1
movl $.L.str, %edx
movl %r13d, %edi
movq %r15, %rsi
callq getopt
# kill: def $eax killed $eax def $rax
shll $24, %eax
cmpl $-16777216, %eax # imm = 0xFF000000
je .LBB2_16
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
sarl $24, %eax
leal -98(%rax), %ecx
cmpl $18, %ecx
ja .LBB2_4
# %bb.10: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
jmpq *.LJTI2_0(,%rcx,8)
.LBB2_11: # in Loop: Header=BB2_3 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_3 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_3 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB2_15
.LBB2_24:
xorps %xmm2, %xmm2
movq 8(%rsp), %rbx # 8-byte Reload
.LBB2_25: # %._crit_edge104
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
divss %xmm0, %xmm2
movss %xmm2, 8(%rsp) # 4-byte Spill
callq clock
movslq 16(%rsp), %rcx # 4-byte Folded Reload
movslq %ebx, %r14
imulq %rcx, %r14
imulq 160(%rsp), %r14 # 8-byte Folded Reload
subq 152(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rbx
movq %rdx, %rax
shrq $63, %rax
shrq $7, %rbx
addl %eax, %ebx
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ss %r14, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.4, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4: # %.lr.ph
.cfi_def_cfa_offset 224
cmpl $63, %eax
jne .LBB2_9
# %bb.5:
movl optopt(%rip), %edx
leal -98(%rdx), %eax
cmpl $18, %eax
ja .LBB2_7
# %bb.6:
movl $.L.str.1, %esi
movl $327713, %ecx # imm = 0x50021
btl %eax, %ecx
jae .LBB2_7
.LBB2_8:
movq stderr(%rip), %rdi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
.LBB2_9:
callq abort
.LBB2_7:
movl $.L.str.2, %esi
jmp .LBB2_8
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI2_0:
.quad .LBB2_11
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_14
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_13
.quad .LBB2_9
.quad .LBB2_12
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11initThreadsPfP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2piPfP12hiprandStatei, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11initThreadsPfP12hiprandState,@object # @_Z11initThreadsPfP12hiprandState
.section .rodata,"a",@progbits
.globl _Z11initThreadsPfP12hiprandState
.p2align 3, 0x0
_Z11initThreadsPfP12hiprandState:
.quad _Z26__device_stub__initThreadsPfP12hiprandState
.size _Z11initThreadsPfP12hiprandState, 8
.type _Z2piPfP12hiprandStatei,@object # @_Z2piPfP12hiprandStatei
.globl _Z2piPfP12hiprandStatei
.p2align 3, 0x0
_Z2piPfP12hiprandStatei:
.quad _Z17__device_stub__piPfP12hiprandStatei
.size _Z2piPfP12hiprandStatei, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "g:b:t:r:"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Option -%c requires an argument.\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Unknown option `-%c'.\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " iters/ms\n"
.size .L.str.4, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11initThreadsPfP12hiprandState"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2piPfP12hiprandStatei"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__initThreadsPfP12hiprandState
.addrsig_sym _Z17__device_stub__piPfP12hiprandStatei
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11initThreadsPfP12hiprandState
.addrsig_sym _Z2piPfP12hiprandStatei
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000290ff_00000000-6_pi2.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3899:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3899:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW
.type _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW, @function
_Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW:
.LFB3921:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11initThreadsPfP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3921:
.size _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW, .-_Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW
.globl _Z11initThreadsPfP17curandStateXORWOW
.type _Z11initThreadsPfP17curandStateXORWOW, @function
_Z11initThreadsPfP17curandStateXORWOW:
.LFB3922:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3922:
.size _Z11initThreadsPfP17curandStateXORWOW, .-_Z11initThreadsPfP17curandStateXORWOW
.globl _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi
.type _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi, @function
_Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi:
.LFB3923:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z2piPfP17curandStateXORWOWi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi, .-_Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi
.globl _Z2piPfP17curandStateXORWOWi
.type _Z2piPfP17curandStateXORWOWi, @function
_Z2piPfP17curandStateXORWOWi:
.LFB3924:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3924:
.size _Z2piPfP17curandStateXORWOWi, .-_Z2piPfP17curandStateXORWOWi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Option -%c requires an argument.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Unknown option `-%c'.\n"
.LC3:
.string "g:b:t:r:"
.LC5:
.string "\n"
.LC6:
.string " iters/ms\n"
.text
.globl main
.type main, @function
main:
.LFB3896:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movl %edi, %r13d
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, opterr(%rip)
movl $10, %ebx
movl $1000, 12(%rsp)
movl $256, %ebp
movl $256, %r15d
leaq .LC3(%rip), %r14
jmp .L20
.L44:
cmpb $63, %al
je .L23
cmpb $98, %al
jne .L25
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L20
.L21:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
.L20:
movq %r14, %rdx
movq %r12, %rsi
movl %r13d, %edi
call getopt@PLT
cmpb $-1, %al
je .L43
cmpb $103, %al
je .L21
jle .L44
cmpb $114, %al
je .L26
cmpb $116, %al
jne .L25
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, 12(%rsp)
jmp .L20
.L26:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L20
.L23:
movl optopt(%rip), %ecx
leal -98(%rcx), %eax
cmpl $18, %eax
ja .L29
movl $327713, %edx
btq %rax, %rdx
jnc .L29
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.L30:
call abort@PLT
.L29:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L30
.L25:
call abort@PLT
.L43:
movl %r15d, %r13d
imull %ebp, %r13d
movslq %r13d, %r14
leaq 0(,%r14,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
leaq 32(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq (%r14,%r14,2), %rsi
salq $4, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
call clock@PLT
movq %rax, 24(%rsp)
movl %ebp, %r14d
movl %ebp, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L32:
testl %ebx, %ebx
jle .L33
movl $1, %ebp
jmp .L35
.L45:
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z51__device_stub__Z11initThreadsPfP17curandStateXORWOWPfP17curandStateXORWOW
jmp .L32
.L34:
addl $1, %ebp
cmpl %ebp, %ebx
jl .L33
.L35:
movl %r14d, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %r15d, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L34
movl 12(%rsp), %edx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z42__device_stub__Z2piPfP17curandStateXORWOWiPfP17curandStateXORWOWi
jmp .L34
.L33:
movl $2, %ecx
movq %r12, %rdx
movq 32(%rsp), %rsi
movq 16(%rsp), %r15
movq %r15, %rdi
call cudaMemcpy@PLT
testl %r13d, %r13d
jle .L39
movq %r15, %rax
addq %r15, %r12
pxor %xmm0, %xmm0
pxor %xmm2, %xmm2
cvtsi2ssl %ebx, %xmm2
.L37:
movss (%rax), %xmm1
divss %xmm2, %xmm1
addss %xmm1, %xmm0
addq $4, %rax
cmpq %r12, %rax
jne .L37
.L36:
pxor %xmm1, %xmm1
cvtsi2ssl %r13d, %xmm1
divss %xmm1, %xmm0
movd %xmm0, %ebp
call clock@PLT
movslq %r13d, %r13
movslq 12(%rsp), %rdx
imulq %rdx, %r13
movslq %ebx, %rbx
imulq %rbx, %r13
movq 24(%rsp), %rcx
subq %rcx, %rax
movq %rax, %rcx
movabsq $2361183241434822607, %rdx
imulq %rdx
sarq $7, %rdx
sarq $63, %rcx
movq %rdx, %rbx
subq %rcx, %rbx
movd %ebp, %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC5(%rip), %r14
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl %ebx, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %r14, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %r13, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ebx, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 16(%rsp), %rdi
call free@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pxor %xmm0, %xmm0
jmp .L36
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3896:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z2piPfP17curandStateXORWOWi"
.section .rodata.str1.8
.align 8
.LC8:
.string "_Z11initThreadsPfP17curandStateXORWOW"
.section .rodata.str1.1
.LC9:
.string "precalc_xorwow_matrix"
.LC10:
.string "precalc_xorwow_offset_matrix"
.LC11:
.string "mrg32k3aM1"
.LC12:
.string "mrg32k3aM2"
.LC13:
.string "mrg32k3aM1SubSeq"
.LC14:
.string "mrg32k3aM2SubSeq"
.LC15:
.string "mrg32k3aM1Seq"
.LC16:
.string "mrg32k3aM2Seq"
.LC17:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3926:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z2piPfP17curandStateXORWOWi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z11initThreadsPfP17curandStateXORWOW(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3926:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC4:
.long 1082130432
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "pi2.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__initThreadsPfP12hiprandState # -- Begin function _Z26__device_stub__initThreadsPfP12hiprandState
.p2align 4, 0x90
.type _Z26__device_stub__initThreadsPfP12hiprandState,@function
_Z26__device_stub__initThreadsPfP12hiprandState: # @_Z26__device_stub__initThreadsPfP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11initThreadsPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__initThreadsPfP12hiprandState, .Lfunc_end0-_Z26__device_stub__initThreadsPfP12hiprandState
.cfi_endproc
# -- End function
.globl _Z17__device_stub__piPfP12hiprandStatei # -- Begin function _Z17__device_stub__piPfP12hiprandStatei
.p2align 4, 0x90
.type _Z17__device_stub__piPfP12hiprandStatei,@function
_Z17__device_stub__piPfP12hiprandStatei: # @_Z17__device_stub__piPfP12hiprandStatei
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z2piPfP12hiprandStatei, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z17__device_stub__piPfP12hiprandStatei, .Lfunc_end1-_Z17__device_stub__piPfP12hiprandStatei
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x40800000 # float 4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
movl %edi, %r13d
movl $0, opterr(%rip)
movl $.L.str, %edx
callq getopt
# kill: def $eax killed $eax def $rax
shll $24, %eax
cmpl $-16777216, %eax # imm = 0xFF000000
jne .LBB2_2
# %bb.1:
movl $256, %ebp # imm = 0x100
movl $1000, %eax # imm = 0x3E8
movq %rax, 16(%rsp) # 8-byte Spill
movl $10, %ebx
movl $256, %r12d # imm = 0x100
.LBB2_16: # %._crit_edge
movl %r12d, %eax
imull %ebp, %eax
movl %eax, 104(%rsp) # 4-byte Spill
movslq %eax, %r14
leaq (,%r14,4), %r13
movq %r13, %rdi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movq %r13, 144(%rsp) # 8-byte Spill
movq %r13, %rsi
callq hipMalloc
movq %r14, 160(%rsp) # 8-byte Spill
movq %r14, %rax
shlq $4, %rax
leaq (%rax,%rax,2), %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
callq clock
movq %rax, 152(%rsp) # 8-byte Spill
movl %r12d, %r12d
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movl %ebp, %ebp
orq %rax, %rbp
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_18
# %bb.17:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11initThreadsPfP12hiprandState, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_18:
movq %rbx, 8(%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB2_23
# %bb.19:
leaq 40(%rsp), %r13
leaq 112(%rsp), %rbx
movq 8(%rsp), %rax # 8-byte Reload
movl %eax, %r14d
jmp .LBB2_20
.p2align 4, 0x90
.LBB2_22: # in Loop: Header=BB2_20 Depth=1
decl %r14d
je .LBB2_23
.LBB2_20: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_22
# %bb.21: # in Loop: Header=BB2_20 Depth=1
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movq 16(%rsp), %rax # 8-byte Reload
movl %eax, 108(%rsp)
leaq 96(%rsp), %rax
movq %rax, 112(%rsp)
leaq 88(%rsp), %rax
movq %rax, 120(%rsp)
leaq 108(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
movl $_Z2piPfP12hiprandStatei, %edi
movq %rbx, %r9
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_22
.LBB2_23: # %._crit_edge99
movq 24(%rsp), %rsi
movq %r15, %rdi
movq 144(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movl 104(%rsp), %edx # 4-byte Reload
testl %edx, %edx
jle .LBB2_24
# %bb.26: # %.lr.ph103
movq 8(%rsp), %rbx # 8-byte Reload
cvtsi2ss %ebx, %xmm0
movl %edx, %eax
xorps %xmm2, %xmm2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_27: # =>This Inner Loop Header: Depth=1
movss (%r15,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm0, %xmm1
addss %xmm1, %xmm2
incq %rcx
cmpq %rcx, %rax
jne .LBB2_27
jmp .LBB2_25
.LBB2_2: # %.lr.ph.preheader
movl $10, %ebx
movl $1000, %ecx # imm = 0x3E8
movq %rcx, 16(%rsp) # 8-byte Spill
movl $256, %r12d # imm = 0x100
movl $256, %ebp # imm = 0x100
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_13: # in Loop: Header=BB2_3 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
.LBB2_15: # in Loop: Header=BB2_3 Depth=1
movl $.L.str, %edx
movl %r13d, %edi
movq %r15, %rsi
callq getopt
# kill: def $eax killed $eax def $rax
shll $24, %eax
cmpl $-16777216, %eax # imm = 0xFF000000
je .LBB2_16
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
sarl $24, %eax
leal -98(%rax), %ecx
cmpl $18, %ecx
ja .LBB2_4
# %bb.10: # %.lr.ph
# in Loop: Header=BB2_3 Depth=1
jmpq *.LJTI2_0(,%rcx,8)
.LBB2_11: # in Loop: Header=BB2_3 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_3 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 16(%rsp) # 8-byte Spill
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_3 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB2_15
.LBB2_24:
xorps %xmm2, %xmm2
movq 8(%rsp), %rbx # 8-byte Reload
.LBB2_25: # %._crit_edge104
xorps %xmm0, %xmm0
cvtsi2ss %edx, %xmm0
divss %xmm0, %xmm2
movss %xmm2, 8(%rsp) # 4-byte Spill
callq clock
movslq 16(%rsp), %rcx # 4-byte Folded Reload
movslq %ebx, %r14
imulq %rcx, %r14
imulq 160(%rsp), %r14 # 8-byte Folded Reload
subq 152(%rsp), %rax # 8-byte Folded Reload
movabsq $2361183241434822607, %rcx # imm = 0x20C49BA5E353F7CF
imulq %rcx
movq %rdx, %rbx
movq %rdx, %rax
shrq $63, %rax
shrq $7, %rbx
addl %eax, %ebx
movss 8(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI2_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movl $.L.str.3, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
xorps %xmm0, %xmm0
cvtsi2ss %r14, %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
divss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.4, %esi
movl $10, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_4: # %.lr.ph
.cfi_def_cfa_offset 224
cmpl $63, %eax
jne .LBB2_9
# %bb.5:
movl optopt(%rip), %edx
leal -98(%rdx), %eax
cmpl $18, %eax
ja .LBB2_7
# %bb.6:
movl $.L.str.1, %esi
movl $327713, %ecx # imm = 0x50021
btl %eax, %ecx
jae .LBB2_7
.LBB2_8:
movq stderr(%rip), %rdi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
.LBB2_9:
callq abort
.LBB2_7:
movl $.L.str.2, %esi
jmp .LBB2_8
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI2_0:
.quad .LBB2_11
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_14
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_9
.quad .LBB2_13
.quad .LBB2_9
.quad .LBB2_12
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11initThreadsPfP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2piPfP12hiprandStatei, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11initThreadsPfP12hiprandState,@object # @_Z11initThreadsPfP12hiprandState
.section .rodata,"a",@progbits
.globl _Z11initThreadsPfP12hiprandState
.p2align 3, 0x0
_Z11initThreadsPfP12hiprandState:
.quad _Z26__device_stub__initThreadsPfP12hiprandState
.size _Z11initThreadsPfP12hiprandState, 8
.type _Z2piPfP12hiprandStatei,@object # @_Z2piPfP12hiprandStatei
.globl _Z2piPfP12hiprandStatei
.p2align 3, 0x0
_Z2piPfP12hiprandStatei:
.quad _Z17__device_stub__piPfP12hiprandStatei
.size _Z2piPfP12hiprandStatei, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "g:b:t:r:"
.size .L.str, 9
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Option -%c requires an argument.\n"
.size .L.str.1, 34
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Unknown option `-%c'.\n"
.size .L.str.2, 23
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\n"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " iters/ms\n"
.size .L.str.4, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11initThreadsPfP12hiprandState"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z2piPfP12hiprandStatei"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__initThreadsPfP12hiprandState
.addrsig_sym _Z17__device_stub__piPfP12hiprandStatei
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11initThreadsPfP12hiprandState
.addrsig_sym _Z2piPfP12hiprandStatei
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#include<stdlib.h>
#define CHECK(res) if (res!=cudaSuccess){exit(-1);} //check if success
const int height=10; //the kinds of attributes(>=)
const int width=100; //the kinds of datas(>=)
const int kinds=30; //the kinds of types(>=)
const int bit_size=width*height*sizeof(int ); //the size of bitat[][]
const int index_size=width*sizeof(int );
unsigned int bit[height][width];
unsigned int bitat[width][height]; //add 0-Fill data
int key[height][kinds];
int offset[height][kinds];
int index_bit[width];
int index_long[1];
int attr_size; //the kinds of attributes(=)
int attr_total; //the kinds of datas/31 (=)
unsigned int bin_31=0x80000000;
FILE *fp;
char str[33];
cudaError_t res;
void my_itoa(int num,char *strr,int bin2) //change num(decimal) into strr(binary)
{
int i;
int b=0x00000001;
for(i=31;i>=0;i--)
{
if(num&b)
strr[i]='1';
else
strr[i]='0';
num=num>>1;
}
strr[32]='\0';
}
void get_attr_size() //get attr_size
{
fp=fopen("outputm.txt","r");
char c;
attr_size=0;
while((c=fgetc(fp))!=EOF)
{
if(c=='[')
attr_size++;
}
attr_size=attr_size/2;
fclose(fp);
}
void get_bitmap() //get bitmap,key and offset from file
{
fp=fopen("outputm.txt","r");
int i,j,k,offs;
char init;
i=0;j=0;k=0;
fscanf(fp,"%d",&bit[i][j]);j++;
while((init=fgetc(fp))!=EOF)
{
if(init=='[')
{
fscanf(fp,"%d",&offs);
while(fgetc(fp)!=']')
{
key[i][k]=offs;k++;
fscanf(fp,"%d",&offs);
}
key[i][k]=offs;
while(fgetc(fp)!='[');k=0;
fscanf(fp,"%d",&offs);
while(fgetc(fp)!=']')
{
offset[i][k]=offs;k++;
fscanf(fp,"%d",&offs);
}
offset[i][k]=offs;
i++;j=0;k=0;
}
else{
fscanf(fp,"%d",&bit[i][j]);
j++;
}
}
}
void get_total()
{
int i,tsize,tlie;
attr_total=0;
tsize=key[0][0];
tlie=offset[0][0];
for(i=0;i<tsize;i++)
{
attr_total++;
if(bit[0][tlie+i]<=bin_31)
attr_total=attr_total+bit[0][tlie+i]-1;
}
printf("attr_total:%d\n",attr_total);
}
void get_attr() //get attr from screen,store them in the bitat[][]
{
int i,j,k,attr;
int size[height];
int lie[height];
int local;
index_long[0]=0;
for(i=0;i<attr_total;i++)
{
for(j=0;j<attr_size;j++)
bitat[i][j]=0xffffffff;
}
for(i=0;i<attr_size;i++)
{
printf("Please input the attribute you choose(if not,input -1):\n");
scanf("%d",&attr);
if(attr==-1)
{
size[i]=0;
lie[i]=0;
}
else{
size[i]=key[i][attr]; //find key and offset
lie[i]=offset[i][attr];
}
}
for(i=0;i<attr_size;i++) //store bitmap in the bitat[][]
{
local=-1;
for(j=0;j<size[i];j++)
{
local+=1;
if(bit[i][lie[i]+j]>bin_31) //not 0-Fill
{
bitat[local][i]=bit[i][lie[i]+j];
}
else //0-Fill
{
for(k=0;k<bit[i][lie[i]+j];k++)
{
bitat[local+k][i]=0;
}
local=local+bit[i][lie[i]+j]-1;
}
}
}
}
__device__ void d_itoa(int num,char *strr) //device change num(decimal) into strr(binary)
{
int i;
int b=0x00000001;
for(i=31;i>=0;i--)
{
if(num&b)
strr[i]='1';
else
strr[i]='0';
num=num>>1;
}
strr[32]='\0';
}
__global__ void kernel_index_bitmap(unsigned int **dbit,int *dindex_bit,int *dindex_long,int dtotal,int dsize,int dheight,int dmul)
{
int i,j,k,addr;
char strr[33];
unsigned int num;
int idx=threadIdx.x+blockIdx.x*blockDim.x;
int idy;
int *add=(int *)((int *)dbit); //the address of the bitat[][]
for(i=0;i<dmul;i++)
{
idy=dmul*idx+i;
num=0xffffffff; //num=32 bits of '1'
if(idy<dtotal)
{
for(j=0;j<dsize;j++)
{
num&=add[idy*dheight+j];
printf("(%d,%d):%d\n",idy,idy*dheight+j,add[idy*dheight+j]);
}
printf("num:(%d,%d):%d\n",idx,idy*dheight+j,num);
d_itoa(num,strr);
printf("%d:%s\n",idy,strr);
for(j=1;j<32;j++)
{
if(strr[j]=='1')
{
addr=idy*31+j;
printf("attr:%d\n",addr);
k=atomicAdd(&(dindex_long[0]),1);
dindex_bit[k]=addr;
printf("%d:%d\n",k,dindex_bit[k]);
}
}
}
}
}
void cuda_malloc_cpy()
{
int i,j,mul;
int thread_size=3;
int block_size=1;
mul=(attr_total+(thread_size*block_size-1))/(thread_size*block_size);//distribution of number of tasks
printf("mul:%d\n",mul);
int *dindex_bit;
int *dindex_long;
unsigned int **dbit;
int a[width][height];//test
for(i=0;i<width;i++)
{
for(j=0;j<height;j++)
{
a[i][j]=0;
}
}
res=cudaMalloc((void **)&dindex_bit,index_size);CHECK(res);printf("\n[0] \n");
res=cudaMalloc((void **)&dindex_long,sizeof(int ));CHECK(res);printf("[1] \n");
res=cudaMalloc((void **)&dbit,bit_size);CHECK(res);printf("[2] \n");
res=cudaMemcpy(dbit,bitat,bit_size,cudaMemcpyHostToDevice);CHECK(res);printf("[3] \n");
res=cudaMemcpy(dindex_long,index_long,sizeof(int ),cudaMemcpyHostToDevice);CHECK(res);printf("[4] \n");
dim3 threads(thread_size,1);
dim3 blocks(block_size,1);
kernel_index_bitmap<<<blocks,threads>>>(dbit,dindex_bit,dindex_long,attr_total,attr_size,height,mul);
printf("---------------T_T-------------\n");
res=cudaMemcpy(index_bit,dindex_bit,index_size,cudaMemcpyDeviceToHost);CHECK(res);printf("[5] \n");
res=cudaMemcpy(index_long,dindex_long,sizeof(int ),cudaMemcpyDeviceToHost);CHECK(res);printf("[6] \n");
res=cudaMemcpy(a,dbit,bit_size,cudaMemcpyDeviceToHost);CHECK(res);printf("[7] \n");
printf("long:%d\n",index_long[0]);
for(i=0;i<index_long[0];i++)
printf("%d,",index_bit[i]);
printf("\n");
for(i=0;i<attr_total;i++)
{
for(j=0;j<attr_size;j++)
{
printf("%d,",a[i][j]);
}
printf("\n");
}
cudaFree(dbit);
}
int main()
{
get_attr_size();
get_bitmap();
get_total();
get_attr();
cuda_malloc_cpy();
return 0;
} | .file "tmpxft_0016854f_00000000-6_index2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7my_itoaiPci
.type _Z7my_itoaiPci, @function
_Z7my_itoaiPci:
.LFB2057:
.cfi_startproc
endbr64
leaq 31(%rsi), %rax
jmp .L6
.L4:
movb $48, (%rax)
.L5:
sarl %edi
leaq -1(%rax), %rdx
cmpq %rsi, %rax
je .L8
movq %rdx, %rax
.L6:
testb $1, %dil
je .L4
movb $49, (%rax)
jmp .L5
.L8:
movb $0, 32(%rsi)
ret
.cfi_endproc
.LFE2057:
.size _Z7my_itoaiPci, .-_Z7my_itoaiPci
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "outputm.txt"
.text
.globl _Z13get_attr_sizev
.type _Z13get_attr_sizev, @function
_Z13get_attr_sizev:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, fp(%rip)
movl $0, %eax
.L10:
movl %eax, attr_size(%rip)
.L11:
movq fp(%rip), %rdi
call fgetc@PLT
cmpb $-1, %al
je .L15
cmpb $91, %al
jne .L11
movl attr_size(%rip), %eax
addl $1, %eax
jmp .L10
.L15:
movl attr_size(%rip), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %eax, attr_size(%rip)
movq fp(%rip), %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13get_attr_sizev, .-_Z13get_attr_sizev
.section .rodata.str1.1
.LC2:
.string "%d"
.text
.globl _Z10get_bitmapv
.type _Z10get_bitmapv, @function
_Z10get_bitmapv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movq %rax, fp(%rip)
leaq bit(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $1, %ebx
movl $0, %r13d
leaq bit(%rip), %r15
leaq .LC2(%rip), %rbp
jmp .L17
.L30:
leaq 4(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq %r13d, %rax
movq %rax, %r12
salq $4, %r12
subq %rax, %r12
salq $3, %r12
leaq key(%rip), %rax
leaq (%rax,%r12), %r14
movl $0, %ebx
jmp .L19
.L20:
movl 4(%rsp), %eax
movl %eax, (%r14,%rbx,4)
leaq 4(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
.L19:
movq fp(%rip), %rdi
call fgetc@PLT
cmpl $93, %eax
jne .L20
movslq %ebx, %rbx
movslq %r13d, %rdx
movq %rdx, %rax
salq $4, %rax
subq %rdx, %rax
leaq (%rbx,%rax,2), %rax
movl 4(%rsp), %edx
leaq key(%rip), %rcx
movl %edx, (%rcx,%rax,4)
.L21:
movq fp(%rip), %rdi
call fgetc@PLT
cmpl $91, %eax
jne .L21
leaq 4(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq offset(%rip), %rax
addq %rax, %r12
movl $0, %ebx
jmp .L22
.L23:
movl 4(%rsp), %eax
movl %eax, (%r12,%rbx,4)
leaq 4(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
.L22:
movq fp(%rip), %rdi
call fgetc@PLT
cmpl $93, %eax
jne .L23
movslq %ebx, %rbx
movslq %r13d, %rdx
movq %rdx, %rax
salq $4, %rax
subq %rdx, %rax
leaq (%rbx,%rax,2), %rax
movl 4(%rsp), %edx
leaq offset(%rip), %rcx
movl %edx, (%rcx,%rax,4)
addl $1, %r13d
movl $0, %ebx
.L17:
movq fp(%rip), %rdi
call fgetc@PLT
cmpb $-1, %al
je .L29
cmpb $91, %al
je .L30
movslq %r13d, %rax
leaq (%rax,%rax,4), %rax
leaq (%rax,%rax,4), %rdx
movslq %ebx, %rax
leaq (%rax,%rdx,4), %rax
leaq (%r15,%rax,4), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
jmp .L17
.L29:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10get_bitmapv, .-_Z10get_bitmapv
.section .rodata.str1.1
.LC3:
.string "attr_total:%d\n"
.text
.globl _Z9get_totalv
.type _Z9get_totalv, @function
_Z9get_totalv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, attr_total(%rip)
movl key(%rip), %eax
movl offset(%rip), %ecx
testl %eax, %eax
jle .L33
movl bin_31(%rip), %r8d
movslq %ecx, %rcx
leaq bit(%rip), %rsi
leaq (%rsi,%rcx,4), %rdx
cltq
addq %rcx, %rax
leaq (%rsi,%rax,4), %rdi
movl $0, %eax
.L36:
movl (%rdx), %ecx
leal 1(%rax), %esi
addl %ecx, %eax
cmpl %ecx, %r8d
cmovb %esi, %eax
addq $4, %rdx
cmpq %rdi, %rdx
jne .L36
movl %eax, attr_total(%rip)
.L33:
movl attr_total(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9get_totalv, .-_Z9get_totalv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Please input the attribute you choose(if not,input -1):\n"
.text
.globl _Z8get_attrv
.type _Z8get_attrv, @function
_Z8get_attrv:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, index_long(%rip)
movl attr_total(%rip), %eax
testl %eax, %eax
jle .L40
movl attr_size(%rip), %esi
movslq %esi, %rcx
leaq bitat(%rip), %rdi
leaq (%rdi,%rcx,4), %rdx
cltq
leaq (%rax,%rax,4), %rax
leaq (%rcx,%rax,2), %rax
leaq (%rdi,%rax,4), %rdi
negq %rcx
salq $2, %rcx
jmp .L41
.L42:
movl $-1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L42
.L44:
addq $40, %rdx
cmpq %rdi, %rdx
je .L40
.L41:
leaq (%rdx,%rcx), %rax
testl %esi, %esi
jg .L42
jmp .L44
.L40:
cmpl $0, attr_size(%rip)
jle .L39
movl $0, %ebx
leaq .LC4(%rip), %r13
leaq .LC2(%rip), %rbp
leaq key(%rip), %r15
leaq offset(%rip), %r14
jmp .L48
.L66:
movl $0, 16(%rsp,%rbx,4)
movl $0, %eax
.L47:
movl %eax, 64(%rsp,%rbx,4)
movl attr_size(%rip), %r12d
addq $1, %rbx
cmpl %ebx, %r12d
jle .L65
.L48:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %eax
cmpl $-1, %eax
je .L66
cltq
movslq %ebx, %rcx
movq %rcx, %rdx
salq $4, %rdx
movq %rdx, %rsi
subq %rcx, %rsi
leaq (%rax,%rsi,2), %rsi
movl (%r15,%rsi,4), %esi
movl %esi, 16(%rsp,%rbx,4)
subq %rcx, %rdx
leaq (%rax,%rdx,2), %rax
movl (%r14,%rax,4), %eax
jmp .L47
.L65:
testl %r12d, %r12d
jle .L39
movl bin_31(%rip), %ebx
movslq %r12d, %r12
movl $0, %ebp
movl $0, %r9d
leaq bit(%rip), %r13
movl $-1, %r14d
leaq bitat(%rip), %r8
jmp .L49
.L67:
testl %ecx, %ecx
je .L52
movslq %eax, %rsi
leaq (%rsi,%rsi,4), %rax
leaq (%r9,%rax,2), %rax
leaq (%r8,%rax,4), %rax
movl %ecx, %r15d
addq %r15, %rsi
leaq (%rsi,%rsi,4), %rsi
leaq (%r9,%rsi,2), %rsi
leaq (%r8,%rsi,4), %rsi
.L54:
movl $0, 40(%rax)
addq $40, %rax
cmpq %rsi, %rax
jne .L54
.L52:
leal -1(%rcx,%rdi), %eax
.L53:
addq $4, %rdx
cmpq %r10, %rdx
je .L57
.L55:
leal 1(%rax), %edi
movl (%rdx), %ecx
cmpl %ecx, %ebx
jnb .L67
movslq %edi, %rax
leaq (%rax,%rax,4), %rax
leaq (%r11,%rax,2), %rax
movl %ecx, (%r8,%rax,4)
movl %edi, %eax
jmp .L53
.L57:
addq $1, %r9
addq $100, %rbp
cmpq %r12, %r9
je .L39
.L49:
movl %r9d, %r11d
movl 16(%rsp,%r9,4), %eax
testl %eax, %eax
jle .L57
movslq 64(%rsp,%r9,4), %rcx
leaq (%rcx,%rbp), %rdx
leaq 0(%r13,%rdx,4), %rdx
cltq
addq %rcx, %rax
addq %rbp, %rax
leaq 0(%r13,%rax,4), %r10
movl %r14d, %eax
movslq %r11d, %r11
jmp .L55
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z8get_attrv, .-_Z8get_attrv
.globl _Z6d_itoaiPc
.type _Z6d_itoaiPc, @function
_Z6d_itoaiPc:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z6d_itoaiPc, .-_Z6d_itoaiPc
.globl _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii
.type _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii, @function
_Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii:
.LFB2089:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19kernel_index_bitmapPPjPiS1_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii, .-_Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii
.globl _Z19kernel_index_bitmapPPjPiS1_iiii
.type _Z19kernel_index_bitmapPPjPiS1_iiii, @function
_Z19kernel_index_bitmapPPjPiS1_iiii:
.LFB2090:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z19kernel_index_bitmapPPjPiS1_iiii, .-_Z19kernel_index_bitmapPPjPiS1_iiii
.section .rodata.str1.1
.LC5:
.string "mul:%d\n"
.LC6:
.string "\n[0] \n"
.LC7:
.string "[1] \n"
.LC8:
.string "[2] \n"
.LC9:
.string "[3] \n"
.LC10:
.string "[4] \n"
.section .rodata.str1.8
.align 8
.LC11:
.string "---------------T_T-------------\n"
.section .rodata.str1.1
.LC12:
.string "[5] \n"
.LC13:
.string "[6] \n"
.LC14:
.string "[7] \n"
.LC15:
.string "long:%d\n"
.LC16:
.string "%d,"
.LC17:
.string "\n"
.text
.globl _Z15cuda_malloc_cpyv
.type _Z15cuda_malloc_cpyv, @function
_Z15cuda_malloc_cpyv:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4064, %rsp
.cfi_def_cfa_offset 4112
movq %fs:40, %rax
movq %rax, 4056(%rsp)
xorl %eax, %eax
movl attr_total(%rip), %eax
addl $2, %eax
movslq %eax, %rbx
imulq $1431655766, %rbx, %rbx
shrq $32, %rbx
sarl $31, %eax
subl %eax, %ebx
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rbp
leaq 88(%rsp), %rdx
leaq 4088(%rsp), %rcx
jmp .L80
.L107:
addq $40, %rdx
cmpq %rcx, %rdx
je .L82
.L80:
leaq -40(%rdx), %rax
.L81:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L81
jmp .L107
.L82:
movq %rsp, %rdi
movl $400, %esi
call cudaMalloc@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L108
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L109
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L110
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4000, %edx
leaq bitat(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L111
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4, %edx
leaq index_long(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L112
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L113
.L88:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $400, %edx
movq (%rsp), %rsi
leaq index_bit(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L114
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
leaq index_long(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L115
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L116
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl index_long(%rip), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, index_long(%rip)
jle .L92
movl $0, %ebx
leaq index_bit(%rip), %r13
leaq .LC16(%rip), %r12
.L93:
movl 0(%r13,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, index_long(%rip)
jg .L93
.L92:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC16(%rip), %r12
leaq .LC17(%rip), %r14
cmpl $0, attr_total(%rip)
jg .L94
.L95:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4056(%rsp), %rax
subq %fs:40, %rax
jne .L117
addq $4064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L108:
.cfi_restore_state
movl $-1, %edi
call exit@PLT
.L109:
movl $-1, %edi
call exit@PLT
.L110:
movl $-1, %edi
call exit@PLT
.L111:
movl $-1, %edi
call exit@PLT
.L112:
movl $-1, %edi
call exit@PLT
.L113:
subq $8, %rsp
.cfi_def_cfa_offset 4120
pushq %rbx
.cfi_def_cfa_offset 4128
movl $10, %r9d
movl attr_size(%rip), %r8d
movl attr_total(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii
addq $16, %rsp
.cfi_def_cfa_offset 4112
jmp .L88
.L114:
movl $-1, %edi
call exit@PLT
.L115:
movl $-1, %edi
call exit@PLT
.L116:
movl $-1, %edi
call exit@PLT
.L96:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, attr_size(%rip)
jg .L96
.L97:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq $40, %rbp
cmpl %r13d, attr_total(%rip)
jle .L95
.L94:
movl $0, %ebx
cmpl $0, attr_size(%rip)
jg .L96
jmp .L97
.L117:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z15cuda_malloc_cpyv, .-_Z15cuda_malloc_cpyv
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z13get_attr_sizev
call _Z10get_bitmapv
call _Z9get_totalv
call _Z8get_attrv
call _Z15cuda_malloc_cpyv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC18:
.string "_Z19kernel_index_bitmapPPjPiS1_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z19kernel_index_bitmapPPjPiS1_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl res
.bss
.align 4
.type res, @object
.size res, 4
res:
.zero 4
.globl str
.align 32
.type str, @object
.size str, 33
str:
.zero 33
.globl fp
.align 8
.type fp, @object
.size fp, 8
fp:
.zero 8
.globl bin_31
.data
.align 4
.type bin_31, @object
.size bin_31, 4
bin_31:
.long -2147483648
.globl attr_total
.bss
.align 4
.type attr_total, @object
.size attr_total, 4
attr_total:
.zero 4
.globl attr_size
.align 4
.type attr_size, @object
.size attr_size, 4
attr_size:
.zero 4
.globl index_long
.align 4
.type index_long, @object
.size index_long, 4
index_long:
.zero 4
.globl index_bit
.align 32
.type index_bit, @object
.size index_bit, 400
index_bit:
.zero 400
.globl offset
.align 32
.type offset, @object
.size offset, 1200
offset:
.zero 1200
.globl key
.align 32
.type key, @object
.size key, 1200
key:
.zero 1200
.globl bitat
.align 32
.type bitat, @object
.size bitat, 4000
bitat:
.zero 4000
.globl bit
.align 32
.type bit, @object
.size bit, 4000
bit:
.zero 4000
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#include<stdlib.h>
#define CHECK(res) if (res!=cudaSuccess){exit(-1);} //check if success
const int height=10; //the kinds of attributes(>=)
const int width=100; //the kinds of datas(>=)
const int kinds=30; //the kinds of types(>=)
const int bit_size=width*height*sizeof(int ); //the size of bitat[][]
const int index_size=width*sizeof(int );
unsigned int bit[height][width];
unsigned int bitat[width][height]; //add 0-Fill data
int key[height][kinds];
int offset[height][kinds];
int index_bit[width];
int index_long[1];
int attr_size; //the kinds of attributes(=)
int attr_total; //the kinds of datas/31 (=)
unsigned int bin_31=0x80000000;
FILE *fp;
char str[33];
cudaError_t res;
void my_itoa(int num,char *strr,int bin2) //change num(decimal) into strr(binary)
{
int i;
int b=0x00000001;
for(i=31;i>=0;i--)
{
if(num&b)
strr[i]='1';
else
strr[i]='0';
num=num>>1;
}
strr[32]='\0';
}
void get_attr_size() //get attr_size
{
fp=fopen("outputm.txt","r");
char c;
attr_size=0;
while((c=fgetc(fp))!=EOF)
{
if(c=='[')
attr_size++;
}
attr_size=attr_size/2;
fclose(fp);
}
void get_bitmap() //get bitmap,key and offset from file
{
fp=fopen("outputm.txt","r");
int i,j,k,offs;
char init;
i=0;j=0;k=0;
fscanf(fp,"%d",&bit[i][j]);j++;
while((init=fgetc(fp))!=EOF)
{
if(init=='[')
{
fscanf(fp,"%d",&offs);
while(fgetc(fp)!=']')
{
key[i][k]=offs;k++;
fscanf(fp,"%d",&offs);
}
key[i][k]=offs;
while(fgetc(fp)!='[');k=0;
fscanf(fp,"%d",&offs);
while(fgetc(fp)!=']')
{
offset[i][k]=offs;k++;
fscanf(fp,"%d",&offs);
}
offset[i][k]=offs;
i++;j=0;k=0;
}
else{
fscanf(fp,"%d",&bit[i][j]);
j++;
}
}
}
void get_total()
{
int i,tsize,tlie;
attr_total=0;
tsize=key[0][0];
tlie=offset[0][0];
for(i=0;i<tsize;i++)
{
attr_total++;
if(bit[0][tlie+i]<=bin_31)
attr_total=attr_total+bit[0][tlie+i]-1;
}
printf("attr_total:%d\n",attr_total);
}
void get_attr() //get attr from screen,store them in the bitat[][]
{
int i,j,k,attr;
int size[height];
int lie[height];
int local;
index_long[0]=0;
for(i=0;i<attr_total;i++)
{
for(j=0;j<attr_size;j++)
bitat[i][j]=0xffffffff;
}
for(i=0;i<attr_size;i++)
{
printf("Please input the attribute you choose(if not,input -1):\n");
scanf("%d",&attr);
if(attr==-1)
{
size[i]=0;
lie[i]=0;
}
else{
size[i]=key[i][attr]; //find key and offset
lie[i]=offset[i][attr];
}
}
for(i=0;i<attr_size;i++) //store bitmap in the bitat[][]
{
local=-1;
for(j=0;j<size[i];j++)
{
local+=1;
if(bit[i][lie[i]+j]>bin_31) //not 0-Fill
{
bitat[local][i]=bit[i][lie[i]+j];
}
else //0-Fill
{
for(k=0;k<bit[i][lie[i]+j];k++)
{
bitat[local+k][i]=0;
}
local=local+bit[i][lie[i]+j]-1;
}
}
}
}
__device__ void d_itoa(int num,char *strr) //device change num(decimal) into strr(binary)
{
int i;
int b=0x00000001;
for(i=31;i>=0;i--)
{
if(num&b)
strr[i]='1';
else
strr[i]='0';
num=num>>1;
}
strr[32]='\0';
}
__global__ void kernel_index_bitmap(unsigned int **dbit,int *dindex_bit,int *dindex_long,int dtotal,int dsize,int dheight,int dmul)
{
int i,j,k,addr;
char strr[33];
unsigned int num;
int idx=threadIdx.x+blockIdx.x*blockDim.x;
int idy;
int *add=(int *)((int *)dbit); //the address of the bitat[][]
for(i=0;i<dmul;i++)
{
idy=dmul*idx+i;
num=0xffffffff; //num=32 bits of '1'
if(idy<dtotal)
{
for(j=0;j<dsize;j++)
{
num&=add[idy*dheight+j];
printf("(%d,%d):%d\n",idy,idy*dheight+j,add[idy*dheight+j]);
}
printf("num:(%d,%d):%d\n",idx,idy*dheight+j,num);
d_itoa(num,strr);
printf("%d:%s\n",idy,strr);
for(j=1;j<32;j++)
{
if(strr[j]=='1')
{
addr=idy*31+j;
printf("attr:%d\n",addr);
k=atomicAdd(&(dindex_long[0]),1);
dindex_bit[k]=addr;
printf("%d:%d\n",k,dindex_bit[k]);
}
}
}
}
}
void cuda_malloc_cpy()
{
int i,j,mul;
int thread_size=3;
int block_size=1;
mul=(attr_total+(thread_size*block_size-1))/(thread_size*block_size);//distribution of number of tasks
printf("mul:%d\n",mul);
int *dindex_bit;
int *dindex_long;
unsigned int **dbit;
int a[width][height];//test
for(i=0;i<width;i++)
{
for(j=0;j<height;j++)
{
a[i][j]=0;
}
}
res=cudaMalloc((void **)&dindex_bit,index_size);CHECK(res);printf("\n[0] \n");
res=cudaMalloc((void **)&dindex_long,sizeof(int ));CHECK(res);printf("[1] \n");
res=cudaMalloc((void **)&dbit,bit_size);CHECK(res);printf("[2] \n");
res=cudaMemcpy(dbit,bitat,bit_size,cudaMemcpyHostToDevice);CHECK(res);printf("[3] \n");
res=cudaMemcpy(dindex_long,index_long,sizeof(int ),cudaMemcpyHostToDevice);CHECK(res);printf("[4] \n");
dim3 threads(thread_size,1);
dim3 blocks(block_size,1);
kernel_index_bitmap<<<blocks,threads>>>(dbit,dindex_bit,dindex_long,attr_total,attr_size,height,mul);
printf("---------------T_T-------------\n");
res=cudaMemcpy(index_bit,dindex_bit,index_size,cudaMemcpyDeviceToHost);CHECK(res);printf("[5] \n");
res=cudaMemcpy(index_long,dindex_long,sizeof(int ),cudaMemcpyDeviceToHost);CHECK(res);printf("[6] \n");
res=cudaMemcpy(a,dbit,bit_size,cudaMemcpyDeviceToHost);CHECK(res);printf("[7] \n");
printf("long:%d\n",index_long[0]);
for(i=0;i<index_long[0];i++)
printf("%d,",index_bit[i]);
printf("\n");
for(i=0;i<attr_total;i++)
{
for(j=0;j<attr_size;j++)
{
printf("%d,",a[i][j]);
}
printf("\n");
}
cudaFree(dbit);
}
int main()
{
get_attr_size();
get_bitmap();
get_total();
get_attr();
cuda_malloc_cpy();
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<stdlib.h>
#define CHECK(res) if (res!=hipSuccess){exit(-1);} //check if success
const int height=10; //the kinds of attributes(>=)
const int width=100; //the kinds of datas(>=)
const int kinds=30; //the kinds of types(>=)
const int bit_size=width*height*sizeof(int ); //the size of bitat[][]
const int index_size=width*sizeof(int );
unsigned int bit[height][width];
unsigned int bitat[width][height]; //add 0-Fill data
int key[height][kinds];
int offset[height][kinds];
int index_bit[width];
int index_long[1];
int attr_size; //the kinds of attributes(=)
int attr_total; //the kinds of datas/31 (=)
unsigned int bin_31=0x80000000;
FILE *fp;
char str[33];
hipError_t res;
void my_itoa(int num,char *strr,int bin2) //change num(decimal) into strr(binary)
{
int i;
int b=0x00000001;
for(i=31;i>=0;i--)
{
if(num&b)
strr[i]='1';
else
strr[i]='0';
num=num>>1;
}
strr[32]='\0';
}
void get_attr_size() //get attr_size
{
fp=fopen("outputm.txt","r");
char c;
attr_size=0;
while((c=fgetc(fp))!=EOF)
{
if(c=='[')
attr_size++;
}
attr_size=attr_size/2;
fclose(fp);
}
void get_bitmap() //get bitmap,key and offset from file
{
fp=fopen("outputm.txt","r");
int i,j,k,offs;
char init;
i=0;j=0;k=0;
fscanf(fp,"%d",&bit[i][j]);j++;
while((init=fgetc(fp))!=EOF)
{
if(init=='[')
{
fscanf(fp,"%d",&offs);
while(fgetc(fp)!=']')
{
key[i][k]=offs;k++;
fscanf(fp,"%d",&offs);
}
key[i][k]=offs;
while(fgetc(fp)!='[');k=0;
fscanf(fp,"%d",&offs);
while(fgetc(fp)!=']')
{
offset[i][k]=offs;k++;
fscanf(fp,"%d",&offs);
}
offset[i][k]=offs;
i++;j=0;k=0;
}
else{
fscanf(fp,"%d",&bit[i][j]);
j++;
}
}
}
void get_total()
{
int i,tsize,tlie;
attr_total=0;
tsize=key[0][0];
tlie=offset[0][0];
for(i=0;i<tsize;i++)
{
attr_total++;
if(bit[0][tlie+i]<=bin_31)
attr_total=attr_total+bit[0][tlie+i]-1;
}
printf("attr_total:%d\n",attr_total);
}
void get_attr() //get attr from screen,store them in the bitat[][]
{
int i,j,k,attr;
int size[height];
int lie[height];
int local;
index_long[0]=0;
for(i=0;i<attr_total;i++)
{
for(j=0;j<attr_size;j++)
bitat[i][j]=0xffffffff;
}
for(i=0;i<attr_size;i++)
{
printf("Please input the attribute you choose(if not,input -1):\n");
scanf("%d",&attr);
if(attr==-1)
{
size[i]=0;
lie[i]=0;
}
else{
size[i]=key[i][attr]; //find key and offset
lie[i]=offset[i][attr];
}
}
for(i=0;i<attr_size;i++) //store bitmap in the bitat[][]
{
local=-1;
for(j=0;j<size[i];j++)
{
local+=1;
if(bit[i][lie[i]+j]>bin_31) //not 0-Fill
{
bitat[local][i]=bit[i][lie[i]+j];
}
else //0-Fill
{
for(k=0;k<bit[i][lie[i]+j];k++)
{
bitat[local+k][i]=0;
}
local=local+bit[i][lie[i]+j]-1;
}
}
}
}
__device__ void d_itoa(int num,char *strr) //device change num(decimal) into strr(binary)
{
int i;
int b=0x00000001;
for(i=31;i>=0;i--)
{
if(num&b)
strr[i]='1';
else
strr[i]='0';
num=num>>1;
}
strr[32]='\0';
}
__global__ void kernel_index_bitmap(unsigned int **dbit,int *dindex_bit,int *dindex_long,int dtotal,int dsize,int dheight,int dmul)
{
int i,j,k,addr;
char strr[33];
unsigned int num;
int idx=threadIdx.x+blockIdx.x*blockDim.x;
int idy;
int *add=(int *)((int *)dbit); //the address of the bitat[][]
for(i=0;i<dmul;i++)
{
idy=dmul*idx+i;
num=0xffffffff; //num=32 bits of '1'
if(idy<dtotal)
{
for(j=0;j<dsize;j++)
{
num&=add[idy*dheight+j];
printf("(%d,%d):%d\n",idy,idy*dheight+j,add[idy*dheight+j]);
}
printf("num:(%d,%d):%d\n",idx,idy*dheight+j,num);
d_itoa(num,strr);
printf("%d:%s\n",idy,strr);
for(j=1;j<32;j++)
{
if(strr[j]=='1')
{
addr=idy*31+j;
printf("attr:%d\n",addr);
k=atomicAdd(&(dindex_long[0]),1);
dindex_bit[k]=addr;
printf("%d:%d\n",k,dindex_bit[k]);
}
}
}
}
}
void cuda_malloc_cpy()
{
int i,j,mul;
int thread_size=3;
int block_size=1;
mul=(attr_total+(thread_size*block_size-1))/(thread_size*block_size);//distribution of number of tasks
printf("mul:%d\n",mul);
int *dindex_bit;
int *dindex_long;
unsigned int **dbit;
int a[width][height];//test
for(i=0;i<width;i++)
{
for(j=0;j<height;j++)
{
a[i][j]=0;
}
}
res=hipMalloc((void **)&dindex_bit,index_size);CHECK(res);printf("\n[0] \n");
res=hipMalloc((void **)&dindex_long,sizeof(int ));CHECK(res);printf("[1] \n");
res=hipMalloc((void **)&dbit,bit_size);CHECK(res);printf("[2] \n");
res=hipMemcpy(dbit,bitat,bit_size,hipMemcpyHostToDevice);CHECK(res);printf("[3] \n");
res=hipMemcpy(dindex_long,index_long,sizeof(int ),hipMemcpyHostToDevice);CHECK(res);printf("[4] \n");
dim3 threads(thread_size,1);
dim3 blocks(block_size,1);
kernel_index_bitmap<<<blocks,threads>>>(dbit,dindex_bit,dindex_long,attr_total,attr_size,height,mul);
printf("---------------T_T-------------\n");
res=hipMemcpy(index_bit,dindex_bit,index_size,hipMemcpyDeviceToHost);CHECK(res);printf("[5] \n");
res=hipMemcpy(index_long,dindex_long,sizeof(int ),hipMemcpyDeviceToHost);CHECK(res);printf("[6] \n");
res=hipMemcpy(a,dbit,bit_size,hipMemcpyDeviceToHost);CHECK(res);printf("[7] \n");
printf("long:%d\n",index_long[0]);
for(i=0;i<index_long[0];i++)
printf("%d,",index_bit[i]);
printf("\n");
for(i=0;i<attr_total;i++)
{
for(j=0;j<attr_size;j++)
{
printf("%d,",a[i][j]);
}
printf("\n");
}
hipFree(dbit);
}
int main()
{
get_attr_size();
get_bitmap();
get_total();
get_attr();
cuda_malloc_cpy();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#include<stdlib.h>
#define CHECK(res) if (res!=hipSuccess){exit(-1);} //check if success
const int height=10; //the kinds of attributes(>=)
const int width=100; //the kinds of datas(>=)
const int kinds=30; //the kinds of types(>=)
const int bit_size=width*height*sizeof(int ); //the size of bitat[][]
const int index_size=width*sizeof(int );
unsigned int bit[height][width];
unsigned int bitat[width][height]; //add 0-Fill data
int key[height][kinds];
int offset[height][kinds];
int index_bit[width];
int index_long[1];
int attr_size; //the kinds of attributes(=)
int attr_total; //the kinds of datas/31 (=)
unsigned int bin_31=0x80000000;
FILE *fp;
char str[33];
hipError_t res;
void my_itoa(int num,char *strr,int bin2) //change num(decimal) into strr(binary)
{
int i;
int b=0x00000001;
for(i=31;i>=0;i--)
{
if(num&b)
strr[i]='1';
else
strr[i]='0';
num=num>>1;
}
strr[32]='\0';
}
void get_attr_size() //get attr_size
{
fp=fopen("outputm.txt","r");
char c;
attr_size=0;
while((c=fgetc(fp))!=EOF)
{
if(c=='[')
attr_size++;
}
attr_size=attr_size/2;
fclose(fp);
}
void get_bitmap() //get bitmap,key and offset from file
{
fp=fopen("outputm.txt","r");
int i,j,k,offs;
char init;
i=0;j=0;k=0;
fscanf(fp,"%d",&bit[i][j]);j++;
while((init=fgetc(fp))!=EOF)
{
if(init=='[')
{
fscanf(fp,"%d",&offs);
while(fgetc(fp)!=']')
{
key[i][k]=offs;k++;
fscanf(fp,"%d",&offs);
}
key[i][k]=offs;
while(fgetc(fp)!='[');k=0;
fscanf(fp,"%d",&offs);
while(fgetc(fp)!=']')
{
offset[i][k]=offs;k++;
fscanf(fp,"%d",&offs);
}
offset[i][k]=offs;
i++;j=0;k=0;
}
else{
fscanf(fp,"%d",&bit[i][j]);
j++;
}
}
}
void get_total()
{
int i,tsize,tlie;
attr_total=0;
tsize=key[0][0];
tlie=offset[0][0];
for(i=0;i<tsize;i++)
{
attr_total++;
if(bit[0][tlie+i]<=bin_31)
attr_total=attr_total+bit[0][tlie+i]-1;
}
printf("attr_total:%d\n",attr_total);
}
void get_attr() //get attr from screen,store them in the bitat[][]
{
int i,j,k,attr;
int size[height];
int lie[height];
int local;
index_long[0]=0;
for(i=0;i<attr_total;i++)
{
for(j=0;j<attr_size;j++)
bitat[i][j]=0xffffffff;
}
for(i=0;i<attr_size;i++)
{
printf("Please input the attribute you choose(if not,input -1):\n");
scanf("%d",&attr);
if(attr==-1)
{
size[i]=0;
lie[i]=0;
}
else{
size[i]=key[i][attr]; //find key and offset
lie[i]=offset[i][attr];
}
}
for(i=0;i<attr_size;i++) //store bitmap in the bitat[][]
{
local=-1;
for(j=0;j<size[i];j++)
{
local+=1;
if(bit[i][lie[i]+j]>bin_31) //not 0-Fill
{
bitat[local][i]=bit[i][lie[i]+j];
}
else //0-Fill
{
for(k=0;k<bit[i][lie[i]+j];k++)
{
bitat[local+k][i]=0;
}
local=local+bit[i][lie[i]+j]-1;
}
}
}
}
__device__ void d_itoa(int num,char *strr) //device change num(decimal) into strr(binary)
{
int i;
int b=0x00000001;
for(i=31;i>=0;i--)
{
if(num&b)
strr[i]='1';
else
strr[i]='0';
num=num>>1;
}
strr[32]='\0';
}
__global__ void kernel_index_bitmap(unsigned int **dbit,int *dindex_bit,int *dindex_long,int dtotal,int dsize,int dheight,int dmul)
{
int i,j,k,addr;
char strr[33];
unsigned int num;
int idx=threadIdx.x+blockIdx.x*blockDim.x;
int idy;
int *add=(int *)((int *)dbit); //the address of the bitat[][]
for(i=0;i<dmul;i++)
{
idy=dmul*idx+i;
num=0xffffffff; //num=32 bits of '1'
if(idy<dtotal)
{
for(j=0;j<dsize;j++)
{
num&=add[idy*dheight+j];
printf("(%d,%d):%d\n",idy,idy*dheight+j,add[idy*dheight+j]);
}
printf("num:(%d,%d):%d\n",idx,idy*dheight+j,num);
d_itoa(num,strr);
printf("%d:%s\n",idy,strr);
for(j=1;j<32;j++)
{
if(strr[j]=='1')
{
addr=idy*31+j;
printf("attr:%d\n",addr);
k=atomicAdd(&(dindex_long[0]),1);
dindex_bit[k]=addr;
printf("%d:%d\n",k,dindex_bit[k]);
}
}
}
}
}
void cuda_malloc_cpy()
{
int i,j,mul;
int thread_size=3;
int block_size=1;
mul=(attr_total+(thread_size*block_size-1))/(thread_size*block_size);//distribution of number of tasks
printf("mul:%d\n",mul);
int *dindex_bit;
int *dindex_long;
unsigned int **dbit;
int a[width][height];//test
for(i=0;i<width;i++)
{
for(j=0;j<height;j++)
{
a[i][j]=0;
}
}
res=hipMalloc((void **)&dindex_bit,index_size);CHECK(res);printf("\n[0] \n");
res=hipMalloc((void **)&dindex_long,sizeof(int ));CHECK(res);printf("[1] \n");
res=hipMalloc((void **)&dbit,bit_size);CHECK(res);printf("[2] \n");
res=hipMemcpy(dbit,bitat,bit_size,hipMemcpyHostToDevice);CHECK(res);printf("[3] \n");
res=hipMemcpy(dindex_long,index_long,sizeof(int ),hipMemcpyHostToDevice);CHECK(res);printf("[4] \n");
dim3 threads(thread_size,1);
dim3 blocks(block_size,1);
kernel_index_bitmap<<<blocks,threads>>>(dbit,dindex_bit,dindex_long,attr_total,attr_size,height,mul);
printf("---------------T_T-------------\n");
res=hipMemcpy(index_bit,dindex_bit,index_size,hipMemcpyDeviceToHost);CHECK(res);printf("[5] \n");
res=hipMemcpy(index_long,dindex_long,sizeof(int ),hipMemcpyDeviceToHost);CHECK(res);printf("[6] \n");
res=hipMemcpy(a,dbit,bit_size,hipMemcpyDeviceToHost);CHECK(res);printf("[7] \n");
printf("long:%d\n",index_long[0]);
for(i=0;i<index_long[0];i++)
printf("%d,",index_bit[i]);
printf("\n");
for(i=0;i<attr_total;i++)
{
for(j=0;j<attr_size;j++)
{
printf("%d,",a[i][j]);
}
printf("\n");
}
hipFree(dbit);
}
int main()
{
get_attr_size();
get_bitmap();
get_total();
get_attr();
cuda_malloc_cpy();
return 0;
} | .text
.file "index2.hip"
.globl _Z7my_itoaiPci # -- Begin function _Z7my_itoaiPci
.p2align 4, 0x90
.type _Z7my_itoaiPci,@function
_Z7my_itoaiPci: # @_Z7my_itoaiPci
.cfi_startproc
# %bb.0:
movl $32, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %edi, %ecx
andb $1, %cl
orb $48, %cl
movb %cl, -1(%rsi,%rax)
sarl %edi
decq %rax
jne .LBB0_1
# %bb.2:
movb $0, 32(%rsi)
retq
.Lfunc_end0:
.size _Z7my_itoaiPci, .Lfunc_end0-_Z7my_itoaiPci
.cfi_endproc
# -- End function
.globl _Z13get_attr_sizev # -- Begin function _Z13get_attr_sizev
.p2align 4, 0x90
.type _Z13get_attr_sizev,@function
_Z13get_attr_sizev: # @_Z13get_attr_sizev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, fp(%rip)
xorl %eax, %eax
.LBB1_1: # %.sink.split
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl %eax, attr_size(%rip)
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movq fp(%rip), %rdi
callq fgetc
cmpb $-1, %al
je .LBB1_5
# %bb.3: # in Loop: Header=BB1_2 Depth=2
movzbl %al, %eax
cmpl $91, %eax
jne .LBB1_2
# %bb.4: # in Loop: Header=BB1_1 Depth=1
movl attr_size(%rip), %eax
incl %eax
jmp .LBB1_1
.LBB1_5:
movl attr_size(%rip), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movl %ecx, attr_size(%rip)
movq fp(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z13get_attr_sizev, .Lfunc_end1-_Z13get_attr_sizev
.cfi_endproc
# -- End function
.globl _Z10get_bitmapv # -- Begin function _Z10get_bitmapv
.p2align 4, 0x90
.type _Z10get_bitmapv,@function
_Z10get_bitmapv: # @_Z10get_bitmapv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, fp(%rip)
movl $bit, %r15d
movl $.L.str.2, %esi
movl $bit, %edx
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl $1, %eax
movl $key, %r12d
movl $offset, %r13d
leaq 12(%rsp), %rbx
xorl %ebp, %ebp
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_12: # %._crit_edge32
# in Loop: Header=BB2_1 Depth=1
movl 12(%rsp), %eax
movl %ebp, %ecx
movl %eax, offset(%r14,%rcx,4)
movl %r15d, %ebp
incl %ebp
movq 16(%rsp), %r15 # 8-byte Reload
addq $400, %r15 # imm = 0x190
addq $120, %r12
addq $120, %r13
xorl %eax, %eax
.LBB2_1: # %.outer
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_5 Depth 2
# Child Loop BB2_8 Depth 2
# Child Loop BB2_10 Depth 2
movl %eax, %eax
leaq (%r15,%rax,4), %r14
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq fp(%rip), %rdi
callq fgetc
cmpb $-1, %al
je .LBB2_14
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movzbl %al, %eax
cmpl $91, %eax
je .LBB2_4
# %bb.13: # in Loop: Header=BB2_2 Depth=2
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r14
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
callq fgetc
xorl %r14d, %r14d
cmpl $93, %eax
je .LBB2_7
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 12(%rsp), %eax
movl %eax, (%r12,%r14,4)
incq %r14
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
callq fgetc
cmpl $93, %eax
jne .LBB2_5
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
movq %r15, 16(%rsp) # 8-byte Spill
movl 12(%rsp), %eax
movl %ebp, %ecx
movl %r14d, %edx
imulq $120, %rcx, %r14
movl %eax, key(%r14,%rdx,4)
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq fp(%rip), %rdi
callq fgetc
cmpl $91, %eax
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_1 Depth=1
movl %ebp, %r15d
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
callq fgetc
xorl %ebp, %ebp
cmpl $93, %eax
je .LBB2_12
.p2align 4, 0x90
.LBB2_10: # %.lr.ph31
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 12(%rsp), %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
callq fgetc
cmpl $93, %eax
jne .LBB2_10
jmp .LBB2_12
.LBB2_14:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10get_bitmapv, .Lfunc_end2-_Z10get_bitmapv
.cfi_endproc
# -- End function
.globl _Z9get_totalv # -- Begin function _Z9get_totalv
.p2align 4, 0x90
.type _Z9get_totalv,@function
_Z9get_totalv: # @_Z9get_totalv
.cfi_startproc
# %bb.0:
movl $0, attr_total(%rip)
movl key(%rip), %eax
testl %eax, %eax
jle .LBB3_4
# %bb.1: # %.lr.ph
movslq offset(%rip), %rdx
movl attr_total(%rip), %ecx
movl bin_31(%rip), %esi
xorl %edi, %edi
shlq $2, %rdx
movl $1, %r8d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movl bit(%rdx,%rdi,4), %r9d
cmpl %esi, %r9d
cmoval %r8d, %r9d
addl %r9d, %ecx
incq %rdi
cmpq %rdi, %rax
jne .LBB3_2
# %bb.3: # %._crit_edge
movl %ecx, attr_total(%rip)
.LBB3_4:
movl attr_total(%rip), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z9get_totalv, .Lfunc_end3-_Z9get_totalv
.cfi_endproc
# -- End function
.globl _Z8get_attrv # -- Begin function _Z8get_attrv
.p2align 4, 0x90
.type _Z8get_attrv,@function
_Z8get_attrv: # @_Z8get_attrv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, index_long(%rip)
movl attr_total(%rip), %eax
testl %eax, %eax
jle .LBB4_5
# %bb.1: # %.preheader51.lr.ph
movl attr_size(%rip), %r14d
movq %r14, %rbx
shlq $2, %rbx
shlq $3, %rax
leaq (%rax,%rax,4), %r15
xorl %r12d, %r12d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
addq $40, %r12
cmpq %r12, %r15
je .LBB4_5
.LBB4_2: # %.preheader51
# =>This Inner Loop Header: Depth=1
testl %r14d, %r14d
jle .LBB4_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
leaq bitat(%r12), %rdi
movl $255, %esi
movq %rbx, %rdx
callq memset@PLT
jmp .LBB4_4
.LBB4_5: # %.preheader50
movl attr_size(%rip), %ecx
testl %ecx, %ecx
jle .LBB4_9
# %bb.6: # %.lr.ph55.preheader
leaq 12(%rsp), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_18: # in Loop: Header=BB4_7 Depth=1
movl key(%r14,%rax,4), %ecx
movl %ecx, 16(%rsp,%r15,4)
movl offset(%r14,%rax,4), %eax
.LBB4_19: # in Loop: Header=BB4_7 Depth=1
movl %eax, 64(%rsp,%r15,4)
incq %r15
movslq attr_size(%rip), %rcx
addq $120, %r14
cmpq %rcx, %r15
jge .LBB4_9
.LBB4_7: # %.lr.ph55
# =>This Inner Loop Header: Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rax
cmpq $-1, %rax
jne .LBB4_18
# %bb.8: # in Loop: Header=BB4_7 Depth=1
movl $0, 16(%rsp,%r15,4)
xorl %eax, %eax
jmp .LBB4_19
.LBB4_9: # %.preheader49
testl %ecx, %ecx
jle .LBB4_23
# %bb.10: # %.preheader48.lr.ph
movl bin_31(%rip), %eax
movl %ecx, %ecx
movl $bitat, %edx
xorl %esi, %esi
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_22: # %._crit_edge62
# in Loop: Header=BB4_11 Depth=1
incq %rsi
addq $4, %rdx
cmpq %rcx, %rsi
je .LBB4_23
.LBB4_11: # %.preheader48
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
# Child Loop BB4_16 Depth 3
movl 16(%rsp,%rsi,4), %edi
testl %edi, %edi
jle .LBB4_22
# %bb.12: # %.lr.ph61
# in Loop: Header=BB4_11 Depth=1
movslq 64(%rsp,%rsi,4), %r8
movl $-1, %ebx
imulq $400, %rsi, %r9 # imm = 0x190
leaq (,%rsi,4), %r10
xorl %r11d, %r11d
jmp .LBB4_13
.p2align 4, 0x90
.LBB4_20: # in Loop: Header=BB4_13 Depth=2
movslq %ebp, %rbx
leaq (%rbx,%rbx,4), %rbx
movl %r14d, bitat(%r10,%rbx,8)
.LBB4_21: # in Loop: Header=BB4_13 Depth=2
incq %r11
movl %ebp, %ebx
cmpq %rdi, %r11
je .LBB4_22
.LBB4_13: # Parent Loop BB4_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_16 Depth 3
leal 1(%rbx), %ebp
leaq (%r11,%r8), %r14
movl bit(%r9,%r14,4), %r14d
cmpl %eax, %r14d
ja .LBB4_20
# %bb.14: # %.preheader
# in Loop: Header=BB4_13 Depth=2
testl %r14d, %r14d
je .LBB4_17
# %bb.15: # %.lr.ph57.preheader
# in Loop: Header=BB4_13 Depth=2
movslq %ebp, %r15
leaq (%r15,%r15,4), %r15
leaq (%rdx,%r15,8), %r15
leaq (,%r14,8), %r12
leaq (%r12,%r12,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_16: # %.lr.ph57
# Parent Loop BB4_11 Depth=1
# Parent Loop BB4_13 Depth=2
# => This Inner Loop Header: Depth=3
movl $0, (%r15,%r13)
addq $40, %r13
cmpq %r13, %r12
jne .LBB4_16
.LBB4_17: # %._crit_edge58
# in Loop: Header=BB4_13 Depth=2
addl %ebx, %r14d
movl %r14d, %ebp
jmp .LBB4_21
.LBB4_23: # %._crit_edge64
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8get_attrv, .Lfunc_end4-_Z8get_attrv
.cfi_endproc
# -- End function
.globl _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii # -- Begin function _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.p2align 4, 0x90
.type _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii,@function
_Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii: # @_Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19kernel_index_bitmapPPjPiS1_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii, .Lfunc_end5-_Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.cfi_endproc
# -- End function
.globl _Z15cuda_malloc_cpyv # -- Begin function _Z15cuda_malloc_cpyv
.p2align 4, 0x90
.type _Z15cuda_malloc_cpyv,@function
_Z15cuda_malloc_cpyv: # @_Z15cuda_malloc_cpyv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $4176, %rsp # imm = 0x1050
.cfi_def_cfa_offset 4208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl attr_total(%rip), %eax
addl $2, %eax
cltq
imulq $1431655766, %rax, %rbx # imm = 0x55555556
movq %rbx, %rax
shrq $63, %rax
shrq $32, %rbx
addl %eax, %ebx
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 176(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
xorl %esi, %esi
callq memset@PLT
leaq 32(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.1:
movl $.Lstr.2, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.2:
movl $.Lstr.3, %edi
callq puts@PLT
movq %rsp, %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.3:
movl $.Lstr.4, %edi
callq puts@PLT
movq (%rsp), %rdi
movl $bitat, %esi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.4:
movl $.Lstr.5, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $index_long, %esi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.5:
movl $.Lstr.6, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_7
# %bb.6:
movq (%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movl attr_total(%rip), %esi
movl attr_size(%rip), %edi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 28(%rsp)
movl %edi, 24(%rsp)
movl $10, 20(%rsp)
movl %ebx, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z19kernel_index_bitmapPPjPiS1_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_7:
movl $.Lstr.7, %edi
callq puts@PLT
movq 32(%rsp), %rsi
movl $index_bit, %edi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.8:
movl $.Lstr.8, %edi
callq puts@PLT
movq 8(%rsp), %rsi
movl $index_long, %edi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.9:
movl $.Lstr.9, %edi
callq puts@PLT
movq (%rsp), %rsi
leaq 176(%rsp), %rbx
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.10:
movl $.Lstr.10, %edi
callq puts@PLT
movl index_long(%rip), %esi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
cmpl $0, index_long(%rip)
jle .LBB6_13
# %bb.11: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_12: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl index_bit(,%r14,4), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
incq %r14
movslq index_long(%rip), %rax
cmpq %rax, %r14
jl .LBB6_12
.LBB6_13: # %._crit_edge
movl $10, %edi
callq putchar@PLT
cmpl $0, attr_total(%rip)
jle .LBB6_19
# %bb.14: # %.preheader.preheader
xorl %r14d, %r14d
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_18: # %._crit_edge56
# in Loop: Header=BB6_15 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
movslq attr_total(%rip), %rax
addq $40, %rbx
cmpq %rax, %r14
jge .LBB6_19
.LBB6_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_17 Depth 2
cmpl $0, attr_size(%rip)
jle .LBB6_18
# %bb.16: # %.lr.ph55.preheader
# in Loop: Header=BB6_15 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_17: # %.lr.ph55
# Parent Loop BB6_15 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
incq %r15
movslq attr_size(%rip), %rax
cmpq %rax, %r15
jl .LBB6_17
jmp .LBB6_18
.LBB6_19: # %._crit_edge58
movq (%rsp), %rdi
callq hipFree
addq $4176, %rsp # imm = 0x1050
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_20:
.cfi_def_cfa_offset 4208
movl $-1, %edi
callq exit
.Lfunc_end6:
.size _Z15cuda_malloc_cpyv, .Lfunc_end6-_Z15cuda_malloc_cpyv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, fp(%rip)
xorl %eax, %eax
.LBB7_1: # %.sink.split
# =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
movl %eax, attr_size(%rip)
.p2align 4, 0x90
.LBB7_2: # Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
movq fp(%rip), %rdi
callq fgetc
cmpb $-1, %al
je .LBB7_5
# %bb.3: # in Loop: Header=BB7_2 Depth=2
movzbl %al, %eax
cmpl $91, %eax
jne .LBB7_2
# %bb.4: # in Loop: Header=BB7_1 Depth=1
movl attr_size(%rip), %eax
incl %eax
jmp .LBB7_1
.LBB7_5: # %_Z13get_attr_sizev.exit
movl attr_size(%rip), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movl %ecx, attr_size(%rip)
movq fp(%rip), %rdi
callq fclose
callq _Z10get_bitmapv
movl $0, attr_total(%rip)
movl key(%rip), %eax
testl %eax, %eax
jle .LBB7_9
# %bb.6: # %.lr.ph.i
movslq offset(%rip), %rcx
movl bin_31(%rip), %edx
xorl %esi, %esi
shlq $2, %rcx
movl $1, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_7: # =>This Inner Loop Header: Depth=1
movl bit(%rcx,%rsi,4), %r9d
cmpl %edx, %r9d
cmoval %edi, %r9d
addl %r9d, %r8d
incq %rsi
cmpq %rsi, %rax
jne .LBB7_7
# %bb.8: # %._crit_edge.i
movl %r8d, attr_total(%rip)
.LBB7_9: # %_Z9get_totalv.exit
movl attr_total(%rip), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
callq _Z8get_attrv
callq _Z15cuda_malloc_cpyv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19kernel_index_bitmapPPjPiS1_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type bit,@object # @bit
.bss
.globl bit
.p2align 4, 0x0
bit:
.zero 4000
.size bit, 4000
.type bitat,@object # @bitat
.globl bitat
.p2align 4, 0x0
bitat:
.zero 4000
.size bitat, 4000
.type key,@object # @key
.globl key
.p2align 4, 0x0
key:
.zero 1200
.size key, 1200
.type offset,@object # @offset
.globl offset
.p2align 4, 0x0
offset:
.zero 1200
.size offset, 1200
.type index_bit,@object # @index_bit
.globl index_bit
.p2align 4, 0x0
index_bit:
.zero 400
.size index_bit, 400
.type index_long,@object # @index_long
.globl index_long
.p2align 2, 0x0
index_long:
.zero 4
.size index_long, 4
.type attr_size,@object # @attr_size
.globl attr_size
.p2align 2, 0x0
attr_size:
.long 0 # 0x0
.size attr_size, 4
.type attr_total,@object # @attr_total
.globl attr_total
.p2align 2, 0x0
attr_total:
.long 0 # 0x0
.size attr_total, 4
.type bin_31,@object # @bin_31
.data
.globl bin_31
.p2align 2, 0x0
bin_31:
.long 2147483648 # 0x80000000
.size bin_31, 4
.type fp,@object # @fp
.bss
.globl fp
.p2align 3, 0x0
fp:
.quad 0
.size fp, 8
.type str,@object # @str
.globl str
.p2align 4, 0x0
str:
.zero 33
.size str, 33
.type res,@object # @res
.globl res
.p2align 2, 0x0
res:
.long 0 # 0x0
.size res, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "outputm.txt"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "attr_total:%d\n"
.size .L.str.3, 15
.type _Z19kernel_index_bitmapPPjPiS1_iiii,@object # @_Z19kernel_index_bitmapPPjPiS1_iiii
.section .rodata,"a",@progbits
.globl _Z19kernel_index_bitmapPPjPiS1_iiii
.p2align 3, 0x0
_Z19kernel_index_bitmapPPjPiS1_iiii:
.quad _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.size _Z19kernel_index_bitmapPPjPiS1_iiii, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "mul:%d\n"
.size .L.str.5, 8
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "long:%d\n"
.size .L.str.15, 9
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%d,"
.size .L.str.16, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19kernel_index_bitmapPPjPiS1_iiii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Please input the attribute you choose(if not,input -1):"
.size .Lstr.1, 56
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n[0] "
.size .Lstr.2, 6
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "[1] "
.size .Lstr.3, 5
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "[2] "
.size .Lstr.4, 5
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "[3] "
.size .Lstr.5, 5
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "[4] "
.size .Lstr.6, 5
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "---------------T_T-------------"
.size .Lstr.7, 32
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "[5] "
.size .Lstr.8, 5
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "[6] "
.size .Lstr.9, 5
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "[7] "
.size .Lstr.10, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym bit
.addrsig_sym bitat
.addrsig_sym index_bit
.addrsig_sym index_long
.addrsig_sym _Z19kernel_index_bitmapPPjPiS1_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016854f_00000000-6_index2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2067:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2067:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7my_itoaiPci
.type _Z7my_itoaiPci, @function
_Z7my_itoaiPci:
.LFB2057:
.cfi_startproc
endbr64
leaq 31(%rsi), %rax
jmp .L6
.L4:
movb $48, (%rax)
.L5:
sarl %edi
leaq -1(%rax), %rdx
cmpq %rsi, %rax
je .L8
movq %rdx, %rax
.L6:
testb $1, %dil
je .L4
movb $49, (%rax)
jmp .L5
.L8:
movb $0, 32(%rsi)
ret
.cfi_endproc
.LFE2057:
.size _Z7my_itoaiPci, .-_Z7my_itoaiPci
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "outputm.txt"
.text
.globl _Z13get_attr_sizev
.type _Z13get_attr_sizev, @function
_Z13get_attr_sizev:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, fp(%rip)
movl $0, %eax
.L10:
movl %eax, attr_size(%rip)
.L11:
movq fp(%rip), %rdi
call fgetc@PLT
cmpb $-1, %al
je .L15
cmpb $91, %al
jne .L11
movl attr_size(%rip), %eax
addl $1, %eax
jmp .L10
.L15:
movl attr_size(%rip), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
movl %eax, attr_size(%rip)
movq fp(%rip), %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z13get_attr_sizev, .-_Z13get_attr_sizev
.section .rodata.str1.1
.LC2:
.string "%d"
.text
.globl _Z10get_bitmapv
.type _Z10get_bitmapv, @function
_Z10get_bitmapv:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %rdi
movq %rax, fp(%rip)
leaq bit(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $0, %eax
call __isoc23_fscanf@PLT
movl $1, %ebx
movl $0, %r13d
leaq bit(%rip), %r15
leaq .LC2(%rip), %rbp
jmp .L17
.L30:
leaq 4(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movslq %r13d, %rax
movq %rax, %r12
salq $4, %r12
subq %rax, %r12
salq $3, %r12
leaq key(%rip), %rax
leaq (%rax,%r12), %r14
movl $0, %ebx
jmp .L19
.L20:
movl 4(%rsp), %eax
movl %eax, (%r14,%rbx,4)
leaq 4(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
.L19:
movq fp(%rip), %rdi
call fgetc@PLT
cmpl $93, %eax
jne .L20
movslq %ebx, %rbx
movslq %r13d, %rdx
movq %rdx, %rax
salq $4, %rax
subq %rdx, %rax
leaq (%rbx,%rax,2), %rax
movl 4(%rsp), %edx
leaq key(%rip), %rcx
movl %edx, (%rcx,%rax,4)
.L21:
movq fp(%rip), %rdi
call fgetc@PLT
cmpl $91, %eax
jne .L21
leaq 4(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
leaq offset(%rip), %rax
addq %rax, %r12
movl $0, %ebx
jmp .L22
.L23:
movl 4(%rsp), %eax
movl %eax, (%r12,%rbx,4)
leaq 4(%rsp), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addq $1, %rbx
.L22:
movq fp(%rip), %rdi
call fgetc@PLT
cmpl $93, %eax
jne .L23
movslq %ebx, %rbx
movslq %r13d, %rdx
movq %rdx, %rax
salq $4, %rax
subq %rdx, %rax
leaq (%rbx,%rax,2), %rax
movl 4(%rsp), %edx
leaq offset(%rip), %rcx
movl %edx, (%rcx,%rax,4)
addl $1, %r13d
movl $0, %ebx
.L17:
movq fp(%rip), %rdi
call fgetc@PLT
cmpb $-1, %al
je .L29
cmpb $91, %al
je .L30
movslq %r13d, %rax
leaq (%rax,%rax,4), %rax
leaq (%rax,%rax,4), %rdx
movslq %ebx, %rax
leaq (%rax,%rdx,4), %rax
leaq (%r15,%rax,4), %rdx
movq %rbp, %rsi
movq fp(%rip), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
addl $1, %ebx
jmp .L17
.L29:
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z10get_bitmapv, .-_Z10get_bitmapv
.section .rodata.str1.1
.LC3:
.string "attr_total:%d\n"
.text
.globl _Z9get_totalv
.type _Z9get_totalv, @function
_Z9get_totalv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, attr_total(%rip)
movl key(%rip), %eax
movl offset(%rip), %ecx
testl %eax, %eax
jle .L33
movl bin_31(%rip), %r8d
movslq %ecx, %rcx
leaq bit(%rip), %rsi
leaq (%rsi,%rcx,4), %rdx
cltq
addq %rcx, %rax
leaq (%rsi,%rax,4), %rdi
movl $0, %eax
.L36:
movl (%rdx), %ecx
leal 1(%rax), %esi
addl %ecx, %eax
cmpl %ecx, %r8d
cmovb %esi, %eax
addq $4, %rdx
cmpq %rdi, %rdx
jne .L36
movl %eax, attr_total(%rip)
.L33:
movl attr_total(%rip), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9get_totalv, .-_Z9get_totalv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Please input the attribute you choose(if not,input -1):\n"
.text
.globl _Z8get_attrv
.type _Z8get_attrv, @function
_Z8get_attrv:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movl $0, index_long(%rip)
movl attr_total(%rip), %eax
testl %eax, %eax
jle .L40
movl attr_size(%rip), %esi
movslq %esi, %rcx
leaq bitat(%rip), %rdi
leaq (%rdi,%rcx,4), %rdx
cltq
leaq (%rax,%rax,4), %rax
leaq (%rcx,%rax,2), %rax
leaq (%rdi,%rax,4), %rdi
negq %rcx
salq $2, %rcx
jmp .L41
.L42:
movl $-1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L42
.L44:
addq $40, %rdx
cmpq %rdi, %rdx
je .L40
.L41:
leaq (%rdx,%rcx), %rax
testl %esi, %esi
jg .L42
jmp .L44
.L40:
cmpl $0, attr_size(%rip)
jle .L39
movl $0, %ebx
leaq .LC4(%rip), %r13
leaq .LC2(%rip), %rbp
leaq key(%rip), %r15
leaq offset(%rip), %r14
jmp .L48
.L66:
movl $0, 16(%rsp,%rbx,4)
movl $0, %eax
.L47:
movl %eax, 64(%rsp,%rbx,4)
movl attr_size(%rip), %r12d
addq $1, %rbx
cmpl %ebx, %r12d
jle .L65
.L48:
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 12(%rsp), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 12(%rsp), %eax
cmpl $-1, %eax
je .L66
cltq
movslq %ebx, %rcx
movq %rcx, %rdx
salq $4, %rdx
movq %rdx, %rsi
subq %rcx, %rsi
leaq (%rax,%rsi,2), %rsi
movl (%r15,%rsi,4), %esi
movl %esi, 16(%rsp,%rbx,4)
subq %rcx, %rdx
leaq (%rax,%rdx,2), %rax
movl (%r14,%rax,4), %eax
jmp .L47
.L65:
testl %r12d, %r12d
jle .L39
movl bin_31(%rip), %ebx
movslq %r12d, %r12
movl $0, %ebp
movl $0, %r9d
leaq bit(%rip), %r13
movl $-1, %r14d
leaq bitat(%rip), %r8
jmp .L49
.L67:
testl %ecx, %ecx
je .L52
movslq %eax, %rsi
leaq (%rsi,%rsi,4), %rax
leaq (%r9,%rax,2), %rax
leaq (%r8,%rax,4), %rax
movl %ecx, %r15d
addq %r15, %rsi
leaq (%rsi,%rsi,4), %rsi
leaq (%r9,%rsi,2), %rsi
leaq (%r8,%rsi,4), %rsi
.L54:
movl $0, 40(%rax)
addq $40, %rax
cmpq %rsi, %rax
jne .L54
.L52:
leal -1(%rcx,%rdi), %eax
.L53:
addq $4, %rdx
cmpq %r10, %rdx
je .L57
.L55:
leal 1(%rax), %edi
movl (%rdx), %ecx
cmpl %ecx, %ebx
jnb .L67
movslq %edi, %rax
leaq (%rax,%rax,4), %rax
leaq (%r11,%rax,2), %rax
movl %ecx, (%r8,%rax,4)
movl %edi, %eax
jmp .L53
.L57:
addq $1, %r9
addq $100, %rbp
cmpq %r12, %r9
je .L39
.L49:
movl %r9d, %r11d
movl 16(%rsp,%r9,4), %eax
testl %eax, %eax
jle .L57
movslq 64(%rsp,%r9,4), %rcx
leaq (%rcx,%rbp), %rdx
leaq 0(%r13,%rdx,4), %rdx
cltq
addq %rcx, %rax
addq %rbp, %rax
leaq 0(%r13,%rax,4), %r10
movl %r14d, %eax
movslq %r11d, %r11
jmp .L55
.L39:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L68
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z8get_attrv, .-_Z8get_attrv
.globl _Z6d_itoaiPc
.type _Z6d_itoaiPc, @function
_Z6d_itoaiPc:
.LFB2062:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2062:
.size _Z6d_itoaiPc, .-_Z6d_itoaiPc
.globl _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii
.type _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii, @function
_Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii:
.LFB2089:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L75
.L71:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L76
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L75:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z19kernel_index_bitmapPPjPiS1_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L71
.L76:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii, .-_Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii
.globl _Z19kernel_index_bitmapPPjPiS1_iiii
.type _Z19kernel_index_bitmapPPjPiS1_iiii, @function
_Z19kernel_index_bitmapPPjPiS1_iiii:
.LFB2090:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z19kernel_index_bitmapPPjPiS1_iiii, .-_Z19kernel_index_bitmapPPjPiS1_iiii
.section .rodata.str1.1
.LC5:
.string "mul:%d\n"
.LC6:
.string "\n[0] \n"
.LC7:
.string "[1] \n"
.LC8:
.string "[2] \n"
.LC9:
.string "[3] \n"
.LC10:
.string "[4] \n"
.section .rodata.str1.8
.align 8
.LC11:
.string "---------------T_T-------------\n"
.section .rodata.str1.1
.LC12:
.string "[5] \n"
.LC13:
.string "[6] \n"
.LC14:
.string "[7] \n"
.LC15:
.string "long:%d\n"
.LC16:
.string "%d,"
.LC17:
.string "\n"
.text
.globl _Z15cuda_malloc_cpyv
.type _Z15cuda_malloc_cpyv, @function
_Z15cuda_malloc_cpyv:
.LFB2063:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $4064, %rsp
.cfi_def_cfa_offset 4112
movq %fs:40, %rax
movq %rax, 4056(%rsp)
xorl %eax, %eax
movl attr_total(%rip), %eax
addl $2, %eax
movslq %eax, %rbx
imulq $1431655766, %rbx, %rbx
shrq $32, %rbx
sarl $31, %eax
subl %eax, %ebx
movl %ebx, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rbp
leaq 88(%rsp), %rdx
leaq 4088(%rsp), %rcx
jmp .L80
.L107:
addq $40, %rdx
cmpq %rcx, %rdx
je .L82
.L80:
leaq -40(%rdx), %rax
.L81:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L81
jmp .L107
.L82:
movq %rsp, %rdi
movl $400, %esi
call cudaMalloc@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L108
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L109
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L110
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4000, %edx
leaq bitat(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L111
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $4, %edx
leaq index_long(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L112
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $3, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L113
.L88:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $400, %edx
movq (%rsp), %rsi
leaq index_bit(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L114
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
leaq index_long(%rip), %rdi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L115
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $4000, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl %eax, res(%rip)
testl %eax, %eax
jne .L116
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl index_long(%rip), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, index_long(%rip)
jle .L92
movl $0, %ebx
leaq index_bit(%rip), %r13
leaq .LC16(%rip), %r12
.L93:
movl 0(%r13,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, index_long(%rip)
jg .L93
.L92:
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r13d
leaq .LC16(%rip), %r12
leaq .LC17(%rip), %r14
cmpl $0, attr_total(%rip)
jg .L94
.L95:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 4056(%rsp), %rax
subq %fs:40, %rax
jne .L117
addq $4064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L108:
.cfi_restore_state
movl $-1, %edi
call exit@PLT
.L109:
movl $-1, %edi
call exit@PLT
.L110:
movl $-1, %edi
call exit@PLT
.L111:
movl $-1, %edi
call exit@PLT
.L112:
movl $-1, %edi
call exit@PLT
.L113:
subq $8, %rsp
.cfi_def_cfa_offset 4120
pushq %rbx
.cfi_def_cfa_offset 4128
movl $10, %r9d
movl attr_size(%rip), %r8d
movl attr_total(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z49__device_stub__Z19kernel_index_bitmapPPjPiS1_iiiiPPjPiS1_iiii
addq $16, %rsp
.cfi_def_cfa_offset 4112
jmp .L88
.L114:
movl $-1, %edi
call exit@PLT
.L115:
movl $-1, %edi
call exit@PLT
.L116:
movl $-1, %edi
call exit@PLT
.L96:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, attr_size(%rip)
jg .L96
.L97:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addq $40, %rbp
cmpl %r13d, attr_total(%rip)
jle .L95
.L94:
movl $0, %ebx
cmpl $0, attr_size(%rip)
jg .L96
jmp .L97
.L117:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z15cuda_malloc_cpyv, .-_Z15cuda_malloc_cpyv
.globl main
.type main, @function
main:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z13get_attr_sizev
call _Z10get_bitmapv
call _Z9get_totalv
call _Z8get_attrv
call _Z15cuda_malloc_cpyv
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC18:
.string "_Z19kernel_index_bitmapPPjPiS1_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z19kernel_index_bitmapPPjPiS1_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl res
.bss
.align 4
.type res, @object
.size res, 4
res:
.zero 4
.globl str
.align 32
.type str, @object
.size str, 33
str:
.zero 33
.globl fp
.align 8
.type fp, @object
.size fp, 8
fp:
.zero 8
.globl bin_31
.data
.align 4
.type bin_31, @object
.size bin_31, 4
bin_31:
.long -2147483648
.globl attr_total
.bss
.align 4
.type attr_total, @object
.size attr_total, 4
attr_total:
.zero 4
.globl attr_size
.align 4
.type attr_size, @object
.size attr_size, 4
attr_size:
.zero 4
.globl index_long
.align 4
.type index_long, @object
.size index_long, 4
index_long:
.zero 4
.globl index_bit
.align 32
.type index_bit, @object
.size index_bit, 400
index_bit:
.zero 400
.globl offset
.align 32
.type offset, @object
.size offset, 1200
offset:
.zero 1200
.globl key
.align 32
.type key, @object
.size key, 1200
key:
.zero 1200
.globl bitat
.align 32
.type bitat, @object
.size bitat, 4000
bitat:
.zero 4000
.globl bit
.align 32
.type bit, @object
.size bit, 4000
bit:
.zero 4000
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "index2.hip"
.globl _Z7my_itoaiPci # -- Begin function _Z7my_itoaiPci
.p2align 4, 0x90
.type _Z7my_itoaiPci,@function
_Z7my_itoaiPci: # @_Z7my_itoaiPci
.cfi_startproc
# %bb.0:
movl $32, %eax
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %edi, %ecx
andb $1, %cl
orb $48, %cl
movb %cl, -1(%rsi,%rax)
sarl %edi
decq %rax
jne .LBB0_1
# %bb.2:
movb $0, 32(%rsi)
retq
.Lfunc_end0:
.size _Z7my_itoaiPci, .Lfunc_end0-_Z7my_itoaiPci
.cfi_endproc
# -- End function
.globl _Z13get_attr_sizev # -- Begin function _Z13get_attr_sizev
.p2align 4, 0x90
.type _Z13get_attr_sizev,@function
_Z13get_attr_sizev: # @_Z13get_attr_sizev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, fp(%rip)
xorl %eax, %eax
.LBB1_1: # %.sink.split
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
movl %eax, attr_size(%rip)
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
movq fp(%rip), %rdi
callq fgetc
cmpb $-1, %al
je .LBB1_5
# %bb.3: # in Loop: Header=BB1_2 Depth=2
movzbl %al, %eax
cmpl $91, %eax
jne .LBB1_2
# %bb.4: # in Loop: Header=BB1_1 Depth=1
movl attr_size(%rip), %eax
incl %eax
jmp .LBB1_1
.LBB1_5:
movl attr_size(%rip), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movl %ecx, attr_size(%rip)
movq fp(%rip), %rdi
popq %rax
.cfi_def_cfa_offset 8
jmp fclose # TAILCALL
.Lfunc_end1:
.size _Z13get_attr_sizev, .Lfunc_end1-_Z13get_attr_sizev
.cfi_endproc
# -- End function
.globl _Z10get_bitmapv # -- Begin function _Z10get_bitmapv
.p2align 4, 0x90
.type _Z10get_bitmapv,@function
_Z10get_bitmapv: # @_Z10get_bitmapv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, fp(%rip)
movl $bit, %r15d
movl $.L.str.2, %esi
movl $bit, %edx
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl $1, %eax
movl $key, %r12d
movl $offset, %r13d
leaq 12(%rsp), %rbx
xorl %ebp, %ebp
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_12: # %._crit_edge32
# in Loop: Header=BB2_1 Depth=1
movl 12(%rsp), %eax
movl %ebp, %ecx
movl %eax, offset(%r14,%rcx,4)
movl %r15d, %ebp
incl %ebp
movq 16(%rsp), %r15 # 8-byte Reload
addq $400, %r15 # imm = 0x190
addq $120, %r12
addq $120, %r13
xorl %eax, %eax
.LBB2_1: # %.outer
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_5 Depth 2
# Child Loop BB2_8 Depth 2
# Child Loop BB2_10 Depth 2
movl %eax, %eax
leaq (%r15,%rax,4), %r14
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq fp(%rip), %rdi
callq fgetc
cmpb $-1, %al
je .LBB2_14
# %bb.3: # in Loop: Header=BB2_2 Depth=2
movzbl %al, %eax
cmpl $91, %eax
je .LBB2_4
# %bb.13: # in Loop: Header=BB2_2 Depth=2
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r14
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_1 Depth=1
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
callq fgetc
xorl %r14d, %r14d
cmpl $93, %eax
je .LBB2_7
.p2align 4, 0x90
.LBB2_5: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 12(%rsp), %eax
movl %eax, (%r12,%r14,4)
incq %r14
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
callq fgetc
cmpl $93, %eax
jne .LBB2_5
.LBB2_7: # %._crit_edge
# in Loop: Header=BB2_1 Depth=1
movq %r15, 16(%rsp) # 8-byte Spill
movl 12(%rsp), %eax
movl %ebp, %ecx
movl %r14d, %edx
imulq $120, %rcx, %r14
movl %eax, key(%r14,%rdx,4)
.p2align 4, 0x90
.LBB2_8: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movq fp(%rip), %rdi
callq fgetc
cmpl $91, %eax
jne .LBB2_8
# %bb.9: # in Loop: Header=BB2_1 Depth=1
movl %ebp, %r15d
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
callq fgetc
xorl %ebp, %ebp
cmpl $93, %eax
je .LBB2_12
.p2align 4, 0x90
.LBB2_10: # %.lr.ph31
# Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movl 12(%rsp), %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
movq fp(%rip), %rdi
movl $.L.str.2, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq fp(%rip), %rdi
callq fgetc
cmpl $93, %eax
jne .LBB2_10
jmp .LBB2_12
.LBB2_14:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z10get_bitmapv, .Lfunc_end2-_Z10get_bitmapv
.cfi_endproc
# -- End function
.globl _Z9get_totalv # -- Begin function _Z9get_totalv
.p2align 4, 0x90
.type _Z9get_totalv,@function
_Z9get_totalv: # @_Z9get_totalv
.cfi_startproc
# %bb.0:
movl $0, attr_total(%rip)
movl key(%rip), %eax
testl %eax, %eax
jle .LBB3_4
# %bb.1: # %.lr.ph
movslq offset(%rip), %rdx
movl attr_total(%rip), %ecx
movl bin_31(%rip), %esi
xorl %edi, %edi
shlq $2, %rdx
movl $1, %r8d
.p2align 4, 0x90
.LBB3_2: # =>This Inner Loop Header: Depth=1
movl bit(%rdx,%rdi,4), %r9d
cmpl %esi, %r9d
cmoval %r8d, %r9d
addl %r9d, %ecx
incq %rdi
cmpq %rdi, %rax
jne .LBB3_2
# %bb.3: # %._crit_edge
movl %ecx, attr_total(%rip)
.LBB3_4:
movl attr_total(%rip), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z9get_totalv, .Lfunc_end3-_Z9get_totalv
.cfi_endproc
# -- End function
.globl _Z8get_attrv # -- Begin function _Z8get_attrv
.p2align 4, 0x90
.type _Z8get_attrv,@function
_Z8get_attrv: # @_Z8get_attrv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $104, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, index_long(%rip)
movl attr_total(%rip), %eax
testl %eax, %eax
jle .LBB4_5
# %bb.1: # %.preheader51.lr.ph
movl attr_size(%rip), %r14d
movq %r14, %rbx
shlq $2, %rbx
shlq $3, %rax
leaq (%rax,%rax,4), %r15
xorl %r12d, %r12d
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_4: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
addq $40, %r12
cmpq %r12, %r15
je .LBB4_5
.LBB4_2: # %.preheader51
# =>This Inner Loop Header: Depth=1
testl %r14d, %r14d
jle .LBB4_4
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
leaq bitat(%r12), %rdi
movl $255, %esi
movq %rbx, %rdx
callq memset@PLT
jmp .LBB4_4
.LBB4_5: # %.preheader50
movl attr_size(%rip), %ecx
testl %ecx, %ecx
jle .LBB4_9
# %bb.6: # %.lr.ph55.preheader
leaq 12(%rsp), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB4_7
.p2align 4, 0x90
.LBB4_18: # in Loop: Header=BB4_7 Depth=1
movl key(%r14,%rax,4), %ecx
movl %ecx, 16(%rsp,%r15,4)
movl offset(%r14,%rax,4), %eax
.LBB4_19: # in Loop: Header=BB4_7 Depth=1
movl %eax, 64(%rsp,%r15,4)
incq %r15
movslq attr_size(%rip), %rcx
addq $120, %r14
cmpq %rcx, %r15
jge .LBB4_9
.LBB4_7: # %.lr.ph55
# =>This Inner Loop Header: Depth=1
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %rax
cmpq $-1, %rax
jne .LBB4_18
# %bb.8: # in Loop: Header=BB4_7 Depth=1
movl $0, 16(%rsp,%r15,4)
xorl %eax, %eax
jmp .LBB4_19
.LBB4_9: # %.preheader49
testl %ecx, %ecx
jle .LBB4_23
# %bb.10: # %.preheader48.lr.ph
movl bin_31(%rip), %eax
movl %ecx, %ecx
movl $bitat, %edx
xorl %esi, %esi
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_22: # %._crit_edge62
# in Loop: Header=BB4_11 Depth=1
incq %rsi
addq $4, %rdx
cmpq %rcx, %rsi
je .LBB4_23
.LBB4_11: # %.preheader48
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
# Child Loop BB4_16 Depth 3
movl 16(%rsp,%rsi,4), %edi
testl %edi, %edi
jle .LBB4_22
# %bb.12: # %.lr.ph61
# in Loop: Header=BB4_11 Depth=1
movslq 64(%rsp,%rsi,4), %r8
movl $-1, %ebx
imulq $400, %rsi, %r9 # imm = 0x190
leaq (,%rsi,4), %r10
xorl %r11d, %r11d
jmp .LBB4_13
.p2align 4, 0x90
.LBB4_20: # in Loop: Header=BB4_13 Depth=2
movslq %ebp, %rbx
leaq (%rbx,%rbx,4), %rbx
movl %r14d, bitat(%r10,%rbx,8)
.LBB4_21: # in Loop: Header=BB4_13 Depth=2
incq %r11
movl %ebp, %ebx
cmpq %rdi, %r11
je .LBB4_22
.LBB4_13: # Parent Loop BB4_11 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_16 Depth 3
leal 1(%rbx), %ebp
leaq (%r11,%r8), %r14
movl bit(%r9,%r14,4), %r14d
cmpl %eax, %r14d
ja .LBB4_20
# %bb.14: # %.preheader
# in Loop: Header=BB4_13 Depth=2
testl %r14d, %r14d
je .LBB4_17
# %bb.15: # %.lr.ph57.preheader
# in Loop: Header=BB4_13 Depth=2
movslq %ebp, %r15
leaq (%r15,%r15,4), %r15
leaq (%rdx,%r15,8), %r15
leaq (,%r14,8), %r12
leaq (%r12,%r12,4), %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB4_16: # %.lr.ph57
# Parent Loop BB4_11 Depth=1
# Parent Loop BB4_13 Depth=2
# => This Inner Loop Header: Depth=3
movl $0, (%r15,%r13)
addq $40, %r13
cmpq %r13, %r12
jne .LBB4_16
.LBB4_17: # %._crit_edge58
# in Loop: Header=BB4_13 Depth=2
addl %ebx, %r14d
movl %r14d, %ebp
jmp .LBB4_21
.LBB4_23: # %._crit_edge64
addq $104, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z8get_attrv, .Lfunc_end4-_Z8get_attrv
.cfi_endproc
# -- End function
.globl _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii # -- Begin function _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.p2align 4, 0x90
.type _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii,@function
_Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii: # @_Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z19kernel_index_bitmapPPjPiS1_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end5:
.size _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii, .Lfunc_end5-_Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.cfi_endproc
# -- End function
.globl _Z15cuda_malloc_cpyv # -- Begin function _Z15cuda_malloc_cpyv
.p2align 4, 0x90
.type _Z15cuda_malloc_cpyv,@function
_Z15cuda_malloc_cpyv: # @_Z15cuda_malloc_cpyv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $4176, %rsp # imm = 0x1050
.cfi_def_cfa_offset 4208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl attr_total(%rip), %eax
addl $2, %eax
cltq
imulq $1431655766, %rax, %rbx # imm = 0x55555556
movq %rbx, %rax
shrq $63, %rax
shrq $32, %rbx
addl %eax, %ebx
movl $.L.str.5, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 176(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
xorl %esi, %esi
callq memset@PLT
leaq 32(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.1:
movl $.Lstr.2, %edi
callq puts@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.2:
movl $.Lstr.3, %edi
callq puts@PLT
movq %rsp, %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.3:
movl $.Lstr.4, %edi
callq puts@PLT
movq (%rsp), %rdi
movl $bitat, %esi
movl $4000, %edx # imm = 0xFA0
movl $1, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.4:
movl $.Lstr.5, %edi
callq puts@PLT
movq 8(%rsp), %rdi
movl $index_long, %esi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.5:
movl $.Lstr.6, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 2(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_7
# %bb.6:
movq (%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movl attr_total(%rip), %esi
movl attr_size(%rip), %edi
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %esi, 28(%rsp)
movl %edi, 24(%rsp)
movl $10, 20(%rsp)
movl %ebx, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z19kernel_index_bitmapPPjPiS1_iiii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_7:
movl $.Lstr.7, %edi
callq puts@PLT
movq 32(%rsp), %rsi
movl $index_bit, %edi
movl $400, %edx # imm = 0x190
movl $2, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.8:
movl $.Lstr.8, %edi
callq puts@PLT
movq 8(%rsp), %rsi
movl $index_long, %edi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.9:
movl $.Lstr.9, %edi
callq puts@PLT
movq (%rsp), %rsi
leaq 176(%rsp), %rbx
movl $4000, %edx # imm = 0xFA0
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl %eax, res(%rip)
testl %eax, %eax
jne .LBB6_20
# %bb.10:
movl $.Lstr.10, %edi
callq puts@PLT
movl index_long(%rip), %esi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
cmpl $0, index_long(%rip)
jle .LBB6_13
# %bb.11: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB6_12: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl index_bit(,%r14,4), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
incq %r14
movslq index_long(%rip), %rax
cmpq %rax, %r14
jl .LBB6_12
.LBB6_13: # %._crit_edge
movl $10, %edi
callq putchar@PLT
cmpl $0, attr_total(%rip)
jle .LBB6_19
# %bb.14: # %.preheader.preheader
xorl %r14d, %r14d
jmp .LBB6_15
.p2align 4, 0x90
.LBB6_18: # %._crit_edge56
# in Loop: Header=BB6_15 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
movslq attr_total(%rip), %rax
addq $40, %rbx
cmpq %rax, %r14
jge .LBB6_19
.LBB6_15: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB6_17 Depth 2
cmpl $0, attr_size(%rip)
jle .LBB6_18
# %bb.16: # %.lr.ph55.preheader
# in Loop: Header=BB6_15 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB6_17: # %.lr.ph55
# Parent Loop BB6_15 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %esi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
incq %r15
movslq attr_size(%rip), %rax
cmpq %rax, %r15
jl .LBB6_17
jmp .LBB6_18
.LBB6_19: # %._crit_edge58
movq (%rsp), %rdi
callq hipFree
addq $4176, %rsp # imm = 0x1050
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB6_20:
.cfi_def_cfa_offset 4208
movl $-1, %edi
callq exit
.Lfunc_end6:
.size _Z15cuda_malloc_cpyv, .Lfunc_end6-_Z15cuda_malloc_cpyv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, fp(%rip)
xorl %eax, %eax
.LBB7_1: # %.sink.split
# =>This Loop Header: Depth=1
# Child Loop BB7_2 Depth 2
movl %eax, attr_size(%rip)
.p2align 4, 0x90
.LBB7_2: # Parent Loop BB7_1 Depth=1
# => This Inner Loop Header: Depth=2
movq fp(%rip), %rdi
callq fgetc
cmpb $-1, %al
je .LBB7_5
# %bb.3: # in Loop: Header=BB7_2 Depth=2
movzbl %al, %eax
cmpl $91, %eax
jne .LBB7_2
# %bb.4: # in Loop: Header=BB7_1 Depth=1
movl attr_size(%rip), %eax
incl %eax
jmp .LBB7_1
.LBB7_5: # %_Z13get_attr_sizev.exit
movl attr_size(%rip), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
movl %ecx, attr_size(%rip)
movq fp(%rip), %rdi
callq fclose
callq _Z10get_bitmapv
movl $0, attr_total(%rip)
movl key(%rip), %eax
testl %eax, %eax
jle .LBB7_9
# %bb.6: # %.lr.ph.i
movslq offset(%rip), %rcx
movl bin_31(%rip), %edx
xorl %esi, %esi
shlq $2, %rcx
movl $1, %edi
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB7_7: # =>This Inner Loop Header: Depth=1
movl bit(%rcx,%rsi,4), %r9d
cmpl %edx, %r9d
cmoval %edi, %r9d
addl %r9d, %r8d
incq %rsi
cmpq %rsi, %rax
jne .LBB7_7
# %bb.8: # %._crit_edge.i
movl %r8d, attr_total(%rip)
.LBB7_9: # %_Z9get_totalv.exit
movl attr_total(%rip), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
callq _Z8get_attrv
callq _Z15cuda_malloc_cpyv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19kernel_index_bitmapPPjPiS1_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type bit,@object # @bit
.bss
.globl bit
.p2align 4, 0x0
bit:
.zero 4000
.size bit, 4000
.type bitat,@object # @bitat
.globl bitat
.p2align 4, 0x0
bitat:
.zero 4000
.size bitat, 4000
.type key,@object # @key
.globl key
.p2align 4, 0x0
key:
.zero 1200
.size key, 1200
.type offset,@object # @offset
.globl offset
.p2align 4, 0x0
offset:
.zero 1200
.size offset, 1200
.type index_bit,@object # @index_bit
.globl index_bit
.p2align 4, 0x0
index_bit:
.zero 400
.size index_bit, 400
.type index_long,@object # @index_long
.globl index_long
.p2align 2, 0x0
index_long:
.zero 4
.size index_long, 4
.type attr_size,@object # @attr_size
.globl attr_size
.p2align 2, 0x0
attr_size:
.long 0 # 0x0
.size attr_size, 4
.type attr_total,@object # @attr_total
.globl attr_total
.p2align 2, 0x0
attr_total:
.long 0 # 0x0
.size attr_total, 4
.type bin_31,@object # @bin_31
.data
.globl bin_31
.p2align 2, 0x0
bin_31:
.long 2147483648 # 0x80000000
.size bin_31, 4
.type fp,@object # @fp
.bss
.globl fp
.p2align 3, 0x0
fp:
.quad 0
.size fp, 8
.type str,@object # @str
.globl str
.p2align 4, 0x0
str:
.zero 33
.size str, 33
.type res,@object # @res
.globl res
.p2align 2, 0x0
res:
.long 0 # 0x0
.size res, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "outputm.txt"
.size .L.str, 12
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "attr_total:%d\n"
.size .L.str.3, 15
.type _Z19kernel_index_bitmapPPjPiS1_iiii,@object # @_Z19kernel_index_bitmapPPjPiS1_iiii
.section .rodata,"a",@progbits
.globl _Z19kernel_index_bitmapPPjPiS1_iiii
.p2align 3, 0x0
_Z19kernel_index_bitmapPPjPiS1_iiii:
.quad _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.size _Z19kernel_index_bitmapPPjPiS1_iiii, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "mul:%d\n"
.size .L.str.5, 8
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "long:%d\n"
.size .L.str.15, 9
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%d,"
.size .L.str.16, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z19kernel_index_bitmapPPjPiS1_iiii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "Please input the attribute you choose(if not,input -1):"
.size .Lstr.1, 56
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "\n[0] "
.size .Lstr.2, 6
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "[1] "
.size .Lstr.3, 5
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "[2] "
.size .Lstr.4, 5
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "[3] "
.size .Lstr.5, 5
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "[4] "
.size .Lstr.6, 5
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz "---------------T_T-------------"
.size .Lstr.7, 32
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz "[5] "
.size .Lstr.8, 5
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "[6] "
.size .Lstr.9, 5
.type .Lstr.10,@object # @str.10
.Lstr.10:
.asciz "[7] "
.size .Lstr.10, 5
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__kernel_index_bitmapPPjPiS1_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym bit
.addrsig_sym bitat
.addrsig_sym index_bit
.addrsig_sym index_long
.addrsig_sym _Z19kernel_index_bitmapPPjPiS1_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <chrono>
#include <cassert>
#include <cmath>
#include <cstdlib>
#include <vector>
#include <algorithm>
#define BLOCKSIZE 128
// MUST BE ASSOCIATIVE
__device__ inline int f(int a, int b){
return a + b;
}
/**
* Implements prefix-scan using a Hillis-Steele algorithm.
* Since Hillis-Steele assumes as many concurrent processors as data lines, we need to use
* "double-buffering" to simulate concurrent modifications.
* Since this algorithm requires 2 DRAM accesses per thread, this is a slow algorithm.
* In my results, it's still faster than a CPU algorithm. GPUs are so cool :)
**/
__global__ void prefix_scan(const int n, const int jump, int* old, int* nnew){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(0 <= i - jump){
nnew[i] = f(old[i], old[i - jump]);
} else {
nnew[i] = old[i];
}
}
int main(){
const int n = (1 << 28);
const int block_size = BLOCKSIZE;
assert(n % block_size == 0);
int *x = (int *) malloc(n * sizeof(int));
assert(x != NULL);
for(int i = 0; i < n; i++){
x[i] = 1;
}
int *d_x, *d_y;
cudaMalloc(&d_x, n * sizeof(int));
cudaMalloc(&d_y, n * sizeof(int));
cudaMemcpy(d_x, x, n * sizeof(float), cudaMemcpyHostToDevice);
int block_count = n / block_size;
for(int i = 1, j = 0; i < n; i *= 2, j++){
prefix_scan<<<block_count, block_size>>>(n, i, d_x, d_y);
std::swap(d_x, d_y);
}
int *result = (int *) malloc(n * sizeof(int));
cudaMemcpy(result, d_x, n * sizeof(int), cudaMemcpyDeviceToHost);
// Test to make sure prefix scan is correct.
for(int i = 0; i < n; i++){
if(result[i] != i + 1){
std::cerr << i << ' ' << i + 1 << ' ' << result[i] << '\n';
return -1;
}
}
std::cout << "memory usage: " << n * sizeof(int) << " bytes" << std::endl;
} | code for sm_80
Function : _Z11prefix_scaniiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0205 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fc80003f06270 */
/*0080*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000eb2000c1e1900 */
/*0090*/ @P0 IADD3 R4, R0, -c[0x0][0x164], RZ ; /* 0x8000590000040a10 */
/* 0x000fca0007ffe0ff */
/*00a0*/ @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004040625 */
/* 0x000fcc00078e0205 */
/*00b0*/ @P0 LDG.E R4, [R4.64] ; /* 0x0000000404040981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe40000011400 */
/*00d0*/ LEA R6, P1, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000067a11 */
/* 0x000fc800078210ff */
/*00e0*/ LEA.HI.X R7, R0, c[0x0][0x174], R7, 0x2, P1 ; /* 0x00005d0000077a11 */
/* 0x000fe200008f1407 */
/*00f0*/ @P0 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109090824 */
/* 0x004fca00078e0204 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <chrono>
#include <cassert>
#include <cmath>
#include <cstdlib>
#include <vector>
#include <algorithm>
#define BLOCKSIZE 128
// MUST BE ASSOCIATIVE
__device__ inline int f(int a, int b){
return a + b;
}
/**
* Implements prefix-scan using a Hillis-Steele algorithm.
* Since Hillis-Steele assumes as many concurrent processors as data lines, we need to use
* "double-buffering" to simulate concurrent modifications.
* Since this algorithm requires 2 DRAM accesses per thread, this is a slow algorithm.
* In my results, it's still faster than a CPU algorithm. GPUs are so cool :)
**/
__global__ void prefix_scan(const int n, const int jump, int* old, int* nnew){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(0 <= i - jump){
nnew[i] = f(old[i], old[i - jump]);
} else {
nnew[i] = old[i];
}
}
int main(){
const int n = (1 << 28);
const int block_size = BLOCKSIZE;
assert(n % block_size == 0);
int *x = (int *) malloc(n * sizeof(int));
assert(x != NULL);
for(int i = 0; i < n; i++){
x[i] = 1;
}
int *d_x, *d_y;
cudaMalloc(&d_x, n * sizeof(int));
cudaMalloc(&d_y, n * sizeof(int));
cudaMemcpy(d_x, x, n * sizeof(float), cudaMemcpyHostToDevice);
int block_count = n / block_size;
for(int i = 1, j = 0; i < n; i *= 2, j++){
prefix_scan<<<block_count, block_size>>>(n, i, d_x, d_y);
std::swap(d_x, d_y);
}
int *result = (int *) malloc(n * sizeof(int));
cudaMemcpy(result, d_x, n * sizeof(int), cudaMemcpyDeviceToHost);
// Test to make sure prefix scan is correct.
for(int i = 0; i < n; i++){
if(result[i] != i + 1){
std::cerr << i << ' ' << i + 1 << ' ' << result[i] << '\n';
return -1;
}
}
std::cout << "memory usage: " << n * sizeof(int) << " bytes" << std::endl;
} | .file "tmpxft_00138814_00000000-6_naive_parallel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4390:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4390:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_
.type _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_, @function
_Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_:
.LFB4412:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11prefix_scaniiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4412:
.size _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_, .-_Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_
.globl _Z11prefix_scaniiPiS_
.type _Z11prefix_scaniiPiS_, @function
_Z11prefix_scaniiPiS_:
.LFB4413:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4413:
.size _Z11prefix_scaniiPiS_, .-_Z11prefix_scaniiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "memory usage: "
.LC1:
.string " bytes"
.text
.globl main
.type main, @function
main:
.LFB4386:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
leaq 1073741824(%rax), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rsp, %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $28, %ebx
movl $1, %ebp
jmp .L14
.L13:
movq (%rsp), %rax
movq 8(%rsp), %r12
movq %r12, (%rsp)
movq %rax, 8(%rsp)
addl %ebp, %ebp
subl $1, %ebx
je .L23
.L14:
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $2097152, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movl %ebp, %esi
movl $268435456, %edi
call _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_
jmp .L13
.L23:
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $1073741824, %edx
movq %r12, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
movl $0, %ebx
.L17:
movq %rax, %rbp
movl %ebx, %esi
addl $1, %ebx
addq $4, %rax
cmpl %ebx, 0(%rbp)
jne .L24
cmpl $268435456, %ebx
jne .L17
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $1073741824, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
jmp .L11
.L24:
leaq _ZSt4cerr(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $32, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $32, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
movl 0(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $-1, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4386:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11prefix_scaniiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4415:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prefix_scaniiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4415:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <chrono>
#include <cassert>
#include <cmath>
#include <cstdlib>
#include <vector>
#include <algorithm>
#define BLOCKSIZE 128
// MUST BE ASSOCIATIVE
__device__ inline int f(int a, int b){
return a + b;
}
/**
* Implements prefix-scan using a Hillis-Steele algorithm.
* Since Hillis-Steele assumes as many concurrent processors as data lines, we need to use
* "double-buffering" to simulate concurrent modifications.
* Since this algorithm requires 2 DRAM accesses per thread, this is a slow algorithm.
* In my results, it's still faster than a CPU algorithm. GPUs are so cool :)
**/
__global__ void prefix_scan(const int n, const int jump, int* old, int* nnew){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(0 <= i - jump){
nnew[i] = f(old[i], old[i - jump]);
} else {
nnew[i] = old[i];
}
}
int main(){
const int n = (1 << 28);
const int block_size = BLOCKSIZE;
assert(n % block_size == 0);
int *x = (int *) malloc(n * sizeof(int));
assert(x != NULL);
for(int i = 0; i < n; i++){
x[i] = 1;
}
int *d_x, *d_y;
cudaMalloc(&d_x, n * sizeof(int));
cudaMalloc(&d_y, n * sizeof(int));
cudaMemcpy(d_x, x, n * sizeof(float), cudaMemcpyHostToDevice);
int block_count = n / block_size;
for(int i = 1, j = 0; i < n; i *= 2, j++){
prefix_scan<<<block_count, block_size>>>(n, i, d_x, d_y);
std::swap(d_x, d_y);
}
int *result = (int *) malloc(n * sizeof(int));
cudaMemcpy(result, d_x, n * sizeof(int), cudaMemcpyDeviceToHost);
// Test to make sure prefix scan is correct.
for(int i = 0; i < n; i++){
if(result[i] != i + 1){
std::cerr << i << ' ' << i + 1 << ' ' << result[i] << '\n';
return -1;
}
}
std::cout << "memory usage: " << n * sizeof(int) << " bytes" << std::endl;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
#include <cassert>
#include <cmath>
#include <cstdlib>
#include <vector>
#include <algorithm>
#define BLOCKSIZE 128
// MUST BE ASSOCIATIVE
__device__ inline int f(int a, int b){
return a + b;
}
/**
* Implements prefix-scan using a Hillis-Steele algorithm.
* Since Hillis-Steele assumes as many concurrent processors as data lines, we need to use
* "double-buffering" to simulate concurrent modifications.
* Since this algorithm requires 2 DRAM accesses per thread, this is a slow algorithm.
* In my results, it's still faster than a CPU algorithm. GPUs are so cool :)
**/
__global__ void prefix_scan(const int n, const int jump, int* old, int* nnew){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(0 <= i - jump){
nnew[i] = f(old[i], old[i - jump]);
} else {
nnew[i] = old[i];
}
}
int main(){
const int n = (1 << 28);
const int block_size = BLOCKSIZE;
assert(n % block_size == 0);
int *x = (int *) malloc(n * sizeof(int));
assert(x != NULL);
for(int i = 0; i < n; i++){
x[i] = 1;
}
int *d_x, *d_y;
hipMalloc(&d_x, n * sizeof(int));
hipMalloc(&d_y, n * sizeof(int));
hipMemcpy(d_x, x, n * sizeof(float), hipMemcpyHostToDevice);
int block_count = n / block_size;
for(int i = 1, j = 0; i < n; i *= 2, j++){
prefix_scan<<<block_count, block_size>>>(n, i, d_x, d_y);
std::swap(d_x, d_y);
}
int *result = (int *) malloc(n * sizeof(int));
hipMemcpy(result, d_x, n * sizeof(int), hipMemcpyDeviceToHost);
// Test to make sure prefix scan is correct.
for(int i = 0; i < n; i++){
if(result[i] != i + 1){
std::cerr << i << ' ' << i + 1 << ' ' << result[i] << '\n';
return -1;
}
}
std::cout << "memory usage: " << n * sizeof(int) << " bytes" << std::endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
#include <cassert>
#include <cmath>
#include <cstdlib>
#include <vector>
#include <algorithm>
#define BLOCKSIZE 128
// MUST BE ASSOCIATIVE
__device__ inline int f(int a, int b){
return a + b;
}
/**
* Implements prefix-scan using a Hillis-Steele algorithm.
* Since Hillis-Steele assumes as many concurrent processors as data lines, we need to use
* "double-buffering" to simulate concurrent modifications.
* Since this algorithm requires 2 DRAM accesses per thread, this is a slow algorithm.
* In my results, it's still faster than a CPU algorithm. GPUs are so cool :)
**/
__global__ void prefix_scan(const int n, const int jump, int* old, int* nnew){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(0 <= i - jump){
nnew[i] = f(old[i], old[i - jump]);
} else {
nnew[i] = old[i];
}
}
int main(){
const int n = (1 << 28);
const int block_size = BLOCKSIZE;
assert(n % block_size == 0);
int *x = (int *) malloc(n * sizeof(int));
assert(x != NULL);
for(int i = 0; i < n; i++){
x[i] = 1;
}
int *d_x, *d_y;
hipMalloc(&d_x, n * sizeof(int));
hipMalloc(&d_y, n * sizeof(int));
hipMemcpy(d_x, x, n * sizeof(float), hipMemcpyHostToDevice);
int block_count = n / block_size;
for(int i = 1, j = 0; i < n; i *= 2, j++){
prefix_scan<<<block_count, block_size>>>(n, i, d_x, d_y);
std::swap(d_x, d_y);
}
int *result = (int *) malloc(n * sizeof(int));
hipMemcpy(result, d_x, n * sizeof(int), hipMemcpyDeviceToHost);
// Test to make sure prefix scan is correct.
for(int i = 0; i < n; i++){
if(result[i] != i + 1){
std::cerr << i << ' ' << i + 1 << ' ' << result[i] << '\n';
return -1;
}
}
std::cout << "memory usage: " << n * sizeof(int) << " bytes" << std::endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11prefix_scaniiPiS_
.globl _Z11prefix_scaniiPiS_
.p2align 8
.type _Z11prefix_scaniiPiS_,@function
_Z11prefix_scaniiPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v2, s4, v2
s_mov_b32 s4, exec_lo
global_load_b32 v4, v[3:4], off
v_cmpx_lt_i32_e32 -1, v2
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v2, v4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11prefix_scaniiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11prefix_scaniiPiS_, .Lfunc_end0-_Z11prefix_scaniiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11prefix_scaniiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11prefix_scaniiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
#include <cassert>
#include <cmath>
#include <cstdlib>
#include <vector>
#include <algorithm>
#define BLOCKSIZE 128
// MUST BE ASSOCIATIVE
__device__ inline int f(int a, int b){
return a + b;
}
/**
* Implements prefix-scan using a Hillis-Steele algorithm.
* Since Hillis-Steele assumes as many concurrent processors as data lines, we need to use
* "double-buffering" to simulate concurrent modifications.
* Since this algorithm requires 2 DRAM accesses per thread, this is a slow algorithm.
* In my results, it's still faster than a CPU algorithm. GPUs are so cool :)
**/
__global__ void prefix_scan(const int n, const int jump, int* old, int* nnew){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(0 <= i - jump){
nnew[i] = f(old[i], old[i - jump]);
} else {
nnew[i] = old[i];
}
}
int main(){
const int n = (1 << 28);
const int block_size = BLOCKSIZE;
assert(n % block_size == 0);
int *x = (int *) malloc(n * sizeof(int));
assert(x != NULL);
for(int i = 0; i < n; i++){
x[i] = 1;
}
int *d_x, *d_y;
hipMalloc(&d_x, n * sizeof(int));
hipMalloc(&d_y, n * sizeof(int));
hipMemcpy(d_x, x, n * sizeof(float), hipMemcpyHostToDevice);
int block_count = n / block_size;
for(int i = 1, j = 0; i < n; i *= 2, j++){
prefix_scan<<<block_count, block_size>>>(n, i, d_x, d_y);
std::swap(d_x, d_y);
}
int *result = (int *) malloc(n * sizeof(int));
hipMemcpy(result, d_x, n * sizeof(int), hipMemcpyDeviceToHost);
// Test to make sure prefix scan is correct.
for(int i = 0; i < n; i++){
if(result[i] != i + 1){
std::cerr << i << ' ' << i + 1 << ' ' << result[i] << '\n';
return -1;
}
}
std::cout << "memory usage: " << n * sizeof(int) << " bytes" << std::endl;
} | .text
.file "naive_parallel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__prefix_scaniiPiS_ # -- Begin function _Z26__device_stub__prefix_scaniiPiS_
.p2align 4, 0x90
.type _Z26__device_stub__prefix_scaniiPiS_,@function
_Z26__device_stub__prefix_scaniiPiS_: # @_Z26__device_stub__prefix_scaniiPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11prefix_scaniiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__prefix_scaniiPiS_, .Lfunc_end0-_Z26__device_stub__prefix_scaniiPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2:
movabsq $4294967424, %rbx # imm = 0x100000080
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq 8(%rsp), %rdi
movl $1, %r12d
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 2097024(%rbx), %r14
leaq 80(%rsp), %r13
leaq 72(%rsp), %rbp
leaq 32(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
leal (%r12,%r12), %eax
cmpl $134217728, %r12d # imm = 0x8000000
movl %eax, %r12d
jae .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl $268435456, 28(%rsp) # imm = 0x10000000
movl %r12d, 24(%rsp)
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 32(%rsp)
leaq 24(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z11prefix_scaniiPiS_, %edi
movq %r15, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %esi
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
cmpq $268435456, %r15 # imm = 0x10000000
je .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl (%rbx,%r15,4), %eax
incq %r15
decq %rsi
cmpq %rax, %r15
je .LBB1_7
# %bb.10:
negq %rsi
cmpq $268435456, %rsi # imm = 0x10000000
setae %bpl
movl $_ZSt4cerr, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movb $32, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_12
# %bb.11:
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_13
.LBB1_8:
movb $1, %bpl
testb %bpl, %bpl
jne .LBB1_21
jmp .LBB1_26
.LBB1_12:
movq %rax, %r14
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
movq %r14, %rdi
.LBB1_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movl %r15d, %esi
callq _ZNSolsEi
movb $32, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_15
# %bb.14:
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_16
.LBB1_15:
movq %rax, %r14
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
movq %r14, %rdi
.LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit32
movl -4(%rbx,%r15,4), %esi
callq _ZNSolsEi
movb $10, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_18
# %bb.17:
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_19
.LBB1_18:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit35
movl $-1, %r14d
testb %bpl, %bpl
je .LBB1_26
.LBB1_21:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1073741824, %esi # imm = 0x40000000
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .LBB1_27
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_24
# %bb.23:
movzbl 67(%r15), %eax
jmp .LBB1_25
.LBB1_24:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_26:
movl %r14d, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prefix_scaniiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11prefix_scaniiPiS_,@object # @_Z11prefix_scaniiPiS_
.section .rodata,"a",@progbits
.globl _Z11prefix_scaniiPiS_
.p2align 3, 0x0
_Z11prefix_scaniiPiS_:
.quad _Z26__device_stub__prefix_scaniiPiS_
.size _Z11prefix_scaniiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "memory usage: "
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " bytes"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11prefix_scaniiPiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__prefix_scaniiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11prefix_scaniiPiS_
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11prefix_scaniiPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0205 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x164], PT ; /* 0x0000590000007a0c */
/* 0x000fc80003f06270 */
/*0080*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000eb2000c1e1900 */
/*0090*/ @P0 IADD3 R4, R0, -c[0x0][0x164], RZ ; /* 0x8000590000040a10 */
/* 0x000fca0007ffe0ff */
/*00a0*/ @P0 IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004040625 */
/* 0x000fcc00078e0205 */
/*00b0*/ @P0 LDG.E R4, [R4.64] ; /* 0x0000000404040981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ SHF.R.S32.HI R7, RZ, 0x1f, R0 ; /* 0x0000001fff077819 */
/* 0x000fe40000011400 */
/*00d0*/ LEA R6, P1, R0, c[0x0][0x170], 0x2 ; /* 0x00005c0000067a11 */
/* 0x000fc800078210ff */
/*00e0*/ LEA.HI.X R7, R0, c[0x0][0x174], R7, 0x2, P1 ; /* 0x00005d0000077a11 */
/* 0x000fe200008f1407 */
/*00f0*/ @P0 IMAD.IADD R9, R9, 0x1, R4 ; /* 0x0000000109090824 */
/* 0x004fca00078e0204 */
/*0100*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11prefix_scaniiPiS_
.globl _Z11prefix_scaniiPiS_
.p2align 8
.type _Z11prefix_scaniiPiS_,@function
_Z11prefix_scaniiPiS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
s_load_b32 s4, s[0:1], 0x4
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_add_co_u32 v3, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v1, vcc_lo
s_waitcnt lgkmcnt(0)
v_subrev_nc_u32_e32 v2, s4, v2
s_mov_b32 s4, exec_lo
global_load_b32 v4, v[3:4], off
v_cmpx_lt_i32_e32 -1, v2
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v2, v4
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11prefix_scaniiPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11prefix_scaniiPiS_, .Lfunc_end0-_Z11prefix_scaniiPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11prefix_scaniiPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11prefix_scaniiPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00138814_00000000-6_naive_parallel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4390:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4390:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_
.type _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_, @function
_Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_:
.LFB4412:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11prefix_scaniiPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4412:
.size _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_, .-_Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_
.globl _Z11prefix_scaniiPiS_
.type _Z11prefix_scaniiPiS_, @function
_Z11prefix_scaniiPiS_:
.LFB4413:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4413:
.size _Z11prefix_scaniiPiS_, .-_Z11prefix_scaniiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "memory usage: "
.LC1:
.string " bytes"
.text
.globl main
.type main, @function
main:
.LFB4386:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
leaq 1073741824(%rax), %rdx
.L12:
movl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rsp, %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $28, %ebx
movl $1, %ebp
jmp .L14
.L13:
movq (%rsp), %rax
movq 8(%rsp), %r12
movq %r12, (%rsp)
movq %rax, 8(%rsp)
addl %ebp, %ebp
subl $1, %ebx
je .L23
.L14:
movl $128, 28(%rsp)
movl $1, 32(%rsp)
movl $2097152, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movl %ebp, %esi
movl $268435456, %edi
call _Z35__device_stub__Z11prefix_scaniiPiS_iiPiS_
jmp .L13
.L23:
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $1073741824, %edx
movq %r12, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %rax
movl $0, %ebx
.L17:
movq %rax, %rbp
movl %ebx, %esi
addl $1, %ebx
addq $4, %rax
cmpl %ebx, 0(%rbp)
jne .L24
cmpl $268435456, %ebx
jne .L17
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $1073741824, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %eax
jmp .L11
.L24:
leaq _ZSt4cerr(%rip), %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $32, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
movl %ebx, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $32, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
movl 0(%rbp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $-1, %eax
.L11:
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L25
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4386:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z11prefix_scaniiPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4415:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11prefix_scaniiPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4415:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "naive_parallel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__prefix_scaniiPiS_ # -- Begin function _Z26__device_stub__prefix_scaniiPiS_
.p2align 4, 0x90
.type _Z26__device_stub__prefix_scaniiPiS_,@function
_Z26__device_stub__prefix_scaniiPiS_: # @_Z26__device_stub__prefix_scaniiPiS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11prefix_scaniiPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__prefix_scaniiPiS_, .Lfunc_end0-_Z26__device_stub__prefix_scaniiPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%r14,%rax,4)
incq %rax
cmpq $268435456, %rax # imm = 0x10000000
jne .LBB1_1
# %bb.2:
movabsq $4294967424, %rbx # imm = 0x100000080
leaq 8(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq 8(%rsp), %rdi
movl $1, %r12d
movl $1073741824, %edx # imm = 0x40000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 2097024(%rbx), %r14
leaq 80(%rsp), %r13
leaq 72(%rsp), %rbp
leaq 32(%rsp), %r15
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rcx, 8(%rsp)
movq %rax, 16(%rsp)
leal (%r12,%r12), %eax
cmpl $134217728, %r12d # imm = 0x8000000
movl %eax, %r12d
jae .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movl $268435456, 28(%rsp) # imm = 0x10000000
movl %r12d, 24(%rsp)
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 32(%rsp)
leaq 24(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z11prefix_scaniiPiS_, %edi
movq %r15, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %rbx
movq 8(%rsp), %rsi
movl $1073741824, %edx # imm = 0x40000000
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
movl $1, %esi
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_7: # =>This Inner Loop Header: Depth=1
cmpq $268435456, %r15 # imm = 0x10000000
je .LBB1_8
# %bb.9: # in Loop: Header=BB1_7 Depth=1
movl (%rbx,%r15,4), %eax
incq %r15
decq %rsi
cmpq %rax, %r15
je .LBB1_7
# %bb.10:
negq %rsi
cmpq $268435456, %rsi # imm = 0x10000000
setae %bpl
movl $_ZSt4cerr, %edi
# kill: def $esi killed $esi killed $rsi
callq _ZNSolsEi
movb $32, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_12
# %bb.11:
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_13
.LBB1_8:
movb $1, %bpl
testb %bpl, %bpl
jne .LBB1_21
jmp .LBB1_26
.LBB1_12:
movq %rax, %r14
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
movq %r14, %rdi
.LBB1_13: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movl %r15d, %esi
callq _ZNSolsEi
movb $32, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_15
# %bb.14:
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rdi
jmp .LBB1_16
.LBB1_15:
movq %rax, %r14
movq %rax, %rdi
movl $32, %esi
callq _ZNSo3putEc
movq %r14, %rdi
.LBB1_16: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit32
movl -4(%rbx,%r15,4), %esi
callq _ZNSolsEi
movb $10, 32(%rsp)
movq (%rax), %rcx
movq -24(%rcx), %rcx
cmpq $0, 16(%rax,%rcx)
je .LBB1_18
# %bb.17:
leaq 32(%rsp), %rsi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_19
.LBB1_18:
movq %rax, %rdi
movl $10, %esi
callq _ZNSo3putEc
.LBB1_19: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit35
movl $-1, %r14d
testb %bpl, %bpl
je .LBB1_26
.LBB1_21:
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $1073741824, %esi # imm = 0x40000000
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.1, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r15
testq %r15, %r15
je .LBB1_27
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_24
# %bb.23:
movzbl 67(%r15), %eax
jmp .LBB1_25
.LBB1_24:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
.LBB1_26:
movl %r14d, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_27:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11prefix_scaniiPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11prefix_scaniiPiS_,@object # @_Z11prefix_scaniiPiS_
.section .rodata,"a",@progbits
.globl _Z11prefix_scaniiPiS_
.p2align 3, 0x0
_Z11prefix_scaniiPiS_:
.quad _Z26__device_stub__prefix_scaniiPiS_
.size _Z11prefix_scaniiPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "memory usage: "
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " bytes"
.size .L.str.1, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11prefix_scaniiPiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__prefix_scaniiPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11prefix_scaniiPiS_
.addrsig_sym _ZSt4cerr
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void conv_kernel(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// X: [1, 256, 7, 7]
// batch x in_channel x feature_size x feature_size
// W: [128, 256, 5, 5]
// out_channel x in_channels x kernel_size x kernel_size
// Y: [1, 128, 7, 7]
// batch x out_channels x feature_size x feature_size
int batch, out;
__shared__ float shared_X[7][7];
__shared__ float shared_W[5][5];
// __shared__ float shared_Y[7][7];
batch = blockIdx.x;
out = blockIdx.y;
// int h_in, w_in;
int h_out, w_out;
h_out = threadIdx.x;
w_out = threadIdx.y;
// h_in = h_out - 2; //padding = 2
// w_in = w_out - 2;
float sum = 0.;
int X_idx, W_idx, Y_idx;
for (int in = 0; in < in_channels; in++)
{
// load W to shared memory
// just use h_out and w_out
if (h_out < kernel_size && w_out < kernel_size)
{
W_idx = out * in_channels * kernel_size * kernel_size +
in * kernel_size * kernel_size +
h_out * kernel_size + w_out;
shared_W[h_out][w_out] = W[W_idx];
}
__syncthreads();
// load X to shared memory
if ((h_out < feature_size) && (h_out >= 0) && (w_out < feature_size) && (w_out >= 0))
{
X_idx = batch * 255 * 7 * 7 +
in * 7 * 7 +
h_out * 7 + w_out;
shared_X[h_out][w_out] = X[X_idx];
}
__syncthreads();
for (int p = 0; p < kernel_size; p++)
{
for (int q = 0; q < kernel_size; q++)
{
// have problem boundary check
int h_idx = h_out - 2 + p;
int w_idx = w_out - 2 + q;
if (h_idx >= 0 && h_idx < feature_size &&
w_idx >= 0 && w_idx < feature_size)
{
sum += shared_X[h_idx][w_idx] * shared_W[p][q];
}
}
}
__syncthreads();
}
Y_idx = batch * out_channels * feature_size * feature_size +
out * feature_size * feature_size +
h_out * feature_size + w_out;
Y[Y_idx] = sum;
}
void launch_conv(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// for blocksize x,y for output size of feature map
// since in this task, each feature map is small,
// just set a const value?
dim3 blockSize(7, 7, 1);
// gridsize is for in channels and out channels
dim3 gridSize(batch_size, out_channels, 1);
conv_kernel<<<gridSize, blockSize>>>(Y,
X,
W,
in_channels,
out_channels,
kernel_size,
feature_size,
batch_size);
} | code for sm_80
Function : _Z11conv_kernelPfPKfS1_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e640000002600 */
/*0050*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0070*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000ea80000002100 */
/*0080*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000eee0000002200 */
/*0090*/ @!P0 BRA 0x8f0 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.AND P0, PT, R6.reuse, c[0x0][0x184], PT ; /* 0x0000610006007a0c */
/* 0x044fe20003f06270 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0b7624 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.AND P2, PT, R7.reuse, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x048fe20003f46270 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x14 ; /* 0x00000014ff037424 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6.reuse, -0x1, !P0 ; /* 0xffffffff0600780c */
/* 0x040fe20004704270 */
/*00f0*/ IMAD.SHL.U32 R15, R7, 0x4, RZ ; /* 0x00000004070f7824 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R0, R11, -0x1, RZ ; /* 0xffffffff0b007810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R14, R6, R3, 0xc4 ; /* 0x000000c4060e7424 */
/* 0x000fe200078e0203 */
/*0120*/ ISETP.LT.AND P1, PT, R7, c[0x0][0x184], P0 ; /* 0x0000610007007a0c */
/* 0x000fe20000721270 */
/*0130*/ IMAD R17, R4, 0x30cf, R7 ; /* 0x000030cf04117824 */
/* 0x001fe200078e0207 */
/*0140*/ LOP3.LUT R11, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b0b7812 */
/* 0x000fe200078ec0ff */
/*0150*/ IMAD R13, R6, 0x1c, R15.reuse ; /* 0x0000001c060d7824 */
/* 0x100fe200078e020f */
/*0160*/ ISETP.GE.U32.AND P4, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f86070 */
/*0170*/ IMAD.IADD R14, R14, 0x1, R15 ; /* 0x000000010e0e7824 */
/* 0x000fe200078e020f */
/*0180*/ IADD3 R8, R6.reuse, -0x2, RZ ; /* 0xfffffffe06087810 */
/* 0x040fe20007ffe0ff */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R9, R7.reuse, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x040fe20007ffe0ff */
/*01b0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R10, R7, -0x2, RZ ; /* 0xfffffffe070a7810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD R17, R6.reuse, 0x7, R17 ; /* 0x0000000706117824 */
/* 0x040fe200078e0211 */
/*01e0*/ ISETP.LT.AND P0, PT, R6, c[0x0][0x180], !P2 ; /* 0x0000600006007a0c */
/* 0x000fc40005701270 */
/*01f0*/ ISETP.GT.AND P1, PT, R7, -0x1, P1 ; /* 0xffffffff0700780c */
/* 0x000fe40000f24270 */
/*0200*/ IADD3 R15, R15, -0x40, RZ ; /* 0xffffffc00f0f7810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R16, R11, -c[0x0][0x180], RZ ; /* 0x800060000b107a10 */
/* 0x000fcc0007ffe0ff */
/*0220*/ BSSY B0, 0x2c0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0230*/ @!P0 BRA 0x2b0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD R3, R5, c[0x0][0x178], R12 ; /* 0x00005e0005037a24 */
/* 0x002fc800078e020c */
/*0250*/ IMAD R2, R3, c[0x0][0x180], R6 ; /* 0x0000600003027a24 */
/* 0x000fe400078e0206 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD R2, R2, c[0x0][0x180], R7 ; /* 0x0000600002027a24 */
/* 0x000fc800078e0207 */
/*0280*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fcc00078e0203 */
/*0290*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ STS [R14], R3 ; /* 0x000000030e007388 */
/* 0x0041e40000000800 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ BSSY B0, 0x350 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*02e0*/ @!P1 BRA 0x340 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe400078e00ff */
/*0300*/ IMAD R2, R12, 0x31, R17 ; /* 0x000000310c027824 */
/* 0x000fc800078e0211 */
/*0310*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0320*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0330*/ STS [R13], R2 ; /* 0x000000020d007388 */
/* 0x0041e40000000800 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x001fe200078e00ff */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0370*/ ISETP.GE.AND P2, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f46270 */
/*0380*/ @!P2 BRA 0x8b0 ; /* 0x000005200000a947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*03a0*/ ISETP.NE.AND P5, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003fa5270 */
/*03b0*/ IMAD.IADD R2, R8, 0x1, R3 ; /* 0x0000000108027824 */
/* 0x000fe400078e0203 */
/*03c0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*03d0*/ @!P4 BRA 0x680 ; /* 0x000002a00000c947 */
/* 0x000ff20003800000 */
/*03e0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x14 ; /* 0x00000014ff147424 */
/* 0x000fe200078e00ff */
/*03f0*/ ISETP.GE.AND P6, PT, R2, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x000fe20003fc6270 */
/*0400*/ IMAD.IADD R18, R6, 0x1, R3 ; /* 0x0000000106127824 */
/* 0x000fe400078e0203 */
/*0410*/ IMAD R20, R3, R20, 0xc4 ; /* 0x000000c403147424 */
/* 0x000fe400078e0214 */
/*0420*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc400078e00ff */
/*0430*/ IMAD.MOV.U32 R21, RZ, RZ, R9 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0009 */
/*0440*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe20007ffe0ff */
/*0450*/ IMAD R18, R18, 0x1c, R15 ; /* 0x0000001c12127824 */
/* 0x000fc600078e020f */
/*0460*/ IADD3 R23, R21.reuse, -0x3, RZ ; /* 0xfffffffd15177810 */
/* 0x040fe40007ffe0ff */
/*0470*/ IADD3 R25, R21, -0x2, RZ ; /* 0xfffffffe15197810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LOP3.LUT R22, R23, R2, RZ, 0xfc, !PT ; /* 0x0000000217167212 */
/* 0x000fe400078efcff */
/*0490*/ IADD3 R27, R21, -0x1, RZ ; /* 0xffffffff151b7810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.LT.OR P3, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fc40003761670 */
/*04b0*/ LOP3.LUT R22, R25, R2, RZ, 0xfc, !PT ; /* 0x0000000219167212 */
/* 0x000fe400078efcff */
/*04c0*/ ISETP.GE.OR P3, PT, R23, c[0x0][0x184], P3 ; /* 0x0000610017007a0c */
/* 0x000fe40001f66670 */
/*04d0*/ ISETP.LT.OR P2, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fe40003741670 */
/*04e0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ ISETP.GE.OR P2, PT, R25, c[0x0][0x184], P2 ; /* 0x0000610019007a0c */
/* 0x000fc60001746670 */
/*0500*/ IMAD.IADD R26, R16, 0x1, R19 ; /* 0x00000001101a7824 */
/* 0x000fc800078e0213 */
/*0510*/ @!P3 LDS R23, [R20+-0x8] ; /* 0xfffff8001417b984 */
/* 0x000fe80000000800 */
/*0520*/ @!P3 LDS R22, [R18] ; /* 0x000000001216b984 */
/* 0x000e280000000800 */
/*0530*/ @!P2 LDS R25, [R20+-0x4] ; /* 0xfffffc001419a984 */
/* 0x000fe80000000800 */
/*0540*/ @!P2 LDS R24, [R18+0x4] ; /* 0x000004001218a984 */
/* 0x000ea20000000800 */
/*0550*/ @!P3 FFMA R0, R23, R22, R0 ; /* 0x000000161700b223 */
/* 0x001fe20000000000 */
/*0560*/ LOP3.LUT R22, R27, R2, RZ, 0xfc, !PT ; /* 0x000000021b167212 */
/* 0x000fc800078efcff */
/*0570*/ ISETP.LT.OR P3, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fe40003761670 */
/*0580*/ LOP3.LUT R22, R21, R2, RZ, 0xfc, !PT ; /* 0x0000000215167212 */
/* 0x000fe200078efcff */
/*0590*/ @!P2 FFMA R0, R25, R24, R0 ; /* 0x000000181900a223 */
/* 0x004fe20000000000 */
/*05a0*/ ISETP.GE.OR P3, PT, R27, c[0x0][0x184], P3 ; /* 0x000061001b007a0c */
/* 0x000fe40001f66670 */
/*05b0*/ ISETP.LT.OR P2, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fc80003741670 */
/*05c0*/ ISETP.GE.OR P2, PT, R21.reuse, c[0x0][0x184], P2 ; /* 0x0000610015007a0c */
/* 0x040fe40001746670 */
/*05d0*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fca0007ffe0ff */
/*05e0*/ @!P3 LDS R23, [R20] ; /* 0x000000001417b984 */
/* 0x000fe80000000800 */
/*05f0*/ @!P3 LDS R22, [R18+0x8] ; /* 0x000008001216b984 */
/* 0x000e280000000800 */
/*0600*/ @!P2 LDS R25, [R20+0x4] ; /* 0x000004001419a984 */
/* 0x0005e80000000800 */
/*0610*/ @!P2 LDS R24, [R18+0xc] ; /* 0x00000c001218a984 */
/* 0x0007220000000800 */
/*0620*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x004fc40007ffe0ff */
/*0630*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x008fe20007ffe0ff */
/*0640*/ @!P3 FFMA R0, R23, R22, R0 ; /* 0x000000161700b223 */
/* 0x001fe20000000000 */
/*0650*/ ISETP.NE.AND P3, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fc60003f65270 */
/*0660*/ @!P2 FFMA R0, R25, R24, R0 ; /* 0x000000181900a223 */
/* 0x010fd40000000000 */
/*0670*/ @P3 BRA 0x460 ; /* 0xfffffde000003947 */
/* 0x000fea000383ffff */
/*0680*/ @!P5 BRA 0x880 ; /* 0x000001f00000d947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.IADD R23, R10, 0x1, R19 ; /* 0x000000010a177824 */
/* 0x000fe200078e0213 */
/*06a0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x000fe20003f46270 */
/*06b0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x14 ; /* 0x00000014ff147424 */
/* 0x000fe200078e00ff */
/*06c0*/ ISETP.NE.AND P5, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe40003fa5270 */
/*06d0*/ LOP3.LUT R18, R23, R2, RZ, 0xfc, !PT ; /* 0x0000000217127212 */
/* 0x000fe200078efcff */
/*06e0*/ IMAD R20, R3, R20, 0xc4 ; /* 0x000000c403147424 */
/* 0x000fc600078e0214 */
/*06f0*/ ISETP.LT.OR P3, PT, R18, RZ, P2 ; /* 0x000000ff1200720c */
/* 0x000fe20001761670 */
/*0700*/ IMAD R18, R2, 0x7, R23 ; /* 0x0000000702127824 */
/* 0x000fe400078e0217 */
/*0710*/ IMAD R22, R19, 0x4, R20 ; /* 0x0000000413167824 */
/* 0x000fe200078e0214 */
/*0720*/ ISETP.GE.OR P3, PT, R23, c[0x0][0x184], P3 ; /* 0x0000610017007a0c */
/* 0x000fe20001f66670 */
/*0730*/ IMAD.SHL.U32 R18, R18, 0x4, RZ ; /* 0x0000000412127824 */
/* 0x000fd800078e00ff */
/*0740*/ @!P3 LDS R21, [R18] ; /* 0x000000001215b984 */
/* 0x000fe80000000800 */
/*0750*/ @!P3 LDS R20, [R22] ; /* 0x000000001614b984 */
/* 0x000e240000000800 */
/*0760*/ @!P3 FFMA R0, R21, R20, R0 ; /* 0x000000141500b223 */
/* 0x001fe20000000000 */
/*0770*/ @!P5 BRA 0x880 ; /* 0x000001000000d947 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R21, R23, 0x1, RZ ; /* 0x0000000117157810 */
/* 0x000fe40007ffe0ff */
/*0790*/ ISETP.NE.AND P5, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe40003fa5270 */
/*07a0*/ LOP3.LUT R20, R21, R2, RZ, 0xfc, !PT ; /* 0x0000000215147212 */
/* 0x000fc800078efcff */
/*07b0*/ ISETP.LT.OR P3, PT, R20, RZ, P2 ; /* 0x000000ff1400720c */
/* 0x000fc80001761670 */
/*07c0*/ ISETP.GE.OR P3, PT, R21, c[0x0][0x184], P3 ; /* 0x0000610015007a0c */
/* 0x000fda0001f66670 */
/*07d0*/ @!P3 LDS R21, [R22+0x4] ; /* 0x000004001615b984 */
/* 0x000fe80000000800 */
/*07e0*/ @!P3 LDS R20, [R18+0x4] ; /* 0x000004001214b984 */
/* 0x000e240000000800 */
/*07f0*/ @!P3 FFMA R0, R21, R20, R0 ; /* 0x000000141500b223 */
/* 0x001fe20000000000 */
/*0800*/ @!P5 BRA 0x880 ; /* 0x000000700000d947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.IADD R19, R7, 0x1, R19 ; /* 0x0000000107137824 */
/* 0x000fca00078e0213 */
/*0820*/ LOP3.LUT R2, R19, R2, RZ, 0xfc, !PT ; /* 0x0000000213027212 */
/* 0x000fc800078efcff */
/*0830*/ ISETP.LT.OR P2, PT, R2, RZ, P2 ; /* 0x000000ff0200720c */
/* 0x000fc80001741670 */
/*0840*/ ISETP.GE.OR P2, PT, R19, c[0x0][0x184], P2 ; /* 0x0000610013007a0c */
/* 0x000fda0001746670 */
/*0850*/ @!P2 LDS R19, [R22+0x8] ; /* 0x000008001613a984 */
/* 0x000fe80000000800 */
/*0860*/ @!P2 LDS R18, [R18+0x8] ; /* 0x000008001212a984 */
/* 0x000e240000000800 */
/*0870*/ @!P2 FFMA R0, R19, R18, R0 ; /* 0x000000121300a223 */
/* 0x001fe40000000000 */
/*0880*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0890*/ ISETP.GE.AND P2, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fda0003f46270 */
/*08a0*/ @!P2 BRA 0x3a0 ; /* 0xfffffaf00000a947 */
/* 0x000fea000383ffff */
/*08b0*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*08d0*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x000fda0003f46270 */
/*08e0*/ @!P2 BRA 0x220 ; /* 0xfffff9300000a947 */
/* 0x000fea000383ffff */
/*08f0*/ IMAD R5, R4, c[0x0][0x17c], R5 ; /* 0x00005f0004057a24 */
/* 0x003fe400078e0205 */
/*0900*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0910*/ IMAD R6, R5, c[0x0][0x184], R6 ; /* 0x0000610005067a24 */
/* 0x004fc800078e0206 */
/*0920*/ IMAD R2, R6, c[0x0][0x184], R7 ; /* 0x0000610006027a24 */
/* 0x008fc800078e0207 */
/*0930*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0940*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*0950*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0960*/ BRA 0x960; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void conv_kernel(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// X: [1, 256, 7, 7]
// batch x in_channel x feature_size x feature_size
// W: [128, 256, 5, 5]
// out_channel x in_channels x kernel_size x kernel_size
// Y: [1, 128, 7, 7]
// batch x out_channels x feature_size x feature_size
int batch, out;
__shared__ float shared_X[7][7];
__shared__ float shared_W[5][5];
// __shared__ float shared_Y[7][7];
batch = blockIdx.x;
out = blockIdx.y;
// int h_in, w_in;
int h_out, w_out;
h_out = threadIdx.x;
w_out = threadIdx.y;
// h_in = h_out - 2; //padding = 2
// w_in = w_out - 2;
float sum = 0.;
int X_idx, W_idx, Y_idx;
for (int in = 0; in < in_channels; in++)
{
// load W to shared memory
// just use h_out and w_out
if (h_out < kernel_size && w_out < kernel_size)
{
W_idx = out * in_channels * kernel_size * kernel_size +
in * kernel_size * kernel_size +
h_out * kernel_size + w_out;
shared_W[h_out][w_out] = W[W_idx];
}
__syncthreads();
// load X to shared memory
if ((h_out < feature_size) && (h_out >= 0) && (w_out < feature_size) && (w_out >= 0))
{
X_idx = batch * 255 * 7 * 7 +
in * 7 * 7 +
h_out * 7 + w_out;
shared_X[h_out][w_out] = X[X_idx];
}
__syncthreads();
for (int p = 0; p < kernel_size; p++)
{
for (int q = 0; q < kernel_size; q++)
{
// have problem boundary check
int h_idx = h_out - 2 + p;
int w_idx = w_out - 2 + q;
if (h_idx >= 0 && h_idx < feature_size &&
w_idx >= 0 && w_idx < feature_size)
{
sum += shared_X[h_idx][w_idx] * shared_W[p][q];
}
}
}
__syncthreads();
}
Y_idx = batch * out_channels * feature_size * feature_size +
out * feature_size * feature_size +
h_out * feature_size + w_out;
Y[Y_idx] = sum;
}
void launch_conv(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// for blocksize x,y for output size of feature map
// since in this task, each feature map is small,
// just set a const value?
dim3 blockSize(7, 7, 1);
// gridsize is for in channels and out channels
dim3 gridSize(batch_size, out_channels, 1);
conv_kernel<<<gridSize, blockSize>>>(Y,
X,
W,
in_channels,
out_channels,
kernel_size,
feature_size,
batch_size);
} | .file "tmpxft_0011afde_00000000-6_conv_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii
.type _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii, @function
_Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11conv_kernelPfPKfS1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii, .-_Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii
.globl _Z11conv_kernelPfPKfS1_iiiii
.type _Z11conv_kernelPfPKfS1_iiiii, @function
_Z11conv_kernelPfPKfS1_iiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z11conv_kernelPfPKfS1_iiiii, .-_Z11conv_kernelPfPKfS1_iiiii
.globl _Z11launch_convPfPKfS1_iiiii
.type _Z11launch_convPfPKfS1_iiiii, @function
_Z11launch_convPfPKfS1_iiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r15
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
movl %r8d, %ebx
movl %r9d, %r14d
movl $7, 8(%rsp)
movl $7, 12(%rsp)
movl 104(%rsp), %eax
movl %eax, 20(%rsp)
movl %r8d, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl %r14d, %r9d
movl %ebx, %r8d
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %r15, %rdi
call _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11launch_convPfPKfS1_iiiii, .-_Z11launch_convPfPKfS1_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11conv_kernelPfPKfS1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11conv_kernelPfPKfS1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void conv_kernel(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// X: [1, 256, 7, 7]
// batch x in_channel x feature_size x feature_size
// W: [128, 256, 5, 5]
// out_channel x in_channels x kernel_size x kernel_size
// Y: [1, 128, 7, 7]
// batch x out_channels x feature_size x feature_size
int batch, out;
__shared__ float shared_X[7][7];
__shared__ float shared_W[5][5];
// __shared__ float shared_Y[7][7];
batch = blockIdx.x;
out = blockIdx.y;
// int h_in, w_in;
int h_out, w_out;
h_out = threadIdx.x;
w_out = threadIdx.y;
// h_in = h_out - 2; //padding = 2
// w_in = w_out - 2;
float sum = 0.;
int X_idx, W_idx, Y_idx;
for (int in = 0; in < in_channels; in++)
{
// load W to shared memory
// just use h_out and w_out
if (h_out < kernel_size && w_out < kernel_size)
{
W_idx = out * in_channels * kernel_size * kernel_size +
in * kernel_size * kernel_size +
h_out * kernel_size + w_out;
shared_W[h_out][w_out] = W[W_idx];
}
__syncthreads();
// load X to shared memory
if ((h_out < feature_size) && (h_out >= 0) && (w_out < feature_size) && (w_out >= 0))
{
X_idx = batch * 255 * 7 * 7 +
in * 7 * 7 +
h_out * 7 + w_out;
shared_X[h_out][w_out] = X[X_idx];
}
__syncthreads();
for (int p = 0; p < kernel_size; p++)
{
for (int q = 0; q < kernel_size; q++)
{
// have problem boundary check
int h_idx = h_out - 2 + p;
int w_idx = w_out - 2 + q;
if (h_idx >= 0 && h_idx < feature_size &&
w_idx >= 0 && w_idx < feature_size)
{
sum += shared_X[h_idx][w_idx] * shared_W[p][q];
}
}
}
__syncthreads();
}
Y_idx = batch * out_channels * feature_size * feature_size +
out * feature_size * feature_size +
h_out * feature_size + w_out;
Y[Y_idx] = sum;
}
void launch_conv(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// for blocksize x,y for output size of feature map
// since in this task, each feature map is small,
// just set a const value?
dim3 blockSize(7, 7, 1);
// gridsize is for in channels and out channels
dim3 gridSize(batch_size, out_channels, 1);
conv_kernel<<<gridSize, blockSize>>>(Y,
X,
W,
in_channels,
out_channels,
kernel_size,
feature_size,
batch_size);
} | #include <hip/hip_runtime.h>
__global__ void conv_kernel(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// X: [1, 256, 7, 7]
// batch x in_channel x feature_size x feature_size
// W: [128, 256, 5, 5]
// out_channel x in_channels x kernel_size x kernel_size
// Y: [1, 128, 7, 7]
// batch x out_channels x feature_size x feature_size
int batch, out;
__shared__ float shared_X[7][7];
__shared__ float shared_W[5][5];
// __shared__ float shared_Y[7][7];
batch = blockIdx.x;
out = blockIdx.y;
// int h_in, w_in;
int h_out, w_out;
h_out = threadIdx.x;
w_out = threadIdx.y;
// h_in = h_out - 2; //padding = 2
// w_in = w_out - 2;
float sum = 0.;
int X_idx, W_idx, Y_idx;
for (int in = 0; in < in_channels; in++)
{
// load W to shared memory
// just use h_out and w_out
if (h_out < kernel_size && w_out < kernel_size)
{
W_idx = out * in_channels * kernel_size * kernel_size +
in * kernel_size * kernel_size +
h_out * kernel_size + w_out;
shared_W[h_out][w_out] = W[W_idx];
}
__syncthreads();
// load X to shared memory
if ((h_out < feature_size) && (h_out >= 0) && (w_out < feature_size) && (w_out >= 0))
{
X_idx = batch * 255 * 7 * 7 +
in * 7 * 7 +
h_out * 7 + w_out;
shared_X[h_out][w_out] = X[X_idx];
}
__syncthreads();
for (int p = 0; p < kernel_size; p++)
{
for (int q = 0; q < kernel_size; q++)
{
// have problem boundary check
int h_idx = h_out - 2 + p;
int w_idx = w_out - 2 + q;
if (h_idx >= 0 && h_idx < feature_size &&
w_idx >= 0 && w_idx < feature_size)
{
sum += shared_X[h_idx][w_idx] * shared_W[p][q];
}
}
}
__syncthreads();
}
Y_idx = batch * out_channels * feature_size * feature_size +
out * feature_size * feature_size +
h_out * feature_size + w_out;
Y[Y_idx] = sum;
}
void launch_conv(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// for blocksize x,y for output size of feature map
// since in this task, each feature map is small,
// just set a const value?
dim3 blockSize(7, 7, 1);
// gridsize is for in channels and out channels
dim3 gridSize(batch_size, out_channels, 1);
conv_kernel<<<gridSize, blockSize>>>(Y,
X,
W,
in_channels,
out_channels,
kernel_size,
feature_size,
batch_size);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void conv_kernel(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// X: [1, 256, 7, 7]
// batch x in_channel x feature_size x feature_size
// W: [128, 256, 5, 5]
// out_channel x in_channels x kernel_size x kernel_size
// Y: [1, 128, 7, 7]
// batch x out_channels x feature_size x feature_size
int batch, out;
__shared__ float shared_X[7][7];
__shared__ float shared_W[5][5];
// __shared__ float shared_Y[7][7];
batch = blockIdx.x;
out = blockIdx.y;
// int h_in, w_in;
int h_out, w_out;
h_out = threadIdx.x;
w_out = threadIdx.y;
// h_in = h_out - 2; //padding = 2
// w_in = w_out - 2;
float sum = 0.;
int X_idx, W_idx, Y_idx;
for (int in = 0; in < in_channels; in++)
{
// load W to shared memory
// just use h_out and w_out
if (h_out < kernel_size && w_out < kernel_size)
{
W_idx = out * in_channels * kernel_size * kernel_size +
in * kernel_size * kernel_size +
h_out * kernel_size + w_out;
shared_W[h_out][w_out] = W[W_idx];
}
__syncthreads();
// load X to shared memory
if ((h_out < feature_size) && (h_out >= 0) && (w_out < feature_size) && (w_out >= 0))
{
X_idx = batch * 255 * 7 * 7 +
in * 7 * 7 +
h_out * 7 + w_out;
shared_X[h_out][w_out] = X[X_idx];
}
__syncthreads();
for (int p = 0; p < kernel_size; p++)
{
for (int q = 0; q < kernel_size; q++)
{
// have problem boundary check
int h_idx = h_out - 2 + p;
int w_idx = w_out - 2 + q;
if (h_idx >= 0 && h_idx < feature_size &&
w_idx >= 0 && w_idx < feature_size)
{
sum += shared_X[h_idx][w_idx] * shared_W[p][q];
}
}
}
__syncthreads();
}
Y_idx = batch * out_channels * feature_size * feature_size +
out * feature_size * feature_size +
h_out * feature_size + w_out;
Y[Y_idx] = sum;
}
void launch_conv(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// for blocksize x,y for output size of feature map
// since in this task, each feature map is small,
// just set a const value?
dim3 blockSize(7, 7, 1);
// gridsize is for in channels and out channels
dim3 gridSize(batch_size, out_channels, 1);
conv_kernel<<<gridSize, blockSize>>>(Y,
X,
W,
in_channels,
out_channels,
kernel_size,
feature_size,
batch_size);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11conv_kernelPfPKfS1_iiiii
.globl _Z11conv_kernelPfPKfS1_iiiii
.p2align 8
.type _Z11conv_kernelPfPKfS1_iiiii,@function
_Z11conv_kernelPfPKfS1_iiiii:
s_clause 0x1
s_load_b32 s12, s[0:1], 0x18
s_load_b32 s7, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_16
s_clause 0x1
s_load_b32 s13, s[0:1], 0x20
s_load_b128 s[8:11], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_max_i32_e32 v9, v1, v0
v_mul_u32_u24_e32 v7, 20, v1
v_mul_u32_u24_e32 v8, 7, v1
s_delay_alu instid0(VALU_DEP_4)
v_mad_u32_u24 v6, v1, 28, v2
s_mul_i32 s3, s14, 0x30cf
v_add_nc_u32_e32 v4, -2, v1
v_add_nc_u32_e32 v5, -2, v0
v_add3_u32 v7, v7, v2, 0xd0
v_cmp_gt_i32_e64 s2, s7, v9
v_add3_u32 v2, s3, v0, v8
v_subrev_nc_u32_e32 v8, 64, v6
s_mul_i32 s17, s15, s12
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s3, s13, v9
s_cmp_gt_i32 s13, 0
s_cselect_b32 s16, -1, 0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_add_i32 s18, s18, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, s12
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_17
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_5
s_add_i32 s5, s18, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, s5, s13, v[1:2]
v_mad_u64_u32 v[10:11], null, v9, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[9:10], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_7
v_mad_u64_u32 v[9:10], null, s18, 49, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v6, v9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_2
v_mov_b32_e32 v9, v8
s_mov_b32 s19, 0
s_movk_i32 s20, 0xd0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
v_add_nc_u32_e32 v9, 28, v9
s_add_i32 s19, s19, 1
s_add_i32 s20, s20, 20
s_cmp_eq_u32 s19, s13
s_cbranch_scc1 .LBB0_2
.LBB0_10:
v_add_nc_u32_e32 v10, s19, v4
s_mov_b32 s21, s20
s_mov_b32 s22, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v10
v_cmp_gt_i32_e64 s4, s7, v10
v_mov_b32_e32 v10, v9
s_branch .LBB0_13
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s23
v_add_nc_u32_e32 v10, 4, v10
s_add_i32 s22, s22, 1
s_add_i32 s21, s21, 4
s_cmp_eq_u32 s13, s22
s_cbranch_scc1 .LBB0_9
.LBB0_13:
s_and_saveexec_b32 s23, vcc_lo
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v11, s22, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s5, -1, v11
v_cmp_gt_i32_e64 s6, s7, v11
s_and_b32 s5, s4, s5
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s6
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v11, s21
ds_load_b32 v12, v10
ds_load_b32 v11, v11
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v12, v11
s_branch .LBB0_11
.LBB0_16:
v_mov_b32_e32 v3, 0
.LBB0_17:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s14, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
v_mad_u64_u32 v[4:5], null, s2, s7, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s7, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11conv_kernelPfPKfS1_iiiii
.amdhsa_group_segment_fixed_size 308
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11conv_kernelPfPKfS1_iiiii, .Lfunc_end0-_Z11conv_kernelPfPKfS1_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 308
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11conv_kernelPfPKfS1_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z11conv_kernelPfPKfS1_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void conv_kernel(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// X: [1, 256, 7, 7]
// batch x in_channel x feature_size x feature_size
// W: [128, 256, 5, 5]
// out_channel x in_channels x kernel_size x kernel_size
// Y: [1, 128, 7, 7]
// batch x out_channels x feature_size x feature_size
int batch, out;
__shared__ float shared_X[7][7];
__shared__ float shared_W[5][5];
// __shared__ float shared_Y[7][7];
batch = blockIdx.x;
out = blockIdx.y;
// int h_in, w_in;
int h_out, w_out;
h_out = threadIdx.x;
w_out = threadIdx.y;
// h_in = h_out - 2; //padding = 2
// w_in = w_out - 2;
float sum = 0.;
int X_idx, W_idx, Y_idx;
for (int in = 0; in < in_channels; in++)
{
// load W to shared memory
// just use h_out and w_out
if (h_out < kernel_size && w_out < kernel_size)
{
W_idx = out * in_channels * kernel_size * kernel_size +
in * kernel_size * kernel_size +
h_out * kernel_size + w_out;
shared_W[h_out][w_out] = W[W_idx];
}
__syncthreads();
// load X to shared memory
if ((h_out < feature_size) && (h_out >= 0) && (w_out < feature_size) && (w_out >= 0))
{
X_idx = batch * 255 * 7 * 7 +
in * 7 * 7 +
h_out * 7 + w_out;
shared_X[h_out][w_out] = X[X_idx];
}
__syncthreads();
for (int p = 0; p < kernel_size; p++)
{
for (int q = 0; q < kernel_size; q++)
{
// have problem boundary check
int h_idx = h_out - 2 + p;
int w_idx = w_out - 2 + q;
if (h_idx >= 0 && h_idx < feature_size &&
w_idx >= 0 && w_idx < feature_size)
{
sum += shared_X[h_idx][w_idx] * shared_W[p][q];
}
}
}
__syncthreads();
}
Y_idx = batch * out_channels * feature_size * feature_size +
out * feature_size * feature_size +
h_out * feature_size + w_out;
Y[Y_idx] = sum;
}
void launch_conv(float *Y,
const float *X,
const float *W,
int in_channels,
int out_channels,
int kernel_size,
int feature_size,
int batch_size)
{
// for blocksize x,y for output size of feature map
// since in this task, each feature map is small,
// just set a const value?
dim3 blockSize(7, 7, 1);
// gridsize is for in channels and out channels
dim3 gridSize(batch_size, out_channels, 1);
conv_kernel<<<gridSize, blockSize>>>(Y,
X,
W,
in_channels,
out_channels,
kernel_size,
feature_size,
batch_size);
} | .text
.file "conv_kernel.hip"
.globl _Z26__device_stub__conv_kernelPfPKfS1_iiiii # -- Begin function _Z26__device_stub__conv_kernelPfPKfS1_iiiii
.p2align 4, 0x90
.type _Z26__device_stub__conv_kernelPfPKfS1_iiiii,@function
_Z26__device_stub__conv_kernelPfPKfS1_iiiii: # @_Z26__device_stub__conv_kernelPfPKfS1_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11conv_kernelPfPKfS1_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z26__device_stub__conv_kernelPfPKfS1_iiiii, .Lfunc_end0-_Z26__device_stub__conv_kernelPfPKfS1_iiiii
.cfi_endproc
# -- End function
.globl _Z11launch_convPfPKfS1_iiiii # -- Begin function _Z11launch_convPfPKfS1_iiiii
.p2align 4, 0x90
.type _Z11launch_convPfPKfS1_iiiii,@function
_Z11launch_convPfPKfS1_iiiii: # @_Z11launch_convPfPKfS1_iiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r14d
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movl 232(%rsp), %eax
movq %r14, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $30064771079, %rdx # imm = 0x700000007
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl 224(%rsp), %eax
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movq %r15, 72(%rsp)
movl %ebp, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebx, 12(%rsp)
movl %eax, 8(%rsp)
movl 232(%rsp), %eax
movl %eax, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11conv_kernelPfPKfS1_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11launch_convPfPKfS1_iiiii, .Lfunc_end1-_Z11launch_convPfPKfS1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11conv_kernelPfPKfS1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11conv_kernelPfPKfS1_iiiii,@object # @_Z11conv_kernelPfPKfS1_iiiii
.section .rodata,"a",@progbits
.globl _Z11conv_kernelPfPKfS1_iiiii
.p2align 3, 0x0
_Z11conv_kernelPfPKfS1_iiiii:
.quad _Z26__device_stub__conv_kernelPfPKfS1_iiiii
.size _Z11conv_kernelPfPKfS1_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11conv_kernelPfPKfS1_iiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__conv_kernelPfPKfS1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11conv_kernelPfPKfS1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11conv_kernelPfPKfS1_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e640000002600 */
/*0050*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0070*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000ea80000002100 */
/*0080*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000eee0000002200 */
/*0090*/ @!P0 BRA 0x8f0 ; /* 0x0000085000008947 */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.GE.AND P0, PT, R6.reuse, c[0x0][0x184], PT ; /* 0x0000610006007a0c */
/* 0x044fe20003f06270 */
/*00b0*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff0b7624 */
/* 0x000fe200078e00ff */
/*00c0*/ ISETP.GE.AND P2, PT, R7.reuse, c[0x0][0x180], PT ; /* 0x0000600007007a0c */
/* 0x048fe20003f46270 */
/*00d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x14 ; /* 0x00000014ff037424 */
/* 0x000fe200078e00ff */
/*00e0*/ ISETP.GT.AND P0, PT, R6.reuse, -0x1, !P0 ; /* 0xffffffff0600780c */
/* 0x040fe20004704270 */
/*00f0*/ IMAD.SHL.U32 R15, R7, 0x4, RZ ; /* 0x00000004070f7824 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R0, R11, -0x1, RZ ; /* 0xffffffff0b007810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD R14, R6, R3, 0xc4 ; /* 0x000000c4060e7424 */
/* 0x000fe200078e0203 */
/*0120*/ ISETP.LT.AND P1, PT, R7, c[0x0][0x184], P0 ; /* 0x0000610007007a0c */
/* 0x000fe20000721270 */
/*0130*/ IMAD R17, R4, 0x30cf, R7 ; /* 0x000030cf04117824 */
/* 0x001fe200078e0207 */
/*0140*/ LOP3.LUT R11, R11, 0x3, RZ, 0xc0, !PT ; /* 0x000000030b0b7812 */
/* 0x000fe200078ec0ff */
/*0150*/ IMAD R13, R6, 0x1c, R15.reuse ; /* 0x0000001c060d7824 */
/* 0x100fe200078e020f */
/*0160*/ ISETP.GE.U32.AND P4, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f86070 */
/*0170*/ IMAD.IADD R14, R14, 0x1, R15 ; /* 0x000000010e0e7824 */
/* 0x000fe200078e020f */
/*0180*/ IADD3 R8, R6.reuse, -0x2, RZ ; /* 0xfffffffe06087810 */
/* 0x040fe20007ffe0ff */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01a0*/ IADD3 R9, R7.reuse, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x040fe20007ffe0ff */
/*01b0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3 R10, R7, -0x2, RZ ; /* 0xfffffffe070a7810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ IMAD R17, R6.reuse, 0x7, R17 ; /* 0x0000000706117824 */
/* 0x040fe200078e0211 */
/*01e0*/ ISETP.LT.AND P0, PT, R6, c[0x0][0x180], !P2 ; /* 0x0000600006007a0c */
/* 0x000fc40005701270 */
/*01f0*/ ISETP.GT.AND P1, PT, R7, -0x1, P1 ; /* 0xffffffff0700780c */
/* 0x000fe40000f24270 */
/*0200*/ IADD3 R15, R15, -0x40, RZ ; /* 0xffffffc00f0f7810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R16, R11, -c[0x0][0x180], RZ ; /* 0x800060000b107a10 */
/* 0x000fcc0007ffe0ff */
/*0220*/ BSSY B0, 0x2c0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0230*/ @!P0 BRA 0x2b0 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD R3, R5, c[0x0][0x178], R12 ; /* 0x00005e0005037a24 */
/* 0x002fc800078e020c */
/*0250*/ IMAD R2, R3, c[0x0][0x180], R6 ; /* 0x0000600003027a24 */
/* 0x000fe400078e0206 */
/*0260*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0270*/ IMAD R2, R2, c[0x0][0x180], R7 ; /* 0x0000600002027a24 */
/* 0x000fc800078e0207 */
/*0280*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fcc00078e0203 */
/*0290*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ STS [R14], R3 ; /* 0x000000030e007388 */
/* 0x0041e40000000800 */
/*02b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ BSSY B0, 0x350 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*02e0*/ @!P1 BRA 0x340 ; /* 0x0000005000009947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fe400078e00ff */
/*0300*/ IMAD R2, R12, 0x31, R17 ; /* 0x000000310c027824 */
/* 0x000fc800078e0211 */
/*0310*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0203 */
/*0320*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0330*/ STS [R13], R2 ; /* 0x000000020d007388 */
/* 0x0041e40000000800 */
/*0340*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x001fe200078e00ff */
/*0360*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0370*/ ISETP.GE.AND P2, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f46270 */
/*0380*/ @!P2 BRA 0x8b0 ; /* 0x000005200000a947 */
/* 0x000fea0003800000 */
/*0390*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fc600078e00ff */
/*03a0*/ ISETP.NE.AND P5, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003fa5270 */
/*03b0*/ IMAD.IADD R2, R8, 0x1, R3 ; /* 0x0000000108027824 */
/* 0x000fe400078e0203 */
/*03c0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe200078e00ff */
/*03d0*/ @!P4 BRA 0x680 ; /* 0x000002a00000c947 */
/* 0x000ff20003800000 */
/*03e0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x14 ; /* 0x00000014ff147424 */
/* 0x000fe200078e00ff */
/*03f0*/ ISETP.GE.AND P6, PT, R2, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x000fe20003fc6270 */
/*0400*/ IMAD.IADD R18, R6, 0x1, R3 ; /* 0x0000000106127824 */
/* 0x000fe400078e0203 */
/*0410*/ IMAD R20, R3, R20, 0xc4 ; /* 0x000000c403147424 */
/* 0x000fe400078e0214 */
/*0420*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc400078e00ff */
/*0430*/ IMAD.MOV.U32 R21, RZ, RZ, R9 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0009 */
/*0440*/ IADD3 R20, R20, 0x8, RZ ; /* 0x0000000814147810 */
/* 0x000fe20007ffe0ff */
/*0450*/ IMAD R18, R18, 0x1c, R15 ; /* 0x0000001c12127824 */
/* 0x000fc600078e020f */
/*0460*/ IADD3 R23, R21.reuse, -0x3, RZ ; /* 0xfffffffd15177810 */
/* 0x040fe40007ffe0ff */
/*0470*/ IADD3 R25, R21, -0x2, RZ ; /* 0xfffffffe15197810 */
/* 0x000fe40007ffe0ff */
/*0480*/ LOP3.LUT R22, R23, R2, RZ, 0xfc, !PT ; /* 0x0000000217167212 */
/* 0x000fe400078efcff */
/*0490*/ IADD3 R27, R21, -0x1, RZ ; /* 0xffffffff151b7810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ ISETP.LT.OR P3, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fc40003761670 */
/*04b0*/ LOP3.LUT R22, R25, R2, RZ, 0xfc, !PT ; /* 0x0000000219167212 */
/* 0x000fe400078efcff */
/*04c0*/ ISETP.GE.OR P3, PT, R23, c[0x0][0x184], P3 ; /* 0x0000610017007a0c */
/* 0x000fe40001f66670 */
/*04d0*/ ISETP.LT.OR P2, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fe40003741670 */
/*04e0*/ IADD3 R19, R19, 0x4, RZ ; /* 0x0000000413137810 */
/* 0x000fe40007ffe0ff */
/*04f0*/ ISETP.GE.OR P2, PT, R25, c[0x0][0x184], P2 ; /* 0x0000610019007a0c */
/* 0x000fc60001746670 */
/*0500*/ IMAD.IADD R26, R16, 0x1, R19 ; /* 0x00000001101a7824 */
/* 0x000fc800078e0213 */
/*0510*/ @!P3 LDS R23, [R20+-0x8] ; /* 0xfffff8001417b984 */
/* 0x000fe80000000800 */
/*0520*/ @!P3 LDS R22, [R18] ; /* 0x000000001216b984 */
/* 0x000e280000000800 */
/*0530*/ @!P2 LDS R25, [R20+-0x4] ; /* 0xfffffc001419a984 */
/* 0x000fe80000000800 */
/*0540*/ @!P2 LDS R24, [R18+0x4] ; /* 0x000004001218a984 */
/* 0x000ea20000000800 */
/*0550*/ @!P3 FFMA R0, R23, R22, R0 ; /* 0x000000161700b223 */
/* 0x001fe20000000000 */
/*0560*/ LOP3.LUT R22, R27, R2, RZ, 0xfc, !PT ; /* 0x000000021b167212 */
/* 0x000fc800078efcff */
/*0570*/ ISETP.LT.OR P3, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fe40003761670 */
/*0580*/ LOP3.LUT R22, R21, R2, RZ, 0xfc, !PT ; /* 0x0000000215167212 */
/* 0x000fe200078efcff */
/*0590*/ @!P2 FFMA R0, R25, R24, R0 ; /* 0x000000181900a223 */
/* 0x004fe20000000000 */
/*05a0*/ ISETP.GE.OR P3, PT, R27, c[0x0][0x184], P3 ; /* 0x000061001b007a0c */
/* 0x000fe40001f66670 */
/*05b0*/ ISETP.LT.OR P2, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fc80003741670 */
/*05c0*/ ISETP.GE.OR P2, PT, R21.reuse, c[0x0][0x184], P2 ; /* 0x0000610015007a0c */
/* 0x040fe40001746670 */
/*05d0*/ IADD3 R21, R21, 0x4, RZ ; /* 0x0000000415157810 */
/* 0x000fca0007ffe0ff */
/*05e0*/ @!P3 LDS R23, [R20] ; /* 0x000000001417b984 */
/* 0x000fe80000000800 */
/*05f0*/ @!P3 LDS R22, [R18+0x8] ; /* 0x000008001216b984 */
/* 0x000e280000000800 */
/*0600*/ @!P2 LDS R25, [R20+0x4] ; /* 0x000004001419a984 */
/* 0x0005e80000000800 */
/*0610*/ @!P2 LDS R24, [R18+0xc] ; /* 0x00000c001218a984 */
/* 0x0007220000000800 */
/*0620*/ IADD3 R20, R20, 0x10, RZ ; /* 0x0000001014147810 */
/* 0x004fc40007ffe0ff */
/*0630*/ IADD3 R18, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x008fe20007ffe0ff */
/*0640*/ @!P3 FFMA R0, R23, R22, R0 ; /* 0x000000161700b223 */
/* 0x001fe20000000000 */
/*0650*/ ISETP.NE.AND P3, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fc60003f65270 */
/*0660*/ @!P2 FFMA R0, R25, R24, R0 ; /* 0x000000181900a223 */
/* 0x010fd40000000000 */
/*0670*/ @P3 BRA 0x460 ; /* 0xfffffde000003947 */
/* 0x000fea000383ffff */
/*0680*/ @!P5 BRA 0x880 ; /* 0x000001f00000d947 */
/* 0x000fea0003800000 */
/*0690*/ IMAD.IADD R23, R10, 0x1, R19 ; /* 0x000000010a177824 */
/* 0x000fe200078e0213 */
/*06a0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x184], PT ; /* 0x0000610002007a0c */
/* 0x000fe20003f46270 */
/*06b0*/ IMAD.MOV.U32 R20, RZ, RZ, 0x14 ; /* 0x00000014ff147424 */
/* 0x000fe200078e00ff */
/*06c0*/ ISETP.NE.AND P5, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe40003fa5270 */
/*06d0*/ LOP3.LUT R18, R23, R2, RZ, 0xfc, !PT ; /* 0x0000000217127212 */
/* 0x000fe200078efcff */
/*06e0*/ IMAD R20, R3, R20, 0xc4 ; /* 0x000000c403147424 */
/* 0x000fc600078e0214 */
/*06f0*/ ISETP.LT.OR P3, PT, R18, RZ, P2 ; /* 0x000000ff1200720c */
/* 0x000fe20001761670 */
/*0700*/ IMAD R18, R2, 0x7, R23 ; /* 0x0000000702127824 */
/* 0x000fe400078e0217 */
/*0710*/ IMAD R22, R19, 0x4, R20 ; /* 0x0000000413167824 */
/* 0x000fe200078e0214 */
/*0720*/ ISETP.GE.OR P3, PT, R23, c[0x0][0x184], P3 ; /* 0x0000610017007a0c */
/* 0x000fe20001f66670 */
/*0730*/ IMAD.SHL.U32 R18, R18, 0x4, RZ ; /* 0x0000000412127824 */
/* 0x000fd800078e00ff */
/*0740*/ @!P3 LDS R21, [R18] ; /* 0x000000001215b984 */
/* 0x000fe80000000800 */
/*0750*/ @!P3 LDS R20, [R22] ; /* 0x000000001614b984 */
/* 0x000e240000000800 */
/*0760*/ @!P3 FFMA R0, R21, R20, R0 ; /* 0x000000141500b223 */
/* 0x001fe20000000000 */
/*0770*/ @!P5 BRA 0x880 ; /* 0x000001000000d947 */
/* 0x000fea0003800000 */
/*0780*/ IADD3 R21, R23, 0x1, RZ ; /* 0x0000000117157810 */
/* 0x000fe40007ffe0ff */
/*0790*/ ISETP.NE.AND P5, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fe40003fa5270 */
/*07a0*/ LOP3.LUT R20, R21, R2, RZ, 0xfc, !PT ; /* 0x0000000215147212 */
/* 0x000fc800078efcff */
/*07b0*/ ISETP.LT.OR P3, PT, R20, RZ, P2 ; /* 0x000000ff1400720c */
/* 0x000fc80001761670 */
/*07c0*/ ISETP.GE.OR P3, PT, R21, c[0x0][0x184], P3 ; /* 0x0000610015007a0c */
/* 0x000fda0001f66670 */
/*07d0*/ @!P3 LDS R21, [R22+0x4] ; /* 0x000004001615b984 */
/* 0x000fe80000000800 */
/*07e0*/ @!P3 LDS R20, [R18+0x4] ; /* 0x000004001214b984 */
/* 0x000e240000000800 */
/*07f0*/ @!P3 FFMA R0, R21, R20, R0 ; /* 0x000000141500b223 */
/* 0x001fe20000000000 */
/*0800*/ @!P5 BRA 0x880 ; /* 0x000000700000d947 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.IADD R19, R7, 0x1, R19 ; /* 0x0000000107137824 */
/* 0x000fca00078e0213 */
/*0820*/ LOP3.LUT R2, R19, R2, RZ, 0xfc, !PT ; /* 0x0000000213027212 */
/* 0x000fc800078efcff */
/*0830*/ ISETP.LT.OR P2, PT, R2, RZ, P2 ; /* 0x000000ff0200720c */
/* 0x000fc80001741670 */
/*0840*/ ISETP.GE.OR P2, PT, R19, c[0x0][0x184], P2 ; /* 0x0000610013007a0c */
/* 0x000fda0001746670 */
/*0850*/ @!P2 LDS R19, [R22+0x8] ; /* 0x000008001613a984 */
/* 0x000fe80000000800 */
/*0860*/ @!P2 LDS R18, [R18+0x8] ; /* 0x000008001212a984 */
/* 0x000e240000000800 */
/*0870*/ @!P2 FFMA R0, R19, R18, R0 ; /* 0x000000121300a223 */
/* 0x001fe40000000000 */
/*0880*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0890*/ ISETP.GE.AND P2, PT, R3, c[0x0][0x180], PT ; /* 0x0000600003007a0c */
/* 0x000fda0003f46270 */
/*08a0*/ @!P2 BRA 0x3a0 ; /* 0xfffffaf00000a947 */
/* 0x000fea000383ffff */
/*08b0*/ IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fe20007ffe0ff */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*08d0*/ ISETP.GE.AND P2, PT, R12, c[0x0][0x178], PT ; /* 0x00005e000c007a0c */
/* 0x000fda0003f46270 */
/*08e0*/ @!P2 BRA 0x220 ; /* 0xfffff9300000a947 */
/* 0x000fea000383ffff */
/*08f0*/ IMAD R5, R4, c[0x0][0x17c], R5 ; /* 0x00005f0004057a24 */
/* 0x003fe400078e0205 */
/*0900*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*0910*/ IMAD R6, R5, c[0x0][0x184], R6 ; /* 0x0000610005067a24 */
/* 0x004fc800078e0206 */
/*0920*/ IMAD R2, R6, c[0x0][0x184], R7 ; /* 0x0000610006027a24 */
/* 0x008fc800078e0207 */
/*0930*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0940*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101904 */
/*0950*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0960*/ BRA 0x960; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11conv_kernelPfPKfS1_iiiii
.globl _Z11conv_kernelPfPKfS1_iiiii
.p2align 8
.type _Z11conv_kernelPfPKfS1_iiiii,@function
_Z11conv_kernelPfPKfS1_iiiii:
s_clause 0x1
s_load_b32 s12, s[0:1], 0x18
s_load_b32 s7, s[0:1], 0x24
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_16
s_clause 0x1
s_load_b32 s13, s[0:1], 0x20
s_load_b128 s[8:11], s[0:1], 0x8
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0
v_max_i32_e32 v9, v1, v0
v_mul_u32_u24_e32 v7, 20, v1
v_mul_u32_u24_e32 v8, 7, v1
s_delay_alu instid0(VALU_DEP_4)
v_mad_u32_u24 v6, v1, 28, v2
s_mul_i32 s3, s14, 0x30cf
v_add_nc_u32_e32 v4, -2, v1
v_add_nc_u32_e32 v5, -2, v0
v_add3_u32 v7, v7, v2, 0xd0
v_cmp_gt_i32_e64 s2, s7, v9
v_add3_u32 v2, s3, v0, v8
v_subrev_nc_u32_e32 v8, 64, v6
s_mul_i32 s17, s15, s12
s_mov_b32 s18, 0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s3, s13, v9
s_cmp_gt_i32 s13, 0
s_cselect_b32 s16, -1, 0
s_branch .LBB0_3
.LBB0_2:
s_set_inst_prefetch_distance 0x2
s_add_i32 s18, s18, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s18, s12
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_17
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_5
s_add_i32 s5, s18, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[9:10], null, s5, s13, v[1:2]
v_mad_u64_u32 v[10:11], null, v9, s13, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[9:10], 2, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v7, v9
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_7
v_mad_u64_u32 v[9:10], null, s18, 49, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
global_load_b32 v9, v[9:10], off
s_waitcnt vmcnt(0)
ds_store_b32 v6, v9
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB0_2
v_mov_b32_e32 v9, v8
s_mov_b32 s19, 0
s_movk_i32 s20, 0xd0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_10
.p2align 6
.LBB0_9:
v_add_nc_u32_e32 v9, 28, v9
s_add_i32 s19, s19, 1
s_add_i32 s20, s20, 20
s_cmp_eq_u32 s19, s13
s_cbranch_scc1 .LBB0_2
.LBB0_10:
v_add_nc_u32_e32 v10, s19, v4
s_mov_b32 s21, s20
s_mov_b32 s22, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v10
v_cmp_gt_i32_e64 s4, s7, v10
v_mov_b32_e32 v10, v9
s_branch .LBB0_13
.p2align 6
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s5
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s23
v_add_nc_u32_e32 v10, 4, v10
s_add_i32 s22, s22, 1
s_add_i32 s21, s21, 4
s_cmp_eq_u32 s13, s22
s_cbranch_scc1 .LBB0_9
.LBB0_13:
s_and_saveexec_b32 s23, vcc_lo
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v11, s22, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_lt_i32_e64 s5, -1, v11
v_cmp_gt_i32_e64 s6, s7, v11
s_and_b32 s5, s4, s5
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s6, s5, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s6
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v11, s21
ds_load_b32 v12, v10
ds_load_b32 v11, v11
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v3, v12, v11
s_branch .LBB0_11
.LBB0_16:
v_mov_b32_e32 v3, 0
.LBB0_17:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s14, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s2, s2, s15
v_mad_u64_u32 v[4:5], null, s2, s7, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s7, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11conv_kernelPfPKfS1_iiiii
.amdhsa_group_segment_fixed_size 308
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11conv_kernelPfPKfS1_iiiii, .Lfunc_end0-_Z11conv_kernelPfPKfS1_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 308
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11conv_kernelPfPKfS1_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z11conv_kernelPfPKfS1_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011afde_00000000-6_conv_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii
.type _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii, @function
_Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11conv_kernelPfPKfS1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii, .-_Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii
.globl _Z11conv_kernelPfPKfS1_iiiii
.type _Z11conv_kernelPfPKfS1_iiiii, @function
_Z11conv_kernelPfPKfS1_iiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z11conv_kernelPfPKfS1_iiiii, .-_Z11conv_kernelPfPKfS1_iiiii
.globl _Z11launch_convPfPKfS1_iiiii
.type _Z11launch_convPfPKfS1_iiiii, @function
_Z11launch_convPfPKfS1_iiiii:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r15
movq %rsi, %rbp
movq %rdx, %r12
movl %ecx, %r13d
movl %r8d, %ebx
movl %r9d, %r14d
movl $7, 8(%rsp)
movl $7, 12(%rsp)
movl 104(%rsp), %eax
movl %eax, 20(%rsp)
movl %r8d, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 104
movl 104(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 112
movl %r14d, %r9d
movl %ebx, %r8d
movl %r13d, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %r15, %rdi
call _Z42__device_stub__Z11conv_kernelPfPKfS1_iiiiiPfPKfS1_iiiii
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.cfi_endproc
.LFE2027:
.size _Z11launch_convPfPKfS1_iiiii, .-_Z11launch_convPfPKfS1_iiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11conv_kernelPfPKfS1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11conv_kernelPfPKfS1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "conv_kernel.hip"
.globl _Z26__device_stub__conv_kernelPfPKfS1_iiiii # -- Begin function _Z26__device_stub__conv_kernelPfPKfS1_iiiii
.p2align 4, 0x90
.type _Z26__device_stub__conv_kernelPfPKfS1_iiiii,@function
_Z26__device_stub__conv_kernelPfPKfS1_iiiii: # @_Z26__device_stub__conv_kernelPfPKfS1_iiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11conv_kernelPfPKfS1_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z26__device_stub__conv_kernelPfPKfS1_iiiii, .Lfunc_end0-_Z26__device_stub__conv_kernelPfPKfS1_iiiii
.cfi_endproc
# -- End function
.globl _Z11launch_convPfPKfS1_iiiii # -- Begin function _Z11launch_convPfPKfS1_iiiii
.p2align 4, 0x90
.type _Z11launch_convPfPKfS1_iiiii,@function
_Z11launch_convPfPKfS1_iiiii: # @_Z11launch_convPfPKfS1_iiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r14d
movl %ecx, %ebp
movq %rdx, %r15
movq %rsi, %r12
movq %rdi, %r13
movl 232(%rsp), %eax
movq %r14, %rdi
shlq $32, %rdi
orq %rax, %rdi
movabsq $30064771079, %rdx # imm = 0x700000007
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl 224(%rsp), %eax
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movq %r15, 72(%rsp)
movl %ebp, 20(%rsp)
movl %r14d, 16(%rsp)
movl %ebx, 12(%rsp)
movl %eax, 8(%rsp)
movl 232(%rsp), %eax
movl %eax, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11conv_kernelPfPKfS1_iiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11launch_convPfPKfS1_iiiii, .Lfunc_end1-_Z11launch_convPfPKfS1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11conv_kernelPfPKfS1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11conv_kernelPfPKfS1_iiiii,@object # @_Z11conv_kernelPfPKfS1_iiiii
.section .rodata,"a",@progbits
.globl _Z11conv_kernelPfPKfS1_iiiii
.p2align 3, 0x0
_Z11conv_kernelPfPKfS1_iiiii:
.quad _Z26__device_stub__conv_kernelPfPKfS1_iiiii
.size _Z11conv_kernelPfPKfS1_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11conv_kernelPfPKfS1_iiiii"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__conv_kernelPfPKfS1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11conv_kernelPfPKfS1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
__global__ void zhuanshi(int *d_b,int *d_bt,int n)
{
int ITdx = threadIdx.x;
int IBdx = blockIdx.x;
d_bt[ITdx * n + IBdx] = d_b[IBdx * n + ITdx];
}
__global__ void neiji(int *d_a,int *d_bt,int *d_c,int *d_data,int ICTdx,int ICBdx,int n)
{
/*
int INTdx = threadIdx.x;
int i = 2, j = 1;
d_data[INTdx] = d_a[ICTdx * n + INTdx] * d_bt[ICBdx * n + INTdx];
__syncthreads();
while(i <= n)
{
if(INTdx % 2 == 0)
{
d_data[INTdx] += d_data[INTdx + j];
}
i *= 2;
j *= 2;
}
d_c[ICTdx * n + ICBdx] = d_data[0];
*/
}
__global__ void chengfa(int *d_a,int *d_bt,int *d_c,int *d_data,int n)
{
/*
int ICTdx = threadIdx.x;
int ICBdx = blockIdx.x;
neiji<<<1,n>>>(d_a,d_bt,d_c,d_data,ICTdx,ICBdx,n);
__syncthreads();
*/
}
int main()
{
int blag = 1;//标志位
int n = 0;
/******判断输入数据是否合法************/
do{
std::cout << "请输入矩阵的维度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的矩阵维度有误,请重新输入!" << std::endl;
}else{
blag = 0;
}
}while(blag);
/*******申请主机内存*********/
int *h_a = (int*)malloc(sizeof(int) * n * n);
int *h_b = (int*)malloc(sizeof(int) * n * n);
int *h_c = (int*)malloc(sizeof(int) * n * n);
int *h_bt = (int*)malloc(sizeof(int) * n * n);
/*******初始化主机内存数据********/
srand(time(NULL));//设置随机数值
for(int i = 0; i < n * n; ++i)
{
h_a[i] = rand() % 11;
h_b[i] = rand() % 11;
h_c[i] = 0;
h_bt[i] = 0;
}
/*******申请设备内存*******/
int *d_a,*d_b,*d_c,*d_bt,*d_data;
cudaMalloc((void**)&d_a,sizeof(int) * n * n);
cudaMalloc((void**)&d_b,sizeof(int) * n * n);
cudaMalloc((void**)&d_c,sizeof(int) * n * n);
cudaMalloc((void**)&d_bt,sizeof(int) * n * n);
cudaMalloc((void**)&d_data,sizeof(int)*n);
/******主机内存数据复制到设备内存中************/
cudaMemcpy(d_a,h_a,sizeof(int) * n * n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int) * n * n,cudaMemcpyHostToDevice);
std::cout << "测试点" << std::endl;
/*******执行核函数******/
zhuanshi<<<n,n>>>(d_b,d_bt,n);
chengfa<<<n,n>>>(d_a,d_bt,d_c,d_data,n);
/*****设备内存数据复制到主机内存中*****/
cudaMemcpy(h_bt,d_bt,sizeof(int) * n * n,cudaMemcpyDeviceToHost);
cudaMemcpy(h_c,d_c,sizeof(int) * n * n,cudaMemcpyDeviceToHost);
std::cout << "CPU内存数据h_a:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_a[%d][%d] = %d\t",i,j,h_a[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_b:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_b[%d][%d] = %d\t",i,j,h_b[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_bt:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_bt[%d][%d] = %d\t",i,j,h_bt[n * i + j]);
}
printf("\n");
}
std::cout << "GPU内存数据:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_c[%d][%d] = %d\t",i,j,h_c[n * i + j]);
}
printf("\n");
}
/*******释放内存*********/
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
std::cout << "运行结束" << std::endl;
return 0;
} | code for sm_80
Function : _Z7chengfaPiS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5neijiPiS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8zhuanshiPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R5, c[0x0][0x170], R4 ; /* 0x00005c0005027a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD R4, R4, c[0x0][0x170], R5 ; /* 0x00005c0004047a24 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
__global__ void zhuanshi(int *d_b,int *d_bt,int n)
{
int ITdx = threadIdx.x;
int IBdx = blockIdx.x;
d_bt[ITdx * n + IBdx] = d_b[IBdx * n + ITdx];
}
__global__ void neiji(int *d_a,int *d_bt,int *d_c,int *d_data,int ICTdx,int ICBdx,int n)
{
/*
int INTdx = threadIdx.x;
int i = 2, j = 1;
d_data[INTdx] = d_a[ICTdx * n + INTdx] * d_bt[ICBdx * n + INTdx];
__syncthreads();
while(i <= n)
{
if(INTdx % 2 == 0)
{
d_data[INTdx] += d_data[INTdx + j];
}
i *= 2;
j *= 2;
}
d_c[ICTdx * n + ICBdx] = d_data[0];
*/
}
__global__ void chengfa(int *d_a,int *d_bt,int *d_c,int *d_data,int n)
{
/*
int ICTdx = threadIdx.x;
int ICBdx = blockIdx.x;
neiji<<<1,n>>>(d_a,d_bt,d_c,d_data,ICTdx,ICBdx,n);
__syncthreads();
*/
}
int main()
{
int blag = 1;//标志位
int n = 0;
/******判断输入数据是否合法************/
do{
std::cout << "请输入矩阵的维度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的矩阵维度有误,请重新输入!" << std::endl;
}else{
blag = 0;
}
}while(blag);
/*******申请主机内存*********/
int *h_a = (int*)malloc(sizeof(int) * n * n);
int *h_b = (int*)malloc(sizeof(int) * n * n);
int *h_c = (int*)malloc(sizeof(int) * n * n);
int *h_bt = (int*)malloc(sizeof(int) * n * n);
/*******初始化主机内存数据********/
srand(time(NULL));//设置随机数值
for(int i = 0; i < n * n; ++i)
{
h_a[i] = rand() % 11;
h_b[i] = rand() % 11;
h_c[i] = 0;
h_bt[i] = 0;
}
/*******申请设备内存*******/
int *d_a,*d_b,*d_c,*d_bt,*d_data;
cudaMalloc((void**)&d_a,sizeof(int) * n * n);
cudaMalloc((void**)&d_b,sizeof(int) * n * n);
cudaMalloc((void**)&d_c,sizeof(int) * n * n);
cudaMalloc((void**)&d_bt,sizeof(int) * n * n);
cudaMalloc((void**)&d_data,sizeof(int)*n);
/******主机内存数据复制到设备内存中************/
cudaMemcpy(d_a,h_a,sizeof(int) * n * n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int) * n * n,cudaMemcpyHostToDevice);
std::cout << "测试点" << std::endl;
/*******执行核函数******/
zhuanshi<<<n,n>>>(d_b,d_bt,n);
chengfa<<<n,n>>>(d_a,d_bt,d_c,d_data,n);
/*****设备内存数据复制到主机内存中*****/
cudaMemcpy(h_bt,d_bt,sizeof(int) * n * n,cudaMemcpyDeviceToHost);
cudaMemcpy(h_c,d_c,sizeof(int) * n * n,cudaMemcpyDeviceToHost);
std::cout << "CPU内存数据h_a:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_a[%d][%d] = %d\t",i,j,h_a[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_b:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_b[%d][%d] = %d\t",i,j,h_b[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_bt:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_bt[%d][%d] = %d\t",i,j,h_bt[n * i + j]);
}
printf("\n");
}
std::cout << "GPU内存数据:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_c[%d][%d] = %d\t",i,j,h_c[n * i + j]);
}
printf("\n");
}
/*******释放内存*********/
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
std::cout << "运行结束" << std::endl;
return 0;
} | .file "tmpxft_0017ba7e_00000000-6_chengfa.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8zhuanshiPiS_iPiS_i
.type _Z30__device_stub__Z8zhuanshiPiS_iPiS_i, @function
_Z30__device_stub__Z8zhuanshiPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8zhuanshiPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z8zhuanshiPiS_iPiS_i, .-_Z30__device_stub__Z8zhuanshiPiS_iPiS_i
.globl _Z8zhuanshiPiS_i
.type _Z8zhuanshiPiS_i, @function
_Z8zhuanshiPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8zhuanshiPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8zhuanshiPiS_i, .-_Z8zhuanshiPiS_i
.globl _Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii
.type _Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii, @function
_Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5neijiPiS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii, .-_Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii
.globl _Z5neijiPiS_S_S_iii
.type _Z5neijiPiS_S_S_iii, @function
_Z5neijiPiS_S_S_iii:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z5neijiPiS_S_S_iii, .-_Z5neijiPiS_S_S_iii
.globl _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i
.type _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i, @function
_Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i:
.LFB3698:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7chengfaPiS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i, .-_Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i
.globl _Z7chengfaPiS_S_S_i
.type _Z7chengfaPiS_S_S_i, @function
_Z7chengfaPiS_S_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z7chengfaPiS_S_S_i, .-_Z7chengfaPiS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265\347\232\204\347\273\264\345\272\246:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\344\275\240\350\276\223\345\205\245\347\232\204\347\237\251\351\230\265\347\273\264\345\272\246\346\234\211\350\257\257,\350\257\267\351\207\215\346\226\260\350\276\223\345\205\245!"
.section .rodata.str1.1
.LC2:
.string "\346\265\213\350\257\225\347\202\271"
.LC3:
.string "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_a:"
.LC4:
.string "h_a[%d][%d] = %d\t"
.LC5:
.string "\n"
.LC6:
.string "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_b:"
.LC7:
.string "h_b[%d][%d] = %d\t"
.LC8:
.string "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_bt:"
.LC9:
.string "h_bt[%d][%d] = %d\t"
.LC10:
.string "GPU\345\206\205\345\255\230\346\225\260\346\215\256:"
.LC11:
.string "h_c[%d][%d] = %d\t"
.LC12:
.string "\350\277\220\350\241\214\347\273\223\346\235\237"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq .LC0(%rip), %r12
leaq _ZSt4cout(%rip), %rbx
leaq _ZSt3cin(%rip), %rbp
leaq .LC1(%rip), %r13
jmp .L37
.L86:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L84
call _ZSt16__throw_bad_castv@PLT
.L84:
call __stack_chk_fail@PLT
.L30:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L87:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L85
call _ZSt16__throw_bad_castv@PLT
.L85:
call __stack_chk_fail@PLT
.L35:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L36:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L37:
movl $25, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L86
cmpb $0, 56(%r14)
je .L30
movzbl 67(%r14), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 4(%rsp), %rsi
movq %rbp, %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jg .L32
movl $47, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L87
cmpb $0, 56(%r14)
je .L35
movzbl 67(%r14), %esi
jmp .L36
.L88:
movl 4(%rsp), %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z8zhuanshiPiS_iPiS_i
jmp .L39
.L89:
movl 4(%rsp), %r8d
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i
jmp .L40
.L43:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L43
.L44:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L42
.L41:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L43
jmp .L44
.L47:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl 0(%r13,%rax,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L47
.L48:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L46
.L45:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L47
jmp .L48
.L51:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r15,%rax,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L51
.L52:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L50
.L49:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L51
jmp .L52
.L55:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r14,%rax,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L55
.L56:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L54
.L53:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L55
jmp .L56
.L32:
movslq %eax, %rbx
imulq %rbx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl 4(%rsp), %eax
movl %eax, %edx
imull %eax, %edx
movl $0, %ebx
testl %edx, %edx
jle .L57
.L38:
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx,4)
movl $0, (%r14,%rbx,4)
movl $0, (%r15,%rbx,4)
movl 4(%rsp), %eax
addq $1, %rbx
movl %eax, %edx
imull %eax, %edx
cmpl %ebx, %edx
jg .L38
.L57:
cltq
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rdx
movl $1, %ecx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 4(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L88
.L39:
movl 4(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L89
.L40:
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
cmpl $0, 4(%rsp)
jg .L41
.L42:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
cmpl $0, 4(%rsp)
jg .L45
.L46:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
cmpl $0, 4(%rsp)
jg .L49
.L50:
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq .LC11(%rip), %r15
cmpl $0, 4(%rsp)
jg .L53
.L54:
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L90
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z7chengfaPiS_S_S_i"
.LC14:
.string "_Z5neijiPiS_S_S_iii"
.LC15:
.string "_Z8zhuanshiPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7chengfaPiS_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z5neijiPiS_S_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z8zhuanshiPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
__global__ void zhuanshi(int *d_b,int *d_bt,int n)
{
int ITdx = threadIdx.x;
int IBdx = blockIdx.x;
d_bt[ITdx * n + IBdx] = d_b[IBdx * n + ITdx];
}
__global__ void neiji(int *d_a,int *d_bt,int *d_c,int *d_data,int ICTdx,int ICBdx,int n)
{
/*
int INTdx = threadIdx.x;
int i = 2, j = 1;
d_data[INTdx] = d_a[ICTdx * n + INTdx] * d_bt[ICBdx * n + INTdx];
__syncthreads();
while(i <= n)
{
if(INTdx % 2 == 0)
{
d_data[INTdx] += d_data[INTdx + j];
}
i *= 2;
j *= 2;
}
d_c[ICTdx * n + ICBdx] = d_data[0];
*/
}
__global__ void chengfa(int *d_a,int *d_bt,int *d_c,int *d_data,int n)
{
/*
int ICTdx = threadIdx.x;
int ICBdx = blockIdx.x;
neiji<<<1,n>>>(d_a,d_bt,d_c,d_data,ICTdx,ICBdx,n);
__syncthreads();
*/
}
int main()
{
int blag = 1;//标志位
int n = 0;
/******判断输入数据是否合法************/
do{
std::cout << "请输入矩阵的维度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的矩阵维度有误,请重新输入!" << std::endl;
}else{
blag = 0;
}
}while(blag);
/*******申请主机内存*********/
int *h_a = (int*)malloc(sizeof(int) * n * n);
int *h_b = (int*)malloc(sizeof(int) * n * n);
int *h_c = (int*)malloc(sizeof(int) * n * n);
int *h_bt = (int*)malloc(sizeof(int) * n * n);
/*******初始化主机内存数据********/
srand(time(NULL));//设置随机数值
for(int i = 0; i < n * n; ++i)
{
h_a[i] = rand() % 11;
h_b[i] = rand() % 11;
h_c[i] = 0;
h_bt[i] = 0;
}
/*******申请设备内存*******/
int *d_a,*d_b,*d_c,*d_bt,*d_data;
cudaMalloc((void**)&d_a,sizeof(int) * n * n);
cudaMalloc((void**)&d_b,sizeof(int) * n * n);
cudaMalloc((void**)&d_c,sizeof(int) * n * n);
cudaMalloc((void**)&d_bt,sizeof(int) * n * n);
cudaMalloc((void**)&d_data,sizeof(int)*n);
/******主机内存数据复制到设备内存中************/
cudaMemcpy(d_a,h_a,sizeof(int) * n * n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,sizeof(int) * n * n,cudaMemcpyHostToDevice);
std::cout << "测试点" << std::endl;
/*******执行核函数******/
zhuanshi<<<n,n>>>(d_b,d_bt,n);
chengfa<<<n,n>>>(d_a,d_bt,d_c,d_data,n);
/*****设备内存数据复制到主机内存中*****/
cudaMemcpy(h_bt,d_bt,sizeof(int) * n * n,cudaMemcpyDeviceToHost);
cudaMemcpy(h_c,d_c,sizeof(int) * n * n,cudaMemcpyDeviceToHost);
std::cout << "CPU内存数据h_a:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_a[%d][%d] = %d\t",i,j,h_a[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_b:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_b[%d][%d] = %d\t",i,j,h_b[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_bt:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_bt[%d][%d] = %d\t",i,j,h_bt[n * i + j]);
}
printf("\n");
}
std::cout << "GPU内存数据:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_c[%d][%d] = %d\t",i,j,h_c[n * i + j]);
}
printf("\n");
}
/*******释放内存*********/
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
std::cout << "运行结束" << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
__global__ void zhuanshi(int *d_b,int *d_bt,int n)
{
int ITdx = threadIdx.x;
int IBdx = blockIdx.x;
d_bt[ITdx * n + IBdx] = d_b[IBdx * n + ITdx];
}
__global__ void neiji(int *d_a,int *d_bt,int *d_c,int *d_data,int ICTdx,int ICBdx,int n)
{
/*
int INTdx = threadIdx.x;
int i = 2, j = 1;
d_data[INTdx] = d_a[ICTdx * n + INTdx] * d_bt[ICBdx * n + INTdx];
__syncthreads();
while(i <= n)
{
if(INTdx % 2 == 0)
{
d_data[INTdx] += d_data[INTdx + j];
}
i *= 2;
j *= 2;
}
d_c[ICTdx * n + ICBdx] = d_data[0];
*/
}
__global__ void chengfa(int *d_a,int *d_bt,int *d_c,int *d_data,int n)
{
/*
int ICTdx = threadIdx.x;
int ICBdx = blockIdx.x;
neiji<<<1,n>>>(d_a,d_bt,d_c,d_data,ICTdx,ICBdx,n);
__syncthreads();
*/
}
int main()
{
int blag = 1;//标志位
int n = 0;
/******判断输入数据是否合法************/
do{
std::cout << "请输入矩阵的维度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的矩阵维度有误,请重新输入!" << std::endl;
}else{
blag = 0;
}
}while(blag);
/*******申请主机内存*********/
int *h_a = (int*)malloc(sizeof(int) * n * n);
int *h_b = (int*)malloc(sizeof(int) * n * n);
int *h_c = (int*)malloc(sizeof(int) * n * n);
int *h_bt = (int*)malloc(sizeof(int) * n * n);
/*******初始化主机内存数据********/
srand(time(NULL));//设置随机数值
for(int i = 0; i < n * n; ++i)
{
h_a[i] = rand() % 11;
h_b[i] = rand() % 11;
h_c[i] = 0;
h_bt[i] = 0;
}
/*******申请设备内存*******/
int *d_a,*d_b,*d_c,*d_bt,*d_data;
hipMalloc((void**)&d_a,sizeof(int) * n * n);
hipMalloc((void**)&d_b,sizeof(int) * n * n);
hipMalloc((void**)&d_c,sizeof(int) * n * n);
hipMalloc((void**)&d_bt,sizeof(int) * n * n);
hipMalloc((void**)&d_data,sizeof(int)*n);
/******主机内存数据复制到设备内存中************/
hipMemcpy(d_a,h_a,sizeof(int) * n * n,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int) * n * n,hipMemcpyHostToDevice);
std::cout << "测试点" << std::endl;
/*******执行核函数******/
zhuanshi<<<n,n>>>(d_b,d_bt,n);
chengfa<<<n,n>>>(d_a,d_bt,d_c,d_data,n);
/*****设备内存数据复制到主机内存中*****/
hipMemcpy(h_bt,d_bt,sizeof(int) * n * n,hipMemcpyDeviceToHost);
hipMemcpy(h_c,d_c,sizeof(int) * n * n,hipMemcpyDeviceToHost);
std::cout << "CPU内存数据h_a:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_a[%d][%d] = %d\t",i,j,h_a[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_b:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_b[%d][%d] = %d\t",i,j,h_b[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_bt:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_bt[%d][%d] = %d\t",i,j,h_bt[n * i + j]);
}
printf("\n");
}
std::cout << "GPU内存数据:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_c[%d][%d] = %d\t",i,j,h_c[n * i + j]);
}
printf("\n");
}
/*******释放内存*********/
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
std::cout << "运行结束" << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
__global__ void zhuanshi(int *d_b,int *d_bt,int n)
{
int ITdx = threadIdx.x;
int IBdx = blockIdx.x;
d_bt[ITdx * n + IBdx] = d_b[IBdx * n + ITdx];
}
__global__ void neiji(int *d_a,int *d_bt,int *d_c,int *d_data,int ICTdx,int ICBdx,int n)
{
/*
int INTdx = threadIdx.x;
int i = 2, j = 1;
d_data[INTdx] = d_a[ICTdx * n + INTdx] * d_bt[ICBdx * n + INTdx];
__syncthreads();
while(i <= n)
{
if(INTdx % 2 == 0)
{
d_data[INTdx] += d_data[INTdx + j];
}
i *= 2;
j *= 2;
}
d_c[ICTdx * n + ICBdx] = d_data[0];
*/
}
__global__ void chengfa(int *d_a,int *d_bt,int *d_c,int *d_data,int n)
{
/*
int ICTdx = threadIdx.x;
int ICBdx = blockIdx.x;
neiji<<<1,n>>>(d_a,d_bt,d_c,d_data,ICTdx,ICBdx,n);
__syncthreads();
*/
}
int main()
{
int blag = 1;//标志位
int n = 0;
/******判断输入数据是否合法************/
do{
std::cout << "请输入矩阵的维度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的矩阵维度有误,请重新输入!" << std::endl;
}else{
blag = 0;
}
}while(blag);
/*******申请主机内存*********/
int *h_a = (int*)malloc(sizeof(int) * n * n);
int *h_b = (int*)malloc(sizeof(int) * n * n);
int *h_c = (int*)malloc(sizeof(int) * n * n);
int *h_bt = (int*)malloc(sizeof(int) * n * n);
/*******初始化主机内存数据********/
srand(time(NULL));//设置随机数值
for(int i = 0; i < n * n; ++i)
{
h_a[i] = rand() % 11;
h_b[i] = rand() % 11;
h_c[i] = 0;
h_bt[i] = 0;
}
/*******申请设备内存*******/
int *d_a,*d_b,*d_c,*d_bt,*d_data;
hipMalloc((void**)&d_a,sizeof(int) * n * n);
hipMalloc((void**)&d_b,sizeof(int) * n * n);
hipMalloc((void**)&d_c,sizeof(int) * n * n);
hipMalloc((void**)&d_bt,sizeof(int) * n * n);
hipMalloc((void**)&d_data,sizeof(int)*n);
/******主机内存数据复制到设备内存中************/
hipMemcpy(d_a,h_a,sizeof(int) * n * n,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int) * n * n,hipMemcpyHostToDevice);
std::cout << "测试点" << std::endl;
/*******执行核函数******/
zhuanshi<<<n,n>>>(d_b,d_bt,n);
chengfa<<<n,n>>>(d_a,d_bt,d_c,d_data,n);
/*****设备内存数据复制到主机内存中*****/
hipMemcpy(h_bt,d_bt,sizeof(int) * n * n,hipMemcpyDeviceToHost);
hipMemcpy(h_c,d_c,sizeof(int) * n * n,hipMemcpyDeviceToHost);
std::cout << "CPU内存数据h_a:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_a[%d][%d] = %d\t",i,j,h_a[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_b:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_b[%d][%d] = %d\t",i,j,h_b[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_bt:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_bt[%d][%d] = %d\t",i,j,h_bt[n * i + j]);
}
printf("\n");
}
std::cout << "GPU内存数据:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_c[%d][%d] = %d\t",i,j,h_c[n * i + j]);
}
printf("\n");
}
/*******释放内存*********/
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
std::cout << "运行结束" << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8zhuanshiPiS_i
.globl _Z8zhuanshiPiS_i
.p2align 8
.type _Z8zhuanshiPiS_i,@function
_Z8zhuanshiPiS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mad_u64_u32 v[1:2], null, v0, s5, s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8zhuanshiPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8zhuanshiPiS_i, .Lfunc_end0-_Z8zhuanshiPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5neijiPiS_S_S_iii
.globl _Z5neijiPiS_S_S_iii
.p2align 8
.type _Z5neijiPiS_S_S_iii,@function
_Z5neijiPiS_S_S_iii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5neijiPiS_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5neijiPiS_S_S_iii, .Lfunc_end1-_Z5neijiPiS_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7chengfaPiS_S_S_i
.globl _Z7chengfaPiS_S_S_i
.p2align 8
.type _Z7chengfaPiS_S_S_i,@function
_Z7chengfaPiS_S_S_i:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7chengfaPiS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7chengfaPiS_S_S_i, .Lfunc_end2-_Z7chengfaPiS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8zhuanshiPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8zhuanshiPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5neijiPiS_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z5neijiPiS_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7chengfaPiS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7chengfaPiS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <time.h>
__global__ void zhuanshi(int *d_b,int *d_bt,int n)
{
int ITdx = threadIdx.x;
int IBdx = blockIdx.x;
d_bt[ITdx * n + IBdx] = d_b[IBdx * n + ITdx];
}
__global__ void neiji(int *d_a,int *d_bt,int *d_c,int *d_data,int ICTdx,int ICBdx,int n)
{
/*
int INTdx = threadIdx.x;
int i = 2, j = 1;
d_data[INTdx] = d_a[ICTdx * n + INTdx] * d_bt[ICBdx * n + INTdx];
__syncthreads();
while(i <= n)
{
if(INTdx % 2 == 0)
{
d_data[INTdx] += d_data[INTdx + j];
}
i *= 2;
j *= 2;
}
d_c[ICTdx * n + ICBdx] = d_data[0];
*/
}
__global__ void chengfa(int *d_a,int *d_bt,int *d_c,int *d_data,int n)
{
/*
int ICTdx = threadIdx.x;
int ICBdx = blockIdx.x;
neiji<<<1,n>>>(d_a,d_bt,d_c,d_data,ICTdx,ICBdx,n);
__syncthreads();
*/
}
int main()
{
int blag = 1;//标志位
int n = 0;
/******判断输入数据是否合法************/
do{
std::cout << "请输入矩阵的维度:" << std::endl;
std::cin >> n;
if(n <= 0)
{
std::cout << "你输入的矩阵维度有误,请重新输入!" << std::endl;
}else{
blag = 0;
}
}while(blag);
/*******申请主机内存*********/
int *h_a = (int*)malloc(sizeof(int) * n * n);
int *h_b = (int*)malloc(sizeof(int) * n * n);
int *h_c = (int*)malloc(sizeof(int) * n * n);
int *h_bt = (int*)malloc(sizeof(int) * n * n);
/*******初始化主机内存数据********/
srand(time(NULL));//设置随机数值
for(int i = 0; i < n * n; ++i)
{
h_a[i] = rand() % 11;
h_b[i] = rand() % 11;
h_c[i] = 0;
h_bt[i] = 0;
}
/*******申请设备内存*******/
int *d_a,*d_b,*d_c,*d_bt,*d_data;
hipMalloc((void**)&d_a,sizeof(int) * n * n);
hipMalloc((void**)&d_b,sizeof(int) * n * n);
hipMalloc((void**)&d_c,sizeof(int) * n * n);
hipMalloc((void**)&d_bt,sizeof(int) * n * n);
hipMalloc((void**)&d_data,sizeof(int)*n);
/******主机内存数据复制到设备内存中************/
hipMemcpy(d_a,h_a,sizeof(int) * n * n,hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,sizeof(int) * n * n,hipMemcpyHostToDevice);
std::cout << "测试点" << std::endl;
/*******执行核函数******/
zhuanshi<<<n,n>>>(d_b,d_bt,n);
chengfa<<<n,n>>>(d_a,d_bt,d_c,d_data,n);
/*****设备内存数据复制到主机内存中*****/
hipMemcpy(h_bt,d_bt,sizeof(int) * n * n,hipMemcpyDeviceToHost);
hipMemcpy(h_c,d_c,sizeof(int) * n * n,hipMemcpyDeviceToHost);
std::cout << "CPU内存数据h_a:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_a[%d][%d] = %d\t",i,j,h_a[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_b:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_b[%d][%d] = %d\t",i,j,h_b[n * i + j]);
}
printf("\n");
}
std::cout << "CPU内存数据h_bt:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_bt[%d][%d] = %d\t",i,j,h_bt[n * i + j]);
}
printf("\n");
}
std::cout << "GPU内存数据:" << std::endl;
for(int i = 0; i < n; ++i)
{
for(int j = 0; j < n; ++j)
{
printf("h_c[%d][%d] = %d\t",i,j,h_c[n * i + j]);
}
printf("\n");
}
/*******释放内存*********/
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
std::cout << "运行结束" << std::endl;
return 0;
} | .text
.file "chengfa.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__zhuanshiPiS_i # -- Begin function _Z23__device_stub__zhuanshiPiS_i
.p2align 4, 0x90
.type _Z23__device_stub__zhuanshiPiS_i,@function
_Z23__device_stub__zhuanshiPiS_i: # @_Z23__device_stub__zhuanshiPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8zhuanshiPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__zhuanshiPiS_i, .Lfunc_end0-_Z23__device_stub__zhuanshiPiS_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__neijiPiS_S_S_iii # -- Begin function _Z20__device_stub__neijiPiS_S_S_iii
.p2align 4, 0x90
.type _Z20__device_stub__neijiPiS_S_S_iii,@function
_Z20__device_stub__neijiPiS_S_S_iii: # @_Z20__device_stub__neijiPiS_S_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5neijiPiS_S_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z20__device_stub__neijiPiS_S_S_iii, .Lfunc_end1-_Z20__device_stub__neijiPiS_S_S_iii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__chengfaPiS_S_S_i # -- Begin function _Z22__device_stub__chengfaPiS_S_S_i
.p2align 4, 0x90
.type _Z22__device_stub__chengfaPiS_S_S_i,@function
_Z22__device_stub__chengfaPiS_S_S_i: # @_Z22__device_stub__chengfaPiS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7chengfaPiS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z22__device_stub__chengfaPiS_S_S_i, .Lfunc_end2-_Z22__device_stub__chengfaPiS_S_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_11
# %bb.1:
leaq 12(%rsp), %rbx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit87
# in Loop: Header=BB3_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_11
.LBB3_2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# =>This Inner Loop Header: Depth=1
cmpb $0, 56(%r14)
je .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB3_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
movl 12(%rsp), %r12d
testl %r12d, %r12d
jg .LBB3_12
# %bb.6: # in Loop: Header=BB3_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
# in Loop: Header=BB3_2 Depth=1
cmpb $0, 56(%r14)
je .LBB3_9
# %bb.8: # in Loop: Header=BB3_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB3_10
.LBB3_12: # %.critedge
imulq %r12, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r12
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 12(%rsp), %eax
testl %eax, %eax
je .LBB3_15
# %bb.13: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_14: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r13,4)
movl $0, (%r15,%r13,4)
movl $0, (%r12,%r13,4)
incq %r13
movl 12(%rsp), %eax
movl %eax, %ecx
imull %ecx, %ecx
cmpq %rcx, %r13
jb .LBB3_14
.LBB3_15: # %._crit_edge136
movslq %eax, %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 168(%rsp), %rdi
callq hipMalloc
movq 40(%rsp), %rdi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_11
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r13)
je .LBB3_18
# %bb.17:
movzbl 67(%r13), %eax
jmp .LBB3_19
.LBB3_18:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92
movabsq $4294967296, %r13 # imm = 0x100000000
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 12(%rsp), %edi
orq %r13, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_21
# %bb.20:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movl 12(%rsp), %edx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %edx, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8zhuanshiPiS_i, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_21:
movl 12(%rsp), %edi
orq %r13, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_23
# %bb.22:
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
movq 168(%rsp), %rsi
movl 12(%rsp), %edi
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rsi, 88(%rsp)
movl %edi, 124(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 124(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7chengfaPiS_S_S_i, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_23:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_11
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r13)
je .LBB3_26
# %bb.25:
movzbl 67(%r13), %eax
jmp .LBB3_27
.LBB3_26:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit97
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
jle .LBB3_33
# %bb.28: # %.preheader129.preheader
xorl %ebp, %ebp
jmp .LBB3_29
.p2align 4, 0x90
.LBB3_32: # %._crit_edge139
# in Loop: Header=BB3_29 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB3_33
.LBB3_29: # %.preheader129
# =>This Loop Header: Depth=1
# Child Loop BB3_31 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_32
# %bb.30: # %.lr.ph138.preheader
# in Loop: Header=BB3_29 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_31: # %.lr.ph138
# Parent Loop BB3_29 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r13, %rax
movl (%rbx,%rax,4), %ecx
movl $.L.str.4, %edi
movl %ebp, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r13
cmpl %eax, %r13d
jl .LBB3_31
jmp .LBB3_32
.LBB3_33: # %._crit_edge141
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_11
# %bb.34: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
cmpb $0, 56(%r13)
je .LBB3_36
# %bb.35:
movzbl 67(%r13), %eax
jmp .LBB3_37
.LBB3_36:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_37: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit102
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
jle .LBB3_43
# %bb.38: # %.preheader128.preheader
xorl %ebp, %ebp
jmp .LBB3_39
.p2align 4, 0x90
.LBB3_42: # %._crit_edge144
# in Loop: Header=BB3_39 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB3_43
.LBB3_39: # %.preheader128
# =>This Loop Header: Depth=1
# Child Loop BB3_41 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_42
# %bb.40: # %.lr.ph143.preheader
# in Loop: Header=BB3_39 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_41: # %.lr.ph143
# Parent Loop BB3_39 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r13, %rax
movl (%r14,%rax,4), %ecx
movl $.L.str.7, %edi
movl %ebp, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r13
cmpl %eax, %r13d
jl .LBB3_41
jmp .LBB3_42
.LBB3_43: # %._crit_edge146
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_11
# %bb.44: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i104
cmpb $0, 56(%r13)
je .LBB3_46
# %bb.45:
movzbl 67(%r13), %eax
jmp .LBB3_47
.LBB3_46:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_47: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit107
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
jle .LBB3_53
# %bb.48: # %.preheader127.preheader
xorl %ebp, %ebp
jmp .LBB3_49
.p2align 4, 0x90
.LBB3_52: # %._crit_edge149
# in Loop: Header=BB3_49 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB3_53
.LBB3_49: # %.preheader127
# =>This Loop Header: Depth=1
# Child Loop BB3_51 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_52
# %bb.50: # %.lr.ph148.preheader
# in Loop: Header=BB3_49 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_51: # %.lr.ph148
# Parent Loop BB3_49 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r13, %rax
movl (%r12,%rax,4), %ecx
movl $.L.str.9, %edi
movl %ebp, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r13
cmpl %eax, %r13d
jl .LBB3_51
jmp .LBB3_52
.LBB3_53: # %._crit_edge151
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_11
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i109
cmpb $0, 56(%r12)
je .LBB3_56
# %bb.55:
movzbl 67(%r12), %eax
jmp .LBB3_57
.LBB3_56:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_57: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit112
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
jle .LBB3_63
# %bb.58: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB3_59
.p2align 4, 0x90
.LBB3_62: # %._crit_edge154
# in Loop: Header=BB3_59 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB3_63
.LBB3_59: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_61 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_62
# %bb.60: # %.lr.ph153.preheader
# in Loop: Header=BB3_59 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_61: # %.lr.ph153
# Parent Loop BB3_59 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r12, %rax
movl (%r15,%rax,4), %ecx
movl $.L.str.11, %edi
movl %ebp, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r12
cmpl %eax, %r12d
jl .LBB3_61
jmp .LBB3_62
.LBB3_63: # %._crit_edge156
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_11
# %bb.64: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i114
cmpb $0, 56(%rbx)
je .LBB3_66
# %bb.65:
movzbl 67(%rbx), %eax
jmp .LBB3_67
.LBB3_66:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_67: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit117
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_11: # %._crit_edge
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8zhuanshiPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5neijiPiS_S_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7chengfaPiS_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8zhuanshiPiS_i,@object # @_Z8zhuanshiPiS_i
.section .rodata,"a",@progbits
.globl _Z8zhuanshiPiS_i
.p2align 3, 0x0
_Z8zhuanshiPiS_i:
.quad _Z23__device_stub__zhuanshiPiS_i
.size _Z8zhuanshiPiS_i, 8
.type _Z5neijiPiS_S_S_iii,@object # @_Z5neijiPiS_S_S_iii
.globl _Z5neijiPiS_S_S_iii
.p2align 3, 0x0
_Z5neijiPiS_S_S_iii:
.quad _Z20__device_stub__neijiPiS_S_S_iii
.size _Z5neijiPiS_S_S_iii, 8
.type _Z7chengfaPiS_S_S_i,@object # @_Z7chengfaPiS_S_S_i
.globl _Z7chengfaPiS_S_S_i
.p2align 3, 0x0
_Z7chengfaPiS_S_S_i:
.quad _Z22__device_stub__chengfaPiS_S_S_i
.size _Z7chengfaPiS_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265\347\232\204\347\273\264\345\272\246:"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\344\275\240\350\276\223\345\205\245\347\232\204\347\237\251\351\230\265\347\273\264\345\272\246\346\234\211\350\257\257,\350\257\267\351\207\215\346\226\260\350\276\223\345\205\245!"
.size .L.str.1, 48
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\346\265\213\350\257\225\347\202\271"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_a:"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "h_a[%d][%d] = %d\t"
.size .L.str.4, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_b:"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "h_b[%d][%d] = %d\t"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_bt:"
.size .L.str.8, 21
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "h_bt[%d][%d] = %d\t"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "GPU\345\206\205\345\255\230\346\225\260\346\215\256:"
.size .L.str.10, 17
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "h_c[%d][%d] = %d\t"
.size .L.str.11, 18
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\350\277\220\350\241\214\347\273\223\346\235\237"
.size .L.str.12, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8zhuanshiPiS_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5neijiPiS_S_S_iii"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7chengfaPiS_S_S_i"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__zhuanshiPiS_i
.addrsig_sym _Z20__device_stub__neijiPiS_S_S_iii
.addrsig_sym _Z22__device_stub__chengfaPiS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8zhuanshiPiS_i
.addrsig_sym _Z5neijiPiS_S_S_iii
.addrsig_sym _Z7chengfaPiS_S_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7chengfaPiS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5neijiPiS_S_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8zhuanshiPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R5, c[0x0][0x170], R4 ; /* 0x00005c0005027a24 */
/* 0x001fca00078e0204 */
/*0060*/ IMAD.WIDE R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD R4, R4, c[0x0][0x170], R5 ; /* 0x00005c0004047a24 */
/* 0x000fc800078e0205 */
/*0090*/ IMAD.WIDE R4, R4, R7, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0207 */
/*00a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8zhuanshiPiS_i
.globl _Z8zhuanshiPiS_i
.p2align 8
.type _Z8zhuanshiPiS_i,@function
_Z8zhuanshiPiS_i:
s_clause 0x1
s_load_b32 s5, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[1:2], null, s4, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[1:2], off
v_mad_u64_u32 v[1:2], null, v0, s5, s[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8zhuanshiPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8zhuanshiPiS_i, .Lfunc_end0-_Z8zhuanshiPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5neijiPiS_S_S_iii
.globl _Z5neijiPiS_S_S_iii
.p2align 8
.type _Z5neijiPiS_S_S_iii,@function
_Z5neijiPiS_S_S_iii:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5neijiPiS_S_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5neijiPiS_S_S_iii, .Lfunc_end1-_Z5neijiPiS_S_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7chengfaPiS_S_S_i
.globl _Z7chengfaPiS_S_S_i
.p2align 8
.type _Z7chengfaPiS_S_S_i,@function
_Z7chengfaPiS_S_S_i:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7chengfaPiS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7chengfaPiS_S_S_i, .Lfunc_end2-_Z7chengfaPiS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8zhuanshiPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8zhuanshiPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5neijiPiS_S_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z5neijiPiS_S_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7chengfaPiS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7chengfaPiS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017ba7e_00000000-6_chengfa.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z8zhuanshiPiS_iPiS_i
.type _Z30__device_stub__Z8zhuanshiPiS_iPiS_i, @function
_Z30__device_stub__Z8zhuanshiPiS_iPiS_i:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8zhuanshiPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z8zhuanshiPiS_iPiS_i, .-_Z30__device_stub__Z8zhuanshiPiS_iPiS_i
.globl _Z8zhuanshiPiS_i
.type _Z8zhuanshiPiS_i, @function
_Z8zhuanshiPiS_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8zhuanshiPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8zhuanshiPiS_i, .-_Z8zhuanshiPiS_i
.globl _Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii
.type _Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii, @function
_Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii:
.LFB3696:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5neijiPiS_S_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii, .-_Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii
.globl _Z5neijiPiS_S_S_iii
.type _Z5neijiPiS_S_S_iii, @function
_Z5neijiPiS_S_S_iii:
.LFB3697:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z33__device_stub__Z5neijiPiS_S_S_iiiPiS_S_S_iii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z5neijiPiS_S_S_iii, .-_Z5neijiPiS_S_S_iii
.globl _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i
.type _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i, @function
_Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i:
.LFB3698:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7chengfaPiS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i, .-_Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i
.globl _Z7chengfaPiS_S_S_i
.type _Z7chengfaPiS_S_S_i, @function
_Z7chengfaPiS_S_S_i:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z7chengfaPiS_S_S_i, .-_Z7chengfaPiS_S_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265\347\232\204\347\273\264\345\272\246:"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "\344\275\240\350\276\223\345\205\245\347\232\204\347\237\251\351\230\265\347\273\264\345\272\246\346\234\211\350\257\257,\350\257\267\351\207\215\346\226\260\350\276\223\345\205\245!"
.section .rodata.str1.1
.LC2:
.string "\346\265\213\350\257\225\347\202\271"
.LC3:
.string "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_a:"
.LC4:
.string "h_a[%d][%d] = %d\t"
.LC5:
.string "\n"
.LC6:
.string "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_b:"
.LC7:
.string "h_b[%d][%d] = %d\t"
.LC8:
.string "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_bt:"
.LC9:
.string "h_bt[%d][%d] = %d\t"
.LC10:
.string "GPU\345\206\205\345\255\230\346\225\260\346\215\256:"
.LC11:
.string "h_c[%d][%d] = %d\t"
.LC12:
.string "\350\277\220\350\241\214\347\273\223\346\235\237"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $0, 4(%rsp)
leaq .LC0(%rip), %r12
leaq _ZSt4cout(%rip), %rbx
leaq _ZSt3cin(%rip), %rbp
leaq .LC1(%rip), %r13
jmp .L37
.L86:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L84
call _ZSt16__throw_bad_castv@PLT
.L84:
call __stack_chk_fail@PLT
.L30:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L31
.L87:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L85
call _ZSt16__throw_bad_castv@PLT
.L85:
call __stack_chk_fail@PLT
.L35:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
.L36:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L37:
movl $25, %edx
movq %r12, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L86
cmpb $0, 56(%r14)
je .L30
movzbl 67(%r14), %esi
.L31:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
leaq 4(%rsp), %rsi
movq %rbp, %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %eax
testl %eax, %eax
jg .L32
movl $47, %edx
movq %r13, %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .L87
cmpb $0, 56(%r14)
je .L35
movzbl 67(%r14), %esi
jmp .L36
.L88:
movl 4(%rsp), %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z8zhuanshiPiS_iPiS_i
jmp .L39
.L89:
movl 4(%rsp), %r8d
movq 40(%rsp), %rcx
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z7chengfaPiS_S_S_iPiS_S_S_i
jmp .L40
.L43:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r12,%rax,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L43
.L44:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L42
.L41:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L43
jmp .L44
.L47:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl 0(%r13,%rax,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L47
.L48:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L46
.L45:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L47
jmp .L48
.L51:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r15,%rax,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L51
.L52:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L50
.L49:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L51
jmp .L52
.L55:
imull %ebp, %eax
addl %ebx, %eax
cltq
movl (%r14,%rax,4), %r8d
movl %ebx, %ecx
movl %ebp, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
movl 4(%rsp), %eax
cmpl %ebx, %eax
jg .L55
.L56:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebp
cmpl %ebp, 4(%rsp)
jle .L54
.L53:
movl 4(%rsp), %eax
movl $0, %ebx
testl %eax, %eax
jg .L55
jmp .L56
.L32:
movslq %eax, %rbx
imulq %rbx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl 4(%rsp), %eax
movl %eax, %edx
imull %eax, %edx
movl $0, %ebx
testl %edx, %edx
jle .L57
.L38:
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $780903145, %rdx, %rdx
sarq $33, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
leal (%rdx,%rcx,2), %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx,4)
movl $0, (%r14,%rbx,4)
movl $0, (%r15,%rbx,4)
movl 4(%rsp), %eax
addq $1, %rbx
movl %eax, %edx
imull %eax, %edx
cmpl %ebx, %edx
jg .L38
.L57:
cltq
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rdx
movl $1, %ecx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rdx
movl $1, %ecx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 4(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L88
.L39:
movl 4(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L89
.L40:
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rax
imulq %rax, %rax
leaq 0(,%rax,4), %rdx
movl $2, %ecx
movq 24(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
cmpl $0, 4(%rsp)
jg .L41
.L42:
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
cmpl $0, 4(%rsp)
jg .L45
.L46:
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
cmpl $0, 4(%rsp)
jg .L49
.L50:
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebp
leaq .LC11(%rip), %r15
cmpl $0, 4(%rsp)
jg .L53
.L54:
movq %r12, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC12(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L90
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L90:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z7chengfaPiS_S_S_i"
.LC14:
.string "_Z5neijiPiS_S_S_iii"
.LC15:
.string "_Z8zhuanshiPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z7chengfaPiS_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z5neijiPiS_S_S_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z8zhuanshiPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "chengfa.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__zhuanshiPiS_i # -- Begin function _Z23__device_stub__zhuanshiPiS_i
.p2align 4, 0x90
.type _Z23__device_stub__zhuanshiPiS_i,@function
_Z23__device_stub__zhuanshiPiS_i: # @_Z23__device_stub__zhuanshiPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8zhuanshiPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__zhuanshiPiS_i, .Lfunc_end0-_Z23__device_stub__zhuanshiPiS_i
.cfi_endproc
# -- End function
.globl _Z20__device_stub__neijiPiS_S_S_iii # -- Begin function _Z20__device_stub__neijiPiS_S_S_iii
.p2align 4, 0x90
.type _Z20__device_stub__neijiPiS_S_S_iii,@function
_Z20__device_stub__neijiPiS_S_S_iii: # @_Z20__device_stub__neijiPiS_S_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5neijiPiS_S_S_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z20__device_stub__neijiPiS_S_S_iii, .Lfunc_end1-_Z20__device_stub__neijiPiS_S_S_iii
.cfi_endproc
# -- End function
.globl _Z22__device_stub__chengfaPiS_S_S_i # -- Begin function _Z22__device_stub__chengfaPiS_S_S_i
.p2align 4, 0x90
.type _Z22__device_stub__chengfaPiS_S_S_i,@function
_Z22__device_stub__chengfaPiS_S_S_i: # @_Z22__device_stub__chengfaPiS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7chengfaPiS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size _Z22__device_stub__chengfaPiS_S_S_i, .Lfunc_end2-_Z22__device_stub__chengfaPiS_S_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $0, 12(%rsp)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_11
# %bb.1:
leaq 12(%rsp), %rbx
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_9: # in Loop: Header=BB3_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit87
# in Loop: Header=BB3_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_11
.LBB3_2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# =>This Inner Loop Header: Depth=1
cmpb $0, 56(%r14)
je .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB3_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt3cin, %edi
movq %rbx, %rsi
callq _ZNSirsERi
movl 12(%rsp), %r12d
testl %r12d, %r12d
jg .LBB3_12
# %bb.6: # in Loop: Header=BB3_2 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $47, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i84
# in Loop: Header=BB3_2 Depth=1
cmpb $0, 56(%r14)
je .LBB3_9
# %bb.8: # in Loop: Header=BB3_2 Depth=1
movzbl 67(%r14), %eax
jmp .LBB3_10
.LBB3_12: # %.critedge
imulq %r12, %r12
shlq $2, %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
movq %r12, %rdi
callq malloc
movq %rax, %r12
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 12(%rsp), %eax
testl %eax, %eax
je .LBB3_15
# %bb.13: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_14: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r13,4)
callq rand
cltq
imulq $780903145, %rax, %rcx # imm = 0x2E8BA2E9
movq %rcx, %rdx
shrq $63, %rdx
sarq $33, %rcx
addl %edx, %ecx
leal (%rcx,%rcx,4), %edx
leal (%rcx,%rdx,2), %ecx
subl %ecx, %eax
movl %eax, (%r14,%r13,4)
movl $0, (%r15,%r13,4)
movl $0, (%r12,%r13,4)
incq %r13
movl 12(%rsp), %eax
movl %eax, %ecx
imull %ecx, %ecx
cmpq %rcx, %r13
jb .LBB3_14
.LBB3_15: # %._crit_edge136
movslq %eax, %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 40(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
imulq %rsi, %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 168(%rsp), %rdi
callq hipMalloc
movq 40(%rsp), %rdi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_11
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i89
cmpb $0, 56(%r13)
je .LBB3_18
# %bb.17:
movzbl 67(%r13), %eax
jmp .LBB3_19
.LBB3_18:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit92
movabsq $4294967296, %r13 # imm = 0x100000000
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 12(%rsp), %edi
orq %r13, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_21
# %bb.20:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movl 12(%rsp), %edx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movl %edx, 48(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z8zhuanshiPiS_i, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_21:
movl 12(%rsp), %edi
orq %r13, %rdi
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_23
# %bb.22:
movq 40(%rsp), %rax
movq 16(%rsp), %rcx
movq 24(%rsp), %rdx
movq 168(%rsp), %rsi
movl 12(%rsp), %edi
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
movq %rdx, 96(%rsp)
movq %rsi, 88(%rsp)
movl %edi, 124(%rsp)
leaq 112(%rsp), %rax
movq %rax, 128(%rsp)
leaq 104(%rsp), %rax
movq %rax, 136(%rsp)
leaq 96(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rax
movq %rax, 152(%rsp)
leaq 124(%rsp), %rax
movq %rax, 160(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z7chengfaPiS_S_S_i, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_23:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rsi
movslq 12(%rsp), %rdx
imulq %rdx, %rdx
shlq $2, %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_11
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i94
cmpb $0, 56(%r13)
je .LBB3_26
# %bb.25:
movzbl 67(%r13), %eax
jmp .LBB3_27
.LBB3_26:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit97
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
jle .LBB3_33
# %bb.28: # %.preheader129.preheader
xorl %ebp, %ebp
jmp .LBB3_29
.p2align 4, 0x90
.LBB3_32: # %._crit_edge139
# in Loop: Header=BB3_29 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB3_33
.LBB3_29: # %.preheader129
# =>This Loop Header: Depth=1
# Child Loop BB3_31 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_32
# %bb.30: # %.lr.ph138.preheader
# in Loop: Header=BB3_29 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_31: # %.lr.ph138
# Parent Loop BB3_29 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r13, %rax
movl (%rbx,%rax,4), %ecx
movl $.L.str.4, %edi
movl %ebp, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r13
cmpl %eax, %r13d
jl .LBB3_31
jmp .LBB3_32
.LBB3_33: # %._crit_edge141
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_11
# %bb.34: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i99
cmpb $0, 56(%r13)
je .LBB3_36
# %bb.35:
movzbl 67(%r13), %eax
jmp .LBB3_37
.LBB3_36:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_37: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit102
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
jle .LBB3_43
# %bb.38: # %.preheader128.preheader
xorl %ebp, %ebp
jmp .LBB3_39
.p2align 4, 0x90
.LBB3_42: # %._crit_edge144
# in Loop: Header=BB3_39 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB3_43
.LBB3_39: # %.preheader128
# =>This Loop Header: Depth=1
# Child Loop BB3_41 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_42
# %bb.40: # %.lr.ph143.preheader
# in Loop: Header=BB3_39 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_41: # %.lr.ph143
# Parent Loop BB3_39 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r13, %rax
movl (%r14,%rax,4), %ecx
movl $.L.str.7, %edi
movl %ebp, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r13
cmpl %eax, %r13d
jl .LBB3_41
jmp .LBB3_42
.LBB3_43: # %._crit_edge146
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_11
# %bb.44: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i104
cmpb $0, 56(%r13)
je .LBB3_46
# %bb.45:
movzbl 67(%r13), %eax
jmp .LBB3_47
.LBB3_46:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_47: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit107
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
jle .LBB3_53
# %bb.48: # %.preheader127.preheader
xorl %ebp, %ebp
jmp .LBB3_49
.p2align 4, 0x90
.LBB3_52: # %._crit_edge149
# in Loop: Header=BB3_49 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB3_53
.LBB3_49: # %.preheader127
# =>This Loop Header: Depth=1
# Child Loop BB3_51 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_52
# %bb.50: # %.lr.ph148.preheader
# in Loop: Header=BB3_49 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_51: # %.lr.ph148
# Parent Loop BB3_49 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r13, %rax
movl (%r12,%rax,4), %ecx
movl $.L.str.9, %edi
movl %ebp, %esi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r13
cmpl %eax, %r13d
jl .LBB3_51
jmp .LBB3_52
.LBB3_53: # %._crit_edge151
movl $_ZSt4cout, %edi
movl $.L.str.10, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB3_11
# %bb.54: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i109
cmpb $0, 56(%r12)
je .LBB3_56
# %bb.55:
movzbl 67(%r12), %eax
jmp .LBB3_57
.LBB3_56:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_57: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit112
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
cmpl $0, 12(%rsp)
jle .LBB3_63
# %bb.58: # %.preheader.preheader
xorl %ebp, %ebp
jmp .LBB3_59
.p2align 4, 0x90
.LBB3_62: # %._crit_edge154
# in Loop: Header=BB3_59 Depth=1
movl $10, %edi
callq putchar@PLT
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB3_63
.LBB3_59: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_61 Depth 2
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB3_62
# %bb.60: # %.lr.ph153.preheader
# in Loop: Header=BB3_59 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_61: # %.lr.ph153
# Parent Loop BB3_59 Depth=1
# => This Inner Loop Header: Depth=2
imull %ebp, %eax
cltq
addq %r12, %rax
movl (%r15,%rax,4), %ecx
movl $.L.str.11, %edi
movl %ebp, %esi
movl %r12d, %edx
xorl %eax, %eax
callq printf
movl 12(%rsp), %eax
incq %r12
cmpl %eax, %r12d
jl .LBB3_61
jmp .LBB3_62
.LBB3_63: # %._crit_edge156
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $_ZSt4cout, %edi
movl $.L.str.12, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB3_11
# %bb.64: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i114
cmpb $0, 56(%rbx)
je .LBB3_66
# %bb.65:
movzbl 67(%rbx), %eax
jmp .LBB3_67
.LBB3_66:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_67: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit117
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_11: # %._crit_edge
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8zhuanshiPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5neijiPiS_S_S_iii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7chengfaPiS_S_S_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8zhuanshiPiS_i,@object # @_Z8zhuanshiPiS_i
.section .rodata,"a",@progbits
.globl _Z8zhuanshiPiS_i
.p2align 3, 0x0
_Z8zhuanshiPiS_i:
.quad _Z23__device_stub__zhuanshiPiS_i
.size _Z8zhuanshiPiS_i, 8
.type _Z5neijiPiS_S_S_iii,@object # @_Z5neijiPiS_S_S_iii
.globl _Z5neijiPiS_S_S_iii
.p2align 3, 0x0
_Z5neijiPiS_S_S_iii:
.quad _Z20__device_stub__neijiPiS_S_S_iii
.size _Z5neijiPiS_S_S_iii, 8
.type _Z7chengfaPiS_S_S_i,@object # @_Z7chengfaPiS_S_S_i
.globl _Z7chengfaPiS_S_S_i
.p2align 3, 0x0
_Z7chengfaPiS_S_S_i:
.quad _Z22__device_stub__chengfaPiS_S_S_i
.size _Z7chengfaPiS_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\350\257\267\350\276\223\345\205\245\347\237\251\351\230\265\347\232\204\347\273\264\345\272\246:"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\344\275\240\350\276\223\345\205\245\347\232\204\347\237\251\351\230\265\347\273\264\345\272\246\346\234\211\350\257\257,\350\257\267\351\207\215\346\226\260\350\276\223\345\205\245!"
.size .L.str.1, 48
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\346\265\213\350\257\225\347\202\271"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_a:"
.size .L.str.3, 20
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "h_a[%d][%d] = %d\t"
.size .L.str.4, 18
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_b:"
.size .L.str.6, 20
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "h_b[%d][%d] = %d\t"
.size .L.str.7, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "CPU\345\206\205\345\255\230\346\225\260\346\215\256h_bt:"
.size .L.str.8, 21
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "h_bt[%d][%d] = %d\t"
.size .L.str.9, 19
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "GPU\345\206\205\345\255\230\346\225\260\346\215\256:"
.size .L.str.10, 17
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "h_c[%d][%d] = %d\t"
.size .L.str.11, 18
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\350\277\220\350\241\214\347\273\223\346\235\237"
.size .L.str.12, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8zhuanshiPiS_i"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5neijiPiS_S_S_iii"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7chengfaPiS_S_S_i"
.size .L__unnamed_3, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__zhuanshiPiS_i
.addrsig_sym _Z20__device_stub__neijiPiS_S_S_iii
.addrsig_sym _Z22__device_stub__chengfaPiS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8zhuanshiPiS_i
.addrsig_sym _Z5neijiPiS_S_S_iii
.addrsig_sym _Z7chengfaPiS_S_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
/* This sample queries the properties of the CUDA devices present in the system. */
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
inline int _ConvertSMVer2Cores(int major, int minor)
{
// Defines for GPU Architecture types (using the SM version to determine the # of cores per SM
typedef struct
{
int SM; // 0xMm (hexidecimal notation), M = SM Major version, and m = SM minor version
int Cores;
} sSMtoCores;
sSMtoCores nGpuArchCoresPerSM[] =
{
{ 0x20, 32 }, // Fermi Generation (SM 2.0) GF100 class
{ 0x21, 48 }, // Fermi Generation (SM 2.1) GF10x class
{ 0x30, 192}, // Kepler Generation (SM 3.0) GK10x class
{ 0x32, 192}, // Kepler Generation (SM 3.2) GK10x class
{ 0x35, 192}, // Kepler Generation (SM 3.5) GK11x class
{ 0x37, 192}, // Kepler Generation (SM 3.7) GK21x class
{ 0x50, 128}, // Maxwell Generation (SM 5.0) GM10x class
{ 0x52, 128}, // Maxwell Generation (SM 5.2) GM20x class
{ 0x53, 128}, // Maxwell Generation (SM 5.3) GM20x class
{ 0x60, 64 }, // Pascal Generation (SM 6.0) GP100 class
{ 0x61, 128}, // Pascal Generation (SM 6.1) GP10x class
{ 0x62, 128}, // Pascal Generation (SM 6.2) GP10x class
{ -1, -1 }
};
int index = 0;
while (nGpuArchCoresPerSM[index].SM != -1)
{
if (nGpuArchCoresPerSM[index].SM == ((major << 4) + minor))
{
return nGpuArchCoresPerSM[index].Cores;
}
index++;
}
// If we don't find the values, we default use the previous one to run properly
printf("MapSMtoCores for SM %d.%d is undefined. Default to use %d Cores/SM\n", major, minor, nGpuArchCoresPerSM[index-1].Cores);
return nGpuArchCoresPerSM[index-1].Cores;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
printf(" Total amount of global memory: %zd bytes\n",
deviceProp.totalGlobalMem);
#if CUDART_VERSION >= 2000
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" CUDA Cores/MP: %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor));
printf(" Total CUDA Cores %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor) * deviceProp.multiProcessorCount);
#endif
printf(" Total amount of constant memory: %zd bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %zd bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %zd bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %zd bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.2f GHz\n",
deviceProp.memoryClockRate * 1e-6f);
printf(" Memory Bus Width: %d bits\n",
deviceProp.memoryBusWidth);
printf(" Number of asynchronous engines: %d\n",
deviceProp.asyncEngineCount);
printf(" It can execute multiple kernels concurrently: %s\n",
deviceProp.concurrentKernels ? "Yes" : "No");
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
/* This sample queries the properties of the CUDA devices present in the system. */
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
inline int _ConvertSMVer2Cores(int major, int minor)
{
// Defines for GPU Architecture types (using the SM version to determine the # of cores per SM
typedef struct
{
int SM; // 0xMm (hexidecimal notation), M = SM Major version, and m = SM minor version
int Cores;
} sSMtoCores;
sSMtoCores nGpuArchCoresPerSM[] =
{
{ 0x20, 32 }, // Fermi Generation (SM 2.0) GF100 class
{ 0x21, 48 }, // Fermi Generation (SM 2.1) GF10x class
{ 0x30, 192}, // Kepler Generation (SM 3.0) GK10x class
{ 0x32, 192}, // Kepler Generation (SM 3.2) GK10x class
{ 0x35, 192}, // Kepler Generation (SM 3.5) GK11x class
{ 0x37, 192}, // Kepler Generation (SM 3.7) GK21x class
{ 0x50, 128}, // Maxwell Generation (SM 5.0) GM10x class
{ 0x52, 128}, // Maxwell Generation (SM 5.2) GM20x class
{ 0x53, 128}, // Maxwell Generation (SM 5.3) GM20x class
{ 0x60, 64 }, // Pascal Generation (SM 6.0) GP100 class
{ 0x61, 128}, // Pascal Generation (SM 6.1) GP10x class
{ 0x62, 128}, // Pascal Generation (SM 6.2) GP10x class
{ -1, -1 }
};
int index = 0;
while (nGpuArchCoresPerSM[index].SM != -1)
{
if (nGpuArchCoresPerSM[index].SM == ((major << 4) + minor))
{
return nGpuArchCoresPerSM[index].Cores;
}
index++;
}
// If we don't find the values, we default use the previous one to run properly
printf("MapSMtoCores for SM %d.%d is undefined. Default to use %d Cores/SM\n", major, minor, nGpuArchCoresPerSM[index-1].Cores);
return nGpuArchCoresPerSM[index-1].Cores;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
printf(" Total amount of global memory: %zd bytes\n",
deviceProp.totalGlobalMem);
#if CUDART_VERSION >= 2000
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" CUDA Cores/MP: %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor));
printf(" Total CUDA Cores %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor) * deviceProp.multiProcessorCount);
#endif
printf(" Total amount of constant memory: %zd bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %zd bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %zd bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %zd bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.2f GHz\n",
deviceProp.memoryClockRate * 1e-6f);
printf(" Memory Bus Width: %d bits\n",
deviceProp.memoryBusWidth);
printf(" Number of asynchronous engines: %d\n",
deviceProp.asyncEngineCount);
printf(" It can execute multiple kernels concurrently: %s\n",
deviceProp.concurrentKernels ? "Yes" : "No");
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | .file "tmpxft_001882b1_00000000-6_dev_properties.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "There is no device supporting CUDA\n"
.align 8
.LC3:
.string "There is no device supporting CUDA.\n"
.align 8
.LC4:
.string "There is 1 device supporting CUDA\n"
.align 8
.LC5:
.string "There are %d devices supporting CUDA\n"
.section .rodata.str1.1
.LC6:
.string "\nDevice %d: \"%s\"\n"
.section .rodata.str1.8
.align 8
.LC7:
.string " Major revision number: %d\n"
.align 8
.LC8:
.string " Minor revision number: %d\n"
.align 8
.LC9:
.string " Total amount of global memory: %zd bytes\n"
.align 8
.LC10:
.string " Number of multiprocessors: %d\n"
.align 8
.LC11:
.string "MapSMtoCores for SM %d.%d is undefined. Default to use %d Cores/SM\n"
.align 8
.LC12:
.string " CUDA Cores/MP: %d\n"
.align 8
.LC13:
.string " Total CUDA Cores %d\n"
.align 8
.LC14:
.string " Total amount of constant memory: %zd bytes\n"
.align 8
.LC15:
.string " Total amount of shared memory per block: %zd bytes\n"
.align 8
.LC16:
.string " Total number of registers available per block: %d\n"
.align 8
.LC17:
.string " Warp size: %d\n"
.align 8
.LC18:
.string " Maximum number of threads per block: %d\n"
.align 8
.LC19:
.string " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.align 8
.LC20:
.string " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.align 8
.LC21:
.string " Maximum memory pitch: %zd bytes\n"
.align 8
.LC22:
.string " Texture alignment: %zd bytes\n"
.align 8
.LC24:
.string " Clock rate: %.2f GHz\n"
.align 8
.LC25:
.string " Memory Clock rate: %.2f GHz\n"
.align 8
.LC26:
.string " Memory Bus Width: %d bits\n"
.align 8
.LC27:
.string " Number of asynchronous engines: %d\n"
.align 8
.LC28:
.string " It can execute multiple kernels concurrently: %s\n"
.align 8
.LC29:
.string " Concurrent copy and execution: %s\n"
.section .rodata.str1.1
.LC30:
.string "\nTEST PASSED\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1168, %rsp
.cfi_def_cfa_offset 1216
movq %fs:40, %rax
movq %rax, 1160(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
je .L25
.L4:
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebx
leaq 128(%rsp), %r13
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
jmp .L17
.L25:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L28:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L8:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movq %r13, %rcx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 488(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 492(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 416(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 516(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 492(%rsp), %r9d
movl 488(%rsp), %edi
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $33, 24(%rsp)
movl $48, 28(%rsp)
movl $48, 32(%rsp)
movl $192, 36(%rsp)
movl $50, 40(%rsp)
movl $192, 44(%rsp)
movl $53, 48(%rsp)
movl $192, 52(%rsp)
movl $55, 56(%rsp)
movl $192, 60(%rsp)
movl $80, 64(%rsp)
movl $128, 68(%rsp)
movl $82, 72(%rsp)
movl $128, 76(%rsp)
movl $83, 80(%rsp)
movl $128, 84(%rsp)
movl $96, 88(%rsp)
movl $64, 92(%rsp)
movl $97, 96(%rsp)
movl $128, 100(%rsp)
movl $98, 104(%rsp)
movl $128, 108(%rsp)
movl $-1, 112(%rsp)
movl $-1, 116(%rsp)
movl %edi, %ecx
sall $4, %ecx
addl %r9d, %ecx
movl $0, %eax
movl $32, %edx
.L11:
movl %eax, %esi
cmpl %edx, %ecx
je .L26
addq $1, %rax
movl 16(%rsp,%rax,8), %edx
cmpl $-1, %edx
jne .L11
movslq %esi, %rsi
movl 20(%rsp,%rsi,8), %r14d
movl %r14d, %r8d
movl %r9d, %ecx
movl %edi, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L10:
movl %r14d, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 492(%rsp), %r9d
movl 488(%rsp), %edi
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $33, 24(%rsp)
movl $48, 28(%rsp)
movl $48, 32(%rsp)
movl $192, 36(%rsp)
movl $50, 40(%rsp)
movl $192, 44(%rsp)
movl $53, 48(%rsp)
movl $192, 52(%rsp)
movl $55, 56(%rsp)
movl $192, 60(%rsp)
movl $80, 64(%rsp)
movl $128, 68(%rsp)
movl $82, 72(%rsp)
movl $128, 76(%rsp)
movl $83, 80(%rsp)
movl $128, 84(%rsp)
movl $96, 88(%rsp)
movl $64, 92(%rsp)
movl $97, 96(%rsp)
movl $128, 100(%rsp)
movl $98, 104(%rsp)
movl $128, 108(%rsp)
movl $-1, 112(%rsp)
movl $-1, 116(%rsp)
movl %edi, %ecx
sall $4, %ecx
addl %r9d, %ecx
movl $0, %eax
movl $32, %edx
.L14:
movl %eax, %esi
cmpl %edx, %ecx
je .L27
addq $1, %rax
movl 16(%rsp,%rax,8), %edx
cmpl $-1, %edx
jne .L14
movslq %esi, %rsi
movl 20(%rsp,%rsi,8), %r14d
movl %r14d, %r8d
movl %r9d, %ecx
movl %edi, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L13:
movl %r14d, %edx
imull 516(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 480(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 424(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 432(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 436(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 448(%rsp), %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 460(%rsp), %r8d
movl 456(%rsp), %ecx
movl 452(%rsp), %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 472(%rsp), %r8d
movl 468(%rsp), %ecx
movl 464(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 440(%rsp), %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 496(%rsp), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 476(%rsp), %xmm0
mulss .LC23(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 736(%rsp), %xmm0
mulss .LC23(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 740(%rsp), %edx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 728(%rsp), %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 704(%rsp)
movq %rbp, %rdx
cmove %r12, %rdx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 512(%rsp)
movq %rbp, %rdx
cmove %r12, %rdx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L5
.L17:
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %ebx, %ebx
jne .L6
movabsq $42945378002703, %rax
cmpq %rax, 488(%rsp)
je .L28
movl 12(%rsp), %edx
cmpl $1, %edx
jne .L8
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L26:
cltq
movl 20(%rsp,%rax,8), %r14d
jmp .L10
.L27:
cltq
movl 20(%rsp,%rax,8), %r14d
jmp .L13
.L5:
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1160(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $1168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC23:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
/* This sample queries the properties of the CUDA devices present in the system. */
// includes, system
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
inline int _ConvertSMVer2Cores(int major, int minor)
{
// Defines for GPU Architecture types (using the SM version to determine the # of cores per SM
typedef struct
{
int SM; // 0xMm (hexidecimal notation), M = SM Major version, and m = SM minor version
int Cores;
} sSMtoCores;
sSMtoCores nGpuArchCoresPerSM[] =
{
{ 0x20, 32 }, // Fermi Generation (SM 2.0) GF100 class
{ 0x21, 48 }, // Fermi Generation (SM 2.1) GF10x class
{ 0x30, 192}, // Kepler Generation (SM 3.0) GK10x class
{ 0x32, 192}, // Kepler Generation (SM 3.2) GK10x class
{ 0x35, 192}, // Kepler Generation (SM 3.5) GK11x class
{ 0x37, 192}, // Kepler Generation (SM 3.7) GK21x class
{ 0x50, 128}, // Maxwell Generation (SM 5.0) GM10x class
{ 0x52, 128}, // Maxwell Generation (SM 5.2) GM20x class
{ 0x53, 128}, // Maxwell Generation (SM 5.3) GM20x class
{ 0x60, 64 }, // Pascal Generation (SM 6.0) GP100 class
{ 0x61, 128}, // Pascal Generation (SM 6.1) GP10x class
{ 0x62, 128}, // Pascal Generation (SM 6.2) GP10x class
{ -1, -1 }
};
int index = 0;
while (nGpuArchCoresPerSM[index].SM != -1)
{
if (nGpuArchCoresPerSM[index].SM == ((major << 4) + minor))
{
return nGpuArchCoresPerSM[index].Cores;
}
index++;
}
// If we don't find the values, we default use the previous one to run properly
printf("MapSMtoCores for SM %d.%d is undefined. Default to use %d Cores/SM\n", major, minor, nGpuArchCoresPerSM[index-1].Cores);
return nGpuArchCoresPerSM[index-1].Cores;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
printf(" Total amount of global memory: %zd bytes\n",
deviceProp.totalGlobalMem);
#if CUDART_VERSION >= 2000
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" CUDA Cores/MP: %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor));
printf(" Total CUDA Cores %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor) * deviceProp.multiProcessorCount);
#endif
printf(" Total amount of constant memory: %zd bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %zd bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %zd bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %zd bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.2f GHz\n",
deviceProp.memoryClockRate * 1e-6f);
printf(" Memory Bus Width: %d bits\n",
deviceProp.memoryBusWidth);
printf(" Number of asynchronous engines: %d\n",
deviceProp.asyncEngineCount);
printf(" It can execute multiple kernels concurrently: %s\n",
deviceProp.concurrentKernels ? "Yes" : "No");
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
/* This sample queries the properties of the CUDA devices present in the system. */
// includes, system
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
inline int _ConvertSMVer2Cores(int major, int minor)
{
// Defines for GPU Architecture types (using the SM version to determine the # of cores per SM
typedef struct
{
int SM; // 0xMm (hexidecimal notation), M = SM Major version, and m = SM minor version
int Cores;
} sSMtoCores;
sSMtoCores nGpuArchCoresPerSM[] =
{
{ 0x20, 32 }, // Fermi Generation (SM 2.0) GF100 class
{ 0x21, 48 }, // Fermi Generation (SM 2.1) GF10x class
{ 0x30, 192}, // Kepler Generation (SM 3.0) GK10x class
{ 0x32, 192}, // Kepler Generation (SM 3.2) GK10x class
{ 0x35, 192}, // Kepler Generation (SM 3.5) GK11x class
{ 0x37, 192}, // Kepler Generation (SM 3.7) GK21x class
{ 0x50, 128}, // Maxwell Generation (SM 5.0) GM10x class
{ 0x52, 128}, // Maxwell Generation (SM 5.2) GM20x class
{ 0x53, 128}, // Maxwell Generation (SM 5.3) GM20x class
{ 0x60, 64 }, // Pascal Generation (SM 6.0) GP100 class
{ 0x61, 128}, // Pascal Generation (SM 6.1) GP10x class
{ 0x62, 128}, // Pascal Generation (SM 6.2) GP10x class
{ -1, -1 }
};
int index = 0;
while (nGpuArchCoresPerSM[index].SM != -1)
{
if (nGpuArchCoresPerSM[index].SM == ((major << 4) + minor))
{
return nGpuArchCoresPerSM[index].Cores;
}
index++;
}
// If we don't find the values, we default use the previous one to run properly
printf("MapSMtoCores for SM %d.%d is undefined. Default to use %d Cores/SM\n", major, minor, nGpuArchCoresPerSM[index-1].Cores);
return nGpuArchCoresPerSM[index-1].Cores;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
printf(" Total amount of global memory: %zd bytes\n",
deviceProp.totalGlobalMem);
#if CUDART_VERSION >= 2000
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" CUDA Cores/MP: %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor));
printf(" Total CUDA Cores %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor) * deviceProp.multiProcessorCount);
#endif
printf(" Total amount of constant memory: %zd bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %zd bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %zd bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %zd bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.2f GHz\n",
deviceProp.memoryClockRate * 1e-6f);
printf(" Memory Bus Width: %d bits\n",
deviceProp.memoryBusWidth);
printf(" Number of asynchronous engines: %d\n",
deviceProp.asyncEngineCount);
printf(" It can execute multiple kernels concurrently: %s\n",
deviceProp.concurrentKernels ? "Yes" : "No");
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
/* This sample queries the properties of the CUDA devices present in the system. */
// includes, system
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
inline int _ConvertSMVer2Cores(int major, int minor)
{
// Defines for GPU Architecture types (using the SM version to determine the # of cores per SM
typedef struct
{
int SM; // 0xMm (hexidecimal notation), M = SM Major version, and m = SM minor version
int Cores;
} sSMtoCores;
sSMtoCores nGpuArchCoresPerSM[] =
{
{ 0x20, 32 }, // Fermi Generation (SM 2.0) GF100 class
{ 0x21, 48 }, // Fermi Generation (SM 2.1) GF10x class
{ 0x30, 192}, // Kepler Generation (SM 3.0) GK10x class
{ 0x32, 192}, // Kepler Generation (SM 3.2) GK10x class
{ 0x35, 192}, // Kepler Generation (SM 3.5) GK11x class
{ 0x37, 192}, // Kepler Generation (SM 3.7) GK21x class
{ 0x50, 128}, // Maxwell Generation (SM 5.0) GM10x class
{ 0x52, 128}, // Maxwell Generation (SM 5.2) GM20x class
{ 0x53, 128}, // Maxwell Generation (SM 5.3) GM20x class
{ 0x60, 64 }, // Pascal Generation (SM 6.0) GP100 class
{ 0x61, 128}, // Pascal Generation (SM 6.1) GP10x class
{ 0x62, 128}, // Pascal Generation (SM 6.2) GP10x class
{ -1, -1 }
};
int index = 0;
while (nGpuArchCoresPerSM[index].SM != -1)
{
if (nGpuArchCoresPerSM[index].SM == ((major << 4) + minor))
{
return nGpuArchCoresPerSM[index].Cores;
}
index++;
}
// If we don't find the values, we default use the previous one to run properly
printf("MapSMtoCores for SM %d.%d is undefined. Default to use %d Cores/SM\n", major, minor, nGpuArchCoresPerSM[index-1].Cores);
return nGpuArchCoresPerSM[index-1].Cores;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
printf(" Total amount of global memory: %zd bytes\n",
deviceProp.totalGlobalMem);
#if CUDART_VERSION >= 2000
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" CUDA Cores/MP: %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor));
printf(" Total CUDA Cores %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor) * deviceProp.multiProcessorCount);
#endif
printf(" Total amount of constant memory: %zd bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %zd bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %zd bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %zd bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.2f GHz\n",
deviceProp.memoryClockRate * 1e-6f);
printf(" Memory Bus Width: %d bits\n",
deviceProp.memoryBusWidth);
printf(" Number of asynchronous engines: %d\n",
deviceProp.asyncEngineCount);
printf(" It can execute multiple kernels concurrently: %s\n",
deviceProp.concurrentKernels ? "Yes" : "No");
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Copyright 1993-2007 NVIDIA Corporation. All rights reserved.
*
* NOTICE TO USER:
*
* This source code is subject to NVIDIA ownership rights under U.S. and
* international Copyright laws. Users and possessors of this source code
* are hereby granted a nonexclusive, royalty-free license to use this code
* in individual and commercial software.
*
* NVIDIA MAKES NO REPRESENTATION ABOUT THE SUITABILITY OF THIS SOURCE
* CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" WITHOUT EXPRESS OR
* IMPLIED WARRANTY OF ANY KIND. NVIDIA DISCLAIMS ALL WARRANTIES WITH
* REGARD TO THIS SOURCE CODE, INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
* IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL,
* OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS
* OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
* OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE
* OR PERFORMANCE OF THIS SOURCE CODE.
*
* U.S. Government End Users. This source code is a "commercial item" as
* that term is defined at 48 C.F.R. 2.101 (OCT 1995), consisting of
* "commercial computer software" and "commercial computer software
* documentation" as such terms are used in 48 C.F.R. 12.212 (SEPT 1995)
* and is provided to the U.S. Government only as a commercial end item.
* Consistent with 48 C.F.R.12.212 and 48 C.F.R. 227.7202-1 through
* 227.7202-4 (JUNE 1995), all U.S. Government End Users acquire the
* source code with only those rights set forth herein.
*
* Any use of this source code in individual and commercial software must
* include, in the user documentation and internal comments to the code,
* the above Disclaimer and U.S. Government End Users Notice.
*/
/* This sample queries the properties of the CUDA devices present in the system. */
// includes, system
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
inline int _ConvertSMVer2Cores(int major, int minor)
{
// Defines for GPU Architecture types (using the SM version to determine the # of cores per SM
typedef struct
{
int SM; // 0xMm (hexidecimal notation), M = SM Major version, and m = SM minor version
int Cores;
} sSMtoCores;
sSMtoCores nGpuArchCoresPerSM[] =
{
{ 0x20, 32 }, // Fermi Generation (SM 2.0) GF100 class
{ 0x21, 48 }, // Fermi Generation (SM 2.1) GF10x class
{ 0x30, 192}, // Kepler Generation (SM 3.0) GK10x class
{ 0x32, 192}, // Kepler Generation (SM 3.2) GK10x class
{ 0x35, 192}, // Kepler Generation (SM 3.5) GK11x class
{ 0x37, 192}, // Kepler Generation (SM 3.7) GK21x class
{ 0x50, 128}, // Maxwell Generation (SM 5.0) GM10x class
{ 0x52, 128}, // Maxwell Generation (SM 5.2) GM20x class
{ 0x53, 128}, // Maxwell Generation (SM 5.3) GM20x class
{ 0x60, 64 }, // Pascal Generation (SM 6.0) GP100 class
{ 0x61, 128}, // Pascal Generation (SM 6.1) GP10x class
{ 0x62, 128}, // Pascal Generation (SM 6.2) GP10x class
{ -1, -1 }
};
int index = 0;
while (nGpuArchCoresPerSM[index].SM != -1)
{
if (nGpuArchCoresPerSM[index].SM == ((major << 4) + minor))
{
return nGpuArchCoresPerSM[index].Cores;
}
index++;
}
// If we don't find the values, we default use the previous one to run properly
printf("MapSMtoCores for SM %d.%d is undefined. Default to use %d Cores/SM\n", major, minor, nGpuArchCoresPerSM[index-1].Cores);
return nGpuArchCoresPerSM[index-1].Cores;
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int
main( int argc, char** argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0)
printf("There is no device supporting CUDA\n");
int dev;
for (dev = 0; dev < deviceCount; ++dev) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999)
printf("There is no device supporting CUDA.\n");
else if (deviceCount == 1)
printf("There is 1 device supporting CUDA\n");
else
printf("There are %d devices supporting CUDA\n", deviceCount);
}
printf("\nDevice %d: \"%s\"\n", dev, deviceProp.name);
printf(" Major revision number: %d\n",
deviceProp.major);
printf(" Minor revision number: %d\n",
deviceProp.minor);
printf(" Total amount of global memory: %zd bytes\n",
deviceProp.totalGlobalMem);
#if CUDART_VERSION >= 2000
printf(" Number of multiprocessors: %d\n",
deviceProp.multiProcessorCount);
printf(" CUDA Cores/MP: %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor));
printf(" Total CUDA Cores %d\n",
_ConvertSMVer2Cores(deviceProp.major, deviceProp.minor) * deviceProp.multiProcessorCount);
#endif
printf(" Total amount of constant memory: %zd bytes\n",
deviceProp.totalConstMem);
printf(" Total amount of shared memory per block: %zd bytes\n",
deviceProp.sharedMemPerBlock);
printf(" Total number of registers available per block: %d\n",
deviceProp.regsPerBlock);
printf(" Warp size: %d\n",
deviceProp.warpSize);
printf(" Maximum number of threads per block: %d\n",
deviceProp.maxThreadsPerBlock);
printf(" Maximum sizes of each dimension of a block: %d x %d x %d\n",
deviceProp.maxThreadsDim[0],
deviceProp.maxThreadsDim[1],
deviceProp.maxThreadsDim[2]);
printf(" Maximum sizes of each dimension of a grid: %d x %d x %d\n",
deviceProp.maxGridSize[0],
deviceProp.maxGridSize[1],
deviceProp.maxGridSize[2]);
printf(" Maximum memory pitch: %zd bytes\n",
deviceProp.memPitch);
printf(" Texture alignment: %zd bytes\n",
deviceProp.textureAlignment);
printf(" Clock rate: %.2f GHz\n",
deviceProp.clockRate * 1e-6f);
printf(" Memory Clock rate: %.2f GHz\n",
deviceProp.memoryClockRate * 1e-6f);
printf(" Memory Bus Width: %d bits\n",
deviceProp.memoryBusWidth);
printf(" Number of asynchronous engines: %d\n",
deviceProp.asyncEngineCount);
printf(" It can execute multiple kernels concurrently: %s\n",
deviceProp.concurrentKernels ? "Yes" : "No");
#if CUDART_VERSION >= 2000
printf(" Concurrent copy and execution: %s\n",
deviceProp.deviceOverlap ? "Yes" : "No");
#endif
}
printf("\nTEST PASSED\n");
} | .text
.file "dev_properties.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jne .LBB0_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB0_2:
cmpl $0, 12(%rsp)
jle .LBB0_13
# %bb.3: # %.lr.ph
leaq 16(%rsp), %rbx
movl $.L.str.23, %r14d
xorl %ebp, %ebp
jmp .LBB0_7
.LBB0_4: # in Loop: Header=BB0_7 Depth=1
movl $.Lstr.3, %edi
.LBB0_5: # in Loop: Header=BB0_7 Depth=1
callq puts@PLT
.LBB0_6: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 380(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
cvtsi2ssl 364(%rsp), %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movl 628(%rsp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movl 616(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 592(%rsp)
movl $.L.str.22, %esi
cmoveq %r14, %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB0_13
.LBB0_7: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %ebp, %ebp
jne .LBB0_6
# %bb.8: # in Loop: Header=BB0_7 Depth=1
cmpl $9999, 376(%rsp) # imm = 0x270F
jne .LBB0_10
# %bb.9: # in Loop: Header=BB0_7 Depth=1
cmpl $9999, 380(%rsp) # imm = 0x270F
je .LBB0_4
.LBB0_10: # in Loop: Header=BB0_7 Depth=1
movl 12(%rsp), %esi
cmpl $1, %esi
jne .LBB0_12
# %bb.11: # in Loop: Header=BB0_7 Depth=1
movl $.Lstr.2, %edi
jmp .LBB0_5
.LBB0_12: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB0_6
.LBB0_13: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "There are %d devices supporting CUDA\n"
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nDevice %d: \"%s\"\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Major revision number: %d\n"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Minor revision number: %d\n"
.size .L.str.6, 53
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Total amount of global memory: %zd bytes\n"
.size .L.str.7, 60
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Total amount of constant memory: %zd bytes\n"
.size .L.str.8, 60
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Total amount of shared memory per block: %zd bytes\n"
.size .L.str.9, 60
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Total number of registers available per block: %d\n"
.size .L.str.10, 53
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Warp size: %d\n"
.size .L.str.11, 53
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Maximum number of threads per block: %d\n"
.size .L.str.12, 53
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.size .L.str.13, 63
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.size .L.str.14, 63
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Maximum memory pitch: %zd bytes\n"
.size .L.str.15, 60
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " Texture alignment: %zd bytes\n"
.size .L.str.16, 60
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " Clock rate: %.2f GHz\n"
.size .L.str.17, 59
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " Memory Clock rate: %.2f GHz\n"
.size .L.str.18, 59
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " Memory Bus Width: %d bits\n"
.size .L.str.19, 58
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " Number of asynchronous engines: %d\n"
.size .L.str.20, 53
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " It can execute multiple kernels concurrently: %s\n"
.size .L.str.21, 53
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Yes"
.size .L.str.22, 4
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "No"
.size .L.str.23, 3
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There is no device supporting CUDA"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nTEST PASSED"
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "There is 1 device supporting CUDA"
.size .Lstr.2, 34
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "There is no device supporting CUDA."
.size .Lstr.3, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001882b1_00000000-6_dev_properties.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Yes"
.LC1:
.string "No"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "There is no device supporting CUDA\n"
.align 8
.LC3:
.string "There is no device supporting CUDA.\n"
.align 8
.LC4:
.string "There is 1 device supporting CUDA\n"
.align 8
.LC5:
.string "There are %d devices supporting CUDA\n"
.section .rodata.str1.1
.LC6:
.string "\nDevice %d: \"%s\"\n"
.section .rodata.str1.8
.align 8
.LC7:
.string " Major revision number: %d\n"
.align 8
.LC8:
.string " Minor revision number: %d\n"
.align 8
.LC9:
.string " Total amount of global memory: %zd bytes\n"
.align 8
.LC10:
.string " Number of multiprocessors: %d\n"
.align 8
.LC11:
.string "MapSMtoCores for SM %d.%d is undefined. Default to use %d Cores/SM\n"
.align 8
.LC12:
.string " CUDA Cores/MP: %d\n"
.align 8
.LC13:
.string " Total CUDA Cores %d\n"
.align 8
.LC14:
.string " Total amount of constant memory: %zd bytes\n"
.align 8
.LC15:
.string " Total amount of shared memory per block: %zd bytes\n"
.align 8
.LC16:
.string " Total number of registers available per block: %d\n"
.align 8
.LC17:
.string " Warp size: %d\n"
.align 8
.LC18:
.string " Maximum number of threads per block: %d\n"
.align 8
.LC19:
.string " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.align 8
.LC20:
.string " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.align 8
.LC21:
.string " Maximum memory pitch: %zd bytes\n"
.align 8
.LC22:
.string " Texture alignment: %zd bytes\n"
.align 8
.LC24:
.string " Clock rate: %.2f GHz\n"
.align 8
.LC25:
.string " Memory Clock rate: %.2f GHz\n"
.align 8
.LC26:
.string " Memory Bus Width: %d bits\n"
.align 8
.LC27:
.string " Number of asynchronous engines: %d\n"
.align 8
.LC28:
.string " It can execute multiple kernels concurrently: %s\n"
.align 8
.LC29:
.string " Concurrent copy and execution: %s\n"
.section .rodata.str1.1
.LC30:
.string "\nTEST PASSED\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1168, %rsp
.cfi_def_cfa_offset 1216
movq %fs:40, %rax
movq %rax, 1160(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
je .L25
.L4:
cmpl $0, 12(%rsp)
jle .L5
movl $0, %ebx
leaq 128(%rsp), %r13
leaq .LC1(%rip), %r12
leaq .LC0(%rip), %rbp
jmp .L17
.L25:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L28:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L8:
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L6:
movq %r13, %rcx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 488(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 492(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 416(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 516(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 492(%rsp), %r9d
movl 488(%rsp), %edi
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $33, 24(%rsp)
movl $48, 28(%rsp)
movl $48, 32(%rsp)
movl $192, 36(%rsp)
movl $50, 40(%rsp)
movl $192, 44(%rsp)
movl $53, 48(%rsp)
movl $192, 52(%rsp)
movl $55, 56(%rsp)
movl $192, 60(%rsp)
movl $80, 64(%rsp)
movl $128, 68(%rsp)
movl $82, 72(%rsp)
movl $128, 76(%rsp)
movl $83, 80(%rsp)
movl $128, 84(%rsp)
movl $96, 88(%rsp)
movl $64, 92(%rsp)
movl $97, 96(%rsp)
movl $128, 100(%rsp)
movl $98, 104(%rsp)
movl $128, 108(%rsp)
movl $-1, 112(%rsp)
movl $-1, 116(%rsp)
movl %edi, %ecx
sall $4, %ecx
addl %r9d, %ecx
movl $0, %eax
movl $32, %edx
.L11:
movl %eax, %esi
cmpl %edx, %ecx
je .L26
addq $1, %rax
movl 16(%rsp,%rax,8), %edx
cmpl $-1, %edx
jne .L11
movslq %esi, %rsi
movl 20(%rsp,%rsi,8), %r14d
movl %r14d, %r8d
movl %r9d, %ecx
movl %edi, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L10:
movl %r14d, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 492(%rsp), %r9d
movl 488(%rsp), %edi
movl $32, 16(%rsp)
movl $32, 20(%rsp)
movl $33, 24(%rsp)
movl $48, 28(%rsp)
movl $48, 32(%rsp)
movl $192, 36(%rsp)
movl $50, 40(%rsp)
movl $192, 44(%rsp)
movl $53, 48(%rsp)
movl $192, 52(%rsp)
movl $55, 56(%rsp)
movl $192, 60(%rsp)
movl $80, 64(%rsp)
movl $128, 68(%rsp)
movl $82, 72(%rsp)
movl $128, 76(%rsp)
movl $83, 80(%rsp)
movl $128, 84(%rsp)
movl $96, 88(%rsp)
movl $64, 92(%rsp)
movl $97, 96(%rsp)
movl $128, 100(%rsp)
movl $98, 104(%rsp)
movl $128, 108(%rsp)
movl $-1, 112(%rsp)
movl $-1, 116(%rsp)
movl %edi, %ecx
sall $4, %ecx
addl %r9d, %ecx
movl $0, %eax
movl $32, %edx
.L14:
movl %eax, %esi
cmpl %edx, %ecx
je .L27
addq $1, %rax
movl 16(%rsp,%rax,8), %edx
cmpl $-1, %edx
jne .L14
movslq %esi, %rsi
movl 20(%rsp,%rsi,8), %r14d
movl %r14d, %r8d
movl %r9d, %ecx
movl %edi, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L13:
movl %r14d, %edx
imull 516(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 480(%rsp), %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 424(%rsp), %rdx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 432(%rsp), %edx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 436(%rsp), %edx
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 448(%rsp), %edx
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 460(%rsp), %r8d
movl 456(%rsp), %ecx
movl 452(%rsp), %edx
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 472(%rsp), %r8d
movl 468(%rsp), %ecx
movl 464(%rsp), %edx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 440(%rsp), %rdx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 496(%rsp), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 476(%rsp), %xmm0
mulss .LC23(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC24(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2ssl 736(%rsp), %xmm0
mulss .LC23(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl 740(%rsp), %edx
leaq .LC26(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 728(%rsp), %edx
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 704(%rsp)
movq %rbp, %rdx
cmove %r12, %rdx
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 512(%rsp)
movq %rbp, %rdx
cmove %r12, %rdx
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L5
.L17:
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
testl %ebx, %ebx
jne .L6
movabsq $42945378002703, %rax
cmpq %rax, 488(%rsp)
je .L28
movl 12(%rsp), %edx
cmpl $1, %edx
jne .L8
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L6
.L26:
cltq
movl 20(%rsp,%rax,8), %r14d
jmp .L10
.L27:
cltq
movl 20(%rsp,%rax,8), %r14d
jmp .L13
.L5:
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1160(%rsp), %rax
subq %fs:40, %rax
jne .L29
movl $0, %eax
addq $1168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC23:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dev_properties.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jne .LBB0_2
# %bb.1:
movl $.Lstr, %edi
callq puts@PLT
.LBB0_2:
cmpl $0, 12(%rsp)
jle .LBB0_13
# %bb.3: # %.lr.ph
leaq 16(%rsp), %rbx
movl $.L.str.23, %r14d
xorl %ebp, %ebp
jmp .LBB0_7
.LBB0_4: # in Loop: Header=BB0_7 Depth=1
movl $.Lstr.3, %edi
.LBB0_5: # in Loop: Header=BB0_7 Depth=1
callq puts@PLT
.LBB0_6: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.4, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
movl 376(%rsp), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 380(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 320(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 324(%rsp), %esi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movq 328(%rsp), %rsi
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
movq 384(%rsp), %rsi
movl $.L.str.16, %edi
xorl %eax, %eax
callq printf
cvtsi2ssl 364(%rsp), %xmm0
movss .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %edi
movb $1, %al
callq printf
xorps %xmm0, %xmm0
cvtsi2ssl 624(%rsp), %xmm0
mulss .LCPI0_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movl 628(%rsp), %esi
movl $.L.str.19, %edi
xorl %eax, %eax
callq printf
movl 616(%rsp), %esi
movl $.L.str.20, %edi
xorl %eax, %eax
callq printf
cmpl $0, 592(%rsp)
movl $.L.str.22, %esi
cmoveq %r14, %rsi
movl $.L.str.21, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB0_13
.LBB0_7: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %ebp, %ebp
jne .LBB0_6
# %bb.8: # in Loop: Header=BB0_7 Depth=1
cmpl $9999, 376(%rsp) # imm = 0x270F
jne .LBB0_10
# %bb.9: # in Loop: Header=BB0_7 Depth=1
cmpl $9999, 380(%rsp) # imm = 0x270F
je .LBB0_4
.LBB0_10: # in Loop: Header=BB0_7 Depth=1
movl 12(%rsp), %esi
cmpl $1, %esi
jne .LBB0_12
# %bb.11: # in Loop: Header=BB0_7 Depth=1
movl $.Lstr.2, %edi
jmp .LBB0_5
.LBB0_12: # in Loop: Header=BB0_7 Depth=1
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
jmp .LBB0_6
.LBB0_13: # %._crit_edge
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "There are %d devices supporting CUDA\n"
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\nDevice %d: \"%s\"\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " Major revision number: %d\n"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " Minor revision number: %d\n"
.size .L.str.6, 53
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " Total amount of global memory: %zd bytes\n"
.size .L.str.7, 60
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " Total amount of constant memory: %zd bytes\n"
.size .L.str.8, 60
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " Total amount of shared memory per block: %zd bytes\n"
.size .L.str.9, 60
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz " Total number of registers available per block: %d\n"
.size .L.str.10, 53
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz " Warp size: %d\n"
.size .L.str.11, 53
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " Maximum number of threads per block: %d\n"
.size .L.str.12, 53
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz " Maximum sizes of each dimension of a block: %d x %d x %d\n"
.size .L.str.13, 63
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz " Maximum sizes of each dimension of a grid: %d x %d x %d\n"
.size .L.str.14, 63
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz " Maximum memory pitch: %zd bytes\n"
.size .L.str.15, 60
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz " Texture alignment: %zd bytes\n"
.size .L.str.16, 60
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz " Clock rate: %.2f GHz\n"
.size .L.str.17, 59
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz " Memory Clock rate: %.2f GHz\n"
.size .L.str.18, 59
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz " Memory Bus Width: %d bits\n"
.size .L.str.19, 58
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz " Number of asynchronous engines: %d\n"
.size .L.str.20, 53
.type .L.str.21,@object # @.str.21
.L.str.21:
.asciz " It can execute multiple kernels concurrently: %s\n"
.size .L.str.21, 53
.type .L.str.22,@object # @.str.22
.L.str.22:
.asciz "Yes"
.size .L.str.22, 4
.type .L.str.23,@object # @.str.23
.L.str.23:
.asciz "No"
.size .L.str.23, 3
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "There is no device supporting CUDA"
.size .Lstr, 35
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nTEST PASSED"
.size .Lstr.1, 13
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "There is 1 device supporting CUDA"
.size .Lstr.2, 34
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "There is no device supporting CUDA."
.size .Lstr.3, 36
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "vec_kernels.cuh"
#include "stddef.h"
#include <cmath>
__global__
void mat_transpose(double *X, double *Xt, size_t m, size_t n)
{
size_t gid = threadIdx.x + blockIdx.x * blockDim.x;
if (gid >= m*n)
return;
size_t row = gid / n;
size_t col = gid % n;
Xt[col * m + row] = X[row * n + col];
}
__global__
void vec_dot_mat(double *X, double *y, double *out, size_t m, size_t n)
{
size_t row_idx = threadIdx.x + blockDim.x * blockIdx.x;
if (row_idx >= m)
return;
out[row_idx] = 0.0;
double accum = 0.0;
for (size_t i = 0; i < n; i++) {
accum += X[row_idx * n + i] * y[i];
}
out[row_idx] = accum;
}
__global__
void vec_add(double *a, double *b, double *out, size_t stride, size_t n)
{
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
if (idx < n)
out[idx] = a[idx] + b[idx];
}
__global__
void vec_dot_product(double *a, double *b, double *out, size_t stride, size_t n)
{
extern __shared__ double temp[];
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
temp[tid] = (idx < n) ? a[idx] * b[idx] : 0;
__syncthreads();
for (size_t shf = blockDim.x / 2; shf > 0; shf >>= 1) {
if (tid < shf) {
temp[tid] += temp[tid + shf];
}
__syncthreads();
}
if (tid == 0)
out[blockIdx.x] = temp[0];
}
__global__
void vec_scalar_mul(double *a, double *out, double c, size_t stride, size_t n)
{
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
if (idx < n)
out[idx] = a[idx] * c;
}
__global__
void vec_sigmoid(double *a, double *out, size_t stride, size_t n)
{
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
if (idx < n)
out[idx] = 1 / (1 + exp(-a[idx]));
}
__global__
void vec_logloss(double *h, double *y, double *out, size_t stride, size_t n)
{
extern __shared__ double temp[];
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
if (idx < n) {
temp[tid] = -(y[idx]) * log(h[idx]) - (1 - (y[idx])) * log(1 - (h[idx]));
} else {
temp[tid] = 0;
}
__syncthreads();
for (size_t shf = blockDim.x / 2; shf > 0; shf >>= 1) {
if (tid < shf) {
temp[tid] += temp[tid + shf];
}
__syncthreads();
}
if (tid == 0)
out[blockIdx.x] = temp[0];
}
__global__
void vec_dot_asym(double *a, double *b, double *out, size_t a_stride, size_t b_stride, size_t a_n, size_t b_n)
{
extern __shared__ double temp[];
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t a_idx = tid * a_stride;
size_t b_idx = tid * b_stride;
if (a_idx < a_n && b_idx < b_n)
temp[tid] = a[a_idx] * b[b_idx];
else
temp[tid] = 0;
__syncthreads();
for (size_t shf = blockDim.x / 2; shf > 0; shf >>= 1) {
if (tid < shf)
temp[tid] += temp[tid + shf];
__syncthreads();
}
if (tid == 0)
out[blockIdx.x] = temp[0];
} | .file "tmpxft_0002b88b_00000000-6_vec_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13mat_transposePdS_mmPdS_mm
.type _Z37__device_stub__Z13mat_transposePdS_mmPdS_mm, @function
_Z37__device_stub__Z13mat_transposePdS_mmPdS_mm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13mat_transposePdS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13mat_transposePdS_mmPdS_mm, .-_Z37__device_stub__Z13mat_transposePdS_mmPdS_mm
.globl _Z13mat_transposePdS_mm
.type _Z13mat_transposePdS_mm, @function
_Z13mat_transposePdS_mm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13mat_transposePdS_mmPdS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13mat_transposePdS_mm, .-_Z13mat_transposePdS_mm
.globl _Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm
.type _Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm, @function
_Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11vec_dot_matPdS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm, .-_Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm
.globl _Z11vec_dot_matPdS_S_mm
.type _Z11vec_dot_matPdS_S_mm, @function
_Z11vec_dot_matPdS_S_mm:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11vec_dot_matPdS_S_mm, .-_Z11vec_dot_matPdS_S_mm
.globl _Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm
.type _Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm, @function
_Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7vec_addPdS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm, .-_Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm
.globl _Z7vec_addPdS_S_mm
.type _Z7vec_addPdS_S_mm, @function
_Z7vec_addPdS_S_mm:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z7vec_addPdS_S_mm, .-_Z7vec_addPdS_S_mm
.globl _Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm
.type _Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm, @function
_Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm:
.LFB2057:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15vec_dot_productPdS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm, .-_Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm
.globl _Z15vec_dot_productPdS_S_mm
.type _Z15vec_dot_productPdS_S_mm, @function
_Z15vec_dot_productPdS_S_mm:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15vec_dot_productPdS_S_mm, .-_Z15vec_dot_productPdS_S_mm
.globl _Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm
.type _Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm, @function
_Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm:
.LFB2059:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14vec_scalar_mulPdS_dmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm, .-_Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm
.globl _Z14vec_scalar_mulPdS_dmm
.type _Z14vec_scalar_mulPdS_dmm, @function
_Z14vec_scalar_mulPdS_dmm:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z14vec_scalar_mulPdS_dmm, .-_Z14vec_scalar_mulPdS_dmm
.globl _Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm
.type _Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm, @function
_Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm:
.LFB2061:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11vec_sigmoidPdS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm, .-_Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm
.globl _Z11vec_sigmoidPdS_mm
.type _Z11vec_sigmoidPdS_mm, @function
_Z11vec_sigmoidPdS_mm:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z11vec_sigmoidPdS_mm, .-_Z11vec_sigmoidPdS_mm
.globl _Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm
.type _Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm, @function
_Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm:
.LFB2063:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11vec_loglossPdS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm, .-_Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm
.globl _Z11vec_loglossPdS_S_mm
.type _Z11vec_loglossPdS_S_mm, @function
_Z11vec_loglossPdS_S_mm:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z11vec_loglossPdS_S_mm, .-_Z11vec_loglossPdS_S_mm
.globl _Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm
.type _Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm, @function
_Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm:
.LFB2065:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12vec_dot_asymPdS_S_mmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm, .-_Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm
.globl _Z12vec_dot_asymPdS_S_mmmm
.type _Z12vec_dot_asymPdS_S_mmmm, @function
_Z12vec_dot_asymPdS_S_mmmm:
.LFB2066:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z12vec_dot_asymPdS_S_mmmm, .-_Z12vec_dot_asymPdS_S_mmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12vec_dot_asymPdS_S_mmmm"
.LC1:
.string "_Z11vec_loglossPdS_S_mm"
.LC2:
.string "_Z11vec_sigmoidPdS_mm"
.LC3:
.string "_Z14vec_scalar_mulPdS_dmm"
.LC4:
.string "_Z15vec_dot_productPdS_S_mm"
.LC5:
.string "_Z7vec_addPdS_S_mm"
.LC6:
.string "_Z11vec_dot_matPdS_S_mm"
.LC7:
.string "_Z13mat_transposePdS_mm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2068:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vec_dot_asymPdS_S_mmmm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vec_loglossPdS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vec_sigmoidPdS_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14vec_scalar_mulPdS_dmm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15vec_dot_productPdS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vec_addPdS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vec_dot_matPdS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mat_transposePdS_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "vec_kernels.cuh"
#include "stddef.h"
#include <cmath>
__global__
void mat_transpose(double *X, double *Xt, size_t m, size_t n)
{
size_t gid = threadIdx.x + blockIdx.x * blockDim.x;
if (gid >= m*n)
return;
size_t row = gid / n;
size_t col = gid % n;
Xt[col * m + row] = X[row * n + col];
}
__global__
void vec_dot_mat(double *X, double *y, double *out, size_t m, size_t n)
{
size_t row_idx = threadIdx.x + blockDim.x * blockIdx.x;
if (row_idx >= m)
return;
out[row_idx] = 0.0;
double accum = 0.0;
for (size_t i = 0; i < n; i++) {
accum += X[row_idx * n + i] * y[i];
}
out[row_idx] = accum;
}
__global__
void vec_add(double *a, double *b, double *out, size_t stride, size_t n)
{
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
if (idx < n)
out[idx] = a[idx] + b[idx];
}
__global__
void vec_dot_product(double *a, double *b, double *out, size_t stride, size_t n)
{
extern __shared__ double temp[];
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
temp[tid] = (idx < n) ? a[idx] * b[idx] : 0;
__syncthreads();
for (size_t shf = blockDim.x / 2; shf > 0; shf >>= 1) {
if (tid < shf) {
temp[tid] += temp[tid + shf];
}
__syncthreads();
}
if (tid == 0)
out[blockIdx.x] = temp[0];
}
__global__
void vec_scalar_mul(double *a, double *out, double c, size_t stride, size_t n)
{
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
if (idx < n)
out[idx] = a[idx] * c;
}
__global__
void vec_sigmoid(double *a, double *out, size_t stride, size_t n)
{
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
if (idx < n)
out[idx] = 1 / (1 + exp(-a[idx]));
}
__global__
void vec_logloss(double *h, double *y, double *out, size_t stride, size_t n)
{
extern __shared__ double temp[];
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t idx = gid * stride;
if (idx < n) {
temp[tid] = -(y[idx]) * log(h[idx]) - (1 - (y[idx])) * log(1 - (h[idx]));
} else {
temp[tid] = 0;
}
__syncthreads();
for (size_t shf = blockDim.x / 2; shf > 0; shf >>= 1) {
if (tid < shf) {
temp[tid] += temp[tid + shf];
}
__syncthreads();
}
if (tid == 0)
out[blockIdx.x] = temp[0];
}
__global__
void vec_dot_asym(double *a, double *b, double *out, size_t a_stride, size_t b_stride, size_t a_n, size_t b_n)
{
extern __shared__ double temp[];
size_t tid = threadIdx.x;
size_t gid = blockIdx.x * blockDim.x + tid;
size_t a_idx = tid * a_stride;
size_t b_idx = tid * b_stride;
if (a_idx < a_n && b_idx < b_n)
temp[tid] = a[a_idx] * b[b_idx];
else
temp[tid] = 0;
__syncthreads();
for (size_t shf = blockDim.x / 2; shf > 0; shf >>= 1) {
if (tid < shf)
temp[tid] += temp[tid + shf];
__syncthreads();
}
if (tid == 0)
out[blockIdx.x] = temp[0];
} | #ifndef CUDA_STATS_VEC_KERNELS_CUH_
#define CUDA_STATS_VEC_KERNELS_CUH_
#include "hip/hip_runtime.h"
#include "stddef.h"
__global__
void mat_transpose(double *X, double *Xt, size_t m, size_t n);
__global__
void vec_add(double *a, double *b, double *out, size_t stride, size_t n);
__global__
void vec_dot_product(double *a, double *b, double *out, size_t stride, size_t n);
__global__
void vec_scalar_mul(double *a, double *out, double c, size_t stride, size_t n);
__global__
void vec_sigmoid(double *a, double *out, size_t stride, size_t n);
__global__
void vec_logloss(double *h, double *y, double *out, size_t stride, size_t n);
__global__
void vec_dot_asym(double *a, double *b, double *out, size_t a_stride, size_t b_stride, size_t a_n, size_t b_n);
__global__
void vec_dot_mat(double *X, double *y, double *out, size_t m, size_t n);
#endif // CUDA_STATS_VEC_KERNELS_CUH_ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef CUDA_STATS_VEC_KERNELS_CUH_
#define CUDA_STATS_VEC_KERNELS_CUH_
#include "hip/hip_runtime.h"
#include "stddef.h"
__global__
void mat_transpose(double *X, double *Xt, size_t m, size_t n);
__global__
void vec_add(double *a, double *b, double *out, size_t stride, size_t n);
__global__
void vec_dot_product(double *a, double *b, double *out, size_t stride, size_t n);
__global__
void vec_scalar_mul(double *a, double *out, double c, size_t stride, size_t n);
__global__
void vec_sigmoid(double *a, double *out, size_t stride, size_t n);
__global__
void vec_logloss(double *h, double *y, double *out, size_t stride, size_t n);
__global__
void vec_dot_asym(double *a, double *b, double *out, size_t a_stride, size_t b_stride, size_t a_n, size_t b_n);
__global__
void vec_dot_mat(double *X, double *y, double *out, size_t m, size_t n);
#endif // CUDA_STATS_VEC_KERNELS_CUH_ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef CUDA_STATS_VEC_KERNELS_CUH_
#define CUDA_STATS_VEC_KERNELS_CUH_
#include "hip/hip_runtime.h"
#include "stddef.h"
__global__
void mat_transpose(double *X, double *Xt, size_t m, size_t n);
__global__
void vec_add(double *a, double *b, double *out, size_t stride, size_t n);
__global__
void vec_dot_product(double *a, double *b, double *out, size_t stride, size_t n);
__global__
void vec_scalar_mul(double *a, double *out, double c, size_t stride, size_t n);
__global__
void vec_sigmoid(double *a, double *out, size_t stride, size_t n);
__global__
void vec_logloss(double *h, double *y, double *out, size_t stride, size_t n);
__global__
void vec_dot_asym(double *a, double *b, double *out, size_t a_stride, size_t b_stride, size_t a_n, size_t b_n);
__global__
void vec_dot_mat(double *X, double *y, double *out, size_t m, size_t n);
#endif // CUDA_STATS_VEC_KERNELS_CUH_ | .text
.file "vec_kernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002b88b_00000000-6_vec_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13mat_transposePdS_mmPdS_mm
.type _Z37__device_stub__Z13mat_transposePdS_mmPdS_mm, @function
_Z37__device_stub__Z13mat_transposePdS_mmPdS_mm:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13mat_transposePdS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z13mat_transposePdS_mmPdS_mm, .-_Z37__device_stub__Z13mat_transposePdS_mmPdS_mm
.globl _Z13mat_transposePdS_mm
.type _Z13mat_transposePdS_mm, @function
_Z13mat_transposePdS_mm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13mat_transposePdS_mmPdS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z13mat_transposePdS_mm, .-_Z13mat_transposePdS_mm
.globl _Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm
.type _Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm, @function
_Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm:
.LFB2053:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11vec_dot_matPdS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm, .-_Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm
.globl _Z11vec_dot_matPdS_S_mm
.type _Z11vec_dot_matPdS_S_mm, @function
_Z11vec_dot_matPdS_S_mm:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11vec_dot_matPdS_S_mmPdS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z11vec_dot_matPdS_S_mm, .-_Z11vec_dot_matPdS_S_mm
.globl _Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm
.type _Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm, @function
_Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm:
.LFB2055:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7vec_addPdS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm, .-_Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm
.globl _Z7vec_addPdS_S_mm
.type _Z7vec_addPdS_S_mm, @function
_Z7vec_addPdS_S_mm:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z7vec_addPdS_S_mmPdS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z7vec_addPdS_S_mm, .-_Z7vec_addPdS_S_mm
.globl _Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm
.type _Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm, @function
_Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm:
.LFB2057:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15vec_dot_productPdS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm, .-_Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm
.globl _Z15vec_dot_productPdS_S_mm
.type _Z15vec_dot_productPdS_S_mm, @function
_Z15vec_dot_productPdS_S_mm:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15vec_dot_productPdS_S_mmPdS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z15vec_dot_productPdS_S_mm, .-_Z15vec_dot_productPdS_S_mm
.globl _Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm
.type _Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm, @function
_Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm:
.LFB2059:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L39
.L35:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L40
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14vec_scalar_mulPdS_dmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L35
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm, .-_Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm
.globl _Z14vec_scalar_mulPdS_dmm
.type _Z14vec_scalar_mulPdS_dmm, @function
_Z14vec_scalar_mulPdS_dmm:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14vec_scalar_mulPdS_dmmPdS_dmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z14vec_scalar_mulPdS_dmm, .-_Z14vec_scalar_mulPdS_dmm
.globl _Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm
.type _Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm, @function
_Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm:
.LFB2061:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L47
.L43:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11vec_sigmoidPdS_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L43
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2061:
.size _Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm, .-_Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm
.globl _Z11vec_sigmoidPdS_mm
.type _Z11vec_sigmoidPdS_mm, @function
_Z11vec_sigmoidPdS_mm:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11vec_sigmoidPdS_mmPdS_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z11vec_sigmoidPdS_mm, .-_Z11vec_sigmoidPdS_mm
.globl _Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm
.type _Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm, @function
_Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm:
.LFB2063:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L55
.L51:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L56
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L55:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11vec_loglossPdS_S_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L51
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm, .-_Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm
.globl _Z11vec_loglossPdS_S_mm
.type _Z11vec_loglossPdS_S_mm, @function
_Z11vec_loglossPdS_S_mm:
.LFB2064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11vec_loglossPdS_S_mmPdS_S_mm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z11vec_loglossPdS_S_mm, .-_Z11vec_loglossPdS_S_mm
.globl _Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm
.type _Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm, @function
_Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm:
.LFB2065:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12vec_dot_asymPdS_S_mmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm, .-_Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm
.globl _Z12vec_dot_asymPdS_S_mmmm
.type _Z12vec_dot_asymPdS_S_mmmm, @function
_Z12vec_dot_asymPdS_S_mmmm:
.LFB2066:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z12vec_dot_asymPdS_S_mmmmPdS_S_mmmm
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z12vec_dot_asymPdS_S_mmmm, .-_Z12vec_dot_asymPdS_S_mmmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12vec_dot_asymPdS_S_mmmm"
.LC1:
.string "_Z11vec_loglossPdS_S_mm"
.LC2:
.string "_Z11vec_sigmoidPdS_mm"
.LC3:
.string "_Z14vec_scalar_mulPdS_dmm"
.LC4:
.string "_Z15vec_dot_productPdS_S_mm"
.LC5:
.string "_Z7vec_addPdS_S_mm"
.LC6:
.string "_Z11vec_dot_matPdS_S_mm"
.LC7:
.string "_Z13mat_transposePdS_mm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2068:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12vec_dot_asymPdS_S_mmmm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vec_loglossPdS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vec_sigmoidPdS_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14vec_scalar_mulPdS_dmm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z15vec_dot_productPdS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7vec_addPdS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z11vec_dot_matPdS_S_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mat_transposePdS_mm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vec_kernels.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
* The MIT License (MIT)
* This file is part of waifu2x-converter-cpp
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
/* -*- mode: c++ -*- */
#define UNROLL9(F) \
F(0); \
F(1); \
F(2); \
F(3); \
F(4); \
F(5); \
F(6); \
F(7); \
F(8); \
#define UNROLL8x3x3(F) \
F(0,0,0); \
F(0,0,1); \
F(0,0,2); \
F(0,1,0); \
F(0,1,1); \
F(0,1,2); \
F(0,2,0); \
F(0,2,1); \
F(0,2,2); \
\
F(1,0,0); \
F(1,0,1); \
F(1,0,2); \
F(1,1,0); \
F(1,1,1); \
F(1,1,2); \
F(1,2,0); \
F(1,2,1); \
F(1,2,2); \
\
F(2,0,0); \
F(2,0,1); \
F(2,0,2); \
F(2,1,0); \
F(2,1,1); \
F(2,1,2); \
F(2,2,0); \
F(2,2,1); \
F(2,2,2); \
\
F(3,0,0); \
F(3,0,1); \
F(3,0,2); \
F(3,1,0); \
F(3,1,1); \
F(3,1,2); \
F(3,2,0); \
F(3,2,1); \
F(3,2,2); \
\
F(4,0,0); \
F(4,0,1); \
F(4,0,2); \
F(4,1,0); \
F(4,1,1); \
F(4,1,2); \
F(4,2,0); \
F(4,2,1); \
F(4,2,2); \
\
F(5,0,0); \
F(5,0,1); \
F(5,0,2); \
F(5,1,0); \
F(5,1,1); \
F(5,1,2); \
F(5,2,0); \
F(5,2,1); \
F(5,2,2); \
\
F(6,0,0); \
F(6,0,1); \
F(6,0,2); \
F(6,1,0); \
F(6,1,1); \
F(6,1,2); \
F(6,2,0); \
F(6,2,1); \
F(6,2,2); \
\
F(7,0,0); \
F(7,0,1); \
F(7,0,2); \
F(7,1,0); \
F(7,1,1); \
F(7,1,2); \
F(7,2,0); \
F(7,2,1); \
F(7,2,2); \
#define UNROLL8(F) \
F(0); \
F(1); \
F(2); \
F(3); \
F(4); \
F(5); \
F(6); \
F(7); \
#define UNROLL8x3(F) \
F(0,0); \
F(0,1); \
F(0,2); \
F(0,3); \
F(0,4); \
F(0,5); \
F(0,6); \
F(0,7); \
\
F(1,0); \
F(1,1); \
F(1,2); \
F(1,3); \
F(1,4); \
F(1,5); \
F(1,6); \
F(1,7); \
\
F(2,0); \
F(2,1); \
F(2,2); \
F(2,3); \
F(2,4); \
F(2,5); \
F(2,6); \
F(2,7); \
#define UNROLL10x3(F) \
F(0,0); \
F(0,1); \
F(0,2); \
F(0,3); \
F(0,4); \
F(0,5); \
F(0,6); \
F(0,7); \
F(0,8); \
F(0,9); \
\
F(1,0); \
F(1,1); \
F(1,2); \
F(1,3); \
F(1,4); \
F(1,5); \
F(1,6); \
F(1,7); \
F(1,8); \
F(1,9); \
\
F(2,0); \
F(2,1); \
F(2,2); \
F(2,3); \
F(2,4); \
F(2,5); \
F(2,6); \
F(2,7); \
F(2,8); \
F(2,9); \
#define BLOCK_SIZE 8
extern __shared__ float shared_buf[];
template <int nInputPlanes>
__device__ void
filter(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
int nOutputPlanes,
const float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
const float * __restrict__ weight)
{
unsigned int yi = blockIdx.x;
size_t in_step = wsz * nInputPlanes;
const float *inp = packed_input;
inp += yi * in_step;
const float *in0p = inp - in_step;
if (yi == 0) {
in0p = inp;
}
const float *in1p = inp;
const float *in2p = inp + in_step;
if (yi == hsz-1) {
in2p = in1p;
}
const float *in01 = in0p;
const float *in11 = in1p;
const float *in21 = in2p;
float *shared_ptr = shared_buf;
float *in_block0_base = shared_ptr;
shared_ptr += nInputPlanes*(BLOCK_SIZE+2);
float *in_block1_base = shared_ptr;
shared_ptr += nInputPlanes*(BLOCK_SIZE+2);
float *in_block2_base = shared_ptr;
shared_ptr += nInputPlanes*(BLOCK_SIZE+2);
float *in_block0 = in_block0_base + nInputPlanes;
float *in_block1 = in_block1_base + nInputPlanes;
float *in_block2 = in_block2_base + nInputPlanes;
int lid = threadIdx.x;
float bv = biases[lid];
for (int xi0=0; xi0<wsz; xi0+=BLOCK_SIZE) {
/*for (unsigned int op=0; op<nOutputPlanes; op++) thread */
{
int op = lid;
int rem = wsz - xi0;
__syncthreads();
if (lid < nInputPlanes/2) {
int bi;
int lid2 = lid*2;
for (bi=0; bi<BLOCK_SIZE; bi++) {
int xi = xi0 + bi;
if (xi == wsz) {
break;
}
/* load to shared */
*(float2*)&in_block0[bi*nInputPlanes + lid2] = *(float2*)&in01[xi*nInputPlanes + lid2];
*(float2*)&in_block1[bi*nInputPlanes + lid2] = *(float2*)&in11[xi*nInputPlanes + lid2];
*(float2*)&in_block2[bi*nInputPlanes + lid2] = *(float2*)&in21[xi*nInputPlanes + lid2];
}
{
int xi = xi0 + bi;
if (xi == wsz) {
*(float2*)&in_block0[bi*(int)nInputPlanes + lid2] = *(float2*)&in01[(xi-1)*(int)nInputPlanes + lid2];
*(float2*)&in_block1[bi*(int)nInputPlanes + lid2] = *(float2*)&in11[(xi-1)*(int)nInputPlanes + lid2];
*(float2*)&in_block2[bi*(int)nInputPlanes + lid2] = *(float2*)&in21[(xi-1)*(int)nInputPlanes + lid2];
} else {
*(float2*)&in_block0[bi*(int)nInputPlanes + lid2] = *(float2*)&in01[xi*(int)nInputPlanes + lid2];
*(float2*)&in_block1[bi*(int)nInputPlanes + lid2] = *(float2*)&in11[xi*(int)nInputPlanes + lid2];
*(float2*)&in_block2[bi*(int)nInputPlanes + lid2] = *(float2*)&in21[xi*(int)nInputPlanes + lid2];
}
}
{
int xi = xi0-1;
if (xi == -1) {
*(float2*)&in_block0[-1*(int)nInputPlanes + (int)lid2] = *(float2*)&in01[lid2];
*(float2*)&in_block1[-1*(int)nInputPlanes + (int)lid2] = *(float2*)&in11[lid2];
*(float2*)&in_block2[-1*(int)nInputPlanes + (int)lid2] = *(float2*)&in21[lid2];
} else {
*(float2*)&in_block0[-1*(int)nInputPlanes + (int)lid2] = *(float2*)&in01[xi*(int)nInputPlanes + lid2];
*(float2*)&in_block1[-1*(int)nInputPlanes + (int)lid2] = *(float2*)&in11[xi*(int)nInputPlanes + lid2];
*(float2*)&in_block2[-1*(int)nInputPlanes + (int)lid2] = *(float2*)&in21[xi*(int)nInputPlanes + lid2];
}
}
}
__syncthreads();
if (rem >= BLOCK_SIZE) {
#define DECL_PTR(y,x) float *p##y##x = &in_block##y[nInputPlanes * (x-1)];
UNROLL10x3(DECL_PTR);
float sum0 = 0;
float sum1 = 0;
float sum2 = 0;
float sum3 = 0;
float sum4 = 0;
float sum5 = 0;
float sum6 = 0;
float sum7 = 0;
{
const float *w0 = weight + lid;
for (int ip = 0; ip < nInputPlanes; ip++) {
#define LOAD_INPUT2(y,x) float2 i##y##x##_2 = *(float2*)&p##y##x[ip];
UNROLL10x3(LOAD_INPUT2);
#define LOAD_COEF(X) float w_##X = w[X * 128];
#define CALC(IDX,Y,I0,I1,I2,I3,I4,I5,I6,I7) \
sum0 += w_##IDX * i##Y##I0; \
sum1 += w_##IDX * i##Y##I1; \
sum2 += w_##IDX * i##Y##I2; \
sum3 += w_##IDX * i##Y##I3; \
sum4 += w_##IDX * i##Y##I4; \
sum5 += w_##IDX * i##Y##I5; \
sum6 += w_##IDX * i##Y##I6; \
sum7 += w_##IDX * i##Y##I7;
{
#define LOAD_INPUT1X(Y,X) float i##Y##X = i##Y##X##_2.x;
UNROLL10x3(LOAD_INPUT1X);
const float *w = (w0 + (ip * 128) * 9);
UNROLL9(LOAD_COEF);
{
CALC(0,0,0,1,2,3,4,5,6,7);
CALC(1,0,1,2,3,4,5,6,7,8);
CALC(2,0,2,3,4,5,6,7,8,9);
CALC(3,1,0,1,2,3,4,5,6,7);
CALC(4,1,1,2,3,4,5,6,7,8);
CALC(5,1,2,3,4,5,6,7,8,9);
CALC(6,2,0,1,2,3,4,5,6,7);
CALC(7,2,1,2,3,4,5,6,7,8);
CALC(8,2,2,3,4,5,6,7,8,9);
}
}
ip++;
{
#define LOAD_INPUT1Y(Y,X) float i##Y##X = i##Y##X##_2.y;
UNROLL10x3(LOAD_INPUT1Y);
const float *w = (w0 + (ip * 128) * 9);
UNROLL9(LOAD_COEF);
{
CALC(0,0,0,1,2,3,4,5,6,7);
CALC(1,0,1,2,3,4,5,6,7,8);
CALC(2,0,2,3,4,5,6,7,8,9);
CALC(3,1,0,1,2,3,4,5,6,7);
CALC(4,1,1,2,3,4,5,6,7,8);
CALC(5,1,2,3,4,5,6,7,8,9);
CALC(6,2,0,1,2,3,4,5,6,7);
CALC(7,2,1,2,3,4,5,6,7,8);
CALC(8,2,2,3,4,5,6,7,8,9);
}
}
}
#define RELU(BI) \
{ \
float *out = packed_output + (yi*wsz + (xi0+BI))*nOutputPlanes; \
\
{ \
int opIndex = lid; \
float v = sum##BI; \
v += bv; \
\
float mtz = max(v, 0.0f); \
float ltz = min(v, 0.0f); \
\
v = ltz * 0.1f + mtz; \
\
out[opIndex] = v; \
} \
}
UNROLL8(RELU);
#undef DECL_PTR
#undef LOAD_COEF
#undef CALC
#undef LOAD_INPUT2
#undef LOAD_INPUT1X
#undef LOAD_INPUT1Y
#undef RELU
}
} else {
for (int bi=0; bi<BLOCK_SIZE; bi++) {
int xi = xi0+bi;
if (xi == wsz) {
break;
}
const float *w0 = weight + lid;
float sum = 0;
for (int ip=0; ip<nInputPlanes; ip++) {
float i00, i01, i02;
float i10, i11, i12;
float i20, i21, i22;
i00 = in_block0[(bi-1)*nInputPlanes+ip];
i10 = in_block1[(bi-1)*nInputPlanes+ip];
i20 = in_block2[(bi-1)*nInputPlanes+ip];
i01 = in_block0[bi*nInputPlanes+ip];
i11 = in_block1[bi*nInputPlanes+ip];
i21 = in_block2[bi*nInputPlanes+ip];
i02 = in_block0[(bi+1)*nInputPlanes+ip];
i12 = in_block1[(bi+1)*nInputPlanes+ip];
i22 = in_block2[(bi+1)*nInputPlanes+ip];
const float *w = w0;
sum += w[(9*ip+0) * 128]*i00;
sum += w[(9*ip+1) * 128]*i01;
sum += w[(9*ip+2) * 128]*i02;
sum += w[(9*ip+3) * 128]*i10;
sum += w[(9*ip+4) * 128]*i11;
sum += w[(9*ip+5) * 128]*i12;
sum += w[(9*ip+6) * 128]*i20;
sum += w[(9*ip+7) * 128]*i21;
sum += w[(9*ip+8) * 128]*i22;
}
float *out = packed_output + (yi*wsz + xi)*nOutputPlanes;
{
float v = sum;
v += bv;
float mtz = max(v, 0.0f);
float ltz = min(v, 0.0f);
v = ltz * 0.1f + mtz;
out[op] = v;
}
}
}
}
}
}
extern "C" __global__ void
filter_i32(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
int nOutputPlanes,
const float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
const float * __restrict__ weight)
{
filter<32>(packed_input, packed_output, nOutputPlanes, biases, hsz, wsz, weight);
}
extern "C" __global__ void
filter_i64(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
int nOutputPlanes,
const float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
const float * __restrict__ weight)
{
filter<64>(packed_input, packed_output, nOutputPlanes, biases, hsz, wsz, weight);
}
extern "C" __global__ void
filter_i128(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
int nOutputPlanes,
const float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
const float * __restrict__ weight)
{
filter<128>(packed_input, packed_output, nOutputPlanes, biases, hsz, wsz, weight);
}
#if __CUDA_ARCH__ >= 300
static inline __device__ float
warp_sum(float v) {
v += __shfl_down_sync(0xFFFFFFFF, v, 1);
v += __shfl_down_sync(0xFFFFFFFF, v, 2);
v += __shfl_down_sync(0xFFFFFFFF, v, 4);
v += __shfl_down_sync(0xFFFFFFFF, v, 8);
v += __shfl_down_sync(0xFFFFFFFF, v, 16);
return v;
}
#endif
template <int nInputPlanes,
int nOutputPlanes>
void __device__
filter_weight_blocking(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
const float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
const float * __restrict__ weight,
int ib0,
int ob0)
{
#define INPUT_BLOCK_SIZE 32
#define OUTPUT_BLOCK_SIZE 64 // == blockDim.x
#define X_BLOCK_SIZE 8
unsigned int yi = blockIdx.x;
size_t in_step = wsz * nInputPlanes;
const float *inp = packed_input;
inp += yi * in_step;
const float *in0p = inp - in_step;
if (yi == 0) {
in0p = inp;
}
const float *in1p = inp;
const float *in2p = inp + in_step;
if (yi == hsz-1) {
in2p = in1p;
}
const float *in01 = in0p;
const float *in11 = in1p;
const float *in21 = in2p;
__shared__ float shared_buf_base[INPUT_BLOCK_SIZE * (X_BLOCK_SIZE+2) * 3];
float *in_block0_base = shared_buf_base + INPUT_BLOCK_SIZE * (BLOCK_SIZE+2) * 0;
float *in_block1_base = shared_buf_base + INPUT_BLOCK_SIZE * (BLOCK_SIZE+2) * 1;
float *in_block2_base = shared_buf_base + INPUT_BLOCK_SIZE * (BLOCK_SIZE+2) * 2;
float *in_block0 = in_block0_base + INPUT_BLOCK_SIZE;
float *in_block1 = in_block1_base + INPUT_BLOCK_SIZE;
float *in_block2 = in_block2_base + INPUT_BLOCK_SIZE;
int lid = threadIdx.x;
{ // ib0
{ // ob0
int op = lid + ob0;
float bv = biases[op];
for (int xi0=0; xi0<wsz; xi0+=BLOCK_SIZE) {
float *out_base = packed_output + (yi*wsz + xi0)*nOutputPlanes + op;
float *linp0 = in_block0 + lid;
float *linp1 = in_block1 + lid;
float *linp2 = in_block2 + lid;
__syncthreads();
int rem = wsz - xi0;
const float *inb0 = in01 + ib0+lid;
const float *inb1 = in11 + ib0+lid;
const float *inb2 = in21 + ib0+lid;
if (rem > 8 && xi0 != 0) {
if (lid < INPUT_BLOCK_SIZE) {
linp0[-1*INPUT_BLOCK_SIZE] = linp0[7*INPUT_BLOCK_SIZE];
linp1[-1*INPUT_BLOCK_SIZE] = linp1[7*INPUT_BLOCK_SIZE];
linp2[-1*INPUT_BLOCK_SIZE] = linp2[7*INPUT_BLOCK_SIZE];
linp0[0*INPUT_BLOCK_SIZE] = linp0[8*INPUT_BLOCK_SIZE];
linp1[0*INPUT_BLOCK_SIZE] = linp1[8*INPUT_BLOCK_SIZE];
linp2[0*INPUT_BLOCK_SIZE] = linp2[8*INPUT_BLOCK_SIZE];
}
__syncthreads();
if (lid < INPUT_BLOCK_SIZE) {
int bi;
#pragma unroll
for (bi=1; bi<X_BLOCK_SIZE+1; bi++) {
int xi = xi0 + bi;
/* load to shared */
linp0[bi*INPUT_BLOCK_SIZE] = inb0[xi*nInputPlanes];
linp1[bi*INPUT_BLOCK_SIZE] = inb1[xi*nInputPlanes];
linp2[bi*INPUT_BLOCK_SIZE] = inb2[xi*nInputPlanes];
}
}
} else {
if (lid < INPUT_BLOCK_SIZE) {
int bi;
for (bi=0; bi<X_BLOCK_SIZE; bi++) {
int xi = xi0 + bi;
if (xi == wsz) {
break;
}
/* load to shared */
linp0[bi*INPUT_BLOCK_SIZE] = inb0[xi*nInputPlanes];
linp1[bi*INPUT_BLOCK_SIZE] = inb1[xi*nInputPlanes];
linp2[bi*INPUT_BLOCK_SIZE] = inb2[xi*nInputPlanes];
}
{
int xi = xi0 + bi;
if (xi == wsz) {
linp0[bi*(int)INPUT_BLOCK_SIZE] = inb0[(xi-1)*(int)nInputPlanes];
linp1[bi*(int)INPUT_BLOCK_SIZE] = inb1[(xi-1)*(int)nInputPlanes];
linp2[bi*(int)INPUT_BLOCK_SIZE] = inb2[(xi-1)*(int)nInputPlanes];
} else {
linp0[bi*(int)INPUT_BLOCK_SIZE] = inb0[xi*(int)nInputPlanes];
linp1[bi*(int)INPUT_BLOCK_SIZE] = inb1[xi*(int)nInputPlanes];
linp2[bi*(int)INPUT_BLOCK_SIZE] = inb2[xi*(int)nInputPlanes];
}
}
{
int xi = xi0-1;
if (xi == -1) {
linp0[-1*(int)INPUT_BLOCK_SIZE] = inb0[0];
linp1[-1*(int)INPUT_BLOCK_SIZE] = inb1[0];
linp2[-1*(int)INPUT_BLOCK_SIZE] = inb2[0];
} else {
linp0[-1*(int)INPUT_BLOCK_SIZE] = inb0[xi*(int)nInputPlanes];
linp1[-1*(int)INPUT_BLOCK_SIZE] = inb1[xi*(int)nInputPlanes];
linp2[-1*(int)INPUT_BLOCK_SIZE] = inb2[xi*(int)nInputPlanes];
}
}
}
}
__syncthreads();
const float *w0 = weight + op;
if (rem >= BLOCK_SIZE) {
#define DECL_PTR(y,x) float *p##y##x = &in_block##y[INPUT_BLOCK_SIZE * (x-1)];
UNROLL10x3(DECL_PTR);
float sum0 = 0;
float sum1 = 0;
float sum2 = 0;
float sum3 = 0;
float sum4 = 0;
float sum5 = 0;
float sum6 = 0;
float sum7 = 0;
for (int ip1 = 0; ip1 < INPUT_BLOCK_SIZE; ip1+=2) {
int ip = ip1 + ib0;
#define LOAD_INPUT2(y,x) float2 i##y##x##_2 = *(float2*)&p##y##x[ip1];
UNROLL10x3(LOAD_INPUT2);
#define LOAD_COEF(X) float w_##X = w[X * 128];
#define CALC(SYM,IDX,Y,I0,I1,I2,I3,I4,I5,I6,I7) \
sum0 += w_##IDX * i##Y##I0##_2.SYM; \
sum1 += w_##IDX * i##Y##I1##_2.SYM; \
sum2 += w_##IDX * i##Y##I2##_2.SYM; \
sum3 += w_##IDX * i##Y##I3##_2.SYM; \
sum4 += w_##IDX * i##Y##I4##_2.SYM; \
sum5 += w_##IDX * i##Y##I5##_2.SYM; \
sum6 += w_##IDX * i##Y##I6##_2.SYM; \
sum7 += w_##IDX * i##Y##I7##_2.SYM;
{
const float *w = (w0 + (ip * 128) * 9);
UNROLL9(LOAD_COEF);
{
CALC(x, 0,0,0,1,2,3,4,5,6,7);
CALC(x, 1,0,1,2,3,4,5,6,7,8);
CALC(x, 2,0,2,3,4,5,6,7,8,9);
CALC(x, 3,1,0,1,2,3,4,5,6,7);
CALC(x, 4,1,1,2,3,4,5,6,7,8);
CALC(x, 5,1,2,3,4,5,6,7,8,9);
CALC(x, 6,2,0,1,2,3,4,5,6,7);
CALC(x, 7,2,1,2,3,4,5,6,7,8);
CALC(x, 8,2,2,3,4,5,6,7,8,9);
}
}
ip++;
{
const float *w = (w0 + (ip * 128) * 9);
UNROLL9(LOAD_COEF);
{
CALC(y, 0,0,0,1,2,3,4,5,6,7);
CALC(y, 1,0,1,2,3,4,5,6,7,8);
CALC(y, 2,0,2,3,4,5,6,7,8,9);
CALC(y, 3,1,0,1,2,3,4,5,6,7);
CALC(y, 4,1,1,2,3,4,5,6,7,8);
CALC(y, 5,1,2,3,4,5,6,7,8,9);
CALC(y, 6,2,0,1,2,3,4,5,6,7);
CALC(y, 7,2,1,2,3,4,5,6,7,8);
CALC(y, 8,2,2,3,4,5,6,7,8,9);
}
}
}
#define RELU(BI) \
{ \
\
{ \
float v = sum##BI + out_base[BI*nOutputPlanes]; \
v += bv; \
\
float mtz = max(v, 0.0f); \
float ltz = min(v, 0.0f); \
\
v = ltz * 0.1f + mtz; \
\
out_base[BI*nOutputPlanes] = v; \
} \
}
if ((ib0+INPUT_BLOCK_SIZE) == nInputPlanes) {
UNROLL8(RELU);
} else if (ib0 == 0) {
out_base[nOutputPlanes*0] = sum0;
out_base[nOutputPlanes*1] = sum1;
out_base[nOutputPlanes*2] = sum2;
out_base[nOutputPlanes*3] = sum3;
out_base[nOutputPlanes*4] = sum4;
out_base[nOutputPlanes*5] = sum5;
out_base[nOutputPlanes*6] = sum6;
out_base[nOutputPlanes*7] = sum7;
} else {
out_base[nOutputPlanes*0] += sum0;
out_base[nOutputPlanes*1] += sum1;
out_base[nOutputPlanes*2] += sum2;
out_base[nOutputPlanes*3] += sum3;
out_base[nOutputPlanes*4] += sum4;
out_base[nOutputPlanes*5] += sum5;
out_base[nOutputPlanes*6] += sum6;
out_base[nOutputPlanes*7] += sum7;
}
} else {
for (int bi=0; bi<X_BLOCK_SIZE; bi++) {
int xi = xi0+bi;
if (xi == wsz) {
break;
}
float sum = 0;
for (int ip1=0; ip1<INPUT_BLOCK_SIZE; ip1++) {
int ip = ib0 + ip1;
float i00, i01, i02;
float i10, i11, i12;
float i20, i21, i22;
i00 = in_block0[(bi-1)*INPUT_BLOCK_SIZE+ip1];
i10 = in_block1[(bi-1)*INPUT_BLOCK_SIZE+ip1];
i20 = in_block2[(bi-1)*INPUT_BLOCK_SIZE+ip1];
i01 = in_block0[bi*INPUT_BLOCK_SIZE+ip1];
i11 = in_block1[bi*INPUT_BLOCK_SIZE+ip1];
i21 = in_block2[bi*INPUT_BLOCK_SIZE+ip1];
i02 = in_block0[(bi+1)*INPUT_BLOCK_SIZE+ip1];
i12 = in_block1[(bi+1)*INPUT_BLOCK_SIZE+ip1];
i22 = in_block2[(bi+1)*INPUT_BLOCK_SIZE+ip1];
sum += w0[(9*ip+0) * 128]*i00;
sum += w0[(9*ip+1) * 128]*i01;
sum += w0[(9*ip+2) * 128]*i02;
sum += w0[(9*ip+3) * 128]*i10;
sum += w0[(9*ip+4) * 128]*i11;
sum += w0[(9*ip+5) * 128]*i12;
sum += w0[(9*ip+6) * 128]*i20;
sum += w0[(9*ip+7) * 128]*i21;
sum += w0[(9*ip+8) * 128]*i22;
}
float *out = packed_output + (yi*wsz + xi)*nOutputPlanes;
if ((ib0+INPUT_BLOCK_SIZE) == nInputPlanes) {
/* last */
float v = sum + out[op];
v += bv;
float mtz = max(v, 0.0f);
float ltz = min(v, 0.0f);
v = ltz * 0.1f + mtz;
out[op] = v;
} else if (ib0 == 0) {
out[op] = sum;
} else {
out[op] += sum;
}
}
}
}
}
}
}
extern "C" __global__
void
filter_i128_o128(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
const float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
const float * __restrict__ weight,
int ib0,
int ob0)
{
filter_weight_blocking<128,128>(packed_input,
packed_output,
biases,
hsz,
wsz,
weight,
ib0,
ob0);
}
extern "C" __global__
void
filter_i64_o128(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
const float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
const float * __restrict__ weight,
int ib0,
int ob0)
{
filter_weight_blocking<64,128>(packed_input,
packed_output,
biases,
hsz,
wsz,
weight,
ib0,
ob0);
}
extern "C" __global__
void
filter_i64_o64(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
const float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
const float * __restrict__ weight,
int ib0,
int ob0)
{
filter_weight_blocking<64,64>(packed_input,
packed_output,
biases,
hsz,
wsz,
weight,
ib0,
ob0);
}
extern "C" __global__ void
filter_i128_o1(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
float * __restrict__ weight)
{
int nInputPlanes = 128;
int nOutputPlanes = 1;
{
unsigned int yi = blockIdx.x;
size_t in_step = wsz * nInputPlanes;
const float *inp = packed_input;
inp += yi * in_step;
const float *in0p = inp - in_step;
if (yi == 0) {
in0p = inp;
}
const float *in1p = inp;
const float *in2p = inp + in_step;
if (yi == hsz-1) {
in2p = in1p;
}
const float *in01 = in0p;
const float *in11 = in1p;
const float *in21 = in2p;
unsigned int lid = threadIdx.x;
float bv0 = biases[0];
/* 128 item */
/* x : (1width/group) */
/* y : (2height/group) */
/* iplane : 1plane / 1item * 128plane */
__shared__ float shared_buf[128 * 10];
float lin00;
float lin01;
float lin02;
float lin10;
float lin11;
float lin12;
float lin20;
float lin21;
float lin22;
float *sum_buffer = shared_buf + 128*9;
#define OUT1_LOAD_WEIGHT(I,Y,X) float w##I##Y##X = weight[(I*16 + lid)*9 + Y*3 + X];
float w00 = weight[lid*9 + 0];
float w01 = weight[lid*9 + 1];
float w02 = weight[lid*9 + 2];
float w10 = weight[lid*9 + 3];
float w11 = weight[lid*9 + 4];
float w12 = weight[lid*9 + 5];
float w20 = weight[lid*9 + 6];
float w21 = weight[lid*9 + 7];
float w22 = weight[lid*9 + 8];
const float *pin01 = in01 + lid;
const float *pin02 = in01 + nInputPlanes + lid;
const float *pin11 = in11 + lid;
const float *pin12 = in11 + nInputPlanes + lid;
const float *pin21 = in21 + lid;
const float *pin22 = in21 + nInputPlanes + lid;
lin01 = pin01[0];
lin02 = pin01[0];
lin11 = pin11[0];
lin12 = pin11[0];
lin21 = pin21[0];
lin22 = pin21[0];
#define OUT1_BODY(LEDGE,REDGE,SUM_RELU) \
{ \
float sum = 0; \
{ \
lin00 = lin01; \
lin01 = lin02; \
\
lin10 = lin11; \
lin11 = lin12; \
\
lin20 = lin21; \
lin21 = lin22; \
\
if (REDGE) { \
lin02 = lin01; \
lin12 = lin11; \
lin22 = lin21; \
} else { \
lin02 = pin02[xi*128]; \
lin12 = pin12[xi*128]; \
lin22 = pin22[xi*128]; \
} \
\
sum += w00 * lin00; \
sum += w10 * lin10; \
sum += w20 * lin20; \
\
sum += w01 * lin01; \
sum += w11 * lin11; \
sum += w21 * lin21; \
\
sum += w02 * lin02; \
sum += w12 * lin12; \
sum += w22 * lin22; \
\
} \
__syncthreads(); \
sum_buffer[lid] = sum; \
__syncthreads(); \
if (lid < 64) { \
float v2 = sum_buffer[lid+64]; \
sum_buffer[lid] += v2; \
} \
__syncthreads(); \
SUM_RELU(0); \
}
#if __CUDA_ARCH__ >= 300
#define SUM_RELU(OI) \
if (lid < 32) { \
float v0 = sum_buffer[lid] + sum_buffer[lid+32]; \
float sum = warp_sum(v0); \
\
if (lid == 0) { \
float v = sum; \
float *out = packed_output + (yi*wsz + xi)*nOutputPlanes; \
v += bv##OI; \
float mtz = max(v, 0.0f); \
float ltz = min(v, 0.0f); \
v = ltz * 0.1f + mtz; \
out[OI] = v; \
} \
} \
#else
#define SUM_RELU(OI) \
if (lid < 32) { \
sum_buffer[lid] += sum_buffer[lid+32]; \
} \
__syncthreads(); \
if (lid < 16) { \
sum_buffer[lid] += sum_buffer[lid+16]; \
} \
__syncthreads(); \
if (lid < 8) { \
sum_buffer[lid] += sum_buffer[lid+8]; \
} \
__syncthreads(); \
if (lid < 4) { \
sum_buffer[lid] += sum_buffer[lid+4]; \
} \
__syncthreads(); \
if (lid < 2) { \
sum_buffer[lid] += sum_buffer[lid+2]; \
} \
__syncthreads(); \
if (lid == 0) { \
float sum = sum_buffer[0] + sum_buffer[1]; \
float v = sum; \
float *out = packed_output + (yi*wsz + xi)*nOutputPlanes; \
v += bv##OI; \
float mtz = max(v, 0.0f); \
float ltz = min(v, 0.0f); \
v = ltz * 0.1f + mtz; \
out[OI] = v; \
}
#endif
for (int xi=0; xi<wsz-1; xi++) {
OUT1_BODY(0,0,SUM_RELU);
}
{
int xi = wsz-1;
OUT1_BODY(0,1,SUM_RELU);
}
}
}
extern "C" __global__ void
filter_i1_o32(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
float * __restrict__ weight)
{
//int nInputPlanes = 1;
int nOutputPlanes = 32;
unsigned int yi = blockIdx.x;
unsigned int lid = threadIdx.x;
size_t in_step = wsz;
const float *inp = packed_input;
inp += in_step * yi;
const float *in0p = inp - in_step;
if (yi == 0) {
in0p = inp;
}
const float *in1p = inp;
const float *in2p = inp + in_step;
if (yi == hsz-1) {
in2p = in1p;
}
const float *in01 = in0p;
const float *in11 = in1p;
const float *in21 = in2p;
__shared__ float in_block0_base[256+2];
__shared__ float in_block1_base[256+2];
__shared__ float in_block2_base[256+2];
float *in_block0 = in_block0_base + 1;
float *in_block1 = in_block1_base + 1;
float *in_block2 = in_block2_base + 1;
/* 256 item / group */
/* x : (64width/group) */
/* 32 oplane : (8weight/item * 4item)*/
unsigned int xoff = lid / 4U;
unsigned int ooff = (lid % 4U) * 8;
#define IN1_LOAD_COEF(O,Y,X) \
float w##O##Y##X = weight[9 * (O + ooff) + (Y*3) + X];
UNROLL8x3x3(IN1_LOAD_COEF);
for (int xi0=0; xi0<wsz; xi0+=256) {
/* load */
__syncthreads();
{
int xi = xi0 + lid;
if (xi < wsz) {
in_block0[lid] = in01[xi0 + lid];
in_block1[lid] = in11[xi0 + lid];
in_block2[lid] = in21[xi0 + lid];
}
if (lid == 0) {
if (xi == 0) {
in_block0[-1] = in01[0];
in_block1[-1] = in11[0];
in_block2[-1] = in21[0];
} else {
in_block0[-1] = in01[xi-1];
in_block1[-1] = in11[xi-1];
in_block2[-1] = in21[xi-1];
}
}
if (xi == wsz-1) {
in_block0[lid+1] = in01[xi];
in_block1[lid+1] = in11[xi];
in_block2[lid+1] = in21[xi];
}
if ((lid == 255) && (xi < wsz-1)) {
in_block0[256] = in01[xi+1];
in_block1[256] = in11[xi+1];
in_block2[256] = in21[xi+1];
}
}
__syncthreads();
for (int xi1_base=0; xi1_base<4; xi1_base++) {
{
int xi1 = xi1_base*64 + xoff;
int xi = xi0 + xi1;
if (xi < wsz) {
#define IN1_DECLSUM(O) float sum##O = 0;
#define IN1_CALC(O,Y,X) sum##O += in_block##Y[xi1+X-1] * w##O##Y##X;
#define IN1_RELU(O) { \
float v = sum##O; \
int opIndex = ooff + O; \
float bv = biases[opIndex]; \
v += bv; \
float mtz = max(v, 0.0f); \
float ltz = min(v, 0.0f); \
v = ltz * 0.1f + mtz; \
out[opIndex] = v; \
}
UNROLL8(IN1_DECLSUM);
UNROLL8x3x3(IN1_CALC);
float *out = packed_output + (yi*wsz + xi) * nOutputPlanes;
UNROLL8(IN1_RELU);
}
}
}
}
}
/* blockDim.x == 192 */
extern "C" __global__ void
filter_i3_o32(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
float * __restrict__ weight)
{
int nInputPlanes = 3;
int nOutputPlanes = 32;
unsigned int yi = blockIdx.x;
unsigned int lid = threadIdx.x;
size_t in_step = wsz * nInputPlanes;
const float *inp = packed_input;
inp += in_step * yi;
const float *in0p = inp - in_step;
if (yi == 0) {
in0p = inp;
}
const float *in1p = inp;
const float *in2p = inp + in_step;
if (yi == hsz-1) {
in2p = in1p;
}
const float *in01 = in0p;
const float *in11 = in1p;
const float *in21 = in2p;
__shared__ float in_block0_base[(64+2)*3];
__shared__ float in_block1_base[(64+2)*3];
__shared__ float in_block2_base[(64+2)*3];
__shared__ float sum_buffer[192];
float *in_block0 = in_block0_base + 3;
float *in_block1 = in_block1_base + 3;
float *in_block2 = in_block2_base + 3;
/* 192 item / group */
/* load 192 item */
/* 3 iplane : */
/* x : (64width/group) */
/* 32 oplane : (8weight/item * 4item)*/
unsigned int ioff = lid / 32U;
unsigned int ooff = lid % 32U;
#define I3_O32_LOAD_COEF(I) \
float w##I = weight[9*nOutputPlanes*ioff+ooff+I*nOutputPlanes];
UNROLL9(I3_O32_LOAD_COEF);
for (int xi0=0; xi0<wsz; xi0+=64) {
/* load */
int nelem = min(wsz - xi0, 64);
int nload = nelem * 3;
if (lid < nload) {
int xi = xi0*3 + lid;
in_block0[lid] = in01[xi];
in_block1[lid] = in11[xi];
in_block2[lid] = in21[xi];
if (lid < 3) {
if (xi <= 2) {
/* left edge */
in_block0[-3+(int)lid] = in01[lid];
in_block1[-3+(int)lid] = in11[lid];
in_block2[-3+(int)lid] = in21[lid];
} else {
/* 0, 1, 2 */
in_block0[-3+(int)lid] = in01[-3+(int)xi];
in_block1[-3+(int)lid] = in11[-3+(int)xi];
in_block2[-3+(int)lid] = in21[-3+(int)xi];
}
}
if (xi >= wsz*3-3) {
/* right edge */
in_block0[lid+3] = in01[xi];
in_block1[lid+3] = in11[xi];
in_block2[lid+3] = in21[xi];
} else if (lid >= 189) {
/* 189, 190, 191 */
in_block0[lid+3] = in01[xi+3];
in_block1[lid+3] = in11[xi+3];
in_block2[lid+3] = in21[xi+3];
}
}
__syncthreads();
for (int xi1=0; xi1<nelem; xi1++) {
int xi = xi0 + xi1;
if (lid < 96) { // 3input x 32output
float sum = 0;
sum += w0 * in_block0[(xi1 - 1)*3+(int)ioff];
sum += w1 * in_block0[(xi1 )*3+(int)ioff];
sum += w2 * in_block0[(xi1 + 1)*3+(int)ioff];
sum += w3 * in_block1[(xi1 - 1)*3+(int)ioff];
sum += w4 * in_block1[(xi1 )*3+(int)ioff];
sum += w5 * in_block1[(xi1 + 1)*3+(int)ioff];
sum += w6 * in_block2[(xi1 - 1)*3+(int)ioff];
sum += w7 * in_block2[(xi1 )*3+(int)ioff];
sum += w8 * in_block2[(xi1 + 1)*3+(int)ioff];
sum_buffer[lid] = sum;
}
__syncthreads();
if (lid < 32) {
int oi = lid;
float v = 0;
float *out = packed_output + (yi*wsz + xi) * nOutputPlanes;
/* 96 to 32 reduction */
v += sum_buffer[32 * 0 + lid];
v += sum_buffer[32 * 1 + lid];
v += sum_buffer[32 * 2 + lid];
float bv = biases[oi];
v += bv;
float mtz = max(v, 0.0f);
float ltz = min(v, 0.0f);
v = ltz * 0.1f + mtz;
out[oi] = v;
}
__syncthreads();
}
}
}
/* blockDim.x == 128 */
extern "C" __global__ void
filter_i128_o3(const float * __restrict__ packed_input,
float * __restrict__ packed_output,
float * __restrict__ biases,
unsigned int hsz,
unsigned int wsz,
float * __restrict__ weight)
{
int nInputPlanes = 128;
int nOutputPlanes = 3;
unsigned int yi = blockIdx.x;
unsigned int lid = threadIdx.x;
size_t in_step = wsz * nInputPlanes;
const float *inp = packed_input;
inp += in_step * yi;
const float *in0p = inp - in_step;
if (yi == 0) {
in0p = inp;
}
const float *in1p = inp;
const float *in2p = inp + in_step;
if (yi == hsz-1) {
in2p = in1p;
}
const float *in01 = in0p;
const float *in11 = in1p;
const float *in21 = in2p;
float lin00, lin01, lin02;
float lin10, lin11, lin12;
float lin20, lin21, lin22;
__shared__ float sum_buffer[128];
/* 128 item / group */
/* load 128 item (load 3elem/item) */
/* 128 iplane
* 1 input
* 3 output (27coeff)
*/
int ioff = lid;
float bv0 = biases[0];
float bv1 = biases[1];
float bv2 = biases[2];
#define I128_O3_LOAD_COEF(I) \
float w0##I = weight[9*0*nInputPlanes + I*nInputPlanes + ioff]; \
float w1##I = weight[9*1*nInputPlanes + I*nInputPlanes + ioff]; \
float w2##I = weight[9*2*nInputPlanes + I*nInputPlanes + ioff];
UNROLL9(I128_O3_LOAD_COEF);
lin01 = lin02 = in01[lid];
lin11 = lin12 = in11[lid];
lin21 = lin22 = in21[lid];
int addroff = 0;
char *p0 = (char*)(in01 + lid + nInputPlanes);
char *p1 = (char*)(in11 + lid + nInputPlanes);
char *p2 = (char*)(in21 + lid + nInputPlanes);
for (int xi=0; xi<wsz; xi++) {
lin00 = lin01;
lin01 = lin02;
lin10 = lin11;
lin11 = lin12;
lin20 = lin21;
lin21 = lin22;
if (xi == wsz-1) {
/* nop */
} else {
lin02 = *(float *)(p0 + addroff);
lin12 = *(float *)(p1 + addroff);
lin22 = *(float *)(p2 + addroff);
}
addroff += nInputPlanes * sizeof(float);
#define I128_O3(OI) \
{ \
float sum = 0; \
sum += w##OI##0 * lin00; \
sum += w##OI##1 * lin01; \
sum += w##OI##2 * lin02; \
\
sum += w##OI##3 * lin10; \
sum += w##OI##4 * lin11; \
sum += w##OI##5 * lin12; \
\
sum += w##OI##6 * lin20; \
sum += w##OI##7 * lin21; \
sum += w##OI##8 * lin22; \
\
__syncthreads(); \
sum_buffer[lid] = sum; \
\
/* 128 to 1 */ \
__syncthreads(); \
if (lid < 64) { \
sum_buffer[lid] += sum_buffer[lid + 64]; \
} \
__syncthreads(); \
\
SUM_RELU(OI); \
}
I128_O3(0);
I128_O3(1);
I128_O3(2);
}
} | .text
.file "modelHandler_CUDA.hip"
.globl __device_stub__filter_i32 # -- Begin function __device_stub__filter_i32
.p2align 4, 0x90
.type __device_stub__filter_i32,@function
__device_stub__filter_i32: # @__device_stub__filter_i32
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i32, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__filter_i32, .Lfunc_end0-__device_stub__filter_i32
.cfi_endproc
# -- End function
.globl __device_stub__filter_i64 # -- Begin function __device_stub__filter_i64
.p2align 4, 0x90
.type __device_stub__filter_i64,@function
__device_stub__filter_i64: # @__device_stub__filter_i64
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i64, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size __device_stub__filter_i64, .Lfunc_end1-__device_stub__filter_i64
.cfi_endproc
# -- End function
.globl __device_stub__filter_i128 # -- Begin function __device_stub__filter_i128
.p2align 4, 0x90
.type __device_stub__filter_i128,@function
__device_stub__filter_i128: # @__device_stub__filter_i128
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 72(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i128, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size __device_stub__filter_i128, .Lfunc_end2-__device_stub__filter_i128
.cfi_endproc
# -- End function
.globl __device_stub__filter_i128_o128 # -- Begin function __device_stub__filter_i128_o128
.p2align 4, 0x90
.type __device_stub__filter_i128_o128,@function
__device_stub__filter_i128_o128: # @__device_stub__filter_i128_o128
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i128_o128, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end3:
.size __device_stub__filter_i128_o128, .Lfunc_end3-__device_stub__filter_i128_o128
.cfi_endproc
# -- End function
.globl __device_stub__filter_i64_o128 # -- Begin function __device_stub__filter_i64_o128
.p2align 4, 0x90
.type __device_stub__filter_i64_o128,@function
__device_stub__filter_i64_o128: # @__device_stub__filter_i64_o128
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i64_o128, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end4:
.size __device_stub__filter_i64_o128, .Lfunc_end4-__device_stub__filter_i64_o128
.cfi_endproc
# -- End function
.globl __device_stub__filter_i64_o64 # -- Begin function __device_stub__filter_i64_o64
.p2align 4, 0x90
.type __device_stub__filter_i64_o64,@function
__device_stub__filter_i64_o64: # @__device_stub__filter_i64_o64
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i64_o64, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end5:
.size __device_stub__filter_i64_o64, .Lfunc_end5-__device_stub__filter_i64_o64
.cfi_endproc
# -- End function
.globl __device_stub__filter_i128_o1 # -- Begin function __device_stub__filter_i128_o1
.p2align 4, 0x90
.type __device_stub__filter_i128_o1,@function
__device_stub__filter_i128_o1: # @__device_stub__filter_i128_o1
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i128_o1, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end6:
.size __device_stub__filter_i128_o1, .Lfunc_end6-__device_stub__filter_i128_o1
.cfi_endproc
# -- End function
.globl __device_stub__filter_i1_o32 # -- Begin function __device_stub__filter_i1_o32
.p2align 4, 0x90
.type __device_stub__filter_i1_o32,@function
__device_stub__filter_i1_o32: # @__device_stub__filter_i1_o32
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i1_o32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end7:
.size __device_stub__filter_i1_o32, .Lfunc_end7-__device_stub__filter_i1_o32
.cfi_endproc
# -- End function
.globl __device_stub__filter_i3_o32 # -- Begin function __device_stub__filter_i3_o32
.p2align 4, 0x90
.type __device_stub__filter_i3_o32,@function
__device_stub__filter_i3_o32: # @__device_stub__filter_i3_o32
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i3_o32, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end8:
.size __device_stub__filter_i3_o32, .Lfunc_end8-__device_stub__filter_i3_o32
.cfi_endproc
# -- End function
.globl __device_stub__filter_i128_o3 # -- Begin function __device_stub__filter_i128_o3
.p2align 4, 0x90
.type __device_stub__filter_i128_o3,@function
__device_stub__filter_i128_o3: # @__device_stub__filter_i128_o3
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $filter_i128_o3, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end9:
.size __device_stub__filter_i128_o3, .Lfunc_end9-__device_stub__filter_i128_o3
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i32, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i64, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i128, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i128_o128, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i64_o128, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i64_o64, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i128_o1, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i1_o32, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i3_o32, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $filter_i128_o3, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type filter_i32,@object # @filter_i32
.section .rodata,"a",@progbits
.globl filter_i32
.p2align 3, 0x0
filter_i32:
.quad __device_stub__filter_i32
.size filter_i32, 8
.type filter_i64,@object # @filter_i64
.globl filter_i64
.p2align 3, 0x0
filter_i64:
.quad __device_stub__filter_i64
.size filter_i64, 8
.type filter_i128,@object # @filter_i128
.globl filter_i128
.p2align 3, 0x0
filter_i128:
.quad __device_stub__filter_i128
.size filter_i128, 8
.type filter_i128_o128,@object # @filter_i128_o128
.globl filter_i128_o128
.p2align 3, 0x0
filter_i128_o128:
.quad __device_stub__filter_i128_o128
.size filter_i128_o128, 8
.type filter_i64_o128,@object # @filter_i64_o128
.globl filter_i64_o128
.p2align 3, 0x0
filter_i64_o128:
.quad __device_stub__filter_i64_o128
.size filter_i64_o128, 8
.type filter_i64_o64,@object # @filter_i64_o64
.globl filter_i64_o64
.p2align 3, 0x0
filter_i64_o64:
.quad __device_stub__filter_i64_o64
.size filter_i64_o64, 8
.type filter_i128_o1,@object # @filter_i128_o1
.globl filter_i128_o1
.p2align 3, 0x0
filter_i128_o1:
.quad __device_stub__filter_i128_o1
.size filter_i128_o1, 8
.type filter_i1_o32,@object # @filter_i1_o32
.globl filter_i1_o32
.p2align 3, 0x0
filter_i1_o32:
.quad __device_stub__filter_i1_o32
.size filter_i1_o32, 8
.type filter_i3_o32,@object # @filter_i3_o32
.globl filter_i3_o32
.p2align 3, 0x0
filter_i3_o32:
.quad __device_stub__filter_i3_o32
.size filter_i3_o32, 8
.type filter_i128_o3,@object # @filter_i128_o3
.globl filter_i128_o3
.p2align 3, 0x0
filter_i128_o3:
.quad __device_stub__filter_i128_o3
.size filter_i128_o3, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "filter_i32"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "filter_i64"
.size .L__unnamed_2, 11
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "filter_i128"
.size .L__unnamed_3, 12
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "filter_i128_o128"
.size .L__unnamed_4, 17
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "filter_i64_o128"
.size .L__unnamed_5, 16
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "filter_i64_o64"
.size .L__unnamed_6, 15
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "filter_i128_o1"
.size .L__unnamed_7, 15
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "filter_i1_o32"
.size .L__unnamed_8, 14
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "filter_i3_o32"
.size .L__unnamed_9, 14
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "filter_i128_o3"
.size .L__unnamed_10, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__filter_i32
.addrsig_sym __device_stub__filter_i64
.addrsig_sym __device_stub__filter_i128
.addrsig_sym __device_stub__filter_i128_o128
.addrsig_sym __device_stub__filter_i64_o128
.addrsig_sym __device_stub__filter_i64_o64
.addrsig_sym __device_stub__filter_i128_o1
.addrsig_sym __device_stub__filter_i1_o32
.addrsig_sym __device_stub__filter_i3_o32
.addrsig_sym __device_stub__filter_i128_o3
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym filter_i32
.addrsig_sym filter_i64
.addrsig_sym filter_i128
.addrsig_sym filter_i128_o128
.addrsig_sym filter_i64_o128
.addrsig_sym filter_i64_o64
.addrsig_sym filter_i128_o1
.addrsig_sym filter_i1_o32
.addrsig_sym filter_i3_o32
.addrsig_sym filter_i128_o3
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
for( int i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void saxpy_line6_kernel(int n, float a, float *x, float *y){
int i = blockIdx.x * blockDim.x + threadIdx.x ;
y[i] = a * x[i] + y[i];
return ;
}
void saxpy_line6_gpu(int n, float a, float *x, float *y){
//TODO kernel
dim3 bs( 4096, 1, 1 );
dim3 ts( 1024, 1, 1);
saxpy_line6_kernel <<< bs, ts >>> ( n , a , x, y) ;
cudaDeviceSynchronize();
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
cudaMallocManaged( (void**)& x, size );
cudaMallocManaged( (void**)& y, size );
a=3;
// initialize for
for( int i=0; i<N; i++){
x[i]=2;
y[i]=0;
}
printf(" data\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
saxpy_line6_gpu(N, a, x, y);
printf(" result\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
cudaFree(x);
cudaFree(y);
return 0;
} | code for sm_80
Function : _Z18saxpy_line6_kernelifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
for( int i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void saxpy_line6_kernel(int n, float a, float *x, float *y){
int i = blockIdx.x * blockDim.x + threadIdx.x ;
y[i] = a * x[i] + y[i];
return ;
}
void saxpy_line6_gpu(int n, float a, float *x, float *y){
//TODO kernel
dim3 bs( 4096, 1, 1 );
dim3 ts( 1024, 1, 1);
saxpy_line6_kernel <<< bs, ts >>> ( n , a , x, y) ;
cudaDeviceSynchronize();
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
cudaMallocManaged( (void**)& x, size );
cudaMallocManaged( (void**)& y, size );
a=3;
// initialize for
for( int i=0; i<N; i++){
x[i]=2;
y[i]=0;
}
printf(" data\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
saxpy_line6_gpu(N, a, x, y);
printf(" result\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
cudaFree(x);
cudaFree(y);
return 0;
} | .file "tmpxft_001489af_00000000-6_step6-saxpy-um.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L5:
movaps %xmm0, %xmm1
mulss (%rsi,%rax), %xmm1
addss (%rdx,%rax), %xmm1
movss %xmm1, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.globl _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_
.type _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_, @function
_Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18saxpy_line6_kernelifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_, .-_Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_
.globl _Z18saxpy_line6_kernelifPfS_
.type _Z18saxpy_line6_kernelifPfS_, @function
_Z18saxpy_line6_kernelifPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18saxpy_line6_kernelifPfS_, .-_Z18saxpy_line6_kernelifPfS_
.globl _Z15saxpy_line6_gpuifPfS_
.type _Z15saxpy_line6_gpuifPfS_, @function
_Z15saxpy_line6_gpuifPfS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movss %xmm0, 12(%rsp)
movq %rsi, %rbp
movq %rdx, %r12
movl $4096, 24(%rsp)
movl $1, 28(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movss 12(%rsp), %xmm0
movl %ebx, %edi
call _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_
jmp .L16
.cfi_endproc
.LFE2058:
.size _Z15saxpy_line6_gpuifPfS_, .-_Z15saxpy_line6_gpuifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " data\n"
.LC3:
.string "y[%d] = %f, "
.LC4:
.string "\n"
.LC6:
.string " result\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC0(%rip), %xmm0
.L20:
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq $16777216, %rax
jne .L20
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L21:
movq 16(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L21
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movss .LC5(%rip), %xmm0
movl $4194304, %edi
call _Z15saxpy_line6_gpuifPfS_
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L22:
movq 16(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L22
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z18saxpy_line6_kernelifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z18saxpy_line6_kernelifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.align 4
.LC5:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
for( int i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void saxpy_line6_kernel(int n, float a, float *x, float *y){
int i = blockIdx.x * blockDim.x + threadIdx.x ;
y[i] = a * x[i] + y[i];
return ;
}
void saxpy_line6_gpu(int n, float a, float *x, float *y){
//TODO kernel
dim3 bs( 4096, 1, 1 );
dim3 ts( 1024, 1, 1);
saxpy_line6_kernel <<< bs, ts >>> ( n , a , x, y) ;
cudaDeviceSynchronize();
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
cudaMallocManaged( (void**)& x, size );
cudaMallocManaged( (void**)& y, size );
a=3;
// initialize for
for( int i=0; i<N; i++){
x[i]=2;
y[i]=0;
}
printf(" data\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
saxpy_line6_gpu(N, a, x, y);
printf(" result\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
cudaFree(x);
cudaFree(y);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
for( int i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void saxpy_line6_kernel(int n, float a, float *x, float *y){
int i = blockIdx.x * blockDim.x + threadIdx.x ;
y[i] = a * x[i] + y[i];
return ;
}
void saxpy_line6_gpu(int n, float a, float *x, float *y){
//TODO kernel
dim3 bs( 4096, 1, 1 );
dim3 ts( 1024, 1, 1);
saxpy_line6_kernel <<< bs, ts >>> ( n , a , x, y) ;
hipDeviceSynchronize();
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
hipMallocManaged( (void**)& x, size );
hipMallocManaged( (void**)& y, size );
a=3;
// initialize for
for( int i=0; i<N; i++){
x[i]=2;
y[i]=0;
}
printf(" data\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
saxpy_line6_gpu(N, a, x, y);
printf(" result\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
hipFree(x);
hipFree(y);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
for( int i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void saxpy_line6_kernel(int n, float a, float *x, float *y){
int i = blockIdx.x * blockDim.x + threadIdx.x ;
y[i] = a * x[i] + y[i];
return ;
}
void saxpy_line6_gpu(int n, float a, float *x, float *y){
//TODO kernel
dim3 bs( 4096, 1, 1 );
dim3 ts( 1024, 1, 1);
saxpy_line6_kernel <<< bs, ts >>> ( n , a , x, y) ;
hipDeviceSynchronize();
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
hipMallocManaged( (void**)& x, size );
hipMallocManaged( (void**)& y, size );
a=3;
// initialize for
for( int i=0; i<N; i++){
x[i]=2;
y[i]=0;
}
printf(" data\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
saxpy_line6_gpu(N, a, x, y);
printf(" result\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
hipFree(x);
hipFree(y);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18saxpy_line6_kernelifPfS_
.globl _Z18saxpy_line6_kernelifPfS_
.p2align 8
.type _Z18saxpy_line6_kernelifPfS_,@function
_Z18saxpy_line6_kernelifPfS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18saxpy_line6_kernelifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18saxpy_line6_kernelifPfS_, .Lfunc_end0-_Z18saxpy_line6_kernelifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18saxpy_line6_kernelifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18saxpy_line6_kernelifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define N 4096 * 1024
void saxpy(int n, float a, float *x, float *y){
for( int i=0; i<n; i++)
{
y[i] = a * x[i] + y[i];
}
return ;
}
__global__ void saxpy_line6_kernel(int n, float a, float *x, float *y){
int i = blockIdx.x * blockDim.x + threadIdx.x ;
y[i] = a * x[i] + y[i];
return ;
}
void saxpy_line6_gpu(int n, float a, float *x, float *y){
//TODO kernel
dim3 bs( 4096, 1, 1 );
dim3 ts( 1024, 1, 1);
saxpy_line6_kernel <<< bs, ts >>> ( n , a , x, y) ;
hipDeviceSynchronize();
return ;
}
int main(){
float *x, *y;
float a;
int size = N * sizeof( float);
hipMallocManaged( (void**)& x, size );
hipMallocManaged( (void**)& y, size );
a=3;
// initialize for
for( int i=0; i<N; i++){
x[i]=2;
y[i]=0;
}
printf(" data\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
saxpy_line6_gpu(N, a, x, y);
printf(" result\n");
for( int i = 0; i < 5; ++i ) printf("y[%d] = %f, ", i, y[i]);
printf ("\n");
hipFree(x);
hipFree(y);
return 0;
} | .text
.file "step6-saxpy-um.hip"
.globl _Z5saxpyifPfS_ # -- Begin function _Z5saxpyifPfS_
.p2align 4, 0x90
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_: # @_Z5saxpyifPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdx,%rcx,4), %xmm1
movss %xmm1, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__saxpy_line6_kernelifPfS_ # -- Begin function _Z33__device_stub__saxpy_line6_kernelifPfS_
.p2align 4, 0x90
.type _Z33__device_stub__saxpy_line6_kernelifPfS_,@function
_Z33__device_stub__saxpy_line6_kernelifPfS_: # @_Z33__device_stub__saxpy_line6_kernelifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18saxpy_line6_kernelifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z33__device_stub__saxpy_line6_kernelifPfS_, .Lfunc_end1-_Z33__device_stub__saxpy_line6_kernelifPfS_
.cfi_endproc
# -- End function
.globl _Z15saxpy_line6_gpuifPfS_ # -- Begin function _Z15saxpy_line6_gpuifPfS_
.p2align 4, 0x90
.type _Z15saxpy_line6_gpuifPfS_,@function
_Z15saxpy_line6_gpuifPfS_: # @_Z15saxpy_line6_gpuifPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movss %xmm0, 4(%rsp) # 4-byte Spill
movl %edi, %ebp
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movl %ebp, 12(%rsp)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 8(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18saxpy_line6_kernelifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15saxpy_line6_gpuifPfS_, .Lfunc_end2-_Z15saxpy_line6_gpuifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x40400000 # float 3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
xorl %ecx, %ecx
movq (%rsp), %rdx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1073741824, (%rax,%rcx,4) # imm = 0x40000000
movl $0, (%rdx,%rcx,4)
incq %rcx
cmpq $4194304, %rcx # imm = 0x400000
jne .LBB3_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $4194304, %edi # imm = 0x400000
callq _Z15saxpy_line6_gpuifPfS_
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB3_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18saxpy_line6_kernelifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18saxpy_line6_kernelifPfS_,@object # @_Z18saxpy_line6_kernelifPfS_
.section .rodata,"a",@progbits
.globl _Z18saxpy_line6_kernelifPfS_
.p2align 3, 0x0
_Z18saxpy_line6_kernelifPfS_:
.quad _Z33__device_stub__saxpy_line6_kernelifPfS_
.size _Z18saxpy_line6_kernelifPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "y[%d] = %f, "
.size .L.str.1, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18saxpy_line6_kernelifPfS_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " data"
.size .Lstr, 6
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " result"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__saxpy_line6_kernelifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18saxpy_line6_kernelifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18saxpy_line6_kernelifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0205 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0205 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FFMA R7, R2, c[0x0][0x164], R7 ; /* 0x0000590002077a23 */
/* 0x004fca0000000007 */
/*00b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18saxpy_line6_kernelifPfS_
.globl _Z18saxpy_line6_kernelifPfS_
.p2align 8
.type _Z18saxpy_line6_kernelifPfS_,@function
_Z18saxpy_line6_kernelifPfS_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b32 s0, s[0:1], 0x4
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v3, s0, v2
global_store_b32 v[0:1], v3, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18saxpy_line6_kernelifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18saxpy_line6_kernelifPfS_, .Lfunc_end0-_Z18saxpy_line6_kernelifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18saxpy_line6_kernelifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18saxpy_line6_kernelifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001489af_00000000-6_step6-saxpy-um.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5saxpyifPfS_
.type _Z5saxpyifPfS_, @function
_Z5saxpyifPfS_:
.LFB2057:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L3
movslq %edi, %rdi
leaq 0(,%rdi,4), %rcx
movl $0, %eax
.L5:
movaps %xmm0, %xmm1
mulss (%rsi,%rax), %xmm1
addss (%rdx,%rax), %xmm1
movss %xmm1, (%rdx,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z5saxpyifPfS_, .-_Z5saxpyifPfS_
.globl _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_
.type _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_, @function
_Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movss %xmm0, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18saxpy_line6_kernelifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_, .-_Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_
.globl _Z18saxpy_line6_kernelifPfS_
.type _Z18saxpy_line6_kernelifPfS_, @function
_Z18saxpy_line6_kernelifPfS_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z18saxpy_line6_kernelifPfS_, .-_Z18saxpy_line6_kernelifPfS_
.globl _Z15saxpy_line6_gpuifPfS_
.type _Z15saxpy_line6_gpuifPfS_, @function
_Z15saxpy_line6_gpuifPfS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebx
movss %xmm0, 12(%rsp)
movq %rsi, %rbp
movq %rdx, %r12
movl $4096, 24(%rsp)
movl $1, 28(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movss 12(%rsp), %xmm0
movl %ebx, %edi
call _Z42__device_stub__Z18saxpy_line6_kernelifPfS_ifPfS_
jmp .L16
.cfi_endproc
.LFE2058:
.size _Z15saxpy_line6_gpuifPfS_, .-_Z15saxpy_line6_gpuifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string " data\n"
.LC3:
.string "y[%d] = %f, "
.LC4:
.string "\n"
.LC6:
.string " result\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC0(%rip), %xmm0
.L20:
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax)
movq 16(%rsp), %rdx
movl $0x00000000, (%rdx,%rax)
addq $4, %rax
cmpq $16777216, %rax
jne .L20
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L21:
movq 16(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L21
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movss .LC5(%rip), %xmm0
movl $4194304, %edi
call _Z15saxpy_line6_gpuifPfS_
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC3(%rip), %rbp
.L22:
movq 16(%rsp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L22
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z18saxpy_line6_kernelifPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z18saxpy_line6_kernelifPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.align 4
.LC5:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "step6-saxpy-um.hip"
.globl _Z5saxpyifPfS_ # -- Begin function _Z5saxpyifPfS_
.p2align 4, 0x90
.type _Z5saxpyifPfS_,@function
_Z5saxpyifPfS_: # @_Z5saxpyifPfS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %edi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rsi,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm0, %xmm1
addss (%rdx,%rcx,4), %xmm1
movss %xmm1, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z5saxpyifPfS_, .Lfunc_end0-_Z5saxpyifPfS_
.cfi_endproc
# -- End function
.globl _Z33__device_stub__saxpy_line6_kernelifPfS_ # -- Begin function _Z33__device_stub__saxpy_line6_kernelifPfS_
.p2align 4, 0x90
.type _Z33__device_stub__saxpy_line6_kernelifPfS_,@function
_Z33__device_stub__saxpy_line6_kernelifPfS_: # @_Z33__device_stub__saxpy_line6_kernelifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movss %xmm0, 8(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18saxpy_line6_kernelifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z33__device_stub__saxpy_line6_kernelifPfS_, .Lfunc_end1-_Z33__device_stub__saxpy_line6_kernelifPfS_
.cfi_endproc
# -- End function
.globl _Z15saxpy_line6_gpuifPfS_ # -- Begin function _Z15saxpy_line6_gpuifPfS_
.p2align 4, 0x90
.type _Z15saxpy_line6_gpuifPfS_,@function
_Z15saxpy_line6_gpuifPfS_: # @_Z15saxpy_line6_gpuifPfS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movss %xmm0, 4(%rsp) # 4-byte Spill
movl %edi, %ebp
movabsq $4294968320, %rdx # imm = 0x100000400
leaq 3072(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movl %ebp, 12(%rsp)
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 8(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18saxpy_line6_kernelifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z15saxpy_line6_gpuifPfS_, .Lfunc_end2-_Z15saxpy_line6_gpuifPfS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x40400000 # float 3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $16, %rsp
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
movq %rsp, %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
movq 8(%rsp), %rax
xorl %ecx, %ecx
movq (%rsp), %rdx
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1073741824, (%rax,%rcx,4) # imm = 0x40000000
movl $0, (%rdx,%rcx,4)
incq %rcx
cmpq $4194304, %rcx # imm = 0x400000
jne .LBB3_1
# %bb.2:
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB3_3
# %bb.4:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rsi
movq (%rsp), %rdx
movss .LCPI3_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movl $4194304, %edi # imm = 0x400000
callq _Z15saxpy_line6_gpuifPfS_
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB3_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $16, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18saxpy_line6_kernelifPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18saxpy_line6_kernelifPfS_,@object # @_Z18saxpy_line6_kernelifPfS_
.section .rodata,"a",@progbits
.globl _Z18saxpy_line6_kernelifPfS_
.p2align 3, 0x0
_Z18saxpy_line6_kernelifPfS_:
.quad _Z33__device_stub__saxpy_line6_kernelifPfS_
.size _Z18saxpy_line6_kernelifPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "y[%d] = %f, "
.size .L.str.1, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z18saxpy_line6_kernelifPfS_"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " data"
.size .Lstr, 6
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " result"
.size .Lstr.1, 8
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__saxpy_line6_kernelifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18saxpy_line6_kernelifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__
void add(double* out,const double* a,const double* b){
int idx = blockIdx.x*blockDim.x + threadIdx.x;
out[idx]=a[idx]+b[idx];
} | code for sm_80
Function : _Z3addPdPKdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R8, R9, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fc800078e0209 */
/*0070*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x0c0fe400078e0209 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0209 */
/*00b0*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */
/* 0x004e0e0000000004 */
/*00c0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__
void add(double* out,const double* a,const double* b){
int idx = blockIdx.x*blockDim.x + threadIdx.x;
out[idx]=a[idx]+b[idx];
} | .file "tmpxft_0005c864_00000000-6_add_kern.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3addPdPKdS1_PdPKdS1_
.type _Z28__device_stub__Z3addPdPKdS1_PdPKdS1_, @function
_Z28__device_stub__Z3addPdPKdS1_PdPKdS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdPKdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z3addPdPKdS1_PdPKdS1_, .-_Z28__device_stub__Z3addPdPKdS1_PdPKdS1_
.globl _Z3addPdPKdS1_
.type _Z3addPdPKdS1_, @function
_Z3addPdPKdS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3addPdPKdS1_PdPKdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPdPKdS1_, .-_Z3addPdPKdS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPdPKdS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdPKdS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__
void add(double* out,const double* a,const double* b){
int idx = blockIdx.x*blockDim.x + threadIdx.x;
out[idx]=a[idx]+b[idx];
} | #include <hip/hip_runtime.h>
__global__
void add(double* out,const double* a,const double* b){
int idx = blockIdx.x*blockDim.x + threadIdx.x;
out[idx]=a[idx]+b[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__
void add(double* out,const double* a,const double* b){
int idx = blockIdx.x*blockDim.x + threadIdx.x;
out[idx]=a[idx]+b[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdPKdS1_
.globl _Z3addPdPKdS1_
.p2align 8
.type _Z3addPdPKdS1_,@function
_Z3addPdPKdS1_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdPKdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdPKdS1_, .Lfunc_end0-_Z3addPdPKdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdPKdS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdPKdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__
void add(double* out,const double* a,const double* b){
int idx = blockIdx.x*blockDim.x + threadIdx.x;
out[idx]=a[idx]+b[idx];
} | .text
.file "add_kern.hip"
.globl _Z18__device_stub__addPdPKdS1_ # -- Begin function _Z18__device_stub__addPdPKdS1_
.p2align 4, 0x90
.type _Z18__device_stub__addPdPKdS1_,@function
_Z18__device_stub__addPdPKdS1_: # @_Z18__device_stub__addPdPKdS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdPKdS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdPKdS1_, .Lfunc_end0-_Z18__device_stub__addPdPKdS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdPKdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdPKdS1_,@object # @_Z3addPdPKdS1_
.section .rodata,"a",@progbits
.globl _Z3addPdPKdS1_
.p2align 3, 0x0
_Z3addPdPKdS1_:
.quad _Z18__device_stub__addPdPKdS1_
.size _Z3addPdPKdS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPdPKdS1_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdPKdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdPKdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPdPKdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R8, R9, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fc800078e0209 */
/*0070*/ IMAD.WIDE R4, R8.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x0c0fe400078e0209 */
/*0080*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*0090*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00a0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0209 */
/*00b0*/ DADD R6, R2, R4 ; /* 0x0000000002067229 */
/* 0x004e0e0000000004 */
/*00c0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x001fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPdPKdS1_
.globl _Z3addPdPKdS1_
.p2align 8
.type _Z3addPdPKdS1_,@function
_Z3addPdPKdS1_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b64 v[2:3], v[2:3], off
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], v[4:5]
global_store_b64 v[0:1], v[2:3], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPdPKdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPdPKdS1_, .Lfunc_end0-_Z3addPdPKdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPdPKdS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPdPKdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0005c864_00000000-6_add_kern.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z3addPdPKdS1_PdPKdS1_
.type _Z28__device_stub__Z3addPdPKdS1_PdPKdS1_, @function
_Z28__device_stub__Z3addPdPKdS1_PdPKdS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPdPKdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z3addPdPKdS1_PdPKdS1_, .-_Z28__device_stub__Z3addPdPKdS1_PdPKdS1_
.globl _Z3addPdPKdS1_
.type _Z3addPdPKdS1_, @function
_Z3addPdPKdS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z3addPdPKdS1_PdPKdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addPdPKdS1_, .-_Z3addPdPKdS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addPdPKdS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPdPKdS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add_kern.hip"
.globl _Z18__device_stub__addPdPKdS1_ # -- Begin function _Z18__device_stub__addPdPKdS1_
.p2align 4, 0x90
.type _Z18__device_stub__addPdPKdS1_,@function
_Z18__device_stub__addPdPKdS1_: # @_Z18__device_stub__addPdPKdS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPdPKdS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPdPKdS1_, .Lfunc_end0-_Z18__device_stub__addPdPKdS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPdPKdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPdPKdS1_,@object # @_Z3addPdPKdS1_
.section .rodata,"a",@progbits
.globl _Z3addPdPKdS1_
.p2align 3, 0x0
_Z3addPdPKdS1_:
.quad _Z18__device_stub__addPdPKdS1_
.size _Z3addPdPKdS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addPdPKdS1_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPdPKdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPdPKdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ComputeBiasTermKernel( float *biasTerm, float cFactor, float *winningFraction, int activeCells, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
biasTerm[threadId] = cFactor * ( 1.00f / activeCells - winningFraction[threadId]);
}
} | code for sm_80
Function : _Z21ComputeBiasTermKernelPffS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F R3, c[0x0][0x178] ; /* 0x00005e0000037b06 */
/* 0x000e220000201400 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IADD3 R2, R3, 0x1800000, RZ ; /* 0x0180000003027810 */
/* 0x001fc80007ffe0ff */
/*00b0*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000002027812 */
/* 0x000fc800078ec0ff */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; /* 0x01ffffff0200780c */
/* 0x000fda0003f04070 */
/*00d0*/ @P0 BRA 0x110 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R2, 0x100 ; /* 0x0000010000027802 */
/* 0x000fe40000000f00 */
/*00f0*/ CALL.REL.NOINC 0x1d0 ; /* 0x000000d000007944 */
/* 0x000fea0003c00000 */
/*0100*/ BRA 0x150 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0110*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x000e240000001000 */
/*0120*/ FFMA R2, R3, R4, -1 ; /* 0xbf80000003027423 */
/* 0x001fc80000000004 */
/*0130*/ FADD.FTZ R5, -R2, -RZ ; /* 0x800000ff02057221 */
/* 0x000fc80000010100 */
/*0140*/ FFMA R4, R4, R5, R4 ; /* 0x0000000504047223 */
/* 0x000fe40000000004 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FADD R6, -R3, R4 ; /* 0x0000000403067221 */
/* 0x006fe40000000100 */
/*0190*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*01a0*/ FMUL R7, R6, c[0x0][0x168] ; /* 0x00005a0006077a20 */
/* 0x000fca0000400000 */
/*01b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.SHL.U32 R4, R3, 0x2, RZ ; /* 0x0000000203047824 */
/* 0x000fca00078e00ff */
/*01e0*/ SHF.R.U32.HI R4, RZ, 0x18, R4 ; /* 0x00000018ff047819 */
/* 0x000fc80000011604 */
/*01f0*/ ISETP.NE.U32.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05070 */
/*0200*/ @P0 BRA 0x2c0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.SHL.U32 R4, R3, 0x2, RZ ; /* 0x0000000203047824 */
/* 0x000fca00078e00ff */
/*0220*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0230*/ @!P0 MUFU.RCP R4, R3 ; /* 0x0000000300048308 */
/* 0x0000620000001000 */
/*0240*/ @!P0 BRA 0x4e0 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0250*/ FFMA R3, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003037823 */
/* 0x001fc800000000ff */
/*0260*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x002e240000001000 */
/*0270*/ FFMA R5, R3, R4, -1 ; /* 0xbf80000003057423 */
/* 0x001fc80000000004 */
/*0280*/ FADD.FTZ R5, -R5, -RZ ; /* 0x800000ff05057221 */
/* 0x000fc80000010100 */
/*0290*/ FFMA R4, R4, R5, R4 ; /* 0x0000000504047223 */
/* 0x000fc80000000004 */
/*02a0*/ FFMA R4, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004047823 */
/* 0x000fe200000000ff */
/*02b0*/ BRA 0x4e0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*02c0*/ IADD3 R5, R4, -0xfd, RZ ; /* 0xffffff0304057810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f04070 */
/*02e0*/ @P0 BRA 0x4d0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT R6, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03067812 */
/* 0x000fe200078ec0ff */
/*0300*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3 ; /* 0x00000003ff0a7424 */
/* 0x000fc600078e00ff */
/*0310*/ LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000006067812 */
/* 0x000fe400078efcff */
/*0320*/ SHF.L.U32 R11, R10, R5, RZ ; /* 0x000000050a0b7219 */
/* 0x000fe400000006ff */
/*0330*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000001000 */
/*0340*/ FFMA R8, R6, R7, -1 ; /* 0xbf80000006087423 */
/* 0x001fc80000000007 */
/*0350*/ FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08087221 */
/* 0x000fc80000010100 */
/*0360*/ FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ; /* 0x0000000807097223 */
/* 0x1c0fe40000004007 */
/*0370*/ FFMA.RP R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc60000008007 */
/*0380*/ LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff09077812 */
/* 0x040fe400078ec0ff */
/*0390*/ FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fe40003f1d000 */
/*03a0*/ LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007087812 */
/* 0x000fe400078efcff */
/*03b0*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*03c0*/ LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b067212 */
/* 0x000fc600078ec0ff */
/*03d0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*03e0*/ SHF.R.U32.HI R6, RZ, R5, R6 ; /* 0x00000005ff067219 */
/* 0x000fc80000011606 */
/*03f0*/ LOP3.LUT P1, RZ, R7, R5, R8, 0xf8, !PT ; /* 0x0000000507ff7212 */
/* 0x000fe4000782f808 */
/*0400*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe4000780c0ff */
/*0410*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fc8000784c0ff */
/*0420*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0430*/ LOP3.LUT P1, RZ, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03ff7812 */
/* 0x000fe4000782c0ff */
/*0440*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0450*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*0460*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0470*/ IADD3 R5, R4, -0xfc, RZ ; /* 0xffffff0404057810 */
/* 0x000fc80007ffe0ff */
/*0480*/ SHF.R.U32.HI R4, RZ, R5, R8 ; /* 0x00000005ff047219 */
/* 0x000fce0000011608 */
/*0490*/ @!P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104048810 */
/* 0x000fca0007ffe0ff */
/*04a0*/ @!P1 IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204049824 */
/* 0x000fca00078e00ff */
/*04b0*/ LOP3.LUT R4, R4, 0x80000000, R3, 0xf8, !PT ; /* 0x8000000004047812 */
/* 0x000fe200078ef803 */
/*04c0*/ BRA 0x4e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*04d0*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x0000640000001000 */
/*04e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x001fc800078e00ff */
/*04f0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffb0002007950 */
/* 0x000fea0003c3ffff */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ComputeBiasTermKernel( float *biasTerm, float cFactor, float *winningFraction, int activeCells, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
biasTerm[threadId] = cFactor * ( 1.00f / activeCells - winningFraction[threadId]);
}
} | .file "tmpxft_0016879d_00000000-6_ComputeBiasTermKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
.type _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii, @function
_Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21ComputeBiasTermKernelPffS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii, .-_Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
.globl _Z21ComputeBiasTermKernelPffS_ii
.type _Z21ComputeBiasTermKernelPffS_ii, @function
_Z21ComputeBiasTermKernelPffS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21ComputeBiasTermKernelPffS_ii, .-_Z21ComputeBiasTermKernelPffS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21ComputeBiasTermKernelPffS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21ComputeBiasTermKernelPffS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ComputeBiasTermKernel( float *biasTerm, float cFactor, float *winningFraction, int activeCells, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
biasTerm[threadId] = cFactor * ( 1.00f / activeCells - winningFraction[threadId]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeBiasTermKernel( float *biasTerm, float cFactor, float *winningFraction, int activeCells, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
biasTerm[threadId] = cFactor * ( 1.00f / activeCells - winningFraction[threadId]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeBiasTermKernel( float *biasTerm, float cFactor, float *winningFraction, int activeCells, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
biasTerm[threadId] = cFactor * ( 1.00f / activeCells - winningFraction[threadId]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21ComputeBiasTermKernelPffS_ii
.globl _Z21ComputeBiasTermKernelPffS_ii
.p2align 8
.type _Z21ComputeBiasTermKernelPffS_ii,@function
_Z21ComputeBiasTermKernelPffS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s4, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_load_b32 s2, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s4
v_div_scale_f32 v4, null, v3, v3, 1.0
v_div_scale_f32 v7, vcc_lo, 1.0, v3, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f32 v3, v4, v3, 1.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v3, v2
v_mul_f32_e32 v2, s2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21ComputeBiasTermKernelPffS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21ComputeBiasTermKernelPffS_ii, .Lfunc_end0-_Z21ComputeBiasTermKernelPffS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21ComputeBiasTermKernelPffS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21ComputeBiasTermKernelPffS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ComputeBiasTermKernel( float *biasTerm, float cFactor, float *winningFraction, int activeCells, int maxCells )
{
int threadId = blockDim.x*blockIdx.y*gridDim.x //rows preceeding current row in grid
+ blockDim.x*blockIdx.x //blocks preceeding current block
+ threadIdx.x;
if(threadId < maxCells)
{
biasTerm[threadId] = cFactor * ( 1.00f / activeCells - winningFraction[threadId]);
}
} | .text
.file "ComputeBiasTermKernel.hip"
.globl _Z36__device_stub__ComputeBiasTermKernelPffS_ii # -- Begin function _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.p2align 4, 0x90
.type _Z36__device_stub__ComputeBiasTermKernelPffS_ii,@function
_Z36__device_stub__ComputeBiasTermKernelPffS_ii: # @_Z36__device_stub__ComputeBiasTermKernelPffS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21ComputeBiasTermKernelPffS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__ComputeBiasTermKernelPffS_ii, .Lfunc_end0-_Z36__device_stub__ComputeBiasTermKernelPffS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21ComputeBiasTermKernelPffS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21ComputeBiasTermKernelPffS_ii,@object # @_Z21ComputeBiasTermKernelPffS_ii
.section .rodata,"a",@progbits
.globl _Z21ComputeBiasTermKernelPffS_ii
.p2align 3, 0x0
_Z21ComputeBiasTermKernelPffS_ii:
.quad _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.size _Z21ComputeBiasTermKernelPffS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21ComputeBiasTermKernelPffS_ii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21ComputeBiasTermKernelPffS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21ComputeBiasTermKernelPffS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x001fc800078e0203 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ I2F R3, c[0x0][0x178] ; /* 0x00005e0000037b06 */
/* 0x000e220000201400 */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IADD3 R2, R3, 0x1800000, RZ ; /* 0x0180000003027810 */
/* 0x001fc80007ffe0ff */
/*00b0*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000002027812 */
/* 0x000fc800078ec0ff */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ffffff, PT ; /* 0x01ffffff0200780c */
/* 0x000fda0003f04070 */
/*00d0*/ @P0 BRA 0x110 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*00e0*/ MOV R2, 0x100 ; /* 0x0000010000027802 */
/* 0x000fe40000000f00 */
/*00f0*/ CALL.REL.NOINC 0x1d0 ; /* 0x000000d000007944 */
/* 0x000fea0003c00000 */
/*0100*/ BRA 0x150 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0110*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x000e240000001000 */
/*0120*/ FFMA R2, R3, R4, -1 ; /* 0xbf80000003027423 */
/* 0x001fc80000000004 */
/*0130*/ FADD.FTZ R5, -R2, -RZ ; /* 0x800000ff02057221 */
/* 0x000fc80000010100 */
/*0140*/ FFMA R4, R4, R5, R4 ; /* 0x0000000504047223 */
/* 0x000fe40000000004 */
/*0150*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*0170*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0180*/ FADD R6, -R3, R4 ; /* 0x0000000403067221 */
/* 0x006fe40000000100 */
/*0190*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fc800078e0205 */
/*01a0*/ FMUL R7, R6, c[0x0][0x168] ; /* 0x00005a0006077a20 */
/* 0x000fca0000400000 */
/*01b0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.SHL.U32 R4, R3, 0x2, RZ ; /* 0x0000000203047824 */
/* 0x000fca00078e00ff */
/*01e0*/ SHF.R.U32.HI R4, RZ, 0x18, R4 ; /* 0x00000018ff047819 */
/* 0x000fc80000011604 */
/*01f0*/ ISETP.NE.U32.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05070 */
/*0200*/ @P0 BRA 0x2c0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.SHL.U32 R4, R3, 0x2, RZ ; /* 0x0000000203047824 */
/* 0x000fca00078e00ff */
/*0220*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0230*/ @!P0 MUFU.RCP R4, R3 ; /* 0x0000000300048308 */
/* 0x0000620000001000 */
/*0240*/ @!P0 BRA 0x4e0 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0250*/ FFMA R3, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003037823 */
/* 0x001fc800000000ff */
/*0260*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x002e240000001000 */
/*0270*/ FFMA R5, R3, R4, -1 ; /* 0xbf80000003057423 */
/* 0x001fc80000000004 */
/*0280*/ FADD.FTZ R5, -R5, -RZ ; /* 0x800000ff05057221 */
/* 0x000fc80000010100 */
/*0290*/ FFMA R4, R4, R5, R4 ; /* 0x0000000504047223 */
/* 0x000fc80000000004 */
/*02a0*/ FFMA R4, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004047823 */
/* 0x000fe200000000ff */
/*02b0*/ BRA 0x4e0 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*02c0*/ IADD3 R5, R4, -0xfd, RZ ; /* 0xffffff0304057810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f04070 */
/*02e0*/ @P0 BRA 0x4d0 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*02f0*/ LOP3.LUT R6, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03067812 */
/* 0x000fe200078ec0ff */
/*0300*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3 ; /* 0x00000003ff0a7424 */
/* 0x000fc600078e00ff */
/*0310*/ LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000006067812 */
/* 0x000fe400078efcff */
/*0320*/ SHF.L.U32 R11, R10, R5, RZ ; /* 0x000000050a0b7219 */
/* 0x000fe400000006ff */
/*0330*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000001000 */
/*0340*/ FFMA R8, R6, R7, -1 ; /* 0xbf80000006087423 */
/* 0x001fc80000000007 */
/*0350*/ FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08087221 */
/* 0x000fc80000010100 */
/*0360*/ FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ; /* 0x0000000807097223 */
/* 0x1c0fe40000004007 */
/*0370*/ FFMA.RP R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc60000008007 */
/*0380*/ LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff09077812 */
/* 0x040fe400078ec0ff */
/*0390*/ FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fe40003f1d000 */
/*03a0*/ LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007087812 */
/* 0x000fe400078efcff */
/*03b0*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*03c0*/ LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b067212 */
/* 0x000fc600078ec0ff */
/*03d0*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*03e0*/ SHF.R.U32.HI R6, RZ, R5, R6 ; /* 0x00000005ff067219 */
/* 0x000fc80000011606 */
/*03f0*/ LOP3.LUT P1, RZ, R7, R5, R8, 0xf8, !PT ; /* 0x0000000507ff7212 */
/* 0x000fe4000782f808 */
/*0400*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe4000780c0ff */
/*0410*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fc8000784c0ff */
/*0420*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0430*/ LOP3.LUT P1, RZ, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03ff7812 */
/* 0x000fe4000782c0ff */
/*0440*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0450*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*0460*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0470*/ IADD3 R5, R4, -0xfc, RZ ; /* 0xffffff0404057810 */
/* 0x000fc80007ffe0ff */
/*0480*/ SHF.R.U32.HI R4, RZ, R5, R8 ; /* 0x00000005ff047219 */
/* 0x000fce0000011608 */
/*0490*/ @!P0 IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104048810 */
/* 0x000fca0007ffe0ff */
/*04a0*/ @!P1 IMAD.SHL.U32 R4, R4, 0x2, RZ ; /* 0x0000000204049824 */
/* 0x000fca00078e00ff */
/*04b0*/ LOP3.LUT R4, R4, 0x80000000, R3, 0xf8, !PT ; /* 0x8000000004047812 */
/* 0x000fe200078ef803 */
/*04c0*/ BRA 0x4e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*04d0*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x0000640000001000 */
/*04e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x001fc800078e00ff */
/*04f0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffb0002007950 */
/* 0x000fea0003c3ffff */
/*0500*/ BRA 0x500; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21ComputeBiasTermKernelPffS_ii
.globl _Z21ComputeBiasTermKernelPffS_ii
.p2align 8
.type _Z21ComputeBiasTermKernelPffS_ii,@function
_Z21ComputeBiasTermKernelPffS_ii:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0x2c
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s3, s15
s_and_b32 s4, s4, 0xffff
s_add_i32 s3, s3, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s3, s4, v[0:1]
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s4, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_load_b32 s2, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_load_b64 s[0:1], s[0:1], 0x0
global_load_b32 v2, v[2:3], off
v_cvt_f32_i32_e32 v3, s4
v_div_scale_f32 v4, null, v3, v3, 1.0
v_div_scale_f32 v7, vcc_lo, 1.0, v3, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_div_fixup_f32 v3, v4, v3, 1.0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v2, v3, v2
v_mul_f32_e32 v2, s2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21ComputeBiasTermKernelPffS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21ComputeBiasTermKernelPffS_ii, .Lfunc_end0-_Z21ComputeBiasTermKernelPffS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21ComputeBiasTermKernelPffS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21ComputeBiasTermKernelPffS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016879d_00000000-6_ComputeBiasTermKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
.type _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii, @function
_Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rsi, 8(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21ComputeBiasTermKernelPffS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii, .-_Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
.globl _Z21ComputeBiasTermKernelPffS_ii
.type _Z21ComputeBiasTermKernelPffS_ii, @function
_Z21ComputeBiasTermKernelPffS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21ComputeBiasTermKernelPffS_iiPffS_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z21ComputeBiasTermKernelPffS_ii, .-_Z21ComputeBiasTermKernelPffS_ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z21ComputeBiasTermKernelPffS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z21ComputeBiasTermKernelPffS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ComputeBiasTermKernel.hip"
.globl _Z36__device_stub__ComputeBiasTermKernelPffS_ii # -- Begin function _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.p2align 4, 0x90
.type _Z36__device_stub__ComputeBiasTermKernelPffS_ii,@function
_Z36__device_stub__ComputeBiasTermKernelPffS_ii: # @_Z36__device_stub__ComputeBiasTermKernelPffS_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movss %xmm0, 12(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21ComputeBiasTermKernelPffS_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__ComputeBiasTermKernelPffS_ii, .Lfunc_end0-_Z36__device_stub__ComputeBiasTermKernelPffS_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21ComputeBiasTermKernelPffS_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21ComputeBiasTermKernelPffS_ii,@object # @_Z21ComputeBiasTermKernelPffS_ii
.section .rodata,"a",@progbits
.globl _Z21ComputeBiasTermKernelPffS_ii
.p2align 3, 0x0
_Z21ComputeBiasTermKernelPffS_ii:
.quad _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.size _Z21ComputeBiasTermKernelPffS_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21ComputeBiasTermKernelPffS_ii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__ComputeBiasTermKernelPffS_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21ComputeBiasTermKernelPffS_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
void cureTest() {
float sqrt
}*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
void cureTest() {
float sqrt
}*/ | .file "tmpxft_0013c1d3_00000000-6_reuse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
void cureTest() {
float sqrt
}*/ | #include <hip/hip_runtime.h>
/*
void cureTest() {
float sqrt
}*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
void cureTest() {
float sqrt
}*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
void cureTest() {
float sqrt
}*/ | .text
.file "reuse.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013c1d3_00000000-6_reuse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reuse.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda.h"
extern "C" {
__device__ double sobely_kernel[3][3] = {{-1, -2, -1}, {0, 0, 0}, {1, 2, 1}};
__device__ double sobelx_kernel[3][3] = {{-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};
__device__ double sharpen_kernel[3][3] = {{0, -1, 0}, {-1, 5, -1}, {0, -1, 0}};
__device__ double blur_kernel[3][3] =
{{0, 0.2, 0}, {0.2, 0.2, 0.2}, {0, 0.2, 0}};
__device__
void simple_convolve(const double* channel,
int dimx,
const double kernel[3][3],
int y,
int x,
double * out) {
double result = 0;
for (int i = -1; i <= 1; ++i) {
for (int j = -1; j <= 1; ++j) {
result += channel[(y + i) * dimx + x + j] * kernel[i + 1][j + 1];
}
}
*out = result;
}
__global__
void sobel_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double sobely;
double sobelx;
simple_convolve(in_channel,
dimx,
sobely_kernel,
idy,
idx,
&sobely);
simple_convolve(in_channel,
dimx,
sobelx_kernel,
idy,
idx,
&sobelx);
out_channel[idy * dimx + idx] = sqrtf(sobely*sobely + sobelx*sobelx);
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = 0;
}
}
__global__
void blur_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double result;
simple_convolve(in_channel,
dimx,
blur_kernel,
idy,
idx,
&result);
out_channel[idy * dimx + idx] = result;
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = in_channel[idy * dimx + idx];
}
}
__global__
void mix_channels(const double * rchannels,
const double * gchannels,
const double * bchannels,
int len,
double* out_channel) {
int id = blockIdx.x*1024 + threadIdx.x;
if (id < len) {
out_channel[id] = rchannels[id] * 0.33
+ gchannels[id] * 0.34
+ bchannels[id] * 0.33;
}
}
__global__
void smoothen(const double* in_channel,
int dimy,
int dimx,
const double* edge_channel,
unsigned char* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy >= dimy || idx >= dimx) {
return;
}
double result = 0;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
simple_convolve(in_channel,
dimx,
(edge_channel[idy * dimx + idx] >= 30 ? sharpen_kernel : blur_kernel),
idy,
idx,
&result);
} else {
result = in_channel[idy * dimx + idx];
}
out_channel[idy * dimx + idx] =
(unsigned char)max(0., min(255., round(result)));
}
__global__
void parallel_max(const double* in, int length, double* out) {
__shared__ double values[1024];
int i = 1;
int idx = blockIdx.x*1024 + threadIdx.x;
values[threadIdx.x] = idx < length ? in[idx] : 0;
__syncthreads();
while (i < 1024) {
if (threadIdx.x + i < 1024) {
values[threadIdx.x] = max(values[threadIdx.x], values[threadIdx.x + i]);
}
i *= 2;
__syncthreads();
}
out[blockIdx.x] = values[0];
}
__global__
void divide_all(double * array, int length, double* divider) { // remove *
int idx = blockIdx.x*1024 + threadIdx.x;
if (idx < length) {
array[idx] *= 255./(*divider);
}
}
} | .file "tmpxft_000d9d2e_00000000-6_filter-noise.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl simple_convolve
.type simple_convolve, @function
simple_convolve:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size simple_convolve, .-simple_convolve
.globl _Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd
.type _Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd, @function
_Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq sobel_filter(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd, .-_Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd
.globl sobel_filter
.type sobel_filter, @function
sobel_filter:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size sobel_filter, .-sobel_filter
.globl _Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd
.type _Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd, @function
_Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq blur_filter(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd, .-_Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd
.globl blur_filter
.type blur_filter, @function
blur_filter:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size blur_filter, .-blur_filter
.globl _Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd
.type _Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd, @function
_Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd:
.LFB2056:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq mix_channels(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd, .-_Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd
.globl mix_channels
.type mix_channels, @function
mix_channels:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size mix_channels, .-mix_channels
.globl _Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph
.type _Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph, @function
_Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph:
.LFB2058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq smoothen(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph, .-_Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph
.globl smoothen
.type smoothen, @function
smoothen:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size smoothen, .-smoothen
.globl _Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd
.type _Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd, @function
_Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd:
.LFB2060:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq parallel_max(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd, .-_Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd
.globl parallel_max
.type parallel_max, @function
parallel_max:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size parallel_max, .-parallel_max
.globl _Z33__device_stub__Z10divide_allPdiS_PdiS_
.type _Z33__device_stub__Z10divide_allPdiS_PdiS_, @function
_Z33__device_stub__Z10divide_allPdiS_PdiS_:
.LFB2062:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq divide_all(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z33__device_stub__Z10divide_allPdiS_PdiS_, .-_Z33__device_stub__Z10divide_allPdiS_PdiS_
.globl divide_all
.type divide_all, @function
divide_all:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10divide_allPdiS_PdiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size divide_all, .-divide_all
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "divide_all"
.LC1:
.string "parallel_max"
.LC2:
.string "smoothen"
.LC3:
.string "mix_channels"
.LC4:
.string "blur_filter"
.LC5:
.string "sobel_filter"
.LC6:
.string "sobely_kernel"
.LC7:
.string "sobelx_kernel"
.LC8:
.string "sharpen_kernel"
.LC9:
.string "blur_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq divide_all(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq parallel_max(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq smoothen(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq mix_channels(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq blur_filter(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq sobel_filter(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13sobely_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13sobelx_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14sharpen_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11blur_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11blur_kernel
.comm _ZL11blur_kernel,72,32
.local _ZL14sharpen_kernel
.comm _ZL14sharpen_kernel,72,32
.local _ZL13sobelx_kernel
.comm _ZL13sobelx_kernel,72,32
.local _ZL13sobely_kernel
.comm _ZL13sobely_kernel,72,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda.h"
extern "C" {
__device__ double sobely_kernel[3][3] = {{-1, -2, -1}, {0, 0, 0}, {1, 2, 1}};
__device__ double sobelx_kernel[3][3] = {{-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};
__device__ double sharpen_kernel[3][3] = {{0, -1, 0}, {-1, 5, -1}, {0, -1, 0}};
__device__ double blur_kernel[3][3] =
{{0, 0.2, 0}, {0.2, 0.2, 0.2}, {0, 0.2, 0}};
__device__
void simple_convolve(const double* channel,
int dimx,
const double kernel[3][3],
int y,
int x,
double * out) {
double result = 0;
for (int i = -1; i <= 1; ++i) {
for (int j = -1; j <= 1; ++j) {
result += channel[(y + i) * dimx + x + j] * kernel[i + 1][j + 1];
}
}
*out = result;
}
__global__
void sobel_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double sobely;
double sobelx;
simple_convolve(in_channel,
dimx,
sobely_kernel,
idy,
idx,
&sobely);
simple_convolve(in_channel,
dimx,
sobelx_kernel,
idy,
idx,
&sobelx);
out_channel[idy * dimx + idx] = sqrtf(sobely*sobely + sobelx*sobelx);
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = 0;
}
}
__global__
void blur_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double result;
simple_convolve(in_channel,
dimx,
blur_kernel,
idy,
idx,
&result);
out_channel[idy * dimx + idx] = result;
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = in_channel[idy * dimx + idx];
}
}
__global__
void mix_channels(const double * rchannels,
const double * gchannels,
const double * bchannels,
int len,
double* out_channel) {
int id = blockIdx.x*1024 + threadIdx.x;
if (id < len) {
out_channel[id] = rchannels[id] * 0.33
+ gchannels[id] * 0.34
+ bchannels[id] * 0.33;
}
}
__global__
void smoothen(const double* in_channel,
int dimy,
int dimx,
const double* edge_channel,
unsigned char* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy >= dimy || idx >= dimx) {
return;
}
double result = 0;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
simple_convolve(in_channel,
dimx,
(edge_channel[idy * dimx + idx] >= 30 ? sharpen_kernel : blur_kernel),
idy,
idx,
&result);
} else {
result = in_channel[idy * dimx + idx];
}
out_channel[idy * dimx + idx] =
(unsigned char)max(0., min(255., round(result)));
}
__global__
void parallel_max(const double* in, int length, double* out) {
__shared__ double values[1024];
int i = 1;
int idx = blockIdx.x*1024 + threadIdx.x;
values[threadIdx.x] = idx < length ? in[idx] : 0;
__syncthreads();
while (i < 1024) {
if (threadIdx.x + i < 1024) {
values[threadIdx.x] = max(values[threadIdx.x], values[threadIdx.x + i]);
}
i *= 2;
__syncthreads();
}
out[blockIdx.x] = values[0];
}
__global__
void divide_all(double * array, int length, double* divider) { // remove *
int idx = blockIdx.x*1024 + threadIdx.x;
if (idx < length) {
array[idx] *= 255./(*divider);
}
}
} | #include "hip/hip_runtime.h"
extern "C" {
__device__ double sobely_kernel[3][3] = {{-1, -2, -1}, {0, 0, 0}, {1, 2, 1}};
__device__ double sobelx_kernel[3][3] = {{-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};
__device__ double sharpen_kernel[3][3] = {{0, -1, 0}, {-1, 5, -1}, {0, -1, 0}};
__device__ double blur_kernel[3][3] =
{{0, 0.2, 0}, {0.2, 0.2, 0.2}, {0, 0.2, 0}};
__device__
void simple_convolve(const double* channel,
int dimx,
const double kernel[3][3],
int y,
int x,
double * out) {
double result = 0;
for (int i = -1; i <= 1; ++i) {
for (int j = -1; j <= 1; ++j) {
result += channel[(y + i) * dimx + x + j] * kernel[i + 1][j + 1];
}
}
*out = result;
}
__global__
void sobel_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double sobely;
double sobelx;
simple_convolve(in_channel,
dimx,
sobely_kernel,
idy,
idx,
&sobely);
simple_convolve(in_channel,
dimx,
sobelx_kernel,
idy,
idx,
&sobelx);
out_channel[idy * dimx + idx] = sqrtf(sobely*sobely + sobelx*sobelx);
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = 0;
}
}
__global__
void blur_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double result;
simple_convolve(in_channel,
dimx,
blur_kernel,
idy,
idx,
&result);
out_channel[idy * dimx + idx] = result;
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = in_channel[idy * dimx + idx];
}
}
__global__
void mix_channels(const double * rchannels,
const double * gchannels,
const double * bchannels,
int len,
double* out_channel) {
int id = blockIdx.x*1024 + threadIdx.x;
if (id < len) {
out_channel[id] = rchannels[id] * 0.33
+ gchannels[id] * 0.34
+ bchannels[id] * 0.33;
}
}
__global__
void smoothen(const double* in_channel,
int dimy,
int dimx,
const double* edge_channel,
unsigned char* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy >= dimy || idx >= dimx) {
return;
}
double result = 0;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
simple_convolve(in_channel,
dimx,
(edge_channel[idy * dimx + idx] >= 30 ? sharpen_kernel : blur_kernel),
idy,
idx,
&result);
} else {
result = in_channel[idy * dimx + idx];
}
out_channel[idy * dimx + idx] =
(unsigned char)max(0., min(255., round(result)));
}
__global__
void parallel_max(const double* in, int length, double* out) {
__shared__ double values[1024];
int i = 1;
int idx = blockIdx.x*1024 + threadIdx.x;
values[threadIdx.x] = idx < length ? in[idx] : 0;
__syncthreads();
while (i < 1024) {
if (threadIdx.x + i < 1024) {
values[threadIdx.x] = max(values[threadIdx.x], values[threadIdx.x + i]);
}
i *= 2;
__syncthreads();
}
out[blockIdx.x] = values[0];
}
__global__
void divide_all(double * array, int length, double* divider) { // remove *
int idx = blockIdx.x*1024 + threadIdx.x;
if (idx < length) {
array[idx] *= 255./(*divider);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
extern "C" {
__device__ double sobely_kernel[3][3] = {{-1, -2, -1}, {0, 0, 0}, {1, 2, 1}};
__device__ double sobelx_kernel[3][3] = {{-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};
__device__ double sharpen_kernel[3][3] = {{0, -1, 0}, {-1, 5, -1}, {0, -1, 0}};
__device__ double blur_kernel[3][3] =
{{0, 0.2, 0}, {0.2, 0.2, 0.2}, {0, 0.2, 0}};
__device__
void simple_convolve(const double* channel,
int dimx,
const double kernel[3][3],
int y,
int x,
double * out) {
double result = 0;
for (int i = -1; i <= 1; ++i) {
for (int j = -1; j <= 1; ++j) {
result += channel[(y + i) * dimx + x + j] * kernel[i + 1][j + 1];
}
}
*out = result;
}
__global__
void sobel_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double sobely;
double sobelx;
simple_convolve(in_channel,
dimx,
sobely_kernel,
idy,
idx,
&sobely);
simple_convolve(in_channel,
dimx,
sobelx_kernel,
idy,
idx,
&sobelx);
out_channel[idy * dimx + idx] = sqrtf(sobely*sobely + sobelx*sobelx);
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = 0;
}
}
__global__
void blur_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double result;
simple_convolve(in_channel,
dimx,
blur_kernel,
idy,
idx,
&result);
out_channel[idy * dimx + idx] = result;
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = in_channel[idy * dimx + idx];
}
}
__global__
void mix_channels(const double * rchannels,
const double * gchannels,
const double * bchannels,
int len,
double* out_channel) {
int id = blockIdx.x*1024 + threadIdx.x;
if (id < len) {
out_channel[id] = rchannels[id] * 0.33
+ gchannels[id] * 0.34
+ bchannels[id] * 0.33;
}
}
__global__
void smoothen(const double* in_channel,
int dimy,
int dimx,
const double* edge_channel,
unsigned char* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy >= dimy || idx >= dimx) {
return;
}
double result = 0;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
simple_convolve(in_channel,
dimx,
(edge_channel[idy * dimx + idx] >= 30 ? sharpen_kernel : blur_kernel),
idy,
idx,
&result);
} else {
result = in_channel[idy * dimx + idx];
}
out_channel[idy * dimx + idx] =
(unsigned char)max(0., min(255., round(result)));
}
__global__
void parallel_max(const double* in, int length, double* out) {
__shared__ double values[1024];
int i = 1;
int idx = blockIdx.x*1024 + threadIdx.x;
values[threadIdx.x] = idx < length ? in[idx] : 0;
__syncthreads();
while (i < 1024) {
if (threadIdx.x + i < 1024) {
values[threadIdx.x] = max(values[threadIdx.x], values[threadIdx.x + i]);
}
i *= 2;
__syncthreads();
}
out[blockIdx.x] = values[0];
}
__global__
void divide_all(double * array, int length, double* divider) { // remove *
int idx = blockIdx.x*1024 + threadIdx.x;
if (idx < length) {
array[idx] *= 255./(*divider);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected sobel_filter
.globl sobel_filter
.p2align 8
.type sobel_filter,@function
sobel_filter:
s_load_b64 s[4:5], s[0:1], 0x8
v_bfe_u32 v6, v0, 10, 10
s_lshl_b32 s12, s15, 5
v_and_b32_e32 v1, 0x3ff, v0
s_lshl_b32 s11, s14, 5
s_mov_b32 s10, 0
v_add_nc_u32_e32 v8, s12, v6
s_mov_b32 s6, 0
v_add_nc_u32_e32 v0, s11, v1
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_le_i32_e64 s7, s2, v8
v_cmpx_gt_i32_e64 s2, v8
v_min_i32_e32 v2, v8, v0
s_add_i32 s2, s5, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_and_not1_b32 s7, s7, exec_lo
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_mov_b32 s6, exec_lo
v_cmp_gt_i32_e64 s2, 1, v2
s_or_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s7, s7, s2
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s8, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s7, exec_lo, s8
v_cmp_gt_i32_e32 vcc_lo, s4, v8
v_cmp_gt_i32_e64 s2, s5, v0
s_and_not1_b32 s6, s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s4, vcc_lo, s2
s_mov_b64 s[2:3], 0
s_and_b32 s10, s4, exec_lo
s_or_b32 exec_lo, exec_lo, s7
v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
s_and_saveexec_b32 s4, s6
s_cbranch_execz .LBB0_14
s_load_b64 s[2:3], s[0:1], 0x0
v_add3_u32 v4, v6, s12, -1
s_mov_b32 s13, -1
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, sobely_kernel@rel32@lo+4
s_addc_u32 s7, s7, sobely_kernel@rel32@hi+12
v_mad_u64_u32 v[2:3], null, s5, v4, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v4, v2, s11, -1
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
s_mov_b64 s[8:9], 0
v_lshlrev_b64 v[9:10], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v10, vcc_lo
.LBB0_7:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v5, s8
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v7, vcc_lo
s_add_u32 s14, s6, s8
s_addc_u32 s15, s7, s9
s_add_u32 s8, s8, 8
global_load_b64 v[9:10], v[9:10], off
s_load_b64 s[14:15], s[14:15], 0x0
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s8, 24
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[2:3], v[9:10], s[14:15], v[2:3]
s_cbranch_scc0 .LBB0_7
s_add_i32 s13, s13, 1
v_add_nc_u32_e32 v4, s5, v4
s_add_u32 s6, s6, 24
s_addc_u32 s7, s7, 0
s_cmp_lg_u32 s13, 2
s_cbranch_scc1 .LBB0_6
v_add3_u32 v4, v6, s12, -1
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, sobelx_kernel@rel32@lo+4
s_addc_u32 s7, s7, sobelx_kernel@rel32@hi+12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[6:7], null, s5, v4, v[1:2]
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
v_add3_u32 v6, v6, s11, -1
s_mov_b32 s11, -1
.p2align 6
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
s_mov_b64 s[8:9], 0
v_lshlrev_b64 v[9:10], 3, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v10, vcc_lo
.LBB0_11:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v1, s8
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v7, vcc_lo
s_add_u32 s12, s6, s8
s_addc_u32 s13, s7, s9
s_add_u32 s8, s8, 8
global_load_b64 v[9:10], v[9:10], off
s_load_b64 s[12:13], s[12:13], 0x0
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s8, 24
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[4:5], v[9:10], s[12:13], v[4:5]
s_cbranch_scc0 .LBB0_11
s_add_i32 s11, s11, 1
v_add_nc_u32_e32 v6, s5, v6
s_add_u32 s6, s6, 24
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s11, 2
s_cbranch_scc0 .LBB0_10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[4:5], v[4:5]
s_or_b32 s10, s10, exec_lo
v_fma_f64 v[1:2], v[2:3], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v1, v[1:2]
v_mul_f32_e32 v2, 0x4f800000, v1
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v2, vcc_lo
v_sqrt_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v1
v_fma_f32 v6, -v4, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v1, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v2, v1, vcc_lo
v_cvt_f64_f32_e32 v[2:3], v1
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s2, s10
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v8, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_16:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel sobel_filter
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size sobel_filter, .Lfunc_end0-sobel_filter
.section .AMDGPU.csdata,"",@progbits
.text
.protected blur_filter
.globl blur_filter
.p2align 8
.type blur_filter,@function
blur_filter:
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v7, v0, 10, 10
s_lshl_b32 s8, s15, 5
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s3, s14, 5
s_mov_b32 s10, 0
v_add_nc_u32_e32 v6, s8, v7
s_mov_b32 s9, 0
v_add_nc_u32_e32 v0, s3, v3
s_mov_b32 s11, exec_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_le_i32_e64 s12, s2, v6
v_cmpx_gt_i32_e64 s2, v6
v_min_i32_e32 v1, v6, v0
s_add_i32 s2, s7, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_and_not1_b32 s12, s12, exec_lo
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_mov_b32 s9, exec_lo
v_cmp_gt_i32_e64 s2, 1, v1
s_or_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, exec_lo
s_or_b32 s12, s12, s2
s_or_b32 exec_lo, exec_lo, s11
s_and_saveexec_b32 s11, s12
s_cbranch_execz .LBB1_6
v_cmp_gt_i32_e32 vcc_lo, s6, v6
v_cmp_gt_i32_e64 s2, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s6, vcc_lo, s2
s_mov_b32 s2, 0
s_and_saveexec_b32 s10, s6
s_xor_b32 s6, exec_lo, s10
s_cbranch_execz .LBB1_5
v_mad_u64_u32 v[4:5], null, v6, s7, v[0:1]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[1:2], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s10, s2, exec_lo
s_and_not1_b32 s9, s9, exec_lo
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s11
s_and_saveexec_b32 s2, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s6, exec_lo, s2
s_cbranch_execz .LBB1_12
s_waitcnt vmcnt(0)
v_add3_u32 v1, v7, s8, -1
s_mov_b32 s11, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, s7, v1, v[3:4]
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
v_add3_u32 v3, v4, s3, -1
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, blur_kernel@rel32@lo+4
s_addc_u32 s3, s3, blur_kernel@rel32@hi+12
.p2align 6
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b64 s[8:9], 0
v_lshlrev_b64 v[4:5], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB1_9:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v4, s8
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v5, vcc_lo
s_add_u32 s12, s2, s8
s_addc_u32 s13, s3, s9
s_add_u32 s8, s8, 8
global_load_b64 v[7:8], v[7:8], off
s_load_b64 s[12:13], s[12:13], 0x0
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s8, 24
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fma_f64 v[1:2], v[7:8], s[12:13], v[1:2]
s_cbranch_scc0 .LBB1_9
s_add_i32 s11, s11, 1
v_add_nc_u32_e32 v3, s7, v3
s_add_u32 s2, s2, 24
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s11, 2
s_cbranch_scc0 .LBB1_8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v6, s7, v[0:1]
s_or_b32 s10, s10, exec_lo
v_ashrrev_i32_e32 v5, 31, v4
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s6
s_and_saveexec_b32 s2, s10
s_cbranch_execz .LBB1_14
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[3:4], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s0, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[1:2], off
.LBB1_14:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel blur_filter
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size blur_filter, .Lfunc_end1-blur_filter
.section .AMDGPU.csdata,"",@progbits
.text
.protected mix_channels
.globl mix_channels
.p2align 8
.type mix_channels,@function
mix_channels:
s_load_b32 s2, s[0:1], 0x18
v_lshl_or_b32 v0, s15, 10, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[2:3], v[2:3], off
v_add_co_u32 v6, vcc_lo, s2, v0
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s3, 0x3fd5c28f
s_mov_b32 s2, 0x5c28f5c3
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b64 v[6:7], v[6:7], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(2)
v_mul_f64 v[2:3], v[2:3], s[2:3]
s_mov_b32 s3, 0x3fd51eb8
s_mov_b32 s2, 0x51eb851f
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f64 v[2:3], v[4:5], s[2:3], v[2:3]
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[6:7], s[2:3], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mix_channels
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 40
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size mix_channels, .Lfunc_end2-mix_channels
.section .AMDGPU.csdata,"",@progbits
.text
.protected smoothen
.globl smoothen
.p2align 8
.type smoothen,@function
smoothen:
s_load_b64 s[4:5], s[0:1], 0x8
v_bfe_u32 v4, v0, 10, 10
v_and_b32_e32 v1, 0x3ff, v0
s_lshl_b32 s8, s15, 5
s_lshl_b32 s3, s14, 5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, s8, v4
v_add_nc_u32_e32 v0, s3, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v6
v_cmp_gt_i32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s6, s2
s_cbranch_execz .LBB3_11
s_load_b64 s[6:7], s[0:1], 0x0
s_add_i32 s2, s4, -1
s_mov_b32 s9, 0
v_cmp_le_i32_e64 s4, s2, v6
s_mov_b32 s10, exec_lo
v_cmpx_gt_i32_e64 s2, v6
v_min_i32_e32 v2, v6, v0
s_add_i32 s2, s5, -1
s_and_not1_b32 s4, s4, exec_lo
v_cmp_le_i32_e32 vcc_lo, s2, v0
s_mov_b32 s9, exec_lo
v_cmp_gt_i32_e64 s2, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s2, vcc_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s4, s2
s_or_b32 exec_lo, exec_lo, s10
s_and_saveexec_b32 s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB3_5
v_mad_u64_u32 v[2:3], null, v6, s5, v[0:1]
s_and_not1_b32 s9, s9, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
.LBB3_5:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s4, s9
s_cbranch_execz .LBB3_10
s_load_b64 s[10:11], s[0:1], 0x10
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[2:3], null, v6, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_getpc_b64 s[10:11]
s_add_u32 s10, s10, sharpen_kernel@rel32@lo+4
s_addc_u32 s11, s11, sharpen_kernel@rel32@hi+12
s_getpc_b64 s[12:13]
s_add_u32 s12, s12, blur_kernel@rel32@lo+4
s_addc_u32 s13, s13, blur_kernel@rel32@hi+12
v_mov_b32_e32 v7, s11
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_le_f64_e32 vcc_lo, 0x403e0000, v[2:3]
v_add3_u32 v2, v4, s8, -1
s_mov_b32 s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, s5, v2, v[1:2]
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v5, s10
v_mov_b32_e32 v3, 0
v_add3_u32 v4, v4, s3, -1
v_cndmask_b32_e32 v1, s13, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_cndmask_b32_e32 v7, s12, v5, vcc_lo
.p2align 6
.LBB3_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
s_mov_b64 s[2:3], 0
v_lshlrev_b64 v[8:9], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v9, vcc_lo
.LBB3_8:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v5, s2
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v11, vcc_lo, v7, s2
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v1, vcc_lo
s_add_u32 s2, s2, 8
global_load_b64 v[9:10], v[9:10], off
global_load_b64 v[11:12], v[11:12], off
s_addc_u32 s3, s3, 0
s_cmp_eq_u32 s2, 24
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[11:12], v[2:3]
s_cbranch_scc0 .LBB3_8
v_add_co_u32 v7, vcc_lo, v7, 24
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
v_add_nc_u32_e32 v4, s5, v4
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 2
s_cbranch_scc0 .LBB3_7
.LBB3_10:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_trunc_f64_e32 v[4:5], v[2:3]
s_load_b64 s[0:1], s[0:1], 0x18
v_add_f64 v[1:2], v[2:3], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f64_e64 s2, |v[1:2]|, 0.5
v_cndmask_b32_e64 v1, 0, 0x3ff00000, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_bfi_b32 v2, 0x7fffffff, v1, v3
v_mov_b32_e32 v1, 0
v_add_f64 v[1:2], v[4:5], v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_f64 v[1:2], v[1:2], 0x406fe000
v_max_f64 v[1:2], v[1:2], 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v3, v[1:2]
v_mad_u64_u32 v[1:2], null, v6, s5, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b8 v[0:1], v3, off
.LBB3_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel smoothen
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size smoothen, .Lfunc_end3-smoothen
.section .AMDGPU.csdata,"",@progbits
.text
.protected parallel_max
.globl parallel_max
.p2align 8
.type parallel_max,@function
parallel_max:
s_load_b32 s3, s[0:1], 0x8
s_mov_b32 s2, s15
v_mov_b32_e32 v1, 0
v_lshl_or_b32 v3, s2, 10, v0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s3, v3
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB4_2
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
.LBB4_2:
s_or_b32 exec_lo, exec_lo, s3
v_lshlrev_b32_e32 v3, 3, v0
s_mov_b32 s3, 1
s_waitcnt vmcnt(0)
ds_store_b64 v3, v[1:2]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_set_inst_prefetch_distance 0x1
s_branch .LBB4_4
.p2align 6
.LBB4_3:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s4, s3, 1
s_cmpk_lt_u32 s3, 0x200
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB4_6
.LBB4_4:
v_add_nc_u32_e32 v1, s3, v0
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x400, v1
s_cbranch_execz .LBB4_3
v_lshlrev_b32_e32 v1, 3, v1
ds_load_b64 v[1:2], v1
ds_load_b64 v[4:5], v3
s_waitcnt lgkmcnt(1)
v_max_f64 v[1:2], v[1:2], v[1:2]
s_waitcnt lgkmcnt(0)
v_max_f64 v[4:5], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1)
v_max_f64 v[1:2], v[4:5], v[1:2]
ds_store_b64 v3, v[1:2]
s_branch .LBB4_3
.LBB4_6:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 3
ds_load_b64 v[0:1], v2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel parallel_max
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size parallel_max, .Lfunc_end4-parallel_max
.section .AMDGPU.csdata,"",@progbits
.text
.protected divide_all
.globl divide_all
.p2align 8
.type divide_all,@function
divide_all:
s_load_b32 s2, s[0:1], 0x8
v_lshl_or_b32 v0, s15, 10, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB5_2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[2:3], 0x0
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s0, 0
s_mov_b32 s1, 0x406fe000
global_load_b64 v[6:7], v[0:1], off
s_waitcnt lgkmcnt(0)
v_div_scale_f64 v[2:3], null, s[2:3], s[2:3], 0x406fe000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[4:5], v[2:3]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[2:3], v[4:5], 1.0
v_fma_f64 v[4:5], v[4:5], v[8:9], v[4:5]
v_div_scale_f64 v[8:9], vcc_lo, s[0:1], s[2:3], s[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[4:5]
v_fma_f64 v[2:3], -v[2:3], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[10:11]
v_div_fixup_f64 v[2:3], v[2:3], s[2:3], 0x406fe000
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[6:7], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB5_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel divide_all
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end5:
.size divide_all, .Lfunc_end5-divide_all
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected sobely_kernel
.type sobely_kernel,@object
.data
.globl sobely_kernel
.p2align 4, 0x0
sobely_kernel:
.quad 0xbff0000000000000
.quad 0xc000000000000000
.quad 0xbff0000000000000
.zero 24
.quad 0x3ff0000000000000
.quad 0x4000000000000000
.quad 0x3ff0000000000000
.size sobely_kernel, 72
.protected sobelx_kernel
.type sobelx_kernel,@object
.globl sobelx_kernel
.p2align 4, 0x0
sobelx_kernel:
.quad 0xbff0000000000000
.quad 0x0000000000000000
.quad 0x3ff0000000000000
.quad 0xc000000000000000
.quad 0x0000000000000000
.quad 0x4000000000000000
.quad 0xbff0000000000000
.quad 0x0000000000000000
.quad 0x3ff0000000000000
.size sobelx_kernel, 72
.protected sharpen_kernel
.type sharpen_kernel,@object
.globl sharpen_kernel
.p2align 4, 0x0
sharpen_kernel:
.quad 0x0000000000000000
.quad 0xbff0000000000000
.quad 0x0000000000000000
.quad 0xbff0000000000000
.quad 0x4014000000000000
.quad 0xbff0000000000000
.quad 0x0000000000000000
.quad 0xbff0000000000000
.quad 0x0000000000000000
.size sharpen_kernel, 72
.protected blur_kernel
.type blur_kernel,@object
.globl blur_kernel
.p2align 4, 0x0
blur_kernel:
.quad 0x0000000000000000
.quad 0x3fc999999999999a
.quad 0x0000000000000000
.quad 0x3fc999999999999a
.quad 0x3fc999999999999a
.quad 0x3fc999999999999a
.quad 0x0000000000000000
.quad 0x3fc999999999999a
.quad 0x0000000000000000
.size blur_kernel, 72
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym sobely_kernel
.addrsig_sym sobelx_kernel
.addrsig_sym sharpen_kernel
.addrsig_sym blur_kernel
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: sobel_filter
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: sobel_filter.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: blur_filter
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: blur_filter.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 40
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mix_channels
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mix_channels.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: smoothen
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: smoothen.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: parallel_max
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: parallel_max.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: divide_all
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: divide_all.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
extern "C" {
__device__ double sobely_kernel[3][3] = {{-1, -2, -1}, {0, 0, 0}, {1, 2, 1}};
__device__ double sobelx_kernel[3][3] = {{-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}};
__device__ double sharpen_kernel[3][3] = {{0, -1, 0}, {-1, 5, -1}, {0, -1, 0}};
__device__ double blur_kernel[3][3] =
{{0, 0.2, 0}, {0.2, 0.2, 0.2}, {0, 0.2, 0}};
__device__
void simple_convolve(const double* channel,
int dimx,
const double kernel[3][3],
int y,
int x,
double * out) {
double result = 0;
for (int i = -1; i <= 1; ++i) {
for (int j = -1; j <= 1; ++j) {
result += channel[(y + i) * dimx + x + j] * kernel[i + 1][j + 1];
}
}
*out = result;
}
__global__
void sobel_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double sobely;
double sobelx;
simple_convolve(in_channel,
dimx,
sobely_kernel,
idy,
idx,
&sobely);
simple_convolve(in_channel,
dimx,
sobelx_kernel,
idy,
idx,
&sobelx);
out_channel[idy * dimx + idx] = sqrtf(sobely*sobely + sobelx*sobelx);
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = 0;
}
}
__global__
void blur_filter(const double* in_channel,
int dimy,
int dimx,
double* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
double result;
simple_convolve(in_channel,
dimx,
blur_kernel,
idy,
idx,
&result);
out_channel[idy * dimx + idx] = result;
} else if (idy < dimy && idx < dimx) {
out_channel[idy * dimx + idx] = in_channel[idy * dimx + idx];
}
}
__global__
void mix_channels(const double * rchannels,
const double * gchannels,
const double * bchannels,
int len,
double* out_channel) {
int id = blockIdx.x*1024 + threadIdx.x;
if (id < len) {
out_channel[id] = rchannels[id] * 0.33
+ gchannels[id] * 0.34
+ bchannels[id] * 0.33;
}
}
__global__
void smoothen(const double* in_channel,
int dimy,
int dimx,
const double* edge_channel,
unsigned char* out_channel) {
int idy = blockIdx.y*32 + threadIdx.y;
int idx = blockIdx.x*32 + threadIdx.x;
if (idy >= dimy || idx >= dimx) {
return;
}
double result = 0;
if (idy < dimy - 1 && idx < dimx - 1 && 0 < idy && 0 < idx) {
simple_convolve(in_channel,
dimx,
(edge_channel[idy * dimx + idx] >= 30 ? sharpen_kernel : blur_kernel),
idy,
idx,
&result);
} else {
result = in_channel[idy * dimx + idx];
}
out_channel[idy * dimx + idx] =
(unsigned char)max(0., min(255., round(result)));
}
__global__
void parallel_max(const double* in, int length, double* out) {
__shared__ double values[1024];
int i = 1;
int idx = blockIdx.x*1024 + threadIdx.x;
values[threadIdx.x] = idx < length ? in[idx] : 0;
__syncthreads();
while (i < 1024) {
if (threadIdx.x + i < 1024) {
values[threadIdx.x] = max(values[threadIdx.x], values[threadIdx.x + i]);
}
i *= 2;
__syncthreads();
}
out[blockIdx.x] = values[0];
}
__global__
void divide_all(double * array, int length, double* divider) { // remove *
int idx = blockIdx.x*1024 + threadIdx.x;
if (idx < length) {
array[idx] *= 255./(*divider);
}
}
} | .text
.file "filter-noise.hip"
.globl __device_stub__sobel_filter # -- Begin function __device_stub__sobel_filter
.p2align 4, 0x90
.type __device_stub__sobel_filter,@function
__device_stub__sobel_filter: # @__device_stub__sobel_filter
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $sobel_filter, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__sobel_filter, .Lfunc_end0-__device_stub__sobel_filter
.cfi_endproc
# -- End function
.globl __device_stub__blur_filter # -- Begin function __device_stub__blur_filter
.p2align 4, 0x90
.type __device_stub__blur_filter,@function
__device_stub__blur_filter: # @__device_stub__blur_filter
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $blur_filter, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__blur_filter, .Lfunc_end1-__device_stub__blur_filter
.cfi_endproc
# -- End function
.globl __device_stub__mix_channels # -- Begin function __device_stub__mix_channels
.p2align 4, 0x90
.type __device_stub__mix_channels,@function
__device_stub__mix_channels: # @__device_stub__mix_channels
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $mix_channels, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size __device_stub__mix_channels, .Lfunc_end2-__device_stub__mix_channels
.cfi_endproc
# -- End function
.globl __device_stub__smoothen # -- Begin function __device_stub__smoothen
.p2align 4, 0x90
.type __device_stub__smoothen,@function
__device_stub__smoothen: # @__device_stub__smoothen
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $smoothen, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__smoothen, .Lfunc_end3-__device_stub__smoothen
.cfi_endproc
# -- End function
.globl __device_stub__parallel_max # -- Begin function __device_stub__parallel_max
.p2align 4, 0x90
.type __device_stub__parallel_max,@function
__device_stub__parallel_max: # @__device_stub__parallel_max
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $parallel_max, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size __device_stub__parallel_max, .Lfunc_end4-__device_stub__parallel_max
.cfi_endproc
# -- End function
.globl __device_stub__divide_all # -- Begin function __device_stub__divide_all
.p2align 4, 0x90
.type __device_stub__divide_all,@function
__device_stub__divide_all: # @__device_stub__divide_all
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $divide_all, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size __device_stub__divide_all, .Lfunc_end5-__device_stub__divide_all
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sobel_filter, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blur_filter, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mix_channels, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $smoothen, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $parallel_max, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $divide_all, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sobely_kernel, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $72, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sobelx_kernel, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $72, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sharpen_kernel, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $72, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $blur_kernel, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $72, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type sobely_kernel,@object # @sobely_kernel
.local sobely_kernel
.comm sobely_kernel,72,16
.type sobelx_kernel,@object # @sobelx_kernel
.local sobelx_kernel
.comm sobelx_kernel,72,16
.type sharpen_kernel,@object # @sharpen_kernel
.local sharpen_kernel
.comm sharpen_kernel,72,16
.type blur_kernel,@object # @blur_kernel
.local blur_kernel
.comm blur_kernel,72,16
.type sobel_filter,@object # @sobel_filter
.section .rodata,"a",@progbits
.globl sobel_filter
.p2align 3, 0x0
sobel_filter:
.quad __device_stub__sobel_filter
.size sobel_filter, 8
.type blur_filter,@object # @blur_filter
.globl blur_filter
.p2align 3, 0x0
blur_filter:
.quad __device_stub__blur_filter
.size blur_filter, 8
.type mix_channels,@object # @mix_channels
.globl mix_channels
.p2align 3, 0x0
mix_channels:
.quad __device_stub__mix_channels
.size mix_channels, 8
.type smoothen,@object # @smoothen
.globl smoothen
.p2align 3, 0x0
smoothen:
.quad __device_stub__smoothen
.size smoothen, 8
.type parallel_max,@object # @parallel_max
.globl parallel_max
.p2align 3, 0x0
parallel_max:
.quad __device_stub__parallel_max
.size parallel_max, 8
.type divide_all,@object # @divide_all
.globl divide_all
.p2align 3, 0x0
divide_all:
.quad __device_stub__divide_all
.size divide_all, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sobel_filter"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "blur_filter"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mix_channels"
.size .L__unnamed_3, 13
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "smoothen"
.size .L__unnamed_4, 9
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "parallel_max"
.size .L__unnamed_5, 13
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "divide_all"
.size .L__unnamed_6, 11
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "sobely_kernel"
.size .L__unnamed_7, 14
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "sobelx_kernel"
.size .L__unnamed_8, 14
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "sharpen_kernel"
.size .L__unnamed_9, 15
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "blur_kernel"
.size .L__unnamed_10, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sobel_filter
.addrsig_sym __device_stub__blur_filter
.addrsig_sym __device_stub__mix_channels
.addrsig_sym __device_stub__smoothen
.addrsig_sym __device_stub__parallel_max
.addrsig_sym __device_stub__divide_all
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sobely_kernel
.addrsig_sym sobelx_kernel
.addrsig_sym sharpen_kernel
.addrsig_sym blur_kernel
.addrsig_sym sobel_filter
.addrsig_sym blur_filter
.addrsig_sym mix_channels
.addrsig_sym smoothen
.addrsig_sym parallel_max
.addrsig_sym divide_all
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d9d2e_00000000-6_filter-noise.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl simple_convolve
.type simple_convolve, @function
simple_convolve:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size simple_convolve, .-simple_convolve
.globl _Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd
.type _Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd, @function
_Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq sobel_filter(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd, .-_Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd
.globl sobel_filter
.type sobel_filter, @function
sobel_filter:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z12sobel_filterPKdiiPdPKdiiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size sobel_filter, .-sobel_filter
.globl _Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd
.type _Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd, @function
_Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd:
.LFB2054:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq blur_filter(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd, .-_Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd
.globl blur_filter
.type blur_filter, @function
blur_filter:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11blur_filterPKdiiPdPKdiiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size blur_filter, .-blur_filter
.globl _Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd
.type _Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd, @function
_Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd:
.LFB2056:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq mix_channels(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd, .-_Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd
.globl mix_channels
.type mix_channels, @function
mix_channels:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z12mix_channelsPKdS0_S0_iPdPKdS0_S0_iPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size mix_channels, .-mix_channels
.globl _Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph
.type _Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph, @function
_Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph:
.LFB2058:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq smoothen(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph, .-_Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph
.globl smoothen
.type smoothen, @function
smoothen:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8smoothenPKdiiS0_PhPKdiiS0_Ph
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size smoothen, .-smoothen
.globl _Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd
.type _Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd, @function
_Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd:
.LFB2060:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq parallel_max(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd, .-_Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd
.globl parallel_max
.type parallel_max, @function
parallel_max:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12parallel_maxPKdiPdPKdiPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size parallel_max, .-parallel_max
.globl _Z33__device_stub__Z10divide_allPdiS_PdiS_
.type _Z33__device_stub__Z10divide_allPdiS_PdiS_, @function
_Z33__device_stub__Z10divide_allPdiS_PdiS_:
.LFB2062:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L49
.L45:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L50
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq divide_all(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L45
.L50:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z33__device_stub__Z10divide_allPdiS_PdiS_, .-_Z33__device_stub__Z10divide_allPdiS_PdiS_
.globl divide_all
.type divide_all, @function
divide_all:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10divide_allPdiS_PdiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size divide_all, .-divide_all
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "divide_all"
.LC1:
.string "parallel_max"
.LC2:
.string "smoothen"
.LC3:
.string "mix_channels"
.LC4:
.string "blur_filter"
.LC5:
.string "sobel_filter"
.LC6:
.string "sobely_kernel"
.LC7:
.string "sobelx_kernel"
.LC8:
.string "sharpen_kernel"
.LC9:
.string "blur_kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq divide_all(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq parallel_max(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq smoothen(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq mix_channels(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq blur_filter(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq sobel_filter(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13sobely_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13sobelx_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL14sharpen_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL11blur_kernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL11blur_kernel
.comm _ZL11blur_kernel,72,32
.local _ZL14sharpen_kernel
.comm _ZL14sharpen_kernel,72,32
.local _ZL13sobelx_kernel
.comm _ZL13sobelx_kernel,72,32
.local _ZL13sobely_kernel
.comm _ZL13sobely_kernel,72,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "filter-noise.hip"
.globl __device_stub__sobel_filter # -- Begin function __device_stub__sobel_filter
.p2align 4, 0x90
.type __device_stub__sobel_filter,@function
__device_stub__sobel_filter: # @__device_stub__sobel_filter
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $sobel_filter, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__sobel_filter, .Lfunc_end0-__device_stub__sobel_filter
.cfi_endproc
# -- End function
.globl __device_stub__blur_filter # -- Begin function __device_stub__blur_filter
.p2align 4, 0x90
.type __device_stub__blur_filter,@function
__device_stub__blur_filter: # @__device_stub__blur_filter
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $blur_filter, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__blur_filter, .Lfunc_end1-__device_stub__blur_filter
.cfi_endproc
# -- End function
.globl __device_stub__mix_channels # -- Begin function __device_stub__mix_channels
.p2align 4, 0x90
.type __device_stub__mix_channels,@function
__device_stub__mix_channels: # @__device_stub__mix_channels
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movq %r8, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $mix_channels, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end2:
.size __device_stub__mix_channels, .Lfunc_end2-__device_stub__mix_channels
.cfi_endproc
# -- End function
.globl __device_stub__smoothen # -- Begin function __device_stub__smoothen
.p2align 4, 0x90
.type __device_stub__smoothen,@function
__device_stub__smoothen: # @__device_stub__smoothen
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $smoothen, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size __device_stub__smoothen, .Lfunc_end3-__device_stub__smoothen
.cfi_endproc
# -- End function
.globl __device_stub__parallel_max # -- Begin function __device_stub__parallel_max
.p2align 4, 0x90
.type __device_stub__parallel_max,@function
__device_stub__parallel_max: # @__device_stub__parallel_max
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $parallel_max, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size __device_stub__parallel_max, .Lfunc_end4-__device_stub__parallel_max
.cfi_endproc
# -- End function
.globl __device_stub__divide_all # -- Begin function __device_stub__divide_all
.p2align 4, 0x90
.type __device_stub__divide_all,@function
__device_stub__divide_all: # @__device_stub__divide_all
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $divide_all, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size __device_stub__divide_all, .Lfunc_end5-__device_stub__divide_all
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $sobel_filter, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $blur_filter, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mix_channels, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $smoothen, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $parallel_max, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $divide_all, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sobely_kernel, %esi
movl $.L__unnamed_7, %edx
movl $.L__unnamed_7, %ecx
movl $72, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sobelx_kernel, %esi
movl $.L__unnamed_8, %edx
movl $.L__unnamed_8, %ecx
movl $72, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $sharpen_kernel, %esi
movl $.L__unnamed_9, %edx
movl $.L__unnamed_9, %ecx
movl $72, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $blur_kernel, %esi
movl $.L__unnamed_10, %edx
movl $.L__unnamed_10, %ecx
movl $72, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type sobely_kernel,@object # @sobely_kernel
.local sobely_kernel
.comm sobely_kernel,72,16
.type sobelx_kernel,@object # @sobelx_kernel
.local sobelx_kernel
.comm sobelx_kernel,72,16
.type sharpen_kernel,@object # @sharpen_kernel
.local sharpen_kernel
.comm sharpen_kernel,72,16
.type blur_kernel,@object # @blur_kernel
.local blur_kernel
.comm blur_kernel,72,16
.type sobel_filter,@object # @sobel_filter
.section .rodata,"a",@progbits
.globl sobel_filter
.p2align 3, 0x0
sobel_filter:
.quad __device_stub__sobel_filter
.size sobel_filter, 8
.type blur_filter,@object # @blur_filter
.globl blur_filter
.p2align 3, 0x0
blur_filter:
.quad __device_stub__blur_filter
.size blur_filter, 8
.type mix_channels,@object # @mix_channels
.globl mix_channels
.p2align 3, 0x0
mix_channels:
.quad __device_stub__mix_channels
.size mix_channels, 8
.type smoothen,@object # @smoothen
.globl smoothen
.p2align 3, 0x0
smoothen:
.quad __device_stub__smoothen
.size smoothen, 8
.type parallel_max,@object # @parallel_max
.globl parallel_max
.p2align 3, 0x0
parallel_max:
.quad __device_stub__parallel_max
.size parallel_max, 8
.type divide_all,@object # @divide_all
.globl divide_all
.p2align 3, 0x0
divide_all:
.quad __device_stub__divide_all
.size divide_all, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "sobel_filter"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "blur_filter"
.size .L__unnamed_2, 12
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "mix_channels"
.size .L__unnamed_3, 13
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "smoothen"
.size .L__unnamed_4, 9
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "parallel_max"
.size .L__unnamed_5, 13
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "divide_all"
.size .L__unnamed_6, 11
.type .L__unnamed_7,@object # @6
.L__unnamed_7:
.asciz "sobely_kernel"
.size .L__unnamed_7, 14
.type .L__unnamed_8,@object # @7
.L__unnamed_8:
.asciz "sobelx_kernel"
.size .L__unnamed_8, 14
.type .L__unnamed_9,@object # @8
.L__unnamed_9:
.asciz "sharpen_kernel"
.size .L__unnamed_9, 15
.type .L__unnamed_10,@object # @9
.L__unnamed_10:
.asciz "blur_kernel"
.size .L__unnamed_10, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__sobel_filter
.addrsig_sym __device_stub__blur_filter
.addrsig_sym __device_stub__mix_channels
.addrsig_sym __device_stub__smoothen
.addrsig_sym __device_stub__parallel_max
.addrsig_sym __device_stub__divide_all
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym sobely_kernel
.addrsig_sym sobelx_kernel
.addrsig_sym sharpen_kernel
.addrsig_sym blur_kernel
.addrsig_sym sobel_filter
.addrsig_sym blur_filter
.addrsig_sym mix_channels
.addrsig_sym smoothen
.addrsig_sym parallel_max
.addrsig_sym divide_all
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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