system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Compute the sum of two vectors using CUDA
* Vishwas S
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int *a, int *b, int *c, int n)
{
int id = blockIdx.x*blockDim.x + threadIdx.x;
if(id<n)
c[id] = a[id] + b[id];
}
int main()
{
int N;
int *a, *b, *c, *da, *db, *dc;
scanf("... | .text
.file "13b.hip"
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu inst... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004a228_00000000-6_13b.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi... | .text
.file "13b.hip"
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x... | code for sm_80
Function : _Z4salePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ H... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x... | .file "tmpxft_0004f7b6_00000000-6_exe3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x... | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4salePiS_S_
.globl _Z4salePiS_S_
.p2align 8
.type _Z4salePiS_S_,@function
_Z4salePiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lg... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]... | .text
.file "exe3.hip"
.globl _Z19__device_stub__salePiS_S_ # -- Begin function _Z19__device_stub__salePiS_S_
.p2align 4, 0x90
.type _Z19__device_stub__salePiS_S_,@function
_Z19__device_stub__salePiS_S_: # @_Z19__device_stub__salePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rd... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4salePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ H... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4salePiS_S_
.globl _Z4salePiS_S_
.p2align 8
.type _Z4salePiS_S_,@function
_Z4salePiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lg... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004f7b6_00000000-6_exe3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "exe3.hip"
.globl _Z19__device_stub__salePiS_S_ # -- Begin function _Z19__device_stub__salePiS_S_
.p2align 4, 0x90
.type _Z19__device_stub__salePiS_S_,@function
_Z19__device_stub__salePiS_S_: # @_Z19__device_stub__salePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rd... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/sort.h>
#include <thrust/device_ptr.h>
#include <thrust/iterator/zip_iterator.h>
//---------------------------------------------------------------------------
// NVCC is not yet able to compile C++11 code.
// Hence the need to keep Thrust and VexCL code in separate files.
//----------------------------... | #include <hip/hip_runtime.h>
#include <thrust/sort.h>
#include <thrust/device_ptr.h>
#include <thrust/iterator/zip_iterator.h>
//---------------------------------------------------------------------------
// NVCC is not yet able to compile C++11 code.
// Hence the need to keep Thrust and VexCL code in separate files.
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (... | code for sm_80
Function : _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (... | .file "tmpxft_000809d3_00000000-6_Compute_weightx_weighty2_norm0_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregist... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.globl _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 8
.type _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@function
_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff:
s_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
... | .text
.file "Compute_weightx_weighty2_norm0_Kernel.hip"
.globl _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff # -- Begin function _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 4, 0x90
.type _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@fun... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.globl _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 8
.type _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@function
_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff:
s_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000809d3_00000000-6_Compute_weightx_weighty2_norm0_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregist... | .text
.file "Compute_weightx_weighty2_norm0_Kernel.hip"
.globl _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff # -- Begin function _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 4, 0x90
.type _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@fun... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * ... | code for sm_80
Function : _Z11relu_kernelPKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * ... | .file "tmpxft_000d91b0_00000000-6_relu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * ... | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11relu_kernelPKfPfi
.globl _Z11relu_kernelPKfPfi
.p2align 8
.type _Z11relu_kernelPKfPfi,@function
_Z11relu_kernelPKfPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n... | .text
.file "relu_kernel.hip"
.globl _Z26__device_stub__relu_kernelPKfPfi # -- Begin function _Z26__device_stub__relu_kernelPKfPfi
.p2align 4, 0x90
.type _Z26__device_stub__relu_kernelPKfPfi,@function
_Z26__device_stub__relu_kernelPKfPfi: # @_Z26__device_stub__relu_kernelPKfPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11relu_kernelPKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11relu_kernelPKfPfi
.globl _Z11relu_kernelPKfPfi
.p2align 8
.type _Z11relu_kernelPKfPfi,@function
_Z11relu_kernelPKfPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d91b0_00000000-6_relu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %... | .text
.file "relu_kernel.hip"
.globl _Z26__device_stub__relu_kernelPKfPfi # -- Begin function _Z26__device_stub__relu_kernelPKfPfi
.p2align 4, 0x90
.type _Z26__device_stub__relu_kernelPKfPfi,@function
_Z26__device_stub__relu_kernelPKfPfi: # @_Z26__device_stub__relu_kernelPKfPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General... | code for sm_80
Function : _Z5sobelPhS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General... | .file "tmpxft_001ba56a_00000000-6_sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General... | #include <hip/hip_runtime.h>
#include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sobelPhS_iiii
.globl _Z5sobelPhS_iiii
.p2align 8
.type _Z5sobelPhS_iiii,@function
_Z5sobelPhS_iiii:
s_load_b64 s[12:13], s[0:1], 0x4
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s8, 0
v_bfe_u32 v1, v0, 10, 10
s_mov_b32 s9, s8
s_mov_... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under... | .text
.file "sobel.hip"
.globl _Z20__device_stub__sobelPhS_iiii # -- Begin function _Z20__device_stub__sobelPhS_iiii
.p2align 4, 0x90
.type _Z20__device_stub__sobelPhS_iiii,@function
_Z20__device_stub__sobelPhS_iiii: # @_Z20__device_stub__sobelPhS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 1... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5sobelPhS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sobelPhS_iiii
.globl _Z5sobelPhS_iiii
.p2align 8
.type _Z5sobelPhS_iiii,@function
_Z5sobelPhS_iiii:
s_load_b64 s[12:13], s[0:1], 0x4
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s8, 0
v_bfe_u32 v1, v0, 10, 10
s_mov_b32 s9, s8
s_mov_... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ba56a_00000000-6_sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.c... | .text
.file "sobel.hip"
.globl _Z20__device_stub__sobelPhS_iiii # -- Begin function _Z20__device_stub__sobelPhS_iiii
.p2align 4, 0x90
.type _Z20__device_stub__sobelPhS_iiii,@function
_Z20__device_stub__sobelPhS_iiii: # @_Z20__device_stub__sobelPhS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 1... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int in... | code for sm_80
Function : _Z6tabfunPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int in... | .file "tmpxft_000eb418_00000000-6_tabfun.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int in... | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6tabfunPffi
.globl _Z6tabfunPffi
.p2align 8
.type _Z6tabfunPffi,@function
_Z6tabfunPffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu insti... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int... | .text
.file "tabfun.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11tabfun_hostPffi
.LCPI0_0:
.long 0x00000000 # float 0
.text
.globl _Z11tabfun_hostPffi
.p2align 4, 0x90
.type _Z11tabfun_hostPffi,@function
_Z11tabfun_hostPffi: ... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6tabfunPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6tabfunPffi
.globl _Z6tabfunPffi
.p2align 8
.type _Z6tabfunPffi,@function
_Z6tabfunPffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu insti... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eb418_00000000-6_tabfun.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.... | .text
.file "tabfun.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11tabfun_hostPffi
.LCPI0_0:
.long 0x00000000 # float 0
.text
.globl _Z11tabfun_hostPffi
.p2align 4, 0x90
.type _Z11tabfun_hostPffi,@function
_Z11tabfun_hostPffi: ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nb... | code for sm_80
Function : _Z6cal_piPfifii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e2800000... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nb... | .file "tmpxft_0017a6d1_00000000-6_ej10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nb... | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nt... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nt... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6cal_piPfifii
.globl _Z6cal_piPfifii
.p2align 8
.type _Z6cal_piPfifii,@function
_Z6cal_piPfifii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nt... | .text
.file "ej10.hip"
.globl _Z21__device_stub__cal_piPfifii # -- Begin function _Z21__device_stub__cal_piPfifii
.p2align 4, 0x90
.type _Z21__device_stub__cal_piPfifii,@function
_Z21__device_stub__cal_piPfifii: # @_Z21__device_stub__cal_piPfifii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
mo... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017a6d1_00000000-6_ej10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cf... | .text
.file "ej10.hip"
.globl _Z21__device_stub__cal_piPfifii # -- Begin function _Z21__device_stub__cal_piPfifii
.p2align 4, 0x90
.type _Z21__device_stub__cal_piPfifii,@function
_Z21__device_stub__cal_piPfifii: # @_Z21__device_stub__cal_piPfifii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
mo... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17)... | code for sm_80
Function : kern7
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, S... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17)... | .file "tmpxft_00094b9c_00000000-6_finalPut-hand-simplified.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@P... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17)... | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17)... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17)... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kern7
.globl kern7
.p2align 8
.type kern7,@function
kern7:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x1c
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17)... | .text
.file "finalPut-hand-simplified.hip"
.globl __device_stub__kern7 # -- Begin function __device_stub__kern7
.p2align 4, 0x90
.type __device_stub__kern7,@function
__device_stub__kern7: # @__device_stub__kern7
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : kern7
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, S... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kern7
.globl kern7
.p2align 8
.type kern7,@function
kern7:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x1c
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00094b9c_00000000-6_finalPut-hand-simplified.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@P... | .text
.file "finalPut-hand-simplified.hip"
.globl __device_stub__kern7 # -- Begin function __device_stub__kern7
.p2align 4, 0x90
.type __device_stub__kern7,@function
__device_stub__kern7: # @__device_stub__kern7
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k... | code for sm_80
Function : _Z16matrixMultKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k... | .file "tmpxft_0016401e_00000000-6_matrixMultKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k... | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixMultKernelPdS_S_i
.globl _Z16matrixMultKernelPdS_S_i
.p2align 8
.type _Z16matrixMultKernelPdS_S_i,@function
_Z16matrixMultKernelPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k ... | .text
.file "matrixMultKernel.hip"
.globl _Z31__device_stub__matrixMultKernelPdS_S_i # -- Begin function _Z31__device_stub__matrixMultKernelPdS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__matrixMultKernelPdS_S_i,@function
_Z31__device_stub__matrixMultKernelPdS_S_i: # @_Z31__device_stub__matrixMultKernelPdS_S_i
.cfi_s... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16matrixMultKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixMultKernelPdS_S_i
.globl _Z16matrixMultKernelPdS_S_i
.p2align 8
.type _Z16matrixMultKernelPdS_S_i,@function
_Z16matrixMultKernelPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016401e_00000000-6_matrixMultKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq ... | .text
.file "matrixMultKernel.hip"
.globl _Z31__device_stub__matrixMultKernelPdS_S_i # -- Begin function _Z31__device_stub__matrixMultKernelPdS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__matrixMultKernelPdS_S_i,@function
_Z31__device_stub__matrixMultKernelPdS_S_i: # @_Z31__device_stub__matrixMultKernelPdS_S_i
.cfi_s... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
... | .file "tmpxft_000baab2_00000000-6_roe_calculate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
... | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid =... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid =... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30multithreads_inverse_calculatePdS_diiiii
.globl _Z30multithreads_inverse_calculatePdS_diiiii
.p2align 8
.type _Z30multithreads_inverse_calculatePdS_diiiii,@function
_Z30multithreads_inverse_calculatePdS_diiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid =... | .text
.file "roe_calculate.hip"
.globl _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii # -- Begin function _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.p2align 4, 0x90
.type _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii,@function
_Z45__device_stub__multithreads_inverse_calculat... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000baab2_00000000-6_roe_calculate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8,... | .text
.file "roe_calculate.hip"
.globl _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii # -- Begin function _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.p2align 4, 0x90
.type _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii,@function
_Z45__device_stub__multithreads_inverse_calculat... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int... | code for sm_80
Function : _Z14tanhActivationiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int... | .file "tmpxft_000481e4_00000000-6_tanhActivation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int... | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * ... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14tanhActivationiiPf
.globl _Z14tanhActivationiiPf
.p2align 8
.type _Z14tanhActivationiiPf,@function
_Z14tanhActivationiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3,... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * ... | .text
.file "tanhActivation.hip"
.globl _Z29__device_stub__tanhActivationiiPf # -- Begin function _Z29__device_stub__tanhActivationiiPf
.p2align 4, 0x90
.type _Z29__device_stub__tanhActivationiiPf,@function
_Z29__device_stub__tanhActivationiiPf: # @_Z29__device_stub__tanhActivationiiPf
.cfi_startproc
# %bb.0:
subq $88... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14tanhActivationiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14tanhActivationiiPf
.globl _Z14tanhActivationiiPf
.p2align 8
.type _Z14tanhActivationiiPf,@function
_Z14tanhActivationiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3,... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000481e4_00000000-6_tanhActivation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8... | .text
.file "tanhActivation.hip"
.globl _Z29__device_stub__tanhActivationiiPf # -- Begin function _Z29__device_stub__tanhActivationiiPf
.p2align 4, 0x90
.type _Z29__device_stub__tanhActivationiiPf,@function
_Z29__device_stub__tanhActivationiiPf: # @_Z29__device_stub__tanhActivationiiPf
.cfi_startproc
# %bb.0:
subq $88... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
// Initialize memory
__global__ void init... | code for sm_80
Function : _Z5saxpyPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ ... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
// Initialize memory
__global__ void init... | .file "tmpxft_000d310c_00000000-6_04.challenge.saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
add... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
// Initialize memory
__global__ void init... | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
// Initialize mem... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
// Initialize mem... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11initVectorsPiS_S_
.globl _Z11initVectorsPiS_S_
.p2align 8
.type _Z11initVectorsPiS_S_,@function
_Z11initVectorsPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
// Initialize mem... | .text
.file "04.challenge.saxpy.hip"
.globl _Z26__device_stub__initVectorsPiS_S_ # -- Begin function _Z26__device_stub__initVectorsPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__initVectorsPiS_S_,@function
_Z26__device_stub__initVectorsPiS_S_: # @_Z26__device_stub__initVectorsPiS_S_
.cfi_startproc
# %bb.0:
subq $10... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ ... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11initVectorsPiS_S_
.globl _Z11initVectorsPiS_S_
.p2align 8
.type _Z11initVectorsPiS_S_,@function
_Z11initVectorsPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d310c_00000000-6_04.challenge.saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
add... | .text
.file "04.challenge.saxpy.hip"
.globl _Z26__device_stub__initVectorsPiS_S_ # -- Begin function _Z26__device_stub__initVectorsPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__initVectorsPiS_S_,@function
_Z26__device_stub__initVectorsPiS_S_: # @_Z26__device_stub__initVectorsPiS_S_
.cfi_startproc
# %bb.0:
subq $10... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
value... | code for sm_80
Function : _Z9radixSortPjiiPiS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x00... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
value... | .file "tmpxft_000fa904_00000000-6_Radix_Sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
value... | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
value... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
value... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9radixSortPjiiPiS0_S0_
.globl _Z9radixSortPjiiPiS0_S0_
.p2align 8
.type _Z9radixSortPjiiPiS0_S0_,@function
_Z9radixSortPjiiPiS0_S0_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x0
s_wa... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
value... | .text
.file "Radix_Sort.hip"
.globl _Z10printArrayPii # -- Begin function _Z10printArrayPii
.p2align 4, 0x90
.type _Z10printArrayPii,@function
_Z10printArrayPii: # @_Z10printArrayPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9radixSortPjiiPiS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x00... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9radixSortPjiiPiS0_S0_
.globl _Z9radixSortPjiiPiS0_S0_
.p2align 8
.type _Z9radixSortPjiiPiS0_S0_,@function
_Z9radixSortPjiiPiS0_S0_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x0
s_wa... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fa904_00000000-6_Radix_Sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "Radix_Sort.hip"
.globl _Z10printArrayPii # -- Begin function _Z10printArrayPii
.p2align 4, 0x90
.type _Z10printArrayPii,@function
_Z10printArrayPii: # @_Z10printArrayPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;... | code for sm_80
Function : _Z10OPT_4_HISTPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e2... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;... | .file "tmpxft_00199ceb_00000000-6_OPT_4_HIST.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int i... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int i... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10OPT_4_HISTPiS_S_i
.globl _Z10OPT_4_HISTPiS_S_i
.p2align 8
.type _Z10OPT_4_HISTPiS_S_i,@function
_Z10OPT_4_HISTPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int i... | .text
.file "OPT_4_HIST.hip"
.globl _Z25__device_stub__OPT_4_HISTPiS_S_i # -- Begin function _Z25__device_stub__OPT_4_HISTPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__OPT_4_HISTPiS_S_i,@function
_Z25__device_stub__OPT_4_HISTPiS_S_i: # @_Z25__device_stub__OPT_4_HISTPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10OPT_4_HISTPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e2... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10OPT_4_HISTPiS_S_i
.globl _Z10OPT_4_HISTPiS_S_i
.p2align 8
.type _Z10OPT_4_HISTPiS_S_i,@function
_Z10OPT_4_HISTPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00199ceb_00000000-6_OPT_4_HIST.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %r... | .text
.file "OPT_4_HIST.hip"
.globl _Z25__device_stub__OPT_4_HISTPiS_S_i # -- Begin function _Z25__device_stub__OPT_4_HISTPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__OPT_4_HISTPiS_S_i,@function
_Z25__device_stub__OPT_4_HISTPiS_S_i: # @_Z25__device_stub__OPT_4_HISTPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad ... | code for sm_80
Function : _Z18matrixAdd_C_KernelPfS_S_mi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad ... | .file "tmpxft_00006656_00000000-6_matrixAdd_C_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
add... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad ... | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < wi... |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < wi... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixAdd_C_KernelPfS_S_mi
.globl _Z18matrixAdd_C_KernelPfS_S_mi
.p2align 8
.type _Z18matrixAdd_C_KernelPfS_S_mi,@function
_Z18matrixAdd_C_KernelPfS_S_mi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
... |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < wi... | .text
.file "matrixAdd_C_Kernel.hip"
.globl _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi # -- Begin function _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.p2align 4, 0x90
.type _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi,@function
_Z33__device_stub__matrixAdd_C_KernelPfS_S_mi: # @_Z33__device_stub__matrixAdd_C_Kern... |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18matrixAdd_C_KernelPfS_S_mi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixAdd_C_KernelPfS_S_mi
.globl _Z18matrixAdd_C_KernelPfS_S_mi
.p2align 8
.type _Z18matrixAdd_C_KernelPfS_S_mi,@function
_Z18matrixAdd_C_KernelPfS_S_mi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
... |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00006656_00000000-6_matrixAdd_C_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
add... | .text
.file "matrixAdd_C_Kernel.hip"
.globl _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi # -- Begin function _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.p2align 4, 0x90
.type _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi,@function
_Z33__device_stub__matrixAdd_C_KernelPfS_S_mi: # @_Z33__device_stub__matrixAdd_C_Kern... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include "functions.cuh"
__global__
void KernelAdd(int n, float * p_sum, float * x, float * y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n )
p_sum[i] = x[i] + y[i];
}
void DeviceKernel(int numBlocks, int sizeBlock, int n, float * p_sum, float * x, float * y){
... | code for sm_80
Function : _Z9KernelAddiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*00... |
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