system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Compute the sum of two vectors using CUDA
* Vishwas S
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void add(int *a, int *b, int *c, int n)
{
int id = blockIdx.x*blockDim.x + threadIdx.x;
if(id<n)
c[id] = a[id] + b[id];
}
int main()
{
int N;
int *a, *b, *c, *da, *db, *dc;
scanf("%d",&N);
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
a = (int *)calloc(N,sizeof(int));
b = (int *)calloc(N,sizeof(int));
c = (int *)calloc(N,sizeof(int));
for(int i = 0; i < N; i++)
{
a[i] = rand()%48;
b[i] = rand()%50;
}
int size = N*sizeof(int);
hipMalloc(&da,size);
hipMalloc(&db,size);
hipMalloc(&dc,size);
hipMemcpy(da,a,size,hipMemcpyHostToDevice);
hipMemcpy(db,b,size,hipMemcpyHostToDevice);
hipEventRecord(start);
add<<<(N+511)/512,512>>>(da,db,dc,N); //block count, threads per block
hipEventRecord(stop);
hipMemcpy(c,dc,size,hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float ms;
hipEventElapsedTime(&ms,start,stop);
printf("%f\n",ms);
} | .text
.file "13b.hip"
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movslq 4(%rsp), %r14
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, %r12
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, %r15
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, %rbx
testq %r14, %r14
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $715827883, %rax, %rcx # imm = 0x2AAAAAAB
movq %rcx, %rdx
shrq $63, %rdx
shrq $35, %rcx
addl %edx, %ecx
shll $4, %ecx
leal (%rcx,%rcx,2), %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r13,4)
incq %r13
movslq 4(%rsp), %r14
cmpq %r14, %r13
jl .LBB1_2
.LBB1_3: # %._crit_edge
shll $2, %r14d
movslq %r14d, %r14
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 4(%rsp), %edi
leal 511(%rdi), %eax
addl $1022, %edi # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004a228_00000000-6_13b.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d"
.LC1:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC0(%rip), %rdi
call __isoc23_scanf@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl 4(%rsp), %r14d
movslq %r14d, %rbx
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %r12
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %rbp
movl $4, %esi
movq %rbx, %rdi
call calloc@PLT
movq %rax, %r13
testl %r14d, %r14d
jle .L12
movl $0, %ebx
.L13:
call rand@PLT
movslq %eax, %rdx
imulq $715827883, %rdx, %rdx
sarq $35, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,2), %edx
sall $4, %edx
subl %edx, %eax
movl %eax, (%r12,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $36, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $50, %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
movl 4(%rsp), %r14d
addq $1, %rbx
cmpl %ebx, %r14d
jg .L13
.L12:
sall $2, %r14d
movslq %r14d, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r14, %rdx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $512, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 4(%rsp), %edx
leal 1022(%rdx), %eax
addl $511, %edx
cmovns %edx, %eax
sarl $9, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl 4(%rsp), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "13b.hip"
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $160, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 4(%rsp), %rsi
movl $.L.str, %edi
xorl %eax, %eax
callq __isoc23_scanf
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movslq 4(%rsp), %r14
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, %r12
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, %r15
movl $4, %esi
movq %r14, %rdi
callq calloc
movq %rax, %rbx
testq %r14, %r14
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $715827883, %rax, %rcx # imm = 0x2AAAAAAB
movq %rcx, %rdx
shrq $63, %rdx
shrq $35, %rcx
addl %edx, %ecx
shll $4, %ecx
leal (%rcx,%rcx,2), %ecx
subl %ecx, %eax
movl %eax, (%r12,%r13,4)
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $36, %rcx
addl %edx, %ecx
imull $50, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r15,%r13,4)
incq %r13
movslq 4(%rsp), %r14
cmpq %r14, %r13
jl .LBB1_2
.LBB1_3: # %._crit_edge
shll $2, %r14d
movslq %r14d, %r14
leaq 48(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 40(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl 4(%rsp), %edi
leal 511(%rdi), %eax
addl $1022, %edi # imm = 0x3FE
testl %eax, %eax
cmovnsl %eax, %edi
sarl $9, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movl 4(%rsp), %esi
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %esi, 20(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 32(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $160, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f\n"
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x] = sum;
}
}
int main(void){
int days = 7;
int items = 4;
int arr[28] = {
3,5,2,0,
2,4,5,1,
0,3,3,1,
3,5,4,4,
4,5,5,3,
10,13,21,16,
8,11,15,8
};
float prices[4] = {29.99,14.99,9.99,24.99};
float out[7];
int *GPU_arr;
int *GPU_price;
int *GPU_out;
cudaMalloc((void**)&GPU_arr,sizeof(int)*28);
cudaMalloc((void**)&GPU_price,sizeof(float)*4);
cudaMalloc((void**)&GPU_out,sizeof(float)*7);
cudaMemcpy(GPU_arr,arr,sizeof(int)*28,cudaMemcpyHostToDevice);
cudaMemcpy(GPU_price,prices,sizeof(float)*4,cudaMemcpyHostToDevice);
sale<<<7,4>>>(GPU_arr,GPU_price,GPU_out);
cudaMemcpy(out,GPU_out,sizeof(float)*7,cudaMemcpyDeviceToHost);
//printf("%d",*c);
//printf("%d,%d,%d,%d\n",c[0],c[1],c[2],c[3]);
return 0;
} | code for sm_80
Function : _Z4salePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R4, R7, R9, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fc800078e0009 */
/*0070*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0209 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R4, R3, RZ ; /* 0x0000000304007224 */
/* 0x004fca00078e02ff */
/*00c0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ LDS.128 R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x001e220000000c00 */
/*0100*/ IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fe200078e0009 */
/*0110*/ IADD3 R0, R14, R13, R12 ; /* 0x0000000d0e007210 */
/* 0x001fc80007ffe00c */
/*0120*/ IADD3 R0, R0, R15, RZ ; /* 0x0000000f00007210 */
/* 0x000fcc0007ffe0ff */
/*0130*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e300000201400 */
/*0140*/ F2I.TRUNC.NTZ R5, R0 ; /* 0x0000000000057305 */
/* 0x001e24000020f100 */
/*0150*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x] = sum;
}
}
int main(void){
int days = 7;
int items = 4;
int arr[28] = {
3,5,2,0,
2,4,5,1,
0,3,3,1,
3,5,4,4,
4,5,5,3,
10,13,21,16,
8,11,15,8
};
float prices[4] = {29.99,14.99,9.99,24.99};
float out[7];
int *GPU_arr;
int *GPU_price;
int *GPU_out;
cudaMalloc((void**)&GPU_arr,sizeof(int)*28);
cudaMalloc((void**)&GPU_price,sizeof(float)*4);
cudaMalloc((void**)&GPU_out,sizeof(float)*7);
cudaMemcpy(GPU_arr,arr,sizeof(int)*28,cudaMemcpyHostToDevice);
cudaMemcpy(GPU_price,prices,sizeof(float)*4,cudaMemcpyHostToDevice);
sale<<<7,4>>>(GPU_arr,GPU_price,GPU_out);
cudaMemcpy(out,GPU_out,sizeof(float)*7,cudaMemcpyDeviceToHost);
//printf("%d",*c);
//printf("%d,%d,%d,%d\n",c[0],c[1],c[2],c[3]);
return 0;
} | .file "tmpxft_0004f7b6_00000000-6_exe3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4salePiS_S_PiS_S_
.type _Z27__device_stub__Z4salePiS_S_PiS_S_, @function
_Z27__device_stub__Z4salePiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4salePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z4salePiS_S_PiS_S_, .-_Z27__device_stub__Z4salePiS_S_PiS_S_
.globl _Z4salePiS_S_
.type _Z4salePiS_S_, @function
_Z4salePiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4salePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4salePiS_S_, .-_Z4salePiS_S_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl $3, 96(%rsp)
movl $5, 100(%rsp)
movl $2, 104(%rsp)
movl $0, 108(%rsp)
movl $2, 112(%rsp)
movl $4, 116(%rsp)
movl $5, 120(%rsp)
movl $1, 124(%rsp)
movl $0, 128(%rsp)
movl $3, 132(%rsp)
movl $3, 136(%rsp)
movl $1, 140(%rsp)
movl $3, 144(%rsp)
movl $5, 148(%rsp)
movl $4, 152(%rsp)
movl $4, 156(%rsp)
movl $4, 160(%rsp)
movl $5, 164(%rsp)
movl $5, 168(%rsp)
movl $3, 172(%rsp)
movl $10, 176(%rsp)
movl $13, 180(%rsp)
movl $21, 184(%rsp)
movl $16, 188(%rsp)
movl $8, 192(%rsp)
movl $11, 196(%rsp)
movl $15, 200(%rsp)
movl $8, 204(%rsp)
movl $0x41efeb85, 48(%rsp)
movl $0x416fd70a, 52(%rsp)
movl $0x411fd70a, 56(%rsp)
movl $0x41c7eb85, 60(%rsp)
movq %rsp, %rdi
movl $112, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $112, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $7, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $28, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z4salePiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z4salePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4salePiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x] = sum;
}
}
int main(void){
int days = 7;
int items = 4;
int arr[28] = {
3,5,2,0,
2,4,5,1,
0,3,3,1,
3,5,4,4,
4,5,5,3,
10,13,21,16,
8,11,15,8
};
float prices[4] = {29.99,14.99,9.99,24.99};
float out[7];
int *GPU_arr;
int *GPU_price;
int *GPU_out;
cudaMalloc((void**)&GPU_arr,sizeof(int)*28);
cudaMalloc((void**)&GPU_price,sizeof(float)*4);
cudaMalloc((void**)&GPU_out,sizeof(float)*7);
cudaMemcpy(GPU_arr,arr,sizeof(int)*28,cudaMemcpyHostToDevice);
cudaMemcpy(GPU_price,prices,sizeof(float)*4,cudaMemcpyHostToDevice);
sale<<<7,4>>>(GPU_arr,GPU_price,GPU_out);
cudaMemcpy(out,GPU_out,sizeof(float)*7,cudaMemcpyDeviceToHost);
//printf("%d",*c);
//printf("%d,%d,%d,%d\n",c[0],c[1],c[2],c[3]);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x] = sum;
}
}
int main(void){
int days = 7;
int items = 4;
int arr[28] = {
3,5,2,0,
2,4,5,1,
0,3,3,1,
3,5,4,4,
4,5,5,3,
10,13,21,16,
8,11,15,8
};
float prices[4] = {29.99,14.99,9.99,24.99};
float out[7];
int *GPU_arr;
int *GPU_price;
int *GPU_out;
hipMalloc((void**)&GPU_arr,sizeof(int)*28);
hipMalloc((void**)&GPU_price,sizeof(float)*4);
hipMalloc((void**)&GPU_out,sizeof(float)*7);
hipMemcpy(GPU_arr,arr,sizeof(int)*28,hipMemcpyHostToDevice);
hipMemcpy(GPU_price,prices,sizeof(float)*4,hipMemcpyHostToDevice);
sale<<<7,4>>>(GPU_arr,GPU_price,GPU_out);
hipMemcpy(out,GPU_out,sizeof(float)*7,hipMemcpyDeviceToHost);
//printf("%d",*c);
//printf("%d,%d,%d,%d\n",c[0],c[1],c[2],c[3]);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x] = sum;
}
}
int main(void){
int days = 7;
int items = 4;
int arr[28] = {
3,5,2,0,
2,4,5,1,
0,3,3,1,
3,5,4,4,
4,5,5,3,
10,13,21,16,
8,11,15,8
};
float prices[4] = {29.99,14.99,9.99,24.99};
float out[7];
int *GPU_arr;
int *GPU_price;
int *GPU_out;
hipMalloc((void**)&GPU_arr,sizeof(int)*28);
hipMalloc((void**)&GPU_price,sizeof(float)*4);
hipMalloc((void**)&GPU_out,sizeof(float)*7);
hipMemcpy(GPU_arr,arr,sizeof(int)*28,hipMemcpyHostToDevice);
hipMemcpy(GPU_price,prices,sizeof(float)*4,hipMemcpyHostToDevice);
sale<<<7,4>>>(GPU_arr,GPU_price,GPU_out);
hipMemcpy(out,GPU_out,sizeof(float)*7,hipMemcpyDeviceToHost);
//printf("%d",*c);
//printf("%d,%d,%d,%d\n",c[0],c[1],c[2],c[3]);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4salePiS_S_
.globl _Z4salePiS_S_
.p2align 8
.type _Z4salePiS_S_,@function
_Z4salePiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v4, v3, s[6:7]
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v4, v1
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_2addr_b32 v[0:1], v4 offset1:1
ds_load_2addr_b32 v[2:3], v4 offset0:2 offset1:3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
v_cvt_i32_f32_e32 v0, v0
global_store_b32 v4, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4salePiS_S_
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4salePiS_S_, .Lfunc_end0-_Z4salePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4salePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4salePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void sale(int *GPU_arr, int *GPU_price,int *GPU_out){
int i = blockIdx.x*blockDim.x + threadIdx.x;
__shared__ int temp[4];
temp[threadIdx.x] = GPU_arr[i] * GPU_price[threadIdx.x];
__syncthreads();
if(threadIdx.x==0){
float sum = 0;
sum = temp[0]+temp[1]+temp[2]+temp[3];
GPU_out[blockIdx.x] = sum;
}
}
int main(void){
int days = 7;
int items = 4;
int arr[28] = {
3,5,2,0,
2,4,5,1,
0,3,3,1,
3,5,4,4,
4,5,5,3,
10,13,21,16,
8,11,15,8
};
float prices[4] = {29.99,14.99,9.99,24.99};
float out[7];
int *GPU_arr;
int *GPU_price;
int *GPU_out;
hipMalloc((void**)&GPU_arr,sizeof(int)*28);
hipMalloc((void**)&GPU_price,sizeof(float)*4);
hipMalloc((void**)&GPU_out,sizeof(float)*7);
hipMemcpy(GPU_arr,arr,sizeof(int)*28,hipMemcpyHostToDevice);
hipMemcpy(GPU_price,prices,sizeof(float)*4,hipMemcpyHostToDevice);
sale<<<7,4>>>(GPU_arr,GPU_price,GPU_out);
hipMemcpy(out,GPU_out,sizeof(float)*7,hipMemcpyDeviceToHost);
//printf("%d",*c);
//printf("%d,%d,%d,%d\n",c[0],c[1],c[2],c[3]);
return 0;
} | .text
.file "exe3.hip"
.globl _Z19__device_stub__salePiS_S_ # -- Begin function _Z19__device_stub__salePiS_S_
.p2align 4, 0x90
.type _Z19__device_stub__salePiS_S_,@function
_Z19__device_stub__salePiS_S_: # @_Z19__device_stub__salePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4salePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__salePiS_S_, .Lfunc_end0-_Z19__device_stub__salePiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41efeb85 # float 29.9899998
.long 0x416fd70a # float 14.9899998
.long 0x411fd70a # float 9.98999977
.long 0x41c7eb85 # float 24.9899998
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movaps .L__const.main.arr+96(%rip), %xmm0
movaps %xmm0, 240(%rsp)
movaps .L__const.main.arr+80(%rip), %xmm0
movaps %xmm0, 224(%rsp)
movaps .L__const.main.arr+64(%rip), %xmm0
movaps %xmm0, 208(%rsp)
movaps .L__const.main.arr+48(%rip), %xmm0
movaps %xmm0, 192(%rsp)
movaps .L__const.main.arr+32(%rip), %xmm0
movaps %xmm0, 176(%rsp)
movaps .L__const.main.arr+16(%rip), %xmm0
movaps %xmm0, 160(%rsp)
movaps .L__const.main.arr(%rip), %xmm0
movaps %xmm0, 144(%rsp)
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [2.99899998E+1,1.49899998E+1,9.98999977E+0,2.49899998E+1]
movaps %xmm0, 128(%rsp)
leaq 16(%rsp), %rdi
movl $112, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rsp, %rdi
movl $28, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $112, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 3(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4salePiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $28, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4salePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4salePiS_S_,@object # @_Z4salePiS_S_
.section .rodata,"a",@progbits
.globl _Z4salePiS_S_
.p2align 3, 0x0
_Z4salePiS_S_:
.quad _Z19__device_stub__salePiS_S_
.size _Z4salePiS_S_, 8
.type .L__const.main.arr,@object # @__const.main.arr
.p2align 4, 0x0
.L__const.main.arr:
.long 3 # 0x3
.long 5 # 0x5
.long 2 # 0x2
.long 0 # 0x0
.long 2 # 0x2
.long 4 # 0x4
.long 5 # 0x5
.long 1 # 0x1
.long 0 # 0x0
.long 3 # 0x3
.long 3 # 0x3
.long 1 # 0x1
.long 3 # 0x3
.long 5 # 0x5
.long 4 # 0x4
.long 4 # 0x4
.long 4 # 0x4
.long 5 # 0x5
.long 5 # 0x5
.long 3 # 0x3
.long 10 # 0xa
.long 13 # 0xd
.long 21 # 0x15
.long 16 # 0x10
.long 8 # 0x8
.long 11 # 0xb
.long 15 # 0xf
.long 8 # 0x8
.size .L__const.main.arr, 112
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4salePiS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__salePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4salePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4salePiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R6, c[0x0][0x0], R7 ; /* 0x0000000006027a24 */
/* 0x001fca00078e0207 */
/*0060*/ IMAD.WIDE.U32 R4, R7, R9, c[0x0][0x168] ; /* 0x00005a0007047625 */
/* 0x000fc800078e0009 */
/*0070*/ IMAD.WIDE R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0209 */
/*0080*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R4, R3, RZ ; /* 0x0000000304007224 */
/* 0x004fca00078e02ff */
/*00c0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ LDS.128 R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x001e220000000c00 */
/*0100*/ IMAD.WIDE.U32 R2, R6, R9, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x000fe200078e0009 */
/*0110*/ IADD3 R0, R14, R13, R12 ; /* 0x0000000d0e007210 */
/* 0x001fc80007ffe00c */
/*0120*/ IADD3 R0, R0, R15, RZ ; /* 0x0000000f00007210 */
/* 0x000fcc0007ffe0ff */
/*0130*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e300000201400 */
/*0140*/ F2I.TRUNC.NTZ R5, R0 ; /* 0x0000000000057305 */
/* 0x001e24000020f100 */
/*0150*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4salePiS_S_
.globl _Z4salePiS_S_
.p2align 8
.type _Z4salePiS_S_,@function
_Z4salePiS_S_:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s2, s15
v_lshlrev_b32_e32 v3, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
s_mov_b32 s3, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_mov_b32 s4, exec_lo
global_load_b32 v4, v3, s[6:7]
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v1, v4, v1
ds_store_b32 v3, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v4, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_lshl_b64 s[2:3], s[2:3], 2
ds_load_2addr_b32 v[0:1], v4 offset1:1
ds_load_2addr_b32 v[2:3], v4 offset0:2 offset1:3
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
v_add_nc_u32_e32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_add_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v0
v_cvt_i32_f32_e32 v0, v0
global_store_b32 v4, v0, s[0:1]
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4salePiS_S_
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4salePiS_S_, .Lfunc_end0-_Z4salePiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4salePiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4salePiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004f7b6_00000000-6_exe3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z4salePiS_S_PiS_S_
.type _Z27__device_stub__Z4salePiS_S_PiS_S_, @function
_Z27__device_stub__Z4salePiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4salePiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z4salePiS_S_PiS_S_, .-_Z27__device_stub__Z4salePiS_S_PiS_S_
.globl _Z4salePiS_S_
.type _Z4salePiS_S_, @function
_Z4salePiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z4salePiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4salePiS_S_, .-_Z4salePiS_S_
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 216(%rsp)
xorl %eax, %eax
movl $3, 96(%rsp)
movl $5, 100(%rsp)
movl $2, 104(%rsp)
movl $0, 108(%rsp)
movl $2, 112(%rsp)
movl $4, 116(%rsp)
movl $5, 120(%rsp)
movl $1, 124(%rsp)
movl $0, 128(%rsp)
movl $3, 132(%rsp)
movl $3, 136(%rsp)
movl $1, 140(%rsp)
movl $3, 144(%rsp)
movl $5, 148(%rsp)
movl $4, 152(%rsp)
movl $4, 156(%rsp)
movl $4, 160(%rsp)
movl $5, 164(%rsp)
movl $5, 168(%rsp)
movl $3, 172(%rsp)
movl $10, 176(%rsp)
movl $13, 180(%rsp)
movl $21, 184(%rsp)
movl $16, 188(%rsp)
movl $8, 192(%rsp)
movl $11, 196(%rsp)
movl $15, 200(%rsp)
movl $8, 204(%rsp)
movl $0x41efeb85, 48(%rsp)
movl $0x416fd70a, 52(%rsp)
movl $0x411fd70a, 56(%rsp)
movl $0x41c7eb85, 60(%rsp)
movq %rsp, %rdi
movl $112, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
leaq 96(%rsp), %rsi
movl $1, %ecx
movl $112, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $16, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 36(%rsp)
movl $1, 40(%rsp)
movl $7, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $28, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movq 216(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $232, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z27__device_stub__Z4salePiS_S_PiS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "_Z4salePiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z4salePiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exe3.hip"
.globl _Z19__device_stub__salePiS_S_ # -- Begin function _Z19__device_stub__salePiS_S_
.p2align 4, 0x90
.type _Z19__device_stub__salePiS_S_,@function
_Z19__device_stub__salePiS_S_: # @_Z19__device_stub__salePiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4salePiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__salePiS_S_, .Lfunc_end0-_Z19__device_stub__salePiS_S_
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x41efeb85 # float 29.9899998
.long 0x416fd70a # float 14.9899998
.long 0x411fd70a # float 9.98999977
.long 0x41c7eb85 # float 24.9899998
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 272
movaps .L__const.main.arr+96(%rip), %xmm0
movaps %xmm0, 240(%rsp)
movaps .L__const.main.arr+80(%rip), %xmm0
movaps %xmm0, 224(%rsp)
movaps .L__const.main.arr+64(%rip), %xmm0
movaps %xmm0, 208(%rsp)
movaps .L__const.main.arr+48(%rip), %xmm0
movaps %xmm0, 192(%rsp)
movaps .L__const.main.arr+32(%rip), %xmm0
movaps %xmm0, 176(%rsp)
movaps .L__const.main.arr+16(%rip), %xmm0
movaps %xmm0, 160(%rsp)
movaps .L__const.main.arr(%rip), %xmm0
movaps %xmm0, 144(%rsp)
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [2.99899998E+1,1.49899998E+1,9.98999977E+0,2.49899998E+1]
movaps %xmm0, 128(%rsp)
leaq 16(%rsp), %rdi
movl $112, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
movq %rsp, %rdi
movl $28, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $112, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $16, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdx # imm = 0x100000004
leaq 3(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4salePiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $28, %edx
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4salePiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4salePiS_S_,@object # @_Z4salePiS_S_
.section .rodata,"a",@progbits
.globl _Z4salePiS_S_
.p2align 3, 0x0
_Z4salePiS_S_:
.quad _Z19__device_stub__salePiS_S_
.size _Z4salePiS_S_, 8
.type .L__const.main.arr,@object # @__const.main.arr
.p2align 4, 0x0
.L__const.main.arr:
.long 3 # 0x3
.long 5 # 0x5
.long 2 # 0x2
.long 0 # 0x0
.long 2 # 0x2
.long 4 # 0x4
.long 5 # 0x5
.long 1 # 0x1
.long 0 # 0x0
.long 3 # 0x3
.long 3 # 0x3
.long 1 # 0x1
.long 3 # 0x3
.long 5 # 0x5
.long 4 # 0x4
.long 4 # 0x4
.long 4 # 0x4
.long 5 # 0x5
.long 5 # 0x5
.long 3 # 0x3
.long 10 # 0xa
.long 13 # 0xd
.long 21 # 0x15
.long 16 # 0x10
.long 8 # 0x8
.long 11 # 0xb
.long 15 # 0xf
.long 8 # 0x8
.size .L__const.main.arr, 112
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4salePiS_S_"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__salePiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4salePiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/sort.h>
#include <thrust/device_ptr.h>
#include <thrust/iterator/zip_iterator.h>
//---------------------------------------------------------------------------
// NVCC is not yet able to compile C++11 code.
// Hence the need to keep Thrust and VexCL code in separate files.
//---------------------------------------------------------------------------
template <typename Key, typename Val>
void thrust_sort_by_key(Key *key_begin, Key *key_end, Val *val_begin) {
thrust::sort_by_key(
thrust::device_pointer_cast(key_begin),
thrust::device_pointer_cast(key_end),
thrust::device_pointer_cast(val_begin)
);
}
template <typename Key, typename Val>
Val* thrust_reduce_by_key(
const Key *key_begin, const Key *key_end, const Val *val_begin,
Key *key_output, Val *val_output
)
{
thrust::pair< thrust::device_ptr<Key>, thrust::device_ptr<Val> >
end = thrust::reduce_by_key(
thrust::device_pointer_cast(key_begin),
thrust::device_pointer_cast(key_end),
thrust::device_pointer_cast(val_begin),
thrust::device_pointer_cast(key_output),
thrust::device_pointer_cast(val_output)
);
return thrust::raw_pointer_cast(end.second);
}
//---------------------------------------------------------------------------
// Same thing, for a pair of keys
//---------------------------------------------------------------------------
template <typename Key1, typename Key2, typename Val>
void thrust_sort_by_key(
Key1 *key1_begin, Key1 *key1_end, Key2 *key2_begin, Val *val_begin)
{
thrust::sort_by_key(
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_begin),
thrust::device_pointer_cast(key2_begin)
)
),
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_end),
thrust::device_pointer_cast(key2_begin + (key1_end - key1_begin))
)
),
thrust::device_pointer_cast(val_begin)
);
}
template <typename Key1, typename Key2, typename Val>
Val* thrust_reduce_by_key(
const Key1 *key1_begin, const Key1 *key1_end, const Key2 *key2_begin,
const Val *val_begin,
Key1 *key1_output, Key2 *key2_output, Val *val_output
)
{
thrust::pair<
thrust::zip_iterator<
thrust::tuple<
thrust::device_ptr<Key1>,
thrust::device_ptr<Key2>
>
>,
thrust::device_ptr<Val>
> end = thrust::reduce_by_key(
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_begin),
thrust::device_pointer_cast(key2_begin)
)
),
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_end),
thrust::device_pointer_cast(key2_begin + (key1_end - key1_begin))
)
),
thrust::device_pointer_cast(val_begin),
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_output),
thrust::device_pointer_cast(key2_output)
)
),
thrust::device_pointer_cast(val_output)
);
return thrust::raw_pointer_cast(end.second);
}
//---------------------------------------------------------------------------
// Due to the code separation we also need to explicitly instantiate the
// necessary templates.
//---------------------------------------------------------------------------
#define VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY(K, V) \
template void thrust_sort_by_key<K, V>( \
K * key_begin, K * key_end, V * val_begin)
VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY(int, double);
#undef VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY
#define VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY(K, V) \
template V * thrust_reduce_by_key<K, V>( \
const K * key_begin, const K * key_end, const V * val_begin, \
K * key_output, V * val_output)
VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY(int, double);
#undef VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY
#define VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY2(K1, K2, V) \
template void thrust_sort_by_key<K1, K2, V>( \
K1 * key1_begin, K1 * key1_end, K2 * key2_begin, V * val_begin)
VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY2(int, int, double);
#undef VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY2
#define VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY2(K1, K2, V) \
template V *thrust_reduce_by_key<K1, K2, V>( \
const K1 * key1_begin, const K1 * key1_end, const K2 * key2_begin, \
const V * val_begin, K1 * key1_output, K2 * key2_output, V * val_output)
VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY2(int, int, double);
#undef VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY2 | #include <hip/hip_runtime.h>
#include <thrust/sort.h>
#include <thrust/device_ptr.h>
#include <thrust/iterator/zip_iterator.h>
//---------------------------------------------------------------------------
// NVCC is not yet able to compile C++11 code.
// Hence the need to keep Thrust and VexCL code in separate files.
//---------------------------------------------------------------------------
template <typename Key, typename Val>
void thrust_sort_by_key(Key *key_begin, Key *key_end, Val *val_begin) {
thrust::sort_by_key(
thrust::device_pointer_cast(key_begin),
thrust::device_pointer_cast(key_end),
thrust::device_pointer_cast(val_begin)
);
}
template <typename Key, typename Val>
Val* thrust_reduce_by_key(
const Key *key_begin, const Key *key_end, const Val *val_begin,
Key *key_output, Val *val_output
)
{
thrust::pair< thrust::device_ptr<Key>, thrust::device_ptr<Val> >
end = thrust::reduce_by_key(
thrust::device_pointer_cast(key_begin),
thrust::device_pointer_cast(key_end),
thrust::device_pointer_cast(val_begin),
thrust::device_pointer_cast(key_output),
thrust::device_pointer_cast(val_output)
);
return thrust::raw_pointer_cast(end.second);
}
//---------------------------------------------------------------------------
// Same thing, for a pair of keys
//---------------------------------------------------------------------------
template <typename Key1, typename Key2, typename Val>
void thrust_sort_by_key(
Key1 *key1_begin, Key1 *key1_end, Key2 *key2_begin, Val *val_begin)
{
thrust::sort_by_key(
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_begin),
thrust::device_pointer_cast(key2_begin)
)
),
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_end),
thrust::device_pointer_cast(key2_begin + (key1_end - key1_begin))
)
),
thrust::device_pointer_cast(val_begin)
);
}
template <typename Key1, typename Key2, typename Val>
Val* thrust_reduce_by_key(
const Key1 *key1_begin, const Key1 *key1_end, const Key2 *key2_begin,
const Val *val_begin,
Key1 *key1_output, Key2 *key2_output, Val *val_output
)
{
thrust::pair<
thrust::zip_iterator<
thrust::tuple<
thrust::device_ptr<Key1>,
thrust::device_ptr<Key2>
>
>,
thrust::device_ptr<Val>
> end = thrust::reduce_by_key(
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_begin),
thrust::device_pointer_cast(key2_begin)
)
),
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_end),
thrust::device_pointer_cast(key2_begin + (key1_end - key1_begin))
)
),
thrust::device_pointer_cast(val_begin),
thrust::make_zip_iterator(
thrust::make_tuple(
thrust::device_pointer_cast(key1_output),
thrust::device_pointer_cast(key2_output)
)
),
thrust::device_pointer_cast(val_output)
);
return thrust::raw_pointer_cast(end.second);
}
//---------------------------------------------------------------------------
// Due to the code separation we also need to explicitly instantiate the
// necessary templates.
//---------------------------------------------------------------------------
#define VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY(K, V) \
template void thrust_sort_by_key<K, V>( \
K * key_begin, K * key_end, V * val_begin)
VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY(int, double);
#undef VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY
#define VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY(K, V) \
template V * thrust_reduce_by_key<K, V>( \
const K * key_begin, const K * key_end, const V * val_begin, \
K * key_output, V * val_output)
VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY(int, double);
#undef VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY
#define VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY2(K1, K2, V) \
template void thrust_sort_by_key<K1, K2, V>( \
K1 * key1_begin, K1 * key1_end, K2 * key2_begin, V * val_begin)
VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY2(int, int, double);
#undef VEXCL_INSTANTIATE_THRUST_SORT_BY_KEY2
#define VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY2(K1, K2, V) \
template V *thrust_reduce_by_key<K1, K2, V>( \
const K1 * key1_begin, const K1 * key1_end, const K2 * key2_begin, \
const V * val_begin, K1 * key1_output, K2 * key2_output, V * val_output)
VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY2(int, int, double);
#undef VEXCL_INSTANTIATE_THRUST_REDUCE_BY_KEY2 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (absIx[x] * absIx[x] + eps);
weighty[x] = 1.0f / (absIy[x] * absIy[x] + eps);
} | code for sm_80
Function : _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B0, 0x1a0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00b0*/ FFMA R4, R2, R2, c[0x0][0x188] ; /* 0x0000620002047623 */
/* 0x004fca0000000002 */
/*00c0*/ IADD3 R5, R4, 0x1800000, RZ ; /* 0x0180000004057810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000005057812 */
/* 0x000fc800078ec0ff */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R5, 0x1ffffff, PT ; /* 0x01ffffff0500780c */
/* 0x000fda0003f04070 */
/*00f0*/ @P0 BRA 0x150 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0110*/ MOV R2, 0x130 ; /* 0x0000013000027802 */
/* 0x000fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0x320 ; /* 0x000001f000007944 */
/* 0x000fea0003c00000 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*0140*/ BRA 0x190 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0150*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x000e240000001000 */
/*0160*/ FFMA R2, R4, R7, -1 ; /* 0xbf80000004027423 */
/* 0x001fc80000000007 */
/*0170*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */
/* 0x000fc80000010100 */
/*0180*/ FFMA R7, R7, R2, R7 ; /* 0x0000000207077223 */
/* 0x000fe40000000007 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*01c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*01d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003ea000c101904 */
/*01e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ BSSY B0, 0x2e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0200*/ FFMA R6, R4, R4, c[0x0][0x188] ; /* 0x0000620004067623 */
/* 0x004fca0000000004 */
/*0210*/ IADD3 R8, R6, 0x1800000, RZ ; /* 0x0180000006087810 */
/* 0x001fc80007ffe0ff */
/*0220*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000008087812 */
/* 0x000fc800078ec0ff */
/*0230*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ffffff, PT ; /* 0x01ffffff0800780c */
/* 0x000fda0003f04070 */
/*0240*/ @P0 BRA 0x290 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0250*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x002fe40000000f00 */
/*0260*/ MOV R2, 0x280 ; /* 0x0000028000027802 */
/* 0x000fe40000000f00 */
/*0270*/ CALL.REL.NOINC 0x320 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0280*/ BRA 0x2d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0290*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x002e240000001000 */
/*02a0*/ FFMA R2, R6, R5, -1 ; /* 0xbf80000006027423 */
/* 0x001fc80000000005 */
/*02b0*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */
/* 0x000fc80000010100 */
/*02c0*/ FFMA R5, R5, R2, R5 ; /* 0x0000000205057223 */
/* 0x000fe40000000005 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ IMAD.SHL.U32 R3, R8, 0x2, RZ ; /* 0x0000000208037824 */
/* 0x000fe200078e00ff */
/*0330*/ BSSY B1, 0x640 ; /* 0x0000030000017945 */
/* 0x000fe80003800000 */
/*0340*/ SHF.R.U32.HI R9, RZ, 0x18, R3 ; /* 0x00000018ff097819 */
/* 0x000fc80000011603 */
/*0350*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05070 */
/*0360*/ @P0 BRA 0x410 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.SHL.U32 R3, R8, 0x2, RZ ; /* 0x0000000208037824 */
/* 0x000fca00078e00ff */
/*0380*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0390*/ @P0 FFMA R4, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008040823 */
/* 0x000fe200000000ff */
/*03a0*/ @!P0 MUFU.RCP R3, R8 ; /* 0x0000000800038308 */
/* 0x000ff00000001000 */
/*03b0*/ @P0 MUFU.RCP R5, R4 ; /* 0x0000000400050308 */
/* 0x000e240000001000 */
/*03c0*/ @P0 FFMA R6, R4, R5, -1 ; /* 0xbf80000004060423 */
/* 0x001fc80000000005 */
/*03d0*/ @P0 FADD.FTZ R6, -R6, -RZ ; /* 0x800000ff06060221 */
/* 0x000fc80000010100 */
/*03e0*/ @P0 FFMA R6, R5, R6, R5 ; /* 0x0000000605060223 */
/* 0x000fc80000000005 */
/*03f0*/ @P0 FFMA R3, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006030823 */
/* 0x000fe200000000ff */
/*0400*/ BRA 0x630 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R10, R9, -0xfd, RZ ; /* 0xffffff03090a7810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GT.U32.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f04070 */
/*0430*/ @P0 BRA 0x620 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT R3, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08037812 */
/* 0x000fe200078ec0ff */
/*0450*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff077435 */
/* 0x000fc600000001ff */
/*0460*/ LOP3.LUT R3, R3, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000003037812 */
/* 0x000fc800078efcff */
/*0470*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x000e260000001000 */
/*0480*/ SHF.L.U32 R7, R7, R10, RZ ; /* 0x0000000a07077219 */
/* 0x000fe200000006ff */
/*0490*/ FFMA R5, R3, R4, -1 ; /* 0xbf80000003057423 */
/* 0x001fc80000000004 */
/*04a0*/ FADD.FTZ R5, -R5, -RZ ; /* 0x800000ff05057221 */
/* 0x000fc80000010100 */
/*04b0*/ FFMA.RM R6, R4.reuse, R5.reuse, R4.reuse ; /* 0x0000000504067223 */
/* 0x1c0fe40000004004 */
/*04c0*/ FFMA.RP R5, R4, R5, R4 ; /* 0x0000000504057223 */
/* 0x000fc60000008004 */
/*04d0*/ LOP3.LUT R4, R6.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06047812 */
/* 0x040fe400078ec0ff */
/*04e0*/ FSETP.NEU.FTZ.AND P0, PT, R6, R5, PT ; /* 0x000000050600720b */
/* 0x000fe40003f1d000 */
/*04f0*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fe400078efcff */
/*0500*/ SEL R5, RZ, 0xffffffff, !P0 ; /* 0xffffffffff057807 */
/* 0x000fe40004000000 */
/*0510*/ LOP3.LUT R7, R7, R4, RZ, 0xc0, !PT ; /* 0x0000000407077212 */
/* 0x000fc600078ec0ff */
/*0520*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a05 */
/*0530*/ SHF.R.U32.HI R7, RZ, R10, R7 ; /* 0x0000000aff077219 */
/* 0x000fc80000011607 */
/*0540*/ LOP3.LUT P1, RZ, R5, R10, R4, 0xf8, !PT ; /* 0x0000000a05ff7212 */
/* 0x000fe4000782f804 */
/*0550*/ LOP3.LUT P0, RZ, R7.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107ff7812 */
/* 0x040fe4000780c0ff */
/*0560*/ LOP3.LUT P2, RZ, R7, 0x2, RZ, 0xc0, !PT ; /* 0x0000000207ff7812 */
/* 0x000fc8000784c0ff */
/*0570*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0580*/ LOP3.LUT P1, RZ, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08ff7812 */
/* 0x000fe4000782c0ff */
/*0590*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fca0004000000 */
/*05a0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0a03 */
/*05b0*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f06270 */
/*05c0*/ IADD3 R3, R9, -0xfc, RZ ; /* 0xffffff0409037810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fce0000011604 */
/*05e0*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fca0007ffe0ff */
/*05f0*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */
/* 0x000fca00078e00ff */
/*0600*/ LOP3.LUT R3, R3, 0x80000000, R8, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef808 */
/*0610*/ BRA 0x630 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0620*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x0000640000001000 */
/*0630*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0640*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x002fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0660*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff99002007950 */
/* 0x000fea0003c3ffff */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (absIx[x] * absIx[x] + eps);
weighty[x] = 1.0f / (absIy[x] * absIy[x] + eps);
} | .file "tmpxft_000809d3_00000000-6_Compute_weightx_weighty2_norm0_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff
.type _Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff, @function
_Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff, .-_Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff
.globl _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.type _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, @function
_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, .-_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (absIx[x] * absIx[x] + eps);
weighty[x] = 1.0f / (absIy[x] * absIy[x] + eps);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (absIx[x] * absIx[x] + eps);
weighty[x] = 1.0f / (absIy[x] * absIy[x] + eps);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (absIx[x] * absIx[x] + eps);
weighty[x] = 1.0f / (absIy[x] * absIy[x] + eps);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.globl _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 8
.type _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@function
_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f32 v4, v2, v2, s0
v_div_scale_f32 v2, null, v4, v4, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v2, v3, 1.0
v_fmac_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v3
v_fma_f32 v7, -v2, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v3
v_fma_f32 v2, -v2, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v5, v2, v3, v5
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_div_fixup_f32 v6, v5, v4, 1.0
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, v2, v2, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v2, v2, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v2, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v2, v3, v2, 1.0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, .Lfunc_end0-_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_weightx_weighty2_norm0_Kernel(float* weightx, float* weighty, const float* absIx, const float* absIy, int nPixels, float norm_for_smooth_term, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;
int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;
weightx[x] = 1.0f / (absIx[x] * absIx[x] + eps);
weighty[x] = 1.0f / (absIy[x] * absIy[x] + eps);
} | .text
.file "Compute_weightx_weighty2_norm0_Kernel.hip"
.globl _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff # -- Begin function _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 4, 0x90
.type _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@function
_Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff: # @_Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, .Lfunc_end0-_Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@object # @_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.section .rodata,"a",@progbits
.globl _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 3, 0x0
_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff:
.quad _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.size _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ BSSY B0, 0x1a0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00b0*/ FFMA R4, R2, R2, c[0x0][0x188] ; /* 0x0000620002047623 */
/* 0x004fca0000000002 */
/*00c0*/ IADD3 R5, R4, 0x1800000, RZ ; /* 0x0180000004057810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ LOP3.LUT R5, R5, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000005057812 */
/* 0x000fc800078ec0ff */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R5, 0x1ffffff, PT ; /* 0x01ffffff0500780c */
/* 0x000fda0003f04070 */
/*00f0*/ @P0 BRA 0x150 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0110*/ MOV R2, 0x130 ; /* 0x0000013000027802 */
/* 0x000fe40000000f00 */
/*0120*/ CALL.REL.NOINC 0x320 ; /* 0x000001f000007944 */
/* 0x000fea0003c00000 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*0140*/ BRA 0x190 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0150*/ MUFU.RCP R7, R4 ; /* 0x0000000400077308 */
/* 0x000e240000001000 */
/*0160*/ FFMA R2, R4, R7, -1 ; /* 0xbf80000004027423 */
/* 0x001fc80000000007 */
/*0170*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */
/* 0x000fc80000010100 */
/*0180*/ FFMA R7, R7, R2, R7 ; /* 0x0000000207077223 */
/* 0x000fe40000000007 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*01b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0205 */
/*01c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x178] ; /* 0x00005e0000047625 */
/* 0x000fe200078e0205 */
/*01d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003ea000c101904 */
/*01e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ BSSY B0, 0x2e0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0200*/ FFMA R6, R4, R4, c[0x0][0x188] ; /* 0x0000620004067623 */
/* 0x004fca0000000004 */
/*0210*/ IADD3 R8, R6, 0x1800000, RZ ; /* 0x0180000006087810 */
/* 0x001fc80007ffe0ff */
/*0220*/ LOP3.LUT R8, R8, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000008087812 */
/* 0x000fc800078ec0ff */
/*0230*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ffffff, PT ; /* 0x01ffffff0800780c */
/* 0x000fda0003f04070 */
/*0240*/ @P0 BRA 0x290 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0250*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x002fe40000000f00 */
/*0260*/ MOV R2, 0x280 ; /* 0x0000028000027802 */
/* 0x000fe40000000f00 */
/*0270*/ CALL.REL.NOINC 0x320 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0280*/ BRA 0x2d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0290*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x002e240000001000 */
/*02a0*/ FFMA R2, R6, R5, -1 ; /* 0xbf80000006027423 */
/* 0x001fc80000000005 */
/*02b0*/ FADD.FTZ R2, -R2, -RZ ; /* 0x800000ff02027221 */
/* 0x000fc80000010100 */
/*02c0*/ FFMA R5, R5, R2, R5 ; /* 0x0000000205057223 */
/* 0x000fe40000000005 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*02f0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0300*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ IMAD.SHL.U32 R3, R8, 0x2, RZ ; /* 0x0000000208037824 */
/* 0x000fe200078e00ff */
/*0330*/ BSSY B1, 0x640 ; /* 0x0000030000017945 */
/* 0x000fe80003800000 */
/*0340*/ SHF.R.U32.HI R9, RZ, 0x18, R3 ; /* 0x00000018ff097819 */
/* 0x000fc80000011603 */
/*0350*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05070 */
/*0360*/ @P0 BRA 0x410 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0370*/ IMAD.SHL.U32 R3, R8, 0x2, RZ ; /* 0x0000000208037824 */
/* 0x000fca00078e00ff */
/*0380*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0390*/ @P0 FFMA R4, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008040823 */
/* 0x000fe200000000ff */
/*03a0*/ @!P0 MUFU.RCP R3, R8 ; /* 0x0000000800038308 */
/* 0x000ff00000001000 */
/*03b0*/ @P0 MUFU.RCP R5, R4 ; /* 0x0000000400050308 */
/* 0x000e240000001000 */
/*03c0*/ @P0 FFMA R6, R4, R5, -1 ; /* 0xbf80000004060423 */
/* 0x001fc80000000005 */
/*03d0*/ @P0 FADD.FTZ R6, -R6, -RZ ; /* 0x800000ff06060221 */
/* 0x000fc80000010100 */
/*03e0*/ @P0 FFMA R6, R5, R6, R5 ; /* 0x0000000605060223 */
/* 0x000fc80000000005 */
/*03f0*/ @P0 FFMA R3, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006030823 */
/* 0x000fe200000000ff */
/*0400*/ BRA 0x630 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0410*/ IADD3 R10, R9, -0xfd, RZ ; /* 0xffffff03090a7810 */
/* 0x000fc80007ffe0ff */
/*0420*/ ISETP.GT.U32.AND P0, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fda0003f04070 */
/*0430*/ @P0 BRA 0x620 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0440*/ LOP3.LUT R3, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08037812 */
/* 0x000fe200078ec0ff */
/*0450*/ HFMA2.MMA R7, -RZ, RZ, 0, 1.78813934326171875e-07 ; /* 0x00000003ff077435 */
/* 0x000fc600000001ff */
/*0460*/ LOP3.LUT R3, R3, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000003037812 */
/* 0x000fc800078efcff */
/*0470*/ MUFU.RCP R4, R3 ; /* 0x0000000300047308 */
/* 0x000e260000001000 */
/*0480*/ SHF.L.U32 R7, R7, R10, RZ ; /* 0x0000000a07077219 */
/* 0x000fe200000006ff */
/*0490*/ FFMA R5, R3, R4, -1 ; /* 0xbf80000003057423 */
/* 0x001fc80000000004 */
/*04a0*/ FADD.FTZ R5, -R5, -RZ ; /* 0x800000ff05057221 */
/* 0x000fc80000010100 */
/*04b0*/ FFMA.RM R6, R4.reuse, R5.reuse, R4.reuse ; /* 0x0000000504067223 */
/* 0x1c0fe40000004004 */
/*04c0*/ FFMA.RP R5, R4, R5, R4 ; /* 0x0000000504057223 */
/* 0x000fc60000008004 */
/*04d0*/ LOP3.LUT R4, R6.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff06047812 */
/* 0x040fe400078ec0ff */
/*04e0*/ FSETP.NEU.FTZ.AND P0, PT, R6, R5, PT ; /* 0x000000050600720b */
/* 0x000fe40003f1d000 */
/*04f0*/ LOP3.LUT R4, R4, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000004047812 */
/* 0x000fe400078efcff */
/*0500*/ SEL R5, RZ, 0xffffffff, !P0 ; /* 0xffffffffff057807 */
/* 0x000fe40004000000 */
/*0510*/ LOP3.LUT R7, R7, R4, RZ, 0xc0, !PT ; /* 0x0000000407077212 */
/* 0x000fc600078ec0ff */
/*0520*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a05 */
/*0530*/ SHF.R.U32.HI R7, RZ, R10, R7 ; /* 0x0000000aff077219 */
/* 0x000fc80000011607 */
/*0540*/ LOP3.LUT P1, RZ, R5, R10, R4, 0xf8, !PT ; /* 0x0000000a05ff7212 */
/* 0x000fe4000782f804 */
/*0550*/ LOP3.LUT P0, RZ, R7.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107ff7812 */
/* 0x040fe4000780c0ff */
/*0560*/ LOP3.LUT P2, RZ, R7, 0x2, RZ, 0xc0, !PT ; /* 0x0000000207ff7812 */
/* 0x000fc8000784c0ff */
/*0570*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*0580*/ LOP3.LUT P1, RZ, R8, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08ff7812 */
/* 0x000fe4000782c0ff */
/*0590*/ SEL R3, RZ, 0x1, !P0 ; /* 0x00000001ff037807 */
/* 0x000fca0004000000 */
/*05a0*/ IMAD.MOV R3, RZ, RZ, -R3 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0a03 */
/*05b0*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f06270 */
/*05c0*/ IADD3 R3, R9, -0xfc, RZ ; /* 0xffffff0409037810 */
/* 0x000fc80007ffe0ff */
/*05d0*/ SHF.R.U32.HI R3, RZ, R3, R4 ; /* 0x00000003ff037219 */
/* 0x000fce0000011604 */
/*05e0*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fca0007ffe0ff */
/*05f0*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */
/* 0x000fca00078e00ff */
/*0600*/ LOP3.LUT R3, R3, 0x80000000, R8, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef808 */
/*0610*/ BRA 0x630 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0620*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x0000640000001000 */
/*0630*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0640*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x002fe20000000f00 */
/*0650*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0660*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff99002007950 */
/* 0x000fea0003c3ffff */
/*0670*/ BRA 0x670; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.globl _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 8
.type _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@function
_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[4:11], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f32 v4, v2, v2, s0
v_div_scale_f32 v2, null, v4, v4, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v2, v3, 1.0
v_fmac_f32_e32 v3, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v3
v_fma_f32 v7, -v2, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v3
v_fma_f32 v2, -v2, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v5, v2, v3, v5
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_div_fixup_f32 v6, v5, v4, 1.0
v_add_co_u32 v4, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v1, vcc_lo
global_store_b32 v[2:3], v6, off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_fma_f32 v2, v2, v2, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v3, null, v2, v2, 1.0
v_div_scale_f32 v6, vcc_lo, 1.0, v2, 1.0
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v2, v3, v2, 1.0
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, .Lfunc_end0-_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000809d3_00000000-6_Compute_weightx_weighty2_norm0_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff
.type _Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff, @function
_Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff, .-_Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff
.globl _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.type _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, @function
_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z68__device_stub__Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iffPfS_PKfS1_iff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, .-_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Compute_weightx_weighty2_norm0_Kernel.hip"
.globl _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff # -- Begin function _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 4, 0x90
.type _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@function
_Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff: # @_Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, .Lfunc_end0-_Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff,@object # @_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.section .rodata,"a",@progbits
.globl _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.p2align 3, 0x0
_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff:
.quad _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.size _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z52__device_stub__Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z37Compute_weightx_weighty2_norm0_KernelPfS_PKfS1_iff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
float element = input[index];
if (element <= 0) {
output[index] = 0;
} else {
output[index] = element;
}
}
} | code for sm_80
Function : _Z11relu_kernelPKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ FSETP.GTU.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x004fda0003f0c000 */
/*00c0*/ @!P0 STG.E [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e2000c101904 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
float element = input[index];
if (element <= 0) {
output[index] = 0;
} else {
output[index] = element;
}
}
} | .file "tmpxft_000d91b0_00000000-6_relu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi
.type _Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi, @function
_Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11relu_kernelPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi, .-_Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi
.globl _Z11relu_kernelPKfPfi
.type _Z11relu_kernelPKfPfi, @function
_Z11relu_kernelPKfPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11relu_kernelPKfPfi, .-_Z11relu_kernelPKfPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11relu_kernelPKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11relu_kernelPKfPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
float element = input[index];
if (element <= 0) {
output[index] = 0;
} else {
output[index] = element;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
float element = input[index];
if (element <= 0) {
output[index] = 0;
} else {
output[index] = element;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
float element = input[index];
if (element <= 0) {
output[index] = 0;
} else {
output[index] = element;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11relu_kernelPKfPfi
.globl _Z11relu_kernelPKfPfi
.p2align 8
.type _Z11relu_kernelPKfPfi,@function
_Z11relu_kernelPKfPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_nge_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11relu_kernelPKfPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11relu_kernelPKfPfi, .Lfunc_end0-_Z11relu_kernelPKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11relu_kernelPKfPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11relu_kernelPKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* TODO: Your code here */
/* all your GPU kernel code, e.g. matrix_softmax_cross_entropy_kernel */
// y = inputs[0], y_ = inputs[1]
// np.mean(-np.sum(y_ * np.log(softmax(y)), axis=1), keepdims=True)
__global__ void relu_kernel(const float *input, float *output, int n) {
int index = blockDim.x * blockIdx.x + threadIdx.x;
if (index < n) {
float element = input[index];
if (element <= 0) {
output[index] = 0;
} else {
output[index] = element;
}
}
} | .text
.file "relu_kernel.hip"
.globl _Z26__device_stub__relu_kernelPKfPfi # -- Begin function _Z26__device_stub__relu_kernelPKfPfi
.p2align 4, 0x90
.type _Z26__device_stub__relu_kernelPKfPfi,@function
_Z26__device_stub__relu_kernelPKfPfi: # @_Z26__device_stub__relu_kernelPKfPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11relu_kernelPKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__relu_kernelPKfPfi, .Lfunc_end0-_Z26__device_stub__relu_kernelPKfPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11relu_kernelPKfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11relu_kernelPKfPfi,@object # @_Z11relu_kernelPKfPfi
.section .rodata,"a",@progbits
.globl _Z11relu_kernelPKfPfi
.p2align 3, 0x0
_Z11relu_kernelPKfPfi:
.quad _Z26__device_stub__relu_kernelPKfPfi
.size _Z11relu_kernelPKfPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11relu_kernelPKfPfi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__relu_kernelPKfPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11relu_kernelPKfPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11relu_kernelPKfPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0205 */
/*00b0*/ FSETP.GTU.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x004fda0003f0c000 */
/*00c0*/ @!P0 STG.E [R4.64], RZ ; /* 0x000000ff04008986 */
/* 0x0001e2000c101904 */
/*00d0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00e0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11relu_kernelPKfPfi
.globl _Z11relu_kernelPKfPfi
.p2align 8
.type _Z11relu_kernelPKfPfi,@function
_Z11relu_kernelPKfPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_nge_f32_e32 vcc_lo, 0, v2
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11relu_kernelPKfPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11relu_kernelPKfPfi, .Lfunc_end0-_Z11relu_kernelPKfPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11relu_kernelPKfPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11relu_kernelPKfPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d91b0_00000000-6_relu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi
.type _Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi, @function
_Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11relu_kernelPKfPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi, .-_Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi
.globl _Z11relu_kernelPKfPfi
.type _Z11relu_kernelPKfPfi, @function
_Z11relu_kernelPKfPfi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11relu_kernelPKfPfiPKfPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11relu_kernelPKfPfi, .-_Z11relu_kernelPKfPfi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11relu_kernelPKfPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11relu_kernelPKfPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "relu_kernel.hip"
.globl _Z26__device_stub__relu_kernelPKfPfi # -- Begin function _Z26__device_stub__relu_kernelPKfPfi
.p2align 4, 0x90
.type _Z26__device_stub__relu_kernelPKfPfi,@function
_Z26__device_stub__relu_kernelPKfPfi: # @_Z26__device_stub__relu_kernelPKfPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11relu_kernelPKfPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__relu_kernelPKfPfi, .Lfunc_end0-_Z26__device_stub__relu_kernelPKfPfi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11relu_kernelPKfPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11relu_kernelPKfPfi,@object # @_Z11relu_kernelPKfPfi
.section .rodata,"a",@progbits
.globl _Z11relu_kernelPKfPfi
.p2align 3, 0x0
_Z11relu_kernelPKfPfi:
.quad _Z26__device_stub__relu_kernelPKfPfi
.size _Z11relu_kernelPKfPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11relu_kernelPKfPfi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__relu_kernelPKfPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11relu_kernelPKfPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.*/
typedef enum color {BLUE, GREEN, RED} Color; //Constants that contains the values for each color of the image
/*The gray function obtain an average of each pixel and assigned to the correct position in the array using
Channels and step constants*/
/*The sobel function uses a convolution algorithm to obtain the edges of the image */
__global__ void sobel(unsigned char *src, unsigned char *dest, int width, int heigth, int step, int channels){
int i, j;
int ren, col, tmp_ren, tmp_col;
int gx[3][3]={{-1,0,1},{-2,0,2},{-1,0,1}}; // gx is defined in the Sobel algorithm
int gy[3][3]={{1,2,1},{0,0,0},{-1,-2,-1}}; // gy is defined in the Sobel algorithm
char temp[3][3];
ren = blockIdx.x;
col = threadIdx.x;
tmp_ren = 0;
tmp_col = 0;
//Multiplication of the 3x3 matrix for each color
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + RED + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + RED] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + GREEN + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + GREEN] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + BLUE + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + BLUE] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);
} | code for sm_80
Function : _Z5sobelPhS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ IMAD R0, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000007a24 */
/* 0x001fc800078e02ff */
/*0050*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x002fca00078e0200 */
/*0060*/ IADD3 R3, R0, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x000fc80007ffe0ff */
/*0070*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0080*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*0090*/ LDG.E.S8 R4, [R2.64+0x3] ; /* 0x0000030402047981 */
/* 0x000ea8000c1e1300 */
/*00a0*/ LDG.E.S8 R5, [R2.64+0x5] ; /* 0x0000050402057981 */
/* 0x000ea2000c1e1300 */
/*00b0*/ BSSY B0, 0x1f0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*00c0*/ LEA R4, R4, -R5, 0x2 ; /* 0x8000000504047211 */
/* 0x004fca00078e10ff */
/*00d0*/ IMAD R4, R5, -0x2, R4 ; /* 0xfffffffe05047824 */
/* 0x000fca00078e0204 */
/*00e0*/ IADD3 R4, -R5, R4, RZ ; /* 0x0000000405047210 */
/* 0x000fca0007ffe1ff */
/*00f0*/ IMAD R4, R4, R4, RZ ; /* 0x0000000404047224 */
/* 0x000fcc00078e02ff */
/*0100*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e240000201400 */
/*0110*/ IADD3 R6, R4, -0xd000000, RZ ; /* 0xf300000004067810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*0130*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0140*/ @!P0 BRA 0x1a0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b7224 */
/* 0x003fe400078e0004 */
/*0160*/ MOV R12, 0x180 ; /* 0x00000180000c7802 */
/* 0x000fca0000000f00 */
/*0170*/ CALL.REL.NOINC 0x540 ; /* 0x000003c000007944 */
/* 0x000fea0003c00000 */
/*0180*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe20000000f00 */
/*0190*/ BRA 0x1e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01a0*/ FMUL.FTZ R7, R4, R5 ; /* 0x0000000504077220 */
/* 0x003fe40000410000 */
/*01b0*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*01c0*/ FFMA R4, -R7, R7, R4 ; /* 0x0000000707047223 */
/* 0x000fc80000000104 */
/*01d0*/ FFMA R6, R4, R5, R7 ; /* 0x0000000504067223 */
/* 0x000fe40000000007 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ F2I.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000e22000020f000 */
/*0200*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0210*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f0eff */
/*0220*/ STG.E.U8 [R4.64+0x2], R7 ; /* 0x0000020704007986 */
/* 0x0011e8000c101104 */
/*0230*/ LDG.E.S8 R0, [R2.64+0x2] ; /* 0x0000020402007981 */
/* 0x000ea8000c1e1300 */
/*0240*/ LDG.E.S8 R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea2000c1e1300 */
/*0250*/ BSSY B0, 0x390 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0260*/ LEA R0, R0, -R9, 0x2 ; /* 0x8000000900007211 */
/* 0x004fca00078e10ff */
/*0270*/ IMAD R0, R9, -0x2, R0 ; /* 0xfffffffe09007824 */
/* 0x000fca00078e0200 */
/*0280*/ IADD3 R0, -R9, R0, RZ ; /* 0x0000000009007210 */
/* 0x000fca0007ffe1ff */
/*0290*/ IMAD R0, R0, R0, RZ ; /* 0x0000000000007224 */
/* 0x000fcc00078e02ff */
/*02a0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e640000201400 */
/*02b0*/ IADD3 R6, R0, -0xd000000, RZ ; /* 0xf300000000067810 */
/* 0x002fcc0007ffe0ff */
/*02c0*/ MUFU.RSQ R9, R0 ; /* 0x0000000000097308 */
/* 0x0000620000001400 */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*02e0*/ @!P0 BRA 0x340 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x003fe400078e0000 */
/*0300*/ MOV R12, 0x320 ; /* 0x00000320000c7802 */
/* 0x000fca0000000f00 */
/*0310*/ CALL.REL.NOINC 0x540 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*0320*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe20000000f00 */
/*0330*/ BRA 0x380 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0340*/ FMUL.FTZ R7, R0, R9 ; /* 0x0000000900077220 */
/* 0x003fe40000410000 */
/*0350*/ FMUL.FTZ R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fe40000410000 */
/*0360*/ FFMA R0, -R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x000fc80000000100 */
/*0370*/ FFMA R0, R0, R9, R7 ; /* 0x0000000900007223 */
/* 0x000fe40000000007 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ F2I.U32.TRUNC.NTZ R7, R0 ; /* 0x0000000000077305 */
/* 0x000e24000020f000 */
/*03a0*/ STG.E.U8 [R4.64+0x1], R7 ; /* 0x0000010704007986 */
/* 0x0011e8000c101104 */
/*03b0*/ LDG.E.S8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea8000c1e1300 */
/*03c0*/ LDG.E.S8 R9, [R2.64+0x3] ; /* 0x0000030402097981 */
/* 0x000ea2000c1e1300 */
/*03d0*/ BSSY B0, 0x510 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*03e0*/ LEA R6, R6, -R9, 0x2 ; /* 0x8000000906067211 */
/* 0x004fca00078e10ff */
/*03f0*/ IMAD R6, R9, -0x2, R6 ; /* 0xfffffffe09067824 */
/* 0x000fca00078e0206 */
/*0400*/ IADD3 R6, -R9, R6, RZ ; /* 0x0000000609067210 */
/* 0x000fca0007ffe1ff */
/*0410*/ IMAD R6, R6, R6, RZ ; /* 0x0000000606067224 */
/* 0x000fcc00078e02ff */
/*0420*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e640000201400 */
/*0430*/ IADD3 R8, R6, -0xd000000, RZ ; /* 0xf300000006087810 */
/* 0x002fcc0007ffe0ff */
/*0440*/ MUFU.RSQ R9, R6 ; /* 0x0000000600097308 */
/* 0x0000620000001400 */
/*0450*/ ISETP.GT.U32.AND P0, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f04070 */
/*0460*/ @!P0 BRA 0x4c0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.MOV.U32 R11, RZ, RZ, R6 ; /* 0x000000ffff0b7224 */
/* 0x003fe400078e0006 */
/*0480*/ MOV R12, 0x4a0 ; /* 0x000004a0000c7802 */
/* 0x000fca0000000f00 */
/*0490*/ CALL.REL.NOINC 0x540 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*04a0*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe20000000f00 */
/*04b0*/ BRA 0x500 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04c0*/ FMUL.FTZ R3, R6, R9 ; /* 0x0000000906037220 */
/* 0x003fe40000410000 */
/*04d0*/ FMUL.FTZ R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fe40000410000 */
/*04e0*/ FFMA R0, -R3, R3, R6 ; /* 0x0000000303007223 */
/* 0x000fc80000000106 */
/*04f0*/ FFMA R0, R0, R9, R3 ; /* 0x0000000900007223 */
/* 0x000fe40000000003 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ F2I.U32.TRUNC.NTZ R3, R0 ; /* 0x0000000000037305 */
/* 0x000e24000020f000 */
/*0520*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101104 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT P0, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fda000780c0ff */
/*0550*/ @!P0 MOV R6, R11 ; /* 0x0000000b00068202 */
/* 0x000fe20000000f00 */
/*0560*/ @!P0 BRA 0x670 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0570*/ FSETP.GEU.FTZ.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x000fda0003f1e000 */
/*0580*/ @!P0 MOV R6, 0x7fffffff ; /* 0x7fffffff00068802 */
/* 0x000fe20000000f00 */
/*0590*/ @!P0 BRA 0x670 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fda0003f1c200 */
/*05b0*/ @P0 FADD.FTZ R6, R11, 1 ; /* 0x3f8000000b060421 */
/* 0x000fe20000010000 */
/*05c0*/ @P0 BRA 0x670 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*05d0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fda0003f1d200 */
/*05e0*/ @P0 FFMA R7, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b070823 */
/* 0x000fc800000000ff */
/*05f0*/ @P0 MUFU.RSQ R6, R7 ; /* 0x0000000700060308 */
/* 0x000e240000001400 */
/*0600*/ @P0 FMUL.FTZ R8, R7, R6 ; /* 0x0000000607080220 */
/* 0x001fe40000410000 */
/*0610*/ @P0 FMUL.FTZ R10, R6, 0.5 ; /* 0x3f000000060a0820 */
/* 0x000fe40000410000 */
/*0620*/ @P0 FADD.FTZ R9, -R8.reuse, -RZ ; /* 0x800000ff08090221 */
/* 0x040fe40000010100 */
/*0630*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff068224 */
/* 0x000fe400078e000b */
/*0640*/ @P0 FFMA R9, R8, R9, R7 ; /* 0x0000000908090223 */
/* 0x000fc80000000007 */
/*0650*/ @P0 FFMA R9, R9, R10, R8 ; /* 0x0000000a09090223 */
/* 0x000fc80000000008 */
/*0660*/ @P0 FMUL.FTZ R6, R9, 2.3283064365386962891e-10 ; /* 0x2f80000009060820 */
/* 0x000fc80000410000 */
/*0670*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0680*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fe40000000f00 */
/*0690*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fc80000000f00 */
/*06a0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff95006007950 */
/* 0x000fea0003c3ffff */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.*/
typedef enum color {BLUE, GREEN, RED} Color; //Constants that contains the values for each color of the image
/*The gray function obtain an average of each pixel and assigned to the correct position in the array using
Channels and step constants*/
/*The sobel function uses a convolution algorithm to obtain the edges of the image */
__global__ void sobel(unsigned char *src, unsigned char *dest, int width, int heigth, int step, int channels){
int i, j;
int ren, col, tmp_ren, tmp_col;
int gx[3][3]={{-1,0,1},{-2,0,2},{-1,0,1}}; // gx is defined in the Sobel algorithm
int gy[3][3]={{1,2,1},{0,0,0},{-1,-2,-1}}; // gy is defined in the Sobel algorithm
char temp[3][3];
ren = blockIdx.x;
col = threadIdx.x;
tmp_ren = 0;
tmp_col = 0;
//Multiplication of the 3x3 matrix for each color
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + RED + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + RED] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + GREEN + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + GREEN] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + BLUE + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + BLUE] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);
} | .file "tmpxft_001ba56a_00000000-6_sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii
.type _Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii, @function
_Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5sobelPhS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii, .-_Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii
.globl _Z5sobelPhS_iiii
.type _Z5sobelPhS_iiii, @function
_Z5sobelPhS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5sobelPhS_iiii, .-_Z5sobelPhS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5sobelPhS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sobelPhS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.*/
typedef enum color {BLUE, GREEN, RED} Color; //Constants that contains the values for each color of the image
/*The gray function obtain an average of each pixel and assigned to the correct position in the array using
Channels and step constants*/
/*The sobel function uses a convolution algorithm to obtain the edges of the image */
__global__ void sobel(unsigned char *src, unsigned char *dest, int width, int heigth, int step, int channels){
int i, j;
int ren, col, tmp_ren, tmp_col;
int gx[3][3]={{-1,0,1},{-2,0,2},{-1,0,1}}; // gx is defined in the Sobel algorithm
int gy[3][3]={{1,2,1},{0,0,0},{-1,-2,-1}}; // gy is defined in the Sobel algorithm
char temp[3][3];
ren = blockIdx.x;
col = threadIdx.x;
tmp_ren = 0;
tmp_col = 0;
//Multiplication of the 3x3 matrix for each color
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + RED + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + RED] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + GREEN + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + GREEN] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + BLUE + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + BLUE] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.*/
typedef enum color {BLUE, GREEN, RED} Color; //Constants that contains the values for each color of the image
/*The gray function obtain an average of each pixel and assigned to the correct position in the array using
Channels and step constants*/
/*The sobel function uses a convolution algorithm to obtain the edges of the image */
__global__ void sobel(unsigned char *src, unsigned char *dest, int width, int heigth, int step, int channels){
int i, j;
int ren, col, tmp_ren, tmp_col;
int gx[3][3]={{-1,0,1},{-2,0,2},{-1,0,1}}; // gx is defined in the Sobel algorithm
int gy[3][3]={{1,2,1},{0,0,0},{-1,-2,-1}}; // gy is defined in the Sobel algorithm
char temp[3][3];
ren = blockIdx.x;
col = threadIdx.x;
tmp_ren = 0;
tmp_col = 0;
//Multiplication of the 3x3 matrix for each color
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + RED + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + RED] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + GREEN + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + GREEN] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + BLUE + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + BLUE] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.*/
typedef enum color {BLUE, GREEN, RED} Color; //Constants that contains the values for each color of the image
/*The gray function obtain an average of each pixel and assigned to the correct position in the array using
Channels and step constants*/
/*The sobel function uses a convolution algorithm to obtain the edges of the image */
__global__ void sobel(unsigned char *src, unsigned char *dest, int width, int heigth, int step, int channels){
int i, j;
int ren, col, tmp_ren, tmp_col;
int gx[3][3]={{-1,0,1},{-2,0,2},{-1,0,1}}; // gx is defined in the Sobel algorithm
int gy[3][3]={{1,2,1},{0,0,0},{-1,-2,-1}}; // gy is defined in the Sobel algorithm
char temp[3][3];
ren = blockIdx.x;
col = threadIdx.x;
tmp_ren = 0;
tmp_col = 0;
//Multiplication of the 3x3 matrix for each color
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + RED + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + RED] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + GREEN + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + GREEN] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + BLUE + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + BLUE] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sobelPhS_iiii
.globl _Z5sobelPhS_iiii
.p2align 8
.type _Z5sobelPhS_iiii,@function
_Z5sobelPhS_iiii:
s_load_b64 s[12:13], s[0:1], 0x4
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s8, 0
v_bfe_u32 v1, v0, 10, 10
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_clause 0x1
s_load_b64 s[4:5], s[2:3], 0x0
s_load_b64 s[0:1], s[2:3], 0x18
v_bfe_u32 v7, v0, 20, 10
v_dual_mov_b32 v14, -1 :: v_dual_mov_b32 v17, -2
v_mov_b32_e32 v12, 2
s_mov_b32 s7, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_u32_u24_e32 v20, 36, v7
v_mov_b32_e32 v15, v17
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s12, 16
v_mul_u32_u24_e32 v8, s13, v1
s_mul_i32 s11, s6, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v5, s11, v4
s_mov_b32 s11, s8
v_mov_b32_e32 v16, 1
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
v_mul_lo_u32 v21, v8, 36
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v3, s11
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v13, v16
v_mul_lo_u32 v9, v4, s13
v_add3_u32 v5, v5, v8, v7
v_mul_lo_u32 v18, v4, s1
v_mov_b32_e32 v2, s10
v_dual_mov_b32 v10, -1 :: v_dual_mov_b32 v11, v16
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v19, v5, 36
s_clause 0x1
scratch_store_b128 off, v[0:3], off offset:16
scratch_store_b128 off, v[0:3], off offset:32
v_mul_lo_u32 v9, v9, s6
s_mul_i32 s6, s15, s0
s_add_u32 s0, s4, 1
v_add3_u32 v5, s6, 2, v18
ds_store_b128 v19, v[0:3]
ds_store_b128 v19, v[0:3] offset:16
ds_store_b32 v19, v14
ds_store_b64 v19, v[16:17] offset:8
ds_store_2addr_b32 v19, v6, v10 offset0:5 offset1:6
ds_store_b32 v19, v16 offset:32
v_mov_b32_e32 v10, 16
v_mov_b32_e32 v0, 0
v_mul_lo_u32 v22, v9, 36
v_mov_b32_e32 v2, 0
s_addc_u32 s8, s5, 0
s_clause 0x2
scratch_store_b96 off, v[11:13], off offset:16
scratch_store_b64 off, v[14:15], off offset:40
scratch_store_b32 off, v14, off offset:48
v_add3_u32 v6, v22, v21, v20
.p2align 6
.LBB0_1:
v_add_nc_u32_e32 v1, s7, v5
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v1
v_add_co_u32 v11, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v12, vcc_lo, s8, v3, vcc_lo
global_load_i8 v11, v[11:12], off
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v12, v0 :: v_dual_add_nc_u32 v1, s9, v10
scratch_load_b32 v13, v1, off
v_add_nc_u32_e32 v1, s9, v6
s_add_i32 s9, s9, 4
s_cmp_lg_u32 s9, 12
ds_load_b32 v14, v1
v_mov_b32_e32 v1, v2
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v14, v11, v[1:2]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v13, v11, v[12:13]
s_cbranch_scc1 .LBB0_2
v_add_nc_u32_e32 v10, 12, v10
v_add_nc_u32_e32 v6, 12, v6
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s7, 2
s_cbranch_scc1 .LBB0_1
v_mul_lo_u32 v1, v2, v2
s_load_b64 s[2:3], s[2:3], 0x8
v_mov_b32_e32 v10, 16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, v0, v[1:2]
v_cvt_f32_i32_e32 v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v1
v_add_nc_u32_e32 v3, 1, v1
v_fma_f32 v5, -v2, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v1, v0
v_cmp_ge_f32_e64 s0, 0, v5
v_mul_lo_u32 v5, v8, 36
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v1, v1, v2, s0
v_cmp_lt_f32_e64 s0, 0, v6
v_mul_u32_u24_e32 v6, 36, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, v3, s0
v_mad_u64_u32 v[2:3], null, v4, s1, s[6:7]
v_mul_lo_u32 v3, v9, 36
s_add_u32 s1, s4, 1
v_mul_f32_e32 v4, 0x37800000, v1
s_mov_b32 s0, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, 1, v2
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
v_ashrrev_i32_e32 v4, 31, v2
v_add3_u32 v12, v3, v5, v6
v_mov_b32_e32 v5, 0
v_cndmask_b32_e32 v3, v1, v0, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_i32_f32_e32 v4, v3
v_mov_b32_e32 v3, 0
s_addc_u32 s2, s5, 0
global_store_b8 v[0:1], v4, off offset:2
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v4, s0, v11
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v4
v_add_co_u32 v13, vcc_lo, s1, v4
v_add_co_ci_u32_e32 v14, vcc_lo, s2, v6, vcc_lo
global_load_i8 v13, v[13:14], off
.LBB0_6:
v_add_nc_u32_e32 v4, s3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v14, v3
scratch_load_b32 v15, v4, off
v_add_nc_u32_e32 v4, s3, v12
s_add_i32 s3, s3, 4
s_cmp_lg_u32 s3, 12
ds_load_b32 v16, v4
v_mov_b32_e32 v4, v5
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v16, v13, v[4:5]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v15, v13, v[14:15]
s_cbranch_scc1 .LBB0_6
v_add_nc_u32_e32 v10, 12, v10
v_add_nc_u32_e32 v12, 12, v12
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 2
s_cbranch_scc1 .LBB0_5
v_mul_lo_u32 v4, v5, v5
s_add_u32 s1, s4, 1
s_addc_u32 s2, s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v3, v3, v[4:5]
v_cvt_f32_i32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
v_fma_f32 v10, -v5, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v6, v4, v3
v_cmp_ge_f32_e64 s0, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cmp_lt_f32_e64 s0, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v4, v6, s0
v_mul_lo_u32 v6, v9, 36
s_mov_b32 s0, -1
v_mul_f32_e32 v5, 0x37800000, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
v_mul_lo_u32 v5, v8, 36
v_mul_u32_u24_e32 v8, 36, v7
v_mov_b32_e32 v7, 16
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v8, v6, v5, v8
v_cvt_i32_f32_e32 v4, v3
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v5, 0
global_store_b8 v[0:1], v4, off offset:1
.p2align 6
.LBB0_9:
v_add_nc_u32_e32 v4, s0, v2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v4
v_add_co_u32 v9, vcc_lo, s1, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s2, v6, vcc_lo
global_load_i8 v9, v[9:10], off
.LBB0_10:
v_add_nc_u32_e32 v4, s3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v10, v3
scratch_load_b32 v11, v4, off
v_add_nc_u32_e32 v4, s3, v8
s_add_i32 s3, s3, 4
s_cmp_lg_u32 s3, 12
ds_load_b32 v12, v4
v_mov_b32_e32 v4, v5
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v12, v9, v[4:5]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v11, v9, v[10:11]
s_cbranch_scc1 .LBB0_10
v_add_nc_u32_e32 v7, 12, v7
v_add_nc_u32_e32 v8, 12, v8
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 2
s_cbranch_scc1 .LBB0_9
v_mul_lo_u32 v2, v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, v3, v[2:3]
v_cvt_f32_i32_e32 v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
global_store_b8 v[0:1], v2, off
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sobelPhS_iiii
.amdhsa_group_segment_fixed_size 36864
.amdhsa_private_segment_fixed_size 64
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sobelPhS_iiii, .Lfunc_end0-_Z5sobelPhS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 36864
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sobelPhS_iiii
.private_segment_fixed_size: 64
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5sobelPhS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* This code will generate a Sobel image and a Gray Scale image. Uses OpenCV, to compile:
nvcc FinalProject.cu `pkg-config --cflags --libs opencv`
Copyright (C) 2018 Jose Andres Cortez Villao
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <https://www.gnu.org/licenses/>.*/
typedef enum color {BLUE, GREEN, RED} Color; //Constants that contains the values for each color of the image
/*The gray function obtain an average of each pixel and assigned to the correct position in the array using
Channels and step constants*/
/*The sobel function uses a convolution algorithm to obtain the edges of the image */
__global__ void sobel(unsigned char *src, unsigned char *dest, int width, int heigth, int step, int channels){
int i, j;
int ren, col, tmp_ren, tmp_col;
int gx[3][3]={{-1,0,1},{-2,0,2},{-1,0,1}}; // gx is defined in the Sobel algorithm
int gy[3][3]={{1,2,1},{0,0,0},{-1,-2,-1}}; // gy is defined in the Sobel algorithm
char temp[3][3];
ren = blockIdx.x;
col = threadIdx.x;
tmp_ren = 0;
tmp_col = 0;
//Multiplication of the 3x3 matrix for each color
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + RED + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + RED] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + GREEN + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + GREEN] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);;
tmp_ren = 0;
tmp_col = 0;
for (i = -1; i < 2; i++) {
for (j = -1; j < 2; j++) {
temp[i+1][j+1]=(int) src[(ren * step) + (col * channels) + BLUE + i + 1];
tmp_ren=tmp_ren + temp[i+1][j+1]*gx[i+1][j+1];
tmp_col=tmp_col + temp[i+1][j+1]*gy[i+1][j+1];
}
}
dest[(ren * step) + (col * channels) + BLUE] = (unsigned char) sqrtf(tmp_col*tmp_col+tmp_ren*tmp_ren);
} | .text
.file "sobel.hip"
.globl _Z20__device_stub__sobelPhS_iiii # -- Begin function _Z20__device_stub__sobelPhS_iiii
.p2align 4, 0x90
.type _Z20__device_stub__sobelPhS_iiii,@function
_Z20__device_stub__sobelPhS_iiii: # @_Z20__device_stub__sobelPhS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sobelPhS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z20__device_stub__sobelPhS_iiii, .Lfunc_end0-_Z20__device_stub__sobelPhS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sobelPhS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sobelPhS_iiii,@object # @_Z5sobelPhS_iiii
.section .rodata,"a",@progbits
.globl _Z5sobelPhS_iiii
.p2align 3, 0x0
_Z5sobelPhS_iiii:
.quad _Z20__device_stub__sobelPhS_iiii
.size _Z5sobelPhS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5sobelPhS_iiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sobelPhS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sobelPhS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5sobelPhS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0040*/ IMAD R0, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000007a24 */
/* 0x001fc800078e02ff */
/*0050*/ IMAD R0, R3, c[0x0][0x178], R0 ; /* 0x00005e0003007a24 */
/* 0x002fca00078e0200 */
/*0060*/ IADD3 R3, R0, -0x1, RZ ; /* 0xffffffff00037810 */
/* 0x000fc80007ffe0ff */
/*0070*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0080*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fca00000f0eff */
/*0090*/ LDG.E.S8 R4, [R2.64+0x3] ; /* 0x0000030402047981 */
/* 0x000ea8000c1e1300 */
/*00a0*/ LDG.E.S8 R5, [R2.64+0x5] ; /* 0x0000050402057981 */
/* 0x000ea2000c1e1300 */
/*00b0*/ BSSY B0, 0x1f0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*00c0*/ LEA R4, R4, -R5, 0x2 ; /* 0x8000000504047211 */
/* 0x004fca00078e10ff */
/*00d0*/ IMAD R4, R5, -0x2, R4 ; /* 0xfffffffe05047824 */
/* 0x000fca00078e0204 */
/*00e0*/ IADD3 R4, -R5, R4, RZ ; /* 0x0000000405047210 */
/* 0x000fca0007ffe1ff */
/*00f0*/ IMAD R4, R4, R4, RZ ; /* 0x0000000404047224 */
/* 0x000fcc00078e02ff */
/*0100*/ I2F R4, R4 ; /* 0x0000000400047306 */
/* 0x000e240000201400 */
/*0110*/ IADD3 R6, R4, -0xd000000, RZ ; /* 0xf300000004067810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*0130*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0140*/ @!P0 BRA 0x1a0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R11, RZ, RZ, R4 ; /* 0x000000ffff0b7224 */
/* 0x003fe400078e0004 */
/*0160*/ MOV R12, 0x180 ; /* 0x00000180000c7802 */
/* 0x000fca0000000f00 */
/*0170*/ CALL.REL.NOINC 0x540 ; /* 0x000003c000007944 */
/* 0x000fea0003c00000 */
/*0180*/ MOV R6, R8 ; /* 0x0000000800067202 */
/* 0x000fe20000000f00 */
/*0190*/ BRA 0x1e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01a0*/ FMUL.FTZ R7, R4, R5 ; /* 0x0000000504077220 */
/* 0x003fe40000410000 */
/*01b0*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*01c0*/ FFMA R4, -R7, R7, R4 ; /* 0x0000000707047223 */
/* 0x000fc80000000104 */
/*01d0*/ FFMA R6, R4, R5, R7 ; /* 0x0000000504067223 */
/* 0x000fe40000000007 */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ F2I.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000e22000020f000 */
/*0200*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*0210*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f0eff */
/*0220*/ STG.E.U8 [R4.64+0x2], R7 ; /* 0x0000020704007986 */
/* 0x0011e8000c101104 */
/*0230*/ LDG.E.S8 R0, [R2.64+0x2] ; /* 0x0000020402007981 */
/* 0x000ea8000c1e1300 */
/*0240*/ LDG.E.S8 R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea2000c1e1300 */
/*0250*/ BSSY B0, 0x390 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0260*/ LEA R0, R0, -R9, 0x2 ; /* 0x8000000900007211 */
/* 0x004fca00078e10ff */
/*0270*/ IMAD R0, R9, -0x2, R0 ; /* 0xfffffffe09007824 */
/* 0x000fca00078e0200 */
/*0280*/ IADD3 R0, -R9, R0, RZ ; /* 0x0000000009007210 */
/* 0x000fca0007ffe1ff */
/*0290*/ IMAD R0, R0, R0, RZ ; /* 0x0000000000007224 */
/* 0x000fcc00078e02ff */
/*02a0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000e640000201400 */
/*02b0*/ IADD3 R6, R0, -0xd000000, RZ ; /* 0xf300000000067810 */
/* 0x002fcc0007ffe0ff */
/*02c0*/ MUFU.RSQ R9, R0 ; /* 0x0000000000097308 */
/* 0x0000620000001400 */
/*02d0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*02e0*/ @!P0 BRA 0x340 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02f0*/ IMAD.MOV.U32 R11, RZ, RZ, R0 ; /* 0x000000ffff0b7224 */
/* 0x003fe400078e0000 */
/*0300*/ MOV R12, 0x320 ; /* 0x00000320000c7802 */
/* 0x000fca0000000f00 */
/*0310*/ CALL.REL.NOINC 0x540 ; /* 0x0000022000007944 */
/* 0x000fea0003c00000 */
/*0320*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe20000000f00 */
/*0330*/ BRA 0x380 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0340*/ FMUL.FTZ R7, R0, R9 ; /* 0x0000000900077220 */
/* 0x003fe40000410000 */
/*0350*/ FMUL.FTZ R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fe40000410000 */
/*0360*/ FFMA R0, -R7, R7, R0 ; /* 0x0000000707007223 */
/* 0x000fc80000000100 */
/*0370*/ FFMA R0, R0, R9, R7 ; /* 0x0000000900007223 */
/* 0x000fe40000000007 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ F2I.U32.TRUNC.NTZ R7, R0 ; /* 0x0000000000077305 */
/* 0x000e24000020f000 */
/*03a0*/ STG.E.U8 [R4.64+0x1], R7 ; /* 0x0000010704007986 */
/* 0x0011e8000c101104 */
/*03b0*/ LDG.E.S8 R6, [R2.64+0x1] ; /* 0x0000010402067981 */
/* 0x000ea8000c1e1300 */
/*03c0*/ LDG.E.S8 R9, [R2.64+0x3] ; /* 0x0000030402097981 */
/* 0x000ea2000c1e1300 */
/*03d0*/ BSSY B0, 0x510 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*03e0*/ LEA R6, R6, -R9, 0x2 ; /* 0x8000000906067211 */
/* 0x004fca00078e10ff */
/*03f0*/ IMAD R6, R9, -0x2, R6 ; /* 0xfffffffe09067824 */
/* 0x000fca00078e0206 */
/*0400*/ IADD3 R6, -R9, R6, RZ ; /* 0x0000000609067210 */
/* 0x000fca0007ffe1ff */
/*0410*/ IMAD R6, R6, R6, RZ ; /* 0x0000000606067224 */
/* 0x000fcc00078e02ff */
/*0420*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e640000201400 */
/*0430*/ IADD3 R8, R6, -0xd000000, RZ ; /* 0xf300000006087810 */
/* 0x002fcc0007ffe0ff */
/*0440*/ MUFU.RSQ R9, R6 ; /* 0x0000000600097308 */
/* 0x0000620000001400 */
/*0450*/ ISETP.GT.U32.AND P0, PT, R8, 0x727fffff, PT ; /* 0x727fffff0800780c */
/* 0x000fda0003f04070 */
/*0460*/ @!P0 BRA 0x4c0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0470*/ IMAD.MOV.U32 R11, RZ, RZ, R6 ; /* 0x000000ffff0b7224 */
/* 0x003fe400078e0006 */
/*0480*/ MOV R12, 0x4a0 ; /* 0x000004a0000c7802 */
/* 0x000fca0000000f00 */
/*0490*/ CALL.REL.NOINC 0x540 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*04a0*/ MOV R0, R8 ; /* 0x0000000800007202 */
/* 0x000fe20000000f00 */
/*04b0*/ BRA 0x500 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04c0*/ FMUL.FTZ R3, R6, R9 ; /* 0x0000000906037220 */
/* 0x003fe40000410000 */
/*04d0*/ FMUL.FTZ R9, R9, 0.5 ; /* 0x3f00000009097820 */
/* 0x000fe40000410000 */
/*04e0*/ FFMA R0, -R3, R3, R6 ; /* 0x0000000303007223 */
/* 0x000fc80000000106 */
/*04f0*/ FFMA R0, R0, R9, R3 ; /* 0x0000000900007223 */
/* 0x000fe40000000003 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ F2I.U32.TRUNC.NTZ R3, R0 ; /* 0x0000000000037305 */
/* 0x000e24000020f000 */
/*0520*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101104 */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ LOP3.LUT P0, RZ, R11, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0bff7812 */
/* 0x000fda000780c0ff */
/*0550*/ @!P0 MOV R6, R11 ; /* 0x0000000b00068202 */
/* 0x000fe20000000f00 */
/*0560*/ @!P0 BRA 0x670 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0570*/ FSETP.GEU.FTZ.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720b */
/* 0x000fda0003f1e000 */
/*0580*/ @!P0 MOV R6, 0x7fffffff ; /* 0x7fffffff00068802 */
/* 0x000fe20000000f00 */
/*0590*/ @!P0 BRA 0x670 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05a0*/ FSETP.GTU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fda0003f1c200 */
/*05b0*/ @P0 FADD.FTZ R6, R11, 1 ; /* 0x3f8000000b060421 */
/* 0x000fe20000010000 */
/*05c0*/ @P0 BRA 0x670 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*05d0*/ FSETP.NEU.FTZ.AND P0, PT, |R11|, +INF , PT ; /* 0x7f8000000b00780b */
/* 0x000fda0003f1d200 */
/*05e0*/ @P0 FFMA R7, R11, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000b070823 */
/* 0x000fc800000000ff */
/*05f0*/ @P0 MUFU.RSQ R6, R7 ; /* 0x0000000700060308 */
/* 0x000e240000001400 */
/*0600*/ @P0 FMUL.FTZ R8, R7, R6 ; /* 0x0000000607080220 */
/* 0x001fe40000410000 */
/*0610*/ @P0 FMUL.FTZ R10, R6, 0.5 ; /* 0x3f000000060a0820 */
/* 0x000fe40000410000 */
/*0620*/ @P0 FADD.FTZ R9, -R8.reuse, -RZ ; /* 0x800000ff08090221 */
/* 0x040fe40000010100 */
/*0630*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff068224 */
/* 0x000fe400078e000b */
/*0640*/ @P0 FFMA R9, R8, R9, R7 ; /* 0x0000000908090223 */
/* 0x000fc80000000007 */
/*0650*/ @P0 FFMA R9, R9, R10, R8 ; /* 0x0000000a09090223 */
/* 0x000fc80000000008 */
/*0660*/ @P0 FMUL.FTZ R6, R9, 2.3283064365386962891e-10 ; /* 0x2f80000009060820 */
/* 0x000fc80000410000 */
/*0670*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0680*/ MOV R8, R6 ; /* 0x0000000600087202 */
/* 0x000fe40000000f00 */
/*0690*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fc80000000f00 */
/*06a0*/ RET.REL.NODEC R6 0x0 ; /* 0xfffff95006007950 */
/* 0x000fea0003c3ffff */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5sobelPhS_iiii
.globl _Z5sobelPhS_iiii
.p2align 8
.type _Z5sobelPhS_iiii,@function
_Z5sobelPhS_iiii:
s_load_b64 s[12:13], s[0:1], 0x4
v_and_b32_e32 v4, 0x3ff, v0
s_mov_b32 s8, 0
v_bfe_u32 v1, v0, 10, 10
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_clause 0x1
s_load_b64 s[4:5], s[2:3], 0x0
s_load_b64 s[0:1], s[2:3], 0x18
v_bfe_u32 v7, v0, 20, 10
v_dual_mov_b32 v14, -1 :: v_dual_mov_b32 v17, -2
v_mov_b32_e32 v12, 2
s_mov_b32 s7, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_u32_u24_e32 v20, 36, v7
v_mov_b32_e32 v15, v17
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s12, 16
v_mul_u32_u24_e32 v8, s13, v1
s_mul_i32 s11, s6, s13
s_delay_alu instid0(SALU_CYCLE_1)
v_mul_lo_u32 v5, s11, v4
s_mov_b32 s11, s8
v_mov_b32_e32 v16, 1
v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9
v_mul_lo_u32 v21, v8, 36
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v3, s11
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v13, v16
v_mul_lo_u32 v9, v4, s13
v_add3_u32 v5, v5, v8, v7
v_mul_lo_u32 v18, v4, s1
v_mov_b32_e32 v2, s10
v_dual_mov_b32 v10, -1 :: v_dual_mov_b32 v11, v16
s_delay_alu instid0(VALU_DEP_4)
v_mul_lo_u32 v19, v5, 36
s_clause 0x1
scratch_store_b128 off, v[0:3], off offset:16
scratch_store_b128 off, v[0:3], off offset:32
v_mul_lo_u32 v9, v9, s6
s_mul_i32 s6, s15, s0
s_add_u32 s0, s4, 1
v_add3_u32 v5, s6, 2, v18
ds_store_b128 v19, v[0:3]
ds_store_b128 v19, v[0:3] offset:16
ds_store_b32 v19, v14
ds_store_b64 v19, v[16:17] offset:8
ds_store_2addr_b32 v19, v6, v10 offset0:5 offset1:6
ds_store_b32 v19, v16 offset:32
v_mov_b32_e32 v10, 16
v_mov_b32_e32 v0, 0
v_mul_lo_u32 v22, v9, 36
v_mov_b32_e32 v2, 0
s_addc_u32 s8, s5, 0
s_clause 0x2
scratch_store_b96 off, v[11:13], off offset:16
scratch_store_b64 off, v[14:15], off offset:40
scratch_store_b32 off, v14, off offset:48
v_add3_u32 v6, v22, v21, v20
.p2align 6
.LBB0_1:
v_add_nc_u32_e32 v1, s7, v5
s_mov_b32 s9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v1
v_add_co_u32 v11, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v12, vcc_lo, s8, v3, vcc_lo
global_load_i8 v11, v[11:12], off
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v12, v0 :: v_dual_add_nc_u32 v1, s9, v10
scratch_load_b32 v13, v1, off
v_add_nc_u32_e32 v1, s9, v6
s_add_i32 s9, s9, 4
s_cmp_lg_u32 s9, 12
ds_load_b32 v14, v1
v_mov_b32_e32 v1, v2
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v14, v11, v[1:2]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[0:1], null, v13, v11, v[12:13]
s_cbranch_scc1 .LBB0_2
v_add_nc_u32_e32 v10, 12, v10
v_add_nc_u32_e32 v6, 12, v6
s_add_i32 s7, s7, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s7, 2
s_cbranch_scc1 .LBB0_1
v_mul_lo_u32 v1, v2, v2
s_load_b64 s[2:3], s[2:3], 0x8
v_mov_b32_e32 v10, 16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, v0, v[1:2]
v_cvt_f32_i32_e32 v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v1, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v1, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v2, -1, v1
v_add_nc_u32_e32 v3, 1, v1
v_fma_f32 v5, -v2, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v3, v1, v0
v_cmp_ge_f32_e64 s0, 0, v5
v_mul_lo_u32 v5, v8, 36
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v1, v1, v2, s0
v_cmp_lt_f32_e64 s0, 0, v6
v_mul_u32_u24_e32 v6, 36, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, v3, s0
v_mad_u64_u32 v[2:3], null, v4, s1, s[6:7]
v_mul_lo_u32 v3, v9, 36
s_add_u32 s1, s4, 1
v_mul_f32_e32 v4, 0x37800000, v1
s_mov_b32 s0, -1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v11, 1, v2
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
v_ashrrev_i32_e32 v4, 31, v2
v_add3_u32 v12, v3, v5, v6
v_mov_b32_e32 v5, 0
v_cndmask_b32_e32 v3, v1, v0, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cvt_i32_f32_e32 v4, v3
v_mov_b32_e32 v3, 0
s_addc_u32 s2, s5, 0
global_store_b8 v[0:1], v4, off offset:2
.p2align 6
.LBB0_5:
v_add_nc_u32_e32 v4, s0, v11
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v4
v_add_co_u32 v13, vcc_lo, s1, v4
v_add_co_ci_u32_e32 v14, vcc_lo, s2, v6, vcc_lo
global_load_i8 v13, v[13:14], off
.LBB0_6:
v_add_nc_u32_e32 v4, s3, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v14, v3
scratch_load_b32 v15, v4, off
v_add_nc_u32_e32 v4, s3, v12
s_add_i32 s3, s3, 4
s_cmp_lg_u32 s3, 12
ds_load_b32 v16, v4
v_mov_b32_e32 v4, v5
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v16, v13, v[4:5]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v15, v13, v[14:15]
s_cbranch_scc1 .LBB0_6
v_add_nc_u32_e32 v10, 12, v10
v_add_nc_u32_e32 v12, 12, v12
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 2
s_cbranch_scc1 .LBB0_5
v_mul_lo_u32 v4, v5, v5
s_add_u32 s1, s4, 1
s_addc_u32 s2, s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v3, v3, v[4:5]
v_cvt_f32_i32_e32 v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v4, 0x4f800000, v3
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v3
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v5, -1, v4
v_add_nc_u32_e32 v6, 1, v4
v_fma_f32 v10, -v5, v4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v6, v4, v3
v_cmp_ge_f32_e64 s0, 0, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, v4, v5, s0
v_cmp_lt_f32_e64 s0, 0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v4, v4, v6, s0
v_mul_lo_u32 v6, v9, 36
s_mov_b32 s0, -1
v_mul_f32_e32 v5, 0x37800000, v4
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v4, v4, v5, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v3, 0x260
v_mul_lo_u32 v5, v8, 36
v_mul_u32_u24_e32 v8, 36, v7
v_mov_b32_e32 v7, 16
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v8, v6, v5, v8
v_cvt_i32_f32_e32 v4, v3
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v5, 0
global_store_b8 v[0:1], v4, off offset:1
.p2align 6
.LBB0_9:
v_add_nc_u32_e32 v4, s0, v2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v6, 31, v4
v_add_co_u32 v9, vcc_lo, s1, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s2, v6, vcc_lo
global_load_i8 v9, v[9:10], off
.LBB0_10:
v_add_nc_u32_e32 v4, s3, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v10, v3
scratch_load_b32 v11, v4, off
v_add_nc_u32_e32 v4, s3, v8
s_add_i32 s3, s3, 4
s_cmp_lg_u32 s3, 12
ds_load_b32 v12, v4
v_mov_b32_e32 v4, v5
s_waitcnt vmcnt(1) lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v12, v9, v[4:5]
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v11, v9, v[10:11]
s_cbranch_scc1 .LBB0_10
v_add_nc_u32_e32 v7, 12, v7
v_add_nc_u32_e32 v8, 12, v8
s_add_i32 s0, s0, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s0, 2
s_cbranch_scc1 .LBB0_9
v_mul_lo_u32 v2, v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v3, v3, v[2:3]
v_cvt_f32_i32_e32 v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v2, v2
global_store_b8 v[0:1], v2, off
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sobelPhS_iiii
.amdhsa_group_segment_fixed_size 36864
.amdhsa_private_segment_fixed_size 64
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 1
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5sobelPhS_iiii, .Lfunc_end0-_Z5sobelPhS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 36864
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sobelPhS_iiii
.private_segment_fixed_size: 64
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5sobelPhS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001ba56a_00000000-6_sobel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii
.type _Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii, @function
_Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5sobelPhS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii, .-_Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii
.globl _Z5sobelPhS_iiii
.type _Z5sobelPhS_iiii, @function
_Z5sobelPhS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5sobelPhS_iiiiPhS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5sobelPhS_iiii, .-_Z5sobelPhS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5sobelPhS_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sobelPhS_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sobel.hip"
.globl _Z20__device_stub__sobelPhS_iiii # -- Begin function _Z20__device_stub__sobelPhS_iiii
.p2align 4, 0x90
.type _Z20__device_stub__sobelPhS_iiii,@function
_Z20__device_stub__sobelPhS_iiii: # @_Z20__device_stub__sobelPhS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5sobelPhS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z20__device_stub__sobelPhS_iiii, .Lfunc_end0-_Z20__device_stub__sobelPhS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sobelPhS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5sobelPhS_iiii,@object # @_Z5sobelPhS_iiii
.section .rodata,"a",@progbits
.globl _Z5sobelPhS_iiii
.p2align 3, 0x0
_Z5sobelPhS_iiii:
.quad _Z20__device_stub__sobelPhS_iiii
.size _Z5sobelPhS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5sobelPhS_iiii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sobelPhS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sobelPhS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
float x = step * index;
tab[index] = sinf(sqrtf(x));
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
cudaError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N;
float *hT = (float *)malloc(size);
float *hRes = (float *)malloc(size);
if (hT == NULL || hRes == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
tcpu = -wtime();
tabfun_host(hT, step, N);
tcpu += wtime();
/* Allocate vectors on device */
float *dT = NULL;
if (cudaMalloc((void **)&dT, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n",
blocksPerGrid, threadsPerBlock);
tgpu = -wtime();
tabfun<<<blocksPerGrid, threadsPerBlock>>>(dT, step, N);
cudaDeviceSynchronize();
tgpu += wtime();
if ( (err = cudaGetLastError()) != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (cudaMemcpy(hRes, dT, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
float d = fabs(hT[i] - hRes[i]);
printf("%d: %f\n", i, d);
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
cudaFree(dT);
free(hT);
free(hRes);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z6tabfunPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x16c], PT ; /* 0x00005b0008007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ I2F R0, R8 ; /* 0x0000000800007306 */
/* 0x000e220000201400 */
/*0080*/ BSSY B0, 0x180 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0090*/ FMUL R0, R0, c[0x0][0x168] ; /* 0x00005a0000007a20 */
/* 0x001fcc0000400000 */
/*00a0*/ MUFU.RSQ R3, R0 ; /* 0x0000000000037308 */
/* 0x0000620000001400 */
/*00b0*/ IADD3 R2, R0, -0xd000000, RZ ; /* 0xf300000000027810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*00d0*/ @!P0 BRA 0x130 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00e0*/ BSSY B1, 0x120 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*00f0*/ MOV R7, 0x110 ; /* 0x0000011000077802 */
/* 0x000fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x730 ; /* 0x0000062000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x170 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0130*/ FMUL.FTZ R9, R0, R3 ; /* 0x0000000300097220 */
/* 0x003fe40000410000 */
/*0140*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*0150*/ FFMA R0, -R9, R9, R0 ; /* 0x0000000909007223 */
/* 0x000fc80000000100 */
/*0160*/ FFMA R9, R0, R3, R9 ; /* 0x0000000300097223 */
/* 0x000fe40000000009 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ FMUL R0, R9.reuse, 0.63661974668502807617 ; /* 0x3f22f98309007820 */
/* 0x040fe20000400000 */
/*0190*/ FSETP.GE.AND P0, PT, |R9|, 105615, PT ; /* 0x47ce47800900780b */
/* 0x000fe20003f06200 */
/*01a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ BSSY B0, 0x5f0 ; /* 0x0000043000007945 */
/* 0x000fe60003800000 */
/*01c0*/ F2I.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e300000203100 */
/*01d0*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x001e240000201400 */
/*01e0*/ FFMA R3, R2, -1.5707962512969970703, R9 ; /* 0xbfc90fda02037823 */
/* 0x001fc80000000009 */
/*01f0*/ FFMA R3, R2, -7.5497894158615963534e-08, R3 ; /* 0xb3a2216802037823 */
/* 0x000fc80000000003 */
/*0200*/ FFMA R6, R2, -5.3903029534742383927e-15, R3 ; /* 0xa7c234c502067823 */
/* 0x000fe20000000003 */
/*0210*/ @!P0 BRA 0x5e0 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.NEU.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f0d200 */
/*0230*/ @!P0 BRA 0x5c0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0240*/ SHF.R.U32.HI R0, RZ, 0x17, R9 ; /* 0x00000017ff007819 */
/* 0x000fe20000011609 */
/*0250*/ IMAD.SHL.U32 R2, R9, 0x100, RZ ; /* 0x0000010009027824 */
/* 0x000fe200078e00ff */
/*0260*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0270*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0280*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe200078ec0ff */
/*0290*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*02a0*/ LOP3.LUT R13, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000020d7812 */
/* 0x000fe400078efcff */
/*02b0*/ IADD3 R10, R0, -0x80, RZ ; /* 0xffffff80000a7810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0001 */
/*02d0*/ SHF.R.U32.HI R12, RZ, 0x5, R10 ; /* 0x00000005ff0c7819 */
/* 0x000fe4000001160a */
/*02e0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ MOV R5, UR9 ; /* 0x0000000900057c02 */
/* 0x000fca0008000f00 */
/*0300*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*0310*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0320*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0330*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x000fe20003f05270 */
/*0340*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0350*/ IMAD.WIDE.U32 R2, R2, R13, RZ ; /* 0x0000000d02027225 */
/* 0x004fca00078e00ff */
/*0360*/ IADD3 R11, P1, R2, R6, RZ ; /* 0x00000006020b7210 */
/* 0x000fc80007f3e0ff */
/*0370*/ IADD3.X R6, R3, UR4, RZ, P1, !PT ; /* 0x0000000403067c10 */
/* 0x000fe20008ffe4ff */
/*0380*/ STL [R0], R11 ; /* 0x0000000b00007387 */
/* 0x0001e40000100800 */
/*0390*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*03a0*/ @P0 BRA 0x2e0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*03b0*/ LOP3.LUT P0, R7, R10, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0a077812 */
/* 0x000fe2000780c0ff */
/*03c0*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e20000100800 */
/*03d0*/ IADD3 R2, -R12.reuse, 0x4, RZ ; /* 0x000000040c027810 */
/* 0x040fe40007ffe1ff */
/*03e0*/ IADD3 R0, -R12, 0x6, RZ ; /* 0x000000060c007810 */
/* 0x000fca0007ffe1ff */
/*03f0*/ IMAD R10, R0, 0x4, R1 ; /* 0x00000004000a7824 */
/* 0x000fc800078e0201 */
/*0400*/ @P0 IMAD R11, R2, 0x4, R1 ; /* 0x00000004020b0824 */
/* 0x000fe200078e0201 */
/*0410*/ LDL R0, [R10] ; /* 0x000000000a007983 */
/* 0x000ea80000100800 */
/*0420*/ @P0 LDL R5, [R11] ; /* 0x000000000b050983 */
/* 0x000ee80000100800 */
/*0430*/ LDL R3, [R10+-0x4] ; /* 0xfffffc000a037983 */
/* 0x000f220000100800 */
/*0440*/ @P0 IADD3 R2, -R7, 0x20, RZ ; /* 0x0000002007020810 */
/* 0x000fc80007ffe1ff */
/*0450*/ @P0 SHF.R.U32.HI R4, RZ, R2.reuse, R5 ; /* 0x00000002ff040219 */
/* 0x088fe40000011605 */
/*0460*/ @P0 SHF.L.U32 R5, R0, R7.reuse, RZ ; /* 0x0000000700050219 */
/* 0x084fe400000006ff */
/*0470*/ @P0 SHF.R.U32.HI R2, RZ, R2, R3 ; /* 0x00000002ff020219 */
/* 0x010fe40000011603 */
/*0480*/ @P0 SHF.L.U32 R7, R3, R7, RZ ; /* 0x0000000703070219 */
/* 0x000fc600000006ff */
/*0490*/ @P0 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102000824 */
/* 0x000fe400078e0205 */
/*04a0*/ @P0 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104030824 */
/* 0x000fca00078e0207 */
/*04b0*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*04c0*/ SHF.R.U32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x000fc80000011605 */
/*04d0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*04e0*/ SHF.L.U32 R4, R3, 0x2, RZ ; /* 0x0000000203047819 */
/* 0x000fd600000006ff */
/*04f0*/ @P1 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff051212 */
/* 0x000fe400078e33ff */
/*0500*/ @P1 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff041212 */
/* 0x000fc800078e33ff */
/*0510*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e620000301c00 */
/*0520*/ LOP3.LUT P0, R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fe2000780c0ff */
/*0530*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x002e620000000000 */
/*0540*/ LEA.HI R0, R0, R7, RZ, 0x2 ; /* 0x0000000700007211 */
/* 0x000fd200078f10ff */
/*0550*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x002e620000301000 */
/*0560*/ @P1 LOP3.LUT R9, R9, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000009091812 */
/* 0x000fe200078e3cff */
/*0570*/ IMAD.MOV R6, RZ, RZ, -R0 ; /* 0x000000ffff067224 */
/* 0x001fc600078e0a00 */
/*0580*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0590*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff000224 */
/* 0x000fc600078e0006 */
/*05a0*/ FSEL R6, R2, -R2, !P1 ; /* 0x8000000202067208 */
/* 0x002fe20004800000 */
/*05b0*/ BRA 0x5e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*05c0*/ FMUL R6, RZ, R9 ; /* 0x00000009ff067220 */
/* 0x000fe40000400000 */
/*05d0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ LOP3.LUT P1, RZ, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100ff7812 */
/* 0x000fe2000782c0ff */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff037424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R2, 0xb94d4153 ; /* 0xb94d415300027802 */
/* 0x000fe20000000f00 */
/*0620*/ FMUL R7, R6, R6 ; /* 0x0000000606077220 */
/* 0x000fe20000400000 */
/*0630*/ LOP3.LUT P0, RZ, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200ff7812 */
/* 0x000fe2000780c0ff */
/*0640*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff057424 */
/* 0x000fe200078e00ff */
/*0650*/ FSEL R3, R3, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb03037808 */
/* 0x000fe20004800000 */
/*0660*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0670*/ FSEL R6, R6, 1, !P1 ; /* 0x3f80000006067808 */
/* 0x000fc40004800000 */
/*0680*/ FSEL R5, -R5, -0.4999999701976776123, !P1 ; /* 0xbeffffff05057808 */
/* 0x000fc60004800100 */
/*0690*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff041424 */
/* 0x000fc800078e00ff */
/*06a0*/ @P1 FFMA R2, R7, R4, -0.0013887860113754868507 ; /* 0xbab607ed07021423 */
/* 0x000fe40000000004 */
/*06b0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e0209 */
/*06c0*/ FFMA R2, R7.reuse, R2, R3 ; /* 0x0000000207027223 */
/* 0x040fe40000000003 */
/*06d0*/ FFMA R3, R6, R7, RZ ; /* 0x0000000706037223 */
/* 0x000fe400000000ff */
/*06e0*/ FFMA R2, R7, R2, R5 ; /* 0x0000000207027223 */
/* 0x000fc80000000005 */
/*06f0*/ FFMA R3, R2, R3, R6 ; /* 0x0000000302037223 */
/* 0x000fc80000000006 */
/*0700*/ @P0 FFMA R3, R3, -1, RZ ; /* 0xbf80000003030823 */
/* 0x000fca00000000ff */
/*0710*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101906 */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0740*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0000 */
/*0750*/ @!P0 BRA 0x860 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0760*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*0770*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff028424 */
/* 0x000fe200078e00ff */
/*0780*/ @!P0 BRA 0x860 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0790*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*07a0*/ @P0 FADD.FTZ R2, R0, 1 ; /* 0x3f80000000020421 */
/* 0x000fe20000010000 */
/*07b0*/ @P0 BRA 0x860 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*07c0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*07d0*/ @P0 FFMA R3, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000030823 */
/* 0x000fc800000000ff */
/*07e0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*07f0*/ @P0 FMUL.FTZ R4, R3, R2 ; /* 0x0000000203040220 */
/* 0x001fe40000410000 */
/*0800*/ @P0 FMUL.FTZ R6, R2, 0.5 ; /* 0x3f00000002060820 */
/* 0x000fe40000410000 */
/*0810*/ @P0 FADD.FTZ R5, -R4.reuse, -RZ ; /* 0x800000ff04050221 */
/* 0x040fe40000010100 */
/*0820*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff028224 */
/* 0x000fe400078e0000 */
/*0830*/ @P0 FFMA R5, R4, R5, R3 ; /* 0x0000000504050223 */
/* 0x000fc80000000003 */
/*0840*/ @P0 FFMA R5, R5, R6, R4 ; /* 0x0000000605050223 */
/* 0x000fc80000000004 */
/*0850*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fca0000410000 */
/*0860*/ MOV R9, R2 ; /* 0x0000000200097202 */
/* 0x000fe20000000f00 */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0007 */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0890*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff76002007950 */
/* 0x000fea0003c3ffff */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
float x = step * index;
tab[index] = sinf(sqrtf(x));
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
cudaError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N;
float *hT = (float *)malloc(size);
float *hRes = (float *)malloc(size);
if (hT == NULL || hRes == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
tcpu = -wtime();
tabfun_host(hT, step, N);
tcpu += wtime();
/* Allocate vectors on device */
float *dT = NULL;
if (cudaMalloc((void **)&dT, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n",
blocksPerGrid, threadsPerBlock);
tgpu = -wtime();
tabfun<<<blocksPerGrid, threadsPerBlock>>>(dT, step, N);
cudaDeviceSynchronize();
tgpu += wtime();
if ( (err = cudaGetLastError()) != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (cudaMemcpy(hRes, dT, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
float d = fabs(hT[i] - hRes[i]);
printf("%d: %f\n", i, d);
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
cudaFree(dT);
free(hT);
free(hRes);
cudaDeviceReset();
return 0;
} | .file "tmpxft_000eb418_00000000-6_tabfun.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11tabfun_hostPffi
.type _Z11tabfun_hostPffi, @function
_Z11tabfun_hostPffi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movss %xmm0, 12(%rsp)
testl %esi, %esi
jle .L3
movq %rdi, %r12
movslq %esi, %rbp
movl $0, %ebx
movl $0x00000000, %r13d
.L8:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss 12(%rsp), %xmm0
movd %r13d, %xmm2
ucomiss %xmm0, %xmm2
ja .L11
sqrtss %xmm0, %xmm0
.L7:
call sinf@PLT
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L8
.L3:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call sqrtf@PLT
jmp .L7
.cfi_endproc
.LFE2057:
.size _Z11tabfun_hostPffi, .-_Z11tabfun_hostPffi
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z27__device_stub__Z6tabfunPffiPffi
.type _Z27__device_stub__Z6tabfunPffiPffi, @function
_Z27__device_stub__Z6tabfunPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6tabfunPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z6tabfunPffiPffi, .-_Z27__device_stub__Z6tabfunPffiPffi
.globl _Z6tabfunPffi
.type _Z6tabfunPffi, @function
_Z6tabfunPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6tabfunPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6tabfunPffi, .-_Z6tabfunPffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Allocation error.\n"
.LC4:
.string "Allocation error\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "CUDA kernel launch with %d blocks of %d threads\n"
.align 8
.LC6:
.string "Failed to launch kernel (error code %s)!\n"
.align 8
.LC8:
.string "Device to host copying failed\n"
.section .rodata.str1.1
.LC10:
.string "%d: %f\n"
.LC11:
.string "CPU version (sec.): %.6f\n"
.LC12:
.string "GPU version (sec.): %.6f\n"
.LC13:
.string "Memory ops. (sec.): %.6f\n"
.LC14:
.string "Speedup: %.2f\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Speedup (with mem ops.): %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
testq %r12, %r12
je .L34
movq %rax, %rbp
testq %rax, %rax
je .L34
call _Z5wtimev
movsd %xmm0, 8(%rsp)
movl $1024, %esi
movss .LC3(%rip), %xmm0
movq %r12, %rdi
call _Z11tabfun_hostPffi
call _Z5wtimev
movapd %xmm0, %xmm3
subsd 8(%rsp), %xmm3
movsd %xmm3, 8(%rsp)
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
movl $1024, %ecx
movl $1, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z5wtimev
movsd %xmm0, 16(%rsp)
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L29:
call cudaDeviceSynchronize@PLT
call _Z5wtimev
subsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
call _Z5wtimev
pxor %xmm1, %xmm1
subsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp)
movl $2, %ecx
movl $4096, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L40
call _Z5wtimev
addsd 24(%rsp), %xmm0
movsd %xmm0, 24(%rsp)
movl $0, %ebx
leaq .LC10(%rip), %r13
.L32:
movss (%r12,%rbx,4), %xmm0
subss 0(%rbp,%rbx,4), %xmm0
andps .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L32
movsd 8(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
divsd 16(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm1
addsd 24(%rsp), %xmm1
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $1024, %esi
movss .LC3(%rip), %xmm0
movq 40(%rsp), %rdi
call _Z27__device_stub__Z6tabfunPffiPffi
jmp .L29
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z6tabfunPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6tabfunPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 981668463
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#include <cuda_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
float x = step * index;
tab[index] = sinf(sqrtf(x));
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
cudaError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N;
float *hT = (float *)malloc(size);
float *hRes = (float *)malloc(size);
if (hT == NULL || hRes == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
tcpu = -wtime();
tabfun_host(hT, step, N);
tcpu += wtime();
/* Allocate vectors on device */
float *dT = NULL;
if (cudaMalloc((void **)&dT, size) != cudaSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n",
blocksPerGrid, threadsPerBlock);
tgpu = -wtime();
tabfun<<<blocksPerGrid, threadsPerBlock>>>(dT, step, N);
cudaDeviceSynchronize();
tgpu += wtime();
if ( (err = cudaGetLastError()) != cudaSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (cudaMemcpy(hRes, dT, size, cudaMemcpyDeviceToHost) != cudaSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
float d = fabs(hT[i] - hRes[i]);
printf("%d: %f\n", i, d);
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
cudaFree(dT);
free(hT);
free(hRes);
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
float x = step * index;
tab[index] = sinf(sqrtf(x));
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
hipError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N;
float *hT = (float *)malloc(size);
float *hRes = (float *)malloc(size);
if (hT == NULL || hRes == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
tcpu = -wtime();
tabfun_host(hT, step, N);
tcpu += wtime();
/* Allocate vectors on device */
float *dT = NULL;
if (hipMalloc((void **)&dT, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n",
blocksPerGrid, threadsPerBlock);
tgpu = -wtime();
tabfun<<<blocksPerGrid, threadsPerBlock>>>(dT, step, N);
hipDeviceSynchronize();
tgpu += wtime();
if ( (err = hipGetLastError()) != hipSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (hipMemcpy(hRes, dT, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
float d = fabs(hT[i] - hRes[i]);
printf("%d: %f\n", i, d);
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(dT);
free(hT);
free(hRes);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
float x = step * index;
tab[index] = sinf(sqrtf(x));
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
hipError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N;
float *hT = (float *)malloc(size);
float *hRes = (float *)malloc(size);
if (hT == NULL || hRes == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
tcpu = -wtime();
tabfun_host(hT, step, N);
tcpu += wtime();
/* Allocate vectors on device */
float *dT = NULL;
if (hipMalloc((void **)&dT, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n",
blocksPerGrid, threadsPerBlock);
tgpu = -wtime();
tabfun<<<blocksPerGrid, threadsPerBlock>>>(dT, step, N);
hipDeviceSynchronize();
tgpu += wtime();
if ( (err = hipGetLastError()) != hipSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (hipMemcpy(hRes, dT, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
float d = fabs(hT[i] - hRes[i]);
printf("%d: %f\n", i, d);
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(dT);
free(hT);
free(hRes);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6tabfunPffi
.globl _Z6tabfunPffi
.p2align 8
.type _Z6tabfunPffi,@function
_Z6tabfunPffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x8
v_cvt_f32_i32_e32 v0, v1
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s2, v0
v_mul_f32_e32 v2, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_sqrt_f32_e32 v2, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v0
v_fma_f32 v6, -v4, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v2, v0, vcc_lo
v_and_b32_e32 v2, 0x7fffffff, v0
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_3
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v5, 0
v_and_or_b32 v13, v2, s2, 0x800000
v_lshrrev_b32_e32 v10, 23, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v13, 0xfe5163ab, 0
v_add_nc_u32_e32 v11, 0xffffff88, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v11
v_mad_u64_u32 v[6:7], null, v13, 0x3c439041, v[4:5]
v_cndmask_b32_e64 v12, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v4, v7
v_add_nc_u32_e32 v12, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v13, 0xdb629599, v[4:5]
v_cmp_lt_u32_e64 s2, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s2
v_dual_mov_b32 v4, v8 :: v_dual_cndmask_b32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v12
v_mad_u64_u32 v[8:9], null, v13, 0xf534ddc0, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v14
v_mov_b32_e32 v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v8, v6, vcc_lo
v_mad_u64_u32 v[9:10], null, v13, 0xfc2757d1, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v6, v3, s2
v_mov_b32_e32 v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v13, 0x4e441529, v[4:5]
v_mov_b32_e32 v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v13, 0xa2f9836e, v[4:5]
v_cndmask_b32_e64 v4, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v5, v10, v8 :: v_dual_add_nc_u32 v4, v4, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v11, v11, v9 :: v_dual_cndmask_b32 v10, v12, v10
v_cndmask_b32_e32 v9, v9, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v8, v11, v5, s2
v_cndmask_b32_e64 v10, v10, v11, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v5, v5, v9, s2
v_sub_nc_u32_e32 v11, 32, v4
v_cndmask_b32_e64 v9, v9, v6, s2
v_cndmask_b32_e64 v10, v10, v8, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v8, v8, v5, s3
v_cndmask_b32_e64 v5, v5, v9, s3
v_cndmask_b32_e64 v3, v9, v3, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v10, v8, v11
v_alignbit_b32 v7, v8, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, v12, v10, vcc_lo
v_alignbit_b32 v10, v5, v3, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v7, v8, vcc_lo
v_bfe_u32 v7, v4, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v10, v5, vcc_lo
v_alignbit_b32 v8, v4, v6, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v9, 0, v7
v_alignbit_b32 v6, v6, v5, 30
v_alignbit_b32 v3, v5, v3, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v8, v9
v_xor_b32_e32 v5, v6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v3, v9
v_clz_i32_u32_e32 v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v10, 32, v10
v_sub_nc_u32_e32 v6, 31, v10
v_lshlrev_b32_e32 v12, 23, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v8, v8, v5, v6
v_alignbit_b32 v3, v5, v3, v6
v_lshrrev_b32_e32 v6, 29, v4
v_alignbit_b32 v5, v8, v3, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v6, 31, v6
v_lshrrev_b32_e32 v8, 9, v8
v_clz_i32_u32_e32 v9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v11, 0.5, v6
v_min_u32_e32 v9, 32, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v11, v11, v12
v_sub_nc_u32_e32 v13, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v3, v5, v3, v13
v_or_b32_e32 v5, v8, v11
v_add_lshl_u32 v8, v9, v10, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v3, 9, v3
v_mul_f32_e32 v9, 0x3fc90fda, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v8
v_fma_f32 v8, v5, 0x3fc90fda, -v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 0x33000000, v3
v_fmamk_f32 v5, v5, 0x33a22168, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v3, v3, v6
v_fmac_f32_e32 v5, 0x3fc90fda, v3
v_lshrrev_b32_e32 v4, 30, v4
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v3, v9, v5 :: v_dual_add_nc_u32 v4, v7, v4
.LBB0_3:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v3, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v4, v3
v_fma_f32 v3, v4, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v3, v4, 0xb3a22168, v3
v_fmamk_f32 v3, v4, 0xa7c234c4, v3
v_cvt_i32_f32_e32 v4, v4
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, v3, v3 :: v_dual_and_b32 v8, 1, v4
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
s_load_b64 s[0:1], s[0:1], 0x0
v_fmaak_f32 v6, s2, v5, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v8
v_lshlrev_b32_e32 v4, 30, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v6, v5, v6, 0xbe2aaa9d
v_fmaak_f32 v7, s3, v5, 0xbab64f3b
v_and_b32_e32 v4, 0x80000000, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v6, v5, v6
v_fmaak_f32 v7, v5, v7, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v3, v3, v6
v_fmaak_f32 v7, v5, v7, 0xbf000004
v_xor_b32_e32 v6, v2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v5, v7, 1.0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v5, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
v_xor3_b32 v3, v6, v4, v3
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6tabfunPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6tabfunPffi, .Lfunc_end0-_Z6tabfunPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6tabfunPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6tabfunPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
const float step = 0.001;
enum {
BLOCK_SIZE = 32,
N = 1024
};
void tabfun_host(float *tab, float step, int n)
{
for (int i = 0; i < n; i++) {
float x = step * i;
tab[i] = sinf(sqrtf(x));
}
}
__global__ void tabfun(float *tab, float step, int n)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < n) {
float x = step * index;
tab[index] = sinf(sqrtf(x));
}
}
double wtime()
{
struct timeval t;
gettimeofday(&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
int main()
{
double tcpu = 0, tgpu = 0, tmem = 0;
hipError_t err;
/* Allocate memory on host */
size_t size = sizeof(float) * N;
float *hT = (float *)malloc(size);
float *hRes = (float *)malloc(size);
if (hT == NULL || hRes == NULL) {
fprintf(stderr, "Allocation error.\n");
exit(EXIT_FAILURE);
}
tcpu = -wtime();
tabfun_host(hT, step, N);
tcpu += wtime();
/* Allocate vectors on device */
float *dT = NULL;
if (hipMalloc((void **)&dT, size) != hipSuccess) {
fprintf(stderr, "Allocation error\n");
exit(EXIT_FAILURE);
}
/* Launch the kernel */
int threadsPerBlock = 1024;
int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
printf("CUDA kernel launch with %d blocks of %d threads\n",
blocksPerGrid, threadsPerBlock);
tgpu = -wtime();
tabfun<<<blocksPerGrid, threadsPerBlock>>>(dT, step, N);
hipDeviceSynchronize();
tgpu += wtime();
if ( (err = hipGetLastError()) != hipSuccess) {
fprintf(stderr, "Failed to launch kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
/* Copy the device vectors to host */
tmem -= wtime();
if (hipMemcpy(hRes, dT, size, hipMemcpyDeviceToHost) != hipSuccess) {
fprintf(stderr, "Device to host copying failed\n");
exit(EXIT_FAILURE);
}
tmem += wtime();
// Verify that the result vector is correct
for (int i = 0; i < N; i++) {
float d = fabs(hT[i] - hRes[i]);
printf("%d: %f\n", i, d);
}
printf("CPU version (sec.): %.6f\n", tcpu);
printf("GPU version (sec.): %.6f\n", tgpu);
printf("Memory ops. (sec.): %.6f\n", tmem);
printf("Speedup: %.2f\n", tcpu / tgpu);
printf("Speedup (with mem ops.): %.2f\n", tcpu / (tgpu + tmem));
hipFree(dT);
free(hT);
free(hRes);
hipDeviceReset();
return 0;
} | .text
.file "tabfun.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11tabfun_hostPffi
.LCPI0_0:
.long 0x00000000 # float 0
.text
.globl _Z11tabfun_hostPffi
.p2align 4, 0x90
.type _Z11tabfun_hostPffi,@function
_Z11tabfun_hostPffi: # @_Z11tabfun_hostPffi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movss %xmm0, 12(%rsp) # 4-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
sqrtss %xmm0, %xmm0
.LBB0_5: # %.lr.ph.split
# in Loop: Header=BB0_2 Depth=1
callq sinf
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
je .LBB0_6
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
ucomiss .LCPI0_0(%rip), %xmm0
jae .LBB0_3
# %bb.4: # %call.sqrt
# in Loop: Header=BB0_2 Depth=1
callq sqrtf
jmp .LBB0_5
.LBB0_6: # %._crit_edge
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11tabfun_hostPffi, .Lfunc_end0-_Z11tabfun_hostPffi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__tabfunPffi # -- Begin function _Z21__device_stub__tabfunPffi
.p2align 4, 0x90
.type _Z21__device_stub__tabfunPffi,@function
_Z21__device_stub__tabfunPffi: # @_Z21__device_stub__tabfunPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6tabfunPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__tabfunPffi, .Lfunc_end1-_Z21__device_stub__tabfunPffi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5wtimev, .Lfunc_end2-_Z5wtimev
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3a83126f # float 0.00100000005
.LCPI3_3:
.long 0x00000000 # float 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
testq %rbx, %rbx
je .LBB3_2
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB3_2
# %bb.4:
xorl %r15d, %r15d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r12
movq 8(%rsp), %r13
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # %call.sqrt
# in Loop: Header=BB3_5 Depth=1
callq sqrtf
.LBB3_8: # %.lr.ph.i.split
# in Loop: Header=BB3_5 Depth=1
callq sinf
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB3_9
.LBB3_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
mulss .LCPI3_0(%rip), %xmm0
ucomiss .LCPI3_3(%rip), %xmm0
jb .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB3_8
.LBB3_9: # %_Z11tabfun_hostPffi.exit
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r15
movq 8(%rsp), %rbp
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.11:
movl $.L.str.2, %edi
movl $1, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 24(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12:
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
movl $981668463, 60(%rsp) # imm = 0x3A83126F
movl $1024, 56(%rsp) # imm = 0x400
leaq 160(%rsp), %rax
movq %rax, (%rsp)
leaq 60(%rsp), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movq %rsp, %r9
movl $_Z6tabfunPffi, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13:
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
callq hipGetLastError
testl %eax, %eax
jne .LBB3_19
# %bb.14:
movq %rbp, 72(%rsp) # 8-byte Spill
movq %r15, 80(%rsp) # 8-byte Spill
movq %r13, 88(%rsp) # 8-byte Spill
movq %r12, 96(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movq 8(%rsp), %r12
movq 48(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_15
# %bb.16:
xorl %r15d, %r15d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r13
movq 8(%rsp), %rbp
.p2align 4, 0x90
.LBB3_17: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r14,%r15,4), %xmm0
andps .LCPI3_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB3_17
# %bb.18:
cvtsi2sd %rbp, %xmm2
movsd .LCPI3_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
cvtsi2sd %r13, %xmm6
addsd %xmm2, %xmm6
cvtsi2sd %r12, %xmm3
mulsd %xmm1, %xmm3
xorps %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2 # 8-byte Folded Reload
cvtsi2sdq 104(%rsp), %xmm4 # 8-byte Folded Reload
addsd %xmm3, %xmm2
mulsd %xmm1, %xmm4
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0 # 8-byte Folded Reload
addsd %xmm4, %xmm0
xorps %xmm3, %xmm3
cvtsi2sdq 40(%rsp), %xmm3 # 8-byte Folded Reload
mulsd %xmm1, %xmm3
xorps %xmm4, %xmm4
cvtsi2sdq 24(%rsp), %xmm4 # 8-byte Folded Reload
addsd %xmm3, %xmm4
subsd %xmm4, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
xorps %xmm3, %xmm3
cvtsi2sdq 72(%rsp), %xmm3 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0 # 8-byte Folded Reload
mulsd %xmm1, %xmm3
addsd %xmm3, %xmm0
xorps %xmm3, %xmm3
cvtsi2sdq 88(%rsp), %xmm3 # 8-byte Folded Reload
mulsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm3, %xmm1
subsd %xmm1, %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorpd %xmm1, %xmm1
subsd %xmm2, %xmm1
addsd %xmm6, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.8, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.9, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd 24(%rsp), %xmm1 # 8-byte Folded Reload
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
jmp .LBB3_3
.LBB3_10:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $17, %esi
jmp .LBB3_3
.LBB3_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_15:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $30, %esi
.LBB3_3:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6tabfunPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6tabfunPffi,@object # @_Z6tabfunPffi
.section .rodata,"a",@progbits
.globl _Z6tabfunPffi
.p2align 3, 0x0
_Z6tabfunPffi:
.quad _Z21__device_stub__tabfunPffi
.size _Z6tabfunPffi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Allocation error.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Allocation error\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA kernel launch with %d blocks of %d threads\n"
.size .L.str.2, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to launch kernel (error code %s)!\n"
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device to host copying failed\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d: %f\n"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU version (sec.): %.6f\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU version (sec.): %.6f\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Memory ops. (sec.): %.6f\n"
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Speedup: %.2f\n"
.size .L.str.9, 15
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Speedup (with mem ops.): %.2f\n"
.size .L.str.10, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6tabfunPffi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__tabfunPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6tabfunPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6tabfunPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x16c], PT ; /* 0x00005b0008007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ I2F R0, R8 ; /* 0x0000000800007306 */
/* 0x000e220000201400 */
/*0080*/ BSSY B0, 0x180 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*0090*/ FMUL R0, R0, c[0x0][0x168] ; /* 0x00005a0000007a20 */
/* 0x001fcc0000400000 */
/*00a0*/ MUFU.RSQ R3, R0 ; /* 0x0000000000037308 */
/* 0x0000620000001400 */
/*00b0*/ IADD3 R2, R0, -0xd000000, RZ ; /* 0xf300000000027810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*00d0*/ @!P0 BRA 0x130 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00e0*/ BSSY B1, 0x120 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*00f0*/ MOV R7, 0x110 ; /* 0x0000011000077802 */
/* 0x000fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x730 ; /* 0x0000062000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x170 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0130*/ FMUL.FTZ R9, R0, R3 ; /* 0x0000000300097220 */
/* 0x003fe40000410000 */
/*0140*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*0150*/ FFMA R0, -R9, R9, R0 ; /* 0x0000000909007223 */
/* 0x000fc80000000100 */
/*0160*/ FFMA R9, R0, R3, R9 ; /* 0x0000000300097223 */
/* 0x000fe40000000009 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ FMUL R0, R9.reuse, 0.63661974668502807617 ; /* 0x3f22f98309007820 */
/* 0x040fe20000400000 */
/*0190*/ FSETP.GE.AND P0, PT, |R9|, 105615, PT ; /* 0x47ce47800900780b */
/* 0x000fe20003f06200 */
/*01a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ BSSY B0, 0x5f0 ; /* 0x0000043000007945 */
/* 0x000fe60003800000 */
/*01c0*/ F2I.NTZ R0, R0 ; /* 0x0000000000007305 */
/* 0x000e300000203100 */
/*01d0*/ I2F R2, R0 ; /* 0x0000000000027306 */
/* 0x001e240000201400 */
/*01e0*/ FFMA R3, R2, -1.5707962512969970703, R9 ; /* 0xbfc90fda02037823 */
/* 0x001fc80000000009 */
/*01f0*/ FFMA R3, R2, -7.5497894158615963534e-08, R3 ; /* 0xb3a2216802037823 */
/* 0x000fc80000000003 */
/*0200*/ FFMA R6, R2, -5.3903029534742383927e-15, R3 ; /* 0xa7c234c502067823 */
/* 0x000fe20000000003 */
/*0210*/ @!P0 BRA 0x5e0 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*0220*/ FSETP.NEU.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f0d200 */
/*0230*/ @!P0 BRA 0x5c0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0240*/ SHF.R.U32.HI R0, RZ, 0x17, R9 ; /* 0x00000017ff007819 */
/* 0x000fe20000011609 */
/*0250*/ IMAD.SHL.U32 R2, R9, 0x100, RZ ; /* 0x0000010009027824 */
/* 0x000fe200078e00ff */
/*0260*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0270*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0280*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe200078ec0ff */
/*0290*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*02a0*/ LOP3.LUT R13, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000020d7812 */
/* 0x000fe400078efcff */
/*02b0*/ IADD3 R10, R0, -0x80, RZ ; /* 0xffffff80000a7810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0001 */
/*02d0*/ SHF.R.U32.HI R12, RZ, 0x5, R10 ; /* 0x00000005ff0c7819 */
/* 0x000fe4000001160a */
/*02e0*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe2000f8e00ff */
/*02f0*/ MOV R5, UR9 ; /* 0x0000000900057c02 */
/* 0x000fca0008000f00 */
/*0300*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*0310*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0320*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0330*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x000fe20003f05270 */
/*0340*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0350*/ IMAD.WIDE.U32 R2, R2, R13, RZ ; /* 0x0000000d02027225 */
/* 0x004fca00078e00ff */
/*0360*/ IADD3 R11, P1, R2, R6, RZ ; /* 0x00000006020b7210 */
/* 0x000fc80007f3e0ff */
/*0370*/ IADD3.X R6, R3, UR4, RZ, P1, !PT ; /* 0x0000000403067c10 */
/* 0x000fe20008ffe4ff */
/*0380*/ STL [R0], R11 ; /* 0x0000000b00007387 */
/* 0x0001e40000100800 */
/*0390*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*03a0*/ @P0 BRA 0x2e0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*03b0*/ LOP3.LUT P0, R7, R10, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0a077812 */
/* 0x000fe2000780c0ff */
/*03c0*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e20000100800 */
/*03d0*/ IADD3 R2, -R12.reuse, 0x4, RZ ; /* 0x000000040c027810 */
/* 0x040fe40007ffe1ff */
/*03e0*/ IADD3 R0, -R12, 0x6, RZ ; /* 0x000000060c007810 */
/* 0x000fca0007ffe1ff */
/*03f0*/ IMAD R10, R0, 0x4, R1 ; /* 0x00000004000a7824 */
/* 0x000fc800078e0201 */
/*0400*/ @P0 IMAD R11, R2, 0x4, R1 ; /* 0x00000004020b0824 */
/* 0x000fe200078e0201 */
/*0410*/ LDL R0, [R10] ; /* 0x000000000a007983 */
/* 0x000ea80000100800 */
/*0420*/ @P0 LDL R5, [R11] ; /* 0x000000000b050983 */
/* 0x000ee80000100800 */
/*0430*/ LDL R3, [R10+-0x4] ; /* 0xfffffc000a037983 */
/* 0x000f220000100800 */
/*0440*/ @P0 IADD3 R2, -R7, 0x20, RZ ; /* 0x0000002007020810 */
/* 0x000fc80007ffe1ff */
/*0450*/ @P0 SHF.R.U32.HI R4, RZ, R2.reuse, R5 ; /* 0x00000002ff040219 */
/* 0x088fe40000011605 */
/*0460*/ @P0 SHF.L.U32 R5, R0, R7.reuse, RZ ; /* 0x0000000700050219 */
/* 0x084fe400000006ff */
/*0470*/ @P0 SHF.R.U32.HI R2, RZ, R2, R3 ; /* 0x00000002ff020219 */
/* 0x010fe40000011603 */
/*0480*/ @P0 SHF.L.U32 R7, R3, R7, RZ ; /* 0x0000000703070219 */
/* 0x000fc600000006ff */
/*0490*/ @P0 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102000824 */
/* 0x000fe400078e0205 */
/*04a0*/ @P0 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104030824 */
/* 0x000fca00078e0207 */
/*04b0*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*04c0*/ SHF.R.U32.HI R7, RZ, 0x1f, R5 ; /* 0x0000001fff077819 */
/* 0x000fc80000011605 */
/*04d0*/ ISETP.NE.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f25270 */
/*04e0*/ SHF.L.U32 R4, R3, 0x2, RZ ; /* 0x0000000203047819 */
/* 0x000fd600000006ff */
/*04f0*/ @P1 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff051212 */
/* 0x000fe400078e33ff */
/*0500*/ @P1 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff041212 */
/* 0x000fc800078e33ff */
/*0510*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e620000301c00 */
/*0520*/ LOP3.LUT P0, R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fe2000780c0ff */
/*0530*/ DMUL R2, R2, c[0x2][0x0] ; /* 0x0080000002027a28 */
/* 0x002e620000000000 */
/*0540*/ LEA.HI R0, R0, R7, RZ, 0x2 ; /* 0x0000000700007211 */
/* 0x000fd200078f10ff */
/*0550*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x002e620000301000 */
/*0560*/ @P1 LOP3.LUT R9, R9, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000009091812 */
/* 0x000fe200078e3cff */
/*0570*/ IMAD.MOV R6, RZ, RZ, -R0 ; /* 0x000000ffff067224 */
/* 0x001fc600078e0a00 */
/*0580*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f25270 */
/*0590*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff000224 */
/* 0x000fc600078e0006 */
/*05a0*/ FSEL R6, R2, -R2, !P1 ; /* 0x8000000202067208 */
/* 0x002fe20004800000 */
/*05b0*/ BRA 0x5e0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*05c0*/ FMUL R6, RZ, R9 ; /* 0x00000009ff067220 */
/* 0x000fe40000400000 */
/*05d0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*05e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05f0*/ LOP3.LUT P1, RZ, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100ff7812 */
/* 0x000fe2000782c0ff */
/*0600*/ IMAD.MOV.U32 R3, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff037424 */
/* 0x000fe200078e00ff */
/*0610*/ MOV R2, 0xb94d4153 ; /* 0xb94d415300027802 */
/* 0x000fe20000000f00 */
/*0620*/ FMUL R7, R6, R6 ; /* 0x0000000606077220 */
/* 0x000fe20000400000 */
/*0630*/ LOP3.LUT P0, RZ, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200ff7812 */
/* 0x000fe2000780c0ff */
/*0640*/ IMAD.MOV.U32 R5, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff057424 */
/* 0x000fe200078e00ff */
/*0650*/ FSEL R3, R3, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb03037808 */
/* 0x000fe20004800000 */
/*0660*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0670*/ FSEL R6, R6, 1, !P1 ; /* 0x3f80000006067808 */
/* 0x000fc40004800000 */
/*0680*/ FSEL R5, -R5, -0.4999999701976776123, !P1 ; /* 0xbeffffff05057808 */
/* 0x000fc60004800100 */
/*0690*/ @P1 IMAD.MOV.U32 R4, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff041424 */
/* 0x000fc800078e00ff */
/*06a0*/ @P1 FFMA R2, R7, R4, -0.0013887860113754868507 ; /* 0xbab607ed07021423 */
/* 0x000fe40000000004 */
/*06b0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fc800078e0209 */
/*06c0*/ FFMA R2, R7.reuse, R2, R3 ; /* 0x0000000207027223 */
/* 0x040fe40000000003 */
/*06d0*/ FFMA R3, R6, R7, RZ ; /* 0x0000000706037223 */
/* 0x000fe400000000ff */
/*06e0*/ FFMA R2, R7, R2, R5 ; /* 0x0000000207027223 */
/* 0x000fc80000000005 */
/*06f0*/ FFMA R3, R2, R3, R6 ; /* 0x0000000302037223 */
/* 0x000fc80000000006 */
/*0700*/ @P0 FFMA R3, R3, -1, RZ ; /* 0xbf80000003030823 */
/* 0x000fca00000000ff */
/*0710*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101906 */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT P0, RZ, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00ff7812 */
/* 0x000fda000780c0ff */
/*0740*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff028224 */
/* 0x000fe200078e0000 */
/*0750*/ @!P0 BRA 0x860 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0760*/ FSETP.GEU.FTZ.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720b */
/* 0x000fda0003f1e000 */
/*0770*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff028424 */
/* 0x000fe200078e00ff */
/*0780*/ @!P0 BRA 0x860 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0790*/ FSETP.GTU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1c200 */
/*07a0*/ @P0 FADD.FTZ R2, R0, 1 ; /* 0x3f80000000020421 */
/* 0x000fe20000010000 */
/*07b0*/ @P0 BRA 0x860 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*07c0*/ FSETP.NEU.FTZ.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f1d200 */
/*07d0*/ @P0 FFMA R3, R0, 1.84467440737095516160e+19, RZ ; /* 0x5f80000000030823 */
/* 0x000fc800000000ff */
/*07e0*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*07f0*/ @P0 FMUL.FTZ R4, R3, R2 ; /* 0x0000000203040220 */
/* 0x001fe40000410000 */
/*0800*/ @P0 FMUL.FTZ R6, R2, 0.5 ; /* 0x3f00000002060820 */
/* 0x000fe40000410000 */
/*0810*/ @P0 FADD.FTZ R5, -R4.reuse, -RZ ; /* 0x800000ff04050221 */
/* 0x040fe40000010100 */
/*0820*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff028224 */
/* 0x000fe400078e0000 */
/*0830*/ @P0 FFMA R5, R4, R5, R3 ; /* 0x0000000504050223 */
/* 0x000fc80000000003 */
/*0840*/ @P0 FFMA R5, R5, R6, R4 ; /* 0x0000000605050223 */
/* 0x000fc80000000004 */
/*0850*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fca0000410000 */
/*0860*/ MOV R9, R2 ; /* 0x0000000200097202 */
/* 0x000fe20000000f00 */
/*0870*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0007 */
/*0880*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0890*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff76002007950 */
/* 0x000fea0003c3ffff */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6tabfunPffi
.globl _Z6tabfunPffi
.p2align 8
.type _Z6tabfunPffi,@function
_Z6tabfunPffi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0xc
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x8
v_cvt_f32_i32_e32 v0, v1
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v0, s2, v0
v_mul_f32_e32 v2, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_sqrt_f32_e32 v2, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, -v3, v2, v0
v_fma_f32 v6, -v4, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v5
v_cndmask_b32_e64 v2, v2, v3, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v6
v_cndmask_b32_e64 v2, v2, v4, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, 0x37800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v2, v0, vcc_lo
v_and_b32_e32 v2, 0x7fffffff, v0
v_cmpx_ngt_f32_e64 0x48000000, |v0|
s_xor_b32 s4, exec_lo, s3
s_cbranch_execz .LBB0_3
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v5, 0
v_and_or_b32 v13, v2, s2, 0x800000
v_lshrrev_b32_e32 v10, 23, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[3:4], null, v13, 0xfe5163ab, 0
v_add_nc_u32_e32 v11, 0xffffff88, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v11
v_mad_u64_u32 v[6:7], null, v13, 0x3c439041, v[4:5]
v_cndmask_b32_e64 v12, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v4, v7
v_add_nc_u32_e32 v12, v12, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v13, 0xdb629599, v[4:5]
v_cmp_lt_u32_e64 s2, 31, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v14, 0, 0xffffffe0, s2
v_dual_mov_b32 v4, v8 :: v_dual_cndmask_b32 v3, v7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v14, v14, v12
v_mad_u64_u32 v[8:9], null, v13, 0xf534ddc0, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v14
v_mov_b32_e32 v4, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v8, v6, vcc_lo
v_mad_u64_u32 v[9:10], null, v13, 0xfc2757d1, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v6, v3, s2
v_mov_b32_e32 v4, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[10:11], null, v13, 0x4e441529, v[4:5]
v_mov_b32_e32 v4, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[11:12], null, v13, 0xa2f9836e, v[4:5]
v_cndmask_b32_e64 v4, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v5, v10, v8 :: v_dual_add_nc_u32 v4, v4, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v11, v11, v9 :: v_dual_cndmask_b32 v10, v12, v10
v_cndmask_b32_e32 v9, v9, v7, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v8, v11, v5, s2
v_cndmask_b32_e64 v10, v10, v11, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v5, v5, v9, s2
v_sub_nc_u32_e32 v11, 32, v4
v_cndmask_b32_e64 v9, v9, v6, s2
v_cndmask_b32_e64 v10, v10, v8, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v8, v8, v5, s3
v_cndmask_b32_e64 v5, v5, v9, s3
v_cndmask_b32_e64 v3, v9, v3, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v12, v10, v8, v11
v_alignbit_b32 v7, v8, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v4, v12, v10, vcc_lo
v_alignbit_b32 v10, v5, v3, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, v7, v8, vcc_lo
v_bfe_u32 v7, v4, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, v10, v5, vcc_lo
v_alignbit_b32 v8, v4, v6, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v9, 0, v7
v_alignbit_b32 v6, v6, v5, 30
v_alignbit_b32 v3, v5, v3, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v8, v8, v9
v_xor_b32_e32 v5, v6, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v3, v3, v9
v_clz_i32_u32_e32 v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v10, 32, v10
v_sub_nc_u32_e32 v6, 31, v10
v_lshlrev_b32_e32 v12, 23, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v8, v8, v5, v6
v_alignbit_b32 v3, v5, v3, v6
v_lshrrev_b32_e32 v6, 29, v4
v_alignbit_b32 v5, v8, v3, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v6, 31, v6
v_lshrrev_b32_e32 v8, 9, v8
v_clz_i32_u32_e32 v9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v11, 0.5, v6
v_min_u32_e32 v9, 32, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v11, v11, v12
v_sub_nc_u32_e32 v13, 31, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v3, v5, v3, v13
v_or_b32_e32 v5, v8, v11
v_add_lshl_u32 v8, v9, v10, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v3, 9, v3
v_mul_f32_e32 v9, 0x3fc90fda, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v8
v_fma_f32 v8, v5, 0x3fc90fda, -v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, 0x33000000, v3
v_fmamk_f32 v5, v5, 0x33a22168, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v3, v3, v6
v_fmac_f32_e32 v5, 0x3fc90fda, v3
v_lshrrev_b32_e32 v4, 30, v4
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v3, v9, v5 :: v_dual_add_nc_u32 v4, v7, v4
.LBB0_3:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v3, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v4, v3
v_fma_f32 v3, v4, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v3, v4, 0xb3a22168, v3
v_fmamk_f32 v3, v4, 0xa7c234c4, v3
v_cvt_i32_f32_e32 v4, v4
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, v3, v3 :: v_dual_and_b32 v8, 1, v4
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
s_load_b64 s[0:1], s[0:1], 0x0
v_fmaak_f32 v6, s2, v5, 0x3c0881c4
v_cmp_eq_u32_e32 vcc_lo, 0, v8
v_lshlrev_b32_e32 v4, 30, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmaak_f32 v6, v5, v6, 0xbe2aaa9d
v_fmaak_f32 v7, s3, v5, 0xbab64f3b
v_and_b32_e32 v4, 0x80000000, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v6, v5, v6
v_fmaak_f32 v7, v5, v7, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v3, v3, v6
v_fmaak_f32 v7, v5, v7, 0xbf000004
v_xor_b32_e32 v6, v2, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v5, v5, v7, 1.0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v5, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
v_xor3_b32 v3, v6, v4, v3
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6tabfunPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6tabfunPffi, .Lfunc_end0-_Z6tabfunPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6tabfunPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6tabfunPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000eb418_00000000-6_tabfun.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11tabfun_hostPffi
.type _Z11tabfun_hostPffi, @function
_Z11tabfun_hostPffi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movss %xmm0, 12(%rsp)
testl %esi, %esi
jle .L3
movq %rdi, %r12
movslq %esi, %rbp
movl $0, %ebx
movl $0x00000000, %r13d
.L8:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss 12(%rsp), %xmm0
movd %r13d, %xmm2
ucomiss %xmm0, %xmm2
ja .L11
sqrtss %xmm0, %xmm0
.L7:
call sinf@PLT
movss %xmm0, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbp, %rbx
jne .L8
.L3:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call sqrtf@PLT
jmp .L7
.cfi_endproc
.LFE2057:
.size _Z11tabfun_hostPffi, .-_Z11tabfun_hostPffi
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2058:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z27__device_stub__Z6tabfunPffiPffi
.type _Z27__device_stub__Z6tabfunPffiPffi, @function
_Z27__device_stub__Z6tabfunPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6tabfunPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z27__device_stub__Z6tabfunPffiPffi, .-_Z27__device_stub__Z6tabfunPffiPffi
.globl _Z6tabfunPffi
.type _Z6tabfunPffi, @function
_Z6tabfunPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z6tabfunPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6tabfunPffi, .-_Z6tabfunPffi
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Allocation error.\n"
.LC4:
.string "Allocation error\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "CUDA kernel launch with %d blocks of %d threads\n"
.align 8
.LC6:
.string "Failed to launch kernel (error code %s)!\n"
.align 8
.LC8:
.string "Device to host copying failed\n"
.section .rodata.str1.1
.LC10:
.string "%d: %f\n"
.LC11:
.string "CPU version (sec.): %.6f\n"
.LC12:
.string "GPU version (sec.): %.6f\n"
.LC13:
.string "Memory ops. (sec.): %.6f\n"
.LC14:
.string "Speedup: %.2f\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "Speedup (with mem ops.): %.2f\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4096, %edi
call malloc@PLT
movq %rax, %r12
movl $4096, %edi
call malloc@PLT
testq %r12, %r12
je .L34
movq %rax, %rbp
testq %rax, %rax
je .L34
call _Z5wtimev
movsd %xmm0, 8(%rsp)
movl $1024, %esi
movss .LC3(%rip), %xmm0
movq %r12, %rdi
call _Z11tabfun_hostPffi
call _Z5wtimev
movapd %xmm0, %xmm3
subsd 8(%rsp), %xmm3
movsd %xmm3, 8(%rsp)
movq $0, 40(%rsp)
leaq 40(%rsp), %rdi
movl $4096, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
movl $1024, %ecx
movl $1, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z5wtimev
movsd %xmm0, 16(%rsp)
movl $1024, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L29:
call cudaDeviceSynchronize@PLT
call _Z5wtimev
subsd 16(%rsp), %xmm0
movsd %xmm0, 16(%rsp)
call cudaGetLastError@PLT
testl %eax, %eax
jne .L39
call _Z5wtimev
pxor %xmm1, %xmm1
subsd %xmm0, %xmm1
movsd %xmm1, 24(%rsp)
movl $2, %ecx
movl $4096, %edx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L40
call _Z5wtimev
addsd 24(%rsp), %xmm0
movsd %xmm0, 24(%rsp)
movl $0, %ebx
leaq .LC10(%rip), %r13
.L32:
movss (%r12,%rbx,4), %xmm0
subss 0(%rbp,%rbx,4), %xmm0
andps .LC9(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1024, %rbx
jne .L32
movsd 8(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm0
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 24(%rsp), %xmm0
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
divsd 16(%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 16(%rsp), %xmm1
addsd 24(%rsp), %xmm1
movsd 8(%rsp), %xmm0
divsd %xmm1, %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L41
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $1024, %esi
movss .LC3(%rip), %xmm0
movq 40(%rsp), %rdi
call _Z27__device_stub__Z6tabfunPffiPffi
jmp .L29
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
leaq .LC8(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z6tabfunPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z6tabfunPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 981668463
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tabfun.hip"
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11tabfun_hostPffi
.LCPI0_0:
.long 0x00000000 # float 0
.text
.globl _Z11tabfun_hostPffi
.p2align 4, 0x90
.type _Z11tabfun_hostPffi,@function
_Z11tabfun_hostPffi: # @_Z11tabfun_hostPffi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $16, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movss %xmm0, 12(%rsp) # 4-byte Spill
testl %esi, %esi
jle .LBB0_6
# %bb.1: # %.lr.ph.preheader
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
sqrtss %xmm0, %xmm0
.LBB0_5: # %.lr.ph.split
# in Loop: Header=BB0_2 Depth=1
callq sinf
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
je .LBB0_6
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
mulss 12(%rsp), %xmm0 # 4-byte Folded Reload
ucomiss .LCPI0_0(%rip), %xmm0
jae .LBB0_3
# %bb.4: # %call.sqrt
# in Loop: Header=BB0_2 Depth=1
callq sqrtf
jmp .LBB0_5
.LBB0_6: # %._crit_edge
addq $16, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11tabfun_hostPffi, .Lfunc_end0-_Z11tabfun_hostPffi
.cfi_endproc
# -- End function
.globl _Z21__device_stub__tabfunPffi # -- Begin function _Z21__device_stub__tabfunPffi
.p2align 4, 0x90
.type _Z21__device_stub__tabfunPffi,@function
_Z21__device_stub__tabfunPffi: # @_Z21__device_stub__tabfunPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6tabfunPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z21__device_stub__tabfunPffi, .Lfunc_end1-_Z21__device_stub__tabfunPffi
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5wtimev, .Lfunc_end2-_Z5wtimev
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x3a83126f # float 0.00100000005
.LCPI3_3:
.long 0x00000000 # float 0
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4096, %edi # imm = 0x1000
callq malloc
movq %rax, %rbx
movl $4096, %edi # imm = 0x1000
callq malloc
testq %rbx, %rbx
je .LBB3_2
# %bb.1:
movq %rax, %r14
testq %rax, %rax
je .LBB3_2
# %bb.4:
xorl %r15d, %r15d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r12
movq 8(%rsp), %r13
jmp .LBB3_5
.p2align 4, 0x90
.LBB3_7: # %call.sqrt
# in Loop: Header=BB3_5 Depth=1
callq sqrtf
.LBB3_8: # %.lr.ph.i.split
# in Loop: Header=BB3_5 Depth=1
callq sinf
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq $1024, %r15 # imm = 0x400
je .LBB3_9
.LBB3_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r15d, %xmm0
mulss .LCPI3_0(%rip), %xmm0
ucomiss .LCPI3_3(%rip), %xmm0
jb .LBB3_7
# %bb.6: # in Loop: Header=BB3_5 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB3_8
.LBB3_9: # %_Z11tabfun_hostPffi.exit
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r15
movq 8(%rsp), %rbp
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
testl %eax, %eax
jne .LBB3_10
# %bb.11:
movl $.L.str.2, %edi
movl $1, %esi
movl $1024, %edx # imm = 0x400
xorl %eax, %eax
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 24(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_13
# %bb.12:
movq 48(%rsp), %rax
movq %rax, 160(%rsp)
movl $981668463, 60(%rsp) # imm = 0x3A83126F
movl $1024, 56(%rsp) # imm = 0x400
leaq 160(%rsp), %rax
movq %rax, (%rsp)
leaq 60(%rsp), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 144(%rsp), %rdi
leaq 128(%rsp), %rsi
leaq 120(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 144(%rsp), %rsi
movl 152(%rsp), %edx
movq 128(%rsp), %rcx
movl 136(%rsp), %r8d
movq %rsp, %r9
movl $_Z6tabfunPffi, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_13:
callq hipDeviceSynchronize
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 32(%rsp) # 8-byte Spill
movq 8(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
callq hipGetLastError
testl %eax, %eax
jne .LBB3_19
# %bb.14:
movq %rbp, 72(%rsp) # 8-byte Spill
movq %r15, 80(%rsp) # 8-byte Spill
movq %r13, 88(%rsp) # 8-byte Spill
movq %r12, 96(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
movq 8(%rsp), %r12
movq 48(%rsp), %rsi
movl $4096, %edx # imm = 0x1000
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_15
# %bb.16:
xorl %r15d, %r15d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r13
movq 8(%rsp), %rbp
.p2align 4, 0x90
.LBB3_17: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
subss (%r14,%r15,4), %xmm0
andps .LCPI3_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB3_17
# %bb.18:
cvtsi2sd %rbp, %xmm2
movsd .LCPI3_2(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm2
cvtsi2sd %r13, %xmm6
addsd %xmm2, %xmm6
cvtsi2sd %r12, %xmm3
mulsd %xmm1, %xmm3
xorps %xmm2, %xmm2
cvtsi2sdq 64(%rsp), %xmm2 # 8-byte Folded Reload
cvtsi2sdq 104(%rsp), %xmm4 # 8-byte Folded Reload
addsd %xmm3, %xmm2
mulsd %xmm1, %xmm4
xorps %xmm0, %xmm0
cvtsi2sdq 32(%rsp), %xmm0 # 8-byte Folded Reload
addsd %xmm4, %xmm0
xorps %xmm3, %xmm3
cvtsi2sdq 40(%rsp), %xmm3 # 8-byte Folded Reload
mulsd %xmm1, %xmm3
xorps %xmm4, %xmm4
cvtsi2sdq 24(%rsp), %xmm4 # 8-byte Folded Reload
addsd %xmm3, %xmm4
subsd %xmm4, %xmm0
movsd %xmm0, 24(%rsp) # 8-byte Spill
xorps %xmm3, %xmm3
cvtsi2sdq 72(%rsp), %xmm3 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sdq 80(%rsp), %xmm0 # 8-byte Folded Reload
mulsd %xmm1, %xmm3
addsd %xmm3, %xmm0
xorps %xmm3, %xmm3
cvtsi2sdq 88(%rsp), %xmm3 # 8-byte Folded Reload
mulsd %xmm1, %xmm3
xorps %xmm1, %xmm1
cvtsi2sdq 96(%rsp), %xmm1 # 8-byte Folded Reload
addsd %xmm3, %xmm1
subsd %xmm1, %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorpd %xmm1, %xmm1
subsd %xmm2, %xmm1
addsd %xmm6, %xmm1
movsd %xmm1, 40(%rsp) # 8-byte Spill
movl $.L.str.6, %edi
movb $1, %al
callq printf
movl $.L.str.7, %edi
movsd 24(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.8, %edi
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd 24(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.9, %edi
movb $1, %al
callq printf
movsd 40(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd 24(%rsp), %xmm1 # 8-byte Folded Reload
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
divsd %xmm1, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movq 48(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_2:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $18, %esi
jmp .LBB3_3
.LBB3_10:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $17, %esi
jmp .LBB3_3
.LBB3_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_15:
movq stderr(%rip), %rcx
movl $.L.str.4, %edi
movl $30, %esi
.LBB3_3:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6tabfunPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6tabfunPffi,@object # @_Z6tabfunPffi
.section .rodata,"a",@progbits
.globl _Z6tabfunPffi
.p2align 3, 0x0
_Z6tabfunPffi:
.quad _Z21__device_stub__tabfunPffi
.size _Z6tabfunPffi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Allocation error.\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Allocation error\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "CUDA kernel launch with %d blocks of %d threads\n"
.size .L.str.2, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to launch kernel (error code %s)!\n"
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Device to host copying failed\n"
.size .L.str.4, 31
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d: %f\n"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "CPU version (sec.): %.6f\n"
.size .L.str.6, 26
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPU version (sec.): %.6f\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Memory ops. (sec.): %.6f\n"
.size .L.str.8, 26
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Speedup: %.2f\n"
.size .L.str.9, 15
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Speedup (with mem ops.): %.2f\n"
.size .L.str.10, 31
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6tabfunPffi"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__tabfunPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6tabfunPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nblocks ) {
x = ( i - 0.5 ) * step;
sum[idx] += 4.0 / ( 1.0 + x * x );
}
}
int main( void ) {
dim3 dimGrid( NUM_BLOCK, 1, 1 );
dim3 dimBlock( NUM_THREAD, 1, 1 );
float *sumHost, *sumDev;
float step = 1.0 / NBIN;
size_t size = NUM_BLOCK * NUM_THREAD * sizeof( float );
sumHost = (float *) malloc( size );
cudaMalloc( (void **) &sumDev, size );
cudaMemset( sumDev, 0, size );
cal_pi <<< dimGrid, dimBlock >>> ( sumDev, NBIN, step, NUM_THREAD, NUM_BLOCK );
cudaMemcpy( sumHost, sumDev, size, cudaMemcpyDeviceToHost );
for( tid = 0; tid < NUM_THREAD * NUM_BLOCK; tid++ )
pi += sumHost[tid];
pi *= step;
printf( "PI = %f\n", pi );
free( sumHost );
cudaFree( sumDev );
return 0;
} | code for sm_80
Function : _Z6cal_piPfifii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0080*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.WIDE R8, R6, R9, c[0x0][0x160] ; /* 0x0000580006087625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x000162000c1e1900 */
/*00b0*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*00c0*/ LOP3.LUT R0, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff007212 */
/* 0x000fe200078e33ff */
/*00d0*/ F2F.F64.F32 R10, c[0x0][0x16c] ; /* 0x00005b00000a7b10 */
/* 0x000e620000201800 */
/*00e0*/ BSSY B0, 0x4a0 ; /* 0x000003b000007945 */
/* 0x000fe40003800000 */
/*00f0*/ IADD3 R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fe20007ffe0ff */
/*0100*/ IMAD R7, RZ, RZ, -UR4 ; /* 0x80000004ff077e24 */
/* 0x000fe2000f8e02ff */
/*0110*/ ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf45070 */
/*0120*/ I2F.U32.RP R4, UR4 ; /* 0x0000000400047d06 */
/* 0x000eb00008209000 */
/*0130*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x004ea40000001000 */
/*0140*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x004fcc0007ffe0ff */
/*0150*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0004e4000021f000 */
/*0160*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x004fe400078e00ff */
/*0170*/ IMAD R7, R7, R3, RZ ; /* 0x0000000307077224 */
/* 0x008fc800078e02ff */
/*0180*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*0190*/ IMAD.HI.U32 R7, R3, R0, RZ ; /* 0x0000000003077227 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*01b0*/ IMAD R0, R3, UR4, R0 ; /* 0x0000000403007c24 */
/* 0x000fca000f8e0200 */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*01d0*/ @P0 IADD3 R0, R0, -UR4, RZ ; /* 0x8000000400000c10 */
/* 0x000fe4000fffe0ff */
/*01e0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.GE.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf26070 */
/*0200*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*0210*/ @!P2 LOP3.LUT R7, RZ, UR4, RZ, 0x33, !PT ; /* 0x00000004ff07ac12 */
/* 0x000fc8000f8e33ff */
/*0220*/ IADD3 R0, R7, 0x1, RZ ; /* 0x0000000107007810 */
/* 0x000fc80007ffe0ff */
/*0230*/ LOP3.LUT P0, R24, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300187812 */
/* 0x000fda000780c0ff */
/*0240*/ @!P0 BRA 0x490 ; /* 0x0000024000008947 */
/* 0x003fea0003800000 */
/*0250*/ I2F.F64 R2, R6 ; /* 0x0000000600027312 */
/* 0x001e220000201c00 */
/*0260*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0270*/ IADD3 R24, R24, -0x1, RZ ; /* 0xffffffff18187810 */
/* 0x000fe20007ffe0ff */
/*0280*/ BSSY B1, 0x440 ; /* 0x000001b000017945 */
/* 0x000fe60003800000 */
/*0290*/ ISETP.NE.AND P1, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f25270 */
/*02a0*/ DADD R2, R2, -0.5 ; /* 0xbfe0000002027429 */
/* 0x001e0c0000000000 */
/*02b0*/ DMUL R2, R10, R2 ; /* 0x000000020a027228 */
/* 0x001e140000000000 */
/*02c0*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e240000301000 */
/*02d0*/ FMUL R0, R2, R2 ; /* 0x0000000202007220 */
/* 0x001fcc0000400000 */
/*02e0*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x000e240000201800 */
/*02f0*/ DADD R12, R12, 1 ; /* 0x3ff000000c0c7429 */
/* 0x001e0c0000000000 */
/*0300*/ MUFU.RCP64H R15, R13 ; /* 0x0000000d000f7308 */
/* 0x001e240000001800 */
/*0310*/ DFMA R16, -R12, R14, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c000000010e */
/*0320*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0330*/ DFMA R16, R14, R16, R14 ; /* 0x000000100e10722b */
/* 0x001e0c000000000e */
/*0340*/ DFMA R14, -R12, R16, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000110 */
/*0350*/ DFMA R14, R16, R14, R16 ; /* 0x0000000e100e722b */
/* 0x001e0c0000000010 */
/*0360*/ DMUL R2, R14, 4 ; /* 0x401000000e027828 */
/* 0x001e0c0000000000 */
/*0370*/ DFMA R16, -R12, R2, 4 ; /* 0x401000000c10742b */
/* 0x001e0c0000000102 */
/*0380*/ DFMA R2, R14, R16, R2 ; /* 0x000000100e02722b */
/* 0x001e140000000002 */
/*0390*/ FFMA R0, RZ, R13, R3 ; /* 0x0000000dff007223 */
/* 0x001fca0000000003 */
/*03a0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*03b0*/ @P0 BRA 0x430 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000d */
/*03d0*/ MOV R4, 0x410 ; /* 0x0000041000047802 */
/* 0x000fe20000000f00 */
/*03e0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x40100000 ; /* 0x40100000ff117424 */
/* 0x000fe400078e00ff */
/*0400*/ CALL.REL.NOINC 0xd20 ; /* 0x0000091000007944 */
/* 0x020fea0003c00000 */
/*0410*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000e */
/*0420*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000f */
/*0430*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0440*/ F2F.F64.F32 R4, R5 ; /* 0x0000000500047310 */
/* 0x020e220000201800 */
/*0450*/ IADD3 R6, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fe2000fffe0ff */
/*0460*/ DADD R2, R4, R2 ; /* 0x0000000004027229 */
/* 0x001e0c0000000002 */
/*0470*/ F2F.F32.F64 R5, R2 ; /* 0x0000000200057310 */
/* 0x0010620000301000 */
/*0480*/ @P1 BRA 0x250 ; /* 0xfffffdc000001947 */
/* 0x000fea000383ffff */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe20003f06070 */
/*04b0*/ BSSY B0, 0xd00 ; /* 0x0000084000007945 */
/* 0x000fd80003800000 */
/*04c0*/ @!P0 BRA 0xcf0 ; /* 0x0000082000008947 */
/* 0x000fea0003800000 */
/*04d0*/ I2F.F64 R2, R6 ; /* 0x0000000600027312 */
/* 0x001e220000201c00 */
/*04e0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*04f0*/ BSSY B1, 0x6a0 ; /* 0x000001a000017945 */
/* 0x000fe20003800000 */
/*0500*/ DADD R2, R2, -0.5 ; /* 0xbfe0000002027429 */
/* 0x001e0c0000000000 */
/*0510*/ DMUL R2, R10, R2 ; /* 0x000000020a027228 */
/* 0x001e140000000000 */
/*0520*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e240000301000 */
/*0530*/ FMUL R0, R2, R2 ; /* 0x0000000202007220 */
/* 0x001fcc0000400000 */
/*0540*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x000e240000201800 */
/*0550*/ DADD R12, R12, 1 ; /* 0x3ff000000c0c7429 */
/* 0x001e0c0000000000 */
/*0560*/ MUFU.RCP64H R15, R13 ; /* 0x0000000d000f7308 */
/* 0x001e240000001800 */
/*0570*/ DFMA R16, -R12, R14, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c000000010e */
/*0580*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0590*/ DFMA R16, R14, R16, R14 ; /* 0x000000100e10722b */
/* 0x001e0c000000000e */
/*05a0*/ DFMA R14, -R12, R16, 1 ; /* 0x3ff000000c0e742b */
/* 0x001e0c0000000110 */
/*05b0*/ DFMA R14, R16, R14, R16 ; /* 0x0000000e100e722b */
/* 0x001e0c0000000010 */
/*05c0*/ DMUL R2, R14, 4 ; /* 0x401000000e027828 */
/* 0x001e0c0000000000 */
/*05d0*/ DFMA R16, -R12, R2, 4 ; /* 0x401000000c10742b */
/* 0x001e0c0000000102 */
/*05e0*/ DFMA R2, R14, R16, R2 ; /* 0x000000100e02722b */
/* 0x001e140000000002 */
/*05f0*/ FFMA R0, RZ, R13, R3 ; /* 0x0000000dff007223 */
/* 0x001fca0000000003 */
/*0600*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0610*/ @P0 BRA 0x690 ; /* 0x0000007000000947 */
/* 0x002fea0003800000 */
/*0620*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000d */
/*0630*/ MOV R4, 0x670 ; /* 0x0000067000047802 */
/* 0x000fe20000000f00 */
/*0640*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0650*/ IMAD.MOV.U32 R17, RZ, RZ, 0x40100000 ; /* 0x40100000ff117424 */
/* 0x000fe400078e00ff */
/*0660*/ CALL.REL.NOINC 0xd20 ; /* 0x000006b000007944 */
/* 0x022fea0003c00000 */
/*0670*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000e */
/*0680*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000f */
/*0690*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*06a0*/ IADD3 R6, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fe2000fffe0ff */
/*06b0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*06c0*/ F2F.F64.F32 R4, R5 ; /* 0x0000000500047310 */
/* 0x022e220000201800 */
/*06d0*/ BSSY B1, 0x890 ; /* 0x000001b000017945 */
/* 0x000fee0003800000 */
/*06e0*/ I2F.F64 R12, R6 ; /* 0x00000006000c7312 */
/* 0x000e620000201c00 */
/*06f0*/ DADD R2, R4, R2 ; /* 0x0000000004027229 */
/* 0x001e0e0000000002 */
/*0700*/ F2F.F32.F64 R7, R2 ; /* 0x0000000200077310 */
/* 0x001fe20000301000 */
/*0710*/ DADD R12, R12, -0.5 ; /* 0xbfe000000c0c7429 */
/* 0x002e0c0000000000 */
/*0720*/ DMUL R14, R10, R12 ; /* 0x0000000c0a0e7228 */
/* 0x001e140000000000 */
/*0730*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e240000301000 */
/*0740*/ FMUL R0, R14, R14 ; /* 0x0000000e0e007220 */
/* 0x001fcc0000400000 */
/*0750*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x000e240000201800 */
/*0760*/ DADD R12, R12, 1 ; /* 0x3ff000000c0c7429 */
/* 0x001e0c0000000000 */
/*0770*/ MUFU.RCP64H R17, R13 ; /* 0x0000000d00117308 */
/* 0x001e240000001800 */
/*0780*/ DFMA R18, -R12, R16, 1 ; /* 0x3ff000000c12742b */
/* 0x001e0c0000000110 */
/*0790*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*07a0*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x001e0c0000000010 */
/*07b0*/ DFMA R16, -R12, R18, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c0000000112 */
/*07c0*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e0c0000000012 */
/*07d0*/ DMUL R14, R16, 4 ; /* 0x40100000100e7828 */
/* 0x001e0c0000000000 */
/*07e0*/ DFMA R18, -R12, R14, 4 ; /* 0x401000000c12742b */
/* 0x001e0c000000010e */
/*07f0*/ DFMA R14, R16, R18, R14 ; /* 0x00000012100e722b */
/* 0x001e14000000000e */
/*0800*/ FFMA R0, RZ, R13, R15 ; /* 0x0000000dff007223 */
/* 0x001fca000000000f */
/*0810*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0820*/ @P0 BRA 0x880 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0830*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000d */
/*0840*/ MOV R4, 0x880 ; /* 0x0000088000047802 */
/* 0x000fe20000000f00 */
/*0850*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0860*/ IMAD.MOV.U32 R17, RZ, RZ, 0x40100000 ; /* 0x40100000ff117424 */
/* 0x000fe400078e00ff */
/*0870*/ CALL.REL.NOINC 0xd20 ; /* 0x000004a000007944 */
/* 0x000fea0003c00000 */
/*0880*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0890*/ IADD3 R6, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fe2000fffe0ff */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*08b0*/ BSSY B1, 0xaa0 ; /* 0x000001e000017945 */
/* 0x000fe40003800000 */
/*08c0*/ I2F.F64 R2, R6 ; /* 0x0000000600027312 */
/* 0x000e240000201c00 */
/*08d0*/ DADD R2, R2, -0.5 ; /* 0xbfe0000002027429 */
/* 0x001e0c0000000000 */
/*08e0*/ DMUL R2, R10, R2 ; /* 0x000000020a027228 */
/* 0x001e140000000000 */
/*08f0*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x001e240000301000 */
/*0900*/ FMUL R0, R2, R2 ; /* 0x0000000202007220 */
/* 0x001fcc0000400000 */
/*0910*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x000e240000201800 */
/*0920*/ DADD R12, R12, 1 ; /* 0x3ff000000c0c7429 */
/* 0x001e0c0000000000 */
/*0930*/ MUFU.RCP64H R5, R13 ; /* 0x0000000d00057308 */
/* 0x001e240000001800 */
/*0940*/ DFMA R16, -R12, R4, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c0000000104 */
/*0950*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0960*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e0c0000000004 */
/*0970*/ DFMA R4, -R12, R16, 1 ; /* 0x3ff000000c04742b */
/* 0x001e0c0000000110 */
/*0980*/ DFMA R16, R16, R4, R16 ; /* 0x000000041010722b */
/* 0x0010480000000010 */
/*0990*/ F2F.F64.F32 R4, R7 ; /* 0x0000000700047310 */
/* 0x001e240000201800 */
/*09a0*/ DMUL R2, R16, 4 ; /* 0x4010000010027828 */
/* 0x002e4c0000000000 */
/*09b0*/ DFMA R18, -R12, R2, 4 ; /* 0x401000000c12742b */
/* 0x002e4c0000000102 */
/*09c0*/ DFMA R2, R16, R18, R2 ; /* 0x000000121002722b */
/* 0x002e480000000002 */
/*09d0*/ DADD R4, R4, R14 ; /* 0x0000000004047229 */
/* 0x001e0c000000000e */
/*09e0*/ FFMA R0, RZ, R13, R3 ; /* 0x0000000dff007223 */
/* 0x002fc80000000003 */
/*09f0*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x0010620000301000 */
/*0a00*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0a10*/ @P0 BRA 0xa90 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0a20*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x001fe200078e000d */
/*0a30*/ MOV R4, 0xa70 ; /* 0x00000a7000047802 */
/* 0x000fe20000000f00 */
/*0a40*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0a50*/ IMAD.MOV.U32 R17, RZ, RZ, 0x40100000 ; /* 0x40100000ff117424 */
/* 0x000fe400078e00ff */
/*0a60*/ CALL.REL.NOINC 0xd20 ; /* 0x000002b000007944 */
/* 0x002fea0003c00000 */
/*0a70*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000e */
/*0a80*/ IMAD.MOV.U32 R3, RZ, RZ, R15 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000f */
/*0a90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x001fea0003800000 */
/*0aa0*/ IADD3 R6, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fe2000fffe0ff */
/*0ab0*/ IMAD.MOV.U32 R16, RZ, RZ, 0x1 ; /* 0x00000001ff107424 */
/* 0x000fe200078e00ff */
/*0ac0*/ F2F.F64.F32 R4, R5 ; /* 0x0000000500047310 */
/* 0x002e220000201800 */
/*0ad0*/ BSSY B1, 0xc90 ; /* 0x000001b000017945 */
/* 0x000fee0003800000 */
/*0ae0*/ I2F.F64 R12, R6 ; /* 0x00000006000c7312 */
/* 0x000e620000201c00 */
/*0af0*/ DADD R2, R4, R2 ; /* 0x0000000004027229 */
/* 0x001e0e0000000002 */
/*0b00*/ F2F.F32.F64 R7, R2 ; /* 0x0000000200077310 */
/* 0x001fe20000301000 */
/*0b10*/ DADD R12, R12, -0.5 ; /* 0xbfe000000c0c7429 */
/* 0x002e0c0000000000 */
/*0b20*/ DMUL R14, R10, R12 ; /* 0x0000000c0a0e7228 */
/* 0x001e140000000000 */
/*0b30*/ F2F.F32.F64 R14, R14 ; /* 0x0000000e000e7310 */
/* 0x001e240000301000 */
/*0b40*/ FMUL R0, R14, R14 ; /* 0x0000000e0e007220 */
/* 0x001fcc0000400000 */
/*0b50*/ F2F.F64.F32 R12, R0 ; /* 0x00000000000c7310 */
/* 0x000e240000201800 */
/*0b60*/ DADD R12, R12, 1 ; /* 0x3ff000000c0c7429 */
/* 0x001e0c0000000000 */
/*0b70*/ MUFU.RCP64H R17, R13 ; /* 0x0000000d00117308 */
/* 0x001e240000001800 */
/*0b80*/ DFMA R18, -R12, R16, 1 ; /* 0x3ff000000c12742b */
/* 0x001e0c0000000110 */
/*0b90*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*0ba0*/ DFMA R18, R16, R18, R16 ; /* 0x000000121012722b */
/* 0x001e0c0000000010 */
/*0bb0*/ DFMA R16, -R12, R18, 1 ; /* 0x3ff000000c10742b */
/* 0x001e0c0000000112 */
/*0bc0*/ DFMA R16, R18, R16, R18 ; /* 0x000000101210722b */
/* 0x001e0c0000000012 */
/*0bd0*/ DMUL R14, R16, 4 ; /* 0x40100000100e7828 */
/* 0x001e0c0000000000 */
/*0be0*/ DFMA R18, -R12, R14, 4 ; /* 0x401000000c12742b */
/* 0x001e0c000000010e */
/*0bf0*/ DFMA R14, R16, R18, R14 ; /* 0x00000012100e722b */
/* 0x001e14000000000e */
/*0c00*/ FFMA R0, RZ, R13, R15 ; /* 0x0000000dff007223 */
/* 0x001fca000000000f */
/*0c10*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*0c20*/ @P0 BRA 0xc80 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0c30*/ IMAD.MOV.U32 R15, RZ, RZ, R13 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e000d */
/*0c40*/ MOV R4, 0xc80 ; /* 0x00000c8000047802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0c60*/ IMAD.MOV.U32 R17, RZ, RZ, 0x40100000 ; /* 0x40100000ff117424 */
/* 0x000fe400078e00ff */
/*0c70*/ CALL.REL.NOINC 0xd20 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0c80*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0c90*/ F2F.F64.F32 R2, R7 ; /* 0x0000000700027310 */
/* 0x000e220000201800 */
/*0ca0*/ IADD3 R6, R6, UR4, RZ ; /* 0x0000000406067c10 */
/* 0x000fc8000fffe0ff */
/*0cb0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x168], PT ; /* 0x00005a0006007a0c */
/* 0x000fe20003f06270 */
/*0cc0*/ DADD R2, R2, R14 ; /* 0x0000000002027229 */
/* 0x001e0c000000000e */
/*0cd0*/ F2F.F32.F64 R5, R2 ; /* 0x0000000200057310 */
/* 0x00106c0000301000 */
/*0ce0*/ @!P0 BRA 0x4d0 ; /* 0xfffff7e000008947 */
/* 0x000fea000383ffff */
/*0cf0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d00*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x022fe2000c101906 */
/*0d10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d20*/ FSETP.GEU.AND P0, PT, |R15|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x040fe20003f0e200 */
/*0d30*/ IMAD.MOV.U32 R14, RZ, RZ, R12 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e000c */
/*0d40*/ LOP3.LUT R13, R15.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff0f0d7812 */
/* 0x040fe200078ec0ff */
/*0d50*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0d60*/ LOP3.LUT R26, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f1a7812 */
/* 0x000fe200078ec0ff */
/*0d70*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff027424 */
/* 0x000fe200078e00ff */
/*0d80*/ LOP3.LUT R13, R13, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff000000d0d7812 */
/* 0x000fc400078efcff */
/*0d90*/ LOP3.LUT R3, R17, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000011037812 */
/* 0x000fc800078ec0ff */
/*0da0*/ ISETP.GE.U32.AND P2, PT, R3, R26, PT ; /* 0x0000001a0300720c */
/* 0x000fe20003f46070 */
/*0db0*/ @!P0 DMUL R12, R14, 8.98846567431157953865e+307 ; /* 0x7fe000000e0c8828 */
/* 0x000e220000000000 */
/*0dc0*/ IMAD.MOV.U32 R0, RZ, RZ, R3 ; /* 0x000000ffff007224 */
/* 0x000fca00078e0003 */
/*0dd0*/ MUFU.RCP64H R19, R13 ; /* 0x0000000d00137308 */
/* 0x001e240000001800 */
/*0de0*/ DFMA R20, R18, -R12, 1 ; /* 0x3ff000001214742b */
/* 0x001e0c000000080c */
/*0df0*/ DFMA R20, R20, R20, R20 ; /* 0x000000141414722b */
/* 0x001e0c0000000014 */
/*0e00*/ DFMA R20, R18, R20, R18 ; /* 0x000000141214722b */
/* 0x0010640000000012 */
/*0e10*/ SEL R19, R2, 0x63400000, !P2 ; /* 0x6340000002137807 */
/* 0x001fe20005000000 */
/*0e20*/ IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0010 */
/*0e30*/ FSETP.GEU.AND P2, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x000fe40003f4e200 */
/*0e40*/ DFMA R28, R20, -R12, 1 ; /* 0x3ff00000141c742b */
/* 0x002e22000000080c */
/*0e50*/ LOP3.LUT R19, R19, 0x800fffff, R17, 0xf8, !PT ; /* 0x800fffff13137812 */
/* 0x000fca00078ef811 */
/*0e60*/ DFMA R28, R20, R28, R20 ; /* 0x0000001c141c722b */
/* 0x00104a0000000014 */
/*0e70*/ @P2 BRA 0xf00 ; /* 0x0000008000002947 */
/* 0x000fea0003800000 */
/*0e80*/ LOP3.LUT R0, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f007812 */
/* 0x003fe200078ec0ff */
/*0e90*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc600078e00ff */
/*0ea0*/ ISETP.GE.U32.AND P2, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fc80003f46070 */
/*0eb0*/ SEL R21, R2, 0x63400000, !P2 ; /* 0x6340000002157807 */
/* 0x000fc80005000000 */
/*0ec0*/ LOP3.LUT R21, R21, 0x80000000, R17, 0xf8, !PT ; /* 0x8000000015157812 */
/* 0x000fc800078ef811 */
/*0ed0*/ LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x0010000015157812 */
/* 0x000fcc00078efcff */
/*0ee0*/ DFMA R18, R18, 2, -R20 ; /* 0x400000001212782b */
/* 0x000e140000000814 */
/*0ef0*/ LOP3.LUT R0, R19, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000013007812 */
/* 0x001fe400078ec0ff */
/*0f00*/ DMUL R20, R28, R18 ; /* 0x000000121c147228 */
/* 0x003e220000000000 */
/*0f10*/ @!P0 LOP3.LUT R26, R13, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000d1a8812 */
/* 0x000fe200078ec0ff */
/*0f20*/ BSSY B2, 0x12c0 ; /* 0x0000039000027945 */
/* 0x000fe80003800000 */
/*0f30*/ DFMA R22, R20, -R12, R18 ; /* 0x8000000c1416722b */
/* 0x001e0c0000000012 */
/*0f40*/ DFMA R22, R28, R22, R20 ; /* 0x000000161c16722b */
/* 0x0010640000000014 */
/*0f50*/ IADD3 R20, R0, -0x1, RZ ; /* 0xffffffff00147810 */
/* 0x001fe40007ffe0ff */
/*0f60*/ IADD3 R21, R26, -0x1, RZ ; /* 0xffffffff1a157810 */
/* 0x000fe40007ffe0ff */
/*0f70*/ ISETP.GT.U32.AND P0, PT, R20, 0x7feffffe, PT ; /* 0x7feffffe1400780c */
/* 0x000fc80003f04070 */
/*0f80*/ ISETP.GT.U32.OR P0, PT, R21, 0x7feffffe, P0 ; /* 0x7feffffe1500780c */
/* 0x000fda0000704470 */
/*0f90*/ @P0 BRA 0x1160 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0fa0*/ LOP3.LUT R16, R15, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000f107812 */
/* 0x002fc800078ec0ff */
/*0fb0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, R16, PT ; /* 0x000000100300720c */
/* 0x040fe20003f06070 */
/*0fc0*/ IMAD.IADD R0, R3, 0x1, -R16 ; /* 0x0000000103007824 */
/* 0x000fe400078e0a10 */
/*0fd0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*0fe0*/ SEL R3, R2, 0x63400000, !P0 ; /* 0x6340000002037807 */
/* 0x000fe40004000000 */
/*0ff0*/ IMNMX R0, R0, -0x46a00000, !PT ; /* 0xb960000000007817 */
/* 0x000fc80007800200 */
/*1000*/ IMNMX R0, R0, 0x46a00000, PT ; /* 0x46a0000000007817 */
/* 0x000fca0003800200 */
/*1010*/ IMAD.IADD R0, R0, 0x1, -R3 ; /* 0x0000000100007824 */
/* 0x000fca00078e0a03 */
/*1020*/ IADD3 R17, R0, 0x7fe00000, RZ ; /* 0x7fe0000000117810 */
/* 0x000fcc0007ffe0ff */
/*1030*/ DMUL R2, R22, R16 ; /* 0x0000001016027228 */
/* 0x000e140000000000 */
/*1040*/ FSETP.GTU.AND P0, PT, |R3|, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x001fda0003f0c200 */
/*1050*/ @P0 BRA 0x12b0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*1060*/ DFMA R12, R22, -R12, R18 ; /* 0x8000000c160c722b */
/* 0x000e220000000012 */
/*1070*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fd200078e00ff */
/*1080*/ FSETP.NEU.AND P0, PT, R13.reuse, RZ, PT ; /* 0x000000ff0d00720b */
/* 0x041fe40003f0d000 */
/*1090*/ LOP3.LUT R15, R13, 0x80000000, R15, 0x48, !PT ; /* 0x800000000d0f7812 */
/* 0x000fc800078e480f */
/*10a0*/ LOP3.LUT R17, R15, R17, RZ, 0xfc, !PT ; /* 0x000000110f117212 */
/* 0x000fce00078efcff */
/*10b0*/ @!P0 BRA 0x12b0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*10c0*/ IMAD.MOV R13, RZ, RZ, -R0 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a00 */
/*10d0*/ DMUL.RP R16, R22, R16 ; /* 0x0000001016107228 */
/* 0x000e220000008000 */
/*10e0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fcc00078e00ff */
/*10f0*/ DFMA R12, R2, -R12, R22 ; /* 0x8000000c020c722b */
/* 0x000e460000000016 */
/*1100*/ LOP3.LUT R15, R17, R15, RZ, 0x3c, !PT ; /* 0x0000000f110f7212 */
/* 0x001fc600078e3cff */
/*1110*/ IADD3 R12, -R0, -0x43300000, RZ ; /* 0xbcd00000000c7810 */
/* 0x002fc80007ffe1ff */
/*1120*/ FSETP.NEU.AND P0, PT, |R13|, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc80003f0d200 */
/*1130*/ FSEL R2, R16, R2, !P0 ; /* 0x0000000210027208 */
/* 0x000fe40004000000 */
/*1140*/ FSEL R3, R15, R3, !P0 ; /* 0x000000030f037208 */
/* 0x000fe20004000000 */
/*1150*/ BRA 0x12b0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*1160*/ DSETP.NAN.AND P0, PT, R16, R16, PT ; /* 0x000000101000722a */
/* 0x002e1c0003f08000 */
/*1170*/ @P0 BRA 0x1290 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*1180*/ DSETP.NAN.AND P0, PT, R14, R14, PT ; /* 0x0000000e0e00722a */
/* 0x000e1c0003f08000 */
/*1190*/ @P0 BRA 0x1260 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*11a0*/ ISETP.NE.AND P0, PT, R0, R26, PT ; /* 0x0000001a0000720c */
/* 0x000fe20003f05270 */
/*11b0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe400078e00ff */
/*11c0*/ IMAD.MOV.U32 R3, RZ, RZ, -0x80000 ; /* 0xfff80000ff037424 */
/* 0x000fd400078e00ff */
/*11d0*/ @!P0 BRA 0x12b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*11e0*/ ISETP.NE.AND P0, PT, R0, 0x7ff00000, PT ; /* 0x7ff000000000780c */
/* 0x000fe40003f05270 */
/*11f0*/ LOP3.LUT R3, R17, 0x80000000, R15, 0x48, !PT ; /* 0x8000000011037812 */
/* 0x000fe400078e480f */
/*1200*/ ISETP.EQ.OR P0, PT, R26, RZ, !P0 ; /* 0x000000ff1a00720c */
/* 0x000fda0004702670 */
/*1210*/ @P0 LOP3.LUT R0, R3, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000003000812 */
/* 0x000fe200078efcff */
/*1220*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff028224 */
/* 0x000fe400078e00ff */
/*1230*/ @P0 IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff020224 */
/* 0x000fe400078e00ff */
/*1240*/ @P0 IMAD.MOV.U32 R3, RZ, RZ, R0 ; /* 0x000000ffff030224 */
/* 0x000fe200078e0000 */
/*1250*/ BRA 0x12b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*1260*/ LOP3.LUT R3, R15, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000f037812 */
/* 0x000fe200078efcff */
/*1270*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*1280*/ BRA 0x12b0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*1290*/ LOP3.LUT R3, R17, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000011037812 */
/* 0x000fe200078efcff */
/*12a0*/ IMAD.MOV.U32 R2, RZ, RZ, R16 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0010 */
/*12b0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*12c0*/ IMAD.MOV.U32 R14, RZ, RZ, R2 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0002 */
/*12d0*/ IMAD.MOV.U32 R15, RZ, RZ, R3 ; /* 0x000000ffff0f7224 */
/* 0x000fc400078e0003 */
/*12e0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0004 */
/*12f0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*1300*/ RET.REL.NODEC R2 0x0 ; /* 0xffffecf002007950 */
/* 0x000fea0003c3ffff */
/*1310*/ BRA 0x1310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nblocks ) {
x = ( i - 0.5 ) * step;
sum[idx] += 4.0 / ( 1.0 + x * x );
}
}
int main( void ) {
dim3 dimGrid( NUM_BLOCK, 1, 1 );
dim3 dimBlock( NUM_THREAD, 1, 1 );
float *sumHost, *sumDev;
float step = 1.0 / NBIN;
size_t size = NUM_BLOCK * NUM_THREAD * sizeof( float );
sumHost = (float *) malloc( size );
cudaMalloc( (void **) &sumDev, size );
cudaMemset( sumDev, 0, size );
cal_pi <<< dimGrid, dimBlock >>> ( sumDev, NBIN, step, NUM_THREAD, NUM_BLOCK );
cudaMemcpy( sumHost, sumDev, size, cudaMemcpyDeviceToHost );
for( tid = 0; tid < NUM_THREAD * NUM_BLOCK; tid++ )
pi += sumHost[tid];
pi *= step;
printf( "PI = %f\n", pi );
free( sumHost );
cudaFree( sumDev );
return 0;
} | .file "tmpxft_0017a6d1_00000000-6_ej10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6cal_piPfifiiPfifii
.type _Z29__device_stub__Z6cal_piPfifiiPfifii, @function
_Z29__device_stub__Z6cal_piPfifiiPfifii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6cal_piPfifii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6cal_piPfifiiPfifii, .-_Z29__device_stub__Z6cal_piPfifiiPfifii
.globl _Z6cal_piPfifii
.type _Z6cal_piPfifii, @function
_Z6cal_piPfifii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6cal_piPfifiiPfifii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6cal_piPfifii, .-_Z6cal_piPfifii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "PI = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $13, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $192, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $9984, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $9984, %esi
call cudaMalloc@PLT
movl $9984, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $9984, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movss pi(%rip), %xmm0
movq %rbx, %rax
leaq 9984(%rbx), %rdx
.L13:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L13
movl $2496, tid(%rip)
mulss .LC0(%rip), %xmm0
movss %xmm0, pi(%rip)
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $13, %ecx
movl $192, %edx
movss .LC0(%rip), %xmm0
movl $1000000, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6cal_piPfifiiPfifii
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6cal_piPfifii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6cal_piPfifii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl pi
.bss
.align 4
.type pi, @object
.size pi, 4
pi:
.zero 4
.globl tid
.align 4
.type tid, @object
.size tid, 4
tid:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nblocks ) {
x = ( i - 0.5 ) * step;
sum[idx] += 4.0 / ( 1.0 + x * x );
}
}
int main( void ) {
dim3 dimGrid( NUM_BLOCK, 1, 1 );
dim3 dimBlock( NUM_THREAD, 1, 1 );
float *sumHost, *sumDev;
float step = 1.0 / NBIN;
size_t size = NUM_BLOCK * NUM_THREAD * sizeof( float );
sumHost = (float *) malloc( size );
cudaMalloc( (void **) &sumDev, size );
cudaMemset( sumDev, 0, size );
cal_pi <<< dimGrid, dimBlock >>> ( sumDev, NBIN, step, NUM_THREAD, NUM_BLOCK );
cudaMemcpy( sumHost, sumDev, size, cudaMemcpyDeviceToHost );
for( tid = 0; tid < NUM_THREAD * NUM_BLOCK; tid++ )
pi += sumHost[tid];
pi *= step;
printf( "PI = %f\n", pi );
free( sumHost );
cudaFree( sumDev );
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nblocks ) {
x = ( i - 0.5 ) * step;
sum[idx] += 4.0 / ( 1.0 + x * x );
}
}
int main( void ) {
dim3 dimGrid( NUM_BLOCK, 1, 1 );
dim3 dimBlock( NUM_THREAD, 1, 1 );
float *sumHost, *sumDev;
float step = 1.0 / NBIN;
size_t size = NUM_BLOCK * NUM_THREAD * sizeof( float );
sumHost = (float *) malloc( size );
hipMalloc( (void **) &sumDev, size );
hipMemset( sumDev, 0, size );
cal_pi <<< dimGrid, dimBlock >>> ( sumDev, NBIN, step, NUM_THREAD, NUM_BLOCK );
hipMemcpy( sumHost, sumDev, size, hipMemcpyDeviceToHost );
for( tid = 0; tid < NUM_THREAD * NUM_BLOCK; tid++ )
pi += sumHost[tid];
pi *= step;
printf( "PI = %f\n", pi );
free( sumHost );
hipFree( sumDev );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nblocks ) {
x = ( i - 0.5 ) * step;
sum[idx] += 4.0 / ( 1.0 + x * x );
}
}
int main( void ) {
dim3 dimGrid( NUM_BLOCK, 1, 1 );
dim3 dimBlock( NUM_THREAD, 1, 1 );
float *sumHost, *sumDev;
float step = 1.0 / NBIN;
size_t size = NUM_BLOCK * NUM_THREAD * sizeof( float );
sumHost = (float *) malloc( size );
hipMalloc( (void **) &sumDev, size );
hipMemset( sumDev, 0, size );
cal_pi <<< dimGrid, dimBlock >>> ( sumDev, NBIN, step, NUM_THREAD, NUM_BLOCK );
hipMemcpy( sumHost, sumDev, size, hipMemcpyDeviceToHost );
for( tid = 0; tid < NUM_THREAD * NUM_BLOCK; tid++ )
pi += sumHost[tid];
pi *= step;
printf( "PI = %f\n", pi );
free( sumHost );
hipFree( sumDev );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6cal_piPfifii
.globl _Z6cal_piPfifii
.p2align 8
.type _Z6cal_piPfifii,@function
_Z6cal_piPfifii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_load_b64 s[4:5], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0xc
s_load_b32 s1, s[0:1], 0x14
s_mov_b32 s0, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
v_cvt_f64_f32_e32 v[4:5], s6
s_mul_i32 s1, s1, s7
global_load_b32 v0, v[2:3], off
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_cvt_f64_i32_e32 v[6:7], v1
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -0.5
v_mul_f64 v[6:7], v[6:7], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v6, v[6:7]
v_mul_f32_e32 v6, v6, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[6:7], v6
v_add_f64 v[6:7], v[6:7], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], 4.0
v_div_scale_f64 v[14:15], vcc_lo, 4.0, v[6:7], 4.0
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_mul_f64 v[12:13], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[10:11], v0
v_cmp_le_i32_e32 vcc_lo, s2, v1
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[6:7], v[8:9], v[6:7], 4.0
v_add_f64 v[6:7], v[6:7], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v0, v[6:7]
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_2
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s0
global_store_b32 v[2:3], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6cal_piPfifii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6cal_piPfifii, .Lfunc_end0-_Z6cal_piPfifii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6cal_piPfifii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6cal_piPfifii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#define NBIN 1000000
#define NUM_BLOCK 13
#define NUM_THREAD 192
int tid;
float pi = 0;
__global__ void cal_pi( float *sum, int nbin, float step, int nthreads, int nblocks ) {
int i;
float x;
int idx = blockIdx.x * blockDim.x + threadIdx.x;
for( i = idx; i < nbin; i += nthreads * nblocks ) {
x = ( i - 0.5 ) * step;
sum[idx] += 4.0 / ( 1.0 + x * x );
}
}
int main( void ) {
dim3 dimGrid( NUM_BLOCK, 1, 1 );
dim3 dimBlock( NUM_THREAD, 1, 1 );
float *sumHost, *sumDev;
float step = 1.0 / NBIN;
size_t size = NUM_BLOCK * NUM_THREAD * sizeof( float );
sumHost = (float *) malloc( size );
hipMalloc( (void **) &sumDev, size );
hipMemset( sumDev, 0, size );
cal_pi <<< dimGrid, dimBlock >>> ( sumDev, NBIN, step, NUM_THREAD, NUM_BLOCK );
hipMemcpy( sumHost, sumDev, size, hipMemcpyDeviceToHost );
for( tid = 0; tid < NUM_THREAD * NUM_BLOCK; tid++ )
pi += sumHost[tid];
pi *= step;
printf( "PI = %f\n", pi );
free( sumHost );
hipFree( sumDev );
return 0;
} | .text
.file "ej10.hip"
.globl _Z21__device_stub__cal_piPfifii # -- Begin function _Z21__device_stub__cal_piPfifii
.p2align 4, 0x90
.type _Z21__device_stub__cal_piPfifii,@function
_Z21__device_stub__cal_piPfifii: # @_Z21__device_stub__cal_piPfifii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6cal_piPfifii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__cal_piPfifii, .Lfunc_end0-_Z21__device_stub__cal_piPfifii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $9984, %edi # imm = 0x2700
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $9984, %esi # imm = 0x2700
callq hipMalloc
movq (%rsp), %rdi
movl $9984, %edx # imm = 0x2700
xorl %esi, %esi
callq hipMemset
movabsq $4294967309, %rdi # imm = 0x10000000D
leaq 179(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl $1000000, 20(%rsp) # imm = 0xF4240
movl $897988541, 16(%rsp) # imm = 0x358637BD
movl $192, 12(%rsp)
movl $13, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6cal_piPfifii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $9984, %edx # imm = 0x2700
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
movss pi(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $2496, %rax # imm = 0x9C0
jne .LBB1_3
# %bb.4:
movl $2496, tid(%rip) # imm = 0x9C0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, pi(%rip)
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6cal_piPfifii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type tid,@object # @tid
.bss
.globl tid
.p2align 2, 0x0
tid:
.long 0 # 0x0
.size tid, 4
.type pi,@object # @pi
.globl pi
.p2align 2, 0x0
pi:
.long 0x00000000 # float 0
.size pi, 4
.type _Z6cal_piPfifii,@object # @_Z6cal_piPfifii
.section .rodata,"a",@progbits
.globl _Z6cal_piPfifii
.p2align 3, 0x0
_Z6cal_piPfifii:
.quad _Z21__device_stub__cal_piPfifii
.size _Z6cal_piPfifii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PI = %f\n"
.size .L.str, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6cal_piPfifii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__cal_piPfifii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6cal_piPfifii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017a6d1_00000000-6_ej10.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6cal_piPfifiiPfifii
.type _Z29__device_stub__Z6cal_piPfifiiPfifii, @function
_Z29__device_stub__Z6cal_piPfifiiPfifii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6cal_piPfifii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z6cal_piPfifiiPfifii, .-_Z29__device_stub__Z6cal_piPfifiiPfifii
.globl _Z6cal_piPfifii
.type _Z6cal_piPfifii, @function
_Z6cal_piPfifii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6cal_piPfifiiPfifii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6cal_piPfifii, .-_Z6cal_piPfifii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "PI = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $13, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $192, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $9984, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $9984, %esi
call cudaMalloc@PLT
movl $9984, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movq 16(%rsp), %rdi
movl 24(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
movl $2, %ecx
movl $9984, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movss pi(%rip), %xmm0
movq %rbx, %rax
leaq 9984(%rbx), %rdx
.L13:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L13
movl $2496, tid(%rip)
mulss .LC0(%rip), %xmm0
movss %xmm0, pi(%rip)
cvtss2sd %xmm0, %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $13, %ecx
movl $192, %edx
movss .LC0(%rip), %xmm0
movl $1000000, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6cal_piPfifiiPfifii
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z6cal_piPfifii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z6cal_piPfifii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl pi
.bss
.align 4
.type pi, @object
.size pi, 4
pi:
.zero 4
.globl tid
.align 4
.type tid, @object
.size tid, 4
tid:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 897988541
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ej10.hip"
.globl _Z21__device_stub__cal_piPfifii # -- Begin function _Z21__device_stub__cal_piPfifii
.p2align 4, 0x90
.type _Z21__device_stub__cal_piPfifii,@function
_Z21__device_stub__cal_piPfifii: # @_Z21__device_stub__cal_piPfifii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movss %xmm0, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6cal_piPfifii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__cal_piPfifii, .Lfunc_end0-_Z21__device_stub__cal_piPfifii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x358637bd # float 9.99999997E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $128, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -16
movl $9984, %edi # imm = 0x2700
callq malloc
movq %rax, %rbx
movq %rsp, %rdi
movl $9984, %esi # imm = 0x2700
callq hipMalloc
movq (%rsp), %rdi
movl $9984, %edx # imm = 0x2700
xorl %esi, %esi
callq hipMemset
movabsq $4294967309, %rdi # imm = 0x10000000D
leaq 179(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq (%rsp), %rax
movq %rax, 72(%rsp)
movl $1000000, 20(%rsp) # imm = 0xF4240
movl $897988541, 16(%rsp) # imm = 0x358637BD
movl $192, 12(%rsp)
movl $13, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6cal_piPfifii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movl $9984, %edx # imm = 0x2700
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
movss pi(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addss (%rbx,%rax,4), %xmm0
incq %rax
cmpq $2496, %rax # imm = 0x9C0
jne .LBB1_3
# %bb.4:
movl $2496, tid(%rip) # imm = 0x9C0
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, pi(%rip)
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6cal_piPfifii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type tid,@object # @tid
.bss
.globl tid
.p2align 2, 0x0
tid:
.long 0 # 0x0
.size tid, 4
.type pi,@object # @pi
.globl pi
.p2align 2, 0x0
pi:
.long 0x00000000 # float 0
.size pi, 4
.type _Z6cal_piPfifii,@object # @_Z6cal_piPfifii
.section .rodata,"a",@progbits
.globl _Z6cal_piPfifii
.p2align 3, 0x0
_Z6cal_piPfifii:
.quad _Z21__device_stub__cal_piPfifii
.size _Z6cal_piPfifii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "PI = %f\n"
.size .L.str, 9
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6cal_piPfifii"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__cal_piPfifii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6cal_piPfifii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17))
write vec_alloca_2[i_3] (max 0.0 (100.0 - 100.0 * arr_0[i_3] *
arr_1[i_3]))) arr_0 arr_1 v_17
vec_alloca_2
; return vec_alloca_2
}
*/
#include "cuda.h"
#include "cuda_runtime_api.h"
#include <inttypes.h>
extern "C" __global__ void kern7(double* uPow, int32_t arr_0dim9,
double* dPow, int32_t arr_1dim11,
int32_t v_1712, double* output,
int32_t vec_alloca_2dim14)
{
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < v_1712;
i += blockDim.x * gridDim.x) {
double strike_minus_st = 100.0 - 100.0 * uPow[i] * dPow[i];
output[i] = max(0.0, strike_minus_st);
}
}
void gc(void** allocs, int* marks, int nallocs)
{
for (int i = 0; i < nallocs; ++i) {
if (marks[i] == 0) {
cudaFree((char*) allocs[i]);
allocs[i] = NULL;
}
marks[i] = 0;
}
}
void mark(void** allocs, int* marks, int nallocs, void* alloc)
{
for (int i = 0; i < nallocs; ++i) {
if (allocs[i] == alloc) {
marks[i] = 1;
return;
}
}
}
cudaError_t host0(double* arr_01, int32_t arr_0dim2, double* arr_13,
int32_t arr_1dim4, double** ptr_resultparam15,
int32_t* scalar_resultparam16)
{
void* allocs[1];
int marks[1];
int nallocs = 0;
int32_t v_17_5;
double* alloc6 = NULL;
v_17_5 = arr_0dim2 > arr_1dim4 ? arr_1dim4 : arr_0dim2;
if (cudaMalloc(&alloc6, v_17_5 * sizeof(double)) != cudaSuccess)
goto done;
allocs[nallocs] = (void*) alloc6;
marks[nallocs++] = 0;
{
dim3 gdims;
dim3 tdims;
gdims.x = 128;
gdims.y = 1;
gdims.z = 1;
tdims.x = 480;
tdims.y = 1;
tdims.z = 1;
kern7<<<gdims, tdims>>>(arr_01, arr_0dim2, arr_13, arr_1dim4, v_17_5,
alloc6, v_17_5);
}
mark(allocs, marks, nallocs, alloc6);
*ptr_resultparam15 = alloc6;
*scalar_resultparam16 = v_17_5;
done:
gc(allocs, marks, nallocs);
return cudaGetLastError();
} | code for sm_80
Function : kern7
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fc800078e0209 */
/*0090*/ IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*00d0*/ DMUL R4, R2, 100 ; /* 0x4059000002047828 */
/* 0x004ecc0000000000 */
/*00e0*/ DFMA R4, -R4, R6, 100 ; /* 0x405900000404742b */
/* 0x0080640000000106 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x001fc800078e00ff */
/*0100*/ DSETP.MAX.AND P0, P1, RZ, R4, PT ; /* 0x00000004ff00722a */
/* 0x002e08000390f000 */
/*0110*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fe40000000f00 */
/*0120*/ SEL R2, R8, R4, P0 ; /* 0x0000000408027207 */
/* 0x001fe20000000000 */
/*0130*/ IMAD.WIDE R4, R0, R9, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fe200078e0209 */
/*0140*/ FSEL R3, R8, R11, P0 ; /* 0x0000000b08037208 */
/* 0x000fc60000000000 */
/*0150*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fc600078e0200 */
/*0160*/ @P1 LOP3.LUT R3, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b031812 */
/* 0x000fe400078efcff */
/*0170*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc60003f06270 */
/*0180*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0001f4000c101b04 */
/*0190*/ @!P0 BRA 0x70 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17))
write vec_alloca_2[i_3] (max 0.0 (100.0 - 100.0 * arr_0[i_3] *
arr_1[i_3]))) arr_0 arr_1 v_17
vec_alloca_2
; return vec_alloca_2
}
*/
#include "cuda.h"
#include "cuda_runtime_api.h"
#include <inttypes.h>
extern "C" __global__ void kern7(double* uPow, int32_t arr_0dim9,
double* dPow, int32_t arr_1dim11,
int32_t v_1712, double* output,
int32_t vec_alloca_2dim14)
{
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < v_1712;
i += blockDim.x * gridDim.x) {
double strike_minus_st = 100.0 - 100.0 * uPow[i] * dPow[i];
output[i] = max(0.0, strike_minus_st);
}
}
void gc(void** allocs, int* marks, int nallocs)
{
for (int i = 0; i < nallocs; ++i) {
if (marks[i] == 0) {
cudaFree((char*) allocs[i]);
allocs[i] = NULL;
}
marks[i] = 0;
}
}
void mark(void** allocs, int* marks, int nallocs, void* alloc)
{
for (int i = 0; i < nallocs; ++i) {
if (allocs[i] == alloc) {
marks[i] = 1;
return;
}
}
}
cudaError_t host0(double* arr_01, int32_t arr_0dim2, double* arr_13,
int32_t arr_1dim4, double** ptr_resultparam15,
int32_t* scalar_resultparam16)
{
void* allocs[1];
int marks[1];
int nallocs = 0;
int32_t v_17_5;
double* alloc6 = NULL;
v_17_5 = arr_0dim2 > arr_1dim4 ? arr_1dim4 : arr_0dim2;
if (cudaMalloc(&alloc6, v_17_5 * sizeof(double)) != cudaSuccess)
goto done;
allocs[nallocs] = (void*) alloc6;
marks[nallocs++] = 0;
{
dim3 gdims;
dim3 tdims;
gdims.x = 128;
gdims.y = 1;
gdims.z = 1;
tdims.x = 480;
tdims.y = 1;
tdims.z = 1;
kern7<<<gdims, tdims>>>(arr_01, arr_0dim2, arr_13, arr_1dim4, v_17_5,
alloc6, v_17_5);
}
mark(allocs, marks, nallocs, alloc6);
*ptr_resultparam15 = alloc6;
*scalar_resultparam16 = v_17_5;
done:
gc(allocs, marks, nallocs);
return cudaGetLastError();
} | .file "tmpxft_00094b9c_00000000-6_finalPut-hand-simplified.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z2gcPPvPii
.type _Z2gcPPvPii, @function
_Z2gcPPvPii:
.LFB2027:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L9
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbx
movq %rdi, %rbp
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %r13
jmp .L6
.L5:
movl $0, (%r12)
addq $4, %rbx
addq $8, %rbp
cmpq %r13, %rbx
je .L12
.L6:
movq %rbx, %r12
cmpl $0, (%rbx)
jne .L5
movq 0(%rbp), %rdi
call cudaFree@PLT
movq $0, 0(%rbp)
jmp .L5
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2027:
.size _Z2gcPPvPii, .-_Z2gcPPvPii
.globl _Z4markPPvPiiS_
.type _Z4markPPvPiiS_, @function
_Z4markPPvPiiS_:
.LFB2028:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L13
movslq %edx, %rdx
movl $0, %eax
.L16:
cmpq %rcx, (%rdi,%rax,8)
je .L18
addq $1, %rax
cmpq %rdx, %rax
jne .L16
.L13:
ret
.L18:
movl $1, (%rsi,%rax,4)
ret
.cfi_endproc
.LFE2028:
.size _Z4markPPvPiiS_, .-_Z4markPPvPiiS_
.globl _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i
.type _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i, @function
_Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq kern7(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i, .-_Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i
.globl kern7
.type kern7, @function
kern7:
.LFB2055:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size kern7, .-kern7
.globl _Z5host0PdiS_iPS_Pi
.type _Z5host0PdiS_iPS_Pi, @function
_Z5host0PdiS_iPS_Pi:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, %ebx
movq %rdx, %r14
movl %ecx, %ebp
movq %r8, %r13
movq %r9, %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
cmpl %ecx, %esi
movl %ecx, %r15d
cmovle %esi, %r15d
movslq %r15d, %rsi
salq $3, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl $0, %edx
testl %eax, %eax
je .L33
.L28:
leaq 60(%rsp), %rsi
leaq 64(%rsp), %rdi
call _Z2gcPPvPii
call cudaGetLastError@PLT
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L34
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 24(%rsp), %rax
movq %rax, 64(%rsp)
movl $0, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 52(%rsp)
movl $128, 36(%rsp)
movl $480, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L29:
movq 24(%rsp), %rbx
leaq 60(%rsp), %rsi
leaq 64(%rsp), %rdi
movq %rbx, %rcx
movl $1, %edx
call _Z4markPPvPiiS_
movq %rbx, 0(%r13)
movl %r15d, (%r12)
movl $1, %edx
jmp .L28
.L35:
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq %r15
.cfi_def_cfa_offset 160
movq 40(%rsp), %r9
movl %r15d, %r8d
movl %ebp, %ecx
movq %r14, %rdx
movl %ebx, %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2029:
.size _Z5host0PdiS_iPS_Pi, .-_Z5host0PdiS_iPS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kern7"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kern7(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17))
write vec_alloca_2[i_3] (max 0.0 (100.0 - 100.0 * arr_0[i_3] *
arr_1[i_3]))) arr_0 arr_1 v_17
vec_alloca_2
; return vec_alloca_2
}
*/
#include "cuda.h"
#include "cuda_runtime_api.h"
#include <inttypes.h>
extern "C" __global__ void kern7(double* uPow, int32_t arr_0dim9,
double* dPow, int32_t arr_1dim11,
int32_t v_1712, double* output,
int32_t vec_alloca_2dim14)
{
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < v_1712;
i += blockDim.x * gridDim.x) {
double strike_minus_st = 100.0 - 100.0 * uPow[i] * dPow[i];
output[i] = max(0.0, strike_minus_st);
}
}
void gc(void** allocs, int* marks, int nallocs)
{
for (int i = 0; i < nallocs; ++i) {
if (marks[i] == 0) {
cudaFree((char*) allocs[i]);
allocs[i] = NULL;
}
marks[i] = 0;
}
}
void mark(void** allocs, int* marks, int nallocs, void* alloc)
{
for (int i = 0; i < nallocs; ++i) {
if (allocs[i] == alloc) {
marks[i] = 1;
return;
}
}
}
cudaError_t host0(double* arr_01, int32_t arr_0dim2, double* arr_13,
int32_t arr_1dim4, double** ptr_resultparam15,
int32_t* scalar_resultparam16)
{
void* allocs[1];
int marks[1];
int nallocs = 0;
int32_t v_17_5;
double* alloc6 = NULL;
v_17_5 = arr_0dim2 > arr_1dim4 ? arr_1dim4 : arr_0dim2;
if (cudaMalloc(&alloc6, v_17_5 * sizeof(double)) != cudaSuccess)
goto done;
allocs[nallocs] = (void*) alloc6;
marks[nallocs++] = 0;
{
dim3 gdims;
dim3 tdims;
gdims.x = 128;
gdims.y = 1;
gdims.z = 1;
tdims.x = 480;
tdims.y = 1;
tdims.z = 1;
kern7<<<gdims, tdims>>>(arr_01, arr_0dim2, arr_13, arr_1dim4, v_17_5,
alloc6, v_17_5);
}
mark(allocs, marks, nallocs, alloc6);
*ptr_resultparam15 = alloc6;
*scalar_resultparam16 = v_17_5;
done:
gc(allocs, marks, nallocs);
return cudaGetLastError();
} | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17))
write vec_alloca_2[i_3] (max 0.0 (100.0 - 100.0 * arr_0[i_3] *
arr_1[i_3]))) arr_0 arr_1 v_17
vec_alloca_2
; return vec_alloca_2
}
*/
#include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
#include <inttypes.h>
extern "C" __global__ void kern7(double* uPow, int32_t arr_0dim9,
double* dPow, int32_t arr_1dim11,
int32_t v_1712, double* output,
int32_t vec_alloca_2dim14)
{
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < v_1712;
i += blockDim.x * gridDim.x) {
double strike_minus_st = 100.0 - 100.0 * uPow[i] * dPow[i];
output[i] = max(0.0, strike_minus_st);
}
}
void gc(void** allocs, int* marks, int nallocs)
{
for (int i = 0; i < nallocs; ++i) {
if (marks[i] == 0) {
hipFree((char*) allocs[i]);
allocs[i] = NULL;
}
marks[i] = 0;
}
}
void mark(void** allocs, int* marks, int nallocs, void* alloc)
{
for (int i = 0; i < nallocs; ++i) {
if (allocs[i] == alloc) {
marks[i] = 1;
return;
}
}
}
hipError_t host0(double* arr_01, int32_t arr_0dim2, double* arr_13,
int32_t arr_1dim4, double** ptr_resultparam15,
int32_t* scalar_resultparam16)
{
void* allocs[1];
int marks[1];
int nallocs = 0;
int32_t v_17_5;
double* alloc6 = NULL;
v_17_5 = arr_0dim2 > arr_1dim4 ? arr_1dim4 : arr_0dim2;
if (hipMalloc(&alloc6, v_17_5 * sizeof(double)) != hipSuccess)
goto done;
allocs[nallocs] = (void*) alloc6;
marks[nallocs++] = 0;
{
dim3 gdims;
dim3 tdims;
gdims.x = 128;
gdims.y = 1;
gdims.z = 1;
tdims.x = 480;
tdims.y = 1;
tdims.z = 1;
kern7<<<gdims, tdims>>>(arr_01, arr_0dim2, arr_13, arr_1dim4, v_17_5,
alloc6, v_17_5);
}
mark(allocs, marks, nallocs, alloc6);
*ptr_resultparam15 = alloc6;
*scalar_resultparam16 = v_17_5;
done:
gc(allocs, marks, nallocs);
return hipGetLastError();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17))
write vec_alloca_2[i_3] (max 0.0 (100.0 - 100.0 * arr_0[i_3] *
arr_1[i_3]))) arr_0 arr_1 v_17
vec_alloca_2
; return vec_alloca_2
}
*/
#include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
#include <inttypes.h>
extern "C" __global__ void kern7(double* uPow, int32_t arr_0dim9,
double* dPow, int32_t arr_1dim11,
int32_t v_1712, double* output,
int32_t vec_alloca_2dim14)
{
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < v_1712;
i += blockDim.x * gridDim.x) {
double strike_minus_st = 100.0 - 100.0 * uPow[i] * dPow[i];
output[i] = max(0.0, strike_minus_st);
}
}
void gc(void** allocs, int* marks, int nallocs)
{
for (int i = 0; i < nallocs; ++i) {
if (marks[i] == 0) {
hipFree((char*) allocs[i]);
allocs[i] = NULL;
}
marks[i] = 0;
}
}
void mark(void** allocs, int* marks, int nallocs, void* alloc)
{
for (int i = 0; i < nallocs; ++i) {
if (allocs[i] == alloc) {
marks[i] = 1;
return;
}
}
}
hipError_t host0(double* arr_01, int32_t arr_0dim2, double* arr_13,
int32_t arr_1dim4, double** ptr_resultparam15,
int32_t* scalar_resultparam16)
{
void* allocs[1];
int marks[1];
int nallocs = 0;
int32_t v_17_5;
double* alloc6 = NULL;
v_17_5 = arr_0dim2 > arr_1dim4 ? arr_1dim4 : arr_0dim2;
if (hipMalloc(&alloc6, v_17_5 * sizeof(double)) != hipSuccess)
goto done;
allocs[nallocs] = (void*) alloc6;
marks[nallocs++] = 0;
{
dim3 gdims;
dim3 tdims;
gdims.x = 128;
gdims.y = 1;
gdims.z = 1;
tdims.x = 480;
tdims.y = 1;
tdims.z = 1;
kern7<<<gdims, tdims>>>(arr_01, arr_0dim2, arr_13, arr_1dim4, v_17_5,
alloc6, v_17_5);
}
mark(allocs, marks, nallocs, alloc6);
*ptr_resultparam15 = alloc6;
*scalar_resultparam16 = v_17_5;
done:
gc(allocs, marks, nallocs);
return hipGetLastError();
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kern7
.globl kern7
.p2align 8
.type kern7,@function
kern7:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x1c
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[4:5], v[4:5], off
v_cmp_le_i32_e32 vcc_lo, s8, v1
v_add_co_u32 v2, s0, s6, v2
global_load_b64 v[6:7], v[6:7], off
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[4:5], 0x40590000
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[6:7], 0x40590000
v_max_f64 v[4:5], v[4:5], 0
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kern7
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kern7, .Lfunc_end0-kern7
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kern7
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kern7.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
\(arr_0 :: Array Double[], arr_1 :: Array Double[]) ->
let { v_17 :: Int32 = min (dim#0 arr_0) (dim#0 arr_1) } in
{ vec_alloca_2 :: Array Double[] <- alloc (Array Double[])[v_17]
; call (\(arr_0 :: Array Double[], arr_1 :: Array Double[], v_17 :: Int32,
vec_alloca_2 :: Array Double[]) ->
parfor((0) <= (i_3) < (v_17))
write vec_alloca_2[i_3] (max 0.0 (100.0 - 100.0 * arr_0[i_3] *
arr_1[i_3]))) arr_0 arr_1 v_17
vec_alloca_2
; return vec_alloca_2
}
*/
#include "hip/hip_runtime.h"
#include "hip/hip_runtime_api.h"
#include <inttypes.h>
extern "C" __global__ void kern7(double* uPow, int32_t arr_0dim9,
double* dPow, int32_t arr_1dim11,
int32_t v_1712, double* output,
int32_t vec_alloca_2dim14)
{
for (int32_t i = blockIdx.x * blockDim.x + threadIdx.x; i < v_1712;
i += blockDim.x * gridDim.x) {
double strike_minus_st = 100.0 - 100.0 * uPow[i] * dPow[i];
output[i] = max(0.0, strike_minus_st);
}
}
void gc(void** allocs, int* marks, int nallocs)
{
for (int i = 0; i < nallocs; ++i) {
if (marks[i] == 0) {
hipFree((char*) allocs[i]);
allocs[i] = NULL;
}
marks[i] = 0;
}
}
void mark(void** allocs, int* marks, int nallocs, void* alloc)
{
for (int i = 0; i < nallocs; ++i) {
if (allocs[i] == alloc) {
marks[i] = 1;
return;
}
}
}
hipError_t host0(double* arr_01, int32_t arr_0dim2, double* arr_13,
int32_t arr_1dim4, double** ptr_resultparam15,
int32_t* scalar_resultparam16)
{
void* allocs[1];
int marks[1];
int nallocs = 0;
int32_t v_17_5;
double* alloc6 = NULL;
v_17_5 = arr_0dim2 > arr_1dim4 ? arr_1dim4 : arr_0dim2;
if (hipMalloc(&alloc6, v_17_5 * sizeof(double)) != hipSuccess)
goto done;
allocs[nallocs] = (void*) alloc6;
marks[nallocs++] = 0;
{
dim3 gdims;
dim3 tdims;
gdims.x = 128;
gdims.y = 1;
gdims.z = 1;
tdims.x = 480;
tdims.y = 1;
tdims.z = 1;
kern7<<<gdims, tdims>>>(arr_01, arr_0dim2, arr_13, arr_1dim4, v_17_5,
alloc6, v_17_5);
}
mark(allocs, marks, nallocs, alloc6);
*ptr_resultparam15 = alloc6;
*scalar_resultparam16 = v_17_5;
done:
gc(allocs, marks, nallocs);
return hipGetLastError();
} | .text
.file "finalPut-hand-simplified.hip"
.globl __device_stub__kern7 # -- Begin function __device_stub__kern7
.p2align 4, 0x90
.type __device_stub__kern7,@function
__device_stub__kern7: # @__device_stub__kern7
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $kern7, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__kern7, .Lfunc_end0-__device_stub__kern7
.cfi_endproc
# -- End function
.globl _Z2gcPPvPii # -- Begin function _Z2gcPPvPii
.p2align 4, 0x90
.type _Z2gcPPvPii,@function
_Z2gcPPvPii: # @_Z2gcPPvPii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_6
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %r15d
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movl $0, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r15
je .LBB1_5
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpl $0, (%rbx,%r12,4)
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq (%r14,%r12,8), %rdi
callq hipFree
movq $0, (%r14,%r12,8)
jmp .LBB1_4
.LBB1_5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_6: # %._crit_edge
retq
.Lfunc_end1:
.size _Z2gcPPvPii, .Lfunc_end1-_Z2gcPPvPii
.cfi_endproc
# -- End function
.globl _Z4markPPvPiiS_ # -- Begin function _Z4markPPvPiiS_
.p2align 4, 0x90
.type _Z4markPPvPiiS_,@function
_Z4markPPvPiiS_: # @_Z4markPPvPiiS_
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq %rcx, (%rdi,%rdx,8)
je .LBB2_4
# %bb.2: # in Loop: Header=BB2_3 Depth=1
incq %rdx
cmpq %rdx, %rax
jne .LBB2_3
.LBB2_5: # %.loopexit
retq
.LBB2_4:
movl $1, (%rsi,%rdx,4)
retq
.Lfunc_end2:
.size _Z4markPPvPiiS_, .Lfunc_end2-_Z4markPPvPiiS_
.cfi_endproc
# -- End function
.globl _Z5host0PdiS_iPS_Pi # -- Begin function _Z5host0PdiS_iPS_Pi
.p2align 4, 0x90
.type _Z5host0PdiS_iPS_Pi,@function
_Z5host0PdiS_iPS_Pi: # @_Z5host0PdiS_iPS_Pi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 48(%rsp) # 8-byte Spill
movq %r8, %rbx
movl %ecx, %r15d
movq %rdx, %rbp
movl %esi, %r13d
movq %rdi, %r12
movq $0, 8(%rsp)
cmpl %ecx, %esi
movl %ecx, %r14d
cmovll %esi, %r14d
movslq %r14d, %rsi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB3_2
# %bb.1:
xorl %ebx, %ebx
# implicit-def: $rdi
# implicit-def: $dl
testl %eax, %eax
jne .LBB3_9
jmp .LBB3_6
.LBB3_2:
movl %eax, 20(%rsp) # 4-byte Spill
movq 8(%rsp), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movabsq $4294967424, %rdi # imm = 0x100000080
leaq 352(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq %r12, 120(%rsp)
movl %r13d, 36(%rsp)
movq %rbp, 112(%rsp)
movl %r15d, 32(%rsp)
movl %r14d, 28(%rsp)
movq %rax, 104(%rsp)
movl %r14d, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 112(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $kern7, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4: # %_Z4markPPvPiiS_.exit
movq 8(%rsp), %rcx
movq 40(%rsp), %rdi # 8-byte Reload
cmpq %rcx, %rdi
setne %dl
movq %rcx, (%rbx)
movq 48(%rsp), %rax # 8-byte Reload
movl %r14d, (%rax)
movl $1, %ebx
movl 20(%rsp), %eax # 4-byte Reload
testl %eax, %eax
je .LBB3_6
.LBB3_9: # %_Z2gcPPvPii.exit
callq hipGetLastError
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=1
.cfi_def_cfa_offset 240
movb $1, %dl
decq %rbx
je .LBB3_9
.LBB3_6: # %.lr.ph.i24
# =>This Inner Loop Header: Depth=1
testb $1, %dl
je .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=1
callq hipFree
xorl %edi, %edi
jmp .LBB3_8
.Lfunc_end3:
.size _Z5host0PdiS_iPS_Pi, .Lfunc_end3-_Z5host0PdiS_iPS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kern7, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type kern7,@object # @kern7
.section .rodata,"a",@progbits
.globl kern7
.p2align 3, 0x0
kern7:
.quad __device_stub__kern7
.size kern7, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kern7"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kern7
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kern7
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : kern7
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fc800078e0209 */
/*0090*/ IMAD.WIDE R6, R0, R9, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*00c0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*00d0*/ DMUL R4, R2, 100 ; /* 0x4059000002047828 */
/* 0x004ecc0000000000 */
/*00e0*/ DFMA R4, -R4, R6, 100 ; /* 0x405900000404742b */
/* 0x0080640000000106 */
/*00f0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x001fc800078e00ff */
/*0100*/ DSETP.MAX.AND P0, P1, RZ, R4, PT ; /* 0x00000004ff00722a */
/* 0x002e08000390f000 */
/*0110*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fe40000000f00 */
/*0120*/ SEL R2, R8, R4, P0 ; /* 0x0000000408027207 */
/* 0x001fe20000000000 */
/*0130*/ IMAD.WIDE R4, R0, R9, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fe200078e0209 */
/*0140*/ FSEL R3, R8, R11, P0 ; /* 0x0000000b08037208 */
/* 0x000fc60000000000 */
/*0150*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fc600078e0200 */
/*0160*/ @P1 LOP3.LUT R3, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b031812 */
/* 0x000fe400078efcff */
/*0170*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fc60003f06270 */
/*0180*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x0001f4000c101b04 */
/*0190*/ @!P0 BRA 0x70 ; /* 0xfffffed000008947 */
/* 0x000fea000383ffff */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kern7
.globl kern7
.p2align 8
.type kern7,@function
kern7:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x1c
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[4:5], v[4:5], off
v_cmp_le_i32_e32 vcc_lo, s8, v1
v_add_co_u32 v2, s0, s6, v2
global_load_b64 v[6:7], v[6:7], off
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(1)
v_mul_f64 v[4:5], v[4:5], 0x40590000
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[6:7], 0x40590000
v_max_f64 v[4:5], v[4:5], 0
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kern7
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kern7, .Lfunc_end0-kern7
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kern7
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kern7.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00094b9c_00000000-6_finalPut-hand-simplified.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z2gcPPvPii
.type _Z2gcPPvPii, @function
_Z2gcPPvPii:
.LFB2027:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L9
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbx
movq %rdi, %rbp
movslq %edx, %rdx
leaq (%rsi,%rdx,4), %r13
jmp .L6
.L5:
movl $0, (%r12)
addq $4, %rbx
addq $8, %rbp
cmpq %r13, %rbx
je .L12
.L6:
movq %rbx, %r12
cmpl $0, (%rbx)
jne .L5
movq 0(%rbp), %rdi
call cudaFree@PLT
movq $0, 0(%rbp)
jmp .L5
.L12:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE2027:
.size _Z2gcPPvPii, .-_Z2gcPPvPii
.globl _Z4markPPvPiiS_
.type _Z4markPPvPiiS_, @function
_Z4markPPvPiiS_:
.LFB2028:
.cfi_startproc
endbr64
testl %edx, %edx
jle .L13
movslq %edx, %rdx
movl $0, %eax
.L16:
cmpq %rcx, (%rdi,%rax,8)
je .L18
addq $1, %rax
cmpq %rdx, %rax
jne .L16
.L13:
ret
.L18:
movl $1, (%rsi,%rax,4)
ret
.cfi_endproc
.LFE2028:
.size _Z4markPPvPiiS_, .-_Z4markPPvPiiS_
.globl _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i
.type _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i, @function
_Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i:
.LFB2054:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 20(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq kern7(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i, .-_Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i
.globl kern7
.type kern7, @function
kern7:
.LFB2055:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size kern7, .-kern7
.globl _Z5host0PdiS_iPS_Pi
.type _Z5host0PdiS_iPS_Pi, @function
_Z5host0PdiS_iPS_Pi:
.LFB2029:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 8(%rsp)
movl %esi, %ebx
movq %rdx, %r14
movl %ecx, %ebp
movq %r8, %r13
movq %r9, %r12
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
cmpl %ecx, %esi
movl %ecx, %r15d
cmovle %esi, %r15d
movslq %r15d, %rsi
salq $3, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl $0, %edx
testl %eax, %eax
je .L33
.L28:
leaq 60(%rsp), %rsi
leaq 64(%rsp), %rdi
call _Z2gcPPvPii
call cudaGetLastError@PLT
movq 72(%rsp), %rdx
subq %fs:40, %rdx
jne .L34
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 24(%rsp), %rax
movq %rax, 64(%rsp)
movl $0, 60(%rsp)
movl $1, 40(%rsp)
movl $1, 52(%rsp)
movl $128, 36(%rsp)
movl $480, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L29:
movq 24(%rsp), %rbx
leaq 60(%rsp), %rsi
leaq 64(%rsp), %rdi
movq %rbx, %rcx
movl $1, %edx
call _Z4markPPvPiiS_
movq %rbx, 0(%r13)
movl %r15d, (%r12)
movl $1, %edx
jmp .L28
.L35:
subq $8, %rsp
.cfi_def_cfa_offset 152
pushq %r15
.cfi_def_cfa_offset 160
movq 40(%rsp), %r9
movl %r15d, %r8d
movl %ebp, %ecx
movq %r14, %rdx
movl %ebx, %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z5kern7PdiS_iiS_iPdiS_iiS_i
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2029:
.size _Z5host0PdiS_iPS_Pi, .-_Z5host0PdiS_iPS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kern7"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kern7(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "finalPut-hand-simplified.hip"
.globl __device_stub__kern7 # -- Begin function __device_stub__kern7
.p2align 4, 0x90
.type __device_stub__kern7,@function
__device_stub__kern7: # @__device_stub__kern7
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %r9, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $kern7, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__kern7, .Lfunc_end0-__device_stub__kern7
.cfi_endproc
# -- End function
.globl _Z2gcPPvPii # -- Begin function _Z2gcPPvPii
.p2align 4, 0x90
.type _Z2gcPPvPii,@function
_Z2gcPPvPii: # @_Z2gcPPvPii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB1_6
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %r15d
xorl %r12d, %r12d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
movl $0, (%rbx,%r12,4)
incq %r12
cmpq %r12, %r15
je .LBB1_5
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpl $0, (%rbx,%r12,4)
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq (%r14,%r12,8), %rdi
callq hipFree
movq $0, (%r14,%r12,8)
jmp .LBB1_4
.LBB1_5:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB1_6: # %._crit_edge
retq
.Lfunc_end1:
.size _Z2gcPPvPii, .Lfunc_end1-_Z2gcPPvPii
.cfi_endproc
# -- End function
.globl _Z4markPPvPiiS_ # -- Begin function _Z4markPPvPiiS_
.p2align 4, 0x90
.type _Z4markPPvPiiS_,@function
_Z4markPPvPiiS_: # @_Z4markPPvPiiS_
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB2_5
# %bb.1: # %.lr.ph.preheader
movl %edx, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB2_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq %rcx, (%rdi,%rdx,8)
je .LBB2_4
# %bb.2: # in Loop: Header=BB2_3 Depth=1
incq %rdx
cmpq %rdx, %rax
jne .LBB2_3
.LBB2_5: # %.loopexit
retq
.LBB2_4:
movl $1, (%rsi,%rdx,4)
retq
.Lfunc_end2:
.size _Z4markPPvPiiS_, .Lfunc_end2-_Z4markPPvPiiS_
.cfi_endproc
# -- End function
.globl _Z5host0PdiS_iPS_Pi # -- Begin function _Z5host0PdiS_iPS_Pi
.p2align 4, 0x90
.type _Z5host0PdiS_iPS_Pi,@function
_Z5host0PdiS_iPS_Pi: # @_Z5host0PdiS_iPS_Pi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 48(%rsp) # 8-byte Spill
movq %r8, %rbx
movl %ecx, %r15d
movq %rdx, %rbp
movl %esi, %r13d
movq %rdi, %r12
movq $0, 8(%rsp)
cmpl %ecx, %esi
movl %ecx, %r14d
cmovll %esi, %r14d
movslq %r14d, %rsi
shlq $3, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
testl %eax, %eax
je .LBB3_2
# %bb.1:
xorl %ebx, %ebx
# implicit-def: $rdi
# implicit-def: $dl
testl %eax, %eax
jne .LBB3_9
jmp .LBB3_6
.LBB3_2:
movl %eax, 20(%rsp) # 4-byte Spill
movq 8(%rsp), %rax
movq %rax, 40(%rsp) # 8-byte Spill
movabsq $4294967424, %rdi # imm = 0x100000080
leaq 352(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 8(%rsp), %rax
movq %r12, 120(%rsp)
movl %r13d, 36(%rsp)
movq %rbp, 112(%rsp)
movl %r15d, 32(%rsp)
movl %r14d, 28(%rsp)
movq %rax, 104(%rsp)
movl %r14d, 24(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 112(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 104(%rsp), %rax
movq %rax, 168(%rsp)
leaq 24(%rsp), %rax
movq %rax, 176(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $kern7, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4: # %_Z4markPPvPiiS_.exit
movq 8(%rsp), %rcx
movq 40(%rsp), %rdi # 8-byte Reload
cmpq %rcx, %rdi
setne %dl
movq %rcx, (%rbx)
movq 48(%rsp), %rax # 8-byte Reload
movl %r14d, (%rax)
movl $1, %ebx
movl 20(%rsp), %eax # 4-byte Reload
testl %eax, %eax
je .LBB3_6
.LBB3_9: # %_Z2gcPPvPii.exit
callq hipGetLastError
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.p2align 4, 0x90
.LBB3_8: # in Loop: Header=BB3_6 Depth=1
.cfi_def_cfa_offset 240
movb $1, %dl
decq %rbx
je .LBB3_9
.LBB3_6: # %.lr.ph.i24
# =>This Inner Loop Header: Depth=1
testb $1, %dl
je .LBB3_8
# %bb.7: # in Loop: Header=BB3_6 Depth=1
callq hipFree
xorl %edi, %edi
jmp .LBB3_8
.Lfunc_end3:
.size _Z5host0PdiS_iPS_Pi, .Lfunc_end3-_Z5host0PdiS_iPS_Pi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kern7, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type kern7,@object # @kern7
.section .rodata,"a",@progbits
.globl kern7
.p2align 3, 0x0
kern7:
.quad __device_stub__kern7
.size kern7, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kern7"
.size .L__unnamed_1, 6
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kern7
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kern7
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = v;
}
} | code for sm_80
Function : _Z16matrixMultKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = v;
}
} | .file "tmpxft_0016401e_00000000-6_matrixMultKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i
.type _Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i, @function
_Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16matrixMultKernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i, .-_Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i
.globl _Z16matrixMultKernelPdS_S_i
.type _Z16matrixMultKernelPdS_S_i, @function
_Z16matrixMultKernelPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16matrixMultKernelPdS_S_i, .-_Z16matrixMultKernelPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16matrixMultKernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrixMultKernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = v;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = v;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = v;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixMultKernelPdS_S_i
.globl _Z16matrixMultKernelPdS_S_i
.p2align 8
.type _Z16matrixMultKernelPdS_S_i,@function
_Z16matrixMultKernelPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16matrixMultKernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16matrixMultKernelPdS_S_i, .Lfunc_end0-_Z16matrixMultKernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16matrixMultKernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16matrixMultKernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define N 1200
#define THREADS 1024
__global__ void matrixMultKernel (double *a, double *b, double *c, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if((row < n) && (col < n)){
double v = 0;
for(int k = 0; k < n; k++){
v += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = v;
}
} | .text
.file "matrixMultKernel.hip"
.globl _Z31__device_stub__matrixMultKernelPdS_S_i # -- Begin function _Z31__device_stub__matrixMultKernelPdS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__matrixMultKernelPdS_S_i,@function
_Z31__device_stub__matrixMultKernelPdS_S_i: # @_Z31__device_stub__matrixMultKernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16matrixMultKernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__matrixMultKernelPdS_S_i, .Lfunc_end0-_Z31__device_stub__matrixMultKernelPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrixMultKernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrixMultKernelPdS_S_i,@object # @_Z16matrixMultKernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z16matrixMultKernelPdS_S_i
.p2align 3, 0x0
_Z16matrixMultKernelPdS_S_i:
.quad _Z31__device_stub__matrixMultKernelPdS_S_i
.size _Z16matrixMultKernelPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16matrixMultKernelPdS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrixMultKernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrixMultKernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16matrixMultKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16matrixMultKernelPdS_S_i
.globl _Z16matrixMultKernelPdS_S_i
.p2align 8
.type _Z16matrixMultKernelPdS_S_i,@function
_Z16matrixMultKernelPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16matrixMultKernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16matrixMultKernelPdS_S_i, .Lfunc_end0-_Z16matrixMultKernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16matrixMultKernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16matrixMultKernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016401e_00000000-6_matrixMultKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i
.type _Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i, @function
_Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16matrixMultKernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i, .-_Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i
.globl _Z16matrixMultKernelPdS_S_i
.type _Z16matrixMultKernelPdS_S_i, @function
_Z16matrixMultKernelPdS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16matrixMultKernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z16matrixMultKernelPdS_S_i, .-_Z16matrixMultKernelPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z16matrixMultKernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z16matrixMultKernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultKernel.hip"
.globl _Z31__device_stub__matrixMultKernelPdS_S_i # -- Begin function _Z31__device_stub__matrixMultKernelPdS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__matrixMultKernelPdS_S_i,@function
_Z31__device_stub__matrixMultKernelPdS_S_i: # @_Z31__device_stub__matrixMultKernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16matrixMultKernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__matrixMultKernelPdS_S_i, .Lfunc_end0-_Z31__device_stub__matrixMultKernelPdS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16matrixMultKernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16matrixMultKernelPdS_S_i,@object # @_Z16matrixMultKernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z16matrixMultKernelPdS_S_i
.p2align 3, 0x0
_Z16matrixMultKernelPdS_S_i:
.quad _Z31__device_stub__matrixMultKernelPdS_S_i
.size _Z16matrixMultKernelPdS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16matrixMultKernelPdS_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__matrixMultKernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16matrixMultKernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_x_out[tid] = short_long*leverage*(quantity/entry_price-quantity/d_x_in[tid])/entry_value*100;
}
}
__global__ void multithreads_normal_calculate(
double* d_x_in, double* d_xnormal_out, int d_n, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_xnormal_out[tid]
= short_long*leverage*(d_x_in[tid]-entry_price)/entry_price*100;
}
}
int main(){
int quantity, entry_price, exit_price, leverage, short_long;
quantity = 1;
entry_price = 1;
exit_price = 1000;
leverage = 1;
short_long = -1;
//ROE inverse calculate
double entry_value, exit_value, profit, roe_inverse;
entry_value = quantity/(double)entry_price;
exit_value = quantity/(double)exit_price;
profit = entry_value-exit_value;
roe_inverse = (profit/entry_value)*100*leverage*short_long;
//ROE normal calculate
double roe_normal;
roe_normal = short_long*leverage*((exit_price-entry_price)/(double)entry_price)*100;
//find array x
int num_arr;
if(entry_price > exit_price){
num_arr = (entry_price - exit_price);
} else{
num_arr = (exit_price - entry_price);
}
int n = num_arr*10+1;
double x_in[n], xinverse_out[n], xnormal_out[n];
for(int i = 0; i < n; i++){
if(entry_price <= exit_price){
x_in[i] = i*0.1 + entry_price;
} else{
x_in[i] = i*0.1 + exit_price;
}
}
//copy data from host to device
double* d_x_in, *d_xinverse_out, *d_xnormal_out;
cudaMalloc((void **) &d_x_in, n*sizeof(double));
cudaMalloc((void **) &d_xinverse_out, n*sizeof(double));
cudaMalloc((void **) &d_xnormal_out, n*sizeof(double));
cudaMemcpy(d_x_in, &x_in, n*sizeof(double), cudaMemcpyHostToDevice);
//time record start
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
//Kernel launch
/*multithreads_inverse_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in, d_xinverse_out, entry_value, n, quantity, entry_price, leverage,short_long);*/
//time record stop
multithreads_normal_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in,d_xnormal_out,n,entry_price,leverage,short_long);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float millisec = 0;
cudaEventElapsedTime(&millisec, start, stop);
//Copy data from device back to host. and free all data allocate on device
cudaMemcpy(&xinverse_out, d_xinverse_out, n*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(&xnormal_out, d_xnormal_out, n*sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(d_x_in);
cudaFree(d_xinverse_out);
cudaFree(d_xnormal_out);
//prit check output
printf("\nROE inverse %.2lf%%\n", roe_inverse);
printf("ROE normal %.2lf%%\n", roe_normal);
printf("num arr: %d\n", num_arr);
printf("n: %d\n", n);
/*for(int i = 0; i < n; i++){
//printf("%.2lf ", xinverse_out[i]);
}
for(int i=0; i<n; i++){
printf("%.2lf" , xnormal_out[i]);
}*/
printf("Time: %.2f ms\n", millisec);
} | .file "tmpxft_000baab2_00000000-6_roe_calculate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii
.type _Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii, @function
_Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z30multithreads_inverse_calculatePdS_diiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii, .-_Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii
.globl _Z30multithreads_inverse_calculatePdS_diiiii
.type _Z30multithreads_inverse_calculatePdS_diiiii, @function
_Z30multithreads_inverse_calculatePdS_diiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z30multithreads_inverse_calculatePdS_diiiii, .-_Z30multithreads_inverse_calculatePdS_diiiii
.globl _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii
.type _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii, @function
_Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29multithreads_normal_calculatePdS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii, .-_Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii
.globl _Z29multithreads_normal_calculatePdS_iiii
.type _Z29multithreads_normal_calculatePdS_iiii, @function
_Z29multithreads_normal_calculatePdS_iiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z29multithreads_normal_calculatePdS_iiii, .-_Z29multithreads_normal_calculatePdS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\nROE inverse %.2lf%%\n"
.LC6:
.string "ROE normal %.2lf%%\n"
.LC7:
.string "num arr: %d\n"
.LC8:
.string "n: %d\n"
.LC9:
.string "Time: %.2f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 13, -24
.cfi_offset 12, -32
.cfi_offset 3, -40
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq -77824(%rsp), %rax
.L20:
cmpq %rax, %rsp
je .L21
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L20
.L21:
subq $2112, %rsp
orq $0, 2104(%rsp)
movq %rsp, %rbx
leaq -77824(%rsp), %rax
.L23:
cmpq %rax, %rsp
je .L24
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L23
.L24:
subq $2112, %rsp
orq $0, 2104(%rsp)
movq %rsp, %r13
leaq -77824(%rsp), %rax
.L26:
cmpq %rax, %rsp
je .L27
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L26
.L27:
subq $2112, %rsp
orq $0, 2104(%rsp)
movq %rsp, %r12
movl $0, %eax
movsd .LC0(%rip), %xmm2
movsd .LC1(%rip), %xmm1
.L29:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $9991, %rax
jne .L29
leaq -104(%rbp), %rdi
movl $79928, %esi
call cudaMalloc@PLT
leaq -96(%rbp), %rdi
movl $79928, %esi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movl $79928, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $79928, %edx
movq %rbx, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
leaq -80(%rbp), %rdi
call cudaEventCreate@PLT
leaq -72(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -80(%rbp), %rdi
call cudaEventRecord@PLT
movl $1024, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $10, -64(%rbp)
movl $1, -60(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movl $0, %esi
movq -72(%rbp), %rdi
call cudaEventRecord@PLT
movq -72(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -52(%rbp)
leaq -52(%rbp), %rdi
movq -72(%rbp), %rdx
movq -80(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $79928, %edx
movq -96(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $79928, %edx
movq -88(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $999, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $9991, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -52(%rbp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
leaq -24(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L34:
.cfi_restore_state
movl $-1, %r9d
movl $1, %r8d
movl $1, %ecx
movl $9991, %edx
movq -88(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "_Z29multithreads_normal_calculatePdS_iiii"
.align 8
.LC11:
.string "_Z30multithreads_inverse_calculatePdS_diiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z29multithreads_normal_calculatePdS_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z30multithreads_inverse_calculatePdS_diiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1717986918
.long 1069128089
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC3:
.long -1717986918
.long -1067910759
.align 8
.LC5:
.long 0
.long -1057463360
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_x_out[tid] = short_long*leverage*(quantity/entry_price-quantity/d_x_in[tid])/entry_value*100;
}
}
__global__ void multithreads_normal_calculate(
double* d_x_in, double* d_xnormal_out, int d_n, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_xnormal_out[tid]
= short_long*leverage*(d_x_in[tid]-entry_price)/entry_price*100;
}
}
int main(){
int quantity, entry_price, exit_price, leverage, short_long;
quantity = 1;
entry_price = 1;
exit_price = 1000;
leverage = 1;
short_long = -1;
//ROE inverse calculate
double entry_value, exit_value, profit, roe_inverse;
entry_value = quantity/(double)entry_price;
exit_value = quantity/(double)exit_price;
profit = entry_value-exit_value;
roe_inverse = (profit/entry_value)*100*leverage*short_long;
//ROE normal calculate
double roe_normal;
roe_normal = short_long*leverage*((exit_price-entry_price)/(double)entry_price)*100;
//find array x
int num_arr;
if(entry_price > exit_price){
num_arr = (entry_price - exit_price);
} else{
num_arr = (exit_price - entry_price);
}
int n = num_arr*10+1;
double x_in[n], xinverse_out[n], xnormal_out[n];
for(int i = 0; i < n; i++){
if(entry_price <= exit_price){
x_in[i] = i*0.1 + entry_price;
} else{
x_in[i] = i*0.1 + exit_price;
}
}
//copy data from host to device
double* d_x_in, *d_xinverse_out, *d_xnormal_out;
cudaMalloc((void **) &d_x_in, n*sizeof(double));
cudaMalloc((void **) &d_xinverse_out, n*sizeof(double));
cudaMalloc((void **) &d_xnormal_out, n*sizeof(double));
cudaMemcpy(d_x_in, &x_in, n*sizeof(double), cudaMemcpyHostToDevice);
//time record start
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
//Kernel launch
/*multithreads_inverse_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in, d_xinverse_out, entry_value, n, quantity, entry_price, leverage,short_long);*/
//time record stop
multithreads_normal_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in,d_xnormal_out,n,entry_price,leverage,short_long);
cudaEventRecord(stop);
cudaEventSynchronize(stop);
float millisec = 0;
cudaEventElapsedTime(&millisec, start, stop);
//Copy data from device back to host. and free all data allocate on device
cudaMemcpy(&xinverse_out, d_xinverse_out, n*sizeof(double), cudaMemcpyDeviceToHost);
cudaMemcpy(&xnormal_out, d_xnormal_out, n*sizeof(double), cudaMemcpyDeviceToHost);
cudaFree(d_x_in);
cudaFree(d_xinverse_out);
cudaFree(d_xnormal_out);
//prit check output
printf("\nROE inverse %.2lf%%\n", roe_inverse);
printf("ROE normal %.2lf%%\n", roe_normal);
printf("num arr: %d\n", num_arr);
printf("n: %d\n", n);
/*for(int i = 0; i < n; i++){
//printf("%.2lf ", xinverse_out[i]);
}
for(int i=0; i<n; i++){
printf("%.2lf" , xnormal_out[i]);
}*/
printf("Time: %.2f ms\n", millisec);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_x_out[tid] = short_long*leverage*(quantity/entry_price-quantity/d_x_in[tid])/entry_value*100;
}
}
__global__ void multithreads_normal_calculate(
double* d_x_in, double* d_xnormal_out, int d_n, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_xnormal_out[tid]
= short_long*leverage*(d_x_in[tid]-entry_price)/entry_price*100;
}
}
int main(){
int quantity, entry_price, exit_price, leverage, short_long;
quantity = 1;
entry_price = 1;
exit_price = 1000;
leverage = 1;
short_long = -1;
//ROE inverse calculate
double entry_value, exit_value, profit, roe_inverse;
entry_value = quantity/(double)entry_price;
exit_value = quantity/(double)exit_price;
profit = entry_value-exit_value;
roe_inverse = (profit/entry_value)*100*leverage*short_long;
//ROE normal calculate
double roe_normal;
roe_normal = short_long*leverage*((exit_price-entry_price)/(double)entry_price)*100;
//find array x
int num_arr;
if(entry_price > exit_price){
num_arr = (entry_price - exit_price);
} else{
num_arr = (exit_price - entry_price);
}
int n = num_arr*10+1;
double x_in[n], xinverse_out[n], xnormal_out[n];
for(int i = 0; i < n; i++){
if(entry_price <= exit_price){
x_in[i] = i*0.1 + entry_price;
} else{
x_in[i] = i*0.1 + exit_price;
}
}
//copy data from host to device
double* d_x_in, *d_xinverse_out, *d_xnormal_out;
hipMalloc((void **) &d_x_in, n*sizeof(double));
hipMalloc((void **) &d_xinverse_out, n*sizeof(double));
hipMalloc((void **) &d_xnormal_out, n*sizeof(double));
hipMemcpy(d_x_in, &x_in, n*sizeof(double), hipMemcpyHostToDevice);
//time record start
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
//Kernel launch
/*multithreads_inverse_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in, d_xinverse_out, entry_value, n, quantity, entry_price, leverage,short_long);*/
//time record stop
multithreads_normal_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in,d_xnormal_out,n,entry_price,leverage,short_long);
hipEventRecord(stop);
hipEventSynchronize(stop);
float millisec = 0;
hipEventElapsedTime(&millisec, start, stop);
//Copy data from device back to host. and free all data allocate on device
hipMemcpy(&xinverse_out, d_xinverse_out, n*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(&xnormal_out, d_xnormal_out, n*sizeof(double), hipMemcpyDeviceToHost);
hipFree(d_x_in);
hipFree(d_xinverse_out);
hipFree(d_xnormal_out);
//prit check output
printf("\nROE inverse %.2lf%%\n", roe_inverse);
printf("ROE normal %.2lf%%\n", roe_normal);
printf("num arr: %d\n", num_arr);
printf("n: %d\n", n);
/*for(int i = 0; i < n; i++){
//printf("%.2lf ", xinverse_out[i]);
}
for(int i=0; i<n; i++){
printf("%.2lf" , xnormal_out[i]);
}*/
printf("Time: %.2f ms\n", millisec);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_x_out[tid] = short_long*leverage*(quantity/entry_price-quantity/d_x_in[tid])/entry_value*100;
}
}
__global__ void multithreads_normal_calculate(
double* d_x_in, double* d_xnormal_out, int d_n, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_xnormal_out[tid]
= short_long*leverage*(d_x_in[tid]-entry_price)/entry_price*100;
}
}
int main(){
int quantity, entry_price, exit_price, leverage, short_long;
quantity = 1;
entry_price = 1;
exit_price = 1000;
leverage = 1;
short_long = -1;
//ROE inverse calculate
double entry_value, exit_value, profit, roe_inverse;
entry_value = quantity/(double)entry_price;
exit_value = quantity/(double)exit_price;
profit = entry_value-exit_value;
roe_inverse = (profit/entry_value)*100*leverage*short_long;
//ROE normal calculate
double roe_normal;
roe_normal = short_long*leverage*((exit_price-entry_price)/(double)entry_price)*100;
//find array x
int num_arr;
if(entry_price > exit_price){
num_arr = (entry_price - exit_price);
} else{
num_arr = (exit_price - entry_price);
}
int n = num_arr*10+1;
double x_in[n], xinverse_out[n], xnormal_out[n];
for(int i = 0; i < n; i++){
if(entry_price <= exit_price){
x_in[i] = i*0.1 + entry_price;
} else{
x_in[i] = i*0.1 + exit_price;
}
}
//copy data from host to device
double* d_x_in, *d_xinverse_out, *d_xnormal_out;
hipMalloc((void **) &d_x_in, n*sizeof(double));
hipMalloc((void **) &d_xinverse_out, n*sizeof(double));
hipMalloc((void **) &d_xnormal_out, n*sizeof(double));
hipMemcpy(d_x_in, &x_in, n*sizeof(double), hipMemcpyHostToDevice);
//time record start
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
//Kernel launch
/*multithreads_inverse_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in, d_xinverse_out, entry_value, n, quantity, entry_price, leverage,short_long);*/
//time record stop
multithreads_normal_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in,d_xnormal_out,n,entry_price,leverage,short_long);
hipEventRecord(stop);
hipEventSynchronize(stop);
float millisec = 0;
hipEventElapsedTime(&millisec, start, stop);
//Copy data from device back to host. and free all data allocate on device
hipMemcpy(&xinverse_out, d_xinverse_out, n*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(&xnormal_out, d_xnormal_out, n*sizeof(double), hipMemcpyDeviceToHost);
hipFree(d_x_in);
hipFree(d_xinverse_out);
hipFree(d_xnormal_out);
//prit check output
printf("\nROE inverse %.2lf%%\n", roe_inverse);
printf("ROE normal %.2lf%%\n", roe_normal);
printf("num arr: %d\n", num_arr);
printf("n: %d\n", n);
/*for(int i = 0; i < n; i++){
//printf("%.2lf ", xinverse_out[i]);
}
for(int i=0; i<n; i++){
printf("%.2lf" , xnormal_out[i]);
}*/
printf("Time: %.2f ms\n", millisec);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30multithreads_inverse_calculatePdS_diiiii
.globl _Z30multithreads_inverse_calculatePdS_diiiii
.p2align 8
.type _Z30multithreads_inverse_calculatePdS_diiiii,@function
_Z30multithreads_inverse_calculatePdS_diiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b128 s[0:3], s[0:1], 0x1c
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_cvt_f64_i32_e32 v[4:5], s0
s_ashr_i32 s4, s1, 31
s_ashr_i32 s11, s0, 31
global_load_b64 v[2:3], v[2:3], off
s_add_i32 s1, s1, s4
s_add_i32 s0, s0, s11
s_xor_b32 s1, s1, s4
s_xor_b32 s0, s0, s11
s_sub_i32 s10, 0, s1
s_xor_b32 s4, s11, s4
s_waitcnt vmcnt(0)
v_div_scale_f64 v[6:7], null, v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[12:13], vcc_lo, v[4:5], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_cvt_f32_u32_e32 v12, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_rcp_iflag_f32_e32 v12, v12
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, 0x4f7ffffe, v12
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_cvt_u32_f32_e32 v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s5, v8
s_mul_i32 s10, s10, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s10, s5, s10
s_add_i32 s5, s5, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s5, s0, s5
s_mul_i32 s10, s5, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s0, s0, s10
s_add_i32 s10, s5, 1
s_sub_i32 s11, s0, s1
s_cmp_ge_u32 s0, s1
s_cselect_b32 s5, s10, s5
s_cselect_b32 s0, s11, s0
s_add_i32 s10, s5, 1
s_cmp_ge_u32 s0, s1
s_cselect_b32 s0, s10, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, s4
s_sub_i32 s0, s0, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_f64_i32_e32 v[8:9], s0
v_div_fixup_f64 v[2:3], v[6:7], v[2:3], v[4:5]
s_mul_i32 s0, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[4:5], s0
v_add_f64 v[2:3], v[8:9], -v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[4:5]
v_div_scale_f64 v[4:5], null, s[8:9], s[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[6:7], v[4:5]
s_waitcnt_depctr 0xfff
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[8:9], v[6:7]
v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[4:5], s[8:9], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], 0x40590000
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30multithreads_inverse_calculatePdS_diiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30multithreads_inverse_calculatePdS_diiiii, .Lfunc_end0-_Z30multithreads_inverse_calculatePdS_diiiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z29multithreads_normal_calculatePdS_iiii
.globl _Z29multithreads_normal_calculatePdS_iiii
.p2align 8
.type _Z29multithreads_normal_calculatePdS_iiii,@function
_Z29multithreads_normal_calculatePdS_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x14
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x1c
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_cvt_f64_i32_e32 v[4:5], s2
s_mul_i32 s0, s0, s3
v_cvt_f64_i32_e32 v[6:7], s0
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_add_f64 v[2:3], v[2:3], -v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], v[6:7]
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_div_scale_f64 v[10:11], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[12:13], v[10:11], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[12:13]
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1)
v_mul_f64 v[2:3], v[2:3], 0x40590000
global_store_b64 v[0:1], v[2:3], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z29multithreads_normal_calculatePdS_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z29multithreads_normal_calculatePdS_iiii, .Lfunc_end1-_Z29multithreads_normal_calculatePdS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30multithreads_inverse_calculatePdS_diiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30multithreads_inverse_calculatePdS_diiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z29multithreads_normal_calculatePdS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z29multithreads_normal_calculatePdS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<math.h>
#define BLOCK_SIZE 1024
__global__ void multithreads_inverse_calculate(
double* d_x_in, double* d_x_out, double entry_value, int d_n, int quantity, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_x_out[tid] = short_long*leverage*(quantity/entry_price-quantity/d_x_in[tid])/entry_value*100;
}
}
__global__ void multithreads_normal_calculate(
double* d_x_in, double* d_xnormal_out, int d_n, int entry_price, int leverage, int short_long
)
{
int tid = blockIdx.x*blockDim.x + threadIdx.x;
//int tid = threadIdx.x;
if(tid < d_n){
//printf("d_x_in[%d]: %.2f\n", tid, d_x_in[tid]); //print d_x_in
d_xnormal_out[tid]
= short_long*leverage*(d_x_in[tid]-entry_price)/entry_price*100;
}
}
int main(){
int quantity, entry_price, exit_price, leverage, short_long;
quantity = 1;
entry_price = 1;
exit_price = 1000;
leverage = 1;
short_long = -1;
//ROE inverse calculate
double entry_value, exit_value, profit, roe_inverse;
entry_value = quantity/(double)entry_price;
exit_value = quantity/(double)exit_price;
profit = entry_value-exit_value;
roe_inverse = (profit/entry_value)*100*leverage*short_long;
//ROE normal calculate
double roe_normal;
roe_normal = short_long*leverage*((exit_price-entry_price)/(double)entry_price)*100;
//find array x
int num_arr;
if(entry_price > exit_price){
num_arr = (entry_price - exit_price);
} else{
num_arr = (exit_price - entry_price);
}
int n = num_arr*10+1;
double x_in[n], xinverse_out[n], xnormal_out[n];
for(int i = 0; i < n; i++){
if(entry_price <= exit_price){
x_in[i] = i*0.1 + entry_price;
} else{
x_in[i] = i*0.1 + exit_price;
}
}
//copy data from host to device
double* d_x_in, *d_xinverse_out, *d_xnormal_out;
hipMalloc((void **) &d_x_in, n*sizeof(double));
hipMalloc((void **) &d_xinverse_out, n*sizeof(double));
hipMalloc((void **) &d_xnormal_out, n*sizeof(double));
hipMemcpy(d_x_in, &x_in, n*sizeof(double), hipMemcpyHostToDevice);
//time record start
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
//Kernel launch
/*multithreads_inverse_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in, d_xinverse_out, entry_value, n, quantity, entry_price, leverage,short_long);*/
//time record stop
multithreads_normal_calculate<<<ceil(n/(double)BLOCK_SIZE), BLOCK_SIZE>>>(
d_x_in,d_xnormal_out,n,entry_price,leverage,short_long);
hipEventRecord(stop);
hipEventSynchronize(stop);
float millisec = 0;
hipEventElapsedTime(&millisec, start, stop);
//Copy data from device back to host. and free all data allocate on device
hipMemcpy(&xinverse_out, d_xinverse_out, n*sizeof(double), hipMemcpyDeviceToHost);
hipMemcpy(&xnormal_out, d_xnormal_out, n*sizeof(double), hipMemcpyDeviceToHost);
hipFree(d_x_in);
hipFree(d_xinverse_out);
hipFree(d_xnormal_out);
//prit check output
printf("\nROE inverse %.2lf%%\n", roe_inverse);
printf("ROE normal %.2lf%%\n", roe_normal);
printf("num arr: %d\n", num_arr);
printf("n: %d\n", n);
/*for(int i = 0; i < n; i++){
//printf("%.2lf ", xinverse_out[i]);
}
for(int i=0; i<n; i++){
printf("%.2lf" , xnormal_out[i]);
}*/
printf("Time: %.2f ms\n", millisec);
} | .text
.file "roe_calculate.hip"
.globl _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii # -- Begin function _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.p2align 4, 0x90
.type _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii,@function
_Z45__device_stub__multithreads_inverse_calculatePdS_diiiii: # @_Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z30multithreads_inverse_calculatePdS_diiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii, .Lfunc_end0-_Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.cfi_endproc
# -- End function
.globl _Z44__device_stub__multithreads_normal_calculatePdS_iiii # -- Begin function _Z44__device_stub__multithreads_normal_calculatePdS_iiii
.p2align 4, 0x90
.type _Z44__device_stub__multithreads_normal_calculatePdS_iiii,@function
_Z44__device_stub__multithreads_normal_calculatePdS_iiii: # @_Z44__device_stub__multithreads_normal_calculatePdS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29multithreads_normal_calculatePdS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z44__device_stub__multithreads_normal_calculatePdS_iiii, .Lfunc_end1-_Z44__device_stub__multithreads_normal_calculatePdS_iiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3fb999999999999a # double 0.10000000000000001
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.LCPI2_2:
.quad 0xc058f9999999999a # double -99.900000000000005
.LCPI2_3:
.quad 0xc0f863c000000000 # double -99900
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $239976, %rsp # imm = 0x3A968
.cfi_def_cfa_offset 239984
xorl %eax, %eax
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
mulsd %xmm0, %xmm2
addsd %xmm1, %xmm2
movsd %xmm2, 176(%rsp,%rax,8)
incq %rax
cmpq $9991, %rax # imm = 0x2707
jne .LBB2_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $79928, %esi # imm = 0x13838
callq hipMalloc
leaq 56(%rsp), %rdi
movl $79928, %esi # imm = 0x13838
callq hipMalloc
leaq 16(%rsp), %rdi
movl $79928, %esi # imm = 0x13838
callq hipMalloc
movq 24(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $79928, %edx # imm = 0x13838
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 1014(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $9991, 44(%rsp) # imm = 0x2707
movl $1, 40(%rsp)
movl $1, 36(%rsp)
movl $-1, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z29multithreads_normal_calculatePdS_iiii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 128(%rsp)
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 56(%rsp), %rsi
leaq 160048(%rsp), %rdi
movl $79928, %edx # imm = 0x13838
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 80112(%rsp), %rdi
movl $79928, %edx # imm = 0x13838
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movsd .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $999, %esi # imm = 0x3E7
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $9991, %esi # imm = 0x2707
xorl %eax, %eax
callq printf
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $239976, %rsp # imm = 0x3A968
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30multithreads_inverse_calculatePdS_diiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29multithreads_normal_calculatePdS_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30multithreads_inverse_calculatePdS_diiiii,@object # @_Z30multithreads_inverse_calculatePdS_diiiii
.section .rodata,"a",@progbits
.globl _Z30multithreads_inverse_calculatePdS_diiiii
.p2align 3, 0x0
_Z30multithreads_inverse_calculatePdS_diiiii:
.quad _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.size _Z30multithreads_inverse_calculatePdS_diiiii, 8
.type _Z29multithreads_normal_calculatePdS_iiii,@object # @_Z29multithreads_normal_calculatePdS_iiii
.globl _Z29multithreads_normal_calculatePdS_iiii
.p2align 3, 0x0
_Z29multithreads_normal_calculatePdS_iiii:
.quad _Z44__device_stub__multithreads_normal_calculatePdS_iiii
.size _Z29multithreads_normal_calculatePdS_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nROE inverse %.2lf%%\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ROE normal %.2lf%%\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "num arr: %d\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "n: %d\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time: %.2f ms\n"
.size .L.str.4, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z30multithreads_inverse_calculatePdS_diiiii"
.size .L__unnamed_1, 45
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z29multithreads_normal_calculatePdS_iiii"
.size .L__unnamed_2, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.addrsig_sym _Z44__device_stub__multithreads_normal_calculatePdS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30multithreads_inverse_calculatePdS_diiiii
.addrsig_sym _Z29multithreads_normal_calculatePdS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000baab2_00000000-6_roe_calculate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii
.type _Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii, @function
_Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movsd %xmm0, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z30multithreads_inverse_calculatePdS_diiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii, .-_Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii
.globl _Z30multithreads_inverse_calculatePdS_diiiii
.type _Z30multithreads_inverse_calculatePdS_diiiii, @function
_Z30multithreads_inverse_calculatePdS_diiiii:
.LFB2083:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z58__device_stub__Z30multithreads_inverse_calculatePdS_diiiiiPdS_diiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z30multithreads_inverse_calculatePdS_diiiii, .-_Z30multithreads_inverse_calculatePdS_diiiii
.globl _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii
.type _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii, @function
_Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z29multithreads_normal_calculatePdS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii, .-_Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii
.globl _Z29multithreads_normal_calculatePdS_iiii
.type _Z29multithreads_normal_calculatePdS_iiii, @function
_Z29multithreads_normal_calculatePdS_iiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z29multithreads_normal_calculatePdS_iiii, .-_Z29multithreads_normal_calculatePdS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "\nROE inverse %.2lf%%\n"
.LC6:
.string "ROE normal %.2lf%%\n"
.LC7:
.string "num arr: %d\n"
.LC8:
.string "n: %d\n"
.LC9:
.string "Time: %.2f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r13
pushq %r12
pushq %rbx
subq $88, %rsp
.cfi_offset 13, -24
.cfi_offset 12, -32
.cfi_offset 3, -40
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq -77824(%rsp), %rax
.L20:
cmpq %rax, %rsp
je .L21
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L20
.L21:
subq $2112, %rsp
orq $0, 2104(%rsp)
movq %rsp, %rbx
leaq -77824(%rsp), %rax
.L23:
cmpq %rax, %rsp
je .L24
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L23
.L24:
subq $2112, %rsp
orq $0, 2104(%rsp)
movq %rsp, %r13
leaq -77824(%rsp), %rax
.L26:
cmpq %rax, %rsp
je .L27
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L26
.L27:
subq $2112, %rsp
orq $0, 2104(%rsp)
movq %rsp, %r12
movl $0, %eax
movsd .LC0(%rip), %xmm2
movsd .LC1(%rip), %xmm1
.L29:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm2, %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $9991, %rax
jne .L29
leaq -104(%rbp), %rdi
movl $79928, %esi
call cudaMalloc@PLT
leaq -96(%rbp), %rdi
movl $79928, %esi
call cudaMalloc@PLT
leaq -88(%rbp), %rdi
movl $79928, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $79928, %edx
movq %rbx, %rsi
movq -104(%rbp), %rdi
call cudaMemcpy@PLT
leaq -80(%rbp), %rdi
call cudaEventCreate@PLT
leaq -72(%rbp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq -80(%rbp), %rdi
call cudaEventRecord@PLT
movl $1024, -52(%rbp)
movl $1, -48(%rbp)
movl $1, -44(%rbp)
movl $10, -64(%rbp)
movl $1, -60(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -52(%rbp), %rdx
movl $1, %ecx
movq -64(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movl $0, %esi
movq -72(%rbp), %rdi
call cudaEventRecord@PLT
movq -72(%rbp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, -52(%rbp)
leaq -52(%rbp), %rdi
movq -72(%rbp), %rdx
movq -80(%rbp), %rsi
call cudaEventElapsedTime@PLT
movl $2, %ecx
movl $79928, %edx
movq -96(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $79928, %edx
movq -88(%rbp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq -104(%rbp), %rdi
call cudaFree@PLT
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -88(%rbp), %rdi
call cudaFree@PLT
movsd .LC3(%rip), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC5(%rip), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $999, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $9991, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd -52(%rbp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
leaq -24(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L34:
.cfi_restore_state
movl $-1, %r9d
movl $1, %r8d
movl $1, %ecx
movl $9991, %edx
movq -88(%rbp), %rsi
movq -104(%rbp), %rdi
call _Z55__device_stub__Z29multithreads_normal_calculatePdS_iiiiPdS_iiii
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC10:
.string "_Z29multithreads_normal_calculatePdS_iiii"
.align 8
.LC11:
.string "_Z30multithreads_inverse_calculatePdS_diiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z29multithreads_normal_calculatePdS_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z30multithreads_inverse_calculatePdS_diiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1717986918
.long 1069128089
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC3:
.long -1717986918
.long -1067910759
.align 8
.LC5:
.long 0
.long -1057463360
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "roe_calculate.hip"
.globl _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii # -- Begin function _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.p2align 4, 0x90
.type _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii,@function
_Z45__device_stub__multithreads_inverse_calculatePdS_diiiii: # @_Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z30multithreads_inverse_calculatePdS_diiiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii, .Lfunc_end0-_Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.cfi_endproc
# -- End function
.globl _Z44__device_stub__multithreads_normal_calculatePdS_iiii # -- Begin function _Z44__device_stub__multithreads_normal_calculatePdS_iiii
.p2align 4, 0x90
.type _Z44__device_stub__multithreads_normal_calculatePdS_iiii,@function
_Z44__device_stub__multithreads_normal_calculatePdS_iiii: # @_Z44__device_stub__multithreads_normal_calculatePdS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z29multithreads_normal_calculatePdS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end1:
.size _Z44__device_stub__multithreads_normal_calculatePdS_iiii, .Lfunc_end1-_Z44__device_stub__multithreads_normal_calculatePdS_iiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3fb999999999999a # double 0.10000000000000001
.LCPI2_1:
.quad 0x3ff0000000000000 # double 1
.LCPI2_2:
.quad 0xc058f9999999999a # double -99.900000000000005
.LCPI2_3:
.quad 0xc0f863c000000000 # double -99900
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $239976, %rsp # imm = 0x3A968
.cfi_def_cfa_offset 239984
xorl %eax, %eax
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
movsd .LCPI2_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm2, %xmm2
cvtsi2sd %eax, %xmm2
mulsd %xmm0, %xmm2
addsd %xmm1, %xmm2
movsd %xmm2, 176(%rsp,%rax,8)
incq %rax
cmpq $9991, %rax # imm = 0x2707
jne .LBB2_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $79928, %esi # imm = 0x13838
callq hipMalloc
leaq 56(%rsp), %rdi
movl $79928, %esi # imm = 0x13838
callq hipMalloc
leaq 16(%rsp), %rdi
movl $79928, %esi # imm = 0x13838
callq hipMalloc
movq 24(%rsp), %rdi
leaq 176(%rsp), %rsi
movl $79928, %edx # imm = 0x13838
movl $1, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967306, %rdi # imm = 0x10000000A
leaq 1014(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movl $9991, 44(%rsp) # imm = 0x2707
movl $1, 40(%rsp)
movl $1, 36(%rsp)
movl $-1, 32(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 44(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 36(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z29multithreads_normal_calculatePdS_iiii, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movl $0, 128(%rsp)
movq 48(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 128(%rsp), %rdi
callq hipEventElapsedTime
movq 56(%rsp), %rsi
leaq 160048(%rsp), %rdi
movl $79928, %edx # imm = 0x13838
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rsi
leaq 80112(%rsp), %rdi
movl $79928, %edx # imm = 0x13838
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str, %edi
movb $1, %al
callq printf
movsd .LCPI2_3(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
movl $.L.str.2, %edi
movl $999, %esi # imm = 0x3E7
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $9991, %esi # imm = 0x2707
xorl %eax, %eax
callq printf
movss 128(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $239976, %rsp # imm = 0x3A968
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30multithreads_inverse_calculatePdS_diiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z29multithreads_normal_calculatePdS_iiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30multithreads_inverse_calculatePdS_diiiii,@object # @_Z30multithreads_inverse_calculatePdS_diiiii
.section .rodata,"a",@progbits
.globl _Z30multithreads_inverse_calculatePdS_diiiii
.p2align 3, 0x0
_Z30multithreads_inverse_calculatePdS_diiiii:
.quad _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.size _Z30multithreads_inverse_calculatePdS_diiiii, 8
.type _Z29multithreads_normal_calculatePdS_iiii,@object # @_Z29multithreads_normal_calculatePdS_iiii
.globl _Z29multithreads_normal_calculatePdS_iiii
.p2align 3, 0x0
_Z29multithreads_normal_calculatePdS_iiii:
.quad _Z44__device_stub__multithreads_normal_calculatePdS_iiii
.size _Z29multithreads_normal_calculatePdS_iiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nROE inverse %.2lf%%\n"
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ROE normal %.2lf%%\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "num arr: %d\n"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "n: %d\n"
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time: %.2f ms\n"
.size .L.str.4, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z30multithreads_inverse_calculatePdS_diiiii"
.size .L__unnamed_1, 45
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z29multithreads_normal_calculatePdS_iiii"
.size .L__unnamed_2, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__multithreads_inverse_calculatePdS_diiiii
.addrsig_sym _Z44__device_stub__multithreads_normal_calculatePdS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30multithreads_inverse_calculatePdS_diiiii
.addrsig_sym _Z29multithreads_normal_calculatePdS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M)
{
float el = __fmul_rn(z[index], c1);
if (el > 4.97)
{
z[index] = 1.7159;
}
else if (el < -4.97)
{
z[index] = -1.7159;
}
else
{
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
}
}
} | code for sm_80
Function : _Z14tanhActivationiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FMUL R0, R0, 0.6666666865348815918 ; /* 0x3f2aaaab00007820 */
/* 0x004fc80000400000 */
/*0100*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x000e240000201800 */
/*0110*/ DSETP.GT.AND P0, PT, R4, c[0x2][0x0], PT ; /* 0x008000000400762a */
/* 0x001e1c0003f04000 */
/*0120*/ @P0 BRA 0x290 ; /* 0x0000016000000947 */
/* 0x001fea0003800000 */
/*0130*/ DSETP.GEU.AND P0, PT, R4, c[0x2][0x8], PT ; /* 0x008002000400762a */
/* 0x000e1c0003f0e000 */
/*0140*/ @!P0 BRA 0x260 ; /* 0x0000011000008947 */
/* 0x001fea0003800000 */
/*0150*/ MOV R5, 0x41e00000 ; /* 0x41e0000000057802 */
/* 0x000fe20000000f00 */
/*0160*/ FMUL R4, R0, R0 ; /* 0x0000000000047220 */
/* 0x000fc80000400000 */
/*0170*/ FFMA R5, R4, R5, 3150 ; /* 0x4544e00004057423 */
/* 0x000fc80000000005 */
/*0180*/ FFMA R5, R4, R5, 62370 ; /* 0x4773a20004057423 */
/* 0x000fc80000000005 */
/*0190*/ FFMA R6, R4.reuse, R5, 135135 ; /* 0x4803f7c004067423 */
/* 0x040fe40000000005 */
/*01a0*/ FADD R5, R4, 378 ; /* 0x43bd000004057421 */
/* 0x000fc60000000000 */
/*01b0*/ FSETP.GEU.AND P0, PT, |R6|, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fe20003f0e200 */
/*01c0*/ FFMA R5, R4, R5, 17235 ; /* 0x4686a60004057423 */
/* 0x000fc80000000005 */
/*01d0*/ FFMA R5, R4, R5, 135135 ; /* 0x4803f7c004057423 */
/* 0x000fc80000000005 */
/*01e0*/ FMUL R0, R0, R5 ; /* 0x0000000500007220 */
/* 0x000fc80000400000 */
/*01f0*/ @!P0 FMUL R6, R6, 16777216 ; /* 0x4b80000006068820 */
/* 0x000fe40000400000 */
/*0200*/ @!P0 FMUL R0, R0, 16777216 ; /* 0x4b80000000008820 */
/* 0x000fe40000400000 */
/*0210*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000001000 */
/*0220*/ FMUL R7, R7, R0 ; /* 0x0000000007077220 */
/* 0x001fc80000400000 */
/*0230*/ FMUL R7, R7, 1.7158999443054199219 ; /* 0x3fdba29c07077820 */
/* 0x000fca0000400000 */
/*0240*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ MOV R5, 0xbfdba29c ; /* 0xbfdba29c00057802 */
/* 0x000fca0000000f00 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ MOV R5, 0x3fdba29c ; /* 0x3fdba29c00057802 */
/* 0x000fca0000000f00 */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M)
{
float el = __fmul_rn(z[index], c1);
if (el > 4.97)
{
z[index] = 1.7159;
}
else if (el < -4.97)
{
z[index] = -1.7159;
}
else
{
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
}
}
} | .file "tmpxft_000481e4_00000000-6_tanhActivation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14tanhActivationiiPfiiPf
.type _Z36__device_stub__Z14tanhActivationiiPfiiPf, @function
_Z36__device_stub__Z14tanhActivationiiPfiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14tanhActivationiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z14tanhActivationiiPfiiPf, .-_Z36__device_stub__Z14tanhActivationiiPfiiPf
.globl _Z14tanhActivationiiPf
.type _Z14tanhActivationiiPf, @function
_Z14tanhActivationiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14tanhActivationiiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14tanhActivationiiPf, .-_Z14tanhActivationiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14tanhActivationiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14tanhActivationiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M)
{
float el = __fmul_rn(z[index], c1);
if (el > 4.97)
{
z[index] = 1.7159;
}
else if (el < -4.97)
{
z[index] = -1.7159;
}
else
{
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M)
{
float el = __fmul_rn(z[index], c1);
if (el > 4.97)
{
z[index] = 1.7159;
}
else if (el < -4.97)
{
z[index] = -1.7159;
}
else
{
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M)
{
float el = __fmul_rn(z[index], c1);
if (el > 4.97)
{
z[index] = 1.7159;
}
else if (el < -4.97)
{
z[index] = -1.7159;
}
else
{
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14tanhActivationiiPf
.globl _Z14tanhActivationiiPf
.p2align 8
.type _Z14tanhActivationiiPf,@function
_Z14tanhActivationiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v5, 0x3fdba29c
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x4013e147
s_mov_b32 s0, 0xae147ae1
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, 0x3f2aaaab, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v4
v_cmpx_nlt_f64_e32 s[0:1], v[2:3]
s_cbranch_execz .LBB0_5
s_mov_b32 s1, 0xc013e147
v_mov_b32_e32 v5, 0xbfdba29c
v_cmp_ngt_f64_e32 vcc_lo, s[0:1], v[2:3]
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_f32_e32 v2, v4, v4
v_fmaak_f32 v3, v4, v4, 0x43bd0000
s_mov_b32 s1, 0x41e00000
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v5, s1, v2, 0x4544e000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v3, v2, v3, 0x4686a600
v_fmaak_f32 v5, v2, v5, 0x4773a200
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v3, v2, v3, 0x4803f7c0
v_dual_fmaak_f32 v2, v2, v5, 0x4803f7c0 :: v_dual_mul_f32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_mul_f32_e32 v5, 0x3fdba29c, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
global_store_b32 v[0:1], v5, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14tanhActivationiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14tanhActivationiiPf, .Lfunc_end0-_Z14tanhActivationiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14tanhActivationiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14tanhActivationiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// filename: eeTanh.cu
// a simple CUDA kernel to square the elements of a matrix
extern "C" // ensure function name to be exactly "eeTanh"
{
}
__global__ void tanhActivation(int N, int M, float *z)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int index = j*N + i;
float c1 = __fdividef(2.0, 3.0);
if (i < N && j < M)
{
float el = __fmul_rn(z[index], c1);
if (el > 4.97)
{
z[index] = 1.7159;
}
else if (el < -4.97)
{
z[index] = -1.7159;
}
else
{
float x2 = __fmul_rn(el, el);
float a = __fmul_rn(el, __fmaf_rn(x2, __fmaf_rn(x2, __fadd_rn(378.0, x2), 17235.0), 135135.0));
float b = __fmaf_rn(x2, __fmaf_rn(x2, __fmaf_rn(x2, 28.0, 3150.0), 62370.0), 135135.0);
float tanh = __fdividef(a, b);
z[index] = __fmul_rn(1.7159, tanh);
}
}
} | .text
.file "tanhActivation.hip"
.globl _Z29__device_stub__tanhActivationiiPf # -- Begin function _Z29__device_stub__tanhActivationiiPf
.p2align 4, 0x90
.type _Z29__device_stub__tanhActivationiiPf,@function
_Z29__device_stub__tanhActivationiiPf: # @_Z29__device_stub__tanhActivationiiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14tanhActivationiiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__tanhActivationiiPf, .Lfunc_end0-_Z29__device_stub__tanhActivationiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14tanhActivationiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14tanhActivationiiPf,@object # @_Z14tanhActivationiiPf
.section .rodata,"a",@progbits
.globl _Z14tanhActivationiiPf
.p2align 3, 0x0
_Z14tanhActivationiiPf:
.quad _Z29__device_stub__tanhActivationiiPf
.size _Z14tanhActivationiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14tanhActivationiiPf"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__tanhActivationiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14tanhActivationiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14tanhActivationiiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R3, R3, c[0x0][0x160], R0 ; /* 0x0000580003037a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fca00078e0202 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ FMUL R0, R0, 0.6666666865348815918 ; /* 0x3f2aaaab00007820 */
/* 0x004fc80000400000 */
/*0100*/ F2F.F64.F32 R4, R0 ; /* 0x0000000000047310 */
/* 0x000e240000201800 */
/*0110*/ DSETP.GT.AND P0, PT, R4, c[0x2][0x0], PT ; /* 0x008000000400762a */
/* 0x001e1c0003f04000 */
/*0120*/ @P0 BRA 0x290 ; /* 0x0000016000000947 */
/* 0x001fea0003800000 */
/*0130*/ DSETP.GEU.AND P0, PT, R4, c[0x2][0x8], PT ; /* 0x008002000400762a */
/* 0x000e1c0003f0e000 */
/*0140*/ @!P0 BRA 0x260 ; /* 0x0000011000008947 */
/* 0x001fea0003800000 */
/*0150*/ MOV R5, 0x41e00000 ; /* 0x41e0000000057802 */
/* 0x000fe20000000f00 */
/*0160*/ FMUL R4, R0, R0 ; /* 0x0000000000047220 */
/* 0x000fc80000400000 */
/*0170*/ FFMA R5, R4, R5, 3150 ; /* 0x4544e00004057423 */
/* 0x000fc80000000005 */
/*0180*/ FFMA R5, R4, R5, 62370 ; /* 0x4773a20004057423 */
/* 0x000fc80000000005 */
/*0190*/ FFMA R6, R4.reuse, R5, 135135 ; /* 0x4803f7c004067423 */
/* 0x040fe40000000005 */
/*01a0*/ FADD R5, R4, 378 ; /* 0x43bd000004057421 */
/* 0x000fc60000000000 */
/*01b0*/ FSETP.GEU.AND P0, PT, |R6|, 1.175494350822287508e-38, PT ; /* 0x008000000600780b */
/* 0x000fe20003f0e200 */
/*01c0*/ FFMA R5, R4, R5, 17235 ; /* 0x4686a60004057423 */
/* 0x000fc80000000005 */
/*01d0*/ FFMA R5, R4, R5, 135135 ; /* 0x4803f7c004057423 */
/* 0x000fc80000000005 */
/*01e0*/ FMUL R0, R0, R5 ; /* 0x0000000500007220 */
/* 0x000fc80000400000 */
/*01f0*/ @!P0 FMUL R6, R6, 16777216 ; /* 0x4b80000006068820 */
/* 0x000fe40000400000 */
/*0200*/ @!P0 FMUL R0, R0, 16777216 ; /* 0x4b80000000008820 */
/* 0x000fe40000400000 */
/*0210*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000001000 */
/*0220*/ FMUL R7, R7, R0 ; /* 0x0000000007077220 */
/* 0x001fc80000400000 */
/*0230*/ FMUL R7, R7, 1.7158999443054199219 ; /* 0x3fdba29c07077820 */
/* 0x000fca0000400000 */
/*0240*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ MOV R5, 0xbfdba29c ; /* 0xbfdba29c00057802 */
/* 0x000fca0000000f00 */
/*0270*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0280*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0290*/ MOV R5, 0x3fdba29c ; /* 0x3fdba29c00057802 */
/* 0x000fca0000000f00 */
/*02a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14tanhActivationiiPf
.globl _Z14tanhActivationiiPf
.p2align 8
.type _Z14tanhActivationiiPf,@function
_Z14tanhActivationiiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[4:5], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x8
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
v_mov_b32_e32 v5, 0x3fdba29c
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0x4013e147
s_mov_b32 s0, 0xae147ae1
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, 0x3f2aaaab, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[2:3], v4
v_cmpx_nlt_f64_e32 s[0:1], v[2:3]
s_cbranch_execz .LBB0_5
s_mov_b32 s1, 0xc013e147
v_mov_b32_e32 v5, 0xbfdba29c
v_cmp_ngt_f64_e32 vcc_lo, s[0:1], v[2:3]
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_f32_e32 v2, v4, v4
v_fmaak_f32 v3, v4, v4, 0x43bd0000
s_mov_b32 s1, 0x41e00000
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fmaak_f32 v5, s1, v2, 0x4544e000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v3, v2, v3, 0x4686a600
v_fmaak_f32 v5, v2, v5, 0x4773a200
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v3, v2, v3, 0x4803f7c0
v_dual_fmaak_f32 v2, v2, v5, 0x4803f7c0 :: v_dual_mul_f32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v4, null, v2, v2, v3
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
v_mul_f32_e32 v7, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v4, v7, v6
v_fmac_f32_e32 v7, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v4, -v4, v7, v6
v_div_fmas_f32 v4, v4, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v4, v2, v3
v_mul_f32_e32 v5, 0x3fdba29c, v2
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s0
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
global_store_b32 v[0:1], v5, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14tanhActivationiiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14tanhActivationiiPf, .Lfunc_end0-_Z14tanhActivationiiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14tanhActivationiiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14tanhActivationiiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000481e4_00000000-6_tanhActivation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14tanhActivationiiPfiiPf
.type _Z36__device_stub__Z14tanhActivationiiPfiiPf, @function
_Z36__device_stub__Z14tanhActivationiiPfiiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14tanhActivationiiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z14tanhActivationiiPfiiPf, .-_Z36__device_stub__Z14tanhActivationiiPfiiPf
.globl _Z14tanhActivationiiPf
.type _Z14tanhActivationiiPf, @function
_Z14tanhActivationiiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14tanhActivationiiPfiiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14tanhActivationiiPf, .-_Z14tanhActivationiiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14tanhActivationiiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14tanhActivationiiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tanhActivation.hip"
.globl _Z29__device_stub__tanhActivationiiPf # -- Begin function _Z29__device_stub__tanhActivationiiPf
.p2align 4, 0x90
.type _Z29__device_stub__tanhActivationiiPf,@function
_Z29__device_stub__tanhActivationiiPf: # @_Z29__device_stub__tanhActivationiiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14tanhActivationiiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__tanhActivationiiPf, .Lfunc_end0-_Z29__device_stub__tanhActivationiiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14tanhActivationiiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14tanhActivationiiPf,@object # @_Z14tanhActivationiiPf
.section .rodata,"a",@progbits
.globl _Z14tanhActivationiiPf
.p2align 3, 0x0
_Z14tanhActivationiiPf:
.quad _Z29__device_stub__tanhActivationiiPf
.size _Z14tanhActivationiiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14tanhActivationiiPf"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__tanhActivationiiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14tanhActivationiiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
// Initialize memory
__global__ void initVectors(int * a, int * b, int * c) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(; i < N; i += stride) {
a[i] = 2;
b[i] = 1;
c[i] = 0;
}
}
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nsys to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* EDIT: I made it run under 77 us :)
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int * a, int * b, int * c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; i < N; i += stride)
c[i] = 2 * a[i] + b[i];
}
int main()
{
int *a, *b, *c;
int size = N * sizeof (int); // The total number of bytes per vector
int deviceId;
cudaDeviceProp props;
cudaGetDevice(&deviceId);
cudaGetDeviceProperties(&props, deviceId);
checkCuda(cudaMallocManaged(&a, size));
checkCuda(cudaMallocManaged(&b, size));
checkCuda(cudaMallocManaged(&c, size));
int threads_per_block = props.warpSize * 8;
int number_of_blocks = props.multiProcessorCount * 32; // using stride is better than arbitrary blocks
// prefetch to gpu
checkCuda(cudaMemPrefetchAsync(a, size, deviceId));
checkCuda(cudaMemPrefetchAsync(b, size, deviceId));
checkCuda(cudaMemPrefetchAsync(c, size, deviceId));
initVectors <<< number_of_blocks, threads_per_block >>>( a, b, c );
checkCuda(cudaGetLastError());
checkCuda(cudaDeviceSynchronize());
saxpy <<< number_of_blocks, threads_per_block >>> ( a, b, c );
checkCuda(cudaGetLastError());
checkCuda(cudaDeviceSynchronize());
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
cudaFree( a ); cudaFree( b ); cudaFree( c );
} | code for sm_80
Function : _Z5saxpyPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x3fffff, PT ; /* 0x003fffff0300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x310 ; /* 0x0000028000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0120*/ IMAD.HI.U32 R6, R5, R7, R4 ; /* 0x0000000705067227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x3fffff, RZ ; /* 0x003fffff03057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fca00078e00ff */
/*0150*/ IADD3 R2, -R6, RZ, RZ ; /* 0x000000ff06027210 */
/* 0x000fca0007ffe1ff */
/*0160*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0190*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*01f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 BRA 0x300 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0230*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0240*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fca00078e0208 */
/*0250*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0260*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x0002a2000c1e1900 */
/*0270*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02a0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc800078e0208 */
/*02b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x002fe200078e0206 */
/*02c0*/ LEA R11, R10, R11, 0x1 ; /* 0x0000000b0a0b7211 */
/* 0x004fca00078e08ff */
/*02d0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*02e0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*02f0*/ @P0 BRA 0x250 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0320*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0330*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0208 */
/*0340*/ IMAD.WIDE R6, R3.reuse, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x0c0fe200078e0208 */
/*0350*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*0380*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x001fc800078e0206 */
/*0390*/ IMAD R19, R2, 0x2, R11 ; /* 0x0000000202137824 */
/* 0x004fe400078e020b */
/*03a0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*03f0*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0400*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fe200078e020c */
/*0410*/ LEA R21, R2, R17, 0x1 ; /* 0x0000001102157211 */
/* 0x004fca00078e08ff */
/*0420*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0430*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R23, [R6.64] ; /* 0x0000000406177981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0460*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*0470*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0206 */
/*0480*/ LEA R23, R2, R23, 0x1 ; /* 0x0000001702177211 */
/* 0x004fca00078e08ff */
/*0490*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000e68000c1e1900 */
/*04b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000e62000c1e1900 */
/*04c0*/ IMAD.WIDE R12, R0.reuse, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0210 */
/*04d0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04e0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04f0*/ ISETP.GE.AND P0, PT, R3, 0x400000, PT ; /* 0x004000000300780c */
/* 0x000fe40003f06270 */
/*0500*/ LEA R15, R8, R11, 0x1 ; /* 0x0000000b080f7211 */
/* 0x002fca00078e08ff */
/*0510*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001ec000c101904 */
/*0520*/ @!P0 BRA 0x320 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11initVectorsPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x3fffff, PT ; /* 0x003fffff0300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0120*/ IMAD.HI.U32 R6, R5, R7, R4 ; /* 0x0000000705067227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x3fffff, RZ ; /* 0x003fffff03057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fca00078e00ff */
/*0150*/ IADD3 R2, -R6, RZ, RZ ; /* 0x000000ff06027210 */
/* 0x000fca0007ffe1ff */
/*0160*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0190*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*01f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 BRA 0x310 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0220*/ HFMA2.MMA R11, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff0b7435 */
/* 0x000fe200000001ff */
/*0230*/ MOV R13, 0x1 ; /* 0x00000001000d7802 */
/* 0x000fe40000000f00 */
/*0240*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0250*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0270*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0280*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e2000c101904 */
/*0290*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe400078e0203 */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0003e8000c101904 */
/*02c0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0005e2000c101904 */
/*02d0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc800078e0208 */
/*02e0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x002fc800078e0206 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x004fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x004fe200000001ff */
/*0340*/ MOV R25, 0x2 ; /* 0x0000000200197802 */
/* 0x000fe20000000f00 */
/*0350*/ HFMA2.MMA R27, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff1b7435 */
/* 0x000fd000000001ff */
/*0360*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R6, R3.reuse, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x0c0fe200078e0208 */
/*0380*/ STG.E [R4.64], R25 ; /* 0x0000001904007986 */
/* 0x0001e6000c101904 */
/*0390*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fe200078e0208 */
/*03a0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e2000c101904 */
/*03b0*/ IADD3 R3, R0.reuse, R3, R0 ; /* 0x0000000300037210 */
/* 0x040fe40007ffe000 */
/*03c0*/ IMAD.WIDE R10, R0.reuse, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0204 */
/*03d0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x0005e2000c101904 */
/*03e0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc40007ffe000 */
/*03f0*/ IMAD.WIDE R12, R0.reuse, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0206 */
/*0400*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x0005e2000c101904 */
/*0410*/ ISETP.GE.AND P0, PT, R3, 0x400000, PT ; /* 0x004000000300780c */
/* 0x000fe40003f06270 */
/*0420*/ IMAD.WIDE R14, R0.reuse, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x040fe200078e0208 */
/*0430*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0005e6000c101904 */
/*0440*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x040fe200078e020a */
/*0450*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x0005e6000c101904 */
/*0460*/ IMAD.WIDE R18, R0.reuse, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x040fe200078e020c */
/*0470*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0005e6000c101904 */
/*0480*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*0490*/ STG.E [R18.64], R27 ; /* 0x0000001b12007986 */
/* 0x0005e6000c101904 */
/*04a0*/ IMAD.WIDE R4, R0.reuse, 0x4, R16 ; /* 0x0000000400047825 */
/* 0x041fe200078e0210 */
/*04b0*/ STG.E [R20.64], RZ ; /* 0x000000ff14007986 */
/* 0x0005e6000c101904 */
/*04c0*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x040fe200078e0212 */
/*04d0*/ STG.E [R4.64], R25 ; /* 0x0000001904007986 */
/* 0x0005e6000c101904 */
/*04e0*/ IMAD.WIDE R6, R0, 0x4, R20 ; /* 0x0000000400067825 */
/* 0x002fe200078e0214 */
/*04f0*/ STG.E [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0005e8000c101904 */
/*0500*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0005e2000c101904 */
/*0510*/ @!P0 BRA 0x330 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
// Initialize memory
__global__ void initVectors(int * a, int * b, int * c) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(; i < N; i += stride) {
a[i] = 2;
b[i] = 1;
c[i] = 0;
}
}
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nsys to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* EDIT: I made it run under 77 us :)
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int * a, int * b, int * c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; i < N; i += stride)
c[i] = 2 * a[i] + b[i];
}
int main()
{
int *a, *b, *c;
int size = N * sizeof (int); // The total number of bytes per vector
int deviceId;
cudaDeviceProp props;
cudaGetDevice(&deviceId);
cudaGetDeviceProperties(&props, deviceId);
checkCuda(cudaMallocManaged(&a, size));
checkCuda(cudaMallocManaged(&b, size));
checkCuda(cudaMallocManaged(&c, size));
int threads_per_block = props.warpSize * 8;
int number_of_blocks = props.multiProcessorCount * 32; // using stride is better than arbitrary blocks
// prefetch to gpu
checkCuda(cudaMemPrefetchAsync(a, size, deviceId));
checkCuda(cudaMemPrefetchAsync(b, size, deviceId));
checkCuda(cudaMemPrefetchAsync(c, size, deviceId));
initVectors <<< number_of_blocks, threads_per_block >>>( a, b, c );
checkCuda(cudaGetLastError());
checkCuda(cudaDeviceSynchronize());
saxpy <<< number_of_blocks, threads_per_block >>> ( a, b, c );
checkCuda(cudaGetLastError());
checkCuda(cudaDeviceSynchronize());
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
cudaFree( a ); cudaFree( b ); cudaFree( c );
} | .file "tmpxft_000d310c_00000000-6_04.challenge.saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9checkCuda9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: %s\n"
.section .text._Z9checkCuda9cudaError,"axG",@progbits,_Z9checkCuda9cudaError,comdat
.weak _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
testl %edi, %edi
jne .L6
.L4:
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.cfi_endproc
.LFE2057:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.text
.globl _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_
.type _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_, @function
_Z35__device_stub__Z11initVectorsPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11initVectorsPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_, .-_Z35__device_stub__Z11initVectorsPiS_S_PiS_S_
.globl _Z11initVectorsPiS_S_
.type _Z11initVectorsPiS_S_, @function
_Z11initVectorsPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11initVectorsPiS_S_, .-_Z11initVectorsPiS_S_
.globl _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
.type _Z28__device_stub__Z5saxpyPiS_S_PiS_S_, @function
_Z28__device_stub__Z5saxpyPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z28__device_stub__Z5saxpyPiS_S_PiS_S_, .-_Z28__device_stub__Z5saxpyPiS_S_PiS_S_
.globl _Z5saxpyPiS_S_
.type _Z5saxpyPiS_S_, @function
_Z5saxpyPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5saxpyPiS_S_, .-_Z5saxpyPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c[%d] = %d, "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1104, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 64(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 32(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl 372(%rsp), %eax
leal 0(,%rax,8), %ebp
movl 452(%rsp), %ebx
sall $5, %ebx
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl %ebp, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L24:
call cudaGetLastError@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl %ebp, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
call cudaGetLastError@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L26:
movq 32(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L26
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777196, %ebp
movl $4194299, %ebx
leaq .LC1(%rip), %r12
.L27:
movq 32(%rsp), %rax
movl (%rax,%rbp), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $4, %rbp
cmpl $4194304, %ebx
jne .L27
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $1104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_
jmp .L24
.L33:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
jmp .L25
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z5saxpyPiS_S_"
.LC4:
.string "_Z11initVectorsPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11initVectorsPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline cudaError_t checkCuda(cudaError_t result) {
if (result != cudaSuccess) {
printf("Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
return result;
}
// Initialize memory
__global__ void initVectors(int * a, int * b, int * c) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(; i < N; i += stride) {
a[i] = 2;
b[i] = 1;
c[i] = 0;
}
}
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nsys to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* EDIT: I made it run under 77 us :)
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int * a, int * b, int * c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; i < N; i += stride)
c[i] = 2 * a[i] + b[i];
}
int main()
{
int *a, *b, *c;
int size = N * sizeof (int); // The total number of bytes per vector
int deviceId;
cudaDeviceProp props;
cudaGetDevice(&deviceId);
cudaGetDeviceProperties(&props, deviceId);
checkCuda(cudaMallocManaged(&a, size));
checkCuda(cudaMallocManaged(&b, size));
checkCuda(cudaMallocManaged(&c, size));
int threads_per_block = props.warpSize * 8;
int number_of_blocks = props.multiProcessorCount * 32; // using stride is better than arbitrary blocks
// prefetch to gpu
checkCuda(cudaMemPrefetchAsync(a, size, deviceId));
checkCuda(cudaMemPrefetchAsync(b, size, deviceId));
checkCuda(cudaMemPrefetchAsync(c, size, deviceId));
initVectors <<< number_of_blocks, threads_per_block >>>( a, b, c );
checkCuda(cudaGetLastError());
checkCuda(cudaDeviceSynchronize());
saxpy <<< number_of_blocks, threads_per_block >>> ( a, b, c );
checkCuda(cudaGetLastError());
checkCuda(cudaDeviceSynchronize());
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
cudaFree( a ); cudaFree( b ); cudaFree( c );
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
// Initialize memory
__global__ void initVectors(int * a, int * b, int * c) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(; i < N; i += stride) {
a[i] = 2;
b[i] = 1;
c[i] = 0;
}
}
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nsys to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* EDIT: I made it run under 77 us :)
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int * a, int * b, int * c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; i < N; i += stride)
c[i] = 2 * a[i] + b[i];
}
int main()
{
int *a, *b, *c;
int size = N * sizeof (int); // The total number of bytes per vector
int deviceId;
hipDeviceProp_t props;
hipGetDevice(&deviceId);
hipGetDeviceProperties(&props, deviceId);
checkCuda(hipMallocManaged(&a, size));
checkCuda(hipMallocManaged(&b, size));
checkCuda(hipMallocManaged(&c, size));
int threads_per_block = props.warpSize * 8;
int number_of_blocks = props.multiProcessorCount * 32; // using stride is better than arbitrary blocks
// prefetch to gpu
checkCuda(hipMemPrefetchAsync(a, size, deviceId));
checkCuda(hipMemPrefetchAsync(b, size, deviceId));
checkCuda(hipMemPrefetchAsync(c, size, deviceId));
initVectors <<< number_of_blocks, threads_per_block >>>( a, b, c );
checkCuda(hipGetLastError());
checkCuda(hipDeviceSynchronize());
saxpy <<< number_of_blocks, threads_per_block >>> ( a, b, c );
checkCuda(hipGetLastError());
checkCuda(hipDeviceSynchronize());
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
hipFree( a ); hipFree( b ); hipFree( c );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
// Initialize memory
__global__ void initVectors(int * a, int * b, int * c) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(; i < N; i += stride) {
a[i] = 2;
b[i] = 1;
c[i] = 0;
}
}
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nsys to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* EDIT: I made it run under 77 us :)
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int * a, int * b, int * c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; i < N; i += stride)
c[i] = 2 * a[i] + b[i];
}
int main()
{
int *a, *b, *c;
int size = N * sizeof (int); // The total number of bytes per vector
int deviceId;
hipDeviceProp_t props;
hipGetDevice(&deviceId);
hipGetDeviceProperties(&props, deviceId);
checkCuda(hipMallocManaged(&a, size));
checkCuda(hipMallocManaged(&b, size));
checkCuda(hipMallocManaged(&c, size));
int threads_per_block = props.warpSize * 8;
int number_of_blocks = props.multiProcessorCount * 32; // using stride is better than arbitrary blocks
// prefetch to gpu
checkCuda(hipMemPrefetchAsync(a, size, deviceId));
checkCuda(hipMemPrefetchAsync(b, size, deviceId));
checkCuda(hipMemPrefetchAsync(c, size, deviceId));
initVectors <<< number_of_blocks, threads_per_block >>>( a, b, c );
checkCuda(hipGetLastError());
checkCuda(hipDeviceSynchronize());
saxpy <<< number_of_blocks, threads_per_block >>> ( a, b, c );
checkCuda(hipGetLastError());
checkCuda(hipDeviceSynchronize());
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
hipFree( a ); hipFree( b ); hipFree( c );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11initVectorsPiS_S_
.globl _Z11initVectorsPiS_S_
.p2align 8
.type _Z11initVectorsPiS_S_,@function
_Z11initVectorsPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x400000, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v0, 2 :: v_dual_mov_b32 v5, 0
v_mov_b32_e32 v4, 1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_add_nc_u32_e32 v1, s8, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0x3fffff, v1
v_add_co_u32 v2, s0, v2, s10
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[6:7], v0, off
global_store_b32 v[8:9], v4, off
global_store_b32 v[10:11], v5, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11initVectorsPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11initVectorsPiS_S_, .Lfunc_end0-_Z11initVectorsPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5saxpyPiS_S_
.globl _Z5saxpyPiS_S_
.p2align 8
.type _Z5saxpyPiS_S_,@function
_Z5saxpyPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x400000, v1
s_cbranch_execz .LBB1_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_lt_i32_e64 s0, 0x3fffff, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_lshl_add_u32 v0, v0, 1, v6
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5saxpyPiS_S_, .Lfunc_end1-_Z5saxpyPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11initVectorsPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11initVectorsPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#define N 2048 * 2048 // Number of elements in each vector
inline hipError_t checkCuda(hipError_t result) {
if (result != hipSuccess) {
printf("Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
return result;
}
// Initialize memory
__global__ void initVectors(int * a, int * b, int * c) {
int i = blockDim.x * blockIdx.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for(; i < N; i += stride) {
a[i] = 2;
b[i] = 1;
c[i] = 0;
}
}
/*
* Optimize this already-accelerated codebase. Work iteratively,
* and use nsys to support your work.
*
* Aim to profile `saxpy` (without modifying `N`) running under
* 20us.
*
* EDIT: I made it run under 77 us :)
*
* Some bugs have been placed in this codebase for your edification.
*/
__global__ void saxpy(int * a, int * b, int * c)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int stride = gridDim.x * blockDim.x;
for (; i < N; i += stride)
c[i] = 2 * a[i] + b[i];
}
int main()
{
int *a, *b, *c;
int size = N * sizeof (int); // The total number of bytes per vector
int deviceId;
hipDeviceProp_t props;
hipGetDevice(&deviceId);
hipGetDeviceProperties(&props, deviceId);
checkCuda(hipMallocManaged(&a, size));
checkCuda(hipMallocManaged(&b, size));
checkCuda(hipMallocManaged(&c, size));
int threads_per_block = props.warpSize * 8;
int number_of_blocks = props.multiProcessorCount * 32; // using stride is better than arbitrary blocks
// prefetch to gpu
checkCuda(hipMemPrefetchAsync(a, size, deviceId));
checkCuda(hipMemPrefetchAsync(b, size, deviceId));
checkCuda(hipMemPrefetchAsync(c, size, deviceId));
initVectors <<< number_of_blocks, threads_per_block >>>( a, b, c );
checkCuda(hipGetLastError());
checkCuda(hipDeviceSynchronize());
saxpy <<< number_of_blocks, threads_per_block >>> ( a, b, c );
checkCuda(hipGetLastError());
checkCuda(hipDeviceSynchronize());
// Print out the first and last 5 values of c for a quality check
for( int i = 0; i < 5; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
for( int i = N-5; i < N; ++i )
printf("c[%d] = %d, ", i, c[i]);
printf ("\n");
hipFree( a ); hipFree( b ); hipFree( c );
} | .text
.file "04.challenge.saxpy.hip"
.globl _Z26__device_stub__initVectorsPiS_S_ # -- Begin function _Z26__device_stub__initVectorsPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__initVectorsPiS_S_,@function
_Z26__device_stub__initVectorsPiS_S_: # @_Z26__device_stub__initVectorsPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11initVectorsPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__initVectorsPiS_S_, .Lfunc_end0-_Z26__device_stub__initVectorsPiS_S_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__saxpyPiS_S_ # -- Begin function _Z20__device_stub__saxpyPiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPiS_S_,@function
_Z20__device_stub__saxpyPiS_S_: # @_Z20__device_stub__saxpyPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__saxpyPiS_S_, .Lfunc_end1-_Z20__device_stub__saxpyPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1616, %rsp # imm = 0x650
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 144(%rsp), %rdi
callq hipGetDevicePropertiesR0600
leaq 32(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_2: # %_Z9checkCuda10hipError_t.exit
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_4: # %_Z9checkCuda10hipError_t.exit29
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_6: # %_Z9checkCuda10hipError_t.exit31
movl 452(%rsp), %ebp
movl 532(%rsp), %ebx
movq 32(%rsp), %rdi
movl 12(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
testl %eax, %eax
je .LBB2_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_8: # %_Z9checkCuda10hipError_t.exit33
movq 24(%rsp), %rdi
movl 12(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
testl %eax, %eax
je .LBB2_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_10: # %_Z9checkCuda10hipError_t.exit35
shll $3, %ebp
shll $5, %ebx
movq 16(%rsp), %rdi
movl 12(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
testl %eax, %eax
je .LBB2_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_12: # %_Z9checkCuda10hipError_t.exit37
movl %ebx, %ebx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %ebp, %r14d
orq %rax, %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11initVectorsPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipGetLastError
testl %eax, %eax
je .LBB2_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_16: # %_Z9checkCuda10hipError_t.exit39
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB2_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_18: # %_Z9checkCuda10hipError_t.exit41
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_20
# %bb.19:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_20:
callq hipGetLastError
testl %eax, %eax
je .LBB2_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_22: # %_Z9checkCuda10hipError_t.exit49
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB2_24
# %bb.23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_24: # %_Z9checkCuda10hipError_t.exit51.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_25: # %_Z9checkCuda10hipError_t.exit51
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB2_25
# %bb.26:
movl $10, %edi
callq putchar@PLT
movl $4194299, %ebx # imm = 0x3FFFFB
.p2align 4, 0x90
.LBB2_27: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4194304, %rbx # imm = 0x400000
jne .LBB2_27
# %bb.28:
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1616, %rsp # imm = 0x650
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11initVectorsPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11initVectorsPiS_S_,@object # @_Z11initVectorsPiS_S_
.section .rodata,"a",@progbits
.globl _Z11initVectorsPiS_S_
.p2align 3, 0x0
_Z11initVectorsPiS_S_:
.quad _Z26__device_stub__initVectorsPiS_S_
.size _Z11initVectorsPiS_S_, 8
.type _Z5saxpyPiS_S_,@object # @_Z5saxpyPiS_S_
.globl _Z5saxpyPiS_S_
.p2align 3, 0x0
_Z5saxpyPiS_S_:
.quad _Z20__device_stub__saxpyPiS_S_
.size _Z5saxpyPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d, "
.size .L.str, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: %s\n"
.size .L.str.2, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11initVectorsPiS_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5saxpyPiS_S_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__initVectorsPiS_S_
.addrsig_sym _Z20__device_stub__saxpyPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11initVectorsPiS_S_
.addrsig_sym _Z5saxpyPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x3fffff, PT ; /* 0x003fffff0300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0xc] ; /* 0x0000030000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x310 ; /* 0x0000028000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0120*/ IMAD.HI.U32 R6, R5, R7, R4 ; /* 0x0000000705067227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x3fffff, RZ ; /* 0x003fffff03057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fca00078e00ff */
/*0150*/ IADD3 R2, -R6, RZ, RZ ; /* 0x000000ff06027210 */
/* 0x000fca0007ffe1ff */
/*0160*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0190*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*01f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 BRA 0x300 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0230*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0240*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fca00078e0208 */
/*0250*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0260*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x0002a2000c1e1900 */
/*0270*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007ffe0ff */
/*0280*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0290*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02a0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc800078e0208 */
/*02b0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x002fe200078e0206 */
/*02c0*/ LEA R11, R10, R11, 0x1 ; /* 0x0000000b0a0b7211 */
/* 0x004fca00078e08ff */
/*02d0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e4000c101904 */
/*02e0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*02f0*/ @P0 BRA 0x250 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0320*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fd400000001ff */
/*0330*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0208 */
/*0340*/ IMAD.WIDE R6, R3.reuse, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x0c0fe200078e0208 */
/*0350*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0360*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fc800078e0208 */
/*0380*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x001fc800078e0206 */
/*0390*/ IMAD R19, R2, 0x2, R11 ; /* 0x0000000202137824 */
/* 0x004fe400078e020b */
/*03a0*/ IMAD.WIDE R10, R0, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x000fc600078e0204 */
/*03b0*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0001e8000c101904 */
/*03c0*/ LDG.E R2, [R10.64] ; /* 0x000000040a027981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*03f0*/ IMAD.WIDE R4, R0, 0x4, R10 ; /* 0x0000000400047825 */
/* 0x000fc800078e020a */
/*0400*/ IMAD.WIDE R6, R0, 0x4, R12 ; /* 0x0000000400067825 */
/* 0x000fe200078e020c */
/*0410*/ LEA R21, R2, R17, 0x1 ; /* 0x0000001102157211 */
/* 0x004fca00078e08ff */
/*0420*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0003e8000c101904 */
/*0430*/ LDG.E R2, [R4.64] ; /* 0x0000000404027981 */
/* 0x000ea8000c1e1900 */
/*0440*/ LDG.E R23, [R6.64] ; /* 0x0000000406177981 */
/* 0x000ea2000c1e1900 */
/*0450*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0460*/ IMAD.WIDE R8, R0, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x001fc800078e0204 */
/*0470*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0206 */
/*0480*/ LEA R23, R2, R23, 0x1 ; /* 0x0000001702177211 */
/* 0x004fca00078e08ff */
/*0490*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0001e8000c101904 */
/*04a0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000e68000c1e1900 */
/*04b0*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000e62000c1e1900 */
/*04c0*/ IMAD.WIDE R12, R0.reuse, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0210 */
/*04d0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04e0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc80007ffe000 */
/*04f0*/ ISETP.GE.AND P0, PT, R3, 0x400000, PT ; /* 0x004000000300780c */
/* 0x000fe40003f06270 */
/*0500*/ LEA R15, R8, R11, 0x1 ; /* 0x0000000b080f7211 */
/* 0x002fca00078e08ff */
/*0510*/ STG.E [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001ec000c101904 */
/*0520*/ @!P0 BRA 0x320 ; /* 0xfffffdf000008947 */
/* 0x000fea000383ffff */
/*0530*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0540*/ BRA 0x540; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11initVectorsPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x3fffff, PT ; /* 0x003fffff0300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x320 ; /* 0x0000029000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*00b0*/ IADD3 R7, RZ, -R0, RZ ; /* 0x80000000ff077210 */
/* 0x000fe40007ffe0ff */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fca0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fc800078e02ff */
/*0120*/ IMAD.HI.U32 R6, R5, R7, R4 ; /* 0x0000000705067227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x3fffff, RZ ; /* 0x003fffff03057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fca00078e00ff */
/*0150*/ IADD3 R2, -R6, RZ, RZ ; /* 0x000000ff06027210 */
/* 0x000fca0007ffe1ff */
/*0160*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0190*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*01f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 BRA 0x310 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0220*/ HFMA2.MMA R11, -RZ, RZ, 0, 1.1920928955078125e-07 ; /* 0x00000002ff0b7435 */
/* 0x000fe200000001ff */
/*0230*/ MOV R13, 0x1 ; /* 0x00000001000d7802 */
/* 0x000fe40000000f00 */
/*0240*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x000fc800078e0208 */
/*0250*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0260*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0270*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0280*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0001e2000c101904 */
/*0290*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe400078e0203 */
/*02a0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*02b0*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0003e8000c101904 */
/*02c0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0005e2000c101904 */
/*02d0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x001fc800078e0208 */
/*02e0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x002fc800078e0206 */
/*02f0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x004fe200078e0204 */
/*0300*/ @P0 BRA 0x270 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0330*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x004fe200000001ff */
/*0340*/ MOV R25, 0x2 ; /* 0x0000000200197802 */
/* 0x000fe20000000f00 */
/*0350*/ HFMA2.MMA R27, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff1b7435 */
/* 0x000fd000000001ff */
/*0360*/ IMAD.WIDE R4, R3, R8, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x000fc800078e0208 */
/*0370*/ IMAD.WIDE R6, R3.reuse, R8.reuse, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x0c0fe200078e0208 */
/*0380*/ STG.E [R4.64], R25 ; /* 0x0000001904007986 */
/* 0x0001e6000c101904 */
/*0390*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fe200078e0208 */
/*03a0*/ STG.E [R6.64], R27 ; /* 0x0000001b06007986 */
/* 0x0003e2000c101904 */
/*03b0*/ IADD3 R3, R0.reuse, R3, R0 ; /* 0x0000000300037210 */
/* 0x040fe40007ffe000 */
/*03c0*/ IMAD.WIDE R10, R0.reuse, 0x4, R4 ; /* 0x00000004000a7825 */
/* 0x040fe200078e0204 */
/*03d0*/ STG.E [R8.64], RZ ; /* 0x000000ff08007986 */
/* 0x0005e2000c101904 */
/*03e0*/ IADD3 R3, R0, R3, R0 ; /* 0x0000000300037210 */
/* 0x000fc40007ffe000 */
/*03f0*/ IMAD.WIDE R12, R0.reuse, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0206 */
/*0400*/ STG.E [R10.64], R25 ; /* 0x000000190a007986 */
/* 0x0005e2000c101904 */
/*0410*/ ISETP.GE.AND P0, PT, R3, 0x400000, PT ; /* 0x004000000300780c */
/* 0x000fe40003f06270 */
/*0420*/ IMAD.WIDE R14, R0.reuse, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x040fe200078e0208 */
/*0430*/ STG.E [R12.64], R27 ; /* 0x0000001b0c007986 */
/* 0x0005e6000c101904 */
/*0440*/ IMAD.WIDE R16, R0.reuse, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x040fe200078e020a */
/*0450*/ STG.E [R14.64], RZ ; /* 0x000000ff0e007986 */
/* 0x0005e6000c101904 */
/*0460*/ IMAD.WIDE R18, R0.reuse, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x040fe200078e020c */
/*0470*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0005e6000c101904 */
/*0480*/ IMAD.WIDE R20, R0.reuse, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x040fe200078e020e */
/*0490*/ STG.E [R18.64], R27 ; /* 0x0000001b12007986 */
/* 0x0005e6000c101904 */
/*04a0*/ IMAD.WIDE R4, R0.reuse, 0x4, R16 ; /* 0x0000000400047825 */
/* 0x041fe200078e0210 */
/*04b0*/ STG.E [R20.64], RZ ; /* 0x000000ff14007986 */
/* 0x0005e6000c101904 */
/*04c0*/ IMAD.WIDE R22, R0.reuse, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x040fe200078e0212 */
/*04d0*/ STG.E [R4.64], R25 ; /* 0x0000001904007986 */
/* 0x0005e6000c101904 */
/*04e0*/ IMAD.WIDE R6, R0, 0x4, R20 ; /* 0x0000000400067825 */
/* 0x002fe200078e0214 */
/*04f0*/ STG.E [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0005e8000c101904 */
/*0500*/ STG.E [R6.64], RZ ; /* 0x000000ff06007986 */
/* 0x0005e2000c101904 */
/*0510*/ @!P0 BRA 0x330 ; /* 0xfffffe1000008947 */
/* 0x000fea000383ffff */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11initVectorsPiS_S_
.globl _Z11initVectorsPiS_S_
.p2align 8
.type _Z11initVectorsPiS_S_,@function
_Z11initVectorsPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x400000, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
v_dual_mov_b32 v0, 2 :: v_dual_mov_b32 v5, 0
v_mov_b32_e32 v4, 1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v8, vcc_lo, s6, v2
v_add_nc_u32_e32 v1, s8, v1
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v10, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v11, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, 0x3fffff, v1
v_add_co_u32 v2, s0, v2, s10
v_add_co_ci_u32_e64 v3, s0, s11, v3, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[6:7], v0, off
global_store_b32 v[8:9], v4, off
global_store_b32 v[10:11], v5, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11initVectorsPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11initVectorsPiS_S_, .Lfunc_end0-_Z11initVectorsPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5saxpyPiS_S_
.globl _Z5saxpyPiS_S_
.p2align 8
.type _Z5saxpyPiS_S_,@function
_Z5saxpyPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x400000, v1
s_cbranch_execz .LBB1_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s8, s9, s8
s_ashr_i32 s9, s8, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[8:9], 2
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_add_nc_u32_e32 v1, s8, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v6, v[6:7], off
v_add_co_u32 v4, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, s10
v_cmp_lt_i32_e64 s0, 0x3fffff, v1
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s1, s0, s1
s_waitcnt vmcnt(0)
v_lshl_add_u32 v0, v0, 1, v6
global_store_b32 v[4:5], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5saxpyPiS_S_, .Lfunc_end1-_Z5saxpyPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11initVectorsPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11initVectorsPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d310c_00000000-6_04.challenge.saxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata._Z9checkCuda9cudaError.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: %s\n"
.section .text._Z9checkCuda9cudaError,"axG",@progbits,_Z9checkCuda9cudaError,comdat
.weak _Z9checkCuda9cudaError
.type _Z9checkCuda9cudaError, @function
_Z9checkCuda9cudaError:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %ebx
testl %edi, %edi
jne .L6
.L4:
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.cfi_endproc
.LFE2057:
.size _Z9checkCuda9cudaError, .-_Z9checkCuda9cudaError
.text
.globl _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_
.type _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_, @function
_Z35__device_stub__Z11initVectorsPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11initVectorsPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_, .-_Z35__device_stub__Z11initVectorsPiS_S_PiS_S_
.globl _Z11initVectorsPiS_S_
.type _Z11initVectorsPiS_S_, @function
_Z11initVectorsPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11initVectorsPiS_S_, .-_Z11initVectorsPiS_S_
.globl _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
.type _Z28__device_stub__Z5saxpyPiS_S_PiS_S_, @function
_Z28__device_stub__Z5saxpyPiS_S_PiS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z28__device_stub__Z5saxpyPiS_S_PiS_S_, .-_Z28__device_stub__Z5saxpyPiS_S_PiS_S_
.globl _Z5saxpyPiS_S_
.type _Z5saxpyPiS_S_, @function
_Z5saxpyPiS_S_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z5saxpyPiS_S_, .-_Z5saxpyPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "c[%d] = %d, "
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1104, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDevice@PLT
leaq 64(%rsp), %rdi
movl 12(%rsp), %esi
call cudaGetDeviceProperties_v2@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 24(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
leaq 32(%rsp), %rdi
movl $1, %edx
movl $16777216, %esi
call cudaMallocManaged@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl 372(%rsp), %eax
leal 0(,%rax,8), %ebp
movl 452(%rsp), %ebx
sall $5, %ebx
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 16(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 24(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $0, %ecx
movl 12(%rsp), %edx
movl $16777216, %esi
movq 32(%rsp), %rdi
call cudaMemPrefetchAsync@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl %ebp, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L24:
call cudaGetLastError@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl %ebp, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ebx, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L25:
call cudaGetLastError@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
call cudaDeviceSynchronize@PLT
movl %eax, %edi
call _Z9checkCuda9cudaError
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L26:
movq 32(%rsp), %rax
movl (%rax,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $5, %rbx
jne .L26
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777196, %ebp
movl $4194299, %ebx
leaq .LC1(%rip), %r12
.L27:
movq 32(%rsp), %rax
movl (%rax,%rbp), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
addq $4, %rbp
cmpl $4194304, %ebx
jne .L27
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $1104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z11initVectorsPiS_S_PiS_S_
jmp .L24
.L33:
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z5saxpyPiS_S_PiS_S_
jmp .L25
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z5saxpyPiS_S_"
.LC4:
.string "_Z11initVectorsPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11initVectorsPiS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "04.challenge.saxpy.hip"
.globl _Z26__device_stub__initVectorsPiS_S_ # -- Begin function _Z26__device_stub__initVectorsPiS_S_
.p2align 4, 0x90
.type _Z26__device_stub__initVectorsPiS_S_,@function
_Z26__device_stub__initVectorsPiS_S_: # @_Z26__device_stub__initVectorsPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11initVectorsPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__initVectorsPiS_S_, .Lfunc_end0-_Z26__device_stub__initVectorsPiS_S_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__saxpyPiS_S_ # -- Begin function _Z20__device_stub__saxpyPiS_S_
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPiS_S_,@function
_Z20__device_stub__saxpyPiS_S_: # @_Z20__device_stub__saxpyPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__saxpyPiS_S_, .Lfunc_end1-_Z20__device_stub__saxpyPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1616, %rsp # imm = 0x650
.cfi_def_cfa_offset 1648
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
movl 12(%rsp), %esi
leaq 144(%rsp), %rdi
callq hipGetDevicePropertiesR0600
leaq 32(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_2: # %_Z9checkCuda10hipError_t.exit
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_4: # %_Z9checkCuda10hipError_t.exit29
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_6: # %_Z9checkCuda10hipError_t.exit31
movl 452(%rsp), %ebp
movl 532(%rsp), %ebx
movq 32(%rsp), %rdi
movl 12(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
testl %eax, %eax
je .LBB2_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_8: # %_Z9checkCuda10hipError_t.exit33
movq 24(%rsp), %rdi
movl 12(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
testl %eax, %eax
je .LBB2_10
# %bb.9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_10: # %_Z9checkCuda10hipError_t.exit35
shll $3, %ebp
shll $5, %ebx
movq 16(%rsp), %rdi
movl 12(%rsp), %edx
movl $16777216, %esi # imm = 0x1000000
xorl %ecx, %ecx
callq hipMemPrefetchAsync
testl %eax, %eax
je .LBB2_12
# %bb.11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_12: # %_Z9checkCuda10hipError_t.exit37
movl %ebx, %ebx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rbx
movl %ebp, %r14d
orq %rax, %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11initVectorsPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
callq hipGetLastError
testl %eax, %eax
je .LBB2_16
# %bb.15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_16: # %_Z9checkCuda10hipError_t.exit39
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB2_18
# %bb.17:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_18: # %_Z9checkCuda10hipError_t.exit41
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_20
# %bb.19:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z5saxpyPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_20:
callq hipGetLastError
testl %eax, %eax
je .LBB2_22
# %bb.21:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_22: # %_Z9checkCuda10hipError_t.exit49
callq hipDeviceSynchronize
testl %eax, %eax
je .LBB2_24
# %bb.23:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB2_24: # %_Z9checkCuda10hipError_t.exit51.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_25: # %_Z9checkCuda10hipError_t.exit51
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $5, %rbx
jne .LBB2_25
# %bb.26:
movl $10, %edi
callq putchar@PLT
movl $4194299, %ebx # imm = 0x3FFFFB
.p2align 4, 0x90
.LBB2_27: # =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movl (%rax,%rbx,4), %edx
movl $.L.str, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $4194304, %rbx # imm = 0x400000
jne .LBB2_27
# %bb.28:
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1616, %rsp # imm = 0x650
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11initVectorsPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11initVectorsPiS_S_,@object # @_Z11initVectorsPiS_S_
.section .rodata,"a",@progbits
.globl _Z11initVectorsPiS_S_
.p2align 3, 0x0
_Z11initVectorsPiS_S_:
.quad _Z26__device_stub__initVectorsPiS_S_
.size _Z11initVectorsPiS_S_, 8
.type _Z5saxpyPiS_S_,@object # @_Z5saxpyPiS_S_
.globl _Z5saxpyPiS_S_
.p2align 3, 0x0
_Z5saxpyPiS_S_:
.quad _Z20__device_stub__saxpyPiS_S_
.size _Z5saxpyPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d, "
.size .L.str, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error: %s\n"
.size .L.str.2, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11initVectorsPiS_S_"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5saxpyPiS_S_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__initVectorsPiS_S_
.addrsig_sym _Z20__device_stub__saxpyPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11initVectorsPiS_S_
.addrsig_sym _Z5saxpyPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
values that belong in each bucket. In the above
example the histogram values would look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
next use an array to count the OFFSET and a copy of that OFFSET array.
This is done by taking the element value at each index of the
histogram and adding it to the value at the previous index.
OFFSET Original:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
OFFSET CHANGED IS JUST A
COPY OF OFFSET ORIGINAL.
OFFSET Changed:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
^ ^ ^
| | |
| | taken from 4th index in histogram plus previous (1+3)
| |
| taken from second index plus the first index (1+2)
|
taken from the first index in histogram (2)
The reason we create a copy is because later, when we
want to determine how to rearange the elements, we have
to decrement the values in OFFSET so they don't overwrite
each other but we must also remember the original OFFSET
values. This will become clearer later.
As you can see the numbers that repeat occur (like index 2
and 4-9) when its corresponding index in the histogram equals 0
so the value doesn't increase.
Now we need to iterate over ArrayVals again and look at
the OFFSET changed array index it corresponds with to determine
where it goes in the list. We'll create a second temporary
list so that we don't ruin the order of the elements in the
original ArrayVals. This can be done in parallel so we can
use a thread to look at each element of ArrayVals at once.
secondList[ArrayValsSize];
we will, for example, look at the first element in ArrayVals.
Its left most digit is 0 so we will look at index 0 in the
OFFSET changed array. We notice it has a value 2 so we can place this
number at the 2nd index of the secondList array we just created.
This would be index 1 because arrays start at 0. So whatever
number fills the OFFSET changed index we subtract 1 to determine the position
to insert into the secondList. After we input into the secondList
we want to decrement the value in OFFSET changed so that the next number
that checks can be placed in an empty spot and not overwrite
the numbers in the same bucket. This means index 0 of the OFFSET changed
array goes from 2 to 1. We do the same thing for the other three
elements in ArrayVals. 31's first digit is a 3 so look at index 3 in
OFFSET changed and we see that it gets placed at 4-1=3 index in the secondList.
Remember to decrement the value at OFFSET changed[3] which = 4 so it becomes 3.
continue this with the next value which is 04 which means we look at
OFFSET changed[0], because its left most digit is 0, which has a value of 1
because the value 2 was decremented when 09 was placed in secondList above
in line 75-78. Because the value is now 1 that means we insert 04 into
index 1-1=0 of secondList. We finish with value 18. OFFSET changed[1] (because its
left most bit is 1) has a value of 3 so we put 18 into secondList[2]
because 3-1 = 2. After every element has been properly inserted into secondList,
it should now look like this:
secondList:
04, 09, 18, 31
We can see that its sorted but the computer doensn't know that.
In order to be sure its sorted we iterate through the histogram
and check to see if each value is at most 1. So if any value
in histogram is greater than 1 then we can't be sure its sorted
because we don't know which threads finished first.
So next if we find a value in histogram that is greater than 1 we
look to that index but in the original OFFSET. So histogram[0] has
a value of 2 which means we look in the original OFFSET[0] to get
the value 2. This means we are working from the ranges of
0-2 in the secondList. so we create histogram and OFFSET again.
To do this we just use a recursion and basically repeate the process
above but now only working with elements 0 and 1 based on the range
provided. We want to do the same process as above but
on the next digit to the right. so we sort 04 and 09
by counting them into the histogram and finding the OFFSET just
like above in lines 15-30.
They will each look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1
OFFSET:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 2
We iterate over histogram and see if any values are
greater than 1. There are none so they must all be
sorted! so we iterate over histogram and when we
get to a value that is non 0 we can point to
secondList and overwrite those numbers with the
current numbers and they will be in the correct
order. histogram[4] is the first element with a
non 0 value. We were given ranges 0-2 from above
(see lines 103-106) so we start at 0 and point
to secondList[0] and insert 4. Then we continue
our iteration over histogram and get to 9 as the
next non 0 element. We can point to secondList[1]
to insert 9. We are done with this part so it will
return to the previous step which is line 102 where
it will continuing iterating over its histogram
looking for values greater than 1. Refer to the
histogram displayed on line 23 as displayed here:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
We branched off initially from histogram[0] because it
had a value greater than 1 but now we are back and can
continue. The rest of the elemnts contain either a 0 or 1
so don't need to be sorted anymore. This means secondList
contains the sorted array.
All that is left is to use threads for each element
of secondList and copy their value into the original
array ArrayVals because ArrayVals is the one that
was sent from the CPU that needs to go back to the CPU.
The array is sorted and we are done!
**************************************************/
//new
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// #define MAX 2147483647;
#define MAX 99;
unsigned int * valuesList;
unsigned int totalNumbers;
void printArray(int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
void printArrayU(unsigned int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
__global__ void radixSort(unsigned int* valuesList, int digit, int arraySize, int* histogram, int* mainOffset, int* mainOffsetAfter) {
// each element is corresponds to a bucket from 0-9
// each element initialized to 0.
// __shared__ int histogram[10];
// int OFFSETOriginal[10];
__shared__ int OFFSETChanged[10];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// take element in values at this instanced thread and find the digit
// we're looking for thats passed in and increment the corresponding element
// in the histogram
if (tid < arraySize)
atomicAdd(&histogram[valuesList[tid]/digit], 1);
__syncthreads();
// find offset values
// OFFSETOriginal[0] = histogram[0];
OFFSETChanged[0] = histogram[0];
// mainHistogram[0] = histogram[0]; // for testing purposes.
mainOffset[0] = histogram[0];
for (int i = 1; i < 10; i++) {
// mainHistogram[i] = histogram[i]; // for testing purposes.
// OFFSETOriginal[i] = OFFSETOriginal[i-1] + histogram[i];
OFFSETChanged[i] = OFFSETChanged[i-1] + histogram[i];
mainOffset[i] = OFFSETChanged[i];
}
// group numbers together by bucket
if (tid < arraySize) {
// get the value at this instanced threads id that corresponds to the value at its index in valuesList
int value = valuesList[tid];
// find the max index this threads value found from valueList by looking in its offsetbucket
int index = OFFSETChanged[valuesList[tid]/digit] - 1;
// set every element in valuesList to 0.
// valuesList[tid] = 0;
// OFFSETChanged[valuesList[tid]/digit]--;
__syncthreads();
// place the values at their index found above as long as its empty (contains a 0)
// if its filled from another thread already placing a value there,
// go to the index before it and keep searching down until you find an empty spot
// while (valuesList[index] != 0) {
// atomicAdd(&OFFSETChanged[valuesList[tid]/digit], -1);
// index = OFFSETChanged[valuesList[tid]/digit] - 1;
// }
int previousValue = value;
valuesList[index] = value;
atomicAdd(&OFFSETChanged[previousValue/digit], -1);
// the list should now be sorted by the 10's digit
}
__syncthreads();
for (int i = 0; i < 10; i++) {
mainOffsetAfter[i] = OFFSETChanged[i];
}
return;
}
__device__ void bucketSort(int* values, int digit) {
}
int * histogram;
int * offset;
int * offsetAfter;
int main(int argc, char **argv) {
totalNumbers = atoi(argv[1]);
int histogramSize = 10;
valuesList = (unsigned int *)malloc(sizeof(unsigned int)*totalNumbers);
histogram = (int*)malloc(sizeof(int)*histogramSize);
offset = (int*)malloc(sizeof(int)*histogramSize);
offsetAfter = (int*)malloc(sizeof(int)*histogramSize);
unsigned int* d_valuesList;
int* d_histogram;
int* d_offset;
int* d_offsetAfter;
srand(1);
// generate totalNumbers random numbers for valuesList
for (int i = 0; i < totalNumbers; i++) {
valuesList[i] = (int) rand()%MAX;
// valuesList[i] = 26;
}
printf("VALUES BEFORE:\n");
printArrayU(valuesList, totalNumbers);
// fill histogram with 0's
for (int i = 0; i < histogramSize; i++) {
histogram[i] = 0;
offset[i] = 0;
offsetAfter[i] = 0;
}
cudaMalloc((void **) &d_valuesList, sizeof(unsigned int)*totalNumbers);
cudaMemcpy(d_valuesList, valuesList, sizeof(unsigned int)*totalNumbers, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_histogram, sizeof(int)*histogramSize);
cudaMemcpy(d_histogram, histogram, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_offset, sizeof(int)*histogramSize);
cudaMemcpy(d_offset, offset, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_offsetAfter, sizeof(int)*histogramSize);
cudaMemcpy(d_offsetAfter, offsetAfter, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
// digit should be the number we divide valuesList[i] by to find a particular digit.
// i.e. if we are looking for the 10's digit we divid by 10. The 100's digit divid
// by 100. 326 divide 100 returns 3. This example we limit our number size to only
// be 2 digits (max_rand defined at top to be 50) so we pass in 10 as our digit to
// find the left most digit, the 10's digit.
// dim3 dimBlock(totalNumbers,1);
dim3 dimGrid(totalNumbers/256 ,1, 1);
if (totalNumbers%256) dimGrid.x++;
dim3 dimBlock (256, 1, 1);
int digit = 10;
radixSort<<<(totalNumbers+255)/256, 256>>>(d_valuesList, digit, totalNumbers, d_histogram, d_offset, d_offsetAfter);
cudaMemcpy(valuesList, d_valuesList, sizeof(unsigned int)*totalNumbers, cudaMemcpyDeviceToHost);
cudaFree(d_valuesList);
cudaMemcpy(histogram, d_histogram, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_histogram);
cudaMemcpy(offset, d_offset, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_offset);
cudaMemcpy(offsetAfter, d_offsetAfter, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_offsetAfter);
printf("HISTOGRAM:\n");
printArray(histogram, histogramSize);
printf("OFFSET BEFORE:\n");
printArray(offset, histogramSize);
printf("OFFSET AFTER:\n");
printArray(offsetAfter, histogramSize);
// print valuesList
printf("VALUES AFTER:\n");
printArrayU(valuesList, totalNumbers);
return 0;
} | code for sm_80
Function : _Z9radixSortPjiiPiS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x230 ; /* 0x000001f000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fe400078e0200 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P3, PT, R5.reuse, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x040fe20003f66270 */
/*00a0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fd800078e0200 */
/*00b0*/ @P3 BRA 0x220 ; /* 0x0000016000003947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ I2F.U32.RP R9, c[0x0][0x168] ; /* 0x00005a0000097b06 */
/* 0x000e220000209000 */
/*00e0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f45070 */
/*00f0*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R6, R9, 0xffffffe, RZ ; /* 0x0ffffffe09067810 */
/* 0x001fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fca00078e00ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a07 */
/*0150*/ IMAD R11, R11, c[0x0][0x168], RZ ; /* 0x00005a000b0b7a24 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fcc00078e0006 */
/*0170*/ IMAD.HI.U32 R7, R7, R8, RZ ; /* 0x0000000807077227 */
/* 0x004fca00078e00ff */
/*0180*/ IADD3 R11, -R7, RZ, RZ ; /* 0x000000ff070b7210 */
/* 0x000fca0007ffe1ff */
/*0190*/ IMAD R8, R11, c[0x0][0x168], R8 ; /* 0x00005a000b087a24 */
/* 0x000fca00078e0208 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R8, R8, -c[0x0][0x168], RZ ; /* 0x80005a0008080a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff07aa12 */
/* 0x000fca00078e33ff */
/*0200*/ IMAD.WIDE.U32 R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fca00078e0000 */
/*0210*/ RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0001e4000c10e184 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x001fe200078e00ff */
/*0260*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fca0000000f00 */
/*0270*/ STG.E [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0041e8000c101904 */
/*0280*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD.IADD R9, R8, 0x1, R9 ; /* 0x0000000108097824 */
/* 0x004fca00078e0209 */
/*02a0*/ STG.E [R6.64+0x4], R9 ; /* 0x0000040906007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.IADD R10, R9, 0x1, R10 ; /* 0x00000001090a7824 */
/* 0x004fca00078e020a */
/*02d0*/ STG.E [R6.64+0x8], R10 ; /* 0x0000080a06007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IADD3 R11, R10, R11, RZ ; /* 0x0000000b0a0b7210 */
/* 0x004fca0007ffe0ff */
/*0300*/ STG.E [R6.64+0xc], R11 ; /* 0x00000c0b06007986 */
/* 0x0001e8000c101904 */
/*0310*/ LDG.E R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000ea4000c1e1900 */
/*0320*/ IMAD.IADD R12, R11, 0x1, R12 ; /* 0x000000010b0c7824 */
/* 0x004fca00078e020c */
/*0330*/ STG.E [R6.64+0x10], R12 ; /* 0x0000100c06007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R13, [R2.64+0x14] ; /* 0x00001404020d7981 */
/* 0x000ea4000c1e1900 */
/*0350*/ IMAD.IADD R13, R12, 0x1, R13 ; /* 0x000000010c0d7824 */
/* 0x004fca00078e020d */
/*0360*/ STG.E [R6.64+0x14], R13 ; /* 0x0000140d06007986 */
/* 0x0001e8000c101904 */
/*0370*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IADD3 R14, R13, R14, RZ ; /* 0x0000000e0d0e7210 */
/* 0x004fca0007ffe0ff */
/*0390*/ STG.E [R6.64+0x18], R14 ; /* 0x0000180e06007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMAD.IADD R15, R14, 0x1, R15 ; /* 0x000000010e0f7824 */
/* 0x004fca00078e020f */
/*03c0*/ STG.E [R6.64+0x1c], R15 ; /* 0x00001c0f06007986 */
/* 0x0001e8000c101904 */
/*03d0*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ IMAD.IADD R16, R15, 0x1, R16 ; /* 0x000000010f107824 */
/* 0x004fca00078e0210 */
/*03f0*/ STG.E [R6.64+0x20], R16 ; /* 0x0000201006007986 */
/* 0x0001e8000c101904 */
/*0400*/ LDG.E R17, [R2.64+0x24] ; /* 0x0000240402117981 */
/* 0x000ea8000c1e1900 */
/*0410*/ STS.128 [RZ], R8 ; /* 0x00000008ff007388 */
/* 0x0001e80000000c00 */
/*0420*/ STS.128 [0x10], R12 ; /* 0x0000100cff007388 */
/* 0x0001e20000000c00 */
/*0430*/ IADD3 R17, R16, R17, RZ ; /* 0x0000001110117210 */
/* 0x004fca0007ffe0ff */
/*0440*/ STG.E [R6.64+0x24], R17 ; /* 0x0000241106007986 */
/* 0x0001e8000c101904 */
/*0450*/ STS.64 [0x20], R16 ; /* 0x00002010ff007388 */
/* 0x0001e20000000a00 */
/*0460*/ @P3 BRA 0x7c0 ; /* 0x0000035000003947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0480*/ I2F.U32.RP R7, c[0x0][0x168] ; /* 0x00005a0000077b06 */
/* 0x001e220000209000 */
/*0490*/ IABS R8, c[0x0][0x168] ; /* 0x00005a0000087a13 */
/* 0x000fe20000000000 */
/*04a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fec0003800000 */
/*04b0*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000ef00000209400 */
/*04c0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e300000001000 */
/*04d0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x008fe20000001000 */
/*04e0*/ IADD3 R2, R7, 0xffffffe, RZ ; /* 0x0ffffffe07027810 */
/* 0x001fce0007ffe0ff */
/*04f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000e4000021f000 */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0510*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x008fc800078e0a03 */
/*0520*/ IMAD R5, R9, c[0x0][0x168], RZ ; /* 0x00005a0009057a24 */
/* 0x002fc800078e02ff */
/*0530*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fe200078e0002 */
/*0540*/ IADD3 R3, R6, 0xffffffe, RZ ; /* 0x0ffffffe06037810 */
/* 0x000fcc0007ffe0ff */
/*0550*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*0560*/ IMAD.HI.U32 R5, R5, R4.reuse, RZ ; /* 0x0000000405057227 */
/* 0x084fe200078e00ff */
/*0570*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*0580*/ IADD3 R7, -R5, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x000fca0007ffe1ff */
/*0590*/ IMAD R2, R7, c[0x0][0x168], R4 ; /* 0x00005a0007027a24 */
/* 0x000fe400078e0204 */
/*05a0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x001fc600078e0a03 */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06070 */
/*05c0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fd800078e02ff */
/*05d0*/ @P0 IADD3 R2, R2, -c[0x0][0x168], RZ ; /* 0x80005a0002020a10 */
/* 0x000fe40007ffe0ff */
/*05e0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f26070 */
/*0600*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0610*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003f05070 */
/*0620*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fe200078e0002 */
/*0630*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fe40000000f00 */
/*0640*/ LOP3.LUT R7, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff077a12 */
/* 0x000fc600078e33ff */
/*0650*/ IMAD.HI.U32 R2, R2, R3, RZ ; /* 0x0000000302027227 */
/* 0x000fe400078e00ff */
/*0660*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0670*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0a02 */
/*0680*/ SEL R5, R7, R5, !P0 ; /* 0x0000000507057207 */
/* 0x000fe40004000000 */
/*0690*/ IMAD R3, R8, R6, R3 ; /* 0x0000000608037224 */
/* 0x000fc800078e0203 */
/*06a0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e280000004800 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06c0*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f24070 */
/*06d0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a08 */
/*06e0*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fc80007ffe0ff */
/*06f0*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0700*/ LOP3.LUT R3, R4, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0004037a12 */
/* 0x000fc800078e3cff */
/*0710*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f46270 */
/*0720*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0730*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*0740*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*0750*/ IADD3 R3, R5, -0x1, RZ ; /* 0xffffffff05037810 */
/* 0x001fe20007ffe0ff */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, -0x1 ; /* 0xffffffffff057424 */
/* 0x000fe400078e00ff */
/*0770*/ @!P2 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff06a224 */
/* 0x000fe400078e0a06 */
/*0780*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0200 */
/*0790*/ SEL R6, R7, R6, !P0 ; /* 0x0000000607067207 */
/* 0x000fe40004000000 */
/*07a0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e8000c101904 */
/*07b0*/ ATOMS.ADD RZ, [R6.X4], R5 ; /* 0x0000000506ff738c */
/* 0x0001e40000004000 */
/*07c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07e0*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x001fe20000000f00 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fc800078e00ff */
/*0800*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e280000000c00 */
/*0810*/ LDS.128 R8, [0x10] ; /* 0x00001000ff087984 */
/* 0x000e680000000c00 */
/*0820*/ LDS.64 R12, [0x20] ; /* 0x00002000ff0c7984 */
/* 0x000ea80000000a00 */
/*0830*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe8000c101904 */
/*0840*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*0850*/ STG.E [R2.64+0x8], R6 ; /* 0x0000080602007986 */
/* 0x000fe8000c101904 */
/*0860*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x000fe8000c101904 */
/*0870*/ STG.E [R2.64+0x10], R8 ; /* 0x0000100802007986 */
/* 0x002fe8000c101904 */
/*0880*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe8000c101904 */
/*0890*/ STG.E [R2.64+0x18], R10 ; /* 0x0000180a02007986 */
/* 0x000fe8000c101904 */
/*08a0*/ STG.E [R2.64+0x1c], R11 ; /* 0x00001c0b02007986 */
/* 0x000fe8000c101904 */
/*08b0*/ STG.E [R2.64+0x20], R12 ; /* 0x0000200c02007986 */
/* 0x004fe8000c101904 */
/*08c0*/ STG.E [R2.64+0x24], R13 ; /* 0x0000240d02007986 */
/* 0x000fe2000c101904 */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
values that belong in each bucket. In the above
example the histogram values would look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
next use an array to count the OFFSET and a copy of that OFFSET array.
This is done by taking the element value at each index of the
histogram and adding it to the value at the previous index.
OFFSET Original:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
OFFSET CHANGED IS JUST A
COPY OF OFFSET ORIGINAL.
OFFSET Changed:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
^ ^ ^
| | |
| | taken from 4th index in histogram plus previous (1+3)
| |
| taken from second index plus the first index (1+2)
|
taken from the first index in histogram (2)
The reason we create a copy is because later, when we
want to determine how to rearange the elements, we have
to decrement the values in OFFSET so they don't overwrite
each other but we must also remember the original OFFSET
values. This will become clearer later.
As you can see the numbers that repeat occur (like index 2
and 4-9) when its corresponding index in the histogram equals 0
so the value doesn't increase.
Now we need to iterate over ArrayVals again and look at
the OFFSET changed array index it corresponds with to determine
where it goes in the list. We'll create a second temporary
list so that we don't ruin the order of the elements in the
original ArrayVals. This can be done in parallel so we can
use a thread to look at each element of ArrayVals at once.
secondList[ArrayValsSize];
we will, for example, look at the first element in ArrayVals.
Its left most digit is 0 so we will look at index 0 in the
OFFSET changed array. We notice it has a value 2 so we can place this
number at the 2nd index of the secondList array we just created.
This would be index 1 because arrays start at 0. So whatever
number fills the OFFSET changed index we subtract 1 to determine the position
to insert into the secondList. After we input into the secondList
we want to decrement the value in OFFSET changed so that the next number
that checks can be placed in an empty spot and not overwrite
the numbers in the same bucket. This means index 0 of the OFFSET changed
array goes from 2 to 1. We do the same thing for the other three
elements in ArrayVals. 31's first digit is a 3 so look at index 3 in
OFFSET changed and we see that it gets placed at 4-1=3 index in the secondList.
Remember to decrement the value at OFFSET changed[3] which = 4 so it becomes 3.
continue this with the next value which is 04 which means we look at
OFFSET changed[0], because its left most digit is 0, which has a value of 1
because the value 2 was decremented when 09 was placed in secondList above
in line 75-78. Because the value is now 1 that means we insert 04 into
index 1-1=0 of secondList. We finish with value 18. OFFSET changed[1] (because its
left most bit is 1) has a value of 3 so we put 18 into secondList[2]
because 3-1 = 2. After every element has been properly inserted into secondList,
it should now look like this:
secondList:
04, 09, 18, 31
We can see that its sorted but the computer doensn't know that.
In order to be sure its sorted we iterate through the histogram
and check to see if each value is at most 1. So if any value
in histogram is greater than 1 then we can't be sure its sorted
because we don't know which threads finished first.
So next if we find a value in histogram that is greater than 1 we
look to that index but in the original OFFSET. So histogram[0] has
a value of 2 which means we look in the original OFFSET[0] to get
the value 2. This means we are working from the ranges of
0-2 in the secondList. so we create histogram and OFFSET again.
To do this we just use a recursion and basically repeate the process
above but now only working with elements 0 and 1 based on the range
provided. We want to do the same process as above but
on the next digit to the right. so we sort 04 and 09
by counting them into the histogram and finding the OFFSET just
like above in lines 15-30.
They will each look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1
OFFSET:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 2
We iterate over histogram and see if any values are
greater than 1. There are none so they must all be
sorted! so we iterate over histogram and when we
get to a value that is non 0 we can point to
secondList and overwrite those numbers with the
current numbers and they will be in the correct
order. histogram[4] is the first element with a
non 0 value. We were given ranges 0-2 from above
(see lines 103-106) so we start at 0 and point
to secondList[0] and insert 4. Then we continue
our iteration over histogram and get to 9 as the
next non 0 element. We can point to secondList[1]
to insert 9. We are done with this part so it will
return to the previous step which is line 102 where
it will continuing iterating over its histogram
looking for values greater than 1. Refer to the
histogram displayed on line 23 as displayed here:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
We branched off initially from histogram[0] because it
had a value greater than 1 but now we are back and can
continue. The rest of the elemnts contain either a 0 or 1
so don't need to be sorted anymore. This means secondList
contains the sorted array.
All that is left is to use threads for each element
of secondList and copy their value into the original
array ArrayVals because ArrayVals is the one that
was sent from the CPU that needs to go back to the CPU.
The array is sorted and we are done!
**************************************************/
//new
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// #define MAX 2147483647;
#define MAX 99;
unsigned int * valuesList;
unsigned int totalNumbers;
void printArray(int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
void printArrayU(unsigned int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
__global__ void radixSort(unsigned int* valuesList, int digit, int arraySize, int* histogram, int* mainOffset, int* mainOffsetAfter) {
// each element is corresponds to a bucket from 0-9
// each element initialized to 0.
// __shared__ int histogram[10];
// int OFFSETOriginal[10];
__shared__ int OFFSETChanged[10];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// take element in values at this instanced thread and find the digit
// we're looking for thats passed in and increment the corresponding element
// in the histogram
if (tid < arraySize)
atomicAdd(&histogram[valuesList[tid]/digit], 1);
__syncthreads();
// find offset values
// OFFSETOriginal[0] = histogram[0];
OFFSETChanged[0] = histogram[0];
// mainHistogram[0] = histogram[0]; // for testing purposes.
mainOffset[0] = histogram[0];
for (int i = 1; i < 10; i++) {
// mainHistogram[i] = histogram[i]; // for testing purposes.
// OFFSETOriginal[i] = OFFSETOriginal[i-1] + histogram[i];
OFFSETChanged[i] = OFFSETChanged[i-1] + histogram[i];
mainOffset[i] = OFFSETChanged[i];
}
// group numbers together by bucket
if (tid < arraySize) {
// get the value at this instanced threads id that corresponds to the value at its index in valuesList
int value = valuesList[tid];
// find the max index this threads value found from valueList by looking in its offsetbucket
int index = OFFSETChanged[valuesList[tid]/digit] - 1;
// set every element in valuesList to 0.
// valuesList[tid] = 0;
// OFFSETChanged[valuesList[tid]/digit]--;
__syncthreads();
// place the values at their index found above as long as its empty (contains a 0)
// if its filled from another thread already placing a value there,
// go to the index before it and keep searching down until you find an empty spot
// while (valuesList[index] != 0) {
// atomicAdd(&OFFSETChanged[valuesList[tid]/digit], -1);
// index = OFFSETChanged[valuesList[tid]/digit] - 1;
// }
int previousValue = value;
valuesList[index] = value;
atomicAdd(&OFFSETChanged[previousValue/digit], -1);
// the list should now be sorted by the 10's digit
}
__syncthreads();
for (int i = 0; i < 10; i++) {
mainOffsetAfter[i] = OFFSETChanged[i];
}
return;
}
__device__ void bucketSort(int* values, int digit) {
}
int * histogram;
int * offset;
int * offsetAfter;
int main(int argc, char **argv) {
totalNumbers = atoi(argv[1]);
int histogramSize = 10;
valuesList = (unsigned int *)malloc(sizeof(unsigned int)*totalNumbers);
histogram = (int*)malloc(sizeof(int)*histogramSize);
offset = (int*)malloc(sizeof(int)*histogramSize);
offsetAfter = (int*)malloc(sizeof(int)*histogramSize);
unsigned int* d_valuesList;
int* d_histogram;
int* d_offset;
int* d_offsetAfter;
srand(1);
// generate totalNumbers random numbers for valuesList
for (int i = 0; i < totalNumbers; i++) {
valuesList[i] = (int) rand()%MAX;
// valuesList[i] = 26;
}
printf("VALUES BEFORE:\n");
printArrayU(valuesList, totalNumbers);
// fill histogram with 0's
for (int i = 0; i < histogramSize; i++) {
histogram[i] = 0;
offset[i] = 0;
offsetAfter[i] = 0;
}
cudaMalloc((void **) &d_valuesList, sizeof(unsigned int)*totalNumbers);
cudaMemcpy(d_valuesList, valuesList, sizeof(unsigned int)*totalNumbers, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_histogram, sizeof(int)*histogramSize);
cudaMemcpy(d_histogram, histogram, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_offset, sizeof(int)*histogramSize);
cudaMemcpy(d_offset, offset, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_offsetAfter, sizeof(int)*histogramSize);
cudaMemcpy(d_offsetAfter, offsetAfter, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
// digit should be the number we divide valuesList[i] by to find a particular digit.
// i.e. if we are looking for the 10's digit we divid by 10. The 100's digit divid
// by 100. 326 divide 100 returns 3. This example we limit our number size to only
// be 2 digits (max_rand defined at top to be 50) so we pass in 10 as our digit to
// find the left most digit, the 10's digit.
// dim3 dimBlock(totalNumbers,1);
dim3 dimGrid(totalNumbers/256 ,1, 1);
if (totalNumbers%256) dimGrid.x++;
dim3 dimBlock (256, 1, 1);
int digit = 10;
radixSort<<<(totalNumbers+255)/256, 256>>>(d_valuesList, digit, totalNumbers, d_histogram, d_offset, d_offsetAfter);
cudaMemcpy(valuesList, d_valuesList, sizeof(unsigned int)*totalNumbers, cudaMemcpyDeviceToHost);
cudaFree(d_valuesList);
cudaMemcpy(histogram, d_histogram, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_histogram);
cudaMemcpy(offset, d_offset, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_offset);
cudaMemcpy(offsetAfter, d_offsetAfter, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_offsetAfter);
printf("HISTOGRAM:\n");
printArray(histogram, histogramSize);
printf("OFFSET BEFORE:\n");
printArray(offset, histogramSize);
printf("OFFSET AFTER:\n");
printArray(offsetAfter, histogramSize);
// print valuesList
printf("VALUES AFTER:\n");
printArrayU(valuesList, totalNumbers);
return 0;
} | .file "tmpxft_000fa904_00000000-6_Radix_Sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[ "
.LC1:
.string "%d "
.LC2:
.string "]\n"
.text
.globl _Z10printArrayPii
.type _Z10printArrayPii, @function
_Z10printArrayPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L4
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC1(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10printArrayPii, .-_Z10printArrayPii
.globl _Z11printArrayUPji
.type _Z11printArrayUPji, @function
_Z11printArrayUPji:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L9
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC1(%rip), %rbp
.L10:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L10
.L9:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11printArrayUPji, .-_Z11printArrayUPji
.globl _Z10bucketSortPii
.type _Z10bucketSortPii, @function
_Z10bucketSortPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10bucketSortPii, .-_Z10bucketSortPii
.globl _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_
.type _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_, @function
_Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9radixSortPjiiPiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_, .-_Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_
.globl _Z9radixSortPjiiPiS0_S0_
.type _Z9radixSortPjiiPiS0_S0_, @function
_Z9radixSortPjiiPiS0_S0_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9radixSortPjiiPiS0_S0_, .-_Z9radixSortPjiiPiS0_S0_
.section .rodata.str1.1
.LC3:
.string "VALUES BEFORE:\n"
.LC4:
.string "HISTOGRAM:\n"
.LC5:
.string "OFFSET BEFORE:\n"
.LC6:
.string "OFFSET AFTER:\n"
.LC7:
.string "VALUES AFTER:\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, totalNumbers(%rip)
movl %eax, %eax
leaq 0(,%rax,4), %rdi
call malloc@PLT
movq %rax, valuesList(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, histogram(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, offset(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, offsetAfter(%rip)
movl $1, %edi
call srand@PLT
cmpl $0, totalNumbers(%rip)
je .L24
movl $0, %ebx
.L25:
call rand@PLT
movslq %eax, %rdx
imulq $-1518422781, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $6, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $99, %edx, %edx
subl %edx, %eax
movq valuesList(%rip), %rdx
movl %eax, (%rdx,%rbx,4)
addq $1, %rbx
cmpl totalNumbers(%rip), %ebx
jb .L25
.L24:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl totalNumbers(%rip), %esi
movq valuesList(%rip), %rdi
call _Z11printArrayUPji
movl $0, %eax
.L26:
movq histogram(%rip), %rdx
movl $0, (%rdx,%rax)
movq offset(%rip), %rdx
movl $0, (%rdx,%rax)
movq offsetAfter(%rip), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L26
movl totalNumbers(%rip), %esi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl totalNumbers(%rip), %edx
salq $2, %rdx
movl $1, %ecx
movq valuesList(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq histogram(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq offset(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq offsetAfter(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl totalNumbers(%rip), %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L27:
movl totalNumbers(%rip), %edx
salq $2, %rdx
movl $2, %ecx
movq (%rsp), %rsi
movq valuesList(%rip), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq histogram(%rip), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq offset(%rip), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq offsetAfter(%rip), %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %esi
movq histogram(%rip), %rdi
call _Z10printArrayPii
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %esi
movq offset(%rip), %rdi
call _Z10printArrayPii
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %esi
movq offsetAfter(%rip), %rdi
call _Z10printArrayPii
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl totalNumbers(%rip), %esi
movq valuesList(%rip), %rdi
call _Z11printArrayUPji
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 24(%rsp), %r9
movq 16(%rsp), %r8
movq 8(%rsp), %rcx
movl totalNumbers(%rip), %edx
movl $10, %esi
movq (%rsp), %rdi
call _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_
jmp .L27
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9radixSortPjiiPiS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9radixSortPjiiPiS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl offsetAfter
.bss
.align 8
.type offsetAfter, @object
.size offsetAfter, 8
offsetAfter:
.zero 8
.globl offset
.align 8
.type offset, @object
.size offset, 8
offset:
.zero 8
.globl histogram
.align 8
.type histogram, @object
.size histogram, 8
histogram:
.zero 8
.globl totalNumbers
.align 4
.type totalNumbers, @object
.size totalNumbers, 4
totalNumbers:
.zero 4
.globl valuesList
.align 8
.type valuesList, @object
.size valuesList, 8
valuesList:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
values that belong in each bucket. In the above
example the histogram values would look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
next use an array to count the OFFSET and a copy of that OFFSET array.
This is done by taking the element value at each index of the
histogram and adding it to the value at the previous index.
OFFSET Original:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
OFFSET CHANGED IS JUST A
COPY OF OFFSET ORIGINAL.
OFFSET Changed:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
^ ^ ^
| | |
| | taken from 4th index in histogram plus previous (1+3)
| |
| taken from second index plus the first index (1+2)
|
taken from the first index in histogram (2)
The reason we create a copy is because later, when we
want to determine how to rearange the elements, we have
to decrement the values in OFFSET so they don't overwrite
each other but we must also remember the original OFFSET
values. This will become clearer later.
As you can see the numbers that repeat occur (like index 2
and 4-9) when its corresponding index in the histogram equals 0
so the value doesn't increase.
Now we need to iterate over ArrayVals again and look at
the OFFSET changed array index it corresponds with to determine
where it goes in the list. We'll create a second temporary
list so that we don't ruin the order of the elements in the
original ArrayVals. This can be done in parallel so we can
use a thread to look at each element of ArrayVals at once.
secondList[ArrayValsSize];
we will, for example, look at the first element in ArrayVals.
Its left most digit is 0 so we will look at index 0 in the
OFFSET changed array. We notice it has a value 2 so we can place this
number at the 2nd index of the secondList array we just created.
This would be index 1 because arrays start at 0. So whatever
number fills the OFFSET changed index we subtract 1 to determine the position
to insert into the secondList. After we input into the secondList
we want to decrement the value in OFFSET changed so that the next number
that checks can be placed in an empty spot and not overwrite
the numbers in the same bucket. This means index 0 of the OFFSET changed
array goes from 2 to 1. We do the same thing for the other three
elements in ArrayVals. 31's first digit is a 3 so look at index 3 in
OFFSET changed and we see that it gets placed at 4-1=3 index in the secondList.
Remember to decrement the value at OFFSET changed[3] which = 4 so it becomes 3.
continue this with the next value which is 04 which means we look at
OFFSET changed[0], because its left most digit is 0, which has a value of 1
because the value 2 was decremented when 09 was placed in secondList above
in line 75-78. Because the value is now 1 that means we insert 04 into
index 1-1=0 of secondList. We finish with value 18. OFFSET changed[1] (because its
left most bit is 1) has a value of 3 so we put 18 into secondList[2]
because 3-1 = 2. After every element has been properly inserted into secondList,
it should now look like this:
secondList:
04, 09, 18, 31
We can see that its sorted but the computer doensn't know that.
In order to be sure its sorted we iterate through the histogram
and check to see if each value is at most 1. So if any value
in histogram is greater than 1 then we can't be sure its sorted
because we don't know which threads finished first.
So next if we find a value in histogram that is greater than 1 we
look to that index but in the original OFFSET. So histogram[0] has
a value of 2 which means we look in the original OFFSET[0] to get
the value 2. This means we are working from the ranges of
0-2 in the secondList. so we create histogram and OFFSET again.
To do this we just use a recursion and basically repeate the process
above but now only working with elements 0 and 1 based on the range
provided. We want to do the same process as above but
on the next digit to the right. so we sort 04 and 09
by counting them into the histogram and finding the OFFSET just
like above in lines 15-30.
They will each look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1
OFFSET:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 2
We iterate over histogram and see if any values are
greater than 1. There are none so they must all be
sorted! so we iterate over histogram and when we
get to a value that is non 0 we can point to
secondList and overwrite those numbers with the
current numbers and they will be in the correct
order. histogram[4] is the first element with a
non 0 value. We were given ranges 0-2 from above
(see lines 103-106) so we start at 0 and point
to secondList[0] and insert 4. Then we continue
our iteration over histogram and get to 9 as the
next non 0 element. We can point to secondList[1]
to insert 9. We are done with this part so it will
return to the previous step which is line 102 where
it will continuing iterating over its histogram
looking for values greater than 1. Refer to the
histogram displayed on line 23 as displayed here:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
We branched off initially from histogram[0] because it
had a value greater than 1 but now we are back and can
continue. The rest of the elemnts contain either a 0 or 1
so don't need to be sorted anymore. This means secondList
contains the sorted array.
All that is left is to use threads for each element
of secondList and copy their value into the original
array ArrayVals because ArrayVals is the one that
was sent from the CPU that needs to go back to the CPU.
The array is sorted and we are done!
**************************************************/
//new
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// #define MAX 2147483647;
#define MAX 99;
unsigned int * valuesList;
unsigned int totalNumbers;
void printArray(int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
void printArrayU(unsigned int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
__global__ void radixSort(unsigned int* valuesList, int digit, int arraySize, int* histogram, int* mainOffset, int* mainOffsetAfter) {
// each element is corresponds to a bucket from 0-9
// each element initialized to 0.
// __shared__ int histogram[10];
// int OFFSETOriginal[10];
__shared__ int OFFSETChanged[10];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// take element in values at this instanced thread and find the digit
// we're looking for thats passed in and increment the corresponding element
// in the histogram
if (tid < arraySize)
atomicAdd(&histogram[valuesList[tid]/digit], 1);
__syncthreads();
// find offset values
// OFFSETOriginal[0] = histogram[0];
OFFSETChanged[0] = histogram[0];
// mainHistogram[0] = histogram[0]; // for testing purposes.
mainOffset[0] = histogram[0];
for (int i = 1; i < 10; i++) {
// mainHistogram[i] = histogram[i]; // for testing purposes.
// OFFSETOriginal[i] = OFFSETOriginal[i-1] + histogram[i];
OFFSETChanged[i] = OFFSETChanged[i-1] + histogram[i];
mainOffset[i] = OFFSETChanged[i];
}
// group numbers together by bucket
if (tid < arraySize) {
// get the value at this instanced threads id that corresponds to the value at its index in valuesList
int value = valuesList[tid];
// find the max index this threads value found from valueList by looking in its offsetbucket
int index = OFFSETChanged[valuesList[tid]/digit] - 1;
// set every element in valuesList to 0.
// valuesList[tid] = 0;
// OFFSETChanged[valuesList[tid]/digit]--;
__syncthreads();
// place the values at their index found above as long as its empty (contains a 0)
// if its filled from another thread already placing a value there,
// go to the index before it and keep searching down until you find an empty spot
// while (valuesList[index] != 0) {
// atomicAdd(&OFFSETChanged[valuesList[tid]/digit], -1);
// index = OFFSETChanged[valuesList[tid]/digit] - 1;
// }
int previousValue = value;
valuesList[index] = value;
atomicAdd(&OFFSETChanged[previousValue/digit], -1);
// the list should now be sorted by the 10's digit
}
__syncthreads();
for (int i = 0; i < 10; i++) {
mainOffsetAfter[i] = OFFSETChanged[i];
}
return;
}
__device__ void bucketSort(int* values, int digit) {
}
int * histogram;
int * offset;
int * offsetAfter;
int main(int argc, char **argv) {
totalNumbers = atoi(argv[1]);
int histogramSize = 10;
valuesList = (unsigned int *)malloc(sizeof(unsigned int)*totalNumbers);
histogram = (int*)malloc(sizeof(int)*histogramSize);
offset = (int*)malloc(sizeof(int)*histogramSize);
offsetAfter = (int*)malloc(sizeof(int)*histogramSize);
unsigned int* d_valuesList;
int* d_histogram;
int* d_offset;
int* d_offsetAfter;
srand(1);
// generate totalNumbers random numbers for valuesList
for (int i = 0; i < totalNumbers; i++) {
valuesList[i] = (int) rand()%MAX;
// valuesList[i] = 26;
}
printf("VALUES BEFORE:\n");
printArrayU(valuesList, totalNumbers);
// fill histogram with 0's
for (int i = 0; i < histogramSize; i++) {
histogram[i] = 0;
offset[i] = 0;
offsetAfter[i] = 0;
}
cudaMalloc((void **) &d_valuesList, sizeof(unsigned int)*totalNumbers);
cudaMemcpy(d_valuesList, valuesList, sizeof(unsigned int)*totalNumbers, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_histogram, sizeof(int)*histogramSize);
cudaMemcpy(d_histogram, histogram, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_offset, sizeof(int)*histogramSize);
cudaMemcpy(d_offset, offset, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_offsetAfter, sizeof(int)*histogramSize);
cudaMemcpy(d_offsetAfter, offsetAfter, sizeof(int)*histogramSize, cudaMemcpyHostToDevice);
// digit should be the number we divide valuesList[i] by to find a particular digit.
// i.e. if we are looking for the 10's digit we divid by 10. The 100's digit divid
// by 100. 326 divide 100 returns 3. This example we limit our number size to only
// be 2 digits (max_rand defined at top to be 50) so we pass in 10 as our digit to
// find the left most digit, the 10's digit.
// dim3 dimBlock(totalNumbers,1);
dim3 dimGrid(totalNumbers/256 ,1, 1);
if (totalNumbers%256) dimGrid.x++;
dim3 dimBlock (256, 1, 1);
int digit = 10;
radixSort<<<(totalNumbers+255)/256, 256>>>(d_valuesList, digit, totalNumbers, d_histogram, d_offset, d_offsetAfter);
cudaMemcpy(valuesList, d_valuesList, sizeof(unsigned int)*totalNumbers, cudaMemcpyDeviceToHost);
cudaFree(d_valuesList);
cudaMemcpy(histogram, d_histogram, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_histogram);
cudaMemcpy(offset, d_offset, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_offset);
cudaMemcpy(offsetAfter, d_offsetAfter, sizeof(int)*histogramSize, cudaMemcpyDeviceToHost);
cudaFree(d_offsetAfter);
printf("HISTOGRAM:\n");
printArray(histogram, histogramSize);
printf("OFFSET BEFORE:\n");
printArray(offset, histogramSize);
printf("OFFSET AFTER:\n");
printArray(offsetAfter, histogramSize);
// print valuesList
printf("VALUES AFTER:\n");
printArrayU(valuesList, totalNumbers);
return 0;
} | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
values that belong in each bucket. In the above
example the histogram values would look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
next use an array to count the OFFSET and a copy of that OFFSET array.
This is done by taking the element value at each index of the
histogram and adding it to the value at the previous index.
OFFSET Original:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
OFFSET CHANGED IS JUST A
COPY OF OFFSET ORIGINAL.
OFFSET Changed:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
^ ^ ^
| | |
| | taken from 4th index in histogram plus previous (1+3)
| |
| taken from second index plus the first index (1+2)
|
taken from the first index in histogram (2)
The reason we create a copy is because later, when we
want to determine how to rearange the elements, we have
to decrement the values in OFFSET so they don't overwrite
each other but we must also remember the original OFFSET
values. This will become clearer later.
As you can see the numbers that repeat occur (like index 2
and 4-9) when its corresponding index in the histogram equals 0
so the value doesn't increase.
Now we need to iterate over ArrayVals again and look at
the OFFSET changed array index it corresponds with to determine
where it goes in the list. We'll create a second temporary
list so that we don't ruin the order of the elements in the
original ArrayVals. This can be done in parallel so we can
use a thread to look at each element of ArrayVals at once.
secondList[ArrayValsSize];
we will, for example, look at the first element in ArrayVals.
Its left most digit is 0 so we will look at index 0 in the
OFFSET changed array. We notice it has a value 2 so we can place this
number at the 2nd index of the secondList array we just created.
This would be index 1 because arrays start at 0. So whatever
number fills the OFFSET changed index we subtract 1 to determine the position
to insert into the secondList. After we input into the secondList
we want to decrement the value in OFFSET changed so that the next number
that checks can be placed in an empty spot and not overwrite
the numbers in the same bucket. This means index 0 of the OFFSET changed
array goes from 2 to 1. We do the same thing for the other three
elements in ArrayVals. 31's first digit is a 3 so look at index 3 in
OFFSET changed and we see that it gets placed at 4-1=3 index in the secondList.
Remember to decrement the value at OFFSET changed[3] which = 4 so it becomes 3.
continue this with the next value which is 04 which means we look at
OFFSET changed[0], because its left most digit is 0, which has a value of 1
because the value 2 was decremented when 09 was placed in secondList above
in line 75-78. Because the value is now 1 that means we insert 04 into
index 1-1=0 of secondList. We finish with value 18. OFFSET changed[1] (because its
left most bit is 1) has a value of 3 so we put 18 into secondList[2]
because 3-1 = 2. After every element has been properly inserted into secondList,
it should now look like this:
secondList:
04, 09, 18, 31
We can see that its sorted but the computer doensn't know that.
In order to be sure its sorted we iterate through the histogram
and check to see if each value is at most 1. So if any value
in histogram is greater than 1 then we can't be sure its sorted
because we don't know which threads finished first.
So next if we find a value in histogram that is greater than 1 we
look to that index but in the original OFFSET. So histogram[0] has
a value of 2 which means we look in the original OFFSET[0] to get
the value 2. This means we are working from the ranges of
0-2 in the secondList. so we create histogram and OFFSET again.
To do this we just use a recursion and basically repeate the process
above but now only working with elements 0 and 1 based on the range
provided. We want to do the same process as above but
on the next digit to the right. so we sort 04 and 09
by counting them into the histogram and finding the OFFSET just
like above in lines 15-30.
They will each look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1
OFFSET:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 2
We iterate over histogram and see if any values are
greater than 1. There are none so they must all be
sorted! so we iterate over histogram and when we
get to a value that is non 0 we can point to
secondList and overwrite those numbers with the
current numbers and they will be in the correct
order. histogram[4] is the first element with a
non 0 value. We were given ranges 0-2 from above
(see lines 103-106) so we start at 0 and point
to secondList[0] and insert 4. Then we continue
our iteration over histogram and get to 9 as the
next non 0 element. We can point to secondList[1]
to insert 9. We are done with this part so it will
return to the previous step which is line 102 where
it will continuing iterating over its histogram
looking for values greater than 1. Refer to the
histogram displayed on line 23 as displayed here:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
We branched off initially from histogram[0] because it
had a value greater than 1 but now we are back and can
continue. The rest of the elemnts contain either a 0 or 1
so don't need to be sorted anymore. This means secondList
contains the sorted array.
All that is left is to use threads for each element
of secondList and copy their value into the original
array ArrayVals because ArrayVals is the one that
was sent from the CPU that needs to go back to the CPU.
The array is sorted and we are done!
**************************************************/
//new
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// #define MAX 2147483647;
#define MAX 99;
unsigned int * valuesList;
unsigned int totalNumbers;
void printArray(int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
void printArrayU(unsigned int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
__global__ void radixSort(unsigned int* valuesList, int digit, int arraySize, int* histogram, int* mainOffset, int* mainOffsetAfter) {
// each element is corresponds to a bucket from 0-9
// each element initialized to 0.
// __shared__ int histogram[10];
// int OFFSETOriginal[10];
__shared__ int OFFSETChanged[10];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// take element in values at this instanced thread and find the digit
// we're looking for thats passed in and increment the corresponding element
// in the histogram
if (tid < arraySize)
atomicAdd(&histogram[valuesList[tid]/digit], 1);
__syncthreads();
// find offset values
// OFFSETOriginal[0] = histogram[0];
OFFSETChanged[0] = histogram[0];
// mainHistogram[0] = histogram[0]; // for testing purposes.
mainOffset[0] = histogram[0];
for (int i = 1; i < 10; i++) {
// mainHistogram[i] = histogram[i]; // for testing purposes.
// OFFSETOriginal[i] = OFFSETOriginal[i-1] + histogram[i];
OFFSETChanged[i] = OFFSETChanged[i-1] + histogram[i];
mainOffset[i] = OFFSETChanged[i];
}
// group numbers together by bucket
if (tid < arraySize) {
// get the value at this instanced threads id that corresponds to the value at its index in valuesList
int value = valuesList[tid];
// find the max index this threads value found from valueList by looking in its offsetbucket
int index = OFFSETChanged[valuesList[tid]/digit] - 1;
// set every element in valuesList to 0.
// valuesList[tid] = 0;
// OFFSETChanged[valuesList[tid]/digit]--;
__syncthreads();
// place the values at their index found above as long as its empty (contains a 0)
// if its filled from another thread already placing a value there,
// go to the index before it and keep searching down until you find an empty spot
// while (valuesList[index] != 0) {
// atomicAdd(&OFFSETChanged[valuesList[tid]/digit], -1);
// index = OFFSETChanged[valuesList[tid]/digit] - 1;
// }
int previousValue = value;
valuesList[index] = value;
atomicAdd(&OFFSETChanged[previousValue/digit], -1);
// the list should now be sorted by the 10's digit
}
__syncthreads();
for (int i = 0; i < 10; i++) {
mainOffsetAfter[i] = OFFSETChanged[i];
}
return;
}
__device__ void bucketSort(int* values, int digit) {
}
int * histogram;
int * offset;
int * offsetAfter;
int main(int argc, char **argv) {
totalNumbers = atoi(argv[1]);
int histogramSize = 10;
valuesList = (unsigned int *)malloc(sizeof(unsigned int)*totalNumbers);
histogram = (int*)malloc(sizeof(int)*histogramSize);
offset = (int*)malloc(sizeof(int)*histogramSize);
offsetAfter = (int*)malloc(sizeof(int)*histogramSize);
unsigned int* d_valuesList;
int* d_histogram;
int* d_offset;
int* d_offsetAfter;
srand(1);
// generate totalNumbers random numbers for valuesList
for (int i = 0; i < totalNumbers; i++) {
valuesList[i] = (int) rand()%MAX;
// valuesList[i] = 26;
}
printf("VALUES BEFORE:\n");
printArrayU(valuesList, totalNumbers);
// fill histogram with 0's
for (int i = 0; i < histogramSize; i++) {
histogram[i] = 0;
offset[i] = 0;
offsetAfter[i] = 0;
}
hipMalloc((void **) &d_valuesList, sizeof(unsigned int)*totalNumbers);
hipMemcpy(d_valuesList, valuesList, sizeof(unsigned int)*totalNumbers, hipMemcpyHostToDevice);
hipMalloc((void**) &d_histogram, sizeof(int)*histogramSize);
hipMemcpy(d_histogram, histogram, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
hipMalloc((void**) &d_offset, sizeof(int)*histogramSize);
hipMemcpy(d_offset, offset, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
hipMalloc((void**) &d_offsetAfter, sizeof(int)*histogramSize);
hipMemcpy(d_offsetAfter, offsetAfter, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
// digit should be the number we divide valuesList[i] by to find a particular digit.
// i.e. if we are looking for the 10's digit we divid by 10. The 100's digit divid
// by 100. 326 divide 100 returns 3. This example we limit our number size to only
// be 2 digits (max_rand defined at top to be 50) so we pass in 10 as our digit to
// find the left most digit, the 10's digit.
// dim3 dimBlock(totalNumbers,1);
dim3 dimGrid(totalNumbers/256 ,1, 1);
if (totalNumbers%256) dimGrid.x++;
dim3 dimBlock (256, 1, 1);
int digit = 10;
radixSort<<<(totalNumbers+255)/256, 256>>>(d_valuesList, digit, totalNumbers, d_histogram, d_offset, d_offsetAfter);
hipMemcpy(valuesList, d_valuesList, sizeof(unsigned int)*totalNumbers, hipMemcpyDeviceToHost);
hipFree(d_valuesList);
hipMemcpy(histogram, d_histogram, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_histogram);
hipMemcpy(offset, d_offset, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_offset);
hipMemcpy(offsetAfter, d_offsetAfter, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_offsetAfter);
printf("HISTOGRAM:\n");
printArray(histogram, histogramSize);
printf("OFFSET BEFORE:\n");
printArray(offset, histogramSize);
printf("OFFSET AFTER:\n");
printArray(offsetAfter, histogramSize);
// print valuesList
printf("VALUES AFTER:\n");
printArrayU(valuesList, totalNumbers);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
values that belong in each bucket. In the above
example the histogram values would look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
next use an array to count the OFFSET and a copy of that OFFSET array.
This is done by taking the element value at each index of the
histogram and adding it to the value at the previous index.
OFFSET Original:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
OFFSET CHANGED IS JUST A
COPY OF OFFSET ORIGINAL.
OFFSET Changed:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
^ ^ ^
| | |
| | taken from 4th index in histogram plus previous (1+3)
| |
| taken from second index plus the first index (1+2)
|
taken from the first index in histogram (2)
The reason we create a copy is because later, when we
want to determine how to rearange the elements, we have
to decrement the values in OFFSET so they don't overwrite
each other but we must also remember the original OFFSET
values. This will become clearer later.
As you can see the numbers that repeat occur (like index 2
and 4-9) when its corresponding index in the histogram equals 0
so the value doesn't increase.
Now we need to iterate over ArrayVals again and look at
the OFFSET changed array index it corresponds with to determine
where it goes in the list. We'll create a second temporary
list so that we don't ruin the order of the elements in the
original ArrayVals. This can be done in parallel so we can
use a thread to look at each element of ArrayVals at once.
secondList[ArrayValsSize];
we will, for example, look at the first element in ArrayVals.
Its left most digit is 0 so we will look at index 0 in the
OFFSET changed array. We notice it has a value 2 so we can place this
number at the 2nd index of the secondList array we just created.
This would be index 1 because arrays start at 0. So whatever
number fills the OFFSET changed index we subtract 1 to determine the position
to insert into the secondList. After we input into the secondList
we want to decrement the value in OFFSET changed so that the next number
that checks can be placed in an empty spot and not overwrite
the numbers in the same bucket. This means index 0 of the OFFSET changed
array goes from 2 to 1. We do the same thing for the other three
elements in ArrayVals. 31's first digit is a 3 so look at index 3 in
OFFSET changed and we see that it gets placed at 4-1=3 index in the secondList.
Remember to decrement the value at OFFSET changed[3] which = 4 so it becomes 3.
continue this with the next value which is 04 which means we look at
OFFSET changed[0], because its left most digit is 0, which has a value of 1
because the value 2 was decremented when 09 was placed in secondList above
in line 75-78. Because the value is now 1 that means we insert 04 into
index 1-1=0 of secondList. We finish with value 18. OFFSET changed[1] (because its
left most bit is 1) has a value of 3 so we put 18 into secondList[2]
because 3-1 = 2. After every element has been properly inserted into secondList,
it should now look like this:
secondList:
04, 09, 18, 31
We can see that its sorted but the computer doensn't know that.
In order to be sure its sorted we iterate through the histogram
and check to see if each value is at most 1. So if any value
in histogram is greater than 1 then we can't be sure its sorted
because we don't know which threads finished first.
So next if we find a value in histogram that is greater than 1 we
look to that index but in the original OFFSET. So histogram[0] has
a value of 2 which means we look in the original OFFSET[0] to get
the value 2. This means we are working from the ranges of
0-2 in the secondList. so we create histogram and OFFSET again.
To do this we just use a recursion and basically repeate the process
above but now only working with elements 0 and 1 based on the range
provided. We want to do the same process as above but
on the next digit to the right. so we sort 04 and 09
by counting them into the histogram and finding the OFFSET just
like above in lines 15-30.
They will each look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1
OFFSET:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 2
We iterate over histogram and see if any values are
greater than 1. There are none so they must all be
sorted! so we iterate over histogram and when we
get to a value that is non 0 we can point to
secondList and overwrite those numbers with the
current numbers and they will be in the correct
order. histogram[4] is the first element with a
non 0 value. We were given ranges 0-2 from above
(see lines 103-106) so we start at 0 and point
to secondList[0] and insert 4. Then we continue
our iteration over histogram and get to 9 as the
next non 0 element. We can point to secondList[1]
to insert 9. We are done with this part so it will
return to the previous step which is line 102 where
it will continuing iterating over its histogram
looking for values greater than 1. Refer to the
histogram displayed on line 23 as displayed here:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
We branched off initially from histogram[0] because it
had a value greater than 1 but now we are back and can
continue. The rest of the elemnts contain either a 0 or 1
so don't need to be sorted anymore. This means secondList
contains the sorted array.
All that is left is to use threads for each element
of secondList and copy their value into the original
array ArrayVals because ArrayVals is the one that
was sent from the CPU that needs to go back to the CPU.
The array is sorted and we are done!
**************************************************/
//new
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// #define MAX 2147483647;
#define MAX 99;
unsigned int * valuesList;
unsigned int totalNumbers;
void printArray(int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
void printArrayU(unsigned int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
__global__ void radixSort(unsigned int* valuesList, int digit, int arraySize, int* histogram, int* mainOffset, int* mainOffsetAfter) {
// each element is corresponds to a bucket from 0-9
// each element initialized to 0.
// __shared__ int histogram[10];
// int OFFSETOriginal[10];
__shared__ int OFFSETChanged[10];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// take element in values at this instanced thread and find the digit
// we're looking for thats passed in and increment the corresponding element
// in the histogram
if (tid < arraySize)
atomicAdd(&histogram[valuesList[tid]/digit], 1);
__syncthreads();
// find offset values
// OFFSETOriginal[0] = histogram[0];
OFFSETChanged[0] = histogram[0];
// mainHistogram[0] = histogram[0]; // for testing purposes.
mainOffset[0] = histogram[0];
for (int i = 1; i < 10; i++) {
// mainHistogram[i] = histogram[i]; // for testing purposes.
// OFFSETOriginal[i] = OFFSETOriginal[i-1] + histogram[i];
OFFSETChanged[i] = OFFSETChanged[i-1] + histogram[i];
mainOffset[i] = OFFSETChanged[i];
}
// group numbers together by bucket
if (tid < arraySize) {
// get the value at this instanced threads id that corresponds to the value at its index in valuesList
int value = valuesList[tid];
// find the max index this threads value found from valueList by looking in its offsetbucket
int index = OFFSETChanged[valuesList[tid]/digit] - 1;
// set every element in valuesList to 0.
// valuesList[tid] = 0;
// OFFSETChanged[valuesList[tid]/digit]--;
__syncthreads();
// place the values at their index found above as long as its empty (contains a 0)
// if its filled from another thread already placing a value there,
// go to the index before it and keep searching down until you find an empty spot
// while (valuesList[index] != 0) {
// atomicAdd(&OFFSETChanged[valuesList[tid]/digit], -1);
// index = OFFSETChanged[valuesList[tid]/digit] - 1;
// }
int previousValue = value;
valuesList[index] = value;
atomicAdd(&OFFSETChanged[previousValue/digit], -1);
// the list should now be sorted by the 10's digit
}
__syncthreads();
for (int i = 0; i < 10; i++) {
mainOffsetAfter[i] = OFFSETChanged[i];
}
return;
}
__device__ void bucketSort(int* values, int digit) {
}
int * histogram;
int * offset;
int * offsetAfter;
int main(int argc, char **argv) {
totalNumbers = atoi(argv[1]);
int histogramSize = 10;
valuesList = (unsigned int *)malloc(sizeof(unsigned int)*totalNumbers);
histogram = (int*)malloc(sizeof(int)*histogramSize);
offset = (int*)malloc(sizeof(int)*histogramSize);
offsetAfter = (int*)malloc(sizeof(int)*histogramSize);
unsigned int* d_valuesList;
int* d_histogram;
int* d_offset;
int* d_offsetAfter;
srand(1);
// generate totalNumbers random numbers for valuesList
for (int i = 0; i < totalNumbers; i++) {
valuesList[i] = (int) rand()%MAX;
// valuesList[i] = 26;
}
printf("VALUES BEFORE:\n");
printArrayU(valuesList, totalNumbers);
// fill histogram with 0's
for (int i = 0; i < histogramSize; i++) {
histogram[i] = 0;
offset[i] = 0;
offsetAfter[i] = 0;
}
hipMalloc((void **) &d_valuesList, sizeof(unsigned int)*totalNumbers);
hipMemcpy(d_valuesList, valuesList, sizeof(unsigned int)*totalNumbers, hipMemcpyHostToDevice);
hipMalloc((void**) &d_histogram, sizeof(int)*histogramSize);
hipMemcpy(d_histogram, histogram, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
hipMalloc((void**) &d_offset, sizeof(int)*histogramSize);
hipMemcpy(d_offset, offset, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
hipMalloc((void**) &d_offsetAfter, sizeof(int)*histogramSize);
hipMemcpy(d_offsetAfter, offsetAfter, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
// digit should be the number we divide valuesList[i] by to find a particular digit.
// i.e. if we are looking for the 10's digit we divid by 10. The 100's digit divid
// by 100. 326 divide 100 returns 3. This example we limit our number size to only
// be 2 digits (max_rand defined at top to be 50) so we pass in 10 as our digit to
// find the left most digit, the 10's digit.
// dim3 dimBlock(totalNumbers,1);
dim3 dimGrid(totalNumbers/256 ,1, 1);
if (totalNumbers%256) dimGrid.x++;
dim3 dimBlock (256, 1, 1);
int digit = 10;
radixSort<<<(totalNumbers+255)/256, 256>>>(d_valuesList, digit, totalNumbers, d_histogram, d_offset, d_offsetAfter);
hipMemcpy(valuesList, d_valuesList, sizeof(unsigned int)*totalNumbers, hipMemcpyDeviceToHost);
hipFree(d_valuesList);
hipMemcpy(histogram, d_histogram, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_histogram);
hipMemcpy(offset, d_offset, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_offset);
hipMemcpy(offsetAfter, d_offsetAfter, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_offsetAfter);
printf("HISTOGRAM:\n");
printArray(histogram, histogramSize);
printf("OFFSET BEFORE:\n");
printArray(offset, histogramSize);
printf("OFFSET AFTER:\n");
printArray(offsetAfter, histogramSize);
// print valuesList
printf("VALUES AFTER:\n");
printArrayU(valuesList, totalNumbers);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9radixSortPjiiPiS0_S0_
.globl _Z9radixSortPjiiPiS0_S0_
.p2align 8
.type _Z9radixSortPjiiPiS0_S0_,@function
_Z9radixSortPjiiPiS0_S0_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f32_u32_e32 v0, s4
v_cmp_gt_i32_e32 vcc_lo, s5, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s2, s8, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s9, v4, s2
s_sub_i32 s2, 0, s4
global_load_b32 v3, v[3:4], off
v_rcp_iflag_f32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_mul_lo_u32 v5, v4, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, 1, v4
v_subrev_nc_u32_e32 v6, s4, v3
v_cmp_le_u32_e64 s2, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v5, v4, v5, s2
v_mov_b32_e32 v4, 0
v_cndmask_b32_e64 v3, v3, v6, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v5
v_cmp_le_u32_e64 s2, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v5, v6, s2
v_mov_b32_e32 v5, 1
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s6, v3
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
global_atomic_add_u32 v[3:4], v5, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v3, 0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_load_b64 s[2:3], s[0:1], 0x18
global_load_b32 v4, v3, s[6:7]
s_mov_b64 s[10:11], 4
s_mov_b32 s5, 4
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v4, s[2:3]
.p2align 6
.LBB0_3:
s_add_u32 s12, s6, s10
s_addc_u32 s13, s7, s11
v_mov_b32_e32 v6, s5
global_load_b32 v5, v3, s[12:13]
s_add_u32 s12, s2, s10
s_addc_u32 s13, s3, s11
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_add_i32 s5, s5, 4
s_cmp_eq_u32 s10, 40
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
ds_store_b32 v6, v4
global_store_b32 v3, v4, s[12:13]
s_cbranch_scc0 .LBB0_3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_ashr_i32 s3, s4, 31
v_rcp_iflag_f32_e32 v0, v0
s_add_i32 s5, s4, s3
s_sub_i32 s6, 0, s4
s_xor_b32 s5, s5, s3
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v3, s6, v0
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v3, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v1, v3
v_add_nc_u32_e32 v1, v1, v3
s_waitcnt vmcnt(0)
v_mul_hi_u32 v0, v2, v0
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v0, s4
v_sub_nc_u32_e32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_dual_cndmask_b32 v3, v4, v3 :: v_dual_add_nc_u32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v0, v0, v6 :: v_dual_add_nc_u32 v7, v2, v5
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v7, v5
v_add_nc_u32_e32 v4, 1, v0
v_xor_b32_e32 v5, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_mul_hi_u32 v1, v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v0, 2, v0
v_mul_lo_u32 v3, v1, s5
ds_load_b32 v0, v0
v_add_nc_u32_e32 v4, 1, v1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_sub_nc_u32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v1, v4 :: v_dual_mov_b32 v4, -1
v_ashrrev_i32_e32 v1, 31, v0
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b32_e32 v3, 2, v3
global_store_b32 v[0:1], v2, off offset:-4
ds_add_u32 v3, v4
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_7:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 40
s_cbranch_scc0 .LBB0_7
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9radixSortPjiiPiS0_S0_
.amdhsa_group_segment_fixed_size 40
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9radixSortPjiiPiS0_S0_, .Lfunc_end0-_Z9radixSortPjiiPiS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 40
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9radixSortPjiiPiS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9radixSortPjiiPiS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //new
/***************** EXAMPLE ***********************
ArrayVals: 9, 31, 4, 18
padded ArrayVals: 09, 31, 04, 18
create histogram of size 10 for buckets 0-9
which each element initialized to 0. Use a thread
on each element of ArrayVals and increment the value
in the bucket it belongs to. This will count how many
values that belong in each bucket. In the above
example the histogram values would look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
next use an array to count the OFFSET and a copy of that OFFSET array.
This is done by taking the element value at each index of the
histogram and adding it to the value at the previous index.
OFFSET Original:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
OFFSET CHANGED IS JUST A
COPY OF OFFSET ORIGINAL.
OFFSET Changed:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
2 | 3 | 3 | 4 | 4 | 4 | 4 | 4 | 4 | 4
^ ^ ^
| | |
| | taken from 4th index in histogram plus previous (1+3)
| |
| taken from second index plus the first index (1+2)
|
taken from the first index in histogram (2)
The reason we create a copy is because later, when we
want to determine how to rearange the elements, we have
to decrement the values in OFFSET so they don't overwrite
each other but we must also remember the original OFFSET
values. This will become clearer later.
As you can see the numbers that repeat occur (like index 2
and 4-9) when its corresponding index in the histogram equals 0
so the value doesn't increase.
Now we need to iterate over ArrayVals again and look at
the OFFSET changed array index it corresponds with to determine
where it goes in the list. We'll create a second temporary
list so that we don't ruin the order of the elements in the
original ArrayVals. This can be done in parallel so we can
use a thread to look at each element of ArrayVals at once.
secondList[ArrayValsSize];
we will, for example, look at the first element in ArrayVals.
Its left most digit is 0 so we will look at index 0 in the
OFFSET changed array. We notice it has a value 2 so we can place this
number at the 2nd index of the secondList array we just created.
This would be index 1 because arrays start at 0. So whatever
number fills the OFFSET changed index we subtract 1 to determine the position
to insert into the secondList. After we input into the secondList
we want to decrement the value in OFFSET changed so that the next number
that checks can be placed in an empty spot and not overwrite
the numbers in the same bucket. This means index 0 of the OFFSET changed
array goes from 2 to 1. We do the same thing for the other three
elements in ArrayVals. 31's first digit is a 3 so look at index 3 in
OFFSET changed and we see that it gets placed at 4-1=3 index in the secondList.
Remember to decrement the value at OFFSET changed[3] which = 4 so it becomes 3.
continue this with the next value which is 04 which means we look at
OFFSET changed[0], because its left most digit is 0, which has a value of 1
because the value 2 was decremented when 09 was placed in secondList above
in line 75-78. Because the value is now 1 that means we insert 04 into
index 1-1=0 of secondList. We finish with value 18. OFFSET changed[1] (because its
left most bit is 1) has a value of 3 so we put 18 into secondList[2]
because 3-1 = 2. After every element has been properly inserted into secondList,
it should now look like this:
secondList:
04, 09, 18, 31
We can see that its sorted but the computer doensn't know that.
In order to be sure its sorted we iterate through the histogram
and check to see if each value is at most 1. So if any value
in histogram is greater than 1 then we can't be sure its sorted
because we don't know which threads finished first.
So next if we find a value in histogram that is greater than 1 we
look to that index but in the original OFFSET. So histogram[0] has
a value of 2 which means we look in the original OFFSET[0] to get
the value 2. This means we are working from the ranges of
0-2 in the secondList. so we create histogram and OFFSET again.
To do this we just use a recursion and basically repeate the process
above but now only working with elements 0 and 1 based on the range
provided. We want to do the same process as above but
on the next digit to the right. so we sort 04 and 09
by counting them into the histogram and finding the OFFSET just
like above in lines 15-30.
They will each look like this:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1
OFFSET:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9
--------------------------------------
0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 2
We iterate over histogram and see if any values are
greater than 1. There are none so they must all be
sorted! so we iterate over histogram and when we
get to a value that is non 0 we can point to
secondList and overwrite those numbers with the
current numbers and they will be in the correct
order. histogram[4] is the first element with a
non 0 value. We were given ranges 0-2 from above
(see lines 103-106) so we start at 0 and point
to secondList[0] and insert 4. Then we continue
our iteration over histogram and get to 9 as the
next non 0 element. We can point to secondList[1]
to insert 9. We are done with this part so it will
return to the previous step which is line 102 where
it will continuing iterating over its histogram
looking for values greater than 1. Refer to the
histogram displayed on line 23 as displayed here:
HISTOGRAM:
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 BUCKET
--------------------------------------
2 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 VALUES COUNTER
We branched off initially from histogram[0] because it
had a value greater than 1 but now we are back and can
continue. The rest of the elemnts contain either a 0 or 1
so don't need to be sorted anymore. This means secondList
contains the sorted array.
All that is left is to use threads for each element
of secondList and copy their value into the original
array ArrayVals because ArrayVals is the one that
was sent from the CPU that needs to go back to the CPU.
The array is sorted and we are done!
**************************************************/
//new
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
// #define MAX 2147483647;
#define MAX 99;
unsigned int * valuesList;
unsigned int totalNumbers;
void printArray(int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
void printArrayU(unsigned int * array, int size) {
printf("[ ");
for (int i = 0; i < size; i++) {
printf("%d ", array[i]);
}
printf("]\n");
}
__global__ void radixSort(unsigned int* valuesList, int digit, int arraySize, int* histogram, int* mainOffset, int* mainOffsetAfter) {
// each element is corresponds to a bucket from 0-9
// each element initialized to 0.
// __shared__ int histogram[10];
// int OFFSETOriginal[10];
__shared__ int OFFSETChanged[10];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// take element in values at this instanced thread and find the digit
// we're looking for thats passed in and increment the corresponding element
// in the histogram
if (tid < arraySize)
atomicAdd(&histogram[valuesList[tid]/digit], 1);
__syncthreads();
// find offset values
// OFFSETOriginal[0] = histogram[0];
OFFSETChanged[0] = histogram[0];
// mainHistogram[0] = histogram[0]; // for testing purposes.
mainOffset[0] = histogram[0];
for (int i = 1; i < 10; i++) {
// mainHistogram[i] = histogram[i]; // for testing purposes.
// OFFSETOriginal[i] = OFFSETOriginal[i-1] + histogram[i];
OFFSETChanged[i] = OFFSETChanged[i-1] + histogram[i];
mainOffset[i] = OFFSETChanged[i];
}
// group numbers together by bucket
if (tid < arraySize) {
// get the value at this instanced threads id that corresponds to the value at its index in valuesList
int value = valuesList[tid];
// find the max index this threads value found from valueList by looking in its offsetbucket
int index = OFFSETChanged[valuesList[tid]/digit] - 1;
// set every element in valuesList to 0.
// valuesList[tid] = 0;
// OFFSETChanged[valuesList[tid]/digit]--;
__syncthreads();
// place the values at their index found above as long as its empty (contains a 0)
// if its filled from another thread already placing a value there,
// go to the index before it and keep searching down until you find an empty spot
// while (valuesList[index] != 0) {
// atomicAdd(&OFFSETChanged[valuesList[tid]/digit], -1);
// index = OFFSETChanged[valuesList[tid]/digit] - 1;
// }
int previousValue = value;
valuesList[index] = value;
atomicAdd(&OFFSETChanged[previousValue/digit], -1);
// the list should now be sorted by the 10's digit
}
__syncthreads();
for (int i = 0; i < 10; i++) {
mainOffsetAfter[i] = OFFSETChanged[i];
}
return;
}
__device__ void bucketSort(int* values, int digit) {
}
int * histogram;
int * offset;
int * offsetAfter;
int main(int argc, char **argv) {
totalNumbers = atoi(argv[1]);
int histogramSize = 10;
valuesList = (unsigned int *)malloc(sizeof(unsigned int)*totalNumbers);
histogram = (int*)malloc(sizeof(int)*histogramSize);
offset = (int*)malloc(sizeof(int)*histogramSize);
offsetAfter = (int*)malloc(sizeof(int)*histogramSize);
unsigned int* d_valuesList;
int* d_histogram;
int* d_offset;
int* d_offsetAfter;
srand(1);
// generate totalNumbers random numbers for valuesList
for (int i = 0; i < totalNumbers; i++) {
valuesList[i] = (int) rand()%MAX;
// valuesList[i] = 26;
}
printf("VALUES BEFORE:\n");
printArrayU(valuesList, totalNumbers);
// fill histogram with 0's
for (int i = 0; i < histogramSize; i++) {
histogram[i] = 0;
offset[i] = 0;
offsetAfter[i] = 0;
}
hipMalloc((void **) &d_valuesList, sizeof(unsigned int)*totalNumbers);
hipMemcpy(d_valuesList, valuesList, sizeof(unsigned int)*totalNumbers, hipMemcpyHostToDevice);
hipMalloc((void**) &d_histogram, sizeof(int)*histogramSize);
hipMemcpy(d_histogram, histogram, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
hipMalloc((void**) &d_offset, sizeof(int)*histogramSize);
hipMemcpy(d_offset, offset, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
hipMalloc((void**) &d_offsetAfter, sizeof(int)*histogramSize);
hipMemcpy(d_offsetAfter, offsetAfter, sizeof(int)*histogramSize, hipMemcpyHostToDevice);
// digit should be the number we divide valuesList[i] by to find a particular digit.
// i.e. if we are looking for the 10's digit we divid by 10. The 100's digit divid
// by 100. 326 divide 100 returns 3. This example we limit our number size to only
// be 2 digits (max_rand defined at top to be 50) so we pass in 10 as our digit to
// find the left most digit, the 10's digit.
// dim3 dimBlock(totalNumbers,1);
dim3 dimGrid(totalNumbers/256 ,1, 1);
if (totalNumbers%256) dimGrid.x++;
dim3 dimBlock (256, 1, 1);
int digit = 10;
radixSort<<<(totalNumbers+255)/256, 256>>>(d_valuesList, digit, totalNumbers, d_histogram, d_offset, d_offsetAfter);
hipMemcpy(valuesList, d_valuesList, sizeof(unsigned int)*totalNumbers, hipMemcpyDeviceToHost);
hipFree(d_valuesList);
hipMemcpy(histogram, d_histogram, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_histogram);
hipMemcpy(offset, d_offset, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_offset);
hipMemcpy(offsetAfter, d_offsetAfter, sizeof(int)*histogramSize, hipMemcpyDeviceToHost);
hipFree(d_offsetAfter);
printf("HISTOGRAM:\n");
printArray(histogram, histogramSize);
printf("OFFSET BEFORE:\n");
printArray(offset, histogramSize);
printf("OFFSET AFTER:\n");
printArray(offsetAfter, histogramSize);
// print valuesList
printf("VALUES AFTER:\n");
printArrayU(valuesList, totalNumbers);
return 0;
} | .text
.file "Radix_Sort.hip"
.globl _Z10printArrayPii # -- Begin function _Z10printArrayPii
.p2align 4, 0x90
.type _Z10printArrayPii,@function
_Z10printArrayPii: # @_Z10printArrayPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $.Lstr.1, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z10printArrayPii, .Lfunc_end0-_Z10printArrayPii
.cfi_endproc
# -- End function
.globl _Z11printArrayUPji # -- Begin function _Z11printArrayUPji
.p2align 4, 0x90
.type _Z11printArrayUPji,@function
_Z11printArrayUPji: # @_Z11printArrayUPji
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.1, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z11printArrayUPji, .Lfunc_end1-_Z11printArrayUPji
.cfi_endproc
# -- End function
.globl _Z24__device_stub__radixSortPjiiPiS0_S0_ # -- Begin function _Z24__device_stub__radixSortPjiiPiS0_S0_
.p2align 4, 0x90
.type _Z24__device_stub__radixSortPjiiPiS0_S0_,@function
_Z24__device_stub__radixSortPjiiPiS0_S0_: # @_Z24__device_stub__radixSortPjiiPiS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9radixSortPjiiPiS0_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z24__device_stub__radixSortPjiiPiS0_S0_, .Lfunc_end2-_Z24__device_stub__radixSortPjiiPiS0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $176, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, totalNumbers(%rip)
movl %eax, %edi
shlq $2, %rdi
callq malloc
movq %rax, valuesList(%rip)
movl $40, %edi
callq malloc
movq %rax, histogram(%rip)
movl $40, %edi
callq malloc
movq %rax, offset(%rip)
movl $40, %edi
callq malloc
movq %rax, offsetAfter(%rip)
movl $1, %edi
callq srand
cmpl $0, totalNumbers(%rip)
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
subl %ecx, %eax
movq valuesList(%rip), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
movl totalNumbers(%rip), %eax
cmpq %rax, %rbx
jb .LBB3_2
.LBB3_3: # %._crit_edge
movl $.Lstr.2, %edi
callq puts@PLT
movq valuesList(%rip), %rbx
movl totalNumbers(%rip), %r14d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %r14d, %r14d
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader.i
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_5
.LBB3_6: # %_Z11printArrayUPji.exit
movl $.Lstr.1, %edi
callq puts@PLT
movq histogram(%rip), %rax
movq offset(%rip), %rcx
xorl %edx, %edx
movq offsetAfter(%rip), %rsi
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
movl $0, (%rax,%rdx,4)
movl $0, (%rcx,%rdx,4)
movl $0, (%rsi,%rdx,4)
incq %rdx
cmpq $10, %rdx
jne .LBB3_7
# %bb.8:
movl totalNumbers(%rip), %esi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movq valuesList(%rip), %rsi
movl totalNumbers(%rip), %edx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movq histogram(%rip), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movq offset(%rip), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movq offsetAfter(%rip), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movl $255, %edi
addl totalNumbers(%rip), %edi
shrl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 32(%rsp), %rax
movl totalNumbers(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
movq %rax, 120(%rsp)
movl $10, 44(%rsp)
movl %ecx, 40(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movq %rdi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 44(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9radixSortPjiiPiS0_S0_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq valuesList(%rip), %rdi
movq 32(%rsp), %rsi
movl totalNumbers(%rip), %edx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq histogram(%rip), %rdi
movq 24(%rsp), %rsi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq offset(%rip), %rdi
movq 16(%rsp), %rsi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq offsetAfter(%rip), %rdi
movq 8(%rsp), %rsi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr.3, %edi
callq puts@PLT
movq histogram(%rip), %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i34
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB3_11
# %bb.12: # %_Z10printArrayPii.exit
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movq offset(%rip), %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_13: # %.lr.ph.i40
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB3_13
# %bb.14: # %_Z10printArrayPii.exit45
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
movq offsetAfter(%rip), %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_15: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB3_15
# %bb.16: # %_Z10printArrayPii.exit52
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
movq valuesList(%rip), %rbx
movl totalNumbers(%rip), %r14d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %r14d, %r14d
jle .LBB3_19
# %bb.17: # %.lr.ph.preheader.i54
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_18: # %.lr.ph.i56
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_18
.LBB3_19: # %_Z11printArrayUPji.exit60
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9radixSortPjiiPiS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type valuesList,@object # @valuesList
.bss
.globl valuesList
.p2align 3, 0x0
valuesList:
.quad 0
.size valuesList, 8
.type totalNumbers,@object # @totalNumbers
.globl totalNumbers
.p2align 2, 0x0
totalNumbers:
.long 0 # 0x0
.size totalNumbers, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[ "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type _Z9radixSortPjiiPiS0_S0_,@object # @_Z9radixSortPjiiPiS0_S0_
.section .rodata,"a",@progbits
.globl _Z9radixSortPjiiPiS0_S0_
.p2align 3, 0x0
_Z9radixSortPjiiPiS0_S0_:
.quad _Z24__device_stub__radixSortPjiiPiS0_S0_
.size _Z9radixSortPjiiPiS0_S0_, 8
.type histogram,@object # @histogram
.bss
.globl histogram
.p2align 3, 0x0
histogram:
.quad 0
.size histogram, 8
.type offset,@object # @offset
.globl offset
.p2align 3, 0x0
offset:
.quad 0
.size offset, 8
.type offsetAfter,@object # @offsetAfter
.globl offsetAfter
.p2align 3, 0x0
offsetAfter:
.quad 0
.size offsetAfter, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9radixSortPjiiPiS0_S0_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "]"
.size .Lstr.1, 2
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "VALUES BEFORE:"
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "HISTOGRAM:"
.size .Lstr.3, 11
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "OFFSET BEFORE:"
.size .Lstr.4, 15
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "OFFSET AFTER:"
.size .Lstr.5, 14
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "VALUES AFTER:"
.size .Lstr.6, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__radixSortPjiiPiS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9radixSortPjiiPiS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9radixSortPjiiPiS0_S0_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x230 ; /* 0x000001f000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0060*/ MOV R3, c[0x0][0x174] ; /* 0x00005d0000037a02 */
/* 0x000fe20000000f00 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fe400078e0200 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fc600078e00ff */
/*0090*/ ISETP.GE.AND P3, PT, R5.reuse, c[0x0][0x16c], PT ; /* 0x00005b0005007a0c */
/* 0x040fe20003f66270 */
/*00a0*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fd800078e0200 */
/*00b0*/ @P3 BRA 0x220 ; /* 0x0000016000003947 */
/* 0x000fea0003800000 */
/*00c0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ I2F.U32.RP R9, c[0x0][0x168] ; /* 0x00005a0000097b06 */
/* 0x000e220000209000 */
/*00e0*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fce0003f45070 */
/*00f0*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x001e240000001000 */
/*0100*/ IADD3 R6, R9, 0xffffffe, RZ ; /* 0x0ffffffe09067810 */
/* 0x001fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fca00078e00ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x002fc800078e0a07 */
/*0150*/ IMAD R11, R11, c[0x0][0x168], RZ ; /* 0x00005a000b0b7a24 */
/* 0x000fc800078e02ff */
/*0160*/ IMAD.HI.U32 R7, R7, R11, R6 ; /* 0x0000000b07077227 */
/* 0x000fcc00078e0006 */
/*0170*/ IMAD.HI.U32 R7, R7, R8, RZ ; /* 0x0000000807077227 */
/* 0x004fca00078e00ff */
/*0180*/ IADD3 R11, -R7, RZ, RZ ; /* 0x000000ff070b7210 */
/* 0x000fca0007ffe1ff */
/*0190*/ IMAD R8, R11, c[0x0][0x168], R8 ; /* 0x00005a000b087a24 */
/* 0x000fca00078e0208 */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f06070 */
/*01b0*/ @P0 IADD3 R8, R8, -c[0x0][0x168], RZ ; /* 0x80005a0008080a10 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ ISETP.GE.U32.AND P1, PT, R8, c[0x0][0x168], PT ; /* 0x00005a0008007a0c */
/* 0x000fda0003f26070 */
/*01e0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @!P2 LOP3.LUT R7, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff07aa12 */
/* 0x000fca00078e33ff */
/*0200*/ IMAD.WIDE.U32 R6, R7, R0, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fca00078e0000 */
/*0210*/ RED.E.ADD.STRONG.GPU [R6.64], R9 ; /* 0x000000090600798e */
/* 0x0001e4000c10e184 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea2000c1e1900 */
/*0250*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff067624 */
/* 0x001fe200078e00ff */
/*0260*/ MOV R7, c[0x0][0x17c] ; /* 0x00005f0000077a02 */
/* 0x000fca0000000f00 */
/*0270*/ STG.E [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0041e8000c101904 */
/*0280*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD.IADD R9, R8, 0x1, R9 ; /* 0x0000000108097824 */
/* 0x004fca00078e0209 */
/*02a0*/ STG.E [R6.64+0x4], R9 ; /* 0x0000040906007986 */
/* 0x0001e8000c101904 */
/*02b0*/ LDG.E R10, [R2.64+0x8] ; /* 0x00000804020a7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ IMAD.IADD R10, R9, 0x1, R10 ; /* 0x00000001090a7824 */
/* 0x004fca00078e020a */
/*02d0*/ STG.E [R6.64+0x8], R10 ; /* 0x0000080a06007986 */
/* 0x0001e8000c101904 */
/*02e0*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IADD3 R11, R10, R11, RZ ; /* 0x0000000b0a0b7210 */
/* 0x004fca0007ffe0ff */
/*0300*/ STG.E [R6.64+0xc], R11 ; /* 0x00000c0b06007986 */
/* 0x0001e8000c101904 */
/*0310*/ LDG.E R12, [R2.64+0x10] ; /* 0x00001004020c7981 */
/* 0x000ea4000c1e1900 */
/*0320*/ IMAD.IADD R12, R11, 0x1, R12 ; /* 0x000000010b0c7824 */
/* 0x004fca00078e020c */
/*0330*/ STG.E [R6.64+0x10], R12 ; /* 0x0000100c06007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R13, [R2.64+0x14] ; /* 0x00001404020d7981 */
/* 0x000ea4000c1e1900 */
/*0350*/ IMAD.IADD R13, R12, 0x1, R13 ; /* 0x000000010c0d7824 */
/* 0x004fca00078e020d */
/*0360*/ STG.E [R6.64+0x14], R13 ; /* 0x0000140d06007986 */
/* 0x0001e8000c101904 */
/*0370*/ LDG.E R14, [R2.64+0x18] ; /* 0x00001804020e7981 */
/* 0x000ea4000c1e1900 */
/*0380*/ IADD3 R14, R13, R14, RZ ; /* 0x0000000e0d0e7210 */
/* 0x004fca0007ffe0ff */
/*0390*/ STG.E [R6.64+0x18], R14 ; /* 0x0000180e06007986 */
/* 0x0001e8000c101904 */
/*03a0*/ LDG.E R15, [R2.64+0x1c] ; /* 0x00001c04020f7981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMAD.IADD R15, R14, 0x1, R15 ; /* 0x000000010e0f7824 */
/* 0x004fca00078e020f */
/*03c0*/ STG.E [R6.64+0x1c], R15 ; /* 0x00001c0f06007986 */
/* 0x0001e8000c101904 */
/*03d0*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000ea4000c1e1900 */
/*03e0*/ IMAD.IADD R16, R15, 0x1, R16 ; /* 0x000000010f107824 */
/* 0x004fca00078e0210 */
/*03f0*/ STG.E [R6.64+0x20], R16 ; /* 0x0000201006007986 */
/* 0x0001e8000c101904 */
/*0400*/ LDG.E R17, [R2.64+0x24] ; /* 0x0000240402117981 */
/* 0x000ea8000c1e1900 */
/*0410*/ STS.128 [RZ], R8 ; /* 0x00000008ff007388 */
/* 0x0001e80000000c00 */
/*0420*/ STS.128 [0x10], R12 ; /* 0x0000100cff007388 */
/* 0x0001e20000000c00 */
/*0430*/ IADD3 R17, R16, R17, RZ ; /* 0x0000001110117210 */
/* 0x004fca0007ffe0ff */
/*0440*/ STG.E [R6.64+0x24], R17 ; /* 0x0000241106007986 */
/* 0x0001e8000c101904 */
/*0450*/ STS.64 [0x20], R16 ; /* 0x00002010ff007388 */
/* 0x0001e20000000a00 */
/*0460*/ @P3 BRA 0x7c0 ; /* 0x0000035000003947 */
/* 0x000fea0003800000 */
/*0470*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0002a2000c1e1900 */
/*0480*/ I2F.U32.RP R7, c[0x0][0x168] ; /* 0x00005a0000077b06 */
/* 0x001e220000209000 */
/*0490*/ IABS R8, c[0x0][0x168] ; /* 0x00005a0000087a13 */
/* 0x000fe20000000000 */
/*04a0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fec0003800000 */
/*04b0*/ I2F.RP R6, R8 ; /* 0x0000000800067306 */
/* 0x000ef00000209400 */
/*04c0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x001e300000001000 */
/*04d0*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x008fe20000001000 */
/*04e0*/ IADD3 R2, R7, 0xffffffe, RZ ; /* 0x0ffffffe07027810 */
/* 0x001fce0007ffe0ff */
/*04f0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000e4000021f000 */
/*0500*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0510*/ IMAD.MOV R9, RZ, RZ, -R3 ; /* 0x000000ffff097224 */
/* 0x008fc800078e0a03 */
/*0520*/ IMAD R5, R9, c[0x0][0x168], RZ ; /* 0x00005a0009057a24 */
/* 0x002fc800078e02ff */
/*0530*/ IMAD.HI.U32 R5, R3, R5, R2 ; /* 0x0000000503057227 */
/* 0x000fe200078e0002 */
/*0540*/ IADD3 R3, R6, 0xffffffe, RZ ; /* 0x0ffffffe06037810 */
/* 0x000fcc0007ffe0ff */
/*0550*/ F2I.FTZ.U32.TRUNC.NTZ R3, R3 ; /* 0x0000000300037305 */
/* 0x000e22000021f000 */
/*0560*/ IMAD.HI.U32 R5, R5, R4.reuse, RZ ; /* 0x0000000405057227 */
/* 0x084fe200078e00ff */
/*0570*/ IABS R6, R4 ; /* 0x0000000400067213 */
/* 0x000fc80000000000 */
/*0580*/ IADD3 R7, -R5, RZ, RZ ; /* 0x000000ff05077210 */
/* 0x000fca0007ffe1ff */
/*0590*/ IMAD R2, R7, c[0x0][0x168], R4 ; /* 0x00005a0007027a24 */
/* 0x000fe400078e0204 */
/*05a0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x001fc600078e0a03 */
/*05b0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f06070 */
/*05c0*/ IMAD R7, R7, R8, RZ ; /* 0x0000000807077224 */
/* 0x000fd800078e02ff */
/*05d0*/ @P0 IADD3 R2, R2, -c[0x0][0x168], RZ ; /* 0x80005a0002020a10 */
/* 0x000fe40007ffe0ff */
/*05e0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fe20003f26070 */
/*0600*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*0610*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fc60003f05070 */
/*0620*/ IMAD.HI.U32 R2, R3, R7, R2 ; /* 0x0000000703027227 */
/* 0x000fe200078e0002 */
/*0630*/ MOV R3, R6 ; /* 0x0000000600037202 */
/* 0x000fe40000000f00 */
/*0640*/ LOP3.LUT R7, RZ, c[0x0][0x168], RZ, 0x33, !PT ; /* 0x00005a00ff077a12 */
/* 0x000fc600078e33ff */
/*0650*/ IMAD.HI.U32 R2, R2, R3, RZ ; /* 0x0000000302027227 */
/* 0x000fe400078e00ff */
/*0660*/ @P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105051810 */
/* 0x000fe40007ffe0ff */
/*0670*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0a02 */
/*0680*/ SEL R5, R7, R5, !P0 ; /* 0x0000000507057207 */
/* 0x000fe40004000000 */
/*0690*/ IMAD R3, R8, R6, R3 ; /* 0x0000000608037224 */
/* 0x000fc800078e0203 */
/*06a0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e280000004800 */
/*06b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*06c0*/ ISETP.GT.U32.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f24070 */
/*06d0*/ @!P1 IMAD.IADD R3, R3, 0x1, -R8 ; /* 0x0000000103039824 */
/* 0x000fe200078e0a08 */
/*06e0*/ @!P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102029810 */
/* 0x000fc80007ffe0ff */
/*06f0*/ ISETP.GE.U32.AND P0, PT, R3, R8, PT ; /* 0x000000080300720c */
/* 0x000fe40003f06070 */
/*0700*/ LOP3.LUT R3, R4, c[0x0][0x168], RZ, 0x3c, !PT ; /* 0x00005a0004037a12 */
/* 0x000fc800078e3cff */
/*0710*/ ISETP.GE.AND P2, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fce0003f46270 */
/*0720*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fe40007ffe0ff */
/*0730*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fe40003f05270 */
/*0740*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fe40000000f00 */
/*0750*/ IADD3 R3, R5, -0x1, RZ ; /* 0xffffffff05037810 */
/* 0x001fe20007ffe0ff */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, -0x1 ; /* 0xffffffffff057424 */
/* 0x000fe400078e00ff */
/*0770*/ @!P2 IMAD.MOV R6, RZ, RZ, -R6 ; /* 0x000000ffff06a224 */
/* 0x000fe400078e0a06 */
/*0780*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc600078e0200 */
/*0790*/ SEL R6, R7, R6, !P0 ; /* 0x0000000607067207 */
/* 0x000fe40004000000 */
/*07a0*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e8000c101904 */
/*07b0*/ ATOMS.ADD RZ, [R6.X4], R5 ; /* 0x0000000506ff738c */
/* 0x0001e40000004000 */
/*07c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*07d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*07e0*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x001fe20000000f00 */
/*07f0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fc800078e00ff */
/*0800*/ LDS.128 R4, [RZ] ; /* 0x00000000ff047984 */
/* 0x000e280000000c00 */
/*0810*/ LDS.128 R8, [0x10] ; /* 0x00001000ff087984 */
/* 0x000e680000000c00 */
/*0820*/ LDS.64 R12, [0x20] ; /* 0x00002000ff0c7984 */
/* 0x000ea80000000a00 */
/*0830*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x001fe8000c101904 */
/*0840*/ STG.E [R2.64+0x4], R5 ; /* 0x0000040502007986 */
/* 0x000fe8000c101904 */
/*0850*/ STG.E [R2.64+0x8], R6 ; /* 0x0000080602007986 */
/* 0x000fe8000c101904 */
/*0860*/ STG.E [R2.64+0xc], R7 ; /* 0x00000c0702007986 */
/* 0x000fe8000c101904 */
/*0870*/ STG.E [R2.64+0x10], R8 ; /* 0x0000100802007986 */
/* 0x002fe8000c101904 */
/*0880*/ STG.E [R2.64+0x14], R9 ; /* 0x0000140902007986 */
/* 0x000fe8000c101904 */
/*0890*/ STG.E [R2.64+0x18], R10 ; /* 0x0000180a02007986 */
/* 0x000fe8000c101904 */
/*08a0*/ STG.E [R2.64+0x1c], R11 ; /* 0x00001c0b02007986 */
/* 0x000fe8000c101904 */
/*08b0*/ STG.E [R2.64+0x20], R12 ; /* 0x0000200c02007986 */
/* 0x004fe8000c101904 */
/*08c0*/ STG.E [R2.64+0x24], R13 ; /* 0x0000240d02007986 */
/* 0x000fe2000c101904 */
/*08d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x8e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9radixSortPjiiPiS0_S0_
.globl _Z9radixSortPjiiPiS0_S0_
.p2align 8
.type _Z9radixSortPjiiPiS0_S0_,@function
_Z9radixSortPjiiPiS0_S0_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_cvt_f32_u32_e32 v0, s4
v_cmp_gt_i32_e32 vcc_lo, s5, v1
v_ashrrev_i32_e32 v2, 31, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_co_u32 v3, s2, s8, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, s2, s9, v4, s2
s_sub_i32 s2, 0, s4
global_load_b32 v3, v[3:4], off
v_rcp_iflag_f32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v4, 0x4f7ffffe, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v4, v4
v_mul_lo_u32 v5, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v5, v4, v5
v_add_nc_u32_e32 v4, v4, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_mul_lo_u32 v5, v4, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v3, v5
v_add_nc_u32_e32 v5, 1, v4
v_subrev_nc_u32_e32 v6, s4, v3
v_cmp_le_u32_e64 s2, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v5, v4, v5, s2
v_mov_b32_e32 v4, 0
v_cndmask_b32_e64 v3, v3, v6, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v6, 1, v5
v_cmp_le_u32_e64 s2, s4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v5, v6, s2
v_mov_b32_e32 v5, 1
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v3, s2, s6, v3
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
global_atomic_add_u32 v[3:4], v5, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
v_mov_b32_e32 v3, 0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_load_b64 s[2:3], s[0:1], 0x18
global_load_b32 v4, v3, s[6:7]
s_mov_b64 s[10:11], 4
s_mov_b32 s5, 4
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v3, v4, s[2:3]
.p2align 6
.LBB0_3:
s_add_u32 s12, s6, s10
s_addc_u32 s13, s7, s11
v_mov_b32_e32 v6, s5
global_load_b32 v5, v3, s[12:13]
s_add_u32 s12, s2, s10
s_addc_u32 s13, s3, s11
s_add_u32 s10, s10, 4
s_addc_u32 s11, s11, 0
s_add_i32 s5, s5, 4
s_cmp_eq_u32 s10, 40
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, v5, v4
ds_store_b32 v6, v4
global_store_b32 v3, v4, s[12:13]
s_cbranch_scc0 .LBB0_3
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_ashr_i32 s3, s4, 31
v_rcp_iflag_f32_e32 v0, v0
s_add_i32 s5, s4, s3
s_sub_i32 s6, 0, s4
s_xor_b32 s5, s5, s3
v_add_co_u32 v1, vcc_lo, s8, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v0, 0x4f7ffffe, v0 :: v_dual_mul_f32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v3, s6, v0
s_sub_i32 s6, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v0, v3
v_add_nc_u32_e32 v0, v0, v3
v_mul_lo_u32 v3, s6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v1, v3
v_add_nc_u32_e32 v1, v1, v3
s_waitcnt vmcnt(0)
v_mul_hi_u32 v0, v2, v0
v_ashrrev_i32_e32 v5, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v4, v0, s4
v_sub_nc_u32_e32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v3, s4, v4
v_cmp_le_u32_e32 vcc_lo, s4, v4
v_dual_cndmask_b32 v3, v4, v3 :: v_dual_add_nc_u32 v6, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v0, v0, v6 :: v_dual_add_nc_u32 v7, v2, v5
v_cmp_le_u32_e32 vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v6, v7, v5
v_add_nc_u32_e32 v4, 1, v0
v_xor_b32_e32 v5, s3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_mul_hi_u32 v1, v6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v0, 2, v0
v_mul_lo_u32 v3, v1, s5
ds_load_b32 v0, v0
v_add_nc_u32_e32 v4, 1, v1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_sub_nc_u32_e32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v3, v1, v4 :: v_dual_mov_b32 v4, -1
v_ashrrev_i32_e32 v1, 31, v0
v_xor_b32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_sub_nc_u32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b32_e32 v3, 2, v3
global_store_b32 v[0:1], v2, off offset:-4
ds_add_u32 v3, v4
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x20
v_mov_b32_e32 v0, 0
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_7:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s2, 40
s_cbranch_scc0 .LBB0_7
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9radixSortPjiiPiS0_S0_
.amdhsa_group_segment_fixed_size 40
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9radixSortPjiiPiS0_S0_, .Lfunc_end0-_Z9radixSortPjiiPiS0_S0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 40
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9radixSortPjiiPiS0_S0_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9radixSortPjiiPiS0_S0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fa904_00000000-6_Radix_Sort.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[ "
.LC1:
.string "%d "
.LC2:
.string "]\n"
.text
.globl _Z10printArrayPii
.type _Z10printArrayPii, @function
_Z10printArrayPii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L4
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC1(%rip), %rbp
.L5:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10printArrayPii, .-_Z10printArrayPii
.globl _Z11printArrayUPji
.type _Z11printArrayUPji, @function
_Z11printArrayUPji:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movl %esi, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L9
movq %r12, %rbx
movslq %ebp, %rbp
leaq (%r12,%rbp,4), %r12
leaq .LC1(%rip), %rbp
.L10:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L10
.L9:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11printArrayUPji, .-_Z11printArrayUPji
.globl _Z10bucketSortPii
.type _Z10bucketSortPii, @function
_Z10bucketSortPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2059:
.size _Z10bucketSortPii, .-_Z10bucketSortPii
.globl _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_
.type _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_, @function
_Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z9radixSortPjiiPiS0_S0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_, .-_Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_
.globl _Z9radixSortPjiiPiS0_S0_
.type _Z9radixSortPjiiPiS0_S0_, @function
_Z9radixSortPjiiPiS0_S0_:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z9radixSortPjiiPiS0_S0_, .-_Z9radixSortPjiiPiS0_S0_
.section .rodata.str1.1
.LC3:
.string "VALUES BEFORE:\n"
.LC4:
.string "HISTOGRAM:\n"
.LC5:
.string "OFFSET BEFORE:\n"
.LC6:
.string "OFFSET AFTER:\n"
.LC7:
.string "VALUES AFTER:\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $64, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, totalNumbers(%rip)
movl %eax, %eax
leaq 0(,%rax,4), %rdi
call malloc@PLT
movq %rax, valuesList(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, histogram(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, offset(%rip)
movl $40, %edi
call malloc@PLT
movq %rax, offsetAfter(%rip)
movl $1, %edi
call srand@PLT
cmpl $0, totalNumbers(%rip)
je .L24
movl $0, %ebx
.L25:
call rand@PLT
movslq %eax, %rdx
imulq $-1518422781, %rdx, %rdx
shrq $32, %rdx
addl %eax, %edx
sarl $6, %edx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $99, %edx, %edx
subl %edx, %eax
movq valuesList(%rip), %rdx
movl %eax, (%rdx,%rbx,4)
addq $1, %rbx
cmpl totalNumbers(%rip), %ebx
jb .L25
.L24:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl totalNumbers(%rip), %esi
movq valuesList(%rip), %rdi
call _Z11printArrayUPji
movl $0, %eax
.L26:
movq histogram(%rip), %rdx
movl $0, (%rdx,%rax)
movq offset(%rip), %rdx
movl $0, (%rdx,%rax)
movq offsetAfter(%rip), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L26
movl totalNumbers(%rip), %esi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl totalNumbers(%rip), %edx
salq $2, %rdx
movl $1, %ecx
movq valuesList(%rip), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq histogram(%rip), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq offset(%rip), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $40, %edx
movq offsetAfter(%rip), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 44(%rsp)
movl $1, 48(%rsp)
movl totalNumbers(%rip), %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L27:
movl totalNumbers(%rip), %edx
salq $2, %rdx
movl $2, %ecx
movq (%rsp), %rsi
movq valuesList(%rip), %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl $2, %ecx
movl $40, %edx
movq 8(%rsp), %rsi
movq histogram(%rip), %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
movq offset(%rip), %rdi
call cudaMemcpy@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq offsetAfter(%rip), %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %esi
movq histogram(%rip), %rdi
call _Z10printArrayPii
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %esi
movq offset(%rip), %rdi
call _Z10printArrayPii
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $10, %esi
movq offsetAfter(%rip), %rdi
call _Z10printArrayPii
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl totalNumbers(%rip), %esi
movq valuesList(%rip), %rdi
call _Z11printArrayUPji
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
movq 24(%rsp), %r9
movq 16(%rsp), %r8
movq 8(%rsp), %rcx
movl totalNumbers(%rip), %edx
movl $10, %esi
movq (%rsp), %rdi
call _Z38__device_stub__Z9radixSortPjiiPiS0_S0_PjiiPiS0_S0_
jmp .L27
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9radixSortPjiiPiS0_S0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9radixSortPjiiPiS0_S0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl offsetAfter
.bss
.align 8
.type offsetAfter, @object
.size offsetAfter, 8
offsetAfter:
.zero 8
.globl offset
.align 8
.type offset, @object
.size offset, 8
offset:
.zero 8
.globl histogram
.align 8
.type histogram, @object
.size histogram, 8
histogram:
.zero 8
.globl totalNumbers
.align 4
.type totalNumbers, @object
.size totalNumbers, 4
totalNumbers:
.zero 4
.globl valuesList
.align 8
.type valuesList, @object
.size valuesList, 8
valuesList:
.zero 8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Radix_Sort.hip"
.globl _Z10printArrayPii # -- Begin function _Z10printArrayPii
.p2align 4, 0x90
.type _Z10printArrayPii,@function
_Z10printArrayPii: # @_Z10printArrayPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB0_2
.LBB0_3: # %._crit_edge
movl $.Lstr.1, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size _Z10printArrayPii, .Lfunc_end0-_Z10printArrayPii
.cfi_endproc
# -- End function
.globl _Z11printArrayUPji # -- Begin function _Z11printArrayUPji
.p2align 4, 0x90
.type _Z11printArrayUPji,@function
_Z11printArrayUPji: # @_Z11printArrayUPji
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB1_2
.LBB1_3: # %._crit_edge
movl $.Lstr.1, %edi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end1:
.size _Z11printArrayUPji, .Lfunc_end1-_Z11printArrayUPji
.cfi_endproc
# -- End function
.globl _Z24__device_stub__radixSortPjiiPiS0_S0_ # -- Begin function _Z24__device_stub__radixSortPjiiPiS0_S0_
.p2align 4, 0x90
.type _Z24__device_stub__radixSortPjiiPiS0_S0_,@function
_Z24__device_stub__radixSortPjiiPiS0_S0_: # @_Z24__device_stub__radixSortPjiiPiS0_S0_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9radixSortPjiiPiS0_S0_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z24__device_stub__radixSortPjiiPiS0_S0_, .Lfunc_end2-_Z24__device_stub__radixSortPjiiPiS0_S0_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $176, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, totalNumbers(%rip)
movl %eax, %edi
shlq $2, %rdi
callq malloc
movq %rax, valuesList(%rip)
movl $40, %edi
callq malloc
movq %rax, histogram(%rip)
movl $40, %edi
callq malloc
movq %rax, offset(%rip)
movl $40, %edi
callq malloc
movq %rax, offsetAfter(%rip)
movl $1, %edi
callq srand
cmpl $0, totalNumbers(%rip)
je .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $-1518422781, %rax, %rcx # imm = 0xA57EB503
shrq $32, %rcx
addl %eax, %ecx
movl %ecx, %edx
shrl $31, %edx
sarl $6, %ecx
addl %edx, %ecx
imull $99, %ecx, %ecx
subl %ecx, %eax
movq valuesList(%rip), %rcx
movl %eax, (%rcx,%rbx,4)
incq %rbx
movl totalNumbers(%rip), %eax
cmpq %rax, %rbx
jb .LBB3_2
.LBB3_3: # %._crit_edge
movl $.Lstr.2, %edi
callq puts@PLT
movq valuesList(%rip), %rbx
movl totalNumbers(%rip), %r14d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %r14d, %r14d
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader.i
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_5
.LBB3_6: # %_Z11printArrayUPji.exit
movl $.Lstr.1, %edi
callq puts@PLT
movq histogram(%rip), %rax
movq offset(%rip), %rcx
xorl %edx, %edx
movq offsetAfter(%rip), %rsi
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
movl $0, (%rax,%rdx,4)
movl $0, (%rcx,%rdx,4)
movl $0, (%rsi,%rdx,4)
incq %rdx
cmpq $10, %rdx
jne .LBB3_7
# %bb.8:
movl totalNumbers(%rip), %esi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movq valuesList(%rip), %rsi
movl totalNumbers(%rip), %edx
shlq $2, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movq histogram(%rip), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movq offset(%rip), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movq offsetAfter(%rip), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movl $255, %edi
addl totalNumbers(%rip), %edi
shrl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 32(%rsp), %rax
movl totalNumbers(%rip), %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
movq %rax, 120(%rsp)
movl $10, 44(%rsp)
movl %ecx, 40(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movq %rdi, 96(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 44(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rax
movq %rax, 152(%rsp)
leaq 104(%rsp), %rax
movq %rax, 160(%rsp)
leaq 96(%rsp), %rax
movq %rax, 168(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z9radixSortPjiiPiS0_S0_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq valuesList(%rip), %rdi
movq 32(%rsp), %rsi
movl totalNumbers(%rip), %edx
shlq $2, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq histogram(%rip), %rdi
movq 24(%rsp), %rsi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq offset(%rip), %rdi
movq 16(%rsp), %rsi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq offsetAfter(%rip), %rdi
movq 8(%rsp), %rsi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr.3, %edi
callq puts@PLT
movq histogram(%rip), %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_11: # %.lr.ph.i34
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB3_11
# %bb.12: # %_Z10printArrayPii.exit
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movq offset(%rip), %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_13: # %.lr.ph.i40
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB3_13
# %bb.14: # %_Z10printArrayPii.exit45
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.5, %edi
callq puts@PLT
movq offsetAfter(%rip), %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_15: # %.lr.ph.i47
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $10, %r14
jne .LBB3_15
# %bb.16: # %_Z10printArrayPii.exit52
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.6, %edi
callq puts@PLT
movq valuesList(%rip), %rbx
movl totalNumbers(%rip), %r14d
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %r14d, %r14d
jle .LBB3_19
# %bb.17: # %.lr.ph.preheader.i54
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_18: # %.lr.ph.i56
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB3_18
.LBB3_19: # %_Z11printArrayUPji.exit60
movl $.Lstr.1, %edi
callq puts@PLT
xorl %eax, %eax
addq $176, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9radixSortPjiiPiS0_S0_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type valuesList,@object # @valuesList
.bss
.globl valuesList
.p2align 3, 0x0
valuesList:
.quad 0
.size valuesList, 8
.type totalNumbers,@object # @totalNumbers
.globl totalNumbers
.p2align 2, 0x0
totalNumbers:
.long 0 # 0x0
.size totalNumbers, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[ "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type _Z9radixSortPjiiPiS0_S0_,@object # @_Z9radixSortPjiiPiS0_S0_
.section .rodata,"a",@progbits
.globl _Z9radixSortPjiiPiS0_S0_
.p2align 3, 0x0
_Z9radixSortPjiiPiS0_S0_:
.quad _Z24__device_stub__radixSortPjiiPiS0_S0_
.size _Z9radixSortPjiiPiS0_S0_, 8
.type histogram,@object # @histogram
.bss
.globl histogram
.p2align 3, 0x0
histogram:
.quad 0
.size histogram, 8
.type offset,@object # @offset
.globl offset
.p2align 3, 0x0
offset:
.quad 0
.size offset, 8
.type offsetAfter,@object # @offsetAfter
.globl offsetAfter
.p2align 3, 0x0
offsetAfter:
.quad 0
.size offsetAfter, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9radixSortPjiiPiS0_S0_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.1,@object # @str.1
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.1:
.asciz "]"
.size .Lstr.1, 2
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "VALUES BEFORE:"
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "HISTOGRAM:"
.size .Lstr.3, 11
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "OFFSET BEFORE:"
.size .Lstr.4, 15
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "OFFSET AFTER:"
.size .Lstr.5, 14
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "VALUES AFTER:"
.size .Lstr.6, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__radixSortPjiiPiS0_S0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9radixSortPjiiPiS0_S0_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;
for(int j = 0; j < n_vertices; j++) {
int jStart = 0;
if(j>0)
jStart = d_LCMSize[j - 1]; //Offset
int jSize = d_LCMSize[j] - jStart;
if(iSize != jSize)
continue;
int eq = 1;
for(int k = 0; k < iSize; k++)
{
if(d_lcmMatrix[iStart + k] != d_lcmMatrix[jStart + k])
{
eq = 0;
break;
}
}
if(eq == 1)
{
count++;
}
}
if(countMax < count)
countMax = count;
atomicAdd((int*)&d_histogram[count], 1);
// d_histogram[count]++;
}
} | code for sm_80
Function : _Z10OPT_4_HISTPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe20003f06270 */
/*0070*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0080*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fce00078e020d */
/*00c0*/ @P0 LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402060981 */
/* 0x000162000c1e1900 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*00f0*/ @!P0 BRA 0x370 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea2000c1e1900 */
/*0110*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R10, R3, -R6, RZ ; /* 0x80000006030a7210 */
/* 0x024fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0150*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.WIDE R2, R7, R13, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e020d */
/*0180*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0190*/ @P0 LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402080981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ BSSY B0, 0x360 ; /* 0x000001a000007945 */
/* 0x000fe60003800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fe20003f06270 */
/*01d0*/ IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105057824 */
/* 0x004fca00078e0a08 */
/*01e0*/ ISETP.NE.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f25270 */
/*01f0*/ @P1 BRA 0x350 ; /* 0x0000015000001947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f26270 */
/*0210*/ BSSY B1, 0x340 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0220*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fd60000000f00 */
/*0230*/ @!P1 BRA 0x330 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e00ff */
/*0250*/ IADD3 R2, R11.reuse, R6, RZ ; /* 0x000000060b027210 */
/* 0x040fe20007ffe0ff */
/*0260*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0270*/ IADD3 R4, R11, R8, RZ ; /* 0x000000080b047210 */
/* 0x000fc60007ffe0ff */
/*0280*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e020d */
/*0290*/ IMAD.WIDE R4, R4, R13, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e020d */
/*02a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.NE.AND P1, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x004fda0003f25270 */
/*02e0*/ @P1 BRA 0x330 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GE.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f26270 */
/*0310*/ @!P1 BRA 0x250 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0320*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fe40000000f00 */
/*0330*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0340*/ IMAD.IADD R0, R0, 0x1, R9 ; /* 0x0000000100007824 */
/* 0x000fe400078e0209 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ @!P0 BRA 0x140 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0370*/ IMAD.WIDE R2, R0, R13, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fe200078e020d */
/*0380*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fca0000000f00 */
/*0390*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;
for(int j = 0; j < n_vertices; j++) {
int jStart = 0;
if(j>0)
jStart = d_LCMSize[j - 1]; //Offset
int jSize = d_LCMSize[j] - jStart;
if(iSize != jSize)
continue;
int eq = 1;
for(int k = 0; k < iSize; k++)
{
if(d_lcmMatrix[iStart + k] != d_lcmMatrix[jStart + k])
{
eq = 0;
break;
}
}
if(eq == 1)
{
count++;
}
}
if(countMax < count)
countMax = count;
atomicAdd((int*)&d_histogram[count], 1);
// d_histogram[count]++;
}
} | .file "tmpxft_00199ceb_00000000-6_OPT_4_HIST.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10OPT_4_HISTPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i
.globl _Z10OPT_4_HISTPiS_S_i
.type _Z10OPT_4_HISTPiS_S_i, @function
_Z10OPT_4_HISTPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10OPT_4_HISTPiS_S_i, .-_Z10OPT_4_HISTPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10OPT_4_HISTPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10OPT_4_HISTPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;
for(int j = 0; j < n_vertices; j++) {
int jStart = 0;
if(j>0)
jStart = d_LCMSize[j - 1]; //Offset
int jSize = d_LCMSize[j] - jStart;
if(iSize != jSize)
continue;
int eq = 1;
for(int k = 0; k < iSize; k++)
{
if(d_lcmMatrix[iStart + k] != d_lcmMatrix[jStart + k])
{
eq = 0;
break;
}
}
if(eq == 1)
{
count++;
}
}
if(countMax < count)
countMax = count;
atomicAdd((int*)&d_histogram[count], 1);
// d_histogram[count]++;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;
for(int j = 0; j < n_vertices; j++) {
int jStart = 0;
if(j>0)
jStart = d_LCMSize[j - 1]; //Offset
int jSize = d_LCMSize[j] - jStart;
if(iSize != jSize)
continue;
int eq = 1;
for(int k = 0; k < iSize; k++)
{
if(d_lcmMatrix[iStart + k] != d_lcmMatrix[jStart + k])
{
eq = 0;
break;
}
}
if(eq == 1)
{
count++;
}
}
if(countMax < count)
countMax = count;
atomicAdd((int*)&d_histogram[count], 1);
// d_histogram[count]++;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;
for(int j = 0; j < n_vertices; j++) {
int jStart = 0;
if(j>0)
jStart = d_LCMSize[j - 1]; //Offset
int jSize = d_LCMSize[j] - jStart;
if(iSize != jSize)
continue;
int eq = 1;
for(int k = 0; k < iSize; k++)
{
if(d_lcmMatrix[iStart + k] != d_lcmMatrix[jStart + k])
{
eq = 0;
break;
}
}
if(eq == 1)
{
count++;
}
}
if(countMax < count)
countMax = count;
atomicAdd((int*)&d_histogram[count], 1);
// d_histogram[count]++;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10OPT_4_HISTPiS_S_i
.globl _Z10OPT_4_HISTPiS_S_i
.p2align 8
.type _Z10OPT_4_HISTPiS_S_i,@function
_Z10OPT_4_HISTPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_21
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off offset:-4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_19
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s13, s4, -4
s_addc_u32 s15, s5, -1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_mov_b32 s8, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_mov_b32_e32 v1, 0
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v4, v4, v0
v_cmp_gt_i32_e64 s14, 1, v4
v_cmp_lt_i32_e32 vcc_lo, 0, v4
s_branch .LBB0_9
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s14, exec_lo
s_and_b32 s3, s20, exec_lo
s_or_b32 s3, s2, s3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s14, exec_lo
s_and_b32 s3, s3, exec_lo
s_or_b32 s2, s2, s3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s17
v_cndmask_b32_e64 v5, 0, 1, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s12
s_cbranch_scc1 .LBB0_18
.LBB0_9:
s_cmp_eq_u32 s8, 0
s_mov_b32 s10, 0
s_cbranch_scc1 .LBB0_11
s_lshl_b64 s[2:3], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s13, s2
s_addc_u32 s3, s15, s3
s_load_b32 s10, s[2:3], 0x0
.LBB0_11:
s_lshl_b64 s[2:3], s[8:9], 2
s_mov_b32 s16, exec_lo
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s2, s2, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_eq_u32_e64 s2, v4
s_cbranch_execz .LBB0_8
s_mov_b32 s2, s14
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_7
global_load_b32 v5, v[2:3], off
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[10:11], 2
s_mov_b32 s11, exec_lo
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_mov_b32 s3, s14
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_eq_u32_e64 s2, v5
s_cbranch_execz .LBB0_6
s_mov_b32 s19, 1
s_mov_b32 s18, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_16
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, exec_lo, s21
s_or_b32 s18, s3, s18
s_and_not1_b32 s3, s20, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s20, s3, s2
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_5
.LBB0_16:
v_cmp_ge_i32_e64 s2, s19, v4
s_or_b32 s21, s21, exec_lo
s_mov_b32 s22, exec_lo
v_cmpx_lt_i32_e64 s19, v4
s_cbranch_execz .LBB0_15
v_add_nc_u32_e32 v5, s19, v0
s_add_i32 s24, s10, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s25, s24, 31
s_lshl_b64 s[24:25], s[24:25], 2
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_u32 s24, s6, s24
s_addc_u32 s25, s7, s25
s_and_not1_b32 s21, s21, exec_lo
s_add_i32 s19, s19, 1
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s3, s6, v5
v_add_co_ci_u32_e64 v6, s3, s7, v6, s3
s_load_b32 s3, s[24:25], 0x0
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e64 s3, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, exec_lo
s_or_b32 s21, s21, s3
s_branch .LBB0_15
.LBB0_18:
v_ashrrev_i32_e32 v2, 31, v1
s_branch .LBB0_20
.LBB0_19:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_20:
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10OPT_4_HISTPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10OPT_4_HISTPiS_S_i, .Lfunc_end0-_Z10OPT_4_HISTPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10OPT_4_HISTPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z10OPT_4_HISTPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void OPT_4_HIST(int *d_lcmMatrix, int *d_LCMSize, int *d_histogram, int n_vertices)
{
int i = threadIdx.x + blockIdx.x * blockDim.x;
int count = 0, countMax = -1;
if(i<n_vertices)
{
int iStart = 0;
if(i>0)
iStart = d_LCMSize[i - 1]; //Offset
count = 0;
int iSize = d_LCMSize[i] - iStart;
for(int j = 0; j < n_vertices; j++) {
int jStart = 0;
if(j>0)
jStart = d_LCMSize[j - 1]; //Offset
int jSize = d_LCMSize[j] - jStart;
if(iSize != jSize)
continue;
int eq = 1;
for(int k = 0; k < iSize; k++)
{
if(d_lcmMatrix[iStart + k] != d_lcmMatrix[jStart + k])
{
eq = 0;
break;
}
}
if(eq == 1)
{
count++;
}
}
if(countMax < count)
countMax = count;
atomicAdd((int*)&d_histogram[count], 1);
// d_histogram[count]++;
}
} | .text
.file "OPT_4_HIST.hip"
.globl _Z25__device_stub__OPT_4_HISTPiS_S_i # -- Begin function _Z25__device_stub__OPT_4_HISTPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__OPT_4_HISTPiS_S_i,@function
_Z25__device_stub__OPT_4_HISTPiS_S_i: # @_Z25__device_stub__OPT_4_HISTPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10OPT_4_HISTPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__OPT_4_HISTPiS_S_i, .Lfunc_end0-_Z25__device_stub__OPT_4_HISTPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10OPT_4_HISTPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10OPT_4_HISTPiS_S_i,@object # @_Z10OPT_4_HISTPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10OPT_4_HISTPiS_S_i
.p2align 3, 0x0
_Z10OPT_4_HISTPiS_S_i:
.quad _Z25__device_stub__OPT_4_HISTPiS_S_i
.size _Z10OPT_4_HISTPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10OPT_4_HISTPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__OPT_4_HISTPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10OPT_4_HISTPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10OPT_4_HISTPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ISETP.GE.AND P0, PT, R2.reuse, 0x1, PT ; /* 0x000000010200780c */
/* 0x040fe20003f06270 */
/*0070*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0080*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.WIDE R2, R2, R13, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fce00078e020d */
/*00c0*/ @P0 LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402060981 */
/* 0x000162000c1e1900 */
/*00d0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*00f0*/ @!P0 BRA 0x370 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x001ea2000c1e1900 */
/*0110*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0130*/ IADD3 R10, R3, -R6, RZ ; /* 0x80000006030a7210 */
/* 0x024fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f05270 */
/*0150*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0160*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.WIDE R2, R7, R13, c[0x0][0x168] ; /* 0x00005a0007027625 */
/* 0x000fca00078e020d */
/*0180*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea8000c1e1900 */
/*0190*/ @P0 LDG.E R8, [R2.64+-0x4] ; /* 0xfffffc0402080981 */
/* 0x000ea2000c1e1900 */
/*01a0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ BSSY B0, 0x360 ; /* 0x000001a000007945 */
/* 0x000fe60003800000 */
/*01c0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fe20003f06270 */
/*01d0*/ IMAD.IADD R5, R5, 0x1, -R8 ; /* 0x0000000105057824 */
/* 0x004fca00078e0a08 */
/*01e0*/ ISETP.NE.AND P1, PT, R10, R5, PT ; /* 0x000000050a00720c */
/* 0x000fda0003f25270 */
/*01f0*/ @P1 BRA 0x350 ; /* 0x0000015000001947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GE.AND P1, PT, R10, 0x1, PT ; /* 0x000000010a00780c */
/* 0x000fe20003f26270 */
/*0210*/ BSSY B1, 0x340 ; /* 0x0000012000017945 */
/* 0x000fe20003800000 */
/*0220*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fd60000000f00 */
/*0230*/ @!P1 BRA 0x330 ; /* 0x000000f000009947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fca00078e00ff */
/*0250*/ IADD3 R2, R11.reuse, R6, RZ ; /* 0x000000060b027210 */
/* 0x040fe20007ffe0ff */
/*0260*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*0270*/ IADD3 R4, R11, R8, RZ ; /* 0x000000080b047210 */
/* 0x000fc60007ffe0ff */
/*0280*/ IMAD.WIDE R2, R2, R13, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fc800078e020d */
/*0290*/ IMAD.WIDE R4, R4, R13, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e020d */
/*02a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*02d0*/ ISETP.NE.AND P1, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x004fda0003f25270 */
/*02e0*/ @P1 BRA 0x330 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*02f0*/ IADD3 R11, R11, 0x1, RZ ; /* 0x000000010b0b7810 */
/* 0x000fc80007ffe0ff */
/*0300*/ ISETP.GE.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00720c */
/* 0x000fda0003f26270 */
/*0310*/ @!P1 BRA 0x250 ; /* 0xffffff3000009947 */
/* 0x000fea000383ffff */
/*0320*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fe40000000f00 */
/*0330*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0340*/ IMAD.IADD R0, R0, 0x1, R9 ; /* 0x0000000100007824 */
/* 0x000fe400078e0209 */
/*0350*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0360*/ @!P0 BRA 0x140 ; /* 0xfffffdd000008947 */
/* 0x000fea000383ffff */
/*0370*/ IMAD.WIDE R2, R0, R13, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fe200078e020d */
/*0380*/ MOV R5, 0x1 ; /* 0x0000000100057802 */
/* 0x000fca0000000f00 */
/*0390*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10OPT_4_HISTPiS_S_i
.globl _Z10OPT_4_HISTPiS_S_i
.p2align 8
.type _Z10OPT_4_HISTPiS_S_i,@function
_Z10OPT_4_HISTPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s12, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s12, v1
s_cbranch_execz .LBB0_21
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e32 0, v1
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v0, v[2:3], off offset:-4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_cmp_lt_i32 s12, 1
s_cbranch_scc1 .LBB0_19
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[6:7], s[0:1], 0x0
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s13, s4, -4
s_addc_u32 s15, s5, -1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_mov_b32 s8, s9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(1)
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_mov_b32_e32 v1, 0
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v4, v4, v0
v_cmp_gt_i32_e64 s14, 1, v4
v_cmp_lt_i32_e32 vcc_lo, 0, v4
s_branch .LBB0_9
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s14, exec_lo
s_and_b32 s3, s20, exec_lo
s_or_b32 s3, s2, s3
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s11
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s2, s14, exec_lo
s_and_b32 s3, s3, exec_lo
s_or_b32 s2, s2, s3
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s17
v_cndmask_b32_e64 v5, 0, 1, s2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s16
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, s12
s_cbranch_scc1 .LBB0_18
.LBB0_9:
s_cmp_eq_u32 s8, 0
s_mov_b32 s10, 0
s_cbranch_scc1 .LBB0_11
s_lshl_b64 s[2:3], s[8:9], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s13, s2
s_addc_u32 s3, s15, s3
s_load_b32 s10, s[2:3], 0x0
.LBB0_11:
s_lshl_b64 s[2:3], s[8:9], 2
s_mov_b32 s16, exec_lo
s_add_u32 s2, s4, s2
s_addc_u32 s3, s5, s3
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s2, s2, s10
s_delay_alu instid0(SALU_CYCLE_1)
v_cmpx_eq_u32_e64 s2, v4
s_cbranch_execz .LBB0_8
s_mov_b32 s2, s14
s_and_saveexec_b32 s17, vcc_lo
s_cbranch_execz .LBB0_7
global_load_b32 v5, v[2:3], off
s_ashr_i32 s11, s10, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[10:11], 2
s_mov_b32 s11, exec_lo
s_add_u32 s2, s6, s2
s_addc_u32 s3, s7, s3
s_load_b32 s2, s[2:3], 0x0
s_mov_b32 s3, s14
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_eq_u32_e64 s2, v5
s_cbranch_execz .LBB0_6
s_mov_b32 s19, 1
s_mov_b32 s18, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_16
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, exec_lo, s21
s_or_b32 s18, s3, s18
s_and_not1_b32 s3, s20, exec_lo
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s20, s3, s2
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_5
.LBB0_16:
v_cmp_ge_i32_e64 s2, s19, v4
s_or_b32 s21, s21, exec_lo
s_mov_b32 s22, exec_lo
v_cmpx_lt_i32_e64 s19, v4
s_cbranch_execz .LBB0_15
v_add_nc_u32_e32 v5, s19, v0
s_add_i32 s24, s10, s19
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s25, s24, 31
s_lshl_b64 s[24:25], s[24:25], 2
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_u32 s24, s6, s24
s_addc_u32 s25, s7, s25
s_and_not1_b32 s21, s21, exec_lo
s_add_i32 s19, s19, 1
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v5, s3, s6, v5
v_add_co_ci_u32_e64 v6, s3, s7, v6, s3
s_load_b32 s3, s[24:25], 0x0
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmp_ne_u32_e64 s3, s3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, exec_lo
s_or_b32 s21, s21, s3
s_branch .LBB0_15
.LBB0_18:
v_ashrrev_i32_e32 v2, 31, v1
s_branch .LBB0_20
.LBB0_19:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_20:
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10OPT_4_HISTPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 26
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10OPT_4_HISTPiS_S_i, .Lfunc_end0-_Z10OPT_4_HISTPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10OPT_4_HISTPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 28
.sgpr_spill_count: 0
.symbol: _Z10OPT_4_HISTPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00199ceb_00000000-6_OPT_4_HIST.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i
.type _Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i, @function
_Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10OPT_4_HISTPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i, .-_Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i
.globl _Z10OPT_4_HISTPiS_S_i
.type _Z10OPT_4_HISTPiS_S_i, @function
_Z10OPT_4_HISTPiS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z10OPT_4_HISTPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10OPT_4_HISTPiS_S_i, .-_Z10OPT_4_HISTPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10OPT_4_HISTPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10OPT_4_HISTPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "OPT_4_HIST.hip"
.globl _Z25__device_stub__OPT_4_HISTPiS_S_i # -- Begin function _Z25__device_stub__OPT_4_HISTPiS_S_i
.p2align 4, 0x90
.type _Z25__device_stub__OPT_4_HISTPiS_S_i,@function
_Z25__device_stub__OPT_4_HISTPiS_S_i: # @_Z25__device_stub__OPT_4_HISTPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10OPT_4_HISTPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__OPT_4_HISTPiS_S_i, .Lfunc_end0-_Z25__device_stub__OPT_4_HISTPiS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10OPT_4_HISTPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10OPT_4_HISTPiS_S_i,@object # @_Z10OPT_4_HISTPiS_S_i
.section .rodata,"a",@progbits
.globl _Z10OPT_4_HISTPiS_S_i
.p2align 3, 0x0
_Z10OPT_4_HISTPiS_S_i:
.quad _Z25__device_stub__OPT_4_HISTPiS_S_i
.size _Z10OPT_4_HISTPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10OPT_4_HISTPiS_S_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__OPT_4_HISTPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10OPT_4_HISTPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
}
}
} | code for sm_80
Function : _Z18matrixAdd_C_KernelPfS_S_mi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x180], !P0 ; /* 0x0000600003007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ MOV R0, c[0x0][0x17c] ; /* 0x00005f0000007a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00d0*/ MOV R5, UR4 ; /* 0x0000000400057c02 */
/* 0x000fe20008000f00 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0100*/ SHF.R.U64 R0, R5, 0x2, R0 ; /* 0x0000000205007819 */
/* 0x000fce0000001200 */
/*0110*/ @!P0 BRA 0xf10 ; /* 0x00000df000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R4, -R2, c[0x0][0x180], RZ ; /* 0x0000600002047a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0150*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f04270 */
/*0160*/ IMAD.WIDE R6, R3, R8, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD.WIDE R10, R3, R8, c[0x0][0x168] ; /* 0x00005a00030a7625 */
/* 0x000fc800078e0208 */
/*0180*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fe200078e0208 */
/*0190*/ @!P0 BRA 0xd10 ; /* 0x00000b7000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x920 ; /* 0x0000075000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R5, [R10.64] ; /* 0x000000060a057981 */
/* 0x002ea8000c1e1900 */
/*01f0*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*0210*/ FADD R5, R5, R12 ; /* 0x0000000c05057221 */
/* 0x004fe40000000000 */
/*0220*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0206 */
/*0230*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0001e8000c101906 */
/*0240*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R19, [R12.64] ; /* 0x000000060c137981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0280*/ FADD R23, R18, R19 ; /* 0x0000001312177221 */
/* 0x004fe40000000000 */
/*0290*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*02a0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101906 */
/*02b0*/ LDG.E R20, [R18.64] ; /* 0x0000000612147981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R16 ; /* 0x0000000400067825 */
/* 0x000fc800078e0210 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x001fc800078e020a */
/*02f0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0212 */
/*0300*/ FADD R5, R20, R21 ; /* 0x0000001514057221 */
/* 0x004fca0000000000 */
/*0310*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001e8000c101906 */
/*0320*/ LDG.E R15, [R8.64] ; /* 0x00000006080f7981 */
/* 0x000e68000c1e1900 */
/*0330*/ LDG.E R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000e62000c1e1900 */
/*0340*/ IMAD.WIDE R20, R0, 0x4, R6 ; /* 0x0000000400147825 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0208 */
/*0360*/ FADD R23, R14, R15 ; /* 0x0000000f0e177221 */
/* 0x002fe40000000000 */
/*0370*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0380*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0003e8000c101906 */
/*0390*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R19, [R10.64] ; /* 0x000000060a137981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fc800078e0214 */
/*03c0*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc800078e020e */
/*03d0*/ IMAD.WIDE R6, R0, 0x4, R10 ; /* 0x0000000400067825 */
/* 0x001fc800078e020a */
/*03e0*/ FADD R5, R18, R19 ; /* 0x0000001312057221 */
/* 0x004fca0000000000 */
/*03f0*/ STG.E [R16.64], R5 ; /* 0x0000000510007986 */
/* 0x0001e8000c101906 */
/*0400*/ LDG.E R18, [R8.64] ; /* 0x0000000608127981 */
/* 0x000e68000c1e1900 */
/*0410*/ LDG.E R19, [R6.64] ; /* 0x0000000606137981 */
/* 0x000e62000c1e1900 */
/*0420*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0210 */
/*0430*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0440*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0450*/ FADD R23, R18, R19 ; /* 0x0000001312177221 */
/* 0x002fca0000000000 */
/*0460*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0003e8000c101906 */
/*0470*/ LDG.E R20, [R14.64] ; /* 0x000000060e147981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x000fc800078e020c */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x000fc800078e020a */
/*04b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x001fc800078e020e */
/*04c0*/ FADD R5, R20, R21 ; /* 0x0000001514057221 */
/* 0x004fca0000000000 */
/*04d0*/ STG.E [R18.64], R5 ; /* 0x0000000512007986 */
/* 0x0001e8000c101906 */
/*04e0*/ LDG.E R7, [R8.64] ; /* 0x0000000608077981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R6, [R16.64] ; /* 0x0000000610067981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc800078e0212 */
/*0510*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x002fc800078e0210 */
/*0520*/ FADD R23, R6, R7 ; /* 0x0000000706177221 */
/* 0x004fe40000000000 */
/*0530*/ IMAD.WIDE R6, R0, 0x4, R8 ; /* 0x0000000400067825 */
/* 0x000fc600078e0208 */
/*0540*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0003e8000c101906 */
/*0550*/ LDG.E R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000e28000c1e1900 */
/*0560*/ LDG.E R15, [R6.64] ; /* 0x00000006060f7981 */
/* 0x000e22000c1e1900 */
/*0570*/ IMAD.WIDE R10, R0, 0x4, R20 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0214 */
/*0580*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fc800078e0206 */
/*0590*/ FADD R5, R14, R15 ; /* 0x0000000f0e057221 */
/* 0x001fe40000000000 */
/*05a0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*05b0*/ STG.E [R10.64], R5 ; /* 0x000000050a007986 */
/* 0x0001e8000c101906 */
/*05c0*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000e68000c1e1900 */
/*05d0*/ LDG.E R19, [R8.64] ; /* 0x0000000608137981 */
/* 0x000e62000c1e1900 */
/*05e0*/ IMAD.WIDE R16, R0, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x000fc800078e020a */
/*05f0*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc800078e020e */
/*0600*/ IMAD.WIDE R6, R0, 0x4, R8 ; /* 0x0000000400067825 */
/* 0x000fc800078e0208 */
/*0610*/ FADD R21, R18, R19 ; /* 0x0000001312157221 */
/* 0x002fca0000000000 */
/*0620*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e8000c101906 */
/*0630*/ LDG.E R20, [R12.64] ; /* 0x000000060c147981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000ea2000c1e1900 */
/*0650*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc800078e0210 */
/*0660*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x001fc800078e0206 */
/*0670*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*0680*/ FADD R23, R20, R23 ; /* 0x0000001714177221 */
/* 0x004fca0000000000 */
/*0690*/ STG.E [R18.64], R23 ; /* 0x0000001712007986 */
/* 0x0001e8000c101906 */
/*06a0*/ LDG.E R20, [R10.64] ; /* 0x000000060a147981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0212 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0208 */
/*06e0*/ IMAD.WIDE R6, R0, 0x4, R10 ; /* 0x0000000400067825 */
/* 0x000fc800078e020a */
/*06f0*/ FADD R5, R5, R20 ; /* 0x0000001405057221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R14.64], R5 ; /* 0x000000050e007986 */
/* 0x0005e8000c101906 */
/*0710*/ LDG.E R20, [R12.64] ; /* 0x000000060c147981 */
/* 0x000ee8000c1e1900 */
/*0720*/ LDG.E R21, [R6.64] ; /* 0x0000000606157981 */
/* 0x002ee2000c1e1900 */
/*0730*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0750*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fc800078e0206 */
/*0760*/ FADD R21, R20, R21 ; /* 0x0000001514157221 */
/* 0x008fca0000000000 */
/*0770*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e8000c101906 */
/*0780*/ LDG.E R20, [R10.64] ; /* 0x000000060a147981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R23, [R8.64] ; /* 0x0000000608177981 */
/* 0x001ea2000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc800078e0210 */
/*07b0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc800078e020a */
/*07c0*/ IMAD.WIDE R6, R0, 0x4, R8 ; /* 0x0000000400067825 */
/* 0x000fc800078e0208 */
/*07d0*/ FADD R5, R20, R23 ; /* 0x0000001714057221 */
/* 0x004fca0000000000 */
/*07e0*/ STG.E [R18.64], R5 ; /* 0x0000000512007986 */
/* 0x0001e8000c101906 */
/*07f0*/ LDG.E R20, [R12.64] ; /* 0x000000060c147981 */
/* 0x000ea8000c1e1900 */
/*0800*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0212 */
/*0820*/ IMAD.WIDE R16, R0, 0x4, R6 ; /* 0x0000000400107825 */
/* 0x002fc800078e0206 */
/*0830*/ FADD R25, R20, R23 ; /* 0x0000001714197221 */
/* 0x004fe40000000000 */
/*0840*/ IMAD.WIDE R20, R0, 0x4, R12 ; /* 0x0000000400147825 */
/* 0x000fc600078e020c */
/*0850*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0003e8000c101906 */
/*0860*/ LDG.E R9, [R16.64] ; /* 0x0000000610097981 */
/* 0x000e28000c1e1900 */
/*0870*/ LDG.E R8, [R20.64] ; /* 0x0000000614087981 */
/* 0x000e22000c1e1900 */
/*0880*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0890*/ IMAD.WIDE R22, R0, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x000fe200078e020e */
/*08a0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc4000fffe03f */
/*08b0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*08c0*/ IMAD.WIDE R10, R0, 0x4, R20 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0214 */
/*08d0*/ IMAD.WIDE R6, R0, 0x4, R16 ; /* 0x0000000400067825 */
/* 0x000fc800078e0210 */
/*08e0*/ FADD R5, R8, R9 ; /* 0x0000000908057221 */
/* 0x001fe40000000000 */
/*08f0*/ IMAD.WIDE R8, R0, 0x4, R22 ; /* 0x0000000400087825 */
/* 0x000fc600078e0216 */
/*0900*/ STG.E [R22.64], R5 ; /* 0x0000000516007986 */
/* 0x0003e2000c101906 */
/*0910*/ @P1 BRA 0x1e0 ; /* 0xfffff8c000001947 */
/* 0x000fea000383ffff */
/*0920*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0930*/ @!P1 BRA 0xcf0 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0940*/ LDG.E R5, [R10.64] ; /* 0x000000060a057981 */
/* 0x002ea8000c1e1900 */
/*0950*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0960*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*0970*/ FADD R5, R5, R12 ; /* 0x0000000c05057221 */
/* 0x004fe40000000000 */
/*0980*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0206 */
/*0990*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0001e8000c101906 */
/*09a0*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R19, [R12.64] ; /* 0x000000060c137981 */
/* 0x000ea2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fc800078e0208 */
/*09d0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*09e0*/ FADD R23, R18, R19 ; /* 0x0000001312177221 */
/* 0x004fe40000000000 */
/*09f0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0a00*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101906 */
/*0a10*/ LDG.E R20, [R18.64] ; /* 0x0000000612147981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IMAD.WIDE R6, R0, 0x4, R16 ; /* 0x0000000400067825 */
/* 0x000fc800078e0210 */
/*0a40*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x001fc800078e020a */
/*0a50*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0212 */
/*0a60*/ FADD R5, R20, R21 ; /* 0x0000001514057221 */
/* 0x004fca0000000000 */
/*0a70*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001e8000c101906 */
/*0a80*/ LDG.E R15, [R8.64] ; /* 0x00000006080f7981 */
/* 0x000e68000c1e1900 */
/*0a90*/ LDG.E R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000e62000c1e1900 */
/*0aa0*/ IMAD.WIDE R20, R0, 0x4, R6 ; /* 0x0000000400147825 */
/* 0x000fc800078e0206 */
/*0ab0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0208 */
/*0ac0*/ FADD R23, R14, R15 ; /* 0x0000000f0e177221 */
/* 0x002fe40000000000 */
/*0ad0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0ae0*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0003e8000c101906 */
/*0af0*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ LDG.E R19, [R10.64] ; /* 0x000000060a137981 */
/* 0x000ea2000c1e1900 */
/*0b10*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fc800078e0214 */
/*0b20*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc800078e020e */
/*0b30*/ IMAD.WIDE R6, R0, 0x4, R10 ; /* 0x0000000400067825 */
/* 0x001fc800078e020a */
/*0b40*/ FADD R5, R18, R19 ; /* 0x0000001312057221 */
/* 0x004fca0000000000 */
/*0b50*/ STG.E [R16.64], R5 ; /* 0x0000000510007986 */
/* 0x0001e8000c101906 */
/*0b60*/ LDG.E R18, [R8.64] ; /* 0x0000000608127981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R19, [R6.64] ; /* 0x0000000606137981 */
/* 0x000ea2000c1e1900 */
/*0b80*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0210 */
/*0b90*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0ba0*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0bb0*/ FADD R25, R18, R19 ; /* 0x0000001312197221 */
/* 0x004fca0000000000 */
/*0bc0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0005e8000c101906 */
/*0bd0*/ LDG.E R20, [R14.64] ; /* 0x000000060e147981 */
/* 0x002ee8000c1e1900 */
/*0be0*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ee2000c1e1900 */
/*0bf0*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x000fc800078e020c */
/*0c00*/ IMAD.WIDE R16, R0, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x001fc800078e020a */
/*0c10*/ FADD R5, R20, R21 ; /* 0x0000001514057221 */
/* 0x008fe40000000000 */
/*0c20*/ IMAD.WIDE R20, R0, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x000fc600078e020e */
/*0c30*/ STG.E [R18.64], R5 ; /* 0x0000000512007986 */
/* 0x0001e8000c101906 */
/*0c40*/ LDG.E R7, [R16.64] ; /* 0x0000000610077981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ LDG.E R6, [R20.64] ; /* 0x0000000614067981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ IMAD.WIDE R22, R0, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x000fe200078e0212 */
/*0c70*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0c80*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0c90*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0ca0*/ IMAD.WIDE R10, R0, 0x4, R20 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0214 */
/*0cb0*/ IMAD.WIDE R8, R0, 0x4, R22 ; /* 0x0000000400087825 */
/* 0x000fc800078e0216 */
/*0cc0*/ FADD R13, R6, R7 ; /* 0x00000007060d7221 */
/* 0x004fe40000000000 */
/*0cd0*/ IMAD.WIDE R6, R0, 0x4, R16 ; /* 0x0000000400067825 */
/* 0x000fc600078e0210 */
/*0ce0*/ STG.E [R22.64], R13 ; /* 0x0000000d16007986 */
/* 0x0001e8000c101906 */
/*0cf0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0d00*/ @!P0 BRA 0xf10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d10*/ LDG.E R5, [R10.64] ; /* 0x000000060a057981 */
/* 0x003ea8000c1e1900 */
/*0d20*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0d30*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*0d40*/ FADD R5, R5, R12 ; /* 0x0000000c05057221 */
/* 0x004fe40000000000 */
/*0d50*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0206 */
/*0d60*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0001e8000c101906 */
/*0d70*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*0d80*/ LDG.E R19, [R12.64] ; /* 0x000000060c137981 */
/* 0x000ea2000c1e1900 */
/*0d90*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fc800078e0208 */
/*0da0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0db0*/ FADD R25, R18, R19 ; /* 0x0000001312197221 */
/* 0x004fe40000000000 */
/*0dc0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0dd0*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0003e8000c101906 */
/*0de0*/ LDG.E R6, [R18.64] ; /* 0x0000000612067981 */
/* 0x000e28000c1e1900 */
/*0df0*/ LDG.E R7, [R10.64] ; /* 0x000000060a077981 */
/* 0x000e22000c1e1900 */
/*0e00*/ IMAD.WIDE R20, R0, 0x4, R16 ; /* 0x0000000400147825 */
/* 0x000fc800078e0210 */
/*0e10*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*0e20*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0212 */
/*0e30*/ FADD R5, R6, R7 ; /* 0x0000000706057221 */
/* 0x001fca0000000000 */
/*0e40*/ STG.E [R20.64], R5 ; /* 0x0000000514007986 */
/* 0x0001e8000c101906 */
/*0e50*/ LDG.E R7, [R14.64] ; /* 0x000000060e077981 */
/* 0x000e68000c1e1900 */
/*0e60*/ LDG.E R6, [R12.64] ; /* 0x000000060c067981 */
/* 0x000e62000c1e1900 */
/*0e70*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0e80*/ IMAD.WIDE R22, R0, 0x4, R20 ; /* 0x0000000400167825 */
/* 0x000fe200078e0214 */
/*0e90*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc4000fffe03f */
/*0ea0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0eb0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0ec0*/ IMAD.WIDE R8, R0, 0x4, R22 ; /* 0x0000000400087825 */
/* 0x000fc800078e0216 */
/*0ed0*/ FADD R17, R6, R7 ; /* 0x0000000706117221 */
/* 0x002fe40000000000 */
/*0ee0*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x000fc600078e020e */
/*0ef0*/ STG.E [R22.64], R17 ; /* 0x0000001116007986 */
/* 0x0001e4000c101906 */
/*0f00*/ @P0 BRA 0xd10 ; /* 0xfffffe0000000947 */
/* 0x001fea000383ffff */
/*0f10*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0f20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0f30*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0f40*/ IMAD R3, R0, UR4, R3 ; /* 0x0000000400037c24 */
/* 0x000fd2000f8e0203 */
/*0f50*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x003fc800078e0208 */
/*0f60*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0f70*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0f80*/ LDG.E R3, [R6.64] ; /* 0x0000000606037981 */
/* 0x0000a8000c1e1900 */
/*0f90*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x0002a2000c1e1900 */
/*0fa0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0fb0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0fc0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*0fd0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*0fe0*/ FADD R3, R3, R10 ; /* 0x0000000a03037221 */
/* 0x004fca0000000000 */
/*0ff0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e4000c101906 */
/*1000*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*1010*/ @P0 BRA 0xf80 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*1020*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1030*/ BRA 0x1030; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
}
}
} | .file "tmpxft_00006656_00000000-6_matrixAdd_C_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi
.type _Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi, @function
_Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18matrixAdd_C_KernelPfS_S_mi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi, .-_Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi
.globl _Z18matrixAdd_C_KernelPfS_S_mi
.type _Z18matrixAdd_C_KernelPfS_S_mi, @function
_Z18matrixAdd_C_KernelPfS_S_mi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18matrixAdd_C_KernelPfS_S_mi, .-_Z18matrixAdd_C_KernelPfS_S_mi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18matrixAdd_C_KernelPfS_S_mi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrixAdd_C_KernelPfS_S_mi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixAdd_C_KernelPfS_S_mi
.globl _Z18matrixAdd_C_KernelPfS_S_mi
.p2align 8
.type _Z18matrixAdd_C_KernelPfS_S_mi,@function
_Z18matrixAdd_C_KernelPfS_S_mi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_alignbit_b32 v0, s7, s6, 2
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s8, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrixAdd_C_KernelPfS_S_mi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrixAdd_C_KernelPfS_S_mi, .Lfunc_end0-_Z18matrixAdd_C_KernelPfS_S_mi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrixAdd_C_KernelPfS_S_mi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrixAdd_C_KernelPfS_S_mi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd_C_Kernel(float* A, float* B, float* C, size_t pitch, int width){
//compute indexes
int col = blockIdx.x * blockDim.x + threadIdx.x;
int rowWidthWithPad = pitch/sizeof(float);
if(col < width){
for (int row = 0; row < width; ++row) {
if(row < width)
C[row * rowWidthWithPad + col] = A[row * rowWidthWithPad + col] + B[row * rowWidthWithPad + col];
}
}
} | .text
.file "matrixAdd_C_Kernel.hip"
.globl _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi # -- Begin function _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.p2align 4, 0x90
.type _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi,@function
_Z33__device_stub__matrixAdd_C_KernelPfS_S_mi: # @_Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18matrixAdd_C_KernelPfS_S_mi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi, .Lfunc_end0-_Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrixAdd_C_KernelPfS_S_mi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matrixAdd_C_KernelPfS_S_mi,@object # @_Z18matrixAdd_C_KernelPfS_S_mi
.section .rodata,"a",@progbits
.globl _Z18matrixAdd_C_KernelPfS_S_mi
.p2align 3, 0x0
_Z18matrixAdd_C_KernelPfS_S_mi:
.quad _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.size _Z18matrixAdd_C_KernelPfS_S_mi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matrixAdd_C_KernelPfS_S_mi"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrixAdd_C_KernelPfS_S_mi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18matrixAdd_C_KernelPfS_S_mi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, c[0x0][0x180] ; /* 0x0000600000027a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0040*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x180], !P0 ; /* 0x0000600003007a0c */
/* 0x000fda0004706670 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*0090*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*00a0*/ MOV R0, c[0x0][0x17c] ; /* 0x00005f0000007a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*00d0*/ MOV R5, UR4 ; /* 0x0000000400057c02 */
/* 0x000fe20008000f00 */
/*00e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00f0*/ LOP3.LUT R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe400078ec0ff */
/*0100*/ SHF.R.U64 R0, R5, 0x2, R0 ; /* 0x0000000205007819 */
/* 0x000fce0000001200 */
/*0110*/ @!P0 BRA 0xf10 ; /* 0x00000df000008947 */
/* 0x000fea0003800000 */
/*0120*/ IADD3 R4, -R2, c[0x0][0x180], RZ ; /* 0x0000600002047a10 */
/* 0x000fe20007ffe1ff */
/*0130*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0140*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0150*/ ISETP.GT.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fce0003f04270 */
/*0160*/ IMAD.WIDE R6, R3, R8, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0208 */
/*0170*/ IMAD.WIDE R10, R3, R8, c[0x0][0x168] ; /* 0x00005a00030a7625 */
/* 0x000fc800078e0208 */
/*0180*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fe200078e0208 */
/*0190*/ @!P0 BRA 0xd10 ; /* 0x00000b7000008947 */
/* 0x000fea0003800000 */
/*01a0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe40003f24270 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01c0*/ @!P1 BRA 0x920 ; /* 0x0000075000009947 */
/* 0x000fea0003800000 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01e0*/ LDG.E R5, [R10.64] ; /* 0x000000060a057981 */
/* 0x002ea8000c1e1900 */
/*01f0*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*0210*/ FADD R5, R5, R12 ; /* 0x0000000c05057221 */
/* 0x004fe40000000000 */
/*0220*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0206 */
/*0230*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0001e8000c101906 */
/*0240*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*0250*/ LDG.E R19, [R12.64] ; /* 0x000000060c137981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fc800078e0208 */
/*0270*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0280*/ FADD R23, R18, R19 ; /* 0x0000001312177221 */
/* 0x004fe40000000000 */
/*0290*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*02a0*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101906 */
/*02b0*/ LDG.E R20, [R18.64] ; /* 0x0000000612147981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ea2000c1e1900 */
/*02d0*/ IMAD.WIDE R6, R0, 0x4, R16 ; /* 0x0000000400067825 */
/* 0x000fc800078e0210 */
/*02e0*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x001fc800078e020a */
/*02f0*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0212 */
/*0300*/ FADD R5, R20, R21 ; /* 0x0000001514057221 */
/* 0x004fca0000000000 */
/*0310*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001e8000c101906 */
/*0320*/ LDG.E R15, [R8.64] ; /* 0x00000006080f7981 */
/* 0x000e68000c1e1900 */
/*0330*/ LDG.E R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000e62000c1e1900 */
/*0340*/ IMAD.WIDE R20, R0, 0x4, R6 ; /* 0x0000000400147825 */
/* 0x000fc800078e0206 */
/*0350*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0208 */
/*0360*/ FADD R23, R14, R15 ; /* 0x0000000f0e177221 */
/* 0x002fe40000000000 */
/*0370*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0380*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0003e8000c101906 */
/*0390*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R19, [R10.64] ; /* 0x000000060a137981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fc800078e0214 */
/*03c0*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc800078e020e */
/*03d0*/ IMAD.WIDE R6, R0, 0x4, R10 ; /* 0x0000000400067825 */
/* 0x001fc800078e020a */
/*03e0*/ FADD R5, R18, R19 ; /* 0x0000001312057221 */
/* 0x004fca0000000000 */
/*03f0*/ STG.E [R16.64], R5 ; /* 0x0000000510007986 */
/* 0x0001e8000c101906 */
/*0400*/ LDG.E R18, [R8.64] ; /* 0x0000000608127981 */
/* 0x000e68000c1e1900 */
/*0410*/ LDG.E R19, [R6.64] ; /* 0x0000000606137981 */
/* 0x000e62000c1e1900 */
/*0420*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0210 */
/*0430*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0440*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0450*/ FADD R23, R18, R19 ; /* 0x0000001312177221 */
/* 0x002fca0000000000 */
/*0460*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x0003e8000c101906 */
/*0470*/ LDG.E R20, [R14.64] ; /* 0x000000060e147981 */
/* 0x000ea8000c1e1900 */
/*0480*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ea2000c1e1900 */
/*0490*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x000fc800078e020c */
/*04a0*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x000fc800078e020a */
/*04b0*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x001fc800078e020e */
/*04c0*/ FADD R5, R20, R21 ; /* 0x0000001514057221 */
/* 0x004fca0000000000 */
/*04d0*/ STG.E [R18.64], R5 ; /* 0x0000000512007986 */
/* 0x0001e8000c101906 */
/*04e0*/ LDG.E R7, [R8.64] ; /* 0x0000000608077981 */
/* 0x000ea8000c1e1900 */
/*04f0*/ LDG.E R6, [R16.64] ; /* 0x0000000610067981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IMAD.WIDE R20, R0, 0x4, R18 ; /* 0x0000000400147825 */
/* 0x000fc800078e0212 */
/*0510*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x002fc800078e0210 */
/*0520*/ FADD R23, R6, R7 ; /* 0x0000000706177221 */
/* 0x004fe40000000000 */
/*0530*/ IMAD.WIDE R6, R0, 0x4, R8 ; /* 0x0000000400067825 */
/* 0x000fc600078e0208 */
/*0540*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0003e8000c101906 */
/*0550*/ LDG.E R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000e28000c1e1900 */
/*0560*/ LDG.E R15, [R6.64] ; /* 0x00000006060f7981 */
/* 0x000e22000c1e1900 */
/*0570*/ IMAD.WIDE R10, R0, 0x4, R20 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0214 */
/*0580*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fc800078e0206 */
/*0590*/ FADD R5, R14, R15 ; /* 0x0000000f0e057221 */
/* 0x001fe40000000000 */
/*05a0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*05b0*/ STG.E [R10.64], R5 ; /* 0x000000050a007986 */
/* 0x0001e8000c101906 */
/*05c0*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000e68000c1e1900 */
/*05d0*/ LDG.E R19, [R8.64] ; /* 0x0000000608137981 */
/* 0x000e62000c1e1900 */
/*05e0*/ IMAD.WIDE R16, R0, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x000fc800078e020a */
/*05f0*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc800078e020e */
/*0600*/ IMAD.WIDE R6, R0, 0x4, R8 ; /* 0x0000000400067825 */
/* 0x000fc800078e0208 */
/*0610*/ FADD R21, R18, R19 ; /* 0x0000001312157221 */
/* 0x002fca0000000000 */
/*0620*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e8000c101906 */
/*0630*/ LDG.E R20, [R12.64] ; /* 0x000000060c147981 */
/* 0x000ea8000c1e1900 */
/*0640*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000ea2000c1e1900 */
/*0650*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc800078e0210 */
/*0660*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x001fc800078e0206 */
/*0670*/ IMAD.WIDE R8, R0, 0x4, R12 ; /* 0x0000000400087825 */
/* 0x000fc800078e020c */
/*0680*/ FADD R23, R20, R23 ; /* 0x0000001714177221 */
/* 0x004fca0000000000 */
/*0690*/ STG.E [R18.64], R23 ; /* 0x0000001712007986 */
/* 0x0001e8000c101906 */
/*06a0*/ LDG.E R20, [R10.64] ; /* 0x000000060a147981 */
/* 0x000ea8000c1e1900 */
/*06b0*/ LDG.E R5, [R8.64] ; /* 0x0000000608057981 */
/* 0x000ea2000c1e1900 */
/*06c0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0212 */
/*06d0*/ IMAD.WIDE R12, R0, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0208 */
/*06e0*/ IMAD.WIDE R6, R0, 0x4, R10 ; /* 0x0000000400067825 */
/* 0x000fc800078e020a */
/*06f0*/ FADD R5, R5, R20 ; /* 0x0000001405057221 */
/* 0x004fca0000000000 */
/*0700*/ STG.E [R14.64], R5 ; /* 0x000000050e007986 */
/* 0x0005e8000c101906 */
/*0710*/ LDG.E R20, [R12.64] ; /* 0x000000060c147981 */
/* 0x000ee8000c1e1900 */
/*0720*/ LDG.E R21, [R6.64] ; /* 0x0000000606157981 */
/* 0x002ee2000c1e1900 */
/*0730*/ IMAD.WIDE R16, R0, 0x4, R14 ; /* 0x0000000400107825 */
/* 0x000fc800078e020e */
/*0740*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0750*/ IMAD.WIDE R8, R0, 0x4, R6 ; /* 0x0000000400087825 */
/* 0x000fc800078e0206 */
/*0760*/ FADD R21, R20, R21 ; /* 0x0000001514157221 */
/* 0x008fca0000000000 */
/*0770*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0003e8000c101906 */
/*0780*/ LDG.E R20, [R10.64] ; /* 0x000000060a147981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R23, [R8.64] ; /* 0x0000000608177981 */
/* 0x001ea2000c1e1900 */
/*07a0*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc800078e0210 */
/*07b0*/ IMAD.WIDE R12, R0, 0x4, R10 ; /* 0x00000004000c7825 */
/* 0x000fc800078e020a */
/*07c0*/ IMAD.WIDE R6, R0, 0x4, R8 ; /* 0x0000000400067825 */
/* 0x000fc800078e0208 */
/*07d0*/ FADD R5, R20, R23 ; /* 0x0000001714057221 */
/* 0x004fca0000000000 */
/*07e0*/ STG.E [R18.64], R5 ; /* 0x0000000512007986 */
/* 0x0001e8000c101906 */
/*07f0*/ LDG.E R20, [R12.64] ; /* 0x000000060c147981 */
/* 0x000ea8000c1e1900 */
/*0800*/ LDG.E R23, [R6.64] ; /* 0x0000000606177981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0212 */
/*0820*/ IMAD.WIDE R16, R0, 0x4, R6 ; /* 0x0000000400107825 */
/* 0x002fc800078e0206 */
/*0830*/ FADD R25, R20, R23 ; /* 0x0000001714197221 */
/* 0x004fe40000000000 */
/*0840*/ IMAD.WIDE R20, R0, 0x4, R12 ; /* 0x0000000400147825 */
/* 0x000fc600078e020c */
/*0850*/ STG.E [R14.64], R25 ; /* 0x000000190e007986 */
/* 0x0003e8000c101906 */
/*0860*/ LDG.E R9, [R16.64] ; /* 0x0000000610097981 */
/* 0x000e28000c1e1900 */
/*0870*/ LDG.E R8, [R20.64] ; /* 0x0000000614087981 */
/* 0x000e22000c1e1900 */
/*0880*/ IADD3 R4, R4, -0x10, RZ ; /* 0xfffffff004047810 */
/* 0x000fe20007ffe0ff */
/*0890*/ IMAD.WIDE R22, R0, 0x4, R14 ; /* 0x0000000400167825 */
/* 0x000fe200078e020e */
/*08a0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc4000fffe03f */
/*08b0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fe20003f24270 */
/*08c0*/ IMAD.WIDE R10, R0, 0x4, R20 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0214 */
/*08d0*/ IMAD.WIDE R6, R0, 0x4, R16 ; /* 0x0000000400067825 */
/* 0x000fc800078e0210 */
/*08e0*/ FADD R5, R8, R9 ; /* 0x0000000908057221 */
/* 0x001fe40000000000 */
/*08f0*/ IMAD.WIDE R8, R0, 0x4, R22 ; /* 0x0000000400087825 */
/* 0x000fc600078e0216 */
/*0900*/ STG.E [R22.64], R5 ; /* 0x0000000516007986 */
/* 0x0003e2000c101906 */
/*0910*/ @P1 BRA 0x1e0 ; /* 0xfffff8c000001947 */
/* 0x000fea000383ffff */
/*0920*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0930*/ @!P1 BRA 0xcf0 ; /* 0x000003b000009947 */
/* 0x000fea0003800000 */
/*0940*/ LDG.E R5, [R10.64] ; /* 0x000000060a057981 */
/* 0x002ea8000c1e1900 */
/*0950*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0960*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*0970*/ FADD R5, R5, R12 ; /* 0x0000000c05057221 */
/* 0x004fe40000000000 */
/*0980*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0206 */
/*0990*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0001e8000c101906 */
/*09a0*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*09b0*/ LDG.E R19, [R12.64] ; /* 0x000000060c137981 */
/* 0x000ea2000c1e1900 */
/*09c0*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fc800078e0208 */
/*09d0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*09e0*/ FADD R23, R18, R19 ; /* 0x0000001312177221 */
/* 0x004fe40000000000 */
/*09f0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0a00*/ STG.E [R16.64], R23 ; /* 0x0000001710007986 */
/* 0x0003e8000c101906 */
/*0a10*/ LDG.E R20, [R18.64] ; /* 0x0000000612147981 */
/* 0x000ea8000c1e1900 */
/*0a20*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IMAD.WIDE R6, R0, 0x4, R16 ; /* 0x0000000400067825 */
/* 0x000fc800078e0210 */
/*0a40*/ IMAD.WIDE R8, R0, 0x4, R10 ; /* 0x0000000400087825 */
/* 0x001fc800078e020a */
/*0a50*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0212 */
/*0a60*/ FADD R5, R20, R21 ; /* 0x0000001514057221 */
/* 0x004fca0000000000 */
/*0a70*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0001e8000c101906 */
/*0a80*/ LDG.E R15, [R8.64] ; /* 0x00000006080f7981 */
/* 0x000e68000c1e1900 */
/*0a90*/ LDG.E R14, [R12.64] ; /* 0x000000060c0e7981 */
/* 0x000e62000c1e1900 */
/*0aa0*/ IMAD.WIDE R20, R0, 0x4, R6 ; /* 0x0000000400147825 */
/* 0x000fc800078e0206 */
/*0ab0*/ IMAD.WIDE R10, R0, 0x4, R8 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0208 */
/*0ac0*/ FADD R23, R14, R15 ; /* 0x0000000f0e177221 */
/* 0x002fe40000000000 */
/*0ad0*/ IMAD.WIDE R14, R0, 0x4, R12 ; /* 0x00000004000e7825 */
/* 0x000fc600078e020c */
/*0ae0*/ STG.E [R20.64], R23 ; /* 0x0000001714007986 */
/* 0x0003e8000c101906 */
/*0af0*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*0b00*/ LDG.E R19, [R10.64] ; /* 0x000000060a137981 */
/* 0x000ea2000c1e1900 */
/*0b10*/ IMAD.WIDE R16, R0, 0x4, R20 ; /* 0x0000000400107825 */
/* 0x000fc800078e0214 */
/*0b20*/ IMAD.WIDE R8, R0, 0x4, R14 ; /* 0x0000000400087825 */
/* 0x000fc800078e020e */
/*0b30*/ IMAD.WIDE R6, R0, 0x4, R10 ; /* 0x0000000400067825 */
/* 0x001fc800078e020a */
/*0b40*/ FADD R5, R18, R19 ; /* 0x0000001312057221 */
/* 0x004fca0000000000 */
/*0b50*/ STG.E [R16.64], R5 ; /* 0x0000000510007986 */
/* 0x0001e8000c101906 */
/*0b60*/ LDG.E R18, [R8.64] ; /* 0x0000000608127981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R19, [R6.64] ; /* 0x0000000606137981 */
/* 0x000ea2000c1e1900 */
/*0b80*/ IMAD.WIDE R12, R0, 0x4, R16 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0210 */
/*0b90*/ IMAD.WIDE R14, R0, 0x4, R8 ; /* 0x00000004000e7825 */
/* 0x000fc800078e0208 */
/*0ba0*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0206 */
/*0bb0*/ FADD R25, R18, R19 ; /* 0x0000001312197221 */
/* 0x004fca0000000000 */
/*0bc0*/ STG.E [R12.64], R25 ; /* 0x000000190c007986 */
/* 0x0005e8000c101906 */
/*0bd0*/ LDG.E R20, [R14.64] ; /* 0x000000060e147981 */
/* 0x002ee8000c1e1900 */
/*0be0*/ LDG.E R21, [R10.64] ; /* 0x000000060a157981 */
/* 0x000ee2000c1e1900 */
/*0bf0*/ IMAD.WIDE R18, R0, 0x4, R12 ; /* 0x0000000400127825 */
/* 0x000fc800078e020c */
/*0c00*/ IMAD.WIDE R16, R0, 0x4, R10 ; /* 0x0000000400107825 */
/* 0x001fc800078e020a */
/*0c10*/ FADD R5, R20, R21 ; /* 0x0000001514057221 */
/* 0x008fe40000000000 */
/*0c20*/ IMAD.WIDE R20, R0, 0x4, R14 ; /* 0x0000000400147825 */
/* 0x000fc600078e020e */
/*0c30*/ STG.E [R18.64], R5 ; /* 0x0000000512007986 */
/* 0x0001e8000c101906 */
/*0c40*/ LDG.E R7, [R16.64] ; /* 0x0000000610077981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ LDG.E R6, [R20.64] ; /* 0x0000000614067981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ IMAD.WIDE R22, R0, 0x4, R18 ; /* 0x0000000400167825 */
/* 0x000fe200078e0212 */
/*0c70*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0c80*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0c90*/ IADD3 R4, R4, -0x8, RZ ; /* 0xfffffff804047810 */
/* 0x000fe20007ffe0ff */
/*0ca0*/ IMAD.WIDE R10, R0, 0x4, R20 ; /* 0x00000004000a7825 */
/* 0x000fc800078e0214 */
/*0cb0*/ IMAD.WIDE R8, R0, 0x4, R22 ; /* 0x0000000400087825 */
/* 0x000fc800078e0216 */
/*0cc0*/ FADD R13, R6, R7 ; /* 0x00000007060d7221 */
/* 0x004fe40000000000 */
/*0cd0*/ IMAD.WIDE R6, R0, 0x4, R16 ; /* 0x0000000400067825 */
/* 0x000fc600078e0210 */
/*0ce0*/ STG.E [R22.64], R13 ; /* 0x0000000d16007986 */
/* 0x0001e8000c101906 */
/*0cf0*/ ISETP.NE.OR P0, PT, R4, RZ, P0 ; /* 0x000000ff0400720c */
/* 0x000fda0000705670 */
/*0d00*/ @!P0 BRA 0xf10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0d10*/ LDG.E R5, [R10.64] ; /* 0x000000060a057981 */
/* 0x003ea8000c1e1900 */
/*0d20*/ LDG.E R12, [R6.64] ; /* 0x00000006060c7981 */
/* 0x000ea2000c1e1900 */
/*0d30*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*0d40*/ FADD R5, R5, R12 ; /* 0x0000000c05057221 */
/* 0x004fe40000000000 */
/*0d50*/ IMAD.WIDE R12, R0, 0x4, R6 ; /* 0x00000004000c7825 */
/* 0x000fc600078e0206 */
/*0d60*/ STG.E [R8.64], R5 ; /* 0x0000000508007986 */
/* 0x0001e8000c101906 */
/*0d70*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*0d80*/ LDG.E R19, [R12.64] ; /* 0x000000060c137981 */
/* 0x000ea2000c1e1900 */
/*0d90*/ IMAD.WIDE R16, R0, 0x4, R8 ; /* 0x0000000400107825 */
/* 0x000fc800078e0208 */
/*0da0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0db0*/ FADD R25, R18, R19 ; /* 0x0000001312197221 */
/* 0x004fe40000000000 */
/*0dc0*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fc600078e020e */
/*0dd0*/ STG.E [R16.64], R25 ; /* 0x0000001910007986 */
/* 0x0003e8000c101906 */
/*0de0*/ LDG.E R6, [R18.64] ; /* 0x0000000612067981 */
/* 0x000e28000c1e1900 */
/*0df0*/ LDG.E R7, [R10.64] ; /* 0x000000060a077981 */
/* 0x000e22000c1e1900 */
/*0e00*/ IMAD.WIDE R20, R0, 0x4, R16 ; /* 0x0000000400147825 */
/* 0x000fc800078e0210 */
/*0e10*/ IMAD.WIDE R14, R0, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x000fc800078e020a */
/*0e20*/ IMAD.WIDE R12, R0, 0x4, R18 ; /* 0x00000004000c7825 */
/* 0x000fc800078e0212 */
/*0e30*/ FADD R5, R6, R7 ; /* 0x0000000706057221 */
/* 0x001fca0000000000 */
/*0e40*/ STG.E [R20.64], R5 ; /* 0x0000000514007986 */
/* 0x0001e8000c101906 */
/*0e50*/ LDG.E R7, [R14.64] ; /* 0x000000060e077981 */
/* 0x000e68000c1e1900 */
/*0e60*/ LDG.E R6, [R12.64] ; /* 0x000000060c067981 */
/* 0x000e62000c1e1900 */
/*0e70*/ IADD3 R4, R4, -0x4, RZ ; /* 0xfffffffc04047810 */
/* 0x000fe20007ffe0ff */
/*0e80*/ IMAD.WIDE R22, R0, 0x4, R20 ; /* 0x0000000400167825 */
/* 0x000fe200078e0214 */
/*0e90*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc4000fffe03f */
/*0ea0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0eb0*/ IMAD.WIDE R10, R0, 0x4, R12 ; /* 0x00000004000a7825 */
/* 0x000fc800078e020c */
/*0ec0*/ IMAD.WIDE R8, R0, 0x4, R22 ; /* 0x0000000400087825 */
/* 0x000fc800078e0216 */
/*0ed0*/ FADD R17, R6, R7 ; /* 0x0000000706117221 */
/* 0x002fe40000000000 */
/*0ee0*/ IMAD.WIDE R6, R0, 0x4, R14 ; /* 0x0000000400067825 */
/* 0x000fc600078e020e */
/*0ef0*/ STG.E [R22.64], R17 ; /* 0x0000001116007986 */
/* 0x0001e4000c101906 */
/*0f00*/ @P0 BRA 0xd10 ; /* 0xfffffe0000000947 */
/* 0x001fea000383ffff */
/*0f10*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fda0003f05270 */
/*0f20*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0f30*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0f40*/ IMAD R3, R0, UR4, R3 ; /* 0x0000000400037c24 */
/* 0x000fd2000f8e0203 */
/*0f50*/ IMAD.WIDE R4, R3, R8, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x003fc800078e0208 */
/*0f60*/ IMAD.WIDE R6, R3, R8, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fc800078e0208 */
/*0f70*/ IMAD.WIDE R8, R3, R8, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fc800078e0208 */
/*0f80*/ LDG.E R3, [R6.64] ; /* 0x0000000606037981 */
/* 0x0000a8000c1e1900 */
/*0f90*/ LDG.E R10, [R8.64] ; /* 0x00000006080a7981 */
/* 0x0002a2000c1e1900 */
/*0fa0*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fc80007ffe0ff */
/*0fb0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0fc0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*0fd0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fc800078e0208 */
/*0fe0*/ FADD R3, R3, R10 ; /* 0x0000000a03037221 */
/* 0x004fca0000000000 */
/*0ff0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001e4000c101906 */
/*1000*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x001fe200078e0204 */
/*1010*/ @P0 BRA 0xf80 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*1020*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*1030*/ BRA 0x1030; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18matrixAdd_C_KernelPfS_S_mi
.globl _Z18matrixAdd_C_KernelPfS_S_mi
.p2align 8
.type _Z18matrixAdd_C_KernelPfS_S_mi,@function
_Z18matrixAdd_C_KernelPfS_S_mi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v0, 0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_load_b256 s[0:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_alignbit_b32 v0, s7, s6, 2
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s8, s8, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s8, 0
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
global_load_b32 v4, v[4:5], off
global_load_b32 v5, v[6:7], off
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v5
global_store_b32 v[2:3], v4, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18matrixAdd_C_KernelPfS_S_mi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18matrixAdd_C_KernelPfS_S_mi, .Lfunc_end0-_Z18matrixAdd_C_KernelPfS_S_mi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18matrixAdd_C_KernelPfS_S_mi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18matrixAdd_C_KernelPfS_S_mi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00006656_00000000-6_matrixAdd_C_Kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi
.type _Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi, @function
_Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z18matrixAdd_C_KernelPfS_S_mi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi, .-_Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi
.globl _Z18matrixAdd_C_KernelPfS_S_mi
.type _Z18matrixAdd_C_KernelPfS_S_mi, @function
_Z18matrixAdd_C_KernelPfS_S_mi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z18matrixAdd_C_KernelPfS_S_miPfS_S_mi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18matrixAdd_C_KernelPfS_S_mi, .-_Z18matrixAdd_C_KernelPfS_S_mi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18matrixAdd_C_KernelPfS_S_mi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18matrixAdd_C_KernelPfS_S_mi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixAdd_C_Kernel.hip"
.globl _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi # -- Begin function _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.p2align 4, 0x90
.type _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi,@function
_Z33__device_stub__matrixAdd_C_KernelPfS_S_mi: # @_Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z18matrixAdd_C_KernelPfS_S_mi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi, .Lfunc_end0-_Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18matrixAdd_C_KernelPfS_S_mi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18matrixAdd_C_KernelPfS_S_mi,@object # @_Z18matrixAdd_C_KernelPfS_S_mi
.section .rodata,"a",@progbits
.globl _Z18matrixAdd_C_KernelPfS_S_mi
.p2align 3, 0x0
_Z18matrixAdd_C_KernelPfS_S_mi:
.quad _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.size _Z18matrixAdd_C_KernelPfS_S_mi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18matrixAdd_C_KernelPfS_S_mi"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__matrixAdd_C_KernelPfS_S_mi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18matrixAdd_C_KernelPfS_S_mi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include "functions.cuh"
__global__
void KernelAdd(int n, float * p_sum, float * x, float * y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n )
p_sum[i] = x[i] + y[i];
}
void DeviceKernel(int numBlocks, int sizeBlock, int n, float * p_sum, float * x, float * y){
KernelAdd <<<numBlocks, sizeBlock>>> (n, p_sum, x, y); // vector addition on DEVICE simple
} | code for sm_80
Function : _Z9KernelAddiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x178] ; /* 0x00005e0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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