system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7x_dot_wPfS_S_jjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ MOV R3, c[0x0][0x17c] ; /* 0x00005f0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R19, -RZ, RZ, 0, 0 ; /* 0x00000000ff137435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e620000002600 */
/*0060*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0070*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe20000000f00 */
/*0080*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002500 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R3.reuse, 0xa, PT ; /* 0x0000000a0300780c */
/* 0x040fe20003f06070 */
/*00a0*/ IMAD.WIDE.U32 R4, R3, -0x33333333, RZ ; /* 0xcccccccd03047825 */
/* 0x000fc400078e00ff */
/*00b0*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000ea60000002100 */
/*00c0*/ LEA.HI R10, R5, 0x1, RZ, 0x1d ; /* 0x00000001050a7811 */
/* 0x000fe200078fe8ff */
/*00d0*/ IMAD R5, R0, 0x28, RZ ; /* 0x0000002800057824 */
/* 0x001fe400078e02ff */
/*00e0*/ IMAD R3, R9, c[0x0][0x4], R0 ; /* 0x0000010009037a24 */
/* 0x002fe200078e0200 */
/*00f0*/ LOP3.LUT R9, R10, 0x1, RZ, 0xc0, !PT ; /* 0x000000010a097812 */
/* 0x000fe200078ec0ff */
/*0100*/ IMAD R4, R7, c[0x0][0x0], R2.reuse ; /* 0x0000000007047a24 */
/* 0x104fe200078e0202 */
/*0110*/ LEA R8, R2, R5, 0x2 ; /* 0x0000000502087211 */
/* 0x000fe200078e10ff */
/*0120*/ IMAD R6, R3, c[0x0][0x17c], R2 ; /* 0x00005f0003067a24 */
/* 0x000fe200078e0202 */
/*0130*/ @!P0 BRA 0x760 ; /* 0x0000062000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f26070 */
/*0150*/ IADD3 R10, R10, -R9, RZ ; /* 0x800000090a0a7210 */
/* 0x000fc40007ffe0ff */
/*0160*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R19, RZ ; /* 0x000000ff00137202 */
/* 0x000fc60000000f00 */
/*0180*/ IMAD R11, R7.reuse, 0xa, R0 ; /* 0x0000000a070b7824 */
/* 0x040fe200078e0200 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fe20003f06070 */
/*01a0*/ IMAD R12, R7, 0xa, R2 ; /* 0x0000000a070c7824 */
/* 0x000fe200078e0202 */
/*01b0*/ MOV R25, RZ ; /* 0x000000ff00197202 */
/* 0x000fe40000000f00 */
/*01c0*/ ISETP.GE.U32.OR P3, PT, R11, c[0x0][0x17c], P0 ; /* 0x00005f000b007a0c */
/* 0x000fe40000766470 */
/*01d0*/ ISETP.GE.U32.OR P2, PT, R12, c[0x0][0x17c], P1 ; /* 0x00005f000c007a0c */
/* 0x000fd60000f46470 */
/*01e0*/ @!P3 IMAD R20, R11, c[0x0][0x180], R4 ; /* 0x000060000b14ba24 */
/* 0x000fe200078e0204 */
/*01f0*/ @!P3 MOV R21, 0x4 ; /* 0x000000040015b802 */
/* 0x000fe20000000f00 */
/*0200*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*0210*/ @!P2 MOV R15, 0x4 ; /* 0x00000004000fa802 */
/* 0x000fe20000000f00 */
/*0220*/ @!P2 IMAD R14, R7, 0xa, R6 ; /* 0x0000000a070ea824 */
/* 0x000fe400078e0206 */
/*0230*/ @!P3 IMAD.WIDE.U32 R20, R20, R21, c[0x0][0x168] ; /* 0x00005a001414b625 */
/* 0x000fc800078e0015 */
/*0240*/ @!P2 IMAD.WIDE.U32 R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0ea625 */
/* 0x000fe200078e000f */
/*0250*/ @!P3 LDG.E R25, [R20.64] ; /* 0x000000041419b981 */
/* 0x0000a8000c1e1900 */
/*0260*/ @!P2 LDG.E R11, [R14.64] ; /* 0x000000040e0ba981 */
/* 0x000ee2000c1e1900 */
/*0270*/ HFMA2.MMA R20, -RZ, RZ, 0, 5.9604644775390625e-07 ; /* 0x0000000aff147435 */
/* 0x001fe400000001ff */
/*0280*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0290*/ STS [R8+0x190], R25 ; /* 0x0001901908007388 */
/* 0x004fe80000000800 */
/*02a0*/ STS [R8], R11 ; /* 0x0000000b08007388 */
/* 0x0081e80000000800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDS R18, [R2.X4+0x190] ; /* 0x0001900002127984 */
/* 0x000fe80000004800 */
/*02d0*/ LDS.64 R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000e680000000a00 */
/*02e0*/ LDS R22, [R2.X4+0x1b8] ; /* 0x0001b80002167984 */
/* 0x000ea80000004800 */
/*02f0*/ LDS R24, [R2.X4+0x1e0] ; /* 0x0001e00002187984 */
/* 0x000fe80000004800 */
/*0300*/ LDS.64 R16, [R5+0x8] ; /* 0x0000080005107984 */
/* 0x000ee80000000a00 */
/*0310*/ LDS R26, [R2.X4+0x208] ; /* 0x00020800021a7984 */
/* 0x000f280000004800 */
/*0320*/ LDS R23, [R2.X4+0x230] ; /* 0x0002300002177984 */
/* 0x000fe80000004800 */
/*0330*/ LDS.64 R14, [R5+0x10] ; /* 0x00001000050e7984 */
/* 0x000f620000000a00 */
/*0340*/ IMAD R11, R7, R20, 0xa ; /* 0x0000000a070b7424 */
/* 0x001fc600078e0214 */
/*0350*/ LDS R28, [R2.X4+0x258] ; /* 0x00025800021c7984 */
/* 0x000e240000004800 */
/*0360*/ IADD3 R20, R11, R2, RZ ; /* 0x000000020b147210 */
/* 0x000fe40007ffe0ff */
/*0370*/ LDS R29, [R2.X4+0x280] ; /* 0x00028000021d7984 */
/* 0x000fe40000004800 */
/*0380*/ ISETP.GE.U32.OR P2, PT, R20, c[0x0][0x17c], P1 ; /* 0x00005f0014007a0c */
/* 0x000fe40000f46470 */
/*0390*/ LDS R25, [R2.X4+0x2d0] ; /* 0x0002d00002197984 */
/* 0x000fe20000004800 */
/*03a0*/ FFMA R12, R18, R12, R19 ; /* 0x0000000c120c7223 */
/* 0x002fc60000000013 */
/*03b0*/ LDS.64 R18, [R5+0x18] ; /* 0x0000180005127984 */
/* 0x000e620000000a00 */
/*03c0*/ FFMA R13, R22, R13, R12 ; /* 0x0000000d160d7223 */
/* 0x004fcc000000000c */
/*03d0*/ @!P2 IADD3 R22, R6, R11, RZ ; /* 0x0000000b0616a210 */
/* 0x000fe20007ffe0ff */
/*03e0*/ FFMA R16, R24, R16, R13 ; /* 0x0000001018107223 */
/* 0x008fe2000000000d */
/*03f0*/ @!P2 MOV R13, 0x4 ; /* 0x00000004000da802 */
/* 0x000fe20000000f00 */
/*0400*/ LDS R24, [R2.X4+0x2f8] ; /* 0x0002f80002187984 */
/* 0x000fe40000004800 */
/*0410*/ FFMA R16, R26, R17, R16 ; /* 0x000000111a107223 */
/* 0x010fe20000000010 */
/*0420*/ IADD3 R17, R11, R0, RZ ; /* 0x000000000b117210 */
/* 0x000fe20007ffe0ff */
/*0430*/ LDS R26, [R2.X4+0x2a8] ; /* 0x0002a800021a7984 */
/* 0x000ea60000004800 */
/*0440*/ ISETP.GE.U32.OR P0, PT, R17, c[0x0][0x17c], P0 ; /* 0x00005f0011007a0c */
/* 0x000fe20000706470 */
/*0450*/ FFMA R14, R23, R14, R16 ; /* 0x0000000e170e7223 */
/* 0x020fc40000000010 */
/*0460*/ @!P2 IMAD.WIDE.U32 R22, R22, R13, c[0x0][0x160] ; /* 0x000058001616a625 */
/* 0x000fe400078e000d */
/*0470*/ LDS.64 R12, [R5+0x20] ; /* 0x00002000050c7984 */
/* 0x000ee80000000a00 */
/*0480*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0490*/ @!P0 IMAD R20, R17, c[0x0][0x180], R4 ; /* 0x0000600011148a24 */
/* 0x000fe200078e0204 */
/*04a0*/ @!P0 MOV R21, 0x4 ; /* 0x0000000400158802 */
/* 0x000fe20000000f00 */
/*04b0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fc800000001ff */
/*04c0*/ @!P0 IMAD.WIDE.U32 R20, R20, R21, c[0x0][0x168] ; /* 0x00005a0014148625 */
/* 0x000fe200078e0015 */
/*04d0*/ @!P2 LDG.E R27, [R22.64] ; /* 0x00000004161ba981 */
/* 0x000f2a000c1e1900 */
/*04e0*/ @!P0 LDG.E R17, [R20.64] ; /* 0x0000000414118981 */
/* 0x000f62000c1e1900 */
/*04f0*/ FFMA R14, R28, R15, R14 ; /* 0x0000000f1c0e7223 */
/* 0x001fc8000000000e */
/*0500*/ FFMA R18, R29, R18, R14 ; /* 0x000000121d127223 */
/* 0x002fc8000000000e */
/*0510*/ FFMA R18, R26, R19, R18 ; /* 0x000000131a127223 */
/* 0x004fc80000000012 */
/*0520*/ FFMA R12, R25, R12, R18 ; /* 0x0000000c190c7223 */
/* 0x008fc80000000012 */
/*0530*/ FFMA R12, R24, R13, R12 ; /* 0x0000000d180c7223 */
/* 0x000fe2000000000c */
/*0540*/ IADD3 R10, R10, -0x2, RZ ; /* 0xfffffffe0a0a7810 */
/* 0x000fc80007ffe0ff */
/*0550*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*0560*/ IADD3 R7, R7, 0x2, RZ ; /* 0x0000000207077810 */
/* 0x000fe20007ffe0ff */
/*0570*/ STS [R8], R27 ; /* 0x0000001b08007388 */
/* 0x010fe80000000800 */
/*0580*/ STS [R8+0x190], R17 ; /* 0x0001901108007388 */
/* 0x020fe80000000800 */
/*0590*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*05a0*/ LDS R27, [R2.X4+0x190] ; /* 0x00019000021b7984 */
/* 0x000fe80000004800 */
/*05b0*/ LDS.64 R16, [R5] ; /* 0x0000000005107984 */
/* 0x000e280000000a00 */
/*05c0*/ LDS R22, [R2.X4+0x1b8] ; /* 0x0001b80002167984 */
/* 0x000e680000004800 */
/*05d0*/ LDS R23, [R2.X4+0x1e0] ; /* 0x0001e00002177984 */
/* 0x000fe80000004800 */
/*05e0*/ LDS.64 R14, [R5+0x8] ; /* 0x00000800050e7984 */
/* 0x000ea80000000a00 */
/*05f0*/ LDS R20, [R2.X4+0x208] ; /* 0x0002080002147984 */
/* 0x000ee80000004800 */
/*0600*/ LDS R21, [R2.X4+0x230] ; /* 0x0002300002157984 */
/* 0x000fe80000004800 */
/*0610*/ LDS.64 R18, [R5+0x10] ; /* 0x0000100005127984 */
/* 0x000f280000000a00 */
/*0620*/ LDS R24, [R2.X4+0x258] ; /* 0x0002580002187984 */
/* 0x000f680000004800 */
/*0630*/ LDS R25, [R2.X4+0x280] ; /* 0x0002800002197984 */
/* 0x000fe20000004800 */
/*0640*/ FFMA R16, R27, R16, R12 ; /* 0x000000101b107223 */
/* 0x001fc6000000000c */
/*0650*/ LDS.64 R12, [R5+0x18] ; /* 0x00001800050c7984 */
/* 0x000e220000000a00 */
/*0660*/ FFMA R16, R22, R17, R16 ; /* 0x0000001116107223 */
/* 0x002fc60000000010 */
/*0670*/ LDS R22, [R2.X4+0x2a8] ; /* 0x0002a80002167984 */
/* 0x000e620000004800 */
/*0680*/ FFMA R26, R23, R14, R16 ; /* 0x0000000e171a7223 */
/* 0x004fc60000000010 */
/*0690*/ LDS R23, [R2.X4+0x2d0] ; /* 0x0002d00002177984 */
/* 0x000fe80000004800 */
/*06a0*/ LDS.64 R16, [R5+0x20] ; /* 0x0000200005107984 */
/* 0x000ea80000000a00 */
/*06b0*/ LDS R14, [R2.X4+0x2f8] ; /* 0x0002f800020e7984 */
/* 0x000ea20000004800 */
/*06c0*/ FFMA R15, R20, R15, R26 ; /* 0x0000000f140f7223 */
/* 0x008fc8000000001a */
/*06d0*/ FFMA R15, R21, R18, R15 ; /* 0x00000012150f7223 */
/* 0x010fc8000000000f */
/*06e0*/ FFMA R15, R24, R19, R15 ; /* 0x00000013180f7223 */
/* 0x020fc8000000000f */
/*06f0*/ FFMA R12, R25, R12, R15 ; /* 0x0000000c190c7223 */
/* 0x001fc8000000000f */
/*0700*/ FFMA R12, R22, R13, R12 ; /* 0x0000000d160c7223 */
/* 0x002fc8000000000c */
/*0710*/ FFMA R12, R23, R16, R12 ; /* 0x00000010170c7223 */
/* 0x004fc8000000000c */
/*0720*/ FFMA R19, R14, R17, R12 ; /* 0x000000110e137223 */
/* 0x000fe2000000000c */
/*0730*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0740*/ @P0 BRA 0x180 ; /* 0xfffffa3000000947 */
/* 0x000fea000383ffff */
/*0750*/ IADD3 R11, R11, 0xa, RZ ; /* 0x0000000a0b0b7810 */
/* 0x000fe40007ffe0ff */
/*0760*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0770*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x180], PT ; /* 0x0000600004007a0c */
/* 0x000fc80003f06070 */
/*0780*/ ISETP.GE.U32.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fce0000706470 */
/*0790*/ @!P1 BRA 0xa70 ; /* 0x000002d000009947 */
/* 0x000fec0003800000 */
/*07a0*/ IADD3 R9, R2, R11.reuse, RZ ; /* 0x0000000b02097210 */
/* 0x080fe20007ffe0ff */
/*07b0*/ HFMA2.MMA R17, -RZ, RZ, 0, 0 ; /* 0x00000000ff117435 */
/* 0x000fe200000001ff */
/*07c0*/ IADD3 R7, R0, R11, RZ ; /* 0x0000000b00077210 */
/* 0x000fe40007ffe0ff */
/*07d0*/ ISETP.GE.U32.AND P1, PT, R9, c[0x0][0x17c], PT ; /* 0x00005f0009007a0c */
/* 0x000fe40003f26070 */
/*07e0*/ ISETP.GE.U32.AND P2, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe40003f46070 */
/*07f0*/ ISETP.GE.U32.OR P1, PT, R3, c[0x0][0x178], P1 ; /* 0x00005e0003007a0c */
/* 0x000fe40000f26470 */
/*0800*/ ISETP.GE.U32.OR P2, PT, R4, c[0x0][0x180], P2 ; /* 0x0000600004007a0c */
/* 0x000fc40001746470 */
/*0810*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fd20000000f00 */
/*0820*/ @!P1 IADD3 R6, R6, R11, RZ ; /* 0x0000000b06069210 */
/* 0x000fe40007ffe0ff */
/*0830*/ @!P1 MOV R11, 0x4 ; /* 0x00000004000b9802 */
/* 0x000fe20000000f00 */
/*0840*/ @!P2 IMAD R10, R7, c[0x0][0x180], R4 ; /* 0x00006000070aaa24 */
/* 0x000fe200078e0204 */
/*0850*/ @!P2 MOV R13, 0x4 ; /* 0x00000004000da802 */
/* 0x000fc60000000f00 */
/*0860*/ @!P1 IMAD.WIDE.U32 R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006069625 */
/* 0x000fc800078e000b */
/*0870*/ @!P2 IMAD.WIDE.U32 R10, R10, R13, c[0x0][0x168] ; /* 0x00005a000a0aa625 */
/* 0x000fe200078e000d */
/*0880*/ @!P1 LDG.E R17, [R6.64] ; /* 0x0000000406119981 */
/* 0x000ea8000c1e1900 */
/*0890*/ @!P2 LDG.E R9, [R10.64] ; /* 0x000000040a09a981 */
/* 0x000ee8000c1e1900 */
/*08a0*/ STS [R8], R17 ; /* 0x0000001108007388 */
/* 0x004fe80000000800 */
/*08b0*/ STS [R8+0x190], R9 ; /* 0x0001900908007388 */
/* 0x008fe80000000800 */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08d0*/ LDS R20, [R2.X4+0x190] ; /* 0x0001900002147984 */
/* 0x000fe80000004800 */
/*08e0*/ LDS.64 R14, [R5] ; /* 0x00000000050e7984 */
/* 0x000e280000000a00 */
/*08f0*/ LDS R22, [R2.X4+0x1b8] ; /* 0x0001b80002167984 */
/* 0x000e680000004800 */
/*0900*/ LDS R23, [R2.X4+0x1e0] ; /* 0x0001e00002177984 */
/* 0x000fe80000004800 */
/*0910*/ LDS.64 R12, [R5+0x8] ; /* 0x00000800050c7984 */
/* 0x000ea80000000a00 */
/*0920*/ LDS R24, [R2.X4+0x208] ; /* 0x0002080002187984 */
/* 0x000ee80000004800 */
/*0930*/ LDS R25, [R2.X4+0x230] ; /* 0x0002300002197984 */
/* 0x000fe80000004800 */
/*0940*/ LDS.64 R10, [R5+0x10] ; /* 0x00001000050a7984 */
/* 0x000f280000000a00 */
/*0950*/ LDS R16, [R2.X4+0x258] ; /* 0x0002580002107984 */
/* 0x000f680000004800 */
/*0960*/ LDS R21, [R2.X4+0x280] ; /* 0x0002800002157984 */
/* 0x000fe80000004800 */
/*0970*/ LDS.64 R6, [R5+0x18] ; /* 0x0000180005067984 */
/* 0x000f680000000a00 */
/*0980*/ LDS R0, [R2.X4+0x2a8] ; /* 0x0002a80002007984 */
/* 0x000f620000004800 */
/*0990*/ FFMA R14, R20, R14, R19 ; /* 0x0000000e140e7223 */
/* 0x001fc60000000013 */
/*09a0*/ LDS R17, [R2.X4+0x2d0] ; /* 0x0002d00002117984 */
/* 0x000fe20000004800 */
/*09b0*/ FFMA R15, R22, R15, R14 ; /* 0x0000000f160f7223 */
/* 0x002fc6000000000e */
/*09c0*/ LDS.64 R8, [R5+0x20] ; /* 0x0000200005087984 */
/* 0x000e280000000a00 */
/*09d0*/ LDS R18, [R2.X4+0x2f8] ; /* 0x0002f80002127984 */
/* 0x000e620000004800 */
/*09e0*/ FFMA R12, R23, R12, R15 ; /* 0x0000000c170c7223 */
/* 0x004fc8000000000f */
/*09f0*/ FFMA R13, R24, R13, R12 ; /* 0x0000000d180d7223 */
/* 0x008fc8000000000c */
/*0a00*/ FFMA R10, R25, R10, R13 ; /* 0x0000000a190a7223 */
/* 0x010fc8000000000d */
/*0a10*/ FFMA R10, R16, R11, R10 ; /* 0x0000000b100a7223 */
/* 0x020fc8000000000a */
/*0a20*/ FFMA R6, R21, R6, R10 ; /* 0x0000000615067223 */
/* 0x000fc8000000000a */
/*0a30*/ FFMA R0, R0, R7, R6 ; /* 0x0000000700007223 */
/* 0x000fc80000000006 */
/*0a40*/ FFMA R0, R17, R8, R0 ; /* 0x0000000811007223 */
/* 0x001fc80000000000 */
/*0a50*/ FFMA R19, R18, R9, R0 ; /* 0x0000000912137223 */
/* 0x002fe20000000000 */
/*0a60*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0a70*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0a80*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0a90*/ IMAD R3, R3, c[0x0][0x180], R4 ; /* 0x0000600003037a24 */
/* 0x000fd200078e0204 */
/*0aa0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0002 */
/*0ab0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe2000c101904 */
/*0ac0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ad0*/ BRA 0xad0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7x_dot_wPfS_S_jjj
.globl _Z7x_dot_wPfS_S_jjj
.p2align 8
.type _Z7x_dot_wPfS_S_jjj,@function
_Z7x_dot_wPfS_S_jjj:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s13, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v5, 2, v1
v_mov_b32_e32 v9, 0
v_mul_u32_u24_e32 v10, 40, v0
v_add_nc_u32_e32 v12, 0x190, v5
v_mad_u32_u24 v11, v0, 40, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u32_u24 v13, v0, 40, v12
s_waitcnt lgkmcnt(0)
s_and_b32 s10, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_add_i32 s2, s9, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s11, s2, 0xcccccccd
s_lshr_b32 s11, s11, 3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[3:4], null, s14, s10, v[1:2]
v_mad_u64_u32 v[4:5], null, v2, s9, v[1:2]
v_cmp_gt_u32_e32 vcc_lo, s8, v2
v_cmp_le_u32_e64 s10, s8, v2
v_cmp_gt_u32_e64 s2, s3, v3
s_delay_alu instid0(VALU_DEP_1)
s_xor_b32 s12, s2, -1
.LBB0_1:
s_delay_alu instid0(VALU_DEP_2)
s_mov_b32 s2, s10
s_mov_b32 s14, 0
s_and_saveexec_b32 s15, vcc_lo
s_mul_i32 s16, s13, 10
s_mov_b32 s14, exec_lo
v_dual_mov_b32 v14, s16 :: v_dual_add_nc_u32 v5, s16, v1
s_and_not1_b32 s16, s10, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s9, v5
s_and_b32 s2, s2, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s16, s2
s_or_b32 exec_lo, exec_lo, s15
s_and_saveexec_b32 s15, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s15
s_cbranch_execz .LBB0_5
s_and_not1_b32 s14, s14, exec_lo
ds_store_b32 v11, v6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s15, s14
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v5, v4, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[5:6]
v_add_co_u32 v7, s2, s4, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, s5, v8, s2
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b32 v11, v5
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s15
v_mad_u64_u32 v[7:8], null, s13, 10, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s2, s9, v7
s_or_b32 s2, s12, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_saveexec_b32 s14, s2
s_xor_b32 s2, exec_lo, s14
s_cbranch_execz .LBB0_9
ds_store_b32 v13, v6
.LBB0_9:
s_and_not1_saveexec_b32 s14, s2
s_cbranch_execz .LBB0_11
v_mad_u64_u32 v[15:16], null, v7, s3, v[3:4]
v_mov_b32_e32 v16, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 2, v[15:16]
v_add_co_u32 v7, s2, s6, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, s7, v8, s2
global_load_b32 v5, v[7:8], off
s_waitcnt vmcnt(0)
ds_store_b32 v13, v5
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s14
v_mov_b32_e32 v5, v12
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_12:
v_add_nc_u32_e32 v7, s2, v10
s_add_i32 s2, s2, 4
ds_load_b32 v8, v5
ds_load_b32 v7, v7
v_add_nc_u32_e32 v5, 40, v5
s_cmp_eq_u32 s2, 40
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v9, v7, v8
s_cbranch_scc0 .LBB0_12
s_add_i32 s2, s13, 1
s_cmp_eq_u32 s13, s11
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_15
s_mov_b32 s13, s2
s_branch .LBB0_1
.LBB0_15:
v_cmp_gt_u32_e32 vcc_lo, s8, v2
v_cmp_gt_u32_e64 s2, s3, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_17
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v2, s3, v[3:4]
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v9, off
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7x_dot_wPfS_S_jjj
.amdhsa_group_segment_fixed_size 800
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7x_dot_wPfS_S_jjj, .Lfunc_end0-_Z7x_dot_wPfS_S_jjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 800
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7x_dot_wPfS_S_jjj
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z7x_dot_wPfS_S_jjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003e1ff_00000000-6_x_dot_w_tile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj
.type _Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj, @function
_Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7x_dot_wPfS_S_jjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj, .-_Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj
.globl _Z7x_dot_wPfS_S_jjj
.type _Z7x_dot_wPfS_S_jjj, @function
_Z7x_dot_wPfS_S_jjj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7x_dot_wPfS_S_jjjPfS_S_jjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7x_dot_wPfS_S_jjj, .-_Z7x_dot_wPfS_S_jjj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7x_dot_wPfS_S_jjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7x_dot_wPfS_S_jjj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "x_dot_w_tile.hip"
.globl _Z22__device_stub__x_dot_wPfS_S_jjj # -- Begin function _Z22__device_stub__x_dot_wPfS_S_jjj
.p2align 4, 0x90
.type _Z22__device_stub__x_dot_wPfS_S_jjj,@function
_Z22__device_stub__x_dot_wPfS_S_jjj: # @_Z22__device_stub__x_dot_wPfS_S_jjj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7x_dot_wPfS_S_jjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z22__device_stub__x_dot_wPfS_S_jjj, .Lfunc_end0-_Z22__device_stub__x_dot_wPfS_S_jjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7x_dot_wPfS_S_jjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7x_dot_wPfS_S_jjj,@object # @_Z7x_dot_wPfS_S_jjj
.section .rodata,"a",@progbits
.globl _Z7x_dot_wPfS_S_jjj
.p2align 3, 0x0
_Z7x_dot_wPfS_S_jjj:
.quad _Z22__device_stub__x_dot_wPfS_S_jjj
.size _Z7x_dot_wPfS_S_jjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7x_dot_wPfS_S_jjj"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__x_dot_wPfS_S_jjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7x_dot_wPfS_S_jjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void sumTriangle(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0.0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle2(float *M, float *V, int N)
{
int j = threadIdx.x;
float sum = 0.0;
int i;
for (i = 0; i <= j; ++i)
{
if (i % 2 == 0)
{
sum += M[i * N + j];
}
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle3(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
int s;
for (s = 1; s < N; s *= 2)
{
if (j % (2 * s) == 0 && j + s < N)
{
V[j] += V[j + s];
}
__syncthreads();
}
V[N] = V[0];
}
int main()
{
int N = 11;
int size_M = N * N;
int size_V = N + 1;
float *M, *V;
M = (float *) malloc(sizeof(float) * size_M);
V = (float *) malloc(sizeof(float) * size_V);
int i, j;
srand(time(0));
V[0] = 0;
for (i = 0; i < N; ++i)
{
V[i + 1] = 0;
for (j = 0; j < N; ++j)
{
M[i * N + j] = rand() % 10000;
}
}
cudaError_t err = cudaSuccess;
float *d_M = NULL, *d_V = NULL;
err = cudaMalloc((void **) &d_M, size_M * sizeof(float));
if (err != cudaSuccess)
{
fprintf(stderr, "Error allocating device vector d_M (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_V, size_V * sizeof(float));
if (err != cudaSuccess)
{
fprintf(stderr, "Error allocating device vector d_V (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_M, M, size_M * sizeof(float), cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Error copying vector M from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_V, V, size_V * sizeof(float), cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Error copying vector V from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
dim3 grid(1, 1, 1);
dim3 block(N, 1, 1);
printf("Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n", grid.x, grid.y, grid.z, block.x, block.y, block.z);
sumTriangle3<<<grid, block>>>(d_M, d_V, N);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Error launching kernel sumTriangle (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(V, d_V, sizeof(float) * size_V, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Error copying vector V from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum_all = 0;
float sum;
for (j = 0; j < N; ++j)
{
sum = 0;
for (i = 0; i <= j; i += 1)
{
sum += M[i * N + j];
}
// if (fabs(sum - V[j]) > 1e-5)
// {
// fprintf(stderr, "Error in kernel's computation - kernel gives incorrect results for triangle sum.\n");
// exit(EXIT_FAILURE);
// }
sum_all += sum;
}
if (fabs(sum_all - V[N]) > 1e-5)
{
fprintf(stderr, "Error in kernel's computation - kernel gives incorrect result for overall sum.\n");
exit(EXIT_FAILURE);
}
printf("TEST PASSED.\n");
return 0;
} | .file "tmpxft_0019af68_00000000-6_3_synchronization.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11sumTrianglePfS_iPfS_i
.type _Z34__device_stub__Z11sumTrianglePfS_iPfS_i, @function
_Z34__device_stub__Z11sumTrianglePfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sumTrianglePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z11sumTrianglePfS_iPfS_i, .-_Z34__device_stub__Z11sumTrianglePfS_iPfS_i
.globl _Z11sumTrianglePfS_i
.type _Z11sumTrianglePfS_i, @function
_Z11sumTrianglePfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11sumTrianglePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11sumTrianglePfS_i, .-_Z11sumTrianglePfS_i
.globl _Z35__device_stub__Z12sumTriangle2PfS_iPfS_i
.type _Z35__device_stub__Z12sumTriangle2PfS_iPfS_i, @function
_Z35__device_stub__Z12sumTriangle2PfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sumTriangle2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z12sumTriangle2PfS_iPfS_i, .-_Z35__device_stub__Z12sumTriangle2PfS_iPfS_i
.globl _Z12sumTriangle2PfS_i
.type _Z12sumTriangle2PfS_i, @function
_Z12sumTriangle2PfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12sumTriangle2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12sumTriangle2PfS_i, .-_Z12sumTriangle2PfS_i
.globl _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i
.type _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i, @function
_Z35__device_stub__Z12sumTriangle3PfS_iPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sumTriangle3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i, .-_Z35__device_stub__Z12sumTriangle3PfS_iPfS_i
.globl _Z12sumTriangle3PfS_i
.type _Z12sumTriangle3PfS_i, @function
_Z12sumTriangle3PfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12sumTriangle3PfS_i, .-_Z12sumTriangle3PfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error allocating device vector d_M (error code %s)!\n"
.align 8
.LC2:
.string "Error allocating device vector d_V (error code %s)!\n"
.align 8
.LC3:
.string "Error copying vector M from host to device (error code %s)!\n"
.align 8
.LC4:
.string "Error copying vector V from host to device (error code %s)!\n"
.align 8
.LC5:
.string "Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n"
.align 8
.LC6:
.string "Error launching kernel sumTriangle (error code %s)!\n"
.align 8
.LC7:
.string "Error copying vector V from device to host (error code %s)!\n"
.align 8
.LC10:
.string "Error in kernel's computation - kernel gives incorrect result for overall sum.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC11:
.string "TEST PASSED.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $484, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
movl $48, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0x00000000, (%rbx)
leaq 4(%rbx), %r15
movq %r14, %r13
leaq 44(%r14), %r12
movq %r12, %rbp
movl $0, %r14d
.L29:
movl $0x00000000, (%r15)
leaq -44(%rbp), %rbx
.L28:
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
addq $4, %r15
addl $11, %r14d
addq $44, %rbp
cmpl $121, %r14d
jne .L29
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 16(%rsp), %rdi
movl $484, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L55
leaq 24(%rsp), %rdi
movl $48, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L56
movl $1, %ecx
movl $484, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L57
movl $1, %ecx
movl $48, %edx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L58
pushq $1
.cfi_def_cfa_offset 136
pushq $1
.cfi_def_cfa_offset 144
movl $11, %r9d
movl $1, %r8d
movl $1, %ecx
movl $1, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $11, 60(%rsp)
movl $1, 64(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 128
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L34:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L60
movl $2, %ecx
movl $48, %edx
movq 24(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
pxor %xmm1, %xmm1
movl $0, %edx
movaps %xmm1, %xmm2
jmp .L36
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl $11, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i
jmp .L34
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
addss %xmm2, %xmm1
addl $1, %edx
addq $4, %r13
addq $48, %r12
.L36:
movq %r13, %rax
pxor %xmm0, %xmm0
testl %edx, %edx
js .L62
.L37:
addss (%rax), %xmm0
addq $44, %rax
cmpq %r12, %rax
jne .L37
addss %xmm0, %xmm1
addl $1, %edx
addq $4, %r13
addq $48, %r12
cmpl $11, %edx
jne .L36
movq (%rsp), %rax
subss 44(%rax), %xmm1
andps .LC8(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
comisd .LC9(%rip), %xmm1
ja .L63
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12sumTriangle3PfS_i"
.LC13:
.string "_Z12sumTriangle2PfS_i"
.LC14:
.string "_Z11sumTrianglePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sumTriangle3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sumTriangle2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sumTrianglePfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void sumTriangle(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0.0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle2(float *M, float *V, int N)
{
int j = threadIdx.x;
float sum = 0.0;
int i;
for (i = 0; i <= j; ++i)
{
if (i % 2 == 0)
{
sum += M[i * N + j];
}
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle3(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
int s;
for (s = 1; s < N; s *= 2)
{
if (j % (2 * s) == 0 && j + s < N)
{
V[j] += V[j + s];
}
__syncthreads();
}
V[N] = V[0];
}
int main()
{
int N = 11;
int size_M = N * N;
int size_V = N + 1;
float *M, *V;
M = (float *) malloc(sizeof(float) * size_M);
V = (float *) malloc(sizeof(float) * size_V);
int i, j;
srand(time(0));
V[0] = 0;
for (i = 0; i < N; ++i)
{
V[i + 1] = 0;
for (j = 0; j < N; ++j)
{
M[i * N + j] = rand() % 10000;
}
}
cudaError_t err = cudaSuccess;
float *d_M = NULL, *d_V = NULL;
err = cudaMalloc((void **) &d_M, size_M * sizeof(float));
if (err != cudaSuccess)
{
fprintf(stderr, "Error allocating device vector d_M (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_V, size_V * sizeof(float));
if (err != cudaSuccess)
{
fprintf(stderr, "Error allocating device vector d_V (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_M, M, size_M * sizeof(float), cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Error copying vector M from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_V, V, size_V * sizeof(float), cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Error copying vector V from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
dim3 grid(1, 1, 1);
dim3 block(N, 1, 1);
printf("Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n", grid.x, grid.y, grid.z, block.x, block.y, block.z);
sumTriangle3<<<grid, block>>>(d_M, d_V, N);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Error launching kernel sumTriangle (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(V, d_V, sizeof(float) * size_V, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Error copying vector V from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum_all = 0;
float sum;
for (j = 0; j < N; ++j)
{
sum = 0;
for (i = 0; i <= j; i += 1)
{
sum += M[i * N + j];
}
// if (fabs(sum - V[j]) > 1e-5)
// {
// fprintf(stderr, "Error in kernel's computation - kernel gives incorrect results for triangle sum.\n");
// exit(EXIT_FAILURE);
// }
sum_all += sum;
}
if (fabs(sum_all - V[N]) > 1e-5)
{
fprintf(stderr, "Error in kernel's computation - kernel gives incorrect result for overall sum.\n");
exit(EXIT_FAILURE);
}
printf("TEST PASSED.\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void sumTriangle(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0.0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle2(float *M, float *V, int N)
{
int j = threadIdx.x;
float sum = 0.0;
int i;
for (i = 0; i <= j; ++i)
{
if (i % 2 == 0)
{
sum += M[i * N + j];
}
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle3(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
int s;
for (s = 1; s < N; s *= 2)
{
if (j % (2 * s) == 0 && j + s < N)
{
V[j] += V[j + s];
}
__syncthreads();
}
V[N] = V[0];
}
int main()
{
int N = 11;
int size_M = N * N;
int size_V = N + 1;
float *M, *V;
M = (float *) malloc(sizeof(float) * size_M);
V = (float *) malloc(sizeof(float) * size_V);
int i, j;
srand(time(0));
V[0] = 0;
for (i = 0; i < N; ++i)
{
V[i + 1] = 0;
for (j = 0; j < N; ++j)
{
M[i * N + j] = rand() % 10000;
}
}
hipError_t err = hipSuccess;
float *d_M = NULL, *d_V = NULL;
err = hipMalloc((void **) &d_M, size_M * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Error allocating device vector d_M (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_V, size_V * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Error allocating device vector d_V (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_M, M, size_M * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector M from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_V, V, size_V * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector V from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
dim3 grid(1, 1, 1);
dim3 block(N, 1, 1);
printf("Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n", grid.x, grid.y, grid.z, block.x, block.y, block.z);
sumTriangle3<<<grid, block>>>(d_M, d_V, N);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Error launching kernel sumTriangle (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(V, d_V, sizeof(float) * size_V, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector V from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum_all = 0;
float sum;
for (j = 0; j < N; ++j)
{
sum = 0;
for (i = 0; i <= j; i += 1)
{
sum += M[i * N + j];
}
// if (fabs(sum - V[j]) > 1e-5)
// {
// fprintf(stderr, "Error in kernel's computation - kernel gives incorrect results for triangle sum.\n");
// exit(EXIT_FAILURE);
// }
sum_all += sum;
}
if (fabs(sum_all - V[N]) > 1e-5)
{
fprintf(stderr, "Error in kernel's computation - kernel gives incorrect result for overall sum.\n");
exit(EXIT_FAILURE);
}
printf("TEST PASSED.\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void sumTriangle(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0.0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle2(float *M, float *V, int N)
{
int j = threadIdx.x;
float sum = 0.0;
int i;
for (i = 0; i <= j; ++i)
{
if (i % 2 == 0)
{
sum += M[i * N + j];
}
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle3(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
int s;
for (s = 1; s < N; s *= 2)
{
if (j % (2 * s) == 0 && j + s < N)
{
V[j] += V[j + s];
}
__syncthreads();
}
V[N] = V[0];
}
int main()
{
int N = 11;
int size_M = N * N;
int size_V = N + 1;
float *M, *V;
M = (float *) malloc(sizeof(float) * size_M);
V = (float *) malloc(sizeof(float) * size_V);
int i, j;
srand(time(0));
V[0] = 0;
for (i = 0; i < N; ++i)
{
V[i + 1] = 0;
for (j = 0; j < N; ++j)
{
M[i * N + j] = rand() % 10000;
}
}
hipError_t err = hipSuccess;
float *d_M = NULL, *d_V = NULL;
err = hipMalloc((void **) &d_M, size_M * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Error allocating device vector d_M (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_V, size_V * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Error allocating device vector d_V (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_M, M, size_M * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector M from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_V, V, size_V * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector V from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
dim3 grid(1, 1, 1);
dim3 block(N, 1, 1);
printf("Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n", grid.x, grid.y, grid.z, block.x, block.y, block.z);
sumTriangle3<<<grid, block>>>(d_M, d_V, N);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Error launching kernel sumTriangle (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(V, d_V, sizeof(float) * size_V, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector V from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum_all = 0;
float sum;
for (j = 0; j < N; ++j)
{
sum = 0;
for (i = 0; i <= j; i += 1)
{
sum += M[i * N + j];
}
// if (fabs(sum - V[j]) > 1e-5)
// {
// fprintf(stderr, "Error in kernel's computation - kernel gives incorrect results for triangle sum.\n");
// exit(EXIT_FAILURE);
// }
sum_all += sum;
}
if (fabs(sum_all - V[N]) > 1e-5)
{
fprintf(stderr, "Error in kernel's computation - kernel gives incorrect result for overall sum.\n");
exit(EXIT_FAILURE);
}
printf("TEST PASSED.\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11sumTrianglePfS_i
.globl _Z11sumTrianglePfS_i
.p2align 8
.type _Z11sumTrianglePfS_i,@function
_Z11sumTrianglePfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_mov_b32_e32 v3, 0
s_mov_b32 s9, -1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
v_add_co_u32 v1, s2, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s2
s_mov_b32 s8, s4
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s3, 0
.LBB0_1:
global_load_b32 v4, v[1:2], off
s_add_i32 s9, s9, 1
v_add_co_u32 v1, vcc_lo, v1, s6
v_cmp_eq_u32_e64 s2, s9, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s2, s4, -1
v_lshlrev_b32_e32 v1, 2, v0
v_cmp_eq_u32_e32 vcc_lo, s2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v3, s[0:1]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_8
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_6
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0
s_mov_b64 s[2:3], s[0:1]
.LBB0_5:
global_load_b32 v2, v1, s[2:3]
s_add_i32 s8, s8, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s8, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v2
s_cbranch_scc1 .LBB0_5
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v0, 0
.LBB0_7:
s_lshl_b64 s[2:3], s[4:5], 2
v_mov_b32_e32 v1, 0
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11sumTrianglePfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11sumTrianglePfS_i, .Lfunc_end0-_Z11sumTrianglePfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12sumTriangle2PfS_i
.globl _Z12sumTriangle2PfS_i
.p2align 8
.type _Z12sumTriangle2PfS_i,@function
_Z12sumTriangle2PfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x10
s_load_b64 s[4:5], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, 1, v0
s_mov_b32 s6, 0
s_mov_b32 s7, 0
s_mov_b32 s8, 0
s_waitcnt lgkmcnt(0)
s_mov_b32 s3, s2
s_branch .LBB1_2
.p2align 6
.LBB1_1:
s_add_i32 s8, s8, 1
s_add_i32 s7, s7, s2
v_cmp_eq_u32_e32 vcc_lo, s8, v2
s_or_b32 s6, vcc_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB1_4
.LBB1_2:
s_bitcmp1_b32 s8, 0
s_cselect_b32 s9, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB1_1
v_add_nc_u32_e32 v3, s7, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v3
s_branch .LBB1_1
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x8
s_add_i32 s4, s2, -1
v_lshlrev_b32_e32 v2, 2, v0
v_cmp_eq_u32_e32 vcc_lo, s4, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v2, v1, s[0:1]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB1_10
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB1_8
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, 0
s_mov_b64 s[4:5], s[0:1]
.LBB1_7:
global_load_b32 v2, v1, s[4:5]
s_add_i32 s3, s3, -1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_lg_u32 s3, 0
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v0, v2
s_cbranch_scc1 .LBB1_7
s_branch .LBB1_9
.LBB1_8:
v_mov_b32_e32 v0, 0
.LBB1_9:
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v1, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sumTriangle2PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z12sumTriangle2PfS_i, .Lfunc_end1-_Z12sumTriangle2PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z12sumTriangle3PfS_i
.globl _Z12sumTriangle3PfS_i
.p2align 8
.type _Z12sumTriangle3PfS_i,@function
_Z12sumTriangle3PfS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v1, 2, v0
v_mov_b32_e32 v3, 0
s_mov_b32 s8, -1
s_waitcnt lgkmcnt(0)
s_ashr_i32 s5, s4, 31
v_add_co_u32 v1, s2, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s2
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s3, 0
.LBB2_1:
global_load_b32 v4, v[1:2], off
s_add_i32 s8, s8, 1
v_add_co_u32 v1, vcc_lo, v1, s6
v_cmp_eq_u32_e64 s2, s8, v0
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_2)
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB2_1
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[2:3], s[0:1], 0x8
v_lshlrev_b32_e32 v1, 2, v0
v_mov_b32_e32 v5, 0
s_cmp_lt_i32 s4, 2
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v3, s[2:3]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
v_add_co_u32 v1, s0, s2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v2, null, s3, 0, s0
s_mov_b32 s1, 1
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_5
.p2align 6
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s0
s_cmp_lt_i32 s1, s4
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB2_7
.LBB2_5:
s_mov_b32 s0, s1
s_lshl_b32 s1, s1, 1
v_add_nc_u32_e32 v3, s0, v0
s_add_i32 s6, s1, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v4, s6, v0
v_cmp_gt_i32_e64 s0, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_u32_e32 vcc_lo, 0, v4
s_and_b32 s6, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s6
s_cbranch_execz .LBB2_4
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
global_store_b32 v[1:2], v3, off
s_branch .LBB2_4
.LBB2_7:
s_set_inst_prefetch_distance 0x2
global_load_b32 v0, v5, s[2:3]
s_lshl_b64 s[0:1], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s2, s0
s_addc_u32 s1, s3, s1
s_waitcnt vmcnt(0)
global_store_b32 v5, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sumTriangle3PfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 9
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z12sumTriangle3PfS_i, .Lfunc_end2-_Z12sumTriangle3PfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11sumTrianglePfS_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z11sumTrianglePfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sumTriangle2PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z12sumTriangle2PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sumTriangle3PfS_i
.private_segment_fixed_size: 0
.sgpr_count: 11
.sgpr_spill_count: 0
.symbol: _Z12sumTriangle3PfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void sumTriangle(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0.0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle2(float *M, float *V, int N)
{
int j = threadIdx.x;
float sum = 0.0;
int i;
for (i = 0; i <= j; ++i)
{
if (i % 2 == 0)
{
sum += M[i * N + j];
}
}
V[j] = sum;
__syncthreads();
if (j == N - 1)
{
sum = 0;
for (i = 0; i < N; ++i)
{
sum += V[i];
}
V[N] = sum;
}
}
__global__
void sumTriangle3(float *M, float *V, int N)
{
int j = threadIdx.x;
int i;
float sum = 0;
for (i = 0; i <= j; ++i)
{
sum += M[i * N + j];
}
V[j] = sum;
__syncthreads();
int s;
for (s = 1; s < N; s *= 2)
{
if (j % (2 * s) == 0 && j + s < N)
{
V[j] += V[j + s];
}
__syncthreads();
}
V[N] = V[0];
}
int main()
{
int N = 11;
int size_M = N * N;
int size_V = N + 1;
float *M, *V;
M = (float *) malloc(sizeof(float) * size_M);
V = (float *) malloc(sizeof(float) * size_V);
int i, j;
srand(time(0));
V[0] = 0;
for (i = 0; i < N; ++i)
{
V[i + 1] = 0;
for (j = 0; j < N; ++j)
{
M[i * N + j] = rand() % 10000;
}
}
hipError_t err = hipSuccess;
float *d_M = NULL, *d_V = NULL;
err = hipMalloc((void **) &d_M, size_M * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Error allocating device vector d_M (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_V, size_V * sizeof(float));
if (err != hipSuccess)
{
fprintf(stderr, "Error allocating device vector d_V (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_M, M, size_M * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector M from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_V, V, size_V * sizeof(float), hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector V from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
dim3 grid(1, 1, 1);
dim3 block(N, 1, 1);
printf("Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n", grid.x, grid.y, grid.z, block.x, block.y, block.z);
sumTriangle3<<<grid, block>>>(d_M, d_V, N);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Error launching kernel sumTriangle (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(V, d_V, sizeof(float) * size_V, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Error copying vector V from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
float sum_all = 0;
float sum;
for (j = 0; j < N; ++j)
{
sum = 0;
for (i = 0; i <= j; i += 1)
{
sum += M[i * N + j];
}
// if (fabs(sum - V[j]) > 1e-5)
// {
// fprintf(stderr, "Error in kernel's computation - kernel gives incorrect results for triangle sum.\n");
// exit(EXIT_FAILURE);
// }
sum_all += sum;
}
if (fabs(sum_all - V[N]) > 1e-5)
{
fprintf(stderr, "Error in kernel's computation - kernel gives incorrect result for overall sum.\n");
exit(EXIT_FAILURE);
}
printf("TEST PASSED.\n");
return 0;
} | .text
.file "3_synchronization.hip"
.globl _Z26__device_stub__sumTrianglePfS_i # -- Begin function _Z26__device_stub__sumTrianglePfS_i
.p2align 4, 0x90
.type _Z26__device_stub__sumTrianglePfS_i,@function
_Z26__device_stub__sumTrianglePfS_i: # @_Z26__device_stub__sumTrianglePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11sumTrianglePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__sumTrianglePfS_i, .Lfunc_end0-_Z26__device_stub__sumTrianglePfS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__sumTriangle2PfS_i # -- Begin function _Z27__device_stub__sumTriangle2PfS_i
.p2align 4, 0x90
.type _Z27__device_stub__sumTriangle2PfS_i,@function
_Z27__device_stub__sumTriangle2PfS_i: # @_Z27__device_stub__sumTriangle2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sumTriangle2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__sumTriangle2PfS_i, .Lfunc_end1-_Z27__device_stub__sumTriangle2PfS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__sumTriangle3PfS_i # -- Begin function _Z27__device_stub__sumTriangle3PfS_i
.p2align 4, 0x90
.type _Z27__device_stub__sumTriangle3PfS_i,@function
_Z27__device_stub__sumTriangle3PfS_i: # @_Z27__device_stub__sumTriangle3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sumTriangle3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__sumTriangle3PfS_i, .Lfunc_end2-_Z27__device_stub__sumTriangle3PfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $484, %edi # imm = 0x1E4
callq malloc
movq %rax, %rbx
movl $48, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $0, (%r14)
movq %rbx, %r12
.p2align 4, 0x90
.LBB3_2: # =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl $0, 4(%r14,%r15,4)
incq %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $11, %r13
jne .LBB3_3
# %bb.1: # %.loopexit
# in Loop: Header=BB3_2 Depth=1
addq $44, %r12
cmpq $11, %r15
jne .LBB3_2
# %bb.4:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
leaq 16(%rsp), %rdi
movl $484, %esi # imm = 0x1E4
callq hipMalloc
testl %eax, %eax
jne .LBB3_5
# %bb.7:
leaq 8(%rsp), %rdi
movl $48, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9:
movq 16(%rsp), %rdi
movl $484, %edx # imm = 0x1E4
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_10
# %bb.11:
movq 8(%rsp), %rdi
movl $48, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_12
# %bb.13:
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.4, %edi
movl $1, %esi
movl $1, %edx
movl $1, %ecx
movl $11, %r8d
movl $1, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 10(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $11, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12sumTriangle3PfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_16
# %bb.17:
movq 8(%rsp), %rsi
movl $48, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_24
# %bb.18: # %.preheader.preheader
xorps %xmm0, %xmm0
movl $44, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_19: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_20 Depth 2
xorl %edx, %edx
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB3_20: # Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
addss (%rbx,%rdx), %xmm1
addq $44, %rdx
cmpq %rdx, %rax
jne .LBB3_20
# %bb.21: # in Loop: Header=BB3_19 Depth=1
addss %xmm1, %xmm0
incq %rcx
addq $4, %rbx
addq $44, %rax
cmpq $11, %rcx
jne .LBB3_19
# %bb.22:
subss 44(%r14), %xmm0
andps .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI3_1(%rip), %xmm0
ja .LBB3_25
# %bb.23:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB3_6
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB3_6
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB3_6
.LBB3_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB3_6
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB3_6
.LBB3_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
.LBB3_6:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_25:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $79, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sumTrianglePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sumTriangle2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sumTriangle3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sumTrianglePfS_i,@object # @_Z11sumTrianglePfS_i
.section .rodata,"a",@progbits
.globl _Z11sumTrianglePfS_i
.p2align 3, 0x0
_Z11sumTrianglePfS_i:
.quad _Z26__device_stub__sumTrianglePfS_i
.size _Z11sumTrianglePfS_i, 8
.type _Z12sumTriangle2PfS_i,@object # @_Z12sumTriangle2PfS_i
.globl _Z12sumTriangle2PfS_i
.p2align 3, 0x0
_Z12sumTriangle2PfS_i:
.quad _Z27__device_stub__sumTriangle2PfS_i
.size _Z12sumTriangle2PfS_i, 8
.type _Z12sumTriangle3PfS_i,@object # @_Z12sumTriangle3PfS_i
.globl _Z12sumTriangle3PfS_i
.p2align 3, 0x0
_Z12sumTriangle3PfS_i:
.quad _Z27__device_stub__sumTriangle3PfS_i
.size _Z12sumTriangle3PfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating device vector d_M (error code %s)!\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error allocating device vector d_V (error code %s)!\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error copying vector M from host to device (error code %s)!\n"
.size .L.str.2, 61
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error copying vector V from host to device (error code %s)!\n"
.size .L.str.3, 61
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n"
.size .L.str.4, 87
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error launching kernel sumTriangle (error code %s)!\n"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error copying vector V from device to host (error code %s)!\n"
.size .L.str.6, 61
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error in kernel's computation - kernel gives incorrect result for overall sum.\n"
.size .L.str.7, 80
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11sumTrianglePfS_i"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12sumTriangle2PfS_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12sumTriangle3PfS_i"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST PASSED."
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sumTrianglePfS_i
.addrsig_sym _Z27__device_stub__sumTriangle2PfS_i
.addrsig_sym _Z27__device_stub__sumTriangle3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sumTrianglePfS_i
.addrsig_sym _Z12sumTriangle2PfS_i
.addrsig_sym _Z12sumTriangle3PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019af68_00000000-6_3_synchronization.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z11sumTrianglePfS_iPfS_i
.type _Z34__device_stub__Z11sumTrianglePfS_iPfS_i, @function
_Z34__device_stub__Z11sumTrianglePfS_iPfS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sumTrianglePfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z11sumTrianglePfS_iPfS_i, .-_Z34__device_stub__Z11sumTrianglePfS_iPfS_i
.globl _Z11sumTrianglePfS_i
.type _Z11sumTrianglePfS_i, @function
_Z11sumTrianglePfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11sumTrianglePfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11sumTrianglePfS_i, .-_Z11sumTrianglePfS_i
.globl _Z35__device_stub__Z12sumTriangle2PfS_iPfS_i
.type _Z35__device_stub__Z12sumTriangle2PfS_iPfS_i, @function
_Z35__device_stub__Z12sumTriangle2PfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sumTriangle2PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z35__device_stub__Z12sumTriangle2PfS_iPfS_i, .-_Z35__device_stub__Z12sumTriangle2PfS_iPfS_i
.globl _Z12sumTriangle2PfS_i
.type _Z12sumTriangle2PfS_i, @function
_Z12sumTriangle2PfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12sumTriangle2PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12sumTriangle2PfS_i, .-_Z12sumTriangle2PfS_i
.globl _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i
.type _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i, @function
_Z35__device_stub__Z12sumTriangle3PfS_iPfS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sumTriangle3PfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i, .-_Z35__device_stub__Z12sumTriangle3PfS_iPfS_i
.globl _Z12sumTriangle3PfS_i
.type _Z12sumTriangle3PfS_i, @function
_Z12sumTriangle3PfS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z12sumTriangle3PfS_i, .-_Z12sumTriangle3PfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Error allocating device vector d_M (error code %s)!\n"
.align 8
.LC2:
.string "Error allocating device vector d_V (error code %s)!\n"
.align 8
.LC3:
.string "Error copying vector M from host to device (error code %s)!\n"
.align 8
.LC4:
.string "Error copying vector V from host to device (error code %s)!\n"
.align 8
.LC5:
.string "Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n"
.align 8
.LC6:
.string "Error launching kernel sumTriangle (error code %s)!\n"
.align 8
.LC7:
.string "Error copying vector V from device to host (error code %s)!\n"
.align 8
.LC10:
.string "Error in kernel's computation - kernel gives incorrect result for overall sum.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC11:
.string "TEST PASSED.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $484, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, 8(%rsp)
movl $48, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $0x00000000, (%rbx)
leaq 4(%rbx), %r15
movq %r14, %r13
leaq 44(%r14), %r12
movq %r12, %rbp
movl $0, %r14d
.L29:
movl $0x00000000, (%r15)
leaq -44(%rbp), %rbx
.L28:
call rand@PLT
movslq %eax, %rdx
imulq $1759218605, %rdx, %rdx
sarq $44, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $10000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L28
addq $4, %r15
addl $11, %r14d
addq $44, %rbp
cmpl $121, %r14d
jne .L29
movq $0, 16(%rsp)
movq $0, 24(%rsp)
leaq 16(%rsp), %rdi
movl $484, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L55
leaq 24(%rsp), %rdi
movl $48, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L56
movl $1, %ecx
movl $484, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L57
movl $1, %ecx
movl $48, %edx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L58
pushq $1
.cfi_def_cfa_offset 136
pushq $1
.cfi_def_cfa_offset 144
movl $11, %r9d
movl $1, %r8d
movl $1, %ecx
movl $1, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $11, 60(%rsp)
movl $1, 64(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 128
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L34:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L60
movl $2, %ecx
movl $48, %edx
movq 24(%rsp), %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L61
pxor %xmm1, %xmm1
movl $0, %edx
movaps %xmm1, %xmm2
jmp .L36
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl $11, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z12sumTriangle3PfS_iPfS_i
jmp .L34
.L60:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
addss %xmm2, %xmm1
addl $1, %edx
addq $4, %r13
addq $48, %r12
.L36:
movq %r13, %rax
pxor %xmm0, %xmm0
testl %edx, %edx
js .L62
.L37:
addss (%rax), %xmm0
addq $44, %rax
cmpq %r12, %rax
jne .L37
addss %xmm0, %xmm1
addl $1, %edx
addq $4, %r13
addq $48, %r12
cmpl $11, %edx
jne .L36
movq (%rsp), %rax
subss 44(%rax), %xmm1
andps .LC8(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
comisd .LC9(%rip), %xmm1
ja .L63
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12sumTriangle3PfS_i"
.LC13:
.string "_Z12sumTriangle2PfS_i"
.LC14:
.string "_Z11sumTrianglePfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sumTriangle3PfS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sumTriangle2PfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sumTrianglePfS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC8:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC9:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "3_synchronization.hip"
.globl _Z26__device_stub__sumTrianglePfS_i # -- Begin function _Z26__device_stub__sumTrianglePfS_i
.p2align 4, 0x90
.type _Z26__device_stub__sumTrianglePfS_i,@function
_Z26__device_stub__sumTrianglePfS_i: # @_Z26__device_stub__sumTrianglePfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11sumTrianglePfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z26__device_stub__sumTrianglePfS_i, .Lfunc_end0-_Z26__device_stub__sumTrianglePfS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__sumTriangle2PfS_i # -- Begin function _Z27__device_stub__sumTriangle2PfS_i
.p2align 4, 0x90
.type _Z27__device_stub__sumTriangle2PfS_i,@function
_Z27__device_stub__sumTriangle2PfS_i: # @_Z27__device_stub__sumTriangle2PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sumTriangle2PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__sumTriangle2PfS_i, .Lfunc_end1-_Z27__device_stub__sumTriangle2PfS_i
.cfi_endproc
# -- End function
.globl _Z27__device_stub__sumTriangle3PfS_i # -- Begin function _Z27__device_stub__sumTriangle3PfS_i
.p2align 4, 0x90
.type _Z27__device_stub__sumTriangle3PfS_i,@function
_Z27__device_stub__sumTriangle3PfS_i: # @_Z27__device_stub__sumTriangle3PfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sumTriangle3PfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__sumTriangle3PfS_i, .Lfunc_end2-_Z27__device_stub__sumTriangle3PfS_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI3_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI3_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $484, %edi # imm = 0x1E4
callq malloc
movq %rax, %rbx
movl $48, %edi
callq malloc
movq %rax, %r14
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $0, (%r14)
movq %rbx, %r12
.p2align 4, 0x90
.LBB3_2: # =>This Loop Header: Depth=1
# Child Loop BB3_3 Depth 2
movl $0, 4(%r14,%r15,4)
incq %r15
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_3: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1759218605, %rax, %rcx # imm = 0x68DB8BAD
movq %rcx, %rdx
shrq $63, %rdx
sarq $44, %rcx
addl %edx, %ecx
imull $10000, %ecx, %ecx # imm = 0x2710
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%r13,4)
incq %r13
cmpq $11, %r13
jne .LBB3_3
# %bb.1: # %.loopexit
# in Loop: Header=BB3_2 Depth=1
addq $44, %r12
cmpq $11, %r15
jne .LBB3_2
# %bb.4:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
leaq 16(%rsp), %rdi
movl $484, %esi # imm = 0x1E4
callq hipMalloc
testl %eax, %eax
jne .LBB3_5
# %bb.7:
leaq 8(%rsp), %rdi
movl $48, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB3_8
# %bb.9:
movq 16(%rsp), %rdi
movl $484, %edx # imm = 0x1E4
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_10
# %bb.11:
movq 8(%rsp), %rdi
movl $48, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_12
# %bb.13:
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.4, %edi
movl $1, %esi
movl $1, %edx
movl $1, %ecx
movl $11, %r8d
movl $1, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 10(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_15
# %bb.14:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $11, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12sumTriangle3PfS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_15:
callq hipGetLastError
testl %eax, %eax
jne .LBB3_16
# %bb.17:
movq 8(%rsp), %rsi
movl $48, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB3_24
# %bb.18: # %.preheader.preheader
xorps %xmm0, %xmm0
movl $44, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB3_19: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_20 Depth 2
xorl %edx, %edx
xorps %xmm1, %xmm1
.p2align 4, 0x90
.LBB3_20: # Parent Loop BB3_19 Depth=1
# => This Inner Loop Header: Depth=2
addss (%rbx,%rdx), %xmm1
addq $44, %rdx
cmpq %rdx, %rax
jne .LBB3_20
# %bb.21: # in Loop: Header=BB3_19 Depth=1
addss %xmm1, %xmm0
incq %rcx
addq $4, %rbx
addq $44, %rax
cmpq $11, %rcx
jne .LBB3_19
# %bb.22:
subss 44(%r14), %xmm0
andps .LCPI3_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
ucomisd .LCPI3_1(%rip), %xmm0
ja .LBB3_25
# %bb.23:
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB3_5:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
jmp .LBB3_6
.LBB3_8:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %esi
jmp .LBB3_6
.LBB3_10:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB3_6
.LBB3_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB3_6
.LBB3_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB3_6
.LBB3_24:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
.LBB3_6:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB3_25:
movq stderr(%rip), %rcx
movl $.L.str.7, %edi
movl $79, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11sumTrianglePfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sumTriangle2PfS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sumTriangle3PfS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11sumTrianglePfS_i,@object # @_Z11sumTrianglePfS_i
.section .rodata,"a",@progbits
.globl _Z11sumTrianglePfS_i
.p2align 3, 0x0
_Z11sumTrianglePfS_i:
.quad _Z26__device_stub__sumTrianglePfS_i
.size _Z11sumTrianglePfS_i, 8
.type _Z12sumTriangle2PfS_i,@object # @_Z12sumTriangle2PfS_i
.globl _Z12sumTriangle2PfS_i
.p2align 3, 0x0
_Z12sumTriangle2PfS_i:
.quad _Z27__device_stub__sumTriangle2PfS_i
.size _Z12sumTriangle2PfS_i, 8
.type _Z12sumTriangle3PfS_i,@object # @_Z12sumTriangle3PfS_i
.globl _Z12sumTriangle3PfS_i
.p2align 3, 0x0
_Z12sumTriangle3PfS_i:
.quad _Z27__device_stub__sumTriangle3PfS_i
.size _Z12sumTriangle3PfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error allocating device vector d_M (error code %s)!\n"
.size .L.str, 53
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Error allocating device vector d_V (error code %s)!\n"
.size .L.str.1, 53
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Error copying vector M from host to device (error code %s)!\n"
.size .L.str.2, 61
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error copying vector V from host to device (error code %s)!\n"
.size .L.str.3, 61
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Lauching cuda kernel sumTriangle with blocks: (%d, %d, %d) and threads: (%d, %d, %d).\n"
.size .L.str.4, 87
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Error launching kernel sumTriangle (error code %s)!\n"
.size .L.str.5, 53
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error copying vector V from device to host (error code %s)!\n"
.size .L.str.6, 61
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Error in kernel's computation - kernel gives incorrect result for overall sum.\n"
.size .L.str.7, 80
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11sumTrianglePfS_i"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z12sumTriangle2PfS_i"
.size .L__unnamed_2, 22
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z12sumTriangle3PfS_i"
.size .L__unnamed_3, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST PASSED."
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__sumTrianglePfS_i
.addrsig_sym _Z27__device_stub__sumTriangle2PfS_i
.addrsig_sym _Z27__device_stub__sumTriangle3PfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11sumTrianglePfS_i
.addrsig_sym _Z12sumTriangle2PfS_i
.addrsig_sym _Z12sumTriangle3PfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Copyright (c) 2019 Opticks Team. All Rights Reserved.
*
* This file is part of Opticks
* (see https://bitbucket.org/simoncblyth/opticks).
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <thrust/for_each.h>
#include <thrust/device_vector.h>
template<typename T>
struct ShortCompressor
{
int _imax ;
T _center ;
T _extent ;
T _max ;
T _step ;
T _eps ;
T _half ;
ShortCompressor( T center, T extent )
:
_imax(32767),
_center(center),
_extent(extent),
_max(_imax),
_step(_extent/_max),
_eps(0.001),
_half(0.5)
{
}
__host__ __device__
T value(int iv)
{
return _center + _step*(T(iv)+_half) ;
}
__host__ __device__
T fvalue(T v)
{
return _max*(v - _center)/_extent ;
}
__device__
int ivalue(double v)
{
T vv = _max*(v - _center)/_extent ;
return __double2int_rn(vv) ;
}
__device__
int ivalue(float v)
{
T vv = _max*(v - _center)/_extent ;
return __float2int_rn(vv) ;
}
__device__
void operator()(float4 v)
{
printf("%15.7f %15.7f %d %15.7f %d %15.7f %d %15.7f %d \n",
v.x, fvalue(v.x), ivalue(v.x),
v.y, ivalue(v.y),
v.z, ivalue(v.z),
v.w, ivalue(v.w)
);
}
__host__
void test(int d0)
{
thrust::device_vector<float4> fvec(10);
// TODO: fix this, better to prep on host then copy to dev in one go
for(int i=0 ; i < 10 ; i++)
{
T val = value(d0+i) ;
fvec[i] = make_float4( val, val, val, T(d0+i) );
}
thrust::for_each(fvec.begin(), fvec.end(), *this );
}
};
int main()
{
float center(0.);
float extent(451.);
ShortCompressor<float> comp(center,extent);
comp.test(3445);
cudaDeviceSynchronize();
} | /*
* Copyright (c) 2019 Opticks Team. All Rights Reserved.
*
* This file is part of Opticks
* (see https://bitbucket.org/simoncblyth/opticks).
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <hip/hip_runtime.h>
#include <thrust/for_each.h>
#include <thrust/device_vector.h>
template<typename T>
struct ShortCompressor
{
int _imax ;
T _center ;
T _extent ;
T _max ;
T _step ;
T _eps ;
T _half ;
ShortCompressor( T center, T extent )
:
_imax(32767),
_center(center),
_extent(extent),
_max(_imax),
_step(_extent/_max),
_eps(0.001),
_half(0.5)
{
}
__host__ __device__
T value(int iv)
{
return _center + _step*(T(iv)+_half) ;
}
__host__ __device__
T fvalue(T v)
{
return _max*(v - _center)/_extent ;
}
__device__
int ivalue(double v)
{
T vv = _max*(v - _center)/_extent ;
return __double2int_rn(vv) ;
}
__device__
int ivalue(float v)
{
T vv = _max*(v - _center)/_extent ;
return __float2int_rn(vv) ;
}
__device__
void operator()(float4 v)
{
printf("%15.7f %15.7f %d %15.7f %d %15.7f %d %15.7f %d \n",
v.x, fvalue(v.x), ivalue(v.x),
v.y, ivalue(v.y),
v.z, ivalue(v.z),
v.w, ivalue(v.w)
);
}
__host__
void test(int d0)
{
thrust::device_vector<float4> fvec(10);
// TODO: fix this, better to prep on host then copy to dev in one go
for(int i=0 ; i < 10 ; i++)
{
T val = value(d0+i) ;
fvec[i] = make_float4( val, val, val, T(d0+i) );
}
thrust::for_each(fvec.begin(), fvec.end(), *this );
}
};
int main()
{
float center(0.);
float extent(451.);
ShortCompressor<float> comp(center,extent);
comp.test(3445);
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cmath>
#include <functional>
#include <random>
#include <sys/time.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform_reduce.h>
#include <thrust/generate.h>
#define N 4
double wtime()
{
struct timeval t;
gettimeofday (&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
float initMatr2()
{
std::default_random_engine generator;
generator.seed(std::random_device()());
std::uniform_real_distribution<float> distrib(0, 100);
return distrib(generator);
}
void thrustCuda()
{
thrust::host_vector<float> mA(N);
thrust::host_vector<float> mB(N);
thrust::generate(mA.begin(), mA.end(), initMatr2);
thrust::generate(mB.begin(), mB.end(), initMatr2);
thrust::device_vector<float> mA_d(mA);
thrust::device_vector<float> mB_d(mB);
thrust::device_vector<float> mC_d(mB);
for (int i = 0; i < N; i++)
thrust::transform(mA_d.begin(), mA_d.end(), mB_d.begin(),
mC_d.begin(), thrust::plus<float>());
thrust::host_vector<float> mC(mC_d);
for (int i = 0; i < N; i++)
std::cout << mA[i] << " ";
std::cout << std::endl;
for (int i = 0; i < N; i++)
std::cout << mB[i] << " ";
std::cout << std::endl;
for (int i = 0; i < N; i++)
std::cout << mC[i] << " ";
std::cout << std::endl;
}
int main()
{
double time = -wtime();
thrustCuda();
time += wtime();
std::cout << time << std::endl;
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_SF_NS9_14no_stencil_tagENS7_4plusIfEENS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FADD R9, R6, R5 ; /* 0x0000000506097221 */
/* 0x005fca0000000000 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <functional>
#include <random>
#include <sys/time.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform_reduce.h>
#include <thrust/generate.h>
#define N 4
double wtime()
{
struct timeval t;
gettimeofday (&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
float initMatr2()
{
std::default_random_engine generator;
generator.seed(std::random_device()());
std::uniform_real_distribution<float> distrib(0, 100);
return distrib(generator);
}
void thrustCuda()
{
thrust::host_vector<float> mA(N);
thrust::host_vector<float> mB(N);
thrust::generate(mA.begin(), mA.end(), initMatr2);
thrust::generate(mB.begin(), mB.end(), initMatr2);
thrust::device_vector<float> mA_d(mA);
thrust::device_vector<float> mB_d(mB);
thrust::device_vector<float> mC_d(mB);
for (int i = 0; i < N; i++)
thrust::transform(mA_d.begin(), mA_d.end(), mB_d.begin(),
mC_d.begin(), thrust::plus<float>());
thrust::host_vector<float> mC(mC_d);
for (int i = 0; i < N; i++)
std::cout << mA[i] << " ";
std::cout << std::endl;
for (int i = 0; i < N; i++)
std::cout << mB[i] << " ";
std::cout << std::endl;
for (int i = 0; i < N; i++)
std::cout << mC[i] << " ";
std::cout << std::endl;
}
int main()
{
double time = -wtime();
thrustCuda();
time += wtime();
std::cout << time << std::endl;
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <functional>
#include <random>
#include <sys/time.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform_reduce.h>
#include <thrust/generate.h>
#define N 4
double wtime()
{
struct timeval t;
gettimeofday (&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
float initMatr2()
{
std::default_random_engine generator;
generator.seed(std::random_device()());
std::uniform_real_distribution<float> distrib(0, 100);
return distrib(generator);
}
void thrustCuda()
{
thrust::host_vector<float> mA(N);
thrust::host_vector<float> mB(N);
thrust::generate(mA.begin(), mA.end(), initMatr2);
thrust::generate(mB.begin(), mB.end(), initMatr2);
thrust::device_vector<float> mA_d(mA);
thrust::device_vector<float> mB_d(mB);
thrust::device_vector<float> mC_d(mB);
for (int i = 0; i < N; i++)
thrust::transform(mA_d.begin(), mA_d.end(), mB_d.begin(),
mC_d.begin(), thrust::plus<float>());
thrust::host_vector<float> mC(mC_d);
for (int i = 0; i < N; i++)
std::cout << mA[i] << " ";
std::cout << std::endl;
for (int i = 0; i < N; i++)
std::cout << mB[i] << " ";
std::cout << std::endl;
for (int i = 0; i < N; i++)
std::cout << mC[i] << " ";
std::cout << std::endl;
}
int main()
{
double time = -wtime();
thrustCuda();
time += wtime();
std::cout << time << std::endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <cmath>
#include <functional>
#include <random>
#include <sys/time.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/transform_reduce.h>
#include <thrust/generate.h>
#define N 4
double wtime()
{
struct timeval t;
gettimeofday (&t, NULL);
return (double)t.tv_sec + (double)t.tv_usec * 1E-6;
}
float initMatr2()
{
std::default_random_engine generator;
generator.seed(std::random_device()());
std::uniform_real_distribution<float> distrib(0, 100);
return distrib(generator);
}
void thrustCuda()
{
thrust::host_vector<float> mA(N);
thrust::host_vector<float> mB(N);
thrust::generate(mA.begin(), mA.end(), initMatr2);
thrust::generate(mB.begin(), mB.end(), initMatr2);
thrust::device_vector<float> mA_d(mA);
thrust::device_vector<float> mB_d(mB);
thrust::device_vector<float> mC_d(mB);
for (int i = 0; i < N; i++)
thrust::transform(mA_d.begin(), mA_d.end(), mB_d.begin(),
mC_d.begin(), thrust::plus<float>());
thrust::host_vector<float> mC(mC_d);
for (int i = 0; i < N; i++)
std::cout << mA[i] << " ";
std::cout << std::endl;
for (int i = 0; i < N; i++)
std::cout << mB[i] << " ";
std::cout << std::endl;
for (int i = 0; i < N; i++)
std::cout << mC[i] << " ";
std::cout << std::endl;
}
int main()
{
double time = -wtime();
thrustCuda();
time += wtime();
std::cout << time << std::endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub11__transform18binary_transform_fINS7_6detail15normal_iteratorINS7_10device_ptrIfEEEESF_SF_NS9_14no_stencil_tagENS7_4plusIfEENS9_21always_true_predicateEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x170], RZ ; /* 0x00005c0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x17c], RZ, P3, !PT ; /* 0x00005f0000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x270 ; /* 0x0000013000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x210 ; /* 0x000000b000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x200 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*01f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0001e4000c101904 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0220*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ea4000c1e1900 */
/*0240*/ FADD R9, R6, R5 ; /* 0x0000000506097221 */
/* 0x005fca0000000000 */
/*0250*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FADD R9, R0, R9 ; /* 0x0000000900097221 */
/* 0x004fca0000000000 */
/*02a0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*02b0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea8000c1e1900 */
/*02c0*/ LDG.E R11, [R4.64+0x400] ; /* 0x00040004040b7981 */
/* 0x000ea4000c1e1900 */
/*02d0*/ FADD R11, R0, R11 ; /* 0x0000000b000b7221 */
/* 0x004fca0000000000 */
/*02e0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_:
s_load_b128 s[4:7], s[0:1], 0x20
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
flat_load_b32 v2, v[2:3]
flat_load_b32 v3, v[4:5]
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 32
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_11__transform18binary_transform_fINS_6detail15normal_iteratorINS_10device_ptrIfEEEES9_S9_NS3_14no_stencil_tagENS_4plusIfEENS3_21always_true_predicateEEElLj1EEEvT0_T1_SG_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ inline static float euclid_distance(int numCoords, int numObjs, int numClusters, int tid, int clusterId, float *objects, float *clusters )
{
float ans=0.0;
for (int i = 0; i < numCoords; i++) {
ans += (objects[3*tid+i] - clusters[i + clusterId*3]) *
(objects[3*tid+i] - clusters[i + clusterId*3]);
}
return(ans);
}
__global__ static void find_nearest_cluster(int numCoords, int numObjs, int numClusters, float *objects, float *deviceClusters, int *membership, int *changedmembership )
{
extern __shared__ float sharedMem[];
float *sh_Clusters = sharedMem;
float *sh_Objects = (float*)&sh_Clusters[numClusters * 3];
for(int i = 0; i < numCoords * numClusters; i++) {
sh_Clusters[i] = deviceClusters[i];
}
__syncthreads();
unsigned int tid = threadIdx.x;
int objectId = blockDim.x * blockIdx.x + threadIdx.x;
while (objectId < numObjs) {
int index, i;
float dist, min_dist;
for(int i = 0; i < numCoords; i++) {
sh_Objects[3*tid+i] = objects[3*objectId+i];
}
index = 0;
min_dist = euclid_distance(numCoords, numObjs, numClusters, tid,
0, sh_Objects, sh_Clusters);
for (i=1; i<numClusters; i++) {
dist = euclid_distance(numCoords, numObjs, numClusters, tid,
i, sh_Objects, sh_Clusters);
if (dist < min_dist) {
min_dist = dist;
index = i;
}
}
if (membership[objectId] != index)
{
changedmembership[objectId] = 1;
membership[objectId] = index;
}
objectId += blockDim.x * gridDim.x;
}
} | .file "tmpxft_001274b3_00000000-6_find_nearest_cluster.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL20find_nearest_clusteriiiPfS_PiS0_, @function
_ZL20find_nearest_clusteriiiPfS_PiS0_:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl %edi, 4(%rsp)
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 24(%rsp)
movq %r9, 32(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL20find_nearest_clusteriiiPfS_PiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _ZL20find_nearest_clusteriiiPfS_PiS0_, .-_ZL20find_nearest_clusteriiiPfS_PiS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20find_nearest_clusteriiiPfS_PiS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL20find_nearest_clusteriiiPfS_PiS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ inline static float euclid_distance(int numCoords, int numObjs, int numClusters, int tid, int clusterId, float *objects, float *clusters )
{
float ans=0.0;
for (int i = 0; i < numCoords; i++) {
ans += (objects[3*tid+i] - clusters[i + clusterId*3]) *
(objects[3*tid+i] - clusters[i + clusterId*3]);
}
return(ans);
}
__global__ static void find_nearest_cluster(int numCoords, int numObjs, int numClusters, float *objects, float *deviceClusters, int *membership, int *changedmembership )
{
extern __shared__ float sharedMem[];
float *sh_Clusters = sharedMem;
float *sh_Objects = (float*)&sh_Clusters[numClusters * 3];
for(int i = 0; i < numCoords * numClusters; i++) {
sh_Clusters[i] = deviceClusters[i];
}
__syncthreads();
unsigned int tid = threadIdx.x;
int objectId = blockDim.x * blockIdx.x + threadIdx.x;
while (objectId < numObjs) {
int index, i;
float dist, min_dist;
for(int i = 0; i < numCoords; i++) {
sh_Objects[3*tid+i] = objects[3*objectId+i];
}
index = 0;
min_dist = euclid_distance(numCoords, numObjs, numClusters, tid,
0, sh_Objects, sh_Clusters);
for (i=1; i<numClusters; i++) {
dist = euclid_distance(numCoords, numObjs, numClusters, tid,
i, sh_Objects, sh_Clusters);
if (dist < min_dist) {
min_dist = dist;
index = i;
}
}
if (membership[objectId] != index)
{
changedmembership[objectId] = 1;
membership[objectId] = index;
}
objectId += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline static float euclid_distance(int numCoords, int numObjs, int numClusters, int tid, int clusterId, float *objects, float *clusters )
{
float ans=0.0;
for (int i = 0; i < numCoords; i++) {
ans += (objects[3*tid+i] - clusters[i + clusterId*3]) *
(objects[3*tid+i] - clusters[i + clusterId*3]);
}
return(ans);
}
__global__ static void find_nearest_cluster(int numCoords, int numObjs, int numClusters, float *objects, float *deviceClusters, int *membership, int *changedmembership )
{
extern __shared__ float sharedMem[];
float *sh_Clusters = sharedMem;
float *sh_Objects = (float*)&sh_Clusters[numClusters * 3];
for(int i = 0; i < numCoords * numClusters; i++) {
sh_Clusters[i] = deviceClusters[i];
}
__syncthreads();
unsigned int tid = threadIdx.x;
int objectId = blockDim.x * blockIdx.x + threadIdx.x;
while (objectId < numObjs) {
int index, i;
float dist, min_dist;
for(int i = 0; i < numCoords; i++) {
sh_Objects[3*tid+i] = objects[3*objectId+i];
}
index = 0;
min_dist = euclid_distance(numCoords, numObjs, numClusters, tid,
0, sh_Objects, sh_Clusters);
for (i=1; i<numClusters; i++) {
dist = euclid_distance(numCoords, numObjs, numClusters, tid,
i, sh_Objects, sh_Clusters);
if (dist < min_dist) {
min_dist = dist;
index = i;
}
}
if (membership[objectId] != index)
{
changedmembership[objectId] = 1;
membership[objectId] = index;
}
objectId += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline static float euclid_distance(int numCoords, int numObjs, int numClusters, int tid, int clusterId, float *objects, float *clusters )
{
float ans=0.0;
for (int i = 0; i < numCoords; i++) {
ans += (objects[3*tid+i] - clusters[i + clusterId*3]) *
(objects[3*tid+i] - clusters[i + clusterId*3]);
}
return(ans);
}
__global__ static void find_nearest_cluster(int numCoords, int numObjs, int numClusters, float *objects, float *deviceClusters, int *membership, int *changedmembership )
{
extern __shared__ float sharedMem[];
float *sh_Clusters = sharedMem;
float *sh_Objects = (float*)&sh_Clusters[numClusters * 3];
for(int i = 0; i < numCoords * numClusters; i++) {
sh_Clusters[i] = deviceClusters[i];
}
__syncthreads();
unsigned int tid = threadIdx.x;
int objectId = blockDim.x * blockIdx.x + threadIdx.x;
while (objectId < numObjs) {
int index, i;
float dist, min_dist;
for(int i = 0; i < numCoords; i++) {
sh_Objects[3*tid+i] = objects[3*objectId+i];
}
index = 0;
min_dist = euclid_distance(numCoords, numObjs, numClusters, tid,
0, sh_Objects, sh_Clusters);
for (i=1; i<numClusters; i++) {
dist = euclid_distance(numCoords, numObjs, numClusters, tid,
i, sh_Objects, sh_Clusters);
if (dist < min_dist) {
min_dist = dist;
index = i;
}
}
if (membership[objectId] != index)
{
changedmembership[objectId] = 1;
membership[objectId] = index;
}
objectId += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL20find_nearest_clusteriiiPfS_PiS0_,"axG",@progbits,_ZL20find_nearest_clusteriiiPfS_PiS0_,comdat
.globl _ZL20find_nearest_clusteriiiPfS_PiS0_
.p2align 8
.type _ZL20find_nearest_clusteriiiPfS_PiS0_,@function
_ZL20find_nearest_clusteriiiPfS_PiS0_:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s7, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x18
s_mov_b32 s5, 0
.LBB0_2:
s_waitcnt lgkmcnt(0)
s_load_b32 s8, s[2:3], 0x0
v_mov_b32_e32 v1, s5
s_add_i32 s4, s4, -1
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_add_i32 s5, s5, 4
s_cmp_eq_u32 s4, 0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v2, s8
ds_store_b32 v1, v2
s_cbranch_scc0 .LBB0_2
.LBB0_3:
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s8, s[0:1], 0x4
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s11, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s11, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_20
s_load_b32 s12, s[2:3], 0x0
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x20
v_mul_u32_u24_e32 v2, 3, v0
s_mul_i32 s13, s7, 12
s_cmp_gt_i32 s6, 0
v_lshl_add_u32 v3, v1, 1, v1
s_cselect_b32 s9, -1, 0
v_lshlrev_b32_e32 v2, 2, v2
v_mov_b32_e32 v0, 1
s_cmp_gt_i32 s7, 1
s_cselect_b32 s10, -1, 0
s_delay_alu instid0(VALU_DEP_2)
v_add_nc_u32_e32 v9, s13, v2
v_add3_u32 v8, 0, s13, v2
s_add_i32 s14, 0, 12
s_waitcnt lgkmcnt(0)
s_mul_i32 s11, s12, s11
s_mov_b32 s12, 0
s_mul_i32 s13, s11, 3
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s15
v_add_nc_u32_e32 v1, s11, v1
v_add_nc_u32_e32 v3, s13, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s8, v1
s_or_b32 s12, vcc_lo, s12
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_20
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_9
v_ashrrev_i32_e32 v4, 31, v3
v_mov_b32_e32 v2, v8
s_mov_b32 s15, s6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.LBB0_8:
global_load_b32 v6, v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s15, s15, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s15, 0
s_waitcnt vmcnt(0)
ds_store_b32 v2, v6
v_add_nc_u32_e32 v2, 4, v2
s_cbranch_scc0 .LBB0_8
.LBB0_9:
v_mov_b32_e32 v2, 0
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_12
s_mov_b32 s15, 0
s_mov_b32 s16, s6
.LBB0_11:
v_dual_mov_b32 v5, s15 :: v_dual_add_nc_u32 v4, s15, v9
s_add_i32 s16, s16, -1
s_add_i32 s15, s15, 4
s_cmp_lg_u32 s16, 0
ds_load_b32 v4, v4
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_sub_f32_e32 v4, v4, v5
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, v4, v4
s_cbranch_scc1 .LBB0_11
.LBB0_12:
v_mov_b32_e32 v10, 0
s_and_not1_b32 vcc_lo, exec_lo, s10
s_cbranch_vccnz .LBB0_18
v_mov_b32_e32 v10, 0
s_mov_b32 s15, 1
s_mov_b32 s16, s14
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_15
.p2align 6
.LBB0_14:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_cmp_lt_f32_e32 vcc_lo, v4, v2
s_add_i32 s16, s16, 12
v_cndmask_b32_e64 v10, v10, s15, vcc_lo
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_add_i32 s15, s15, 1
s_cmp_lg_u32 s15, s7
s_cbranch_scc0 .LBB0_18
.LBB0_15:
v_mov_b32_e32 v4, 0
s_and_not1_b32 vcc_lo, exec_lo, s9
s_cbranch_vccnz .LBB0_14
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, v8
s_mov_b32 s17, s16
s_mov_b32 s18, s6
.LBB0_17:
v_mov_b32_e32 v6, s17
s_add_i32 s18, s18, -1
s_add_i32 s17, s17, 4
s_cmp_lg_u32 s18, 0
ds_load_b32 v7, v5
ds_load_b32 v6, v6
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v6, v7, v6 :: v_dual_add_nc_u32 v5, 4, v5
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v6
s_cbranch_scc1 .LBB0_17
s_branch .LBB0_14
.LBB0_18:
s_set_inst_prefetch_distance 0x2
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_co_u32 v4, vcc_lo, s0, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v7, vcc_lo
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u32_e64 v2, v10
s_cbranch_execz .LBB0_5
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_b32 v[6:7], v0, off
global_store_b32 v[4:5], v10, off
s_branch .LBB0_5
.LBB0_20:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL20find_nearest_clusteriiiPfS_PiS0_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL20find_nearest_clusteriiiPfS_PiS0_,"axG",@progbits,_ZL20find_nearest_clusteriiiPfS_PiS0_,comdat
.Lfunc_end0:
.size _ZL20find_nearest_clusteriiiPfS_PiS0_, .Lfunc_end0-_ZL20find_nearest_clusteriiiPfS_PiS0_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
- .offset: 168
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL20find_nearest_clusteriiiPfS_PiS0_
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _ZL20find_nearest_clusteriiiPfS_PiS0_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline static float euclid_distance(int numCoords, int numObjs, int numClusters, int tid, int clusterId, float *objects, float *clusters )
{
float ans=0.0;
for (int i = 0; i < numCoords; i++) {
ans += (objects[3*tid+i] - clusters[i + clusterId*3]) *
(objects[3*tid+i] - clusters[i + clusterId*3]);
}
return(ans);
}
__global__ static void find_nearest_cluster(int numCoords, int numObjs, int numClusters, float *objects, float *deviceClusters, int *membership, int *changedmembership )
{
extern __shared__ float sharedMem[];
float *sh_Clusters = sharedMem;
float *sh_Objects = (float*)&sh_Clusters[numClusters * 3];
for(int i = 0; i < numCoords * numClusters; i++) {
sh_Clusters[i] = deviceClusters[i];
}
__syncthreads();
unsigned int tid = threadIdx.x;
int objectId = blockDim.x * blockIdx.x + threadIdx.x;
while (objectId < numObjs) {
int index, i;
float dist, min_dist;
for(int i = 0; i < numCoords; i++) {
sh_Objects[3*tid+i] = objects[3*objectId+i];
}
index = 0;
min_dist = euclid_distance(numCoords, numObjs, numClusters, tid,
0, sh_Objects, sh_Clusters);
for (i=1; i<numClusters; i++) {
dist = euclid_distance(numCoords, numObjs, numClusters, tid,
i, sh_Objects, sh_Clusters);
if (dist < min_dist) {
min_dist = dist;
index = i;
}
}
if (membership[objectId] != index)
{
changedmembership[objectId] = 1;
membership[objectId] = index;
}
objectId += blockDim.x * gridDim.x;
}
} | .text
.file "find_nearest_cluster.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001274b3_00000000-6_find_nearest_cluster.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL20find_nearest_clusteriiiPfS_PiS0_, @function
_ZL20find_nearest_clusteriiiPfS_PiS0_:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl %edi, 4(%rsp)
movl %esi, 8(%rsp)
movl %edx, 12(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 24(%rsp)
movq %r9, 32(%rsp)
movq 192(%rsp), %rax
movq %rax, 40(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 40(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _ZL20find_nearest_clusteriiiPfS_PiS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _ZL20find_nearest_clusteriiiPfS_PiS0_, .-_ZL20find_nearest_clusteriiiPfS_PiS0_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z20find_nearest_clusteriiiPfS_PiS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL20find_nearest_clusteriiiPfS_PiS0_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "find_nearest_cluster.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
typedef float MatrixVal;
typedef struct matrix {
MatrixVal *values;
unsigned int rows, cols;
} Matrix;
typedef struct input {
Matrix *A, *B;
} Input;
void setMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col, MatrixVal value) {
matrix->values[col + matrix->cols * row] = value;
}
MatrixVal getMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col) {
return matrix->values[col + matrix->cols * row];
}
void setMatrixSize(Matrix *matrix, unsigned int rows, unsigned int cols) {
matrix->values = (MatrixVal *) malloc(rows * cols * sizeof(MatrixVal));
matrix->cols = cols;
matrix->rows = rows;
}
Matrix *newMatrix() {
Matrix *matrix = (Matrix *) malloc(sizeof(Matrix));
return matrix;
}
void deleteMatrix(Matrix *matrix) {
free(matrix->values);
free(matrix);
}
Matrix *readMatrixFrom(FILE *src) {
unsigned int row, col, rows, cols;
MatrixVal value;
Matrix *matrix = newMatrix();
fscanf(src, "%u %u", &rows, &cols);
setMatrixSize(matrix, rows, cols);
for (row = 0; row < rows; row++) {
for (col = 0; col < cols; col++) {
fscanf(src, "%f", &value);
setMatrixPosition(matrix, row, col, value);
}
}
return matrix;
}
void deleteInput(Input input) {
deleteMatrix(input.A);
deleteMatrix(input.B);
}
Input readMatricesFromFiles(char *fileName1, char *fileName2) {
Input input;
FILE *file1, *file2;
file1 = fopen(fileName1, "r");
input.A = readMatrixFrom(file1);
fclose(file1);
file2 = fopen(fileName2, "r");
input.B = readMatrixFrom(file2);
fclose(file2);
return input;
}
Input readMatricesFromStdin() {
Input input;
input.A = readMatrixFrom(stdin);
input.B = readMatrixFrom(stdin);
return input;
}
void printUsage() {
printf("Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]\n");
printf("\nIf files are not passed, matrices are read from stdin.\n");
printf("Input format: n-rows n-cols entries\n");
printf("Output format: n-rows n-cols result-entries\n");
printf("Output is always to stdout\n");
}
void processUsingCuda(Input input) {
}
void processUsingCpu(Input input) {
}
int main(int argc, char **argv) {
Input input;
if (argc == 2) {
input = readMatricesFromStdin();
} else if (argc == 4) {
input = readMatricesFromFiles(argv[2], argv[3]);
} else {
printf("Error: wrong number of arguments: %d\n", argc);
printUsage();
return 1;
}
if (strcmp(argv[1], "cuda") == 0) {
processUsingCuda(input);
} else if (strcmp(argv[1], "cpu") == 0) {
processUsingCpu(input);
} else {
printf("Error: %s is not a valid form of computation\n");
printUsage();
return 2;
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
typedef float MatrixVal;
typedef struct matrix {
MatrixVal *values;
unsigned int rows, cols;
} Matrix;
typedef struct input {
Matrix *A, *B;
} Input;
void setMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col, MatrixVal value) {
matrix->values[col + matrix->cols * row] = value;
}
MatrixVal getMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col) {
return matrix->values[col + matrix->cols * row];
}
void setMatrixSize(Matrix *matrix, unsigned int rows, unsigned int cols) {
matrix->values = (MatrixVal *) malloc(rows * cols * sizeof(MatrixVal));
matrix->cols = cols;
matrix->rows = rows;
}
Matrix *newMatrix() {
Matrix *matrix = (Matrix *) malloc(sizeof(Matrix));
return matrix;
}
void deleteMatrix(Matrix *matrix) {
free(matrix->values);
free(matrix);
}
Matrix *readMatrixFrom(FILE *src) {
unsigned int row, col, rows, cols;
MatrixVal value;
Matrix *matrix = newMatrix();
fscanf(src, "%u %u", &rows, &cols);
setMatrixSize(matrix, rows, cols);
for (row = 0; row < rows; row++) {
for (col = 0; col < cols; col++) {
fscanf(src, "%f", &value);
setMatrixPosition(matrix, row, col, value);
}
}
return matrix;
}
void deleteInput(Input input) {
deleteMatrix(input.A);
deleteMatrix(input.B);
}
Input readMatricesFromFiles(char *fileName1, char *fileName2) {
Input input;
FILE *file1, *file2;
file1 = fopen(fileName1, "r");
input.A = readMatrixFrom(file1);
fclose(file1);
file2 = fopen(fileName2, "r");
input.B = readMatrixFrom(file2);
fclose(file2);
return input;
}
Input readMatricesFromStdin() {
Input input;
input.A = readMatrixFrom(stdin);
input.B = readMatrixFrom(stdin);
return input;
}
void printUsage() {
printf("Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]\n");
printf("\nIf files are not passed, matrices are read from stdin.\n");
printf("Input format: n-rows n-cols entries\n");
printf("Output format: n-rows n-cols result-entries\n");
printf("Output is always to stdout\n");
}
void processUsingCuda(Input input) {
}
void processUsingCpu(Input input) {
}
int main(int argc, char **argv) {
Input input;
if (argc == 2) {
input = readMatricesFromStdin();
} else if (argc == 4) {
input = readMatricesFromFiles(argv[2], argv[3]);
} else {
printf("Error: wrong number of arguments: %d\n", argc);
printUsage();
return 1;
}
if (strcmp(argv[1], "cuda") == 0) {
processUsingCuda(input);
} else if (strcmp(argv[1], "cpu") == 0) {
processUsingCpu(input);
} else {
printf("Error: %s is not a valid form of computation\n");
printUsage();
return 2;
}
return 0;
} | .file "tmpxft_00096d7d_00000000-6_matrix-multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17setMatrixPositionP6matrixjjf
.type _Z17setMatrixPositionP6matrixjjf, @function
_Z17setMatrixPositionP6matrixjjf:
.LFB2057:
.cfi_startproc
endbr64
imull 12(%rdi), %esi
leal (%rsi,%rdx), %edx
movq (%rdi), %rax
movss %xmm0, (%rax,%rdx,4)
ret
.cfi_endproc
.LFE2057:
.size _Z17setMatrixPositionP6matrixjjf, .-_Z17setMatrixPositionP6matrixjjf
.globl _Z17getMatrixPositionP6matrixjj
.type _Z17getMatrixPositionP6matrixjj, @function
_Z17getMatrixPositionP6matrixjj:
.LFB2058:
.cfi_startproc
endbr64
imull 12(%rdi), %esi
leal (%rsi,%rdx), %edx
movq (%rdi), %rax
movss (%rax,%rdx,4), %xmm0
ret
.cfi_endproc
.LFE2058:
.size _Z17getMatrixPositionP6matrixjj, .-_Z17getMatrixPositionP6matrixjj
.globl _Z13setMatrixSizeP6matrixjj
.type _Z13setMatrixSizeP6matrixjj, @function
_Z13setMatrixSizeP6matrixjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
movl %edx, %r12d
movl %esi, %edi
imull %edx, %edi
salq $2, %rdi
call malloc@PLT
movq %rax, (%rbx)
movl %r12d, 12(%rbx)
movl %ebp, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z13setMatrixSizeP6matrixjj, .-_Z13setMatrixSizeP6matrixjj
.globl _Z9newMatrixv
.type _Z9newMatrixv, @function
_Z9newMatrixv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $16, %edi
call malloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9newMatrixv, .-_Z9newMatrixv
.globl _Z12deleteMatrixP6matrix
.type _Z12deleteMatrixP6matrix, @function
_Z12deleteMatrixP6matrix:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12deleteMatrixP6matrix, .-_Z12deleteMatrixP6matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%u %u"
.LC1:
.string "%f"
.text
.globl _Z14readMatrixFromP8_IO_FILE
.type _Z14readMatrixFromP8_IO_FILE, @function
_Z14readMatrixFromP8_IO_FILE:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call _Z9newMatrixv
movq %rax, %r12
leaq 16(%rsp), %rcx
leaq 12(%rsp), %rdx
leaq .LC0(%rip), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %ebx
movl 16(%rsp), %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z13setMatrixSizeP6matrixjj
movl $0, %ebp
leaq .LC1(%rip), %r14
testl %ebx, %ebx
jne .L12
.L11:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L23
movq %r12, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq 20(%rsp), %rdx
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movss 20(%rsp), %xmm0
movl %ebx, %edx
movl %ebp, %esi
movq %r12, %rdi
call _Z17setMatrixPositionP6matrixjjf
addl $1, %ebx
cmpl 16(%rsp), %ebx
jb .L14
.L15:
addl $1, %ebp
cmpl 12(%rsp), %ebp
jnb .L11
.L12:
movl $0, %ebx
cmpl $0, 16(%rsp)
jne .L14
jmp .L15
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z14readMatrixFromP8_IO_FILE, .-_Z14readMatrixFromP8_IO_FILE
.globl _Z11deleteInput5input
.type _Z11deleteInput5input, @function
_Z11deleteInput5input:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
call _Z12deleteMatrixP6matrix
movq %rbx, %rdi
call _Z12deleteMatrixP6matrix
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z11deleteInput5input, .-_Z11deleteInput5input
.section .rodata.str1.1
.LC2:
.string "r"
.text
.globl _Z21readMatricesFromFilesPcS_
.type _Z21readMatricesFromFilesPcS_, @function
_Z21readMatricesFromFilesPcS_:
.LFB2064:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbp
leaq .LC2(%rip), %r13
movq %r13, %rsi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rdi
call _Z14readMatrixFromP8_IO_FILE
movq %rax, %r12
movq %rbx, %rdi
call fclose@PLT
movq %r13, %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rdi
call _Z14readMatrixFromP8_IO_FILE
movq %rax, %rbp
movq %rbx, %rdi
call fclose@PLT
movq %r12, %rax
movq %rbp, %rdx
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z21readMatricesFromFilesPcS_, .-_Z21readMatricesFromFilesPcS_
.globl _Z21readMatricesFromStdinv
.type _Z21readMatricesFromStdinv, @function
_Z21readMatricesFromStdinv:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq stdin(%rip), %rdi
call _Z14readMatrixFromP8_IO_FILE
movq %rax, %rbx
movq stdin(%rip), %rdi
call _Z14readMatrixFromP8_IO_FILE
movq %rax, %rdx
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z21readMatricesFromStdinv, .-_Z21readMatricesFromStdinv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]\n"
.align 8
.LC4:
.string "\nIf files are not passed, matrices are read from stdin.\n"
.align 8
.LC5:
.string "Input format: n-rows n-cols entries\n"
.align 8
.LC6:
.string "Output format: n-rows n-cols result-entries\n"
.section .rodata.str1.1
.LC7:
.string "Output is always to stdout\n"
.text
.globl _Z10printUsagev
.type _Z10printUsagev, @function
_Z10printUsagev:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z10printUsagev, .-_Z10printUsagev
.globl _Z16processUsingCuda5input
.type _Z16processUsingCuda5input, @function
_Z16processUsingCuda5input:
.LFB2067:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2067:
.size _Z16processUsingCuda5input, .-_Z16processUsingCuda5input
.globl _Z15processUsingCpu5input
.type _Z15processUsingCpu5input, @function
_Z15processUsingCpu5input:
.LFB2068:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2068:
.size _Z15processUsingCpu5input, .-_Z15processUsingCpu5input
.section .rodata.str1.8
.align 8
.LC8:
.string "Error: wrong number of arguments: %d\n"
.section .rodata.str1.1
.LC9:
.string "cuda"
.LC10:
.string "cpu"
.section .rodata.str1.8
.align 8
.LC11:
.string "Error: %s is not a valid form of computation\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
cmpl $2, %edi
je .L40
cmpl $4, %edi
jne .L37
movq 24(%rsi), %rsi
movq 16(%rbx), %rdi
call _Z21readMatricesFromFilesPcS_
.L36:
movq 8(%rbx), %rbx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
je .L38
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
je .L38
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10printUsagev
movl $2, %eax
jmp .L38
.L40:
call _Z21readMatricesFromStdinv
jmp .L36
.L37:
movl %edi, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10printUsagev
movl $1, %eax
.L38:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
typedef float MatrixVal;
typedef struct matrix {
MatrixVal *values;
unsigned int rows, cols;
} Matrix;
typedef struct input {
Matrix *A, *B;
} Input;
void setMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col, MatrixVal value) {
matrix->values[col + matrix->cols * row] = value;
}
MatrixVal getMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col) {
return matrix->values[col + matrix->cols * row];
}
void setMatrixSize(Matrix *matrix, unsigned int rows, unsigned int cols) {
matrix->values = (MatrixVal *) malloc(rows * cols * sizeof(MatrixVal));
matrix->cols = cols;
matrix->rows = rows;
}
Matrix *newMatrix() {
Matrix *matrix = (Matrix *) malloc(sizeof(Matrix));
return matrix;
}
void deleteMatrix(Matrix *matrix) {
free(matrix->values);
free(matrix);
}
Matrix *readMatrixFrom(FILE *src) {
unsigned int row, col, rows, cols;
MatrixVal value;
Matrix *matrix = newMatrix();
fscanf(src, "%u %u", &rows, &cols);
setMatrixSize(matrix, rows, cols);
for (row = 0; row < rows; row++) {
for (col = 0; col < cols; col++) {
fscanf(src, "%f", &value);
setMatrixPosition(matrix, row, col, value);
}
}
return matrix;
}
void deleteInput(Input input) {
deleteMatrix(input.A);
deleteMatrix(input.B);
}
Input readMatricesFromFiles(char *fileName1, char *fileName2) {
Input input;
FILE *file1, *file2;
file1 = fopen(fileName1, "r");
input.A = readMatrixFrom(file1);
fclose(file1);
file2 = fopen(fileName2, "r");
input.B = readMatrixFrom(file2);
fclose(file2);
return input;
}
Input readMatricesFromStdin() {
Input input;
input.A = readMatrixFrom(stdin);
input.B = readMatrixFrom(stdin);
return input;
}
void printUsage() {
printf("Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]\n");
printf("\nIf files are not passed, matrices are read from stdin.\n");
printf("Input format: n-rows n-cols entries\n");
printf("Output format: n-rows n-cols result-entries\n");
printf("Output is always to stdout\n");
}
void processUsingCuda(Input input) {
}
void processUsingCpu(Input input) {
}
int main(int argc, char **argv) {
Input input;
if (argc == 2) {
input = readMatricesFromStdin();
} else if (argc == 4) {
input = readMatricesFromFiles(argv[2], argv[3]);
} else {
printf("Error: wrong number of arguments: %d\n", argc);
printUsage();
return 1;
}
if (strcmp(argv[1], "cuda") == 0) {
processUsingCuda(input);
} else if (strcmp(argv[1], "cpu") == 0) {
processUsingCpu(input);
} else {
printf("Error: %s is not a valid form of computation\n");
printUsage();
return 2;
}
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
typedef float MatrixVal;
typedef struct matrix {
MatrixVal *values;
unsigned int rows, cols;
} Matrix;
typedef struct input {
Matrix *A, *B;
} Input;
void setMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col, MatrixVal value) {
matrix->values[col + matrix->cols * row] = value;
}
MatrixVal getMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col) {
return matrix->values[col + matrix->cols * row];
}
void setMatrixSize(Matrix *matrix, unsigned int rows, unsigned int cols) {
matrix->values = (MatrixVal *) malloc(rows * cols * sizeof(MatrixVal));
matrix->cols = cols;
matrix->rows = rows;
}
Matrix *newMatrix() {
Matrix *matrix = (Matrix *) malloc(sizeof(Matrix));
return matrix;
}
void deleteMatrix(Matrix *matrix) {
free(matrix->values);
free(matrix);
}
Matrix *readMatrixFrom(FILE *src) {
unsigned int row, col, rows, cols;
MatrixVal value;
Matrix *matrix = newMatrix();
fscanf(src, "%u %u", &rows, &cols);
setMatrixSize(matrix, rows, cols);
for (row = 0; row < rows; row++) {
for (col = 0; col < cols; col++) {
fscanf(src, "%f", &value);
setMatrixPosition(matrix, row, col, value);
}
}
return matrix;
}
void deleteInput(Input input) {
deleteMatrix(input.A);
deleteMatrix(input.B);
}
Input readMatricesFromFiles(char *fileName1, char *fileName2) {
Input input;
FILE *file1, *file2;
file1 = fopen(fileName1, "r");
input.A = readMatrixFrom(file1);
fclose(file1);
file2 = fopen(fileName2, "r");
input.B = readMatrixFrom(file2);
fclose(file2);
return input;
}
Input readMatricesFromStdin() {
Input input;
input.A = readMatrixFrom(stdin);
input.B = readMatrixFrom(stdin);
return input;
}
void printUsage() {
printf("Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]\n");
printf("\nIf files are not passed, matrices are read from stdin.\n");
printf("Input format: n-rows n-cols entries\n");
printf("Output format: n-rows n-cols result-entries\n");
printf("Output is always to stdout\n");
}
void processUsingCuda(Input input) {
}
void processUsingCpu(Input input) {
}
int main(int argc, char **argv) {
Input input;
if (argc == 2) {
input = readMatricesFromStdin();
} else if (argc == 4) {
input = readMatricesFromFiles(argv[2], argv[3]);
} else {
printf("Error: wrong number of arguments: %d\n", argc);
printUsage();
return 1;
}
if (strcmp(argv[1], "cuda") == 0) {
processUsingCuda(input);
} else if (strcmp(argv[1], "cpu") == 0) {
processUsingCpu(input);
} else {
printf("Error: %s is not a valid form of computation\n");
printUsage();
return 2;
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
typedef float MatrixVal;
typedef struct matrix {
MatrixVal *values;
unsigned int rows, cols;
} Matrix;
typedef struct input {
Matrix *A, *B;
} Input;
void setMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col, MatrixVal value) {
matrix->values[col + matrix->cols * row] = value;
}
MatrixVal getMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col) {
return matrix->values[col + matrix->cols * row];
}
void setMatrixSize(Matrix *matrix, unsigned int rows, unsigned int cols) {
matrix->values = (MatrixVal *) malloc(rows * cols * sizeof(MatrixVal));
matrix->cols = cols;
matrix->rows = rows;
}
Matrix *newMatrix() {
Matrix *matrix = (Matrix *) malloc(sizeof(Matrix));
return matrix;
}
void deleteMatrix(Matrix *matrix) {
free(matrix->values);
free(matrix);
}
Matrix *readMatrixFrom(FILE *src) {
unsigned int row, col, rows, cols;
MatrixVal value;
Matrix *matrix = newMatrix();
fscanf(src, "%u %u", &rows, &cols);
setMatrixSize(matrix, rows, cols);
for (row = 0; row < rows; row++) {
for (col = 0; col < cols; col++) {
fscanf(src, "%f", &value);
setMatrixPosition(matrix, row, col, value);
}
}
return matrix;
}
void deleteInput(Input input) {
deleteMatrix(input.A);
deleteMatrix(input.B);
}
Input readMatricesFromFiles(char *fileName1, char *fileName2) {
Input input;
FILE *file1, *file2;
file1 = fopen(fileName1, "r");
input.A = readMatrixFrom(file1);
fclose(file1);
file2 = fopen(fileName2, "r");
input.B = readMatrixFrom(file2);
fclose(file2);
return input;
}
Input readMatricesFromStdin() {
Input input;
input.A = readMatrixFrom(stdin);
input.B = readMatrixFrom(stdin);
return input;
}
void printUsage() {
printf("Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]\n");
printf("\nIf files are not passed, matrices are read from stdin.\n");
printf("Input format: n-rows n-cols entries\n");
printf("Output format: n-rows n-cols result-entries\n");
printf("Output is always to stdout\n");
}
void processUsingCuda(Input input) {
}
void processUsingCpu(Input input) {
}
int main(int argc, char **argv) {
Input input;
if (argc == 2) {
input = readMatricesFromStdin();
} else if (argc == 4) {
input = readMatricesFromFiles(argv[2], argv[3]);
} else {
printf("Error: wrong number of arguments: %d\n", argc);
printUsage();
return 1;
}
if (strcmp(argv[1], "cuda") == 0) {
processUsingCuda(input);
} else if (strcmp(argv[1], "cpu") == 0) {
processUsingCpu(input);
} else {
printf("Error: %s is not a valid form of computation\n");
printUsage();
return 2;
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
typedef float MatrixVal;
typedef struct matrix {
MatrixVal *values;
unsigned int rows, cols;
} Matrix;
typedef struct input {
Matrix *A, *B;
} Input;
void setMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col, MatrixVal value) {
matrix->values[col + matrix->cols * row] = value;
}
MatrixVal getMatrixPosition(Matrix *matrix, unsigned int row, unsigned int col) {
return matrix->values[col + matrix->cols * row];
}
void setMatrixSize(Matrix *matrix, unsigned int rows, unsigned int cols) {
matrix->values = (MatrixVal *) malloc(rows * cols * sizeof(MatrixVal));
matrix->cols = cols;
matrix->rows = rows;
}
Matrix *newMatrix() {
Matrix *matrix = (Matrix *) malloc(sizeof(Matrix));
return matrix;
}
void deleteMatrix(Matrix *matrix) {
free(matrix->values);
free(matrix);
}
Matrix *readMatrixFrom(FILE *src) {
unsigned int row, col, rows, cols;
MatrixVal value;
Matrix *matrix = newMatrix();
fscanf(src, "%u %u", &rows, &cols);
setMatrixSize(matrix, rows, cols);
for (row = 0; row < rows; row++) {
for (col = 0; col < cols; col++) {
fscanf(src, "%f", &value);
setMatrixPosition(matrix, row, col, value);
}
}
return matrix;
}
void deleteInput(Input input) {
deleteMatrix(input.A);
deleteMatrix(input.B);
}
Input readMatricesFromFiles(char *fileName1, char *fileName2) {
Input input;
FILE *file1, *file2;
file1 = fopen(fileName1, "r");
input.A = readMatrixFrom(file1);
fclose(file1);
file2 = fopen(fileName2, "r");
input.B = readMatrixFrom(file2);
fclose(file2);
return input;
}
Input readMatricesFromStdin() {
Input input;
input.A = readMatrixFrom(stdin);
input.B = readMatrixFrom(stdin);
return input;
}
void printUsage() {
printf("Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]\n");
printf("\nIf files are not passed, matrices are read from stdin.\n");
printf("Input format: n-rows n-cols entries\n");
printf("Output format: n-rows n-cols result-entries\n");
printf("Output is always to stdout\n");
}
void processUsingCuda(Input input) {
}
void processUsingCpu(Input input) {
}
int main(int argc, char **argv) {
Input input;
if (argc == 2) {
input = readMatricesFromStdin();
} else if (argc == 4) {
input = readMatricesFromFiles(argv[2], argv[3]);
} else {
printf("Error: wrong number of arguments: %d\n", argc);
printUsage();
return 1;
}
if (strcmp(argv[1], "cuda") == 0) {
processUsingCuda(input);
} else if (strcmp(argv[1], "cpu") == 0) {
processUsingCpu(input);
} else {
printf("Error: %s is not a valid form of computation\n");
printUsage();
return 2;
}
return 0;
} | .text
.file "matrix-multiply.hip"
.globl _Z17setMatrixPositionP6matrixjjf # -- Begin function _Z17setMatrixPositionP6matrixjjf
.p2align 4, 0x90
.type _Z17setMatrixPositionP6matrixjjf,@function
_Z17setMatrixPositionP6matrixjjf: # @_Z17setMatrixPositionP6matrixjjf
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
movq (%rdi), %rax
imull 12(%rdi), %esi
addl %edx, %esi
movss %xmm0, (%rax,%rsi,4)
retq
.Lfunc_end0:
.size _Z17setMatrixPositionP6matrixjjf, .Lfunc_end0-_Z17setMatrixPositionP6matrixjjf
.cfi_endproc
# -- End function
.globl _Z17getMatrixPositionP6matrixjj # -- Begin function _Z17getMatrixPositionP6matrixjj
.p2align 4, 0x90
.type _Z17getMatrixPositionP6matrixjj,@function
_Z17getMatrixPositionP6matrixjj: # @_Z17getMatrixPositionP6matrixjj
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
imull 12(%rdi), %esi
movq (%rdi), %rax
addl %edx, %esi
movss (%rax,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
retq
.Lfunc_end1:
.size _Z17getMatrixPositionP6matrixjj, .Lfunc_end1-_Z17getMatrixPositionP6matrixjj
.cfi_endproc
# -- End function
.globl _Z13setMatrixSizeP6matrixjj # -- Begin function _Z13setMatrixSizeP6matrixjj
.p2align 4, 0x90
.type _Z13setMatrixSizeP6matrixjj,@function
_Z13setMatrixSizeP6matrixjj: # @_Z13setMatrixSizeP6matrixjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl %edx, %edi
imull %esi, %edi
shlq $2, %rdi
callq malloc
movq %rax, (%r14)
movl %ebx, 12(%r14)
movl %ebp, 8(%r14)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13setMatrixSizeP6matrixjj, .Lfunc_end2-_Z13setMatrixSizeP6matrixjj
.cfi_endproc
# -- End function
.globl _Z9newMatrixv # -- Begin function _Z9newMatrixv
.p2align 4, 0x90
.type _Z9newMatrixv,@function
_Z9newMatrixv: # @_Z9newMatrixv
.cfi_startproc
# %bb.0:
movl $16, %edi
jmp malloc # TAILCALL
.Lfunc_end3:
.size _Z9newMatrixv, .Lfunc_end3-_Z9newMatrixv
.cfi_endproc
# -- End function
.globl _Z12deleteMatrixP6matrix # -- Begin function _Z12deleteMatrixP6matrix
.p2align 4, 0x90
.type _Z12deleteMatrixP6matrix,@function
_Z12deleteMatrixP6matrix: # @_Z12deleteMatrixP6matrix
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rdi
callq free
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end4:
.size _Z12deleteMatrixP6matrix, .Lfunc_end4-_Z12deleteMatrixP6matrix
.cfi_endproc
# -- End function
.globl _Z14readMatrixFromP8_IO_FILE # -- Begin function _Z14readMatrixFromP8_IO_FILE
.p2align 4, 0x90
.type _Z14readMatrixFromP8_IO_FILE,@function
_Z14readMatrixFromP8_IO_FILE: # @_Z14readMatrixFromP8_IO_FILE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rcx
movl $.L.str, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 16(%rsp), %ebp
movl 12(%rsp), %r12d
movl %r12d, %edi
imull %ebp, %edi
shlq $2, %rdi
callq malloc
movq %rax, (%r14)
movq %r12, 32(%rsp) # 8-byte Spill
movl %r12d, 12(%r14)
movq %r14, 24(%rsp) # 8-byte Spill
movl %ebp, 8(%r14)
cmpl $0, 16(%rsp)
je .LBB5_6
# %bb.1: # %.preheader.preheader
movq %rax, %r15
leaq 20(%rsp), %r12
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incl %r14d
addq 32(%rsp), %rbp # 8-byte Folded Reload
cmpl 16(%rsp), %r14d
jae .LBB5_6
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
cmpl $0, 12(%rsp)
je .LBB5_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
leal (%rbp,%r13), %eax
movss %xmm0, (%r15,%rax,4)
incq %r13
movl 12(%rsp), %eax
cmpq %rax, %r13
jb .LBB5_4
jmp .LBB5_5
.LBB5_6: # %._crit_edge13
movq 24(%rsp), %rax # 8-byte Reload
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z14readMatrixFromP8_IO_FILE, .Lfunc_end5-_Z14readMatrixFromP8_IO_FILE
.cfi_endproc
# -- End function
.globl _Z11deleteInput5input # -- Begin function _Z11deleteInput5input
.p2align 4, 0x90
.type _Z11deleteInput5input,@function
_Z11deleteInput5input: # @_Z11deleteInput5input
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq (%rdi), %rdi
callq free
movq %r14, %rdi
callq free
movq (%rbx), %rdi
callq free
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end6:
.size _Z11deleteInput5input, .Lfunc_end6-_Z11deleteInput5input
.cfi_endproc
# -- End function
.globl _Z21readMatricesFromFilesPcS_ # -- Begin function _Z21readMatricesFromFilesPcS_
.p2align 4, 0x90
.type _Z21readMatricesFromFilesPcS_,@function
_Z21readMatricesFromFilesPcS_: # @_Z21readMatricesFromFilesPcS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
movq %rax, %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %rax, %r15
movq %r14, %rdi
callq fclose
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
movq %rax, %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %rax, %r14
movq %rbx, %rdi
callq fclose
movq %r15, %rax
movq %r14, %rdx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z21readMatricesFromFilesPcS_, .Lfunc_end7-_Z21readMatricesFromFilesPcS_
.cfi_endproc
# -- End function
.globl _Z21readMatricesFromStdinv # -- Begin function _Z21readMatricesFromStdinv
.p2align 4, 0x90
.type _Z21readMatricesFromStdinv,@function
_Z21readMatricesFromStdinv: # @_Z21readMatricesFromStdinv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq stdin(%rip), %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %rax, %rbx
movq stdin(%rip), %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %rax, %rdx
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z21readMatricesFromStdinv, .Lfunc_end8-_Z21readMatricesFromStdinv
.cfi_endproc
# -- End function
.globl _Z10printUsagev # -- Begin function _Z10printUsagev
.p2align 4, 0x90
.type _Z10printUsagev,@function
_Z10printUsagev: # @_Z10printUsagev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end9:
.size _Z10printUsagev, .Lfunc_end9-_Z10printUsagev
.cfi_endproc
# -- End function
.globl _Z16processUsingCuda5input # -- Begin function _Z16processUsingCuda5input
.p2align 4, 0x90
.type _Z16processUsingCuda5input,@function
_Z16processUsingCuda5input: # @_Z16processUsingCuda5input
.cfi_startproc
# %bb.0:
retq
.Lfunc_end10:
.size _Z16processUsingCuda5input, .Lfunc_end10-_Z16processUsingCuda5input
.cfi_endproc
# -- End function
.globl _Z15processUsingCpu5input # -- Begin function _Z15processUsingCpu5input
.p2align 4, 0x90
.type _Z15processUsingCpu5input,@function
_Z15processUsingCpu5input: # @_Z15processUsingCpu5input
.cfi_startproc
# %bb.0:
retq
.Lfunc_end11:
.size _Z15processUsingCpu5input, .Lfunc_end11-_Z15processUsingCpu5input
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $4, %edi
je .LBB12_4
# %bb.1:
movl %edi, %esi
cmpl $2, %edi
jne .LBB12_3
# %bb.2:
movq stdin(%rip), %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq stdin(%rip), %rdi
callq _Z14readMatrixFromP8_IO_FILE
jmp .LBB12_5
.LBB12_4:
movq 16(%rbx), %rdi
movq 24(%rbx), %r14
movl $.L.str.2, %esi
callq fopen
movq %rax, %r15
movq %rax, %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %r15, %rdi
callq fclose
movl $.L.str.2, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
movq %rax, %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %r14, %rdi
callq fclose
.LBB12_5:
movq 8(%rbx), %r14
movl $.L.str.9, %esi
movq %r14, %rdi
callq strcmp
xorl %ebx, %ebx
testl %eax, %eax
je .LBB12_9
# %bb.6:
movl $.L.str.10, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB12_9
# %bb.7:
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $2, %ebx
jmp .LBB12_8
.LBB12_3:
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $1, %ebx
.LBB12_8: # %.sink.split
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
.LBB12_9:
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size main, .Lfunc_end12-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%u %u"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: wrong number of arguments: %d\n"
.size .L.str.8, 38
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "cuda"
.size .L.str.9, 5
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "cpu"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Error: %s is not a valid form of computation\n"
.size .L.str.11, 46
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]"
.size .Lstr, 72
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nIf files are not passed, matrices are read from stdin."
.size .Lstr.1, 56
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Input format: n-rows n-cols entries"
.size .Lstr.2, 36
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Output format: n-rows n-cols result-entries"
.size .Lstr.3, 44
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Output is always to stdout"
.size .Lstr.4, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00096d7d_00000000-6_matrix-multiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2072:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z17setMatrixPositionP6matrixjjf
.type _Z17setMatrixPositionP6matrixjjf, @function
_Z17setMatrixPositionP6matrixjjf:
.LFB2057:
.cfi_startproc
endbr64
imull 12(%rdi), %esi
leal (%rsi,%rdx), %edx
movq (%rdi), %rax
movss %xmm0, (%rax,%rdx,4)
ret
.cfi_endproc
.LFE2057:
.size _Z17setMatrixPositionP6matrixjjf, .-_Z17setMatrixPositionP6matrixjjf
.globl _Z17getMatrixPositionP6matrixjj
.type _Z17getMatrixPositionP6matrixjj, @function
_Z17getMatrixPositionP6matrixjj:
.LFB2058:
.cfi_startproc
endbr64
imull 12(%rdi), %esi
leal (%rsi,%rdx), %edx
movq (%rdi), %rax
movss (%rax,%rdx,4), %xmm0
ret
.cfi_endproc
.LFE2058:
.size _Z17getMatrixPositionP6matrixjj, .-_Z17getMatrixPositionP6matrixjj
.globl _Z13setMatrixSizeP6matrixjj
.type _Z13setMatrixSizeP6matrixjj, @function
_Z13setMatrixSizeP6matrixjj:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl %esi, %ebp
movl %edx, %r12d
movl %esi, %edi
imull %edx, %edi
salq $2, %rdi
call malloc@PLT
movq %rax, (%rbx)
movl %r12d, 12(%rbx)
movl %ebp, 8(%rbx)
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z13setMatrixSizeP6matrixjj, .-_Z13setMatrixSizeP6matrixjj
.globl _Z9newMatrixv
.type _Z9newMatrixv, @function
_Z9newMatrixv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $16, %edi
call malloc@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9newMatrixv, .-_Z9newMatrixv
.globl _Z12deleteMatrixP6matrix
.type _Z12deleteMatrixP6matrix, @function
_Z12deleteMatrixP6matrix:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq (%rdi), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z12deleteMatrixP6matrix, .-_Z12deleteMatrixP6matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%u %u"
.LC1:
.string "%f"
.text
.globl _Z14readMatrixFromP8_IO_FILE
.type _Z14readMatrixFromP8_IO_FILE, @function
_Z14readMatrixFromP8_IO_FILE:
.LFB2062:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
call _Z9newMatrixv
movq %rax, %r12
leaq 16(%rsp), %rcx
leaq 12(%rsp), %rdx
leaq .LC0(%rip), %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %ebx
movl 16(%rsp), %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z13setMatrixSizeP6matrixjj
movl $0, %ebp
leaq .LC1(%rip), %r14
testl %ebx, %ebx
jne .L12
.L11:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L23
movq %r12, %rax
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
leaq 20(%rsp), %rdx
movq %r14, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movss 20(%rsp), %xmm0
movl %ebx, %edx
movl %ebp, %esi
movq %r12, %rdi
call _Z17setMatrixPositionP6matrixjjf
addl $1, %ebx
cmpl 16(%rsp), %ebx
jb .L14
.L15:
addl $1, %ebp
cmpl 12(%rsp), %ebp
jnb .L11
.L12:
movl $0, %ebx
cmpl $0, 16(%rsp)
jne .L14
jmp .L15
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size _Z14readMatrixFromP8_IO_FILE, .-_Z14readMatrixFromP8_IO_FILE
.globl _Z11deleteInput5input
.type _Z11deleteInput5input, @function
_Z11deleteInput5input:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
call _Z12deleteMatrixP6matrix
movq %rbx, %rdi
call _Z12deleteMatrixP6matrix
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _Z11deleteInput5input, .-_Z11deleteInput5input
.section .rodata.str1.1
.LC2:
.string "r"
.text
.globl _Z21readMatricesFromFilesPcS_
.type _Z21readMatricesFromFilesPcS_, @function
_Z21readMatricesFromFilesPcS_:
.LFB2064:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbp
leaq .LC2(%rip), %r13
movq %r13, %rsi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rdi
call _Z14readMatrixFromP8_IO_FILE
movq %rax, %r12
movq %rbx, %rdi
call fclose@PLT
movq %r13, %rsi
movq %rbp, %rdi
call fopen@PLT
movq %rax, %rbx
movq %rax, %rdi
call _Z14readMatrixFromP8_IO_FILE
movq %rax, %rbp
movq %rbx, %rdi
call fclose@PLT
movq %r12, %rax
movq %rbp, %rdx
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2064:
.size _Z21readMatricesFromFilesPcS_, .-_Z21readMatricesFromFilesPcS_
.globl _Z21readMatricesFromStdinv
.type _Z21readMatricesFromStdinv, @function
_Z21readMatricesFromStdinv:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq stdin(%rip), %rdi
call _Z14readMatrixFromP8_IO_FILE
movq %rax, %rbx
movq stdin(%rip), %rdi
call _Z14readMatrixFromP8_IO_FILE
movq %rax, %rdx
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _Z21readMatricesFromStdinv, .-_Z21readMatricesFromStdinv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]\n"
.align 8
.LC4:
.string "\nIf files are not passed, matrices are read from stdin.\n"
.align 8
.LC5:
.string "Input format: n-rows n-cols entries\n"
.align 8
.LC6:
.string "Output format: n-rows n-cols result-entries\n"
.section .rodata.str1.1
.LC7:
.string "Output is always to stdout\n"
.text
.globl _Z10printUsagev
.type _Z10printUsagev, @function
_Z10printUsagev:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z10printUsagev, .-_Z10printUsagev
.globl _Z16processUsingCuda5input
.type _Z16processUsingCuda5input, @function
_Z16processUsingCuda5input:
.LFB2067:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2067:
.size _Z16processUsingCuda5input, .-_Z16processUsingCuda5input
.globl _Z15processUsingCpu5input
.type _Z15processUsingCpu5input, @function
_Z15processUsingCpu5input:
.LFB2068:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2068:
.size _Z15processUsingCpu5input, .-_Z15processUsingCpu5input
.section .rodata.str1.8
.align 8
.LC8:
.string "Error: wrong number of arguments: %d\n"
.section .rodata.str1.1
.LC9:
.string "cuda"
.LC10:
.string "cpu"
.section .rodata.str1.8
.align 8
.LC11:
.string "Error: %s is not a valid form of computation\n"
.text
.globl main
.type main, @function
main:
.LFB2069:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
cmpl $2, %edi
je .L40
cmpl $4, %edi
jne .L37
movq 24(%rsi), %rsi
movq 16(%rbx), %rdi
call _Z21readMatricesFromFilesPcS_
.L36:
movq 8(%rbx), %rbx
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
je .L38
leaq .LC10(%rip), %rsi
movq %rbx, %rdi
call strcmp@PLT
testl %eax, %eax
je .L38
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10printUsagev
movl $2, %eax
jmp .L38
.L40:
call _Z21readMatricesFromStdinv
jmp .L36
.L37:
movl %edi, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z10printUsagev
movl $1, %eax
.L38:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2069:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix-multiply.hip"
.globl _Z17setMatrixPositionP6matrixjjf # -- Begin function _Z17setMatrixPositionP6matrixjjf
.p2align 4, 0x90
.type _Z17setMatrixPositionP6matrixjjf,@function
_Z17setMatrixPositionP6matrixjjf: # @_Z17setMatrixPositionP6matrixjjf
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
movq (%rdi), %rax
imull 12(%rdi), %esi
addl %edx, %esi
movss %xmm0, (%rax,%rsi,4)
retq
.Lfunc_end0:
.size _Z17setMatrixPositionP6matrixjjf, .Lfunc_end0-_Z17setMatrixPositionP6matrixjjf
.cfi_endproc
# -- End function
.globl _Z17getMatrixPositionP6matrixjj # -- Begin function _Z17getMatrixPositionP6matrixjj
.p2align 4, 0x90
.type _Z17getMatrixPositionP6matrixjj,@function
_Z17getMatrixPositionP6matrixjj: # @_Z17getMatrixPositionP6matrixjj
.cfi_startproc
# %bb.0:
# kill: def $esi killed $esi def $rsi
imull 12(%rdi), %esi
movq (%rdi), %rax
addl %edx, %esi
movss (%rax,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
retq
.Lfunc_end1:
.size _Z17getMatrixPositionP6matrixjj, .Lfunc_end1-_Z17getMatrixPositionP6matrixjj
.cfi_endproc
# -- End function
.globl _Z13setMatrixSizeP6matrixjj # -- Begin function _Z13setMatrixSizeP6matrixjj
.p2align 4, 0x90
.type _Z13setMatrixSizeP6matrixjj,@function
_Z13setMatrixSizeP6matrixjj: # @_Z13setMatrixSizeP6matrixjj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movl %edx, %edi
imull %esi, %edi
shlq $2, %rdi
callq malloc
movq %rax, (%r14)
movl %ebx, 12(%r14)
movl %ebp, 8(%r14)
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z13setMatrixSizeP6matrixjj, .Lfunc_end2-_Z13setMatrixSizeP6matrixjj
.cfi_endproc
# -- End function
.globl _Z9newMatrixv # -- Begin function _Z9newMatrixv
.p2align 4, 0x90
.type _Z9newMatrixv,@function
_Z9newMatrixv: # @_Z9newMatrixv
.cfi_startproc
# %bb.0:
movl $16, %edi
jmp malloc # TAILCALL
.Lfunc_end3:
.size _Z9newMatrixv, .Lfunc_end3-_Z9newMatrixv
.cfi_endproc
# -- End function
.globl _Z12deleteMatrixP6matrix # -- Begin function _Z12deleteMatrixP6matrix
.p2align 4, 0x90
.type _Z12deleteMatrixP6matrix,@function
_Z12deleteMatrixP6matrix: # @_Z12deleteMatrixP6matrix
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq %rdi, %rbx
movq (%rdi), %rdi
callq free
movq %rbx, %rdi
popq %rbx
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end4:
.size _Z12deleteMatrixP6matrix, .Lfunc_end4-_Z12deleteMatrixP6matrix
.cfi_endproc
# -- End function
.globl _Z14readMatrixFromP8_IO_FILE # -- Begin function _Z14readMatrixFromP8_IO_FILE
.p2align 4, 0x90
.type _Z14readMatrixFromP8_IO_FILE,@function
_Z14readMatrixFromP8_IO_FILE: # @_Z14readMatrixFromP8_IO_FILE
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movl $16, %edi
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdx
leaq 12(%rsp), %rcx
movl $.L.str, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
movl 16(%rsp), %ebp
movl 12(%rsp), %r12d
movl %r12d, %edi
imull %ebp, %edi
shlq $2, %rdi
callq malloc
movq %rax, (%r14)
movq %r12, 32(%rsp) # 8-byte Spill
movl %r12d, 12(%r14)
movq %r14, 24(%rsp) # 8-byte Spill
movl %ebp, 8(%r14)
cmpl $0, 16(%rsp)
je .LBB5_6
# %bb.1: # %.preheader.preheader
movq %rax, %r15
leaq 20(%rsp), %r12
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # %._crit_edge
# in Loop: Header=BB5_2 Depth=1
incl %r14d
addq 32(%rsp), %rbp # 8-byte Folded Reload
cmpl 16(%rsp), %r14d
jae .LBB5_6
.LBB5_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
cmpl $0, 12(%rsp)
je .LBB5_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB5_2 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.1, %esi
movq %rbx, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
leal (%rbp,%r13), %eax
movss %xmm0, (%r15,%rax,4)
incq %r13
movl 12(%rsp), %eax
cmpq %rax, %r13
jb .LBB5_4
jmp .LBB5_5
.LBB5_6: # %._crit_edge13
movq 24(%rsp), %rax # 8-byte Reload
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z14readMatrixFromP8_IO_FILE, .Lfunc_end5-_Z14readMatrixFromP8_IO_FILE
.cfi_endproc
# -- End function
.globl _Z11deleteInput5input # -- Begin function _Z11deleteInput5input
.p2align 4, 0x90
.type _Z11deleteInput5input,@function
_Z11deleteInput5input: # @_Z11deleteInput5input
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
movq (%rdi), %rdi
callq free
movq %r14, %rdi
callq free
movq (%rbx), %rdi
callq free
movq %rbx, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp free # TAILCALL
.Lfunc_end6:
.size _Z11deleteInput5input, .Lfunc_end6-_Z11deleteInput5input
.cfi_endproc
# -- End function
.globl _Z21readMatricesFromFilesPcS_ # -- Begin function _Z21readMatricesFromFilesPcS_
.p2align 4, 0x90
.type _Z21readMatricesFromFilesPcS_,@function
_Z21readMatricesFromFilesPcS_: # @_Z21readMatricesFromFilesPcS_
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
movq %rax, %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %rax, %r15
movq %r14, %rdi
callq fclose
movl $.L.str.2, %esi
movq %rbx, %rdi
callq fopen
movq %rax, %rbx
movq %rax, %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %rax, %r14
movq %rbx, %rdi
callq fclose
movq %r15, %rax
movq %r14, %rdx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z21readMatricesFromFilesPcS_, .Lfunc_end7-_Z21readMatricesFromFilesPcS_
.cfi_endproc
# -- End function
.globl _Z21readMatricesFromStdinv # -- Begin function _Z21readMatricesFromStdinv
.p2align 4, 0x90
.type _Z21readMatricesFromStdinv,@function
_Z21readMatricesFromStdinv: # @_Z21readMatricesFromStdinv
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movq stdin(%rip), %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %rax, %rbx
movq stdin(%rip), %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %rax, %rdx
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z21readMatricesFromStdinv, .Lfunc_end8-_Z21readMatricesFromStdinv
.cfi_endproc
# -- End function
.globl _Z10printUsagev # -- Begin function _Z10printUsagev
.p2align 4, 0x90
.type _Z10printUsagev,@function
_Z10printUsagev: # @_Z10printUsagev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end9:
.size _Z10printUsagev, .Lfunc_end9-_Z10printUsagev
.cfi_endproc
# -- End function
.globl _Z16processUsingCuda5input # -- Begin function _Z16processUsingCuda5input
.p2align 4, 0x90
.type _Z16processUsingCuda5input,@function
_Z16processUsingCuda5input: # @_Z16processUsingCuda5input
.cfi_startproc
# %bb.0:
retq
.Lfunc_end10:
.size _Z16processUsingCuda5input, .Lfunc_end10-_Z16processUsingCuda5input
.cfi_endproc
# -- End function
.globl _Z15processUsingCpu5input # -- Begin function _Z15processUsingCpu5input
.p2align 4, 0x90
.type _Z15processUsingCpu5input,@function
_Z15processUsingCpu5input: # @_Z15processUsingCpu5input
.cfi_startproc
# %bb.0:
retq
.Lfunc_end11:
.size _Z15processUsingCpu5input, .Lfunc_end11-_Z15processUsingCpu5input
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
cmpl $4, %edi
je .LBB12_4
# %bb.1:
movl %edi, %esi
cmpl $2, %edi
jne .LBB12_3
# %bb.2:
movq stdin(%rip), %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq stdin(%rip), %rdi
callq _Z14readMatrixFromP8_IO_FILE
jmp .LBB12_5
.LBB12_4:
movq 16(%rbx), %rdi
movq 24(%rbx), %r14
movl $.L.str.2, %esi
callq fopen
movq %rax, %r15
movq %rax, %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %r15, %rdi
callq fclose
movl $.L.str.2, %esi
movq %r14, %rdi
callq fopen
movq %rax, %r14
movq %rax, %rdi
callq _Z14readMatrixFromP8_IO_FILE
movq %r14, %rdi
callq fclose
.LBB12_5:
movq 8(%rbx), %r14
movl $.L.str.9, %esi
movq %r14, %rdi
callq strcmp
xorl %ebx, %ebx
testl %eax, %eax
je .LBB12_9
# %bb.6:
movl $.L.str.10, %esi
movq %r14, %rdi
callq strcmp
testl %eax, %eax
je .LBB12_9
# %bb.7:
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl $2, %ebx
jmp .LBB12_8
.LBB12_3:
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movl $1, %ebx
.LBB12_8: # %.sink.split
movl $.Lstr, %edi
callq puts@PLT
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
.LBB12_9:
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end12:
.size main, .Lfunc_end12-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%u %u"
.size .L.str, 6
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%f"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Error: wrong number of arguments: %d\n"
.size .L.str.8, 38
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "cuda"
.size .L.str.9, 5
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "cpu"
.size .L.str.10, 4
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Error: %s is not a valid form of computation\n"
.size .L.str.11, 46
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: matrix-multiply <cuda|cpu> [file-with-matrix1 file-with-matrix2]"
.size .Lstr, 72
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nIf files are not passed, matrices are read from stdin."
.size .Lstr.1, 56
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Input format: n-rows n-cols entries"
.size .Lstr.2, 36
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Output format: n-rows n-cols result-entries"
.size .Lstr.3, 44
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Output is always to stdout"
.size .Lstr.4, 27
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void stream(float* dA, float* dB, float* dC, float alpha, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id] + alpha*dC[id];
}
}
extern "C" {
void LaunchStream(float* dA, float *dB, float* dC, float alpha, int N) {
stream<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, dC, alpha, N);
}
} | code for sm_80
Function : _Z6streamPfS_S_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FFMA R9, R4, c[0x0][0x178], R3 ; /* 0x00005e0004097a23 */
/* 0x004fca0000000003 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void stream(float* dA, float* dB, float* dC, float alpha, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id] + alpha*dC[id];
}
}
extern "C" {
void LaunchStream(float* dA, float *dB, float* dC, float alpha, int N) {
stream<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, dC, alpha, N);
}
} | .file "tmpxft_00070361_00000000-6_stream.kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi
.type _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi, @function
_Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6streamPfS_S_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi, .-_Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi
.globl _Z6streamPfS_S_fi
.type _Z6streamPfS_S_fi, @function
_Z6streamPfS_S_fi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6streamPfS_S_fi, .-_Z6streamPfS_S_fi
.globl LaunchStream
.type LaunchStream, @function
LaunchStream:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movss %xmm0, 12(%rsp)
movl %ecx, %ebx
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2siq %xmm3, %rax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %ecx
movss 12(%rsp), %xmm0
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi
jmp .L11
.cfi_endproc
.LFE2027:
.size LaunchStream, .-LaunchStream
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z6streamPfS_S_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6streamPfS_S_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void stream(float* dA, float* dB, float* dC, float alpha, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id] + alpha*dC[id];
}
}
extern "C" {
void LaunchStream(float* dA, float *dB, float* dC, float alpha, int N) {
stream<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, dC, alpha, N);
}
} | #include <hip/hip_runtime.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void stream(float* dA, float* dB, float* dC, float alpha, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id] + alpha*dC[id];
}
}
extern "C" {
void LaunchStream(float* dA, float *dB, float* dC, float alpha, int N) {
stream<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, dC, alpha, N);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void stream(float* dA, float* dB, float* dC, float alpha, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id] + alpha*dC[id];
}
}
extern "C" {
void LaunchStream(float* dA, float *dB, float* dC, float alpha, int N) {
stream<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, dC, alpha, N);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6streamPfS_S_fi
.globl _Z6streamPfS_S_fi
.p2align 8
.type _Z6streamPfS_S_fi,@function
_Z6streamPfS_S_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s0, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6streamPfS_S_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6streamPfS_S_fi, .Lfunc_end0-_Z6streamPfS_S_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6streamPfS_S_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6streamPfS_S_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#ifndef THREADS_PER_BLOCK
#define THREADS_PER_BLOCK 1024
#endif
__global__ void stream(float* dA, float* dB, float* dC, float alpha, int N) {
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < N) {
dA[id] = dB[id] + alpha*dC[id];
}
}
extern "C" {
void LaunchStream(float* dA, float *dB, float* dC, float alpha, int N) {
stream<<<ceil(((float)N)/THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dA, dB, dC, alpha, N);
}
} | .text
.file "stream.kernel.hip"
.globl _Z21__device_stub__streamPfS_S_fi # -- Begin function _Z21__device_stub__streamPfS_S_fi
.p2align 4, 0x90
.type _Z21__device_stub__streamPfS_S_fi,@function
_Z21__device_stub__streamPfS_S_fi: # @_Z21__device_stub__streamPfS_S_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6streamPfS_S_fi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__streamPfS_S_fi, .Lfunc_end0-_Z21__device_stub__streamPfS_S_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function LaunchStream
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl LaunchStream
.p2align 4, 0x90
.type LaunchStream,@function
LaunchStream: # @LaunchStream
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %rdx, %r14
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movq %rsi, %r15
movq %rdi, %r12
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
movl %ebx, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6streamPfS_S_fi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size LaunchStream, .Lfunc_end1-LaunchStream
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6streamPfS_S_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6streamPfS_S_fi,@object # @_Z6streamPfS_S_fi
.section .rodata,"a",@progbits
.globl _Z6streamPfS_S_fi
.p2align 3, 0x0
_Z6streamPfS_S_fi:
.quad _Z21__device_stub__streamPfS_S_fi
.size _Z6streamPfS_S_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6streamPfS_S_fi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__streamPfS_S_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6streamPfS_S_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6streamPfS_S_fi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FFMA R9, R4, c[0x0][0x178], R3 ; /* 0x00005e0004097a23 */
/* 0x004fca0000000003 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6streamPfS_S_fi
.globl _Z6streamPfS_S_fi
.p2align 8
.type _Z6streamPfS_S_fi,@function
_Z6streamPfS_S_fi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, s0, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6streamPfS_S_fi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6streamPfS_S_fi, .Lfunc_end0-_Z6streamPfS_S_fi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6streamPfS_S_fi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6streamPfS_S_fi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00070361_00000000-6_stream.kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi
.type _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi, @function
_Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6streamPfS_S_fi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi, .-_Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi
.globl _Z6streamPfS_S_fi
.type _Z6streamPfS_S_fi, @function
_Z6streamPfS_S_fi:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6streamPfS_S_fi, .-_Z6streamPfS_S_fi
.globl LaunchStream
.type LaunchStream, @function
LaunchStream:
.LFB2027:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movss %xmm0, 12(%rsp)
movl %ecx, %ebx
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC4(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC1(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L12:
cvttss2siq %xmm3, %rax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl 44(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %ecx
movss 12(%rsp), %xmm0
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z31__device_stub__Z6streamPfS_S_fiPfS_S_fi
jmp .L11
.cfi_endproc
.LFE2027:
.size LaunchStream, .-LaunchStream
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "_Z6streamPfS_S_fi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6streamPfS_S_fi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 981467136
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "stream.kernel.hip"
.globl _Z21__device_stub__streamPfS_S_fi # -- Begin function _Z21__device_stub__streamPfS_S_fi
.p2align 4, 0x90
.type _Z21__device_stub__streamPfS_S_fi,@function
_Z21__device_stub__streamPfS_S_fi: # @_Z21__device_stub__streamPfS_S_fi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6streamPfS_S_fi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__streamPfS_S_fi, .Lfunc_end0-_Z21__device_stub__streamPfS_S_fi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function LaunchStream
.LCPI1_0:
.long 0x3a800000 # float 9.765625E-4
.text
.globl LaunchStream
.p2align 4, 0x90
.type LaunchStream,@function
LaunchStream: # @LaunchStream
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movss %xmm0, 12(%rsp) # 4-byte Spill
movq %rdx, %r14
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movq %rsi, %r15
movq %rdi, %r12
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 20(%rsp)
movl %ebx, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6streamPfS_S_fi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size LaunchStream, .Lfunc_end1-LaunchStream
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6streamPfS_S_fi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6streamPfS_S_fi,@object # @_Z6streamPfS_S_fi
.section .rodata,"a",@progbits
.globl _Z6streamPfS_S_fi
.p2align 3, 0x0
_Z6streamPfS_S_fi:
.quad _Z21__device_stub__streamPfS_S_fi
.size _Z6streamPfS_S_fi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6streamPfS_S_fi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__streamPfS_S_fi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6streamPfS_S_fi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <vector>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
#define CUDA_CALL( call ) \
{ \
cudaError_t err = call; \
if ( cudaSuccess != err) \
fprintf(stderr, "CUDA error for %s in %d of %s : %s.\n", #call , __LINE__ , __FILE__ ,cudaGetErrorString(err));\
}
__global__ void printLinearVector_GPU(size_t* x, size_t i, size_t num_rows, size_t num_cols)
{
for ( int j = 0 ; j < num_cols ; j++ )
printf("%lu ", x[j+i*num_cols]);
printf("\n");
}
__host__ void printLinearVector(size_t* x, size_t num_rows, size_t num_cols)
{
for(int i = 0 ; i < num_rows ; i++ )
{
printLinearVector_GPU<<<1,1>>>(x, i, num_rows, num_cols);
cudaDeviceSynchronize();
}
}
// Determines 1-dimensional CUDA block and grid sizes based on the number of rows N
__host__
void calculateDimensions(size_t N, dim3 &gridDim, dim3 &blockDim)
{
if ( N <= 1024 )
{
blockDim.x = 1024; blockDim.y = 1; blockDim.z = 1;
gridDim.x = 1; gridDim.y = 1; gridDim.z = 1;
}
else
{
blockDim.x = 1024; blockDim.y = 1; blockDim.z = 1;
gridDim.x = (int)ceil(N/blockDim.x)+1; gridDim.y = 1; gridDim.z = 1;
}
}
/// r = A^T * x
/// NOTE: This kernel should be run with A's number of rows as the number of threads
__global__
void ApplyTransposed_GPU_(
const std::size_t num_rows,
const std::size_t max_row_size,
const double* value,
const std::size_t* index,
const double* x,
double* r)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
{
for ( int n = 0; n < max_row_size; n++ )
{
int col = index [ id + n*num_rows ];
double val = value [ id + n*num_rows ];
atomicAdd( &r[col], val*x[id] );
}
}
}
// Ax = r
__global__ void Apply_GPU_ (
const std::size_t num_rows,
const std::size_t max_row_size,
const double* value,
const std::size_t* index,
const double* x,
double* r)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
{
double sum = 0;
for ( int n = 0 ; n < max_row_size; n++ )
{
unsigned int offset = id + n*num_rows;
sum += value[offset] * x[index[offset]];
}
r[id] = sum;
}
}
__global__
void printVector_GPU(double* x, size_t num_rows)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
printf("%d %e\n", id, x[id]);
}
// returns value of a transposed ELLPack matrix A at (row,col)
__device__
double valueAt_(size_t row, size_t col, double* vValue, size_t* vIndex, size_t max_row_size, size_t num_rows)
{
for(size_t k = 0; k < max_row_size; ++k)
{
if(vIndex[k * num_rows + row] == col)
return vValue[k * num_rows + row];
}
return 0.0;
}
__global__
void printELL_GPU_(double* value, size_t* index, size_t max_row_size, size_t num_rows, size_t num_cols)
{
for ( int i = 0 ; i < num_rows ; i++)
{
for ( int j = 0 ; j < num_cols ; j++)
printf("%f ", valueAt_(i, j, value, index, max_row_size, num_rows) );
printf("\n");
}
}
// adds the value to a transposed ELLPack matrix A at (row,col)
__device__
void atomicAddAt_( size_t row, size_t col, double* vValue, size_t* vIndex, size_t max_row_size, size_t num_rows, double value )
{
for(size_t k = 0; k < max_row_size; ++k)
{
// printf("%d\n", (k * num_rows + y) );
if(vIndex[k * num_rows + col] == row)
{
atomicAdd( &vValue[k * num_rows + col] , value );
// vValue[k * num_rows + col] += value;
// printf("%f \n", vValue[k * num_rows + y]);
k = max_row_size; // to exit for loop
}
}
}
// A_coarse = R * A_fine * P
__global__ void PTAP( double* value, size_t* index, size_t max_row_size, size_t num_rows,
double* value_, size_t* index_, size_t max_row_size_, size_t num_rows_,
double* p_value, size_t* p_index, size_t p_max_row_size,
size_t lev)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if( id < num_rows )
{
for ( int i_ = 0 ; i_ < p_max_row_size ; i_++ )
{
size_t i = p_index[id + i_*num_rows];
double P_ki = p_value[id + i_*num_rows];
if(id==0) printf("i = %lu, P_ki = %f\n", i, P_ki);
// if ( id == 1) printf("%f\n", P_ki);
for( int l_ = 0 ; l_ < max_row_size ; l_++ )
{
size_t l = index[id + l_*num_rows];
double A_kl = value[id + l_*num_rows];
double P_ki_A_kl = P_ki * A_kl;
if(id==0) printf("l = %lu, A_kl = %f\n", l, A_kl);
if(id==0) printf("P_ki_A_kl = %f\n", P_ki_A_kl);
for( int j_ = 0 ; j_ < p_max_row_size ; j_++ )
{
size_t j = p_index[l + j_*num_rows];
if( j >= num_rows ) break;
double P_lj = p_value[l + j_*num_rows];
if(id==0) printf("j = %lu, P_lj = %f\n", j, P_lj);
double P_ki_A_kl_P_lj = P_ki_A_kl * P_lj;
if(id==0) printf("PAP(%lu,%lu) = %f\n", i,j,P_ki_A_kl_P_lj);
if(P_ki_A_kl_P_lj != 0.0)
atomicAddAt_( j, i, value_, index_, max_row_size_, num_rows_, P_ki_A_kl_P_lj );
}
}
}
// atomicAddAt_( 0, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 0, 2, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 1, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 2, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 1, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 2, value_, index_, max_row_size_, num_rows_, 10 );
}
}
// Au = b
int main()
{
size_t N = 100;
// A matrix
vector<double> A_value( N, 1);
vector<size_t> A_index( N );
size_t mrs = 1;
for ( int i = 0 ; i < N ; i++ )
A_index[i] = i;
double* d_A_value;
size_t* d_A_index;
CUDA_CALL( cudaMalloc((void**)&d_A_value, sizeof(double) * N ) );
CUDA_CALL( cudaMalloc((void**)&d_A_index, sizeof(size_t) * N ) );
CUDA_CALL( cudaMemcpy(d_A_value, &A_value[0], sizeof(double) * N, cudaMemcpyHostToDevice) );
CUDA_CALL( cudaMemcpy(d_A_index, &A_index[0], sizeof(size_t) * N, cudaMemcpyHostToDevice) );
// vectors
vector<double> u(N,1);
double* d_b;
double* d_u;
CUDA_CALL( cudaMalloc((void**)&d_b, sizeof(double) * N ) );
CUDA_CALL( cudaMalloc((void**)&d_u, sizeof(double) * N ) );
CUDA_CALL( cudaMemcpy(d_u, &u[0], sizeof(double) * N, cudaMemcpyHostToDevice) );
// b = (A^T) * u
ApplyTransposed_GPU_<<<1,N>>>( N, mrs, d_A_value, d_A_index, d_u, d_b );
cudaDeviceSynchronize();
printVector_GPU<<<1,N>>>( d_b, N );
cudaDeviceSynchronize();
}
// // size_t R_mrs = 2;
// // size_t A_mrs = 2;
// // size_t P_mrs = 2;
// // vector<double> A_value_ = { 1,1,1,2,2,2,3,3,3};
// vector<size_t> A_index_ = { 0,0,0,1,1,1,2,2,2};
// vector<double> R_value = { 1, 3, 2, 2, 1, 4};
// vector<size_t> R_index = { 0, 3, 1, 2, 1, 3};
// vector<double> P_value = { 1, 2, 2, 3, 0, 1, 0, 4};
// vector<size_t> P_index = { 0,1,1,0,3,2,3,2};
// // vector<double> A_value = { 1, 5, 1, 2, 2, 1, 1, 0};
// // vector<size_t> A_index = { 0, 2, 1, 3, 1, 2, 3, 4};
// // vector<double> P_value = { 1, 0, 2, 1, 2, 0, 3, 4};
// // vector<size_t> P_index = { 0, 3, 1, 2, 1, 3, 0, 2};
// double* d_A_value;
// double* d_A_value_;
// double* d_R_value;
// double* d_P_value;
// size_t* d_A_index;
// size_t* d_A_index_;
// size_t* d_R_index;
// size_t* d_P_index;
// CUDA_CALL( cudaMalloc((void**)&d_A_value, sizeof(double) * num_rows[1] * A_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_value_, sizeof(double) * num_rows[0] * num_rows[0] ) );
// CUDA_CALL( cudaMalloc((void**)&d_R_value, sizeof(double) * num_rows[0] * R_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_P_value, sizeof(double) * num_rows[1] * P_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_index, sizeof(size_t) * num_rows[1] * A_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_index_, sizeof(size_t) * num_rows[0] * num_rows[0] ) );
// CUDA_CALL( cudaMalloc((void**)&d_R_index, sizeof(size_t) * num_rows[0] * R_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_P_index, sizeof(size_t) * num_rows[1] * P_mrs ) );
// CUDA_CALL( cudaMemcpy(d_A_value, &A_value[0], sizeof(double) * num_rows[1] * A_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_value_, &A_value_[0], sizeof(double) * num_rows[0] * num_rows[0], cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_R_value, &R_value[0], sizeof(double) * num_rows[0] * R_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_P_value, &P_value[0], sizeof(double) * num_rows[1] * P_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_index, &A_index[0], sizeof(size_t) * num_rows[1] * A_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_index_, &A_index_[0], sizeof(size_t) * num_rows[0] * num_rows[0], cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_R_index, &R_index[0], sizeof(size_t) * num_rows[0] * R_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_P_index, &P_index[0], sizeof(size_t) * num_rows[1] * P_mrs, cudaMemcpyHostToDevice) );
// PTAP<<<1,4>>>(d_A_value, d_A_index, A_mrs, num_rows[1], d_A_value_, d_A_index_, 3, num_rows[0], d_P_value, d_P_index, P_mrs, 0);
// cudaDeviceSynchronize();
// // printELL_GPU_<<<1,1>>>(d_A_value, d_A_index, A_mrs, num_rows[1], num_rows[1]);
// // printELL_GPU_<<<1,1>>>(d_A_value_, d_A_index_, 3, num_rows[0], num_rows[0]);
// // printELL_GPU_<<<1,1>>>(d_P_value, d_P_index, P_mrs, num_rows[1], num_rows[0]);
// // printLinearVector(d_A_index_, 3, 3);
// cudaDeviceSynchronize(); | .file "tmpxft_00077a02_00000000-6_bb.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4039:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4039:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z19calculateDimensionsmR4dim3S0_
.type _Z19calculateDimensionsmR4dim3S0_, @function
_Z19calculateDimensionsmR4dim3S0_:
.LFB4033:
.cfi_startproc
endbr64
movl $1, %eax
cmpq $1024, %rdi
jbe .L4
shrq $10, %rdi
pxor %xmm0, %xmm0
cvtsi2sdq %rdi, %xmm0
cvttsd2sil %xmm0, %eax
addl $1, %eax
.L4:
movl $1024, (%rdx)
movl $1, 4(%rdx)
movl $1, 8(%rdx)
movl %eax, (%rsi)
movl $1, 4(%rsi)
movl $1, 8(%rsi)
ret
.cfi_endproc
.LFE4033:
.size _Z19calculateDimensionsmR4dim3S0_, .-_Z19calculateDimensionsmR4dim3S0_
.globl _Z8valueAt_mmPdPmmm
.type _Z8valueAt_mmPdPmmm, @function
_Z8valueAt_mmPdPmmm:
.LFB4034:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4034:
.size _Z8valueAt_mmPdPmmm, .-_Z8valueAt_mmPdPmmm
.globl _Z12atomicAddAt_mmPdPmmmd
.type _Z12atomicAddAt_mmPdPmmmd, @function
_Z12atomicAddAt_mmPdPmmmd:
.LFB4035:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4035:
.size _Z12atomicAddAt_mmPdPmmmd, .-_Z12atomicAddAt_mmPdPmmmd
.globl _Z44__device_stub__Z21printLinearVector_GPUPmmmmPmmmm
.type _Z44__device_stub__Z21printLinearVector_GPUPmmmmPmmmm, @function
_Z44__device_stub__Z21printLinearVector_GPUPmmmmPmmmm:
.LFB4061:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21printLinearVector_GPUPmmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4061:
.size _Z44__device_stub__Z21printLinearVector_GPUPmmmmPmmmm, .-_Z44__device_stub__Z21printLinearVector_GPUPmmmmPmmmm
.globl _Z21printLinearVector_GPUPmmmm
.type _Z21printLinearVector_GPUPmmmm, @function
_Z21printLinearVector_GPUPmmmm:
.LFB4062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z21printLinearVector_GPUPmmmmPmmmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4062:
.size _Z21printLinearVector_GPUPmmmm, .-_Z21printLinearVector_GPUPmmmm
.globl _Z17printLinearVectorPmmm
.type _Z17printLinearVectorPmmm, @function
_Z17printLinearVectorPmmm:
.LFB4032:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L26
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movq %rsi, %rbp
movq %rdx, %r13
movl $0, %ebx
jmp .L23
.L22:
call cudaDeviceSynchronize@PLT
addq $1, %rbx
cmpq %rbx, %rbp
je .L29
.L23:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L22
movq %r13, %rcx
movq %rbp, %rdx
movq %rbx, %rsi
movq %r12, %rdi
call _Z44__device_stub__Z21printLinearVector_GPUPmmmmPmmmm
jmp .L22
.L29:
addq $40, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
ret
.cfi_endproc
.LFE4032:
.size _Z17printLinearVectorPmmm, .-_Z17printLinearVectorPmmm
.globl _Z51__device_stub__Z20ApplyTransposed_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd
.type _Z51__device_stub__Z20ApplyTransposed_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd, @function
_Z51__device_stub__Z20ApplyTransposed_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd:
.LFB4063:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4063:
.size _Z51__device_stub__Z20ApplyTransposed_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd, .-_Z51__device_stub__Z20ApplyTransposed_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd
.globl _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd
.type _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd, @function
_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd:
.LFB4064:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z51__device_stub__Z20ApplyTransposed_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4064:
.size _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd, .-_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd
.globl _Z41__device_stub__Z10Apply_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd
.type _Z41__device_stub__Z10Apply_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd, @function
_Z41__device_stub__Z10Apply_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd:
.LFB4065:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L42
.L38:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L43
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L42:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10Apply_GPU_mmPKdPKmS0_Pd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L38
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4065:
.size _Z41__device_stub__Z10Apply_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd, .-_Z41__device_stub__Z10Apply_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd
.globl _Z10Apply_GPU_mmPKdPKmS0_Pd
.type _Z10Apply_GPU_mmPKdPKmS0_Pd, @function
_Z10Apply_GPU_mmPKdPKmS0_Pd:
.LFB4066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z10Apply_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4066:
.size _Z10Apply_GPU_mmPKdPKmS0_Pd, .-_Z10Apply_GPU_mmPKdPKmS0_Pd
.globl _Z36__device_stub__Z15printVector_GPUPdmPdm
.type _Z36__device_stub__Z15printVector_GPUPdmPdm, @function
_Z36__device_stub__Z15printVector_GPUPdmPdm:
.LFB4067:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L50
.L46:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L51
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z15printVector_GPUPdm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L46
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4067:
.size _Z36__device_stub__Z15printVector_GPUPdmPdm, .-_Z36__device_stub__Z15printVector_GPUPdmPdm
.globl _Z15printVector_GPUPdm
.type _Z15printVector_GPUPdm, @function
_Z15printVector_GPUPdm:
.LFB4068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z15printVector_GPUPdmPdm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4068:
.size _Z15printVector_GPUPdm, .-_Z15printVector_GPUPdm
.globl _Z38__device_stub__Z13printELL_GPU_PdPmmmmPdPmmmm
.type _Z38__device_stub__Z13printELL_GPU_PdPmmmmPdPmmmm, @function
_Z38__device_stub__Z13printELL_GPU_PdPmmmmPdPmmmm:
.LFB4069:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L58
.L54:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13printELL_GPU_PdPmmmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L54
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4069:
.size _Z38__device_stub__Z13printELL_GPU_PdPmmmmPdPmmmm, .-_Z38__device_stub__Z13printELL_GPU_PdPmmmmPdPmmmm
.globl _Z13printELL_GPU_PdPmmmm
.type _Z13printELL_GPU_PdPmmmm, @function
_Z13printELL_GPU_PdPmmmm:
.LFB4070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13printELL_GPU_PdPmmmmPdPmmmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4070:
.size _Z13printELL_GPU_PdPmmmm, .-_Z13printELL_GPU_PdPmmmm
.globl _Z41__device_stub__Z4PTAPPdPmmmS_S0_mmS_S0_mmPdPmmmS_S0_mmS_S0_mm
.type _Z41__device_stub__Z4PTAPPdPmmmS_S0_mmS_S0_mmPdPmmmS_S0_mmS_S0_mm, @function
_Z41__device_stub__Z4PTAPPdPmmmS_S0_mmS_S0_mmPdPmmmS_S0_mmS_S0_mm:
.LFB4071:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movq 272(%rsp), %rax
movq %rax, 8(%rsp)
movq 280(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 256(%rsp), %rax
movq %rax, 176(%rsp)
leaq 264(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 296(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L66
.L62:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L67
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L66:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z4PTAPPdPmmmS_S0_mmS_S0_mm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L62
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4071:
.size _Z41__device_stub__Z4PTAPPdPmmmS_S0_mmS_S0_mmPdPmmmS_S0_mmS_S0_mm, .-_Z41__device_stub__Z4PTAPPdPmmmS_S0_mmS_S0_mmPdPmmmS_S0_mmS_S0_mm
.globl _Z4PTAPPdPmmmS_S0_mmS_S0_mm
.type _Z4PTAPPdPmmmS_S0_mmS_S0_mm, @function
_Z4PTAPPdPmmmS_S0_mmS_S0_mm:
.LFB4072:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 56(%rsp)
.cfi_def_cfa_offset 24
pushq 56(%rsp)
.cfi_def_cfa_offset 32
pushq 56(%rsp)
.cfi_def_cfa_offset 40
pushq 56(%rsp)
.cfi_def_cfa_offset 48
pushq 56(%rsp)
.cfi_def_cfa_offset 56
pushq 56(%rsp)
.cfi_def_cfa_offset 64
call _Z41__device_stub__Z4PTAPPdPmmmS_S0_mmS_S0_mmPdPmmmS_S0_mmS_S0_mm
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4072:
.size _Z4PTAPPdPmmmS_S0_mmS_S0_mm, .-_Z4PTAPPdPmmmS_S0_mmS_S0_mm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4PTAPPdPmmmS_S0_mmS_S0_mm"
.LC1:
.string "_Z13printELL_GPU_PdPmmmm"
.LC2:
.string "_Z15printVector_GPUPdm"
.LC3:
.string "_Z10Apply_GPU_mmPKdPKmS0_Pd"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd"
.align 8
.LC5:
.string "_Z21printLinearVector_GPUPmmmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4074:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4PTAPPdPmmmS_S0_mmS_S0_mm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13printELL_GPU_PdPmmmm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15printVector_GPUPdm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10Apply_GPU_mmPKdPKmS0_Pd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z21printLinearVector_GPUPmmmm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4074:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorIdSaIdEED2Ev,"axG",@progbits,_ZNSt6vectorIdSaIdEED5Ev,comdat
.align 2
.weak _ZNSt6vectorIdSaIdEED2Ev
.type _ZNSt6vectorIdSaIdEED2Ev, @function
_ZNSt6vectorIdSaIdEED2Ev:
.LFB4385:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L75
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L75:
ret
.cfi_endproc
.LFE4385:
.size _ZNSt6vectorIdSaIdEED2Ev, .-_ZNSt6vectorIdSaIdEED2Ev
.weak _ZNSt6vectorIdSaIdEED1Ev
.set _ZNSt6vectorIdSaIdEED1Ev,_ZNSt6vectorIdSaIdEED2Ev
.section .text._ZNSt6vectorImSaImEED2Ev,"axG",@progbits,_ZNSt6vectorImSaImEED5Ev,comdat
.align 2
.weak _ZNSt6vectorImSaImEED2Ev
.type _ZNSt6vectorImSaImEED2Ev, @function
_ZNSt6vectorImSaImEED2Ev:
.LFB4397:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L81
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L81:
ret
.cfi_endproc
.LFE4397:
.size _ZNSt6vectorImSaImEED2Ev, .-_ZNSt6vectorImSaImEED2Ev
.weak _ZNSt6vectorImSaImEED1Ev
.set _ZNSt6vectorImSaImEED1Ev,_ZNSt6vectorImSaImEED2Ev
.section .rodata.str1.8
.align 8
.LC7:
.string "/home/ubuntu/Datasets/stackv2/train-structured/edofersan/tdo/master/Debug/bb.cu"
.align 8
.LC8:
.string "cudaMalloc((void**)&d_A_value, sizeof(double) * N )"
.align 8
.LC9:
.string "CUDA error for %s in %d of %s : %s.\n"
.align 8
.LC10:
.string "cudaMalloc((void**)&d_A_index, sizeof(size_t) * N )"
.align 8
.LC11:
.string "cudaMemcpy(d_A_value, &A_value[0], sizeof(double) * N, cudaMemcpyHostToDevice)"
.align 8
.LC12:
.string "cudaMemcpy(d_A_index, &A_index[0], sizeof(size_t) * N, cudaMemcpyHostToDevice)"
.align 8
.LC13:
.string "cudaMalloc((void**)&d_b, sizeof(double) * N )"
.align 8
.LC14:
.string "cudaMalloc((void**)&d_u, sizeof(double) * N )"
.align 8
.LC15:
.string "cudaMemcpy(d_u, &u[0], sizeof(double) * N, cudaMemcpyHostToDevice)"
.text
.globl main
.type main, @function
main:
.LFB4036:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4036
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %rbx
subq $160, %rsp
.cfi_offset 14, -24
.cfi_offset 3, -32
movq %fs:40, %rax
movq %rax, -24(%rbp)
xorl %eax, %eax
movl $800, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %r14
movq %rax, -112(%rbp)
leaq 800(%rax), %rdx
movq %rdx, -96(%rbp)
movsd .LC6(%rip), %xmm0
.L85:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L85
movq %rdx, -104(%rbp)
movq $0, -72(%rbp)
movq $0, -64(%rbp)
movl $800, %edi
.LEHB1:
call _Znwm@PLT
.LEHE1:
movq %rax, %rbx
movq %rax, -80(%rbp)
leaq 800(%rax), %rdx
movq %rdx, -64(%rbp)
movq $0, (%rax)
leaq 8(%rax), %rax
.L86:
movq $0, (%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L86
movq %rdx, -72(%rbp)
movl $0, %eax
.L87:
movq %rax, (%rbx,%rax,8)
addq $1, %rax
cmpq $100, %rax
jne .L87
leaq -168(%rbp), %rdi
movl $800, %esi
.LEHB2:
call cudaMalloc@PLT
testl %eax, %eax
je .L88
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC7(%rip), %r9
movl $231, %r8d
leaq .LC8(%rip), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L88:
leaq -160(%rbp), %rdi
movl $800, %esi
.cfi_escape 0x2e,0
call cudaMalloc@PLT
testl %eax, %eax
je .L89
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC7(%rip), %r9
movl $232, %r8d
leaq .LC10(%rip), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L89:
movl $1, %ecx
movl $800, %edx
movq %r14, %rsi
movq -168(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaMemcpy@PLT
testl %eax, %eax
je .L90
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC7(%rip), %r9
movl $233, %r8d
leaq .LC11(%rip), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L90:
movl $1, %ecx
movl $800, %edx
movq %rbx, %rsi
movq -160(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaMemcpy@PLT
testl %eax, %eax
je .L91
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC7(%rip), %r9
movl $234, %r8d
leaq .LC12(%rip), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L91:
movq $0, -40(%rbp)
movq $0, -32(%rbp)
movl $800, %edi
.cfi_escape 0x2e,0
call _Znwm@PLT
.LEHE2:
movq %rax, %rbx
movq %rax, -48(%rbp)
leaq 800(%rax), %rdx
movq %rdx, -32(%rbp)
movsd .LC6(%rip), %xmm0
.L92:
movsd %xmm0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L92
movq %rdx, -40(%rbp)
leaq -152(%rbp), %rdi
movl $800, %esi
.LEHB3:
call cudaMalloc@PLT
testl %eax, %eax
je .L93
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC7(%rip), %r9
movl $242, %r8d
leaq .LC13(%rip), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L93:
leaq -144(%rbp), %rdi
movl $800, %esi
.cfi_escape 0x2e,0
call cudaMalloc@PLT
testl %eax, %eax
je .L94
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC7(%rip), %r9
movl $243, %r8d
leaq .LC14(%rip), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L94:
movl $1, %ecx
movl $800, %edx
movq %rbx, %rsi
movq -144(%rbp), %rdi
.cfi_escape 0x2e,0
call cudaMemcpy@PLT
testl %eax, %eax
je .L95
movl %eax, %edi
call cudaGetErrorString@PLT
subq $8, %rsp
pushq %rax
leaq .LC7(%rip), %r9
movl $244, %r8d
leaq .LC15(%rip), %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.cfi_escape 0x2e,0x10
call __fprintf_chk@PLT
addq $16, %rsp
.L95:
movl $100, -124(%rbp)
movl $1, -120(%rbp)
movl $1, -116(%rbp)
movl $1, -136(%rbp)
movl $1, -132(%rbp)
movl $1, -128(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -124(%rbp), %rdx
movl $1, %ecx
movq -136(%rbp), %rdi
movl $1, %esi
.cfi_escape 0x2e,0
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L96
movq -152(%rbp), %r9
movq -144(%rbp), %r8
movq -160(%rbp), %rcx
movq -168(%rbp), %rdx
movl $1, %esi
movl $100, %edi
call _Z51__device_stub__Z20ApplyTransposed_GPU_mmPKdPKmS0_PdmmPKdPKmS0_Pd
.L96:
call cudaDeviceSynchronize@PLT
movl $100, -124(%rbp)
movl $1, -120(%rbp)
movl $1, -116(%rbp)
movl $1, -136(%rbp)
movl $1, -132(%rbp)
movl $1, -128(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -124(%rbp), %rdx
movl $1, %ecx
movq -136(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L97
movl $100, %esi
movq -152(%rbp), %rdi
call _Z36__device_stub__Z15printVector_GPUPdmPdm
.L97:
call cudaDeviceSynchronize@PLT
.LEHE3:
leaq -48(%rbp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
leaq -80(%rbp), %rdi
call _ZNSt6vectorImSaImEED1Ev
leaq -112(%rbp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq -24(%rbp), %rax
subq %fs:40, %rax
jne .L112
movl $0, %eax
leaq -16(%rbp), %rsp
popq %rbx
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L105:
.cfi_restore_state
endbr64
movq %rax, %rbx
leaq -48(%rbp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
.L99:
leaq -80(%rbp), %rdi
call _ZNSt6vectorImSaImEED1Ev
.L100:
leaq -112(%rbp), %rdi
call _ZNSt6vectorIdSaIdEED1Ev
movq -24(%rbp), %rax
subq %fs:40, %rax
je .L101
call __stack_chk_fail@PLT
.L104:
endbr64
movq %rax, %rbx
jmp .L99
.L103:
endbr64
movq %rax, %rbx
jmp .L100
.L101:
movq %rbx, %rdi
.LEHB4:
call _Unwind_Resume@PLT
.LEHE4:
.L112:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4036:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4036:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4036-.LLSDACSB4036
.LLSDACSB4036:
.uleb128 .LEHB0-.LFB4036
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4036
.uleb128 .LEHE1-.LEHB1
.uleb128 .L103-.LFB4036
.uleb128 0
.uleb128 .LEHB2-.LFB4036
.uleb128 .LEHE2-.LEHB2
.uleb128 .L104-.LFB4036
.uleb128 0
.uleb128 .LEHB3-.LFB4036
.uleb128 .LEHE3-.LEHB3
.uleb128 .L105-.LFB4036
.uleb128 0
.uleb128 .LEHB4-.LFB4036
.uleb128 .LEHE4-.LEHB4
.uleb128 0
.uleb128 0
.LLSDACSE4036:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1072693248
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
#define CUDA_CALL( call ) \
{ \
cudaError_t err = call; \
if ( cudaSuccess != err) \
fprintf(stderr, "CUDA error for %s in %d of %s : %s.\n", #call , __LINE__ , __FILE__ ,cudaGetErrorString(err));\
}
__global__ void printLinearVector_GPU(size_t* x, size_t i, size_t num_rows, size_t num_cols)
{
for ( int j = 0 ; j < num_cols ; j++ )
printf("%lu ", x[j+i*num_cols]);
printf("\n");
}
__host__ void printLinearVector(size_t* x, size_t num_rows, size_t num_cols)
{
for(int i = 0 ; i < num_rows ; i++ )
{
printLinearVector_GPU<<<1,1>>>(x, i, num_rows, num_cols);
cudaDeviceSynchronize();
}
}
// Determines 1-dimensional CUDA block and grid sizes based on the number of rows N
__host__
void calculateDimensions(size_t N, dim3 &gridDim, dim3 &blockDim)
{
if ( N <= 1024 )
{
blockDim.x = 1024; blockDim.y = 1; blockDim.z = 1;
gridDim.x = 1; gridDim.y = 1; gridDim.z = 1;
}
else
{
blockDim.x = 1024; blockDim.y = 1; blockDim.z = 1;
gridDim.x = (int)ceil(N/blockDim.x)+1; gridDim.y = 1; gridDim.z = 1;
}
}
/// r = A^T * x
/// NOTE: This kernel should be run with A's number of rows as the number of threads
__global__
void ApplyTransposed_GPU_(
const std::size_t num_rows,
const std::size_t max_row_size,
const double* value,
const std::size_t* index,
const double* x,
double* r)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
{
for ( int n = 0; n < max_row_size; n++ )
{
int col = index [ id + n*num_rows ];
double val = value [ id + n*num_rows ];
atomicAdd( &r[col], val*x[id] );
}
}
}
// Ax = r
__global__ void Apply_GPU_ (
const std::size_t num_rows,
const std::size_t max_row_size,
const double* value,
const std::size_t* index,
const double* x,
double* r)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
{
double sum = 0;
for ( int n = 0 ; n < max_row_size; n++ )
{
unsigned int offset = id + n*num_rows;
sum += value[offset] * x[index[offset]];
}
r[id] = sum;
}
}
__global__
void printVector_GPU(double* x, size_t num_rows)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
printf("%d %e\n", id, x[id]);
}
// returns value of a transposed ELLPack matrix A at (row,col)
__device__
double valueAt_(size_t row, size_t col, double* vValue, size_t* vIndex, size_t max_row_size, size_t num_rows)
{
for(size_t k = 0; k < max_row_size; ++k)
{
if(vIndex[k * num_rows + row] == col)
return vValue[k * num_rows + row];
}
return 0.0;
}
__global__
void printELL_GPU_(double* value, size_t* index, size_t max_row_size, size_t num_rows, size_t num_cols)
{
for ( int i = 0 ; i < num_rows ; i++)
{
for ( int j = 0 ; j < num_cols ; j++)
printf("%f ", valueAt_(i, j, value, index, max_row_size, num_rows) );
printf("\n");
}
}
// adds the value to a transposed ELLPack matrix A at (row,col)
__device__
void atomicAddAt_( size_t row, size_t col, double* vValue, size_t* vIndex, size_t max_row_size, size_t num_rows, double value )
{
for(size_t k = 0; k < max_row_size; ++k)
{
// printf("%d\n", (k * num_rows + y) );
if(vIndex[k * num_rows + col] == row)
{
atomicAdd( &vValue[k * num_rows + col] , value );
// vValue[k * num_rows + col] += value;
// printf("%f \n", vValue[k * num_rows + y]);
k = max_row_size; // to exit for loop
}
}
}
// A_coarse = R * A_fine * P
__global__ void PTAP( double* value, size_t* index, size_t max_row_size, size_t num_rows,
double* value_, size_t* index_, size_t max_row_size_, size_t num_rows_,
double* p_value, size_t* p_index, size_t p_max_row_size,
size_t lev)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if( id < num_rows )
{
for ( int i_ = 0 ; i_ < p_max_row_size ; i_++ )
{
size_t i = p_index[id + i_*num_rows];
double P_ki = p_value[id + i_*num_rows];
if(id==0) printf("i = %lu, P_ki = %f\n", i, P_ki);
// if ( id == 1) printf("%f\n", P_ki);
for( int l_ = 0 ; l_ < max_row_size ; l_++ )
{
size_t l = index[id + l_*num_rows];
double A_kl = value[id + l_*num_rows];
double P_ki_A_kl = P_ki * A_kl;
if(id==0) printf("l = %lu, A_kl = %f\n", l, A_kl);
if(id==0) printf("P_ki_A_kl = %f\n", P_ki_A_kl);
for( int j_ = 0 ; j_ < p_max_row_size ; j_++ )
{
size_t j = p_index[l + j_*num_rows];
if( j >= num_rows ) break;
double P_lj = p_value[l + j_*num_rows];
if(id==0) printf("j = %lu, P_lj = %f\n", j, P_lj);
double P_ki_A_kl_P_lj = P_ki_A_kl * P_lj;
if(id==0) printf("PAP(%lu,%lu) = %f\n", i,j,P_ki_A_kl_P_lj);
if(P_ki_A_kl_P_lj != 0.0)
atomicAddAt_( j, i, value_, index_, max_row_size_, num_rows_, P_ki_A_kl_P_lj );
}
}
}
// atomicAddAt_( 0, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 0, 2, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 1, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 2, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 1, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 2, value_, index_, max_row_size_, num_rows_, 10 );
}
}
// Au = b
int main()
{
size_t N = 100;
// A matrix
vector<double> A_value( N, 1);
vector<size_t> A_index( N );
size_t mrs = 1;
for ( int i = 0 ; i < N ; i++ )
A_index[i] = i;
double* d_A_value;
size_t* d_A_index;
CUDA_CALL( cudaMalloc((void**)&d_A_value, sizeof(double) * N ) );
CUDA_CALL( cudaMalloc((void**)&d_A_index, sizeof(size_t) * N ) );
CUDA_CALL( cudaMemcpy(d_A_value, &A_value[0], sizeof(double) * N, cudaMemcpyHostToDevice) );
CUDA_CALL( cudaMemcpy(d_A_index, &A_index[0], sizeof(size_t) * N, cudaMemcpyHostToDevice) );
// vectors
vector<double> u(N,1);
double* d_b;
double* d_u;
CUDA_CALL( cudaMalloc((void**)&d_b, sizeof(double) * N ) );
CUDA_CALL( cudaMalloc((void**)&d_u, sizeof(double) * N ) );
CUDA_CALL( cudaMemcpy(d_u, &u[0], sizeof(double) * N, cudaMemcpyHostToDevice) );
// b = (A^T) * u
ApplyTransposed_GPU_<<<1,N>>>( N, mrs, d_A_value, d_A_index, d_u, d_b );
cudaDeviceSynchronize();
printVector_GPU<<<1,N>>>( d_b, N );
cudaDeviceSynchronize();
}
// // size_t R_mrs = 2;
// // size_t A_mrs = 2;
// // size_t P_mrs = 2;
// // vector<double> A_value_ = { 1,1,1,2,2,2,3,3,3};
// vector<size_t> A_index_ = { 0,0,0,1,1,1,2,2,2};
// vector<double> R_value = { 1, 3, 2, 2, 1, 4};
// vector<size_t> R_index = { 0, 3, 1, 2, 1, 3};
// vector<double> P_value = { 1, 2, 2, 3, 0, 1, 0, 4};
// vector<size_t> P_index = { 0,1,1,0,3,2,3,2};
// // vector<double> A_value = { 1, 5, 1, 2, 2, 1, 1, 0};
// // vector<size_t> A_index = { 0, 2, 1, 3, 1, 2, 3, 4};
// // vector<double> P_value = { 1, 0, 2, 1, 2, 0, 3, 4};
// // vector<size_t> P_index = { 0, 3, 1, 2, 1, 3, 0, 2};
// double* d_A_value;
// double* d_A_value_;
// double* d_R_value;
// double* d_P_value;
// size_t* d_A_index;
// size_t* d_A_index_;
// size_t* d_R_index;
// size_t* d_P_index;
// CUDA_CALL( cudaMalloc((void**)&d_A_value, sizeof(double) * num_rows[1] * A_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_value_, sizeof(double) * num_rows[0] * num_rows[0] ) );
// CUDA_CALL( cudaMalloc((void**)&d_R_value, sizeof(double) * num_rows[0] * R_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_P_value, sizeof(double) * num_rows[1] * P_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_index, sizeof(size_t) * num_rows[1] * A_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_index_, sizeof(size_t) * num_rows[0] * num_rows[0] ) );
// CUDA_CALL( cudaMalloc((void**)&d_R_index, sizeof(size_t) * num_rows[0] * R_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_P_index, sizeof(size_t) * num_rows[1] * P_mrs ) );
// CUDA_CALL( cudaMemcpy(d_A_value, &A_value[0], sizeof(double) * num_rows[1] * A_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_value_, &A_value_[0], sizeof(double) * num_rows[0] * num_rows[0], cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_R_value, &R_value[0], sizeof(double) * num_rows[0] * R_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_P_value, &P_value[0], sizeof(double) * num_rows[1] * P_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_index, &A_index[0], sizeof(size_t) * num_rows[1] * A_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_index_, &A_index_[0], sizeof(size_t) * num_rows[0] * num_rows[0], cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_R_index, &R_index[0], sizeof(size_t) * num_rows[0] * R_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_P_index, &P_index[0], sizeof(size_t) * num_rows[1] * P_mrs, cudaMemcpyHostToDevice) );
// PTAP<<<1,4>>>(d_A_value, d_A_index, A_mrs, num_rows[1], d_A_value_, d_A_index_, 3, num_rows[0], d_P_value, d_P_index, P_mrs, 0);
// cudaDeviceSynchronize();
// // printELL_GPU_<<<1,1>>>(d_A_value, d_A_index, A_mrs, num_rows[1], num_rows[1]);
// // printELL_GPU_<<<1,1>>>(d_A_value_, d_A_index_, 3, num_rows[0], num_rows[0]);
// // printELL_GPU_<<<1,1>>>(d_P_value, d_P_index, P_mrs, num_rows[1], num_rows[0]);
// // printLinearVector(d_A_index_, 3, 3);
// cudaDeviceSynchronize(); | #include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
using namespace std;
#define CUDA_CALL( call ) \
{ \
hipError_t err = call; \
if ( hipSuccess != err) \
fprintf(stderr, "CUDA error for %s in %d of %s : %s.\n", #call , __LINE__ , __FILE__ ,hipGetErrorString(err));\
}
__global__ void printLinearVector_GPU(size_t* x, size_t i, size_t num_rows, size_t num_cols)
{
for ( int j = 0 ; j < num_cols ; j++ )
printf("%lu ", x[j+i*num_cols]);
printf("\n");
}
__host__ void printLinearVector(size_t* x, size_t num_rows, size_t num_cols)
{
for(int i = 0 ; i < num_rows ; i++ )
{
printLinearVector_GPU<<<1,1>>>(x, i, num_rows, num_cols);
hipDeviceSynchronize();
}
}
// Determines 1-dimensional CUDA block and grid sizes based on the number of rows N
__host__
void calculateDimensions(size_t N, dim3 &gridDim, dim3 &blockDim)
{
if ( N <= 1024 )
{
blockDim.x = 1024; blockDim.y = 1; blockDim.z = 1;
gridDim.x = 1; gridDim.y = 1; gridDim.z = 1;
}
else
{
blockDim.x = 1024; blockDim.y = 1; blockDim.z = 1;
gridDim.x = (int)ceil(N/blockDim.x)+1; gridDim.y = 1; gridDim.z = 1;
}
}
/// r = A^T * x
/// NOTE: This kernel should be run with A's number of rows as the number of threads
__global__
void ApplyTransposed_GPU_(
const std::size_t num_rows,
const std::size_t max_row_size,
const double* value,
const std::size_t* index,
const double* x,
double* r)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
{
for ( int n = 0; n < max_row_size; n++ )
{
int col = index [ id + n*num_rows ];
double val = value [ id + n*num_rows ];
atomicAdd( &r[col], val*x[id] );
}
}
}
// Ax = r
__global__ void Apply_GPU_ (
const std::size_t num_rows,
const std::size_t max_row_size,
const double* value,
const std::size_t* index,
const double* x,
double* r)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
{
double sum = 0;
for ( int n = 0 ; n < max_row_size; n++ )
{
unsigned int offset = id + n*num_rows;
sum += value[offset] * x[index[offset]];
}
r[id] = sum;
}
}
__global__
void printVector_GPU(double* x, size_t num_rows)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
printf("%d %e\n", id, x[id]);
}
// returns value of a transposed ELLPack matrix A at (row,col)
__device__
double valueAt_(size_t row, size_t col, double* vValue, size_t* vIndex, size_t max_row_size, size_t num_rows)
{
for(size_t k = 0; k < max_row_size; ++k)
{
if(vIndex[k * num_rows + row] == col)
return vValue[k * num_rows + row];
}
return 0.0;
}
__global__
void printELL_GPU_(double* value, size_t* index, size_t max_row_size, size_t num_rows, size_t num_cols)
{
for ( int i = 0 ; i < num_rows ; i++)
{
for ( int j = 0 ; j < num_cols ; j++)
printf("%f ", valueAt_(i, j, value, index, max_row_size, num_rows) );
printf("\n");
}
}
// adds the value to a transposed ELLPack matrix A at (row,col)
__device__
void atomicAddAt_( size_t row, size_t col, double* vValue, size_t* vIndex, size_t max_row_size, size_t num_rows, double value )
{
for(size_t k = 0; k < max_row_size; ++k)
{
// printf("%d\n", (k * num_rows + y) );
if(vIndex[k * num_rows + col] == row)
{
atomicAdd( &vValue[k * num_rows + col] , value );
// vValue[k * num_rows + col] += value;
// printf("%f \n", vValue[k * num_rows + y]);
k = max_row_size; // to exit for loop
}
}
}
// A_coarse = R * A_fine * P
__global__ void PTAP( double* value, size_t* index, size_t max_row_size, size_t num_rows,
double* value_, size_t* index_, size_t max_row_size_, size_t num_rows_,
double* p_value, size_t* p_index, size_t p_max_row_size,
size_t lev)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if( id < num_rows )
{
for ( int i_ = 0 ; i_ < p_max_row_size ; i_++ )
{
size_t i = p_index[id + i_*num_rows];
double P_ki = p_value[id + i_*num_rows];
if(id==0) printf("i = %lu, P_ki = %f\n", i, P_ki);
// if ( id == 1) printf("%f\n", P_ki);
for( int l_ = 0 ; l_ < max_row_size ; l_++ )
{
size_t l = index[id + l_*num_rows];
double A_kl = value[id + l_*num_rows];
double P_ki_A_kl = P_ki * A_kl;
if(id==0) printf("l = %lu, A_kl = %f\n", l, A_kl);
if(id==0) printf("P_ki_A_kl = %f\n", P_ki_A_kl);
for( int j_ = 0 ; j_ < p_max_row_size ; j_++ )
{
size_t j = p_index[l + j_*num_rows];
if( j >= num_rows ) break;
double P_lj = p_value[l + j_*num_rows];
if(id==0) printf("j = %lu, P_lj = %f\n", j, P_lj);
double P_ki_A_kl_P_lj = P_ki_A_kl * P_lj;
if(id==0) printf("PAP(%lu,%lu) = %f\n", i,j,P_ki_A_kl_P_lj);
if(P_ki_A_kl_P_lj != 0.0)
atomicAddAt_( j, i, value_, index_, max_row_size_, num_rows_, P_ki_A_kl_P_lj );
}
}
}
// atomicAddAt_( 0, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 0, 2, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 1, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 2, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 1, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 2, value_, index_, max_row_size_, num_rows_, 10 );
}
}
// Au = b
int main()
{
size_t N = 100;
// A matrix
vector<double> A_value( N, 1);
vector<size_t> A_index( N );
size_t mrs = 1;
for ( int i = 0 ; i < N ; i++ )
A_index[i] = i;
double* d_A_value;
size_t* d_A_index;
CUDA_CALL( hipMalloc((void**)&d_A_value, sizeof(double) * N ) );
CUDA_CALL( hipMalloc((void**)&d_A_index, sizeof(size_t) * N ) );
CUDA_CALL( hipMemcpy(d_A_value, &A_value[0], sizeof(double) * N, hipMemcpyHostToDevice) );
CUDA_CALL( hipMemcpy(d_A_index, &A_index[0], sizeof(size_t) * N, hipMemcpyHostToDevice) );
// vectors
vector<double> u(N,1);
double* d_b;
double* d_u;
CUDA_CALL( hipMalloc((void**)&d_b, sizeof(double) * N ) );
CUDA_CALL( hipMalloc((void**)&d_u, sizeof(double) * N ) );
CUDA_CALL( hipMemcpy(d_u, &u[0], sizeof(double) * N, hipMemcpyHostToDevice) );
// b = (A^T) * u
ApplyTransposed_GPU_<<<1,N>>>( N, mrs, d_A_value, d_A_index, d_u, d_b );
hipDeviceSynchronize();
printVector_GPU<<<1,N>>>( d_b, N );
hipDeviceSynchronize();
}
// // size_t R_mrs = 2;
// // size_t A_mrs = 2;
// // size_t P_mrs = 2;
// // vector<double> A_value_ = { 1,1,1,2,2,2,3,3,3};
// vector<size_t> A_index_ = { 0,0,0,1,1,1,2,2,2};
// vector<double> R_value = { 1, 3, 2, 2, 1, 4};
// vector<size_t> R_index = { 0, 3, 1, 2, 1, 3};
// vector<double> P_value = { 1, 2, 2, 3, 0, 1, 0, 4};
// vector<size_t> P_index = { 0,1,1,0,3,2,3,2};
// // vector<double> A_value = { 1, 5, 1, 2, 2, 1, 1, 0};
// // vector<size_t> A_index = { 0, 2, 1, 3, 1, 2, 3, 4};
// // vector<double> P_value = { 1, 0, 2, 1, 2, 0, 3, 4};
// // vector<size_t> P_index = { 0, 3, 1, 2, 1, 3, 0, 2};
// double* d_A_value;
// double* d_A_value_;
// double* d_R_value;
// double* d_P_value;
// size_t* d_A_index;
// size_t* d_A_index_;
// size_t* d_R_index;
// size_t* d_P_index;
// CUDA_CALL( cudaMalloc((void**)&d_A_value, sizeof(double) * num_rows[1] * A_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_value_, sizeof(double) * num_rows[0] * num_rows[0] ) );
// CUDA_CALL( cudaMalloc((void**)&d_R_value, sizeof(double) * num_rows[0] * R_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_P_value, sizeof(double) * num_rows[1] * P_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_index, sizeof(size_t) * num_rows[1] * A_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_index_, sizeof(size_t) * num_rows[0] * num_rows[0] ) );
// CUDA_CALL( cudaMalloc((void**)&d_R_index, sizeof(size_t) * num_rows[0] * R_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_P_index, sizeof(size_t) * num_rows[1] * P_mrs ) );
// CUDA_CALL( cudaMemcpy(d_A_value, &A_value[0], sizeof(double) * num_rows[1] * A_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_value_, &A_value_[0], sizeof(double) * num_rows[0] * num_rows[0], cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_R_value, &R_value[0], sizeof(double) * num_rows[0] * R_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_P_value, &P_value[0], sizeof(double) * num_rows[1] * P_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_index, &A_index[0], sizeof(size_t) * num_rows[1] * A_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_index_, &A_index_[0], sizeof(size_t) * num_rows[0] * num_rows[0], cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_R_index, &R_index[0], sizeof(size_t) * num_rows[0] * R_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_P_index, &P_index[0], sizeof(size_t) * num_rows[1] * P_mrs, cudaMemcpyHostToDevice) );
// PTAP<<<1,4>>>(d_A_value, d_A_index, A_mrs, num_rows[1], d_A_value_, d_A_index_, 3, num_rows[0], d_P_value, d_P_index, P_mrs, 0);
// cudaDeviceSynchronize();
// // printELL_GPU_<<<1,1>>>(d_A_value, d_A_index, A_mrs, num_rows[1], num_rows[1]);
// // printELL_GPU_<<<1,1>>>(d_A_value_, d_A_index_, 3, num_rows[0], num_rows[0]);
// // printELL_GPU_<<<1,1>>>(d_P_value, d_P_index, P_mrs, num_rows[1], num_rows[0]);
// // printLinearVector(d_A_index_, 3, 3);
// cudaDeviceSynchronize(); |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
using namespace std;
#define CUDA_CALL( call ) \
{ \
hipError_t err = call; \
if ( hipSuccess != err) \
fprintf(stderr, "CUDA error for %s in %d of %s : %s.\n", #call , __LINE__ , __FILE__ ,hipGetErrorString(err));\
}
__global__ void printLinearVector_GPU(size_t* x, size_t i, size_t num_rows, size_t num_cols)
{
for ( int j = 0 ; j < num_cols ; j++ )
printf("%lu ", x[j+i*num_cols]);
printf("\n");
}
__host__ void printLinearVector(size_t* x, size_t num_rows, size_t num_cols)
{
for(int i = 0 ; i < num_rows ; i++ )
{
printLinearVector_GPU<<<1,1>>>(x, i, num_rows, num_cols);
hipDeviceSynchronize();
}
}
// Determines 1-dimensional CUDA block and grid sizes based on the number of rows N
__host__
void calculateDimensions(size_t N, dim3 &gridDim, dim3 &blockDim)
{
if ( N <= 1024 )
{
blockDim.x = 1024; blockDim.y = 1; blockDim.z = 1;
gridDim.x = 1; gridDim.y = 1; gridDim.z = 1;
}
else
{
blockDim.x = 1024; blockDim.y = 1; blockDim.z = 1;
gridDim.x = (int)ceil(N/blockDim.x)+1; gridDim.y = 1; gridDim.z = 1;
}
}
/// r = A^T * x
/// NOTE: This kernel should be run with A's number of rows as the number of threads
__global__
void ApplyTransposed_GPU_(
const std::size_t num_rows,
const std::size_t max_row_size,
const double* value,
const std::size_t* index,
const double* x,
double* r)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
{
for ( int n = 0; n < max_row_size; n++ )
{
int col = index [ id + n*num_rows ];
double val = value [ id + n*num_rows ];
atomicAdd( &r[col], val*x[id] );
}
}
}
// Ax = r
__global__ void Apply_GPU_ (
const std::size_t num_rows,
const std::size_t max_row_size,
const double* value,
const std::size_t* index,
const double* x,
double* r)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
{
double sum = 0;
for ( int n = 0 ; n < max_row_size; n++ )
{
unsigned int offset = id + n*num_rows;
sum += value[offset] * x[index[offset]];
}
r[id] = sum;
}
}
__global__
void printVector_GPU(double* x, size_t num_rows)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if ( id < num_rows )
printf("%d %e\n", id, x[id]);
}
// returns value of a transposed ELLPack matrix A at (row,col)
__device__
double valueAt_(size_t row, size_t col, double* vValue, size_t* vIndex, size_t max_row_size, size_t num_rows)
{
for(size_t k = 0; k < max_row_size; ++k)
{
if(vIndex[k * num_rows + row] == col)
return vValue[k * num_rows + row];
}
return 0.0;
}
__global__
void printELL_GPU_(double* value, size_t* index, size_t max_row_size, size_t num_rows, size_t num_cols)
{
for ( int i = 0 ; i < num_rows ; i++)
{
for ( int j = 0 ; j < num_cols ; j++)
printf("%f ", valueAt_(i, j, value, index, max_row_size, num_rows) );
printf("\n");
}
}
// adds the value to a transposed ELLPack matrix A at (row,col)
__device__
void atomicAddAt_( size_t row, size_t col, double* vValue, size_t* vIndex, size_t max_row_size, size_t num_rows, double value )
{
for(size_t k = 0; k < max_row_size; ++k)
{
// printf("%d\n", (k * num_rows + y) );
if(vIndex[k * num_rows + col] == row)
{
atomicAdd( &vValue[k * num_rows + col] , value );
// vValue[k * num_rows + col] += value;
// printf("%f \n", vValue[k * num_rows + y]);
k = max_row_size; // to exit for loop
}
}
}
// A_coarse = R * A_fine * P
__global__ void PTAP( double* value, size_t* index, size_t max_row_size, size_t num_rows,
double* value_, size_t* index_, size_t max_row_size_, size_t num_rows_,
double* p_value, size_t* p_index, size_t p_max_row_size,
size_t lev)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
if( id < num_rows )
{
for ( int i_ = 0 ; i_ < p_max_row_size ; i_++ )
{
size_t i = p_index[id + i_*num_rows];
double P_ki = p_value[id + i_*num_rows];
if(id==0) printf("i = %lu, P_ki = %f\n", i, P_ki);
// if ( id == 1) printf("%f\n", P_ki);
for( int l_ = 0 ; l_ < max_row_size ; l_++ )
{
size_t l = index[id + l_*num_rows];
double A_kl = value[id + l_*num_rows];
double P_ki_A_kl = P_ki * A_kl;
if(id==0) printf("l = %lu, A_kl = %f\n", l, A_kl);
if(id==0) printf("P_ki_A_kl = %f\n", P_ki_A_kl);
for( int j_ = 0 ; j_ < p_max_row_size ; j_++ )
{
size_t j = p_index[l + j_*num_rows];
if( j >= num_rows ) break;
double P_lj = p_value[l + j_*num_rows];
if(id==0) printf("j = %lu, P_lj = %f\n", j, P_lj);
double P_ki_A_kl_P_lj = P_ki_A_kl * P_lj;
if(id==0) printf("PAP(%lu,%lu) = %f\n", i,j,P_ki_A_kl_P_lj);
if(P_ki_A_kl_P_lj != 0.0)
atomicAddAt_( j, i, value_, index_, max_row_size_, num_rows_, P_ki_A_kl_P_lj );
}
}
}
// atomicAddAt_( 0, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 0, 2, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 1, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 1, 2, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 0, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 1, value_, index_, max_row_size_, num_rows_, 10 );
// atomicAddAt_( 2, 2, value_, index_, max_row_size_, num_rows_, 10 );
}
}
// Au = b
int main()
{
size_t N = 100;
// A matrix
vector<double> A_value( N, 1);
vector<size_t> A_index( N );
size_t mrs = 1;
for ( int i = 0 ; i < N ; i++ )
A_index[i] = i;
double* d_A_value;
size_t* d_A_index;
CUDA_CALL( hipMalloc((void**)&d_A_value, sizeof(double) * N ) );
CUDA_CALL( hipMalloc((void**)&d_A_index, sizeof(size_t) * N ) );
CUDA_CALL( hipMemcpy(d_A_value, &A_value[0], sizeof(double) * N, hipMemcpyHostToDevice) );
CUDA_CALL( hipMemcpy(d_A_index, &A_index[0], sizeof(size_t) * N, hipMemcpyHostToDevice) );
// vectors
vector<double> u(N,1);
double* d_b;
double* d_u;
CUDA_CALL( hipMalloc((void**)&d_b, sizeof(double) * N ) );
CUDA_CALL( hipMalloc((void**)&d_u, sizeof(double) * N ) );
CUDA_CALL( hipMemcpy(d_u, &u[0], sizeof(double) * N, hipMemcpyHostToDevice) );
// b = (A^T) * u
ApplyTransposed_GPU_<<<1,N>>>( N, mrs, d_A_value, d_A_index, d_u, d_b );
hipDeviceSynchronize();
printVector_GPU<<<1,N>>>( d_b, N );
hipDeviceSynchronize();
}
// // size_t R_mrs = 2;
// // size_t A_mrs = 2;
// // size_t P_mrs = 2;
// // vector<double> A_value_ = { 1,1,1,2,2,2,3,3,3};
// vector<size_t> A_index_ = { 0,0,0,1,1,1,2,2,2};
// vector<double> R_value = { 1, 3, 2, 2, 1, 4};
// vector<size_t> R_index = { 0, 3, 1, 2, 1, 3};
// vector<double> P_value = { 1, 2, 2, 3, 0, 1, 0, 4};
// vector<size_t> P_index = { 0,1,1,0,3,2,3,2};
// // vector<double> A_value = { 1, 5, 1, 2, 2, 1, 1, 0};
// // vector<size_t> A_index = { 0, 2, 1, 3, 1, 2, 3, 4};
// // vector<double> P_value = { 1, 0, 2, 1, 2, 0, 3, 4};
// // vector<size_t> P_index = { 0, 3, 1, 2, 1, 3, 0, 2};
// double* d_A_value;
// double* d_A_value_;
// double* d_R_value;
// double* d_P_value;
// size_t* d_A_index;
// size_t* d_A_index_;
// size_t* d_R_index;
// size_t* d_P_index;
// CUDA_CALL( cudaMalloc((void**)&d_A_value, sizeof(double) * num_rows[1] * A_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_value_, sizeof(double) * num_rows[0] * num_rows[0] ) );
// CUDA_CALL( cudaMalloc((void**)&d_R_value, sizeof(double) * num_rows[0] * R_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_P_value, sizeof(double) * num_rows[1] * P_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_index, sizeof(size_t) * num_rows[1] * A_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_A_index_, sizeof(size_t) * num_rows[0] * num_rows[0] ) );
// CUDA_CALL( cudaMalloc((void**)&d_R_index, sizeof(size_t) * num_rows[0] * R_mrs ) );
// CUDA_CALL( cudaMalloc((void**)&d_P_index, sizeof(size_t) * num_rows[1] * P_mrs ) );
// CUDA_CALL( cudaMemcpy(d_A_value, &A_value[0], sizeof(double) * num_rows[1] * A_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_value_, &A_value_[0], sizeof(double) * num_rows[0] * num_rows[0], cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_R_value, &R_value[0], sizeof(double) * num_rows[0] * R_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_P_value, &P_value[0], sizeof(double) * num_rows[1] * P_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_index, &A_index[0], sizeof(size_t) * num_rows[1] * A_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_A_index_, &A_index_[0], sizeof(size_t) * num_rows[0] * num_rows[0], cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_R_index, &R_index[0], sizeof(size_t) * num_rows[0] * R_mrs, cudaMemcpyHostToDevice) );
// CUDA_CALL( cudaMemcpy(d_P_index, &P_index[0], sizeof(size_t) * num_rows[1] * P_mrs, cudaMemcpyHostToDevice) );
// PTAP<<<1,4>>>(d_A_value, d_A_index, A_mrs, num_rows[1], d_A_value_, d_A_index_, 3, num_rows[0], d_P_value, d_P_index, P_mrs, 0);
// cudaDeviceSynchronize();
// // printELL_GPU_<<<1,1>>>(d_A_value, d_A_index, A_mrs, num_rows[1], num_rows[1]);
// // printELL_GPU_<<<1,1>>>(d_A_value_, d_A_index_, 3, num_rows[0], num_rows[0]);
// // printELL_GPU_<<<1,1>>>(d_P_value, d_P_index, P_mrs, num_rows[1], num_rows[0]);
// // printLinearVector(d_A_index_, 3, 3);
// cudaDeviceSynchronize(); | .text
.file "bb.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__printLinearVector_GPUPmmmm # -- Begin function _Z36__device_stub__printLinearVector_GPUPmmmm
.p2align 4, 0x90
.type _Z36__device_stub__printLinearVector_GPUPmmmm,@function
_Z36__device_stub__printLinearVector_GPUPmmmm: # @_Z36__device_stub__printLinearVector_GPUPmmmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21printLinearVector_GPUPmmmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__printLinearVector_GPUPmmmm, .Lfunc_end0-_Z36__device_stub__printLinearVector_GPUPmmmm
.cfi_endproc
# -- End function
.globl _Z17printLinearVectorPmmm # -- Begin function _Z17printLinearVectorPmmm
.p2align 4, 0x90
.type _Z17printLinearVectorPmmm,@function
_Z17printLinearVectorPmmm: # @_Z17printLinearVectorPmmm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB1_6
# %bb.1: # %.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
movabsq $4294967297, %r12 # imm = 0x100000001
xorl %ebp, %ebp
leaq 80(%rsp), %r13
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
callq hipDeviceSynchronize
incq %rbp
cmpq %rbp, %r14
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq %r15, 72(%rsp)
movq %rbp, 64(%rsp)
movq %r14, 56(%rsp)
movq %rbx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
movl $_Z21printLinearVector_GPUPmmmm, %edi
movq %r13, %r9
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_4
.LBB1_5:
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_6: # %._crit_edge
retq
.Lfunc_end1:
.size _Z17printLinearVectorPmmm, .Lfunc_end1-_Z17printLinearVectorPmmm
.cfi_endproc
# -- End function
.globl _Z19calculateDimensionsmR4dim3S0_ # -- Begin function _Z19calculateDimensionsmR4dim3S0_
.p2align 4, 0x90
.type _Z19calculateDimensionsmR4dim3S0_,@function
_Z19calculateDimensionsmR4dim3S0_: # @_Z19calculateDimensionsmR4dim3S0_
.cfi_startproc
# %bb.0:
movq %rdi, %rax
shrq $10, %rax
incl %eax
cmpq $1025, %rdi # imm = 0x401
movabsq $4294968320, %rcx # imm = 0x100000400
movq %rcx, (%rdx)
movl $1, %ecx
cmovael %eax, %ecx
movl $1, 8(%rdx)
movl %ecx, (%rsi)
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, 4(%rsi)
retq
.Lfunc_end2:
.size _Z19calculateDimensionsmR4dim3S0_, .Lfunc_end2-_Z19calculateDimensionsmR4dim3S0_
.cfi_endproc
# -- End function
.globl _Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd # -- Begin function _Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd
.p2align 4, 0x90
.type _Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd,@function
_Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd: # @_Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd, .Lfunc_end3-_Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd
.cfi_endproc
# -- End function
.globl _Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd # -- Begin function _Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd
.p2align 4, 0x90
.type _Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd,@function
_Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd: # @_Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10Apply_GPU_mmPKdPKmS0_Pd, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd, .Lfunc_end4-_Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd
.cfi_endproc
# -- End function
.globl _Z30__device_stub__printVector_GPUPdm # -- Begin function _Z30__device_stub__printVector_GPUPdm
.p2align 4, 0x90
.type _Z30__device_stub__printVector_GPUPdm,@function
_Z30__device_stub__printVector_GPUPdm: # @_Z30__device_stub__printVector_GPUPdm
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z15printVector_GPUPdm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end5:
.size _Z30__device_stub__printVector_GPUPdm, .Lfunc_end5-_Z30__device_stub__printVector_GPUPdm
.cfi_endproc
# -- End function
.globl _Z28__device_stub__printELL_GPU_PdPmmmm # -- Begin function _Z28__device_stub__printELL_GPU_PdPmmmm
.p2align 4, 0x90
.type _Z28__device_stub__printELL_GPU_PdPmmmm,@function
_Z28__device_stub__printELL_GPU_PdPmmmm: # @_Z28__device_stub__printELL_GPU_PdPmmmm
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13printELL_GPU_PdPmmmm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end6:
.size _Z28__device_stub__printELL_GPU_PdPmmmm, .Lfunc_end6-_Z28__device_stub__printELL_GPU_PdPmmmm
.cfi_endproc
# -- End function
.globl _Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm # -- Begin function _Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm
.p2align 4, 0x90
.type _Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm,@function
_Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm: # @_Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm
.cfi_startproc
# %bb.0:
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 208(%rsp), %rax
movq %rax, 144(%rsp)
leaq 216(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4PTAPPdPmmmS_S0_mmS_S0_mm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $216, %rsp
.cfi_adjust_cfa_offset -216
retq
.Lfunc_end7:
.size _Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm, .Lfunc_end7-_Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %.noexc
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $184, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
.cfi_escape 0x2e, 0x00
movl $800, %edi # imm = 0x320
callq _Znwm
movq %rax, %rbx
xorl %eax, %eax
movabsq $4607182418800017408, %r12 # imm = 0x3FF0000000000000
.p2align 4, 0x90
.LBB8_1: # %.lr.ph.i.i.i.i.i.i.i.i.i
# =>This Inner Loop Header: Depth=1
movq %r12, (%rbx,%rax)
addq $8, %rax
cmpq $800, %rax # imm = 0x320
jne .LBB8_1
# %bb.2: # %_ZNSt6vectorIdSaIdEEC2EmRKdRKS0_.exit
.Ltmp0:
.cfi_escape 0x2e, 0x00
movl $800, %edi # imm = 0x320
callq _Znwm
.Ltmp1:
# %bb.3: # %_ZNSt6vectorImSaImEEC2EmRKS0_.exit
movq %rax, %r14
.cfi_escape 0x2e, 0x00
xorl %r15d, %r15d
movl $800, %edx # imm = 0x320
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB8_4: # =>This Inner Loop Header: Depth=1
movq %r15, (%r14,%r15,8)
incq %r15
cmpq $100, %r15
jne .LBB8_4
# %bb.5:
.Ltmp3:
.cfi_escape 0x2e, 0x00
leaq 88(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
.Ltmp4:
# %bb.6:
testl %eax, %eax
jne .LBB8_7
.LBB8_9:
.Ltmp8:
.cfi_escape 0x2e, 0x00
leaq 80(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
.Ltmp9:
# %bb.10:
testl %eax, %eax
jne .LBB8_11
.LBB8_13:
movq 88(%rsp), %rdi
.Ltmp13:
.cfi_escape 0x2e, 0x00
movl $800, %edx # imm = 0x320
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp14:
# %bb.14:
testl %eax, %eax
jne .LBB8_15
.LBB8_17:
movq 80(%rsp), %rdi
.Ltmp18:
.cfi_escape 0x2e, 0x00
movl $800, %edx # imm = 0x320
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp19:
# %bb.18:
testl %eax, %eax
jne .LBB8_19
.LBB8_21:
.Ltmp23:
.cfi_escape 0x2e, 0x00
movl $800, %edi # imm = 0x320
callq _Znwm
.Ltmp24:
# %bb.22: # %.lr.ph.i.i.i.i.i.i.i.i.i70.preheader
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB8_23: # %.lr.ph.i.i.i.i.i.i.i.i.i70
# =>This Inner Loop Header: Depth=1
movq %r12, (%r15,%rax)
addq $8, %rax
cmpq $800, %rax # imm = 0x320
jne .LBB8_23
# %bb.24: # %_ZNSt6vectorIdSaIdEEC2EmRKdRKS0_.exit74
.Ltmp26:
.cfi_escape 0x2e, 0x00
leaq 72(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
.Ltmp27:
# %bb.25:
testl %eax, %eax
jne .LBB8_26
.LBB8_28:
.Ltmp31:
.cfi_escape 0x2e, 0x00
leaq 64(%rsp), %rdi
movl $800, %esi # imm = 0x320
callq hipMalloc
.Ltmp32:
# %bb.29:
testl %eax, %eax
jne .LBB8_30
.LBB8_32:
movq 64(%rsp), %rdi
.Ltmp36:
.cfi_escape 0x2e, 0x00
movl $800, %edx # imm = 0x320
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp37:
# %bb.33:
testl %eax, %eax
jne .LBB8_34
.LBB8_36:
.Ltmp41:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294967396, %rdx # imm = 0x100000064
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp42:
# %bb.37:
testl %eax, %eax
jne .LBB8_40
# %bb.38:
movq 88(%rsp), %rax
movq 80(%rsp), %rcx
movq 64(%rsp), %rdx
movq 72(%rsp), %rsi
movq $100, 56(%rsp)
movq $1, 48(%rsp)
movq %rax, 8(%rsp)
movq %rcx, (%rsp)
movq %rdx, 120(%rsp)
movq %rsi, 112(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
.Ltmp43:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 104(%rsp), %rdx
leaq 96(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp44:
# %bb.39: # %.noexc75
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp45:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd, %edi
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp46:
.LBB8_40:
.Ltmp47:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp48:
# %bb.41:
.Ltmp49:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294967396, %rdx # imm = 0x100000064
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp50:
# %bb.42:
testl %eax, %eax
jne .LBB8_45
# %bb.43:
movq 72(%rsp), %rax
movq %rax, 56(%rsp)
movq $100, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
.Ltmp51:
.cfi_escape 0x2e, 0x00
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
.Ltmp52:
# %bb.44: # %.noexc83
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
.Ltmp53:
.cfi_escape 0x2e, 0x10
leaq 128(%rsp), %r9
movl $_Z15printVector_GPUPdm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp54:
.LBB8_45:
.Ltmp55:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp56:
# %bb.46: # %_ZNSt6vectorIdSaIdEED2Ev.exit
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB8_7:
.cfi_def_cfa_offset 224
movq stderr(%rip), %r15
.Ltmp5:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp6:
# %bb.8:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $.L.str.1, %edx
movl $.L.str.2, %r8d
movq %r15, %rdi
movl $231, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB8_9
.LBB8_11:
movq stderr(%rip), %r15
.Ltmp10:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp11:
# %bb.12:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $.L.str.3, %edx
movl $.L.str.2, %r8d
movq %r15, %rdi
movl $232, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB8_13
.LBB8_15:
movq stderr(%rip), %r15
.Ltmp15:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp16:
# %bb.16:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $.L.str.4, %edx
movl $.L.str.2, %r8d
movq %r15, %rdi
movl $233, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB8_17
.LBB8_19:
movq stderr(%rip), %r15
.Ltmp20:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp21:
# %bb.20:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $.L.str.5, %edx
movl $.L.str.2, %r8d
movq %r15, %rdi
movl $234, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB8_21
.LBB8_26:
movq stderr(%rip), %r12
.Ltmp28:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp29:
# %bb.27:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $.L.str.6, %edx
movl $.L.str.2, %r8d
movq %r12, %rdi
movl $242, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB8_28
.LBB8_30:
movq stderr(%rip), %r12
.Ltmp33:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp34:
# %bb.31:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $.L.str.7, %edx
movl $.L.str.2, %r8d
movq %r12, %rdi
movl $243, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB8_32
.LBB8_34:
movq stderr(%rip), %r12
.Ltmp38:
.cfi_escape 0x2e, 0x00
movl %eax, %edi
callq hipGetErrorString
.Ltmp39:
# %bb.35:
.cfi_escape 0x2e, 0x00
movl $.L.str, %esi
movl $.L.str.8, %edx
movl $.L.str.2, %r8d
movq %r12, %rdi
movl $244, %ecx
movq %rax, %r9
xorl %eax, %eax
callq fprintf
jmp .LBB8_36
.LBB8_47:
.Ltmp25:
movq %rax, %r12
jmp .LBB8_53
.LBB8_55:
.Ltmp2:
movq %rax, %r12
jmp .LBB8_54
.LBB8_49:
.Ltmp40:
jmp .LBB8_52
.LBB8_48:
.Ltmp35:
jmp .LBB8_52
.LBB8_51:
.Ltmp30:
jmp .LBB8_52
.LBB8_59:
.Ltmp22:
movq %rax, %r12
jmp .LBB8_53
.LBB8_58:
.Ltmp17:
movq %rax, %r12
jmp .LBB8_53
.LBB8_57:
.Ltmp12:
movq %rax, %r12
jmp .LBB8_53
.LBB8_56:
.Ltmp7:
movq %rax, %r12
jmp .LBB8_53
.LBB8_50:
.Ltmp57:
.LBB8_52: # %_ZNSt6vectorIdSaIdEED2Ev.exit89
movq %rax, %r12
.cfi_escape 0x2e, 0x00
movq %r15, %rdi
callq _ZdlPv
.LBB8_53: # %_ZNSt6vectorImSaImEED2Ev.exit91
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _ZdlPv
.LBB8_54: # %_ZNSt6vectorIdSaIdEED2Ev.exit93
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r12, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table8:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp4-.Ltmp3 # Call between .Ltmp3 and .Ltmp4
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp8-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp8 # Call between .Ltmp8 and .Ltmp9
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp14-.Ltmp13 # Call between .Ltmp13 and .Ltmp14
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp19-.Ltmp18 # Call between .Ltmp18 and .Ltmp19
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp27-.Ltmp26 # Call between .Ltmp26 and .Ltmp27
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp31-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp32-.Ltmp31 # Call between .Ltmp31 and .Ltmp32
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp36-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp37-.Ltmp36 # Call between .Ltmp36 and .Ltmp37
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp41-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp56-.Ltmp41 # Call between .Ltmp41 and .Ltmp56
.uleb128 .Ltmp57-.Lfunc_begin0 # jumps to .Ltmp57
.byte 0 # On action: cleanup
.uleb128 .Ltmp5-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp6-.Ltmp5 # Call between .Ltmp5 and .Ltmp6
.uleb128 .Ltmp7-.Lfunc_begin0 # jumps to .Ltmp7
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.uleb128 .Ltmp12-.Lfunc_begin0 # jumps to .Ltmp12
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.uleb128 .Ltmp17-.Lfunc_begin0 # jumps to .Ltmp17
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp28-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp29-.Ltmp28 # Call between .Ltmp28 and .Ltmp29
.uleb128 .Ltmp30-.Lfunc_begin0 # jumps to .Ltmp30
.byte 0 # On action: cleanup
.uleb128 .Ltmp33-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp34-.Ltmp33 # Call between .Ltmp33 and .Ltmp34
.uleb128 .Ltmp35-.Lfunc_begin0 # jumps to .Ltmp35
.byte 0 # On action: cleanup
.uleb128 .Ltmp38-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Ltmp39-.Ltmp38 # Call between .Ltmp38 and .Ltmp39
.uleb128 .Ltmp40-.Lfunc_begin0 # jumps to .Ltmp40
.byte 0 # On action: cleanup
.uleb128 .Ltmp39-.Lfunc_begin0 # >> Call Site 20 <<
.uleb128 .Lfunc_end8-.Ltmp39 # Call between .Ltmp39 and .Lfunc_end8
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21printLinearVector_GPUPmmmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10Apply_GPU_mmPKdPKmS0_Pd, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15printVector_GPUPdm, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13printELL_GPU_PdPmmmm, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4PTAPPdPmmmS_S0_mmS_S0_mm, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21printLinearVector_GPUPmmmm,@object # @_Z21printLinearVector_GPUPmmmm
.section .rodata,"a",@progbits
.globl _Z21printLinearVector_GPUPmmmm
.p2align 3, 0x0
_Z21printLinearVector_GPUPmmmm:
.quad _Z36__device_stub__printLinearVector_GPUPmmmm
.size _Z21printLinearVector_GPUPmmmm, 8
.type _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd,@object # @_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd
.globl _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd
.p2align 3, 0x0
_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd:
.quad _Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd
.size _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd, 8
.type _Z10Apply_GPU_mmPKdPKmS0_Pd,@object # @_Z10Apply_GPU_mmPKdPKmS0_Pd
.globl _Z10Apply_GPU_mmPKdPKmS0_Pd
.p2align 3, 0x0
_Z10Apply_GPU_mmPKdPKmS0_Pd:
.quad _Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd
.size _Z10Apply_GPU_mmPKdPKmS0_Pd, 8
.type _Z15printVector_GPUPdm,@object # @_Z15printVector_GPUPdm
.globl _Z15printVector_GPUPdm
.p2align 3, 0x0
_Z15printVector_GPUPdm:
.quad _Z30__device_stub__printVector_GPUPdm
.size _Z15printVector_GPUPdm, 8
.type _Z13printELL_GPU_PdPmmmm,@object # @_Z13printELL_GPU_PdPmmmm
.globl _Z13printELL_GPU_PdPmmmm
.p2align 3, 0x0
_Z13printELL_GPU_PdPmmmm:
.quad _Z28__device_stub__printELL_GPU_PdPmmmm
.size _Z13printELL_GPU_PdPmmmm, 8
.type _Z4PTAPPdPmmmS_S0_mmS_S0_mm,@object # @_Z4PTAPPdPmmmS_S0_mmS_S0_mm
.globl _Z4PTAPPdPmmmS_S0_mmS_S0_mm
.p2align 3, 0x0
_Z4PTAPPdPmmmS_S0_mmS_S0_mm:
.quad _Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm
.size _Z4PTAPPdPmmmS_S0_mmS_S0_mm, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error for %s in %d of %s : %s.\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc((void**)&d_A_value, sizeof(double) * N )"
.size .L.str.1, 51
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/edofersan/tdo/master/Debug/bb.hip"
.size .L.str.2, 91
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipMalloc((void**)&d_A_index, sizeof(size_t) * N )"
.size .L.str.3, 51
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMemcpy(d_A_value, &A_value[0], sizeof(double) * N, hipMemcpyHostToDevice)"
.size .L.str.4, 77
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy(d_A_index, &A_index[0], sizeof(size_t) * N, hipMemcpyHostToDevice)"
.size .L.str.5, 77
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipMalloc((void**)&d_b, sizeof(double) * N )"
.size .L.str.6, 45
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "hipMalloc((void**)&d_u, sizeof(double) * N )"
.size .L.str.7, 45
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMemcpy(d_u, &u[0], sizeof(double) * N, hipMemcpyHostToDevice)"
.size .L.str.8, 65
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21printLinearVector_GPUPmmmm"
.size .L__unnamed_1, 31
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd"
.size .L__unnamed_2, 38
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10Apply_GPU_mmPKdPKmS0_Pd"
.size .L__unnamed_3, 28
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z15printVector_GPUPdm"
.size .L__unnamed_4, 23
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z13printELL_GPU_PdPmmmm"
.size .L__unnamed_5, 25
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "_Z4PTAPPdPmmmS_S0_mmS_S0_mm"
.size .L__unnamed_6, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__printLinearVector_GPUPmmmm
.addrsig_sym _Z35__device_stub__ApplyTransposed_GPU_mmPKdPKmS0_Pd
.addrsig_sym _Z25__device_stub__Apply_GPU_mmPKdPKmS0_Pd
.addrsig_sym _Z30__device_stub__printVector_GPUPdm
.addrsig_sym _Z28__device_stub__printELL_GPU_PdPmmmm
.addrsig_sym _Z19__device_stub__PTAPPdPmmmS_S0_mmS_S0_mm
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z21printLinearVector_GPUPmmmm
.addrsig_sym _Z20ApplyTransposed_GPU_mmPKdPKmS0_Pd
.addrsig_sym _Z10Apply_GPU_mmPKdPKmS0_Pd
.addrsig_sym _Z15printVector_GPUPdm
.addrsig_sym _Z13printELL_GPU_PdPmmmm
.addrsig_sym _Z4PTAPPdPmmmS_S0_mmS_S0_mm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <chrono>
const size_t size = 1 << 20;
__global__ void transpose(float_t *matrixOrigin, float_t *matrixRes) {
size_t x = blockIdx.x * blockDim.x + threadIdx.x;
size_t y = blockIdx.y * blockDim.y + threadIdx.y;
size_t width = gridDim.x * blockDim.x;
matrixRes[x + y * width] = matrixOrigin[y + x * width];
}
__global__ void saxpy(float_t *vectorA, float_t *vectorB, float_t alpha) {
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
vectorA[index] = vectorA[index] * alpha + vectorB[index];
}
int32_t main() {
std::chrono::high_resolution_clock::time_point start = std::chrono::high_resolution_clock::now();
cudaStream_t stream0;
const size_t num = 32;
const size_t Nx = 1 << 10;
const size_t Ny = 1 << 10;
cudaStreamCreate(&stream0);
float_t *matrix, *matrix_dev_origin, *matrix_dev_res;
cudaHostAlloc((void **) &matrix, size * sizeof(float_t), cudaHostAllocDefault);
for (int64_t i = 0; i < size; ++i)
matrix[i] = i;
cudaMalloc((void **) &matrix_dev_origin, sizeof(float_t) * size);
cudaMalloc((void **) &matrix_dev_res, sizeof(float_t) * size);
cudaMemcpyAsync(matrix_dev_origin, matrix, sizeof(float_t) * size, cudaMemcpyHostToDevice, stream0);
transpose <<< dim3(Nx / num, Ny / num), dim3(num, num) >>>(matrix_dev_origin, matrix_dev_res);
cudaMemcpyAsync(matrix, matrix_dev_res, sizeof(float_t) * size, cudaMemcpyDeviceToHost, stream0);
cudaStreamSynchronize(stream0);
std::chrono::high_resolution_clock::time_point stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double_t> time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(
stop - start);
std::cout << "Transpose time (s) - " << time_span.count() << std::endl;
// for(int64_t i = 0; i < Ny; ++i)
// {
// for(int64_t j = 0; j < Nx; ++j)
// std:: cout << matrix[i * Nx + j] << " ";
// std::cout << std::endl;
// }
cudaFree(matrix_dev_origin);
cudaFree(matrix_dev_res);
cudaFreeHost(matrix);
start = std::chrono::high_resolution_clock::now();
float_t *vecA, *vecB, *vecA_device, *vecB_device;
cudaStream_t stream_m0;
cudaStreamCreate(&stream_m0);
cudaStream_t stream1;
cudaStreamCreate(&stream1);
cudaHostAlloc((void **) &vecA, size * sizeof(float_t), cudaHostAllocDefault);
cudaHostAlloc((void **) &vecB, size * sizeof(float_t), cudaHostAllocDefault);
for (int64_t i = 0; i < size; ++i) {
vecA[i] = i;
vecB[i] = i * 2 - 1;
}
cudaMalloc((void **) &vecA_device, sizeof(float_t) * size);
cudaMalloc((void **) &vecB_device, sizeof(float_t) * size);
cudaMemcpyAsync(vecA_device, vecA, sizeof(int) * size, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(vecB_device, vecB, sizeof(int) * size, cudaMemcpyHostToDevice, stream1);
saxpy <<< size / 2 / 1024, 1024, 0, stream0 >>>(vecA_device, vecB_device, 2.25);
saxpy <<< size / 2 / 1024, 1024, 0, stream1 >>>(vecA_device + size / 2, vecB_device + size / 2, 2.25);
cudaMemcpyAsync(vecA, vecA_device, sizeof(float_t) * size / 2, cudaMemcpyDeviceToDevice, stream0);
cudaMemcpyAsync(vecA + size / 2, vecA_device + size / 2, sizeof(float_t) * size / 2, cudaMemcpyDeviceToDevice,
stream1);
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
stop = std::chrono::high_resolution_clock::now();
time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(stop - start);
std::cout << "SAXPY time (s) - " << time_span.count() << std::endl;
//for (int64_t i = 0; i < size; ++i)
// std::cout << vecA[i] << " ";
cudaFree(vecA_device);
cudaFree(vecB_device);
cudaFreeHost(vecA);
cudaFreeHost(vecB);
} | code for sm_80
Function : _Z5saxpyPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R4, R2, R7, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0007 */
/*0080*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FFMA R7, R0, c[0x0][0x170], R5 ; /* 0x00005c0000077a23 */
/* 0x004fca0000000005 */
/*00b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fe200078e0205 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fd200078e0203 */
/*00c0*/ IMAD.WIDE.U32 R8, R2, UR4, R4 ; /* 0x0000000402087c25 */
/* 0x000fca000f8e0004 */
/*00d0*/ LEA R6, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008067a11 */
/* 0x000fc800078010ff */
/*00e0*/ LEA.HI.X R7, R8, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590008077a11 */
/* 0x000fcc00000f1409 */
/*00f0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*0100*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fd400000001ff */
/*0110*/ IMAD.WIDE.U32 R2, R4, UR4, R2 ; /* 0x0000000404027c25 */
/* 0x000fca000f8e0002 */
/*0120*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0130*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f1403 */
/*0140*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe2000c101906 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <chrono>
const size_t size = 1 << 20;
__global__ void transpose(float_t *matrixOrigin, float_t *matrixRes) {
size_t x = blockIdx.x * blockDim.x + threadIdx.x;
size_t y = blockIdx.y * blockDim.y + threadIdx.y;
size_t width = gridDim.x * blockDim.x;
matrixRes[x + y * width] = matrixOrigin[y + x * width];
}
__global__ void saxpy(float_t *vectorA, float_t *vectorB, float_t alpha) {
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
vectorA[index] = vectorA[index] * alpha + vectorB[index];
}
int32_t main() {
std::chrono::high_resolution_clock::time_point start = std::chrono::high_resolution_clock::now();
cudaStream_t stream0;
const size_t num = 32;
const size_t Nx = 1 << 10;
const size_t Ny = 1 << 10;
cudaStreamCreate(&stream0);
float_t *matrix, *matrix_dev_origin, *matrix_dev_res;
cudaHostAlloc((void **) &matrix, size * sizeof(float_t), cudaHostAllocDefault);
for (int64_t i = 0; i < size; ++i)
matrix[i] = i;
cudaMalloc((void **) &matrix_dev_origin, sizeof(float_t) * size);
cudaMalloc((void **) &matrix_dev_res, sizeof(float_t) * size);
cudaMemcpyAsync(matrix_dev_origin, matrix, sizeof(float_t) * size, cudaMemcpyHostToDevice, stream0);
transpose <<< dim3(Nx / num, Ny / num), dim3(num, num) >>>(matrix_dev_origin, matrix_dev_res);
cudaMemcpyAsync(matrix, matrix_dev_res, sizeof(float_t) * size, cudaMemcpyDeviceToHost, stream0);
cudaStreamSynchronize(stream0);
std::chrono::high_resolution_clock::time_point stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double_t> time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(
stop - start);
std::cout << "Transpose time (s) - " << time_span.count() << std::endl;
// for(int64_t i = 0; i < Ny; ++i)
// {
// for(int64_t j = 0; j < Nx; ++j)
// std:: cout << matrix[i * Nx + j] << " ";
// std::cout << std::endl;
// }
cudaFree(matrix_dev_origin);
cudaFree(matrix_dev_res);
cudaFreeHost(matrix);
start = std::chrono::high_resolution_clock::now();
float_t *vecA, *vecB, *vecA_device, *vecB_device;
cudaStream_t stream_m0;
cudaStreamCreate(&stream_m0);
cudaStream_t stream1;
cudaStreamCreate(&stream1);
cudaHostAlloc((void **) &vecA, size * sizeof(float_t), cudaHostAllocDefault);
cudaHostAlloc((void **) &vecB, size * sizeof(float_t), cudaHostAllocDefault);
for (int64_t i = 0; i < size; ++i) {
vecA[i] = i;
vecB[i] = i * 2 - 1;
}
cudaMalloc((void **) &vecA_device, sizeof(float_t) * size);
cudaMalloc((void **) &vecB_device, sizeof(float_t) * size);
cudaMemcpyAsync(vecA_device, vecA, sizeof(int) * size, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(vecB_device, vecB, sizeof(int) * size, cudaMemcpyHostToDevice, stream1);
saxpy <<< size / 2 / 1024, 1024, 0, stream0 >>>(vecA_device, vecB_device, 2.25);
saxpy <<< size / 2 / 1024, 1024, 0, stream1 >>>(vecA_device + size / 2, vecB_device + size / 2, 2.25);
cudaMemcpyAsync(vecA, vecA_device, sizeof(float_t) * size / 2, cudaMemcpyDeviceToDevice, stream0);
cudaMemcpyAsync(vecA + size / 2, vecA_device + size / 2, sizeof(float_t) * size / 2, cudaMemcpyDeviceToDevice,
stream1);
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
stop = std::chrono::high_resolution_clock::now();
time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(stop - start);
std::cout << "SAXPY time (s) - " << time_span.count() << std::endl;
//for (int64_t i = 0; i < size; ++i)
// std::cout << vecA[i] << " ";
cudaFree(vecA_device);
cudaFree(vecB_device);
cudaFreeHost(vecA);
cudaFreeHost(vecB);
} | .file "tmpxft_000fe4d0_00000000-6_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9transposePfS_PfS_
.type _Z30__device_stub__Z9transposePfS_PfS_, @function
_Z30__device_stub__Z9transposePfS_PfS_:
.LFB3796:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z30__device_stub__Z9transposePfS_PfS_, .-_Z30__device_stub__Z9transposePfS_PfS_
.globl _Z9transposePfS_
.type _Z9transposePfS_, @function
_Z9transposePfS_:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z9transposePfS_, .-_Z9transposePfS_
.globl _Z27__device_stub__Z5saxpyPfS_fPfS_f
.type _Z27__device_stub__Z5saxpyPfS_fPfS_f, @function
_Z27__device_stub__Z5saxpyPfS_fPfS_f:
.LFB3798:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3798:
.size _Z27__device_stub__Z5saxpyPfS_fPfS_f, .-_Z27__device_stub__Z5saxpyPfS_fPfS_f
.globl _Z5saxpyPfS_f
.type _Z5saxpyPfS_f, @function
_Z5saxpyPfS_f:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5saxpyPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _Z5saxpyPfS_f, .-_Z5saxpyPfS_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Transpose time (s) - "
.LC3:
.string "SAXPY time (s) - "
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movq %rsp, %rdi
call cudaStreamCreate@PLT
leaq 8(%rsp), %rdi
movl $0, %edx
movl $4194304, %esi
call cudaHostAlloc@PLT
movl $0, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L20
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movq (%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $32, 92(%rsp)
movl $32, 96(%rsp)
movl $1, 100(%rsp)
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
movq (%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq (%rsp), %rdi
call cudaStreamSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
leaq 64(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 72(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movl $4194304, %esi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movl $4194304, %esi
call cudaHostAlloc@PLT
movq $-1, %rdx
movl $0, %eax
.L22:
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movq 32(%rsp), %rcx
movss %xmm0, (%rcx,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movq 40(%rsp), %rcx
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
addq $2, %rdx
cmpq $1048576, %rax
jne .L22
leaq 48(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movq (%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 72(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $512, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movq (%rsp), %r9
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L23:
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $512, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movq 72(%rsp), %r9
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
movq (%rsp), %r8
movl $3, %ecx
movl $2097152, %edx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 48(%rsp), %rax
leaq 2097152(%rax), %rsi
movq 32(%rsp), %rax
leaq 2097152(%rax), %rdi
movq 72(%rsp), %r8
movl $3, %ecx
movl $2097152, %edx
call cudaMemcpyAsync@PLT
movq (%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 72(%rsp), %rdi
call cudaStreamSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9transposePfS_PfS_
jmp .L21
.L30:
movss .LC2(%rip), %xmm0
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z27__device_stub__Z5saxpyPfS_fPfS_f
jmp .L23
.L31:
movq 56(%rsp), %rax
leaq 2097152(%rax), %rsi
movq 48(%rsp), %rax
leaq 2097152(%rax), %rdi
movss .LC2(%rip), %xmm0
call _Z27__device_stub__Z5saxpyPfS_fPfS_f
jmp .L24
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z5saxpyPfS_f"
.LC5:
.string "_Z9transposePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3801:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPfS_f(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <chrono>
const size_t size = 1 << 20;
__global__ void transpose(float_t *matrixOrigin, float_t *matrixRes) {
size_t x = blockIdx.x * blockDim.x + threadIdx.x;
size_t y = blockIdx.y * blockDim.y + threadIdx.y;
size_t width = gridDim.x * blockDim.x;
matrixRes[x + y * width] = matrixOrigin[y + x * width];
}
__global__ void saxpy(float_t *vectorA, float_t *vectorB, float_t alpha) {
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
vectorA[index] = vectorA[index] * alpha + vectorB[index];
}
int32_t main() {
std::chrono::high_resolution_clock::time_point start = std::chrono::high_resolution_clock::now();
cudaStream_t stream0;
const size_t num = 32;
const size_t Nx = 1 << 10;
const size_t Ny = 1 << 10;
cudaStreamCreate(&stream0);
float_t *matrix, *matrix_dev_origin, *matrix_dev_res;
cudaHostAlloc((void **) &matrix, size * sizeof(float_t), cudaHostAllocDefault);
for (int64_t i = 0; i < size; ++i)
matrix[i] = i;
cudaMalloc((void **) &matrix_dev_origin, sizeof(float_t) * size);
cudaMalloc((void **) &matrix_dev_res, sizeof(float_t) * size);
cudaMemcpyAsync(matrix_dev_origin, matrix, sizeof(float_t) * size, cudaMemcpyHostToDevice, stream0);
transpose <<< dim3(Nx / num, Ny / num), dim3(num, num) >>>(matrix_dev_origin, matrix_dev_res);
cudaMemcpyAsync(matrix, matrix_dev_res, sizeof(float_t) * size, cudaMemcpyDeviceToHost, stream0);
cudaStreamSynchronize(stream0);
std::chrono::high_resolution_clock::time_point stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double_t> time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(
stop - start);
std::cout << "Transpose time (s) - " << time_span.count() << std::endl;
// for(int64_t i = 0; i < Ny; ++i)
// {
// for(int64_t j = 0; j < Nx; ++j)
// std:: cout << matrix[i * Nx + j] << " ";
// std::cout << std::endl;
// }
cudaFree(matrix_dev_origin);
cudaFree(matrix_dev_res);
cudaFreeHost(matrix);
start = std::chrono::high_resolution_clock::now();
float_t *vecA, *vecB, *vecA_device, *vecB_device;
cudaStream_t stream_m0;
cudaStreamCreate(&stream_m0);
cudaStream_t stream1;
cudaStreamCreate(&stream1);
cudaHostAlloc((void **) &vecA, size * sizeof(float_t), cudaHostAllocDefault);
cudaHostAlloc((void **) &vecB, size * sizeof(float_t), cudaHostAllocDefault);
for (int64_t i = 0; i < size; ++i) {
vecA[i] = i;
vecB[i] = i * 2 - 1;
}
cudaMalloc((void **) &vecA_device, sizeof(float_t) * size);
cudaMalloc((void **) &vecB_device, sizeof(float_t) * size);
cudaMemcpyAsync(vecA_device, vecA, sizeof(int) * size, cudaMemcpyHostToDevice, stream0);
cudaMemcpyAsync(vecB_device, vecB, sizeof(int) * size, cudaMemcpyHostToDevice, stream1);
saxpy <<< size / 2 / 1024, 1024, 0, stream0 >>>(vecA_device, vecB_device, 2.25);
saxpy <<< size / 2 / 1024, 1024, 0, stream1 >>>(vecA_device + size / 2, vecB_device + size / 2, 2.25);
cudaMemcpyAsync(vecA, vecA_device, sizeof(float_t) * size / 2, cudaMemcpyDeviceToDevice, stream0);
cudaMemcpyAsync(vecA + size / 2, vecA_device + size / 2, sizeof(float_t) * size / 2, cudaMemcpyDeviceToDevice,
stream1);
cudaStreamSynchronize(stream0);
cudaStreamSynchronize(stream1);
stop = std::chrono::high_resolution_clock::now();
time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(stop - start);
std::cout << "SAXPY time (s) - " << time_span.count() << std::endl;
//for (int64_t i = 0; i < size; ++i)
// std::cout << vecA[i] << " ";
cudaFree(vecA_device);
cudaFree(vecB_device);
cudaFreeHost(vecA);
cudaFreeHost(vecB);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
const size_t size = 1 << 20;
__global__ void transpose(float_t *matrixOrigin, float_t *matrixRes) {
size_t x = blockIdx.x * blockDim.x + threadIdx.x;
size_t y = blockIdx.y * blockDim.y + threadIdx.y;
size_t width = gridDim.x * blockDim.x;
matrixRes[x + y * width] = matrixOrigin[y + x * width];
}
__global__ void saxpy(float_t *vectorA, float_t *vectorB, float_t alpha) {
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
vectorA[index] = vectorA[index] * alpha + vectorB[index];
}
int32_t main() {
std::chrono::high_resolution_clock::time_point start = std::chrono::high_resolution_clock::now();
hipStream_t stream0;
const size_t num = 32;
const size_t Nx = 1 << 10;
const size_t Ny = 1 << 10;
hipStreamCreate(&stream0);
float_t *matrix, *matrix_dev_origin, *matrix_dev_res;
hipHostAlloc((void **) &matrix, size * sizeof(float_t), hipHostMallocDefault);
for (int64_t i = 0; i < size; ++i)
matrix[i] = i;
hipMalloc((void **) &matrix_dev_origin, sizeof(float_t) * size);
hipMalloc((void **) &matrix_dev_res, sizeof(float_t) * size);
hipMemcpyAsync(matrix_dev_origin, matrix, sizeof(float_t) * size, hipMemcpyHostToDevice, stream0);
transpose <<< dim3(Nx / num, Ny / num), dim3(num, num) >>>(matrix_dev_origin, matrix_dev_res);
hipMemcpyAsync(matrix, matrix_dev_res, sizeof(float_t) * size, hipMemcpyDeviceToHost, stream0);
hipStreamSynchronize(stream0);
std::chrono::high_resolution_clock::time_point stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double_t> time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(
stop - start);
std::cout << "Transpose time (s) - " << time_span.count() << std::endl;
// for(int64_t i = 0; i < Ny; ++i)
// {
// for(int64_t j = 0; j < Nx; ++j)
// std:: cout << matrix[i * Nx + j] << " ";
// std::cout << std::endl;
// }
hipFree(matrix_dev_origin);
hipFree(matrix_dev_res);
hipHostFree(matrix);
start = std::chrono::high_resolution_clock::now();
float_t *vecA, *vecB, *vecA_device, *vecB_device;
hipStream_t stream_m0;
hipStreamCreate(&stream_m0);
hipStream_t stream1;
hipStreamCreate(&stream1);
hipHostAlloc((void **) &vecA, size * sizeof(float_t), hipHostMallocDefault);
hipHostAlloc((void **) &vecB, size * sizeof(float_t), hipHostMallocDefault);
for (int64_t i = 0; i < size; ++i) {
vecA[i] = i;
vecB[i] = i * 2 - 1;
}
hipMalloc((void **) &vecA_device, sizeof(float_t) * size);
hipMalloc((void **) &vecB_device, sizeof(float_t) * size);
hipMemcpyAsync(vecA_device, vecA, sizeof(int) * size, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(vecB_device, vecB, sizeof(int) * size, hipMemcpyHostToDevice, stream1);
saxpy <<< size / 2 / 1024, 1024, 0, stream0 >>>(vecA_device, vecB_device, 2.25);
saxpy <<< size / 2 / 1024, 1024, 0, stream1 >>>(vecA_device + size / 2, vecB_device + size / 2, 2.25);
hipMemcpyAsync(vecA, vecA_device, sizeof(float_t) * size / 2, hipMemcpyDeviceToDevice, stream0);
hipMemcpyAsync(vecA + size / 2, vecA_device + size / 2, sizeof(float_t) * size / 2, hipMemcpyDeviceToDevice,
stream1);
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
stop = std::chrono::high_resolution_clock::now();
time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(stop - start);
std::cout << "SAXPY time (s) - " << time_span.count() << std::endl;
//for (int64_t i = 0; i < size; ++i)
// std::cout << vecA[i] << " ";
hipFree(vecA_device);
hipFree(vecB_device);
hipHostFree(vecA);
hipHostFree(vecB);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
const size_t size = 1 << 20;
__global__ void transpose(float_t *matrixOrigin, float_t *matrixRes) {
size_t x = blockIdx.x * blockDim.x + threadIdx.x;
size_t y = blockIdx.y * blockDim.y + threadIdx.y;
size_t width = gridDim.x * blockDim.x;
matrixRes[x + y * width] = matrixOrigin[y + x * width];
}
__global__ void saxpy(float_t *vectorA, float_t *vectorB, float_t alpha) {
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
vectorA[index] = vectorA[index] * alpha + vectorB[index];
}
int32_t main() {
std::chrono::high_resolution_clock::time_point start = std::chrono::high_resolution_clock::now();
hipStream_t stream0;
const size_t num = 32;
const size_t Nx = 1 << 10;
const size_t Ny = 1 << 10;
hipStreamCreate(&stream0);
float_t *matrix, *matrix_dev_origin, *matrix_dev_res;
hipHostAlloc((void **) &matrix, size * sizeof(float_t), hipHostMallocDefault);
for (int64_t i = 0; i < size; ++i)
matrix[i] = i;
hipMalloc((void **) &matrix_dev_origin, sizeof(float_t) * size);
hipMalloc((void **) &matrix_dev_res, sizeof(float_t) * size);
hipMemcpyAsync(matrix_dev_origin, matrix, sizeof(float_t) * size, hipMemcpyHostToDevice, stream0);
transpose <<< dim3(Nx / num, Ny / num), dim3(num, num) >>>(matrix_dev_origin, matrix_dev_res);
hipMemcpyAsync(matrix, matrix_dev_res, sizeof(float_t) * size, hipMemcpyDeviceToHost, stream0);
hipStreamSynchronize(stream0);
std::chrono::high_resolution_clock::time_point stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double_t> time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(
stop - start);
std::cout << "Transpose time (s) - " << time_span.count() << std::endl;
// for(int64_t i = 0; i < Ny; ++i)
// {
// for(int64_t j = 0; j < Nx; ++j)
// std:: cout << matrix[i * Nx + j] << " ";
// std::cout << std::endl;
// }
hipFree(matrix_dev_origin);
hipFree(matrix_dev_res);
hipHostFree(matrix);
start = std::chrono::high_resolution_clock::now();
float_t *vecA, *vecB, *vecA_device, *vecB_device;
hipStream_t stream_m0;
hipStreamCreate(&stream_m0);
hipStream_t stream1;
hipStreamCreate(&stream1);
hipHostAlloc((void **) &vecA, size * sizeof(float_t), hipHostMallocDefault);
hipHostAlloc((void **) &vecB, size * sizeof(float_t), hipHostMallocDefault);
for (int64_t i = 0; i < size; ++i) {
vecA[i] = i;
vecB[i] = i * 2 - 1;
}
hipMalloc((void **) &vecA_device, sizeof(float_t) * size);
hipMalloc((void **) &vecB_device, sizeof(float_t) * size);
hipMemcpyAsync(vecA_device, vecA, sizeof(int) * size, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(vecB_device, vecB, sizeof(int) * size, hipMemcpyHostToDevice, stream1);
saxpy <<< size / 2 / 1024, 1024, 0, stream0 >>>(vecA_device, vecB_device, 2.25);
saxpy <<< size / 2 / 1024, 1024, 0, stream1 >>>(vecA_device + size / 2, vecB_device + size / 2, 2.25);
hipMemcpyAsync(vecA, vecA_device, sizeof(float_t) * size / 2, hipMemcpyDeviceToDevice, stream0);
hipMemcpyAsync(vecA + size / 2, vecA_device + size / 2, sizeof(float_t) * size / 2, hipMemcpyDeviceToDevice,
stream1);
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
stop = std::chrono::high_resolution_clock::now();
time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(stop - start);
std::cout << "SAXPY time (s) - " << time_span.count() << std::endl;
//for (int64_t i = 0; i < size; ++i)
// std::cout << vecA[i] << " ";
hipFree(vecA_device);
hipFree(vecB_device);
hipHostFree(vecA);
hipHostFree(vecB);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePfS_
.globl _Z9transposePfS_
.p2align 8
.type _Z9transposePfS_,@function
_Z9transposePfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_mul_i32 s5, s5, s6
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v7, v3
v_mad_u64_u32 v[4:5], null, v2, s5, 0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_lshlrev_b64 v[4:5], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
global_load_b32 v4, v[0:1], off
v_mad_u64_u32 v[0:1], null, v6, s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePfS_, .Lfunc_end0-_Z9transposePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5saxpyPfS_f
.globl _Z5saxpyPfS_f
.p2align 8
.type _Z5saxpyPfS_f,@function
_Z5saxpyPfS_f:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, s0, v4
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPfS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5saxpyPfS_f, .Lfunc_end1-_Z5saxpyPfS_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPfS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPfS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <chrono>
const size_t size = 1 << 20;
__global__ void transpose(float_t *matrixOrigin, float_t *matrixRes) {
size_t x = blockIdx.x * blockDim.x + threadIdx.x;
size_t y = blockIdx.y * blockDim.y + threadIdx.y;
size_t width = gridDim.x * blockDim.x;
matrixRes[x + y * width] = matrixOrigin[y + x * width];
}
__global__ void saxpy(float_t *vectorA, float_t *vectorB, float_t alpha) {
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
vectorA[index] = vectorA[index] * alpha + vectorB[index];
}
int32_t main() {
std::chrono::high_resolution_clock::time_point start = std::chrono::high_resolution_clock::now();
hipStream_t stream0;
const size_t num = 32;
const size_t Nx = 1 << 10;
const size_t Ny = 1 << 10;
hipStreamCreate(&stream0);
float_t *matrix, *matrix_dev_origin, *matrix_dev_res;
hipHostAlloc((void **) &matrix, size * sizeof(float_t), hipHostMallocDefault);
for (int64_t i = 0; i < size; ++i)
matrix[i] = i;
hipMalloc((void **) &matrix_dev_origin, sizeof(float_t) * size);
hipMalloc((void **) &matrix_dev_res, sizeof(float_t) * size);
hipMemcpyAsync(matrix_dev_origin, matrix, sizeof(float_t) * size, hipMemcpyHostToDevice, stream0);
transpose <<< dim3(Nx / num, Ny / num), dim3(num, num) >>>(matrix_dev_origin, matrix_dev_res);
hipMemcpyAsync(matrix, matrix_dev_res, sizeof(float_t) * size, hipMemcpyDeviceToHost, stream0);
hipStreamSynchronize(stream0);
std::chrono::high_resolution_clock::time_point stop = std::chrono::high_resolution_clock::now();
std::chrono::duration<double_t> time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(
stop - start);
std::cout << "Transpose time (s) - " << time_span.count() << std::endl;
// for(int64_t i = 0; i < Ny; ++i)
// {
// for(int64_t j = 0; j < Nx; ++j)
// std:: cout << matrix[i * Nx + j] << " ";
// std::cout << std::endl;
// }
hipFree(matrix_dev_origin);
hipFree(matrix_dev_res);
hipHostFree(matrix);
start = std::chrono::high_resolution_clock::now();
float_t *vecA, *vecB, *vecA_device, *vecB_device;
hipStream_t stream_m0;
hipStreamCreate(&stream_m0);
hipStream_t stream1;
hipStreamCreate(&stream1);
hipHostAlloc((void **) &vecA, size * sizeof(float_t), hipHostMallocDefault);
hipHostAlloc((void **) &vecB, size * sizeof(float_t), hipHostMallocDefault);
for (int64_t i = 0; i < size; ++i) {
vecA[i] = i;
vecB[i] = i * 2 - 1;
}
hipMalloc((void **) &vecA_device, sizeof(float_t) * size);
hipMalloc((void **) &vecB_device, sizeof(float_t) * size);
hipMemcpyAsync(vecA_device, vecA, sizeof(int) * size, hipMemcpyHostToDevice, stream0);
hipMemcpyAsync(vecB_device, vecB, sizeof(int) * size, hipMemcpyHostToDevice, stream1);
saxpy <<< size / 2 / 1024, 1024, 0, stream0 >>>(vecA_device, vecB_device, 2.25);
saxpy <<< size / 2 / 1024, 1024, 0, stream1 >>>(vecA_device + size / 2, vecB_device + size / 2, 2.25);
hipMemcpyAsync(vecA, vecA_device, sizeof(float_t) * size / 2, hipMemcpyDeviceToDevice, stream0);
hipMemcpyAsync(vecA + size / 2, vecA_device + size / 2, sizeof(float_t) * size / 2, hipMemcpyDeviceToDevice,
stream1);
hipStreamSynchronize(stream0);
hipStreamSynchronize(stream1);
stop = std::chrono::high_resolution_clock::now();
time_span = std::chrono::duration_cast<std::chrono::duration<double_t>>(stop - start);
std::cout << "SAXPY time (s) - " << time_span.count() << std::endl;
//for (int64_t i = 0; i < size; ++i)
// std::cout << vecA[i] << " ";
hipFree(vecA_device);
hipFree(vecB_device);
hipHostFree(vecA);
hipHostFree(vecB);
} | .text
.file "cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__transposePfS_ # -- Begin function _Z24__device_stub__transposePfS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePfS_,@function
_Z24__device_stub__transposePfS_: # @_Z24__device_stub__transposePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePfS_, .Lfunc_end0-_Z24__device_stub__transposePfS_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__saxpyPfS_f # -- Begin function _Z20__device_stub__saxpyPfS_f
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPfS_f,@function
_Z20__device_stub__saxpyPfS_f: # @_Z20__device_stub__saxpyPfS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPfS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__saxpyPfS_f, .Lfunc_end1-_Z20__device_stub__saxpyPfS_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $192, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
leaq 8(%rsp), %rdi
callq hipStreamCreate
leaq 120(%rsp), %rdi
xorl %r14d, %r14d
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostAlloc
movq 120(%rsp), %rax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14, %xmm0
movss %xmm0, (%rax,%r14,4)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB2_1
# %bb.2:
leaq 152(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 144(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 152(%rsp), %rdi
movq 120(%rsp), %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 152(%rsp), %rax
movq 144(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z9transposePfS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 120(%rsp), %rdi
movq 144(%rsp), %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
callq hipStreamSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 128(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_19
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB2_8
.LBB2_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 152(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipHostFree
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
leaq 184(%rsp), %rdi
callq hipStreamCreate
leaq 104(%rsp), %rdi
callq hipStreamCreate
leaq 32(%rsp), %rdi
xorl %r14d, %r14d
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostAlloc
leaq 136(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostAlloc
movq 32(%rsp), %rax
movq $-1, %rcx
movq 136(%rsp), %rdx
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14, %xmm0
movss %xmm0, 2(%rax,%rcx,2)
xorps %xmm0, %xmm0
cvtsi2ss %rcx, %xmm0
movss %xmm0, 2(%rdx,%rcx,2)
incq %r14
addq $2, %rcx
cmpq $2097151, %rcx # imm = 0x1FFFFF
jne .LBB2_9
# %bb.10:
movabsq $4294967808, %r14 # imm = 0x100000200
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 112(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movq 32(%rsp), %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 112(%rsp), %rdi
movq 136(%rsp), %rsi
movq 104(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %r9
leaq 512(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 24(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl $1074790400, 20(%rsp) # imm = 0x40100000
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z5saxpyPfS_f, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movq 104(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movl $2097152, %eax # imm = 0x200000
movq 24(%rsp), %rcx
addq %rax, %rcx
addq 112(%rsp), %rax
movq %rcx, 96(%rsp)
movq %rax, 88(%rsp)
movl $1074790400, 20(%rsp) # imm = 0x40100000
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z5saxpyPfS_f, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %r8
movl $2097152, %r14d # imm = 0x200000
movl $2097152, %edx # imm = 0x200000
movl $3, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %rdi
addq %r14, %rdi
addq 24(%rsp), %r14
movq 104(%rsp), %r8
movl $2097152, %edx # imm = 0x200000
movq %r14, %rsi
movl $3, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 104(%rsp), %rdi
callq hipStreamSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 128(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%rbx)
je .LBB2_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB2_18
.LBB2_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipHostFree
movq 136(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_19:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPfS_f, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePfS_,@object # @_Z9transposePfS_
.section .rodata,"a",@progbits
.globl _Z9transposePfS_
.p2align 3, 0x0
_Z9transposePfS_:
.quad _Z24__device_stub__transposePfS_
.size _Z9transposePfS_, 8
.type _Z5saxpyPfS_f,@object # @_Z5saxpyPfS_f
.globl _Z5saxpyPfS_f
.p2align 3, 0x0
_Z5saxpyPfS_f:
.quad _Z20__device_stub__saxpyPfS_f
.size _Z5saxpyPfS_f, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Transpose time (s) - "
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "SAXPY time (s) - "
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePfS_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5saxpyPfS_f"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePfS_
.addrsig_sym _Z20__device_stub__saxpyPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePfS_
.addrsig_sym _Z5saxpyPfS_f
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5saxpyPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE.U32 R4, R2, R7, c[0x0][0x168] ; /* 0x00005a0002047625 */
/* 0x000fc800078e0007 */
/*0070*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0007 */
/*0080*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FFMA R7, R0, c[0x0][0x170], R5 ; /* 0x00005c0000077a23 */
/* 0x004fca0000000005 */
/*00b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9transposePfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e220000002600 */
/*0020*/ ULDC UR4, c[0x0][0xc] ; /* 0x0000030000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULDC UR5, c[0x0][0x0] ; /* 0x0000000000057ab9 */
/* 0x000fe20000000800 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002200 */
/*0050*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0060*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R4, R4, c[0x0][0x4], R5 ; /* 0x0000010004047a24 */
/* 0x001fe200078e0205 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x002fd200078e0203 */
/*00c0*/ IMAD.WIDE.U32 R8, R2, UR4, R4 ; /* 0x0000000402087c25 */
/* 0x000fca000f8e0004 */
/*00d0*/ LEA R6, P0, R8, c[0x0][0x160], 0x2 ; /* 0x0000580008067a11 */
/* 0x000fc800078010ff */
/*00e0*/ LEA.HI.X R7, R8, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590008077a11 */
/* 0x000fcc00000f1409 */
/*00f0*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ea2000c1e1900 */
/*0100*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fd400000001ff */
/*0110*/ IMAD.WIDE.U32 R2, R4, UR4, R2 ; /* 0x0000000404027c25 */
/* 0x000fca000f8e0002 */
/*0120*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0130*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f1403 */
/*0140*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x004fe2000c101906 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9transposePfS_
.globl _Z9transposePfS_
.p2align 8
.type _Z9transposePfS_,@function
_Z9transposePfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
s_load_b128 s[0:3], s[0:1], 0x0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s4, 0xffff
s_lshr_b32 s4, s4, 16
v_mad_u64_u32 v[2:3], null, s14, s6, v[1:2]
s_mul_i32 s5, s5, s6
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[6:7], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v7, v3
v_mad_u64_u32 v[4:5], null, v2, s5, 0
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[4:5]
v_lshlrev_b64 v[4:5], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v4
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo
global_load_b32 v4, v[0:1], off
v_mad_u64_u32 v[0:1], null, v6, s5, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, v0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9transposePfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9transposePfS_, .Lfunc_end0-_Z9transposePfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5saxpyPfS_f
.globl _Z5saxpyPfS_f
.p2align 8
.type _Z5saxpyPfS_f,@function
_Z5saxpyPfS_f:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v4, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, s0, v4
global_store_b32 v[2:3], v0, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5saxpyPfS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5saxpyPfS_f, .Lfunc_end1-_Z5saxpyPfS_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9transposePfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9transposePfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5saxpyPfS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5saxpyPfS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fe4d0_00000000-6_cuda.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z9transposePfS_PfS_
.type _Z30__device_stub__Z9transposePfS_PfS_, @function
_Z30__device_stub__Z9transposePfS_PfS_:
.LFB3796:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9transposePfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z30__device_stub__Z9transposePfS_PfS_, .-_Z30__device_stub__Z9transposePfS_PfS_
.globl _Z9transposePfS_
.type _Z9transposePfS_, @function
_Z9transposePfS_:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9transposePfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z9transposePfS_, .-_Z9transposePfS_
.globl _Z27__device_stub__Z5saxpyPfS_fPfS_f
.type _Z27__device_stub__Z5saxpyPfS_fPfS_f, @function
_Z27__device_stub__Z5saxpyPfS_fPfS_f:
.LFB3798:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5saxpyPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3798:
.size _Z27__device_stub__Z5saxpyPfS_fPfS_f, .-_Z27__device_stub__Z5saxpyPfS_fPfS_f
.globl _Z5saxpyPfS_f
.type _Z5saxpyPfS_f, @function
_Z5saxpyPfS_f:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z5saxpyPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _Z5saxpyPfS_f, .-_Z5saxpyPfS_f
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Transpose time (s) - "
.LC3:
.string "SAXPY time (s) - "
.text
.globl main
.type main, @function
main:
.LFB3768:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $112, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
movq %rsp, %rdi
call cudaStreamCreate@PLT
leaq 8(%rsp), %rdi
movl $0, %edx
movl $4194304, %esi
call cudaHostAlloc@PLT
movl $0, %eax
.L20:
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movq 8(%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L20
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movq (%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $32, 92(%rsp)
movl $32, 96(%rsp)
movl $1, 100(%rsp)
movl $32, 80(%rsp)
movl $32, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
movq (%rsp), %r8
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq (%rsp), %rdi
call cudaStreamSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFreeHost@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
leaq 64(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 72(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 32(%rsp), %rdi
movl $0, %edx
movl $4194304, %esi
call cudaHostAlloc@PLT
leaq 40(%rsp), %rdi
movl $0, %edx
movl $4194304, %esi
call cudaHostAlloc@PLT
movq $-1, %rdx
movl $0, %eax
.L22:
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
movq 32(%rsp), %rcx
movss %xmm0, (%rcx,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movq 40(%rsp), %rcx
movss %xmm0, (%rcx,%rax,4)
addq $1, %rax
addq $2, %rdx
cmpq $1048576, %rax
jne .L22
leaq 48(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movq (%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 32(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 72(%rsp), %r8
movl $1, %ecx
movl $4194304, %edx
movq 40(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $512, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movq (%rsp), %r9
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L23:
movl $1024, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $512, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movq 72(%rsp), %r9
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L24:
movq (%rsp), %r8
movl $3, %ecx
movl $2097152, %edx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 48(%rsp), %rax
leaq 2097152(%rax), %rsi
movq 32(%rsp), %rax
leaq 2097152(%rax), %rdi
movq 72(%rsp), %r8
movl $3, %ecx
movl $2097152, %edx
call cudaMemcpyAsync@PLT
movq (%rsp), %rdi
call cudaStreamSynchronize@PLT
movq 72(%rsp), %rdi
call cudaStreamSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z30__device_stub__Z9transposePfS_PfS_
jmp .L21
.L30:
movss .LC2(%rip), %xmm0
movq 56(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z27__device_stub__Z5saxpyPfS_fPfS_f
jmp .L23
.L31:
movq 56(%rsp), %rax
leaq 2097152(%rax), %rsi
movq 48(%rsp), %rax
leaq 2097152(%rax), %rdi
movss .LC2(%rip), %xmm0
call _Z27__device_stub__Z5saxpyPfS_fPfS_f
jmp .L24
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z5saxpyPfS_f"
.LC5:
.string "_Z9transposePfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3801:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z5saxpyPfS_f(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z9transposePfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1104006501
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__transposePfS_ # -- Begin function _Z24__device_stub__transposePfS_
.p2align 4, 0x90
.type _Z24__device_stub__transposePfS_,@function
_Z24__device_stub__transposePfS_: # @_Z24__device_stub__transposePfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9transposePfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__transposePfS_, .Lfunc_end0-_Z24__device_stub__transposePfS_
.cfi_endproc
# -- End function
.globl _Z20__device_stub__saxpyPfS_f # -- Begin function _Z20__device_stub__saxpyPfS_f
.p2align 4, 0x90
.type _Z20__device_stub__saxpyPfS_f,@function
_Z20__device_stub__saxpyPfS_f: # @_Z20__device_stub__saxpyPfS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5saxpyPfS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z20__device_stub__saxpyPfS_f, .Lfunc_end1-_Z20__device_stub__saxpyPfS_f
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x41cdcd6500000000 # double 1.0E+9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $192, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
leaq 8(%rsp), %rdi
callq hipStreamCreate
leaq 120(%rsp), %rdi
xorl %r14d, %r14d
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostAlloc
movq 120(%rsp), %rax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14, %xmm0
movss %xmm0, (%rax,%r14,4)
incq %r14
cmpq $1048576, %r14 # imm = 0x100000
jne .LBB2_1
# %bb.2:
leaq 152(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 144(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 152(%rsp), %rdi
movq 120(%rsp), %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 152(%rsp), %rax
movq 144(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z9transposePfS_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 120(%rsp), %rdi
movq 144(%rsp), %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $2, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
callq hipStreamSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 128(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $21, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_19
# %bb.5: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_7
# %bb.6:
movzbl 67(%rbx), %ecx
jmp .LBB2_8
.LBB2_7:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_8: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 152(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 120(%rsp), %rdi
callq hipHostFree
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %rbx
leaq 184(%rsp), %rdi
callq hipStreamCreate
leaq 104(%rsp), %rdi
callq hipStreamCreate
leaq 32(%rsp), %rdi
xorl %r14d, %r14d
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostAlloc
leaq 136(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
xorl %edx, %edx
callq hipHostAlloc
movq 32(%rsp), %rax
movq $-1, %rcx
movq 136(%rsp), %rdx
.p2align 4, 0x90
.LBB2_9: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %r14, %xmm0
movss %xmm0, 2(%rax,%rcx,2)
xorps %xmm0, %xmm0
cvtsi2ss %rcx, %xmm0
movss %xmm0, 2(%rdx,%rcx,2)
incq %r14
addq $2, %rcx
cmpq $2097151, %rcx # imm = 0x1FFFFF
jne .LBB2_9
# %bb.10:
movabsq $4294967808, %r14 # imm = 0x100000200
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 112(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 24(%rsp), %rdi
movq 32(%rsp), %rsi
movq 8(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 112(%rsp), %rdi
movq 136(%rsp), %rsi
movq 104(%rsp), %r8
movl $4194304, %edx # imm = 0x400000
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %r9
leaq 512(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 24(%rsp), %rax
movq 112(%rsp), %rcx
movq %rax, 96(%rsp)
movq %rcx, 88(%rsp)
movl $1074790400, 20(%rsp) # imm = 0x40100000
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z5saxpyPfS_f, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movq 104(%rsp), %r9
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movl $2097152, %eax # imm = 0x200000
movq 24(%rsp), %rcx
addq %rax, %rcx
addq 112(%rsp), %rax
movq %rcx, 96(%rsp)
movq %rax, 88(%rsp)
movl $1074790400, 20(%rsp) # imm = 0x40100000
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 88(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z5saxpyPfS_f, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %r8
movl $2097152, %r14d # imm = 0x200000
movl $2097152, %edx # imm = 0x200000
movl $3, %ecx
callq hipMemcpyAsync
movq 32(%rsp), %rdi
addq %r14, %rdi
addq 24(%rsp), %r14
movq 104(%rsp), %r8
movl $2097152, %edx # imm = 0x200000
movq %r14, %rsi
movl $3, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 104(%rsp), %rdi
callq hipStreamSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
subq %rbx, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 128(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $17, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 128(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_19
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%rbx)
je .LBB2_17
# %bb.16:
movzbl 67(%rbx), %ecx
jmp .LBB2_18
.LBB2_17:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 24(%rsp), %rdi
callq hipFree
movq 112(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipHostFree
movq 136(%rsp), %rdi
callq hipHostFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_19:
.cfi_def_cfa_offset 224
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9transposePfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5saxpyPfS_f, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9transposePfS_,@object # @_Z9transposePfS_
.section .rodata,"a",@progbits
.globl _Z9transposePfS_
.p2align 3, 0x0
_Z9transposePfS_:
.quad _Z24__device_stub__transposePfS_
.size _Z9transposePfS_, 8
.type _Z5saxpyPfS_f,@object # @_Z5saxpyPfS_f
.globl _Z5saxpyPfS_f
.p2align 3, 0x0
_Z5saxpyPfS_f:
.quad _Z20__device_stub__saxpyPfS_f
.size _Z5saxpyPfS_f, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Transpose time (s) - "
.size .L.str, 22
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "SAXPY time (s) - "
.size .L.str.1, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9transposePfS_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5saxpyPfS_f"
.size .L__unnamed_2, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__transposePfS_
.addrsig_sym _Z20__device_stub__saxpyPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9transposePfS_
.addrsig_sym _Z5saxpyPfS_f
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* Shade Alabsa
* Vector Summation Example from Cuda By Example
* CS 7172
* Edward Jung
* HW 3
* Most is taken from the example in the book with little changes.
*/
#include <stdio.h>
#define N (32 * 1024)
/*
These error functions is ripped from there example. I didn't want to include
their entire file nor did I want to just ignore all the errors.
*/
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
/*
Performs the summation of the vectors on the GPU
*/
__global__ void add(float *a, float *b, float *c) {
int tid = blockIdx.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += gridDim.x;
}
}
void printArray(float *c) {
for (int i = 0; i < N; i++) {
printf("%f ", c[i]);
if (i % 10 == 0) {
printf("\n");
}
}
printf("\n");
}
int main(void) {
float *a, *b, *c;
float *dev_a, *dev_b, *dev_c;
a = (float*)malloc( N * sizeof(float) );
b = (float*)malloc( N * sizeof(float) );
c = (float*)malloc( N * sizeof(float) );
HANDLE_ERROR( cudaMalloc((void**)&dev_a, N * sizeof(float) ));
HANDLE_ERROR( cudaMalloc((void**)&dev_b, N * sizeof(float) ));
HANDLE_ERROR( cudaMalloc((void**)&dev_c, N * sizeof(float) ));
for (int i = 0; i<N; i++) {
a[i] = i * 3.14;
b[i] = 2 * i;
}
HANDLE_ERROR( cudaMemcpy(dev_a, a, N * sizeof(float),
cudaMemcpyHostToDevice));
HANDLE_ERROR( cudaMemcpy(dev_b, b, N * sizeof(float),
cudaMemcpyHostToDevice));
add<<<512,1>>>(dev_a, dev_b, dev_c);
HANDLE_ERROR(cudaMemcpy(c, dev_c, N * sizeof(float),
cudaMemcpyDeviceToHost));
bool success = true;
for (int i = 0; i < N; i++) {
if (a[i] + b[i] != c[i]) {
printf( "Error %f + %f != %f\n", a[i], b[i], c[i]);
success = false;
}
}
if (success) {
printf("We did it!\n");
printArray(c);
}
HANDLE_ERROR( cudaFree(dev_a));
HANDLE_ERROR( cudaFree(dev_b));
HANDLE_ERROR( cudaFree(dev_c));
free(a);
free(b);
free(c);
return 0;
} | code for sm_80
Function : _Z3addPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R0, 0x7fff, PT ; /* 0x00007fff0000780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0060*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x040fe200078e0207 */
/*00b0*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.AND P0, PT, R0, 0x8000, PT ; /* 0x000080000000780c */
/* 0x000fe20003f06270 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*00f0*/ @!P0 BRA 0x50 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* Shade Alabsa
* Vector Summation Example from Cuda By Example
* CS 7172
* Edward Jung
* HW 3
* Most is taken from the example in the book with little changes.
*/
#include <stdio.h>
#define N (32 * 1024)
/*
These error functions is ripped from there example. I didn't want to include
their entire file nor did I want to just ignore all the errors.
*/
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
/*
Performs the summation of the vectors on the GPU
*/
__global__ void add(float *a, float *b, float *c) {
int tid = blockIdx.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += gridDim.x;
}
}
void printArray(float *c) {
for (int i = 0; i < N; i++) {
printf("%f ", c[i]);
if (i % 10 == 0) {
printf("\n");
}
}
printf("\n");
}
int main(void) {
float *a, *b, *c;
float *dev_a, *dev_b, *dev_c;
a = (float*)malloc( N * sizeof(float) );
b = (float*)malloc( N * sizeof(float) );
c = (float*)malloc( N * sizeof(float) );
HANDLE_ERROR( cudaMalloc((void**)&dev_a, N * sizeof(float) ));
HANDLE_ERROR( cudaMalloc((void**)&dev_b, N * sizeof(float) ));
HANDLE_ERROR( cudaMalloc((void**)&dev_c, N * sizeof(float) ));
for (int i = 0; i<N; i++) {
a[i] = i * 3.14;
b[i] = 2 * i;
}
HANDLE_ERROR( cudaMemcpy(dev_a, a, N * sizeof(float),
cudaMemcpyHostToDevice));
HANDLE_ERROR( cudaMemcpy(dev_b, b, N * sizeof(float),
cudaMemcpyHostToDevice));
add<<<512,1>>>(dev_a, dev_b, dev_c);
HANDLE_ERROR(cudaMemcpy(c, dev_c, N * sizeof(float),
cudaMemcpyDeviceToHost));
bool success = true;
for (int i = 0; i < N; i++) {
if (a[i] + b[i] != c[i]) {
printf( "Error %f + %f != %f\n", a[i], b[i], c[i]);
success = false;
}
}
if (success) {
printf("We did it!\n");
printArray(c);
}
HANDLE_ERROR( cudaFree(dev_a));
HANDLE_ERROR( cudaFree(dev_b));
HANDLE_ERROR( cudaFree(dev_c));
free(a);
free(b);
free(c);
return 0;
} | .file "tmpxft_0001aa86_00000000-6_vector_summation.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC1:
.string "%f "
.LC2:
.string "\n"
.text
.globl _Z10printArrayPf
.type _Z10printArrayPf, @function
_Z10printArrayPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
jmp .L11
.L10:
addq $1, %rbx
cmpq $32768, %rbx
je .L14
.L11:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L10
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L14:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10printArrayPf, .-_Z10printArrayPf
.globl _Z26__device_stub__Z3addPfS_S_PfS_S_
.type _Z26__device_stub__Z3addPfS_S_PfS_S_, @function
_Z26__device_stub__Z3addPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z3addPfS_S_PfS_S_, .-_Z26__device_stub__Z3addPfS_S_PfS_S_
.globl _Z3addPfS_S_
.type _Z3addPfS_S_, @function
_Z3addPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPfS_S_, .-_Z3addPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shade34321/cuda/master/vector_summation/vector_summation.cu"
.section .rodata.str1.1
.LC5:
.string "Error %f + %f != %f\n"
.LC6:
.string "We did it!\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $131072, %edi
call malloc@PLT
movq %rax, %r12
movl $131072, %edi
call malloc@PLT
movq %rax, %rbp
movl $131072, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $59, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $60, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $61, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
movsd .LC4(%rip), %xmm1
.L24:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rax,4)
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $32768, %rax
jne .L24
movl $1, %ecx
movl $131072, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $68, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, %ecx
movl $131072, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $70, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L25:
movl $2, %ecx
movl $131072, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $75, %edx
leaq .LC3(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
movl $1, %eax
leaq .LC5(%rip), %r14
jmp .L28
.L35:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPfS_S_PfS_S_
jmp .L25
.L31:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %eax
.L26:
addq $4, %rbx
cmpq $131072, %rbx
je .L36
.L28:
movss (%r12,%rbx), %xmm0
movss 0(%rbp,%rbx), %xmm1
movss 0(%r13,%rbx), %xmm2
movaps %xmm0, %xmm3
addss %xmm1, %xmm3
ucomiss %xmm2, %xmm3
jp .L31
je .L26
jmp .L31
.L36:
testb %al, %al
jne .L37
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $91, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $92, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $93, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call _Z10printArrayPf
jmp .L29
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z3addPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 1374389535
.long 1074339512
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* Shade Alabsa
* Vector Summation Example from Cuda By Example
* CS 7172
* Edward Jung
* HW 3
* Most is taken from the example in the book with little changes.
*/
#include <stdio.h>
#define N (32 * 1024)
/*
These error functions is ripped from there example. I didn't want to include
their entire file nor did I want to just ignore all the errors.
*/
static void HandleError( cudaError_t err, const char *file, int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
/*
Performs the summation of the vectors on the GPU
*/
__global__ void add(float *a, float *b, float *c) {
int tid = blockIdx.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += gridDim.x;
}
}
void printArray(float *c) {
for (int i = 0; i < N; i++) {
printf("%f ", c[i]);
if (i % 10 == 0) {
printf("\n");
}
}
printf("\n");
}
int main(void) {
float *a, *b, *c;
float *dev_a, *dev_b, *dev_c;
a = (float*)malloc( N * sizeof(float) );
b = (float*)malloc( N * sizeof(float) );
c = (float*)malloc( N * sizeof(float) );
HANDLE_ERROR( cudaMalloc((void**)&dev_a, N * sizeof(float) ));
HANDLE_ERROR( cudaMalloc((void**)&dev_b, N * sizeof(float) ));
HANDLE_ERROR( cudaMalloc((void**)&dev_c, N * sizeof(float) ));
for (int i = 0; i<N; i++) {
a[i] = i * 3.14;
b[i] = 2 * i;
}
HANDLE_ERROR( cudaMemcpy(dev_a, a, N * sizeof(float),
cudaMemcpyHostToDevice));
HANDLE_ERROR( cudaMemcpy(dev_b, b, N * sizeof(float),
cudaMemcpyHostToDevice));
add<<<512,1>>>(dev_a, dev_b, dev_c);
HANDLE_ERROR(cudaMemcpy(c, dev_c, N * sizeof(float),
cudaMemcpyDeviceToHost));
bool success = true;
for (int i = 0; i < N; i++) {
if (a[i] + b[i] != c[i]) {
printf( "Error %f + %f != %f\n", a[i], b[i], c[i]);
success = false;
}
}
if (success) {
printf("We did it!\n");
printArray(c);
}
HANDLE_ERROR( cudaFree(dev_a));
HANDLE_ERROR( cudaFree(dev_b));
HANDLE_ERROR( cudaFree(dev_c));
free(a);
free(b);
free(c);
return 0;
} | /*
* Shade Alabsa
* Vector Summation Example from Cuda By Example
* CS 7172
* Edward Jung
* HW 3
* Most is taken from the example in the book with little changes.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N (32 * 1024)
/*
These error functions is ripped from there example. I didn't want to include
their entire file nor did I want to just ignore all the errors.
*/
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
/*
Performs the summation of the vectors on the GPU
*/
__global__ void add(float *a, float *b, float *c) {
int tid = blockIdx.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += gridDim.x;
}
}
void printArray(float *c) {
for (int i = 0; i < N; i++) {
printf("%f ", c[i]);
if (i % 10 == 0) {
printf("\n");
}
}
printf("\n");
}
int main(void) {
float *a, *b, *c;
float *dev_a, *dev_b, *dev_c;
a = (float*)malloc( N * sizeof(float) );
b = (float*)malloc( N * sizeof(float) );
c = (float*)malloc( N * sizeof(float) );
HANDLE_ERROR( hipMalloc((void**)&dev_a, N * sizeof(float) ));
HANDLE_ERROR( hipMalloc((void**)&dev_b, N * sizeof(float) ));
HANDLE_ERROR( hipMalloc((void**)&dev_c, N * sizeof(float) ));
for (int i = 0; i<N; i++) {
a[i] = i * 3.14;
b[i] = 2 * i;
}
HANDLE_ERROR( hipMemcpy(dev_a, a, N * sizeof(float),
hipMemcpyHostToDevice));
HANDLE_ERROR( hipMemcpy(dev_b, b, N * sizeof(float),
hipMemcpyHostToDevice));
add<<<512,1>>>(dev_a, dev_b, dev_c);
HANDLE_ERROR(hipMemcpy(c, dev_c, N * sizeof(float),
hipMemcpyDeviceToHost));
bool success = true;
for (int i = 0; i < N; i++) {
if (a[i] + b[i] != c[i]) {
printf( "Error %f + %f != %f\n", a[i], b[i], c[i]);
success = false;
}
}
if (success) {
printf("We did it!\n");
printArray(c);
}
HANDLE_ERROR( hipFree(dev_a));
HANDLE_ERROR( hipFree(dev_b));
HANDLE_ERROR( hipFree(dev_c));
free(a);
free(b);
free(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* Shade Alabsa
* Vector Summation Example from Cuda By Example
* CS 7172
* Edward Jung
* HW 3
* Most is taken from the example in the book with little changes.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N (32 * 1024)
/*
These error functions is ripped from there example. I didn't want to include
their entire file nor did I want to just ignore all the errors.
*/
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
/*
Performs the summation of the vectors on the GPU
*/
__global__ void add(float *a, float *b, float *c) {
int tid = blockIdx.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += gridDim.x;
}
}
void printArray(float *c) {
for (int i = 0; i < N; i++) {
printf("%f ", c[i]);
if (i % 10 == 0) {
printf("\n");
}
}
printf("\n");
}
int main(void) {
float *a, *b, *c;
float *dev_a, *dev_b, *dev_c;
a = (float*)malloc( N * sizeof(float) );
b = (float*)malloc( N * sizeof(float) );
c = (float*)malloc( N * sizeof(float) );
HANDLE_ERROR( hipMalloc((void**)&dev_a, N * sizeof(float) ));
HANDLE_ERROR( hipMalloc((void**)&dev_b, N * sizeof(float) ));
HANDLE_ERROR( hipMalloc((void**)&dev_c, N * sizeof(float) ));
for (int i = 0; i<N; i++) {
a[i] = i * 3.14;
b[i] = 2 * i;
}
HANDLE_ERROR( hipMemcpy(dev_a, a, N * sizeof(float),
hipMemcpyHostToDevice));
HANDLE_ERROR( hipMemcpy(dev_b, b, N * sizeof(float),
hipMemcpyHostToDevice));
add<<<512,1>>>(dev_a, dev_b, dev_c);
HANDLE_ERROR(hipMemcpy(c, dev_c, N * sizeof(float),
hipMemcpyDeviceToHost));
bool success = true;
for (int i = 0; i < N; i++) {
if (a[i] + b[i] != c[i]) {
printf( "Error %f + %f != %f\n", a[i], b[i], c[i]);
success = false;
}
}
if (success) {
printf("We did it!\n");
printArray(c);
}
HANDLE_ERROR( hipFree(dev_a));
HANDLE_ERROR( hipFree(dev_b));
HANDLE_ERROR( hipFree(dev_c));
free(a);
free(b);
free(c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_
.globl _Z3addPfS_S_
.p2align 8
.type _Z3addPfS_S_,@function
_Z3addPfS_S_:
s_cmpk_gt_i32 s15, 0x7fff
s_cbranch_scc1 .LBB0_3
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_mov_b32 s2, s15
.p2align 6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[10:11], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s12, s4, s10
s_addc_u32 s13, s5, s11
s_add_u32 s14, s6, s10
s_addc_u32 s15, s7, s11
s_clause 0x1
global_load_b32 v1, v0, s[12:13]
global_load_b32 v2, v0, s[14:15]
s_add_u32 s10, s8, s10
s_addc_u32 s11, s9, s11
s_add_i32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s2, 0x8000
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[10:11]
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_, .Lfunc_end0-_Z3addPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
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.size: 2
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.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* Shade Alabsa
* Vector Summation Example from Cuda By Example
* CS 7172
* Edward Jung
* HW 3
* Most is taken from the example in the book with little changes.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N (32 * 1024)
/*
These error functions is ripped from there example. I didn't want to include
their entire file nor did I want to just ignore all the errors.
*/
static void HandleError( hipError_t err, const char *file, int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err), file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR(err) (HandleError(err, __FILE__, __LINE__))
/*
Performs the summation of the vectors on the GPU
*/
__global__ void add(float *a, float *b, float *c) {
int tid = blockIdx.x;
while(tid < N) {
c[tid] = a[tid] + b[tid];
tid += gridDim.x;
}
}
void printArray(float *c) {
for (int i = 0; i < N; i++) {
printf("%f ", c[i]);
if (i % 10 == 0) {
printf("\n");
}
}
printf("\n");
}
int main(void) {
float *a, *b, *c;
float *dev_a, *dev_b, *dev_c;
a = (float*)malloc( N * sizeof(float) );
b = (float*)malloc( N * sizeof(float) );
c = (float*)malloc( N * sizeof(float) );
HANDLE_ERROR( hipMalloc((void**)&dev_a, N * sizeof(float) ));
HANDLE_ERROR( hipMalloc((void**)&dev_b, N * sizeof(float) ));
HANDLE_ERROR( hipMalloc((void**)&dev_c, N * sizeof(float) ));
for (int i = 0; i<N; i++) {
a[i] = i * 3.14;
b[i] = 2 * i;
}
HANDLE_ERROR( hipMemcpy(dev_a, a, N * sizeof(float),
hipMemcpyHostToDevice));
HANDLE_ERROR( hipMemcpy(dev_b, b, N * sizeof(float),
hipMemcpyHostToDevice));
add<<<512,1>>>(dev_a, dev_b, dev_c);
HANDLE_ERROR(hipMemcpy(c, dev_c, N * sizeof(float),
hipMemcpyDeviceToHost));
bool success = true;
for (int i = 0; i < N; i++) {
if (a[i] + b[i] != c[i]) {
printf( "Error %f + %f != %f\n", a[i], b[i], c[i]);
success = false;
}
}
if (success) {
printf("We did it!\n");
printArray(c);
}
HANDLE_ERROR( hipFree(dev_a));
HANDLE_ERROR( hipFree(dev_b));
HANDLE_ERROR( hipFree(dev_c));
free(a);
free(b);
free(c);
return 0;
} | .text
.file "vector_summation.hip"
.globl _Z18__device_stub__addPfS_S_ # -- Begin function _Z18__device_stub__addPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_,@function
_Z18__device_stub__addPfS_S_: # @_Z18__device_stub__addPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_, .Lfunc_end0-_Z18__device_stub__addPfS_S_
.cfi_endproc
# -- End function
.globl _Z10printArrayPf # -- Begin function _Z10printArrayPf
.p2align 4, 0x90
.type _Z10printArrayPf,@function
_Z10printArrayPf: # @_Z10printArrayPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq $-131072, %r14 # imm = 0xFFFE0000
xorl %ebp, %ebp
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %r12d, %r12d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
decl %r12d
incl %ebp
addq $4, %r14
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %r13d
addl %r13d, %r13d
movss 131072(%rbx,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
addl %r12d, %r13d
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_3
.LBB1_4:
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z10printArrayPf, .Lfunc_end1-_Z10printArrayPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x40091eb851eb851f # double 3.1400000000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %rbx
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r14
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 16(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit36
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
testl %eax, %eax
jne .LBB2_32
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit38.preheader
xorl %eax, %eax
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_7: # %_ZL11HandleError10hipError_tPKci.exit38
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rbx,%rcx,4)
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm1, (%r14,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $32768, %rcx # imm = 0x8000
jne .LBB2_7
# %bb.8:
movq 24(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_9
# %bb.10: # %_ZL11HandleError10hipError_tPKci.exit40
movq 16(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.12: # %_ZL11HandleError10hipError_tPKci.exit42
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 511(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
movq 8(%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_33
# %bb.15: # %_ZL11HandleError10hipError_tPKci.exit44.preheader.preheader
movb $1, %al
xorl %r12d, %r12d
jmp .LBB2_16
.p2align 4, 0x90
.LBB2_18: # %_ZL11HandleError10hipError_tPKci.exit44
# in Loop: Header=BB2_16 Depth=1
incq %r12
cmpq $32768, %r12 # imm = 0x8000
je .LBB2_19
.LBB2_16: # %_ZL11HandleError10hipError_tPKci.exit44.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm3
addss %xmm1, %xmm3
movss (%r15,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm3
jne .LBB2_17
jnp .LBB2_18
.LBB2_17: # in Loop: Header=BB2_16 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm2, %xmm2
movl $.L.str.3, %edi
movb $3, %al
callq printf
xorl %eax, %eax
jmp .LBB2_18
.LBB2_19:
testb $1, %al
je .LBB2_25
# %bb.20:
movq %rbx, 32(%rsp) # 8-byte Spill
movq %r15, %rbx
movl $.Lstr, %edi
callq puts@PLT
movq $-131072, %r12 # imm = 0xFFFE0000
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB2_21
.p2align 4, 0x90
.LBB2_23: # in Loop: Header=BB2_21 Depth=1
decl %r13d
incl %ebp
addq $4, %r12
je .LBB2_24
.LBB2_21: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
movl $3435973837, %ecx # imm = 0xCCCCCCCD
imulq %rcx, %rax
shrq $35, %rax
leal (%rax,%rax,4), %r15d
addl %r15d, %r15d
movss 131072(%rbx,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
addl %r13d, %r15d
jne .LBB2_23
# %bb.22: # in Loop: Header=BB2_21 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_23
.LBB2_24: # %_Z10printArrayPf.exit
movl $10, %edi
callq putchar@PLT
movq %rbx, %r15
movq 32(%rsp), %rbx # 8-byte Reload
.LBB2_25:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_26
# %bb.27: # %_ZL11HandleError10hipError_tPKci.exit46
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_28
# %bb.29: # %_ZL11HandleError10hipError_tPKci.exit48
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_30
# %bb.31: # %_ZL11HandleError10hipError_tPKci.exit50
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $61, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $62, %ecx
jmp .LBB2_2
.LBB2_32:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $63, %ecx
jmp .LBB2_2
.LBB2_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $71, %ecx
jmp .LBB2_2
.LBB2_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $73, %ecx
jmp .LBB2_2
.LBB2_33:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $78, %ecx
jmp .LBB2_2
.LBB2_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $93, %ecx
jmp .LBB2_2
.LBB2_28:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $94, %ecx
jmp .LBB2_2
.LBB2_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $95, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_,@object # @_Z3addPfS_S_
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_
.p2align 3, 0x0
_Z3addPfS_S_:
.quad _Z18__device_stub__addPfS_S_
.size _Z3addPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shade34321/cuda/master/vector_summation/vector_summation.hip"
.size .L.str.2, 118
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error %f + %f != %f\n"
.size .L.str.3, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s in %s at line %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "We did it!"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GT.AND P0, PT, R0, 0x7fff, PT ; /* 0x00007fff0000780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0060*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0070*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*0080*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R6, R0.reuse, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x040fe200078e0207 */
/*00b0*/ IADD3 R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.AND P0, PT, R0, 0x8000, PT ; /* 0x000080000000780c */
/* 0x000fe20003f06270 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101904 */
/*00f0*/ @!P0 BRA 0x50 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPfS_S_
.globl _Z3addPfS_S_
.p2align 8
.type _Z3addPfS_S_,@function
_Z3addPfS_S_:
s_cmpk_gt_i32 s15, 0x7fff
s_cbranch_scc1 .LBB0_3
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b32 s0, s[0:1], 0x18
v_mov_b32_e32 v0, 0
s_mov_b32 s2, s15
.p2align 6
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s2, 31
s_lshl_b64 s[10:11], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s12, s4, s10
s_addc_u32 s13, s5, s11
s_add_u32 s14, s6, s10
s_addc_u32 s15, s7, s11
s_clause 0x1
global_load_b32 v1, v0, s[12:13]
global_load_b32 v2, v0, s[14:15]
s_add_u32 s10, s8, s10
s_addc_u32 s11, s9, s11
s_add_i32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s2, 0x8000
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[10:11]
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPfS_S_, .Lfunc_end0-_Z3addPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z3addPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001aa86_00000000-6_vector_summation.cudafe1.cpp"
.text
#APP
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB2057:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1
.LC1:
.string "%f "
.LC2:
.string "\n"
.text
.globl _Z10printArrayPf
.type _Z10printArrayPf, @function
_Z10printArrayPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
jmp .L11
.L10:
addq $1, %rbx
cmpq $32768, %rbx
je .L14
.L11:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $34, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
addl %eax, %eax
cmpl %ebx, %eax
jne .L10
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L10
.L14:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z10printArrayPf, .-_Z10printArrayPf
.globl _Z26__device_stub__Z3addPfS_S_PfS_S_
.type _Z26__device_stub__Z3addPfS_S_PfS_S_, @function
_Z26__device_stub__Z3addPfS_S_PfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z26__device_stub__Z3addPfS_S_PfS_S_, .-_Z26__device_stub__Z3addPfS_S_PfS_S_
.globl _Z3addPfS_S_
.type _Z3addPfS_S_, @function
_Z3addPfS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z3addPfS_S_, .-_Z3addPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/ubuntu/Datasets/stackv2/train-structured/shade34321/cuda/master/vector_summation/vector_summation.cu"
.section .rodata.str1.1
.LC5:
.string "Error %f + %f != %f\n"
.LC6:
.string "We did it!\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $131072, %edi
call malloc@PLT
movq %rax, %r12
movl $131072, %edi
call malloc@PLT
movq %rax, %rbp
movl $131072, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $59, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 16(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $60, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq 24(%rsp), %rdi
movl $131072, %esi
call cudaMalloc@PLT
movl %eax, %edi
movl $61, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %eax
movsd .LC4(%rip), %xmm1
.L24:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
mulsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rax,4)
leal (%rax,%rax), %edx
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $32768, %rax
jne .L24
movl $1, %ecx
movl $131072, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $68, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, %ecx
movl $131072, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $70, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $512, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L25:
movl $2, %ecx
movl $131072, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
movl $75, %edx
leaq .LC3(%rip), %rsi
call _ZL11HandleError9cudaErrorPKci
movl $0, %ebx
movl $1, %eax
leaq .LC5(%rip), %r14
jmp .L28
.L35:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3addPfS_S_PfS_S_
jmp .L25
.L31:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
movq %r14, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %eax
.L26:
addq $4, %rbx
cmpq $131072, %rbx
je .L36
.L28:
movss (%r12,%rbx), %xmm0
movss 0(%rbp,%rbx), %xmm1
movss 0(%r13,%rbx), %xmm2
movaps %xmm0, %xmm3
addss %xmm1, %xmm3
ucomiss %xmm2, %xmm3
jp .L31
je .L26
jmp .L31
.L36:
testb %al, %al
jne .L37
.L29:
movq 8(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $91, %edx
leaq .LC3(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 16(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $92, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq 24(%rsp), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $93, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call _Z10printArrayPf
jmp .L29
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z3addPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 1374389535
.long 1074339512
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_summation.hip"
.globl _Z18__device_stub__addPfS_S_ # -- Begin function _Z18__device_stub__addPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPfS_S_,@function
_Z18__device_stub__addPfS_S_: # @_Z18__device_stub__addPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPfS_S_, .Lfunc_end0-_Z18__device_stub__addPfS_S_
.cfi_endproc
# -- End function
.globl _Z10printArrayPf # -- Begin function _Z10printArrayPf
.p2align 4, 0x90
.type _Z10printArrayPf,@function
_Z10printArrayPf: # @_Z10printArrayPf
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, %rbx
movq $-131072, %r14 # imm = 0xFFFE0000
xorl %ebp, %ebp
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %r12d, %r12d
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_3: # in Loop: Header=BB1_1 Depth=1
decl %r12d
incl %ebp
addq $4, %r14
je .LBB1_4
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
imulq %r15, %rax
shrq $35, %rax
leal (%rax,%rax,4), %r13d
addl %r13d, %r13d
movss 131072(%rbx,%r14), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
addl %r12d, %r13d
jne .LBB1_3
# %bb.2: # in Loop: Header=BB1_1 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB1_3
.LBB1_4:
movl $10, %edi
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z10printArrayPf, .Lfunc_end1-_Z10printArrayPf
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x40091eb851eb851f # double 3.1400000000000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %rbx
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r14
movl $131072, %edi # imm = 0x20000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
leaq 16(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit36
leaq 8(%rsp), %rdi
movl $131072, %esi # imm = 0x20000
callq hipMalloc
testl %eax, %eax
jne .LBB2_32
# %bb.6: # %_ZL11HandleError10hipError_tPKci.exit38.preheader
xorl %eax, %eax
movsd .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_7: # %_ZL11HandleError10hipError_tPKci.exit38
# =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2sd %ecx, %xmm1
mulsd %xmm0, %xmm1
cvtsd2ss %xmm1, %xmm1
movss %xmm1, (%rbx,%rcx,4)
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
movss %xmm1, (%r14,%rcx,4)
incq %rcx
addl $2, %eax
cmpq $32768, %rcx # imm = 0x8000
jne .LBB2_7
# %bb.8:
movq 24(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_9
# %bb.10: # %_ZL11HandleError10hipError_tPKci.exit40
movq 16(%rsp), %rdi
movl $131072, %edx # imm = 0x20000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_11
# %bb.12: # %_ZL11HandleError10hipError_tPKci.exit42
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 511(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
movq 8(%rsp), %rsi
movl $131072, %edx # imm = 0x20000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_33
# %bb.15: # %_ZL11HandleError10hipError_tPKci.exit44.preheader.preheader
movb $1, %al
xorl %r12d, %r12d
jmp .LBB2_16
.p2align 4, 0x90
.LBB2_18: # %_ZL11HandleError10hipError_tPKci.exit44
# in Loop: Header=BB2_16 Depth=1
incq %r12
cmpq $32768, %r12 # imm = 0x8000
je .LBB2_19
.LBB2_16: # %_ZL11HandleError10hipError_tPKci.exit44.preheader
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r14,%r12,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm0, %xmm3
addss %xmm1, %xmm3
movss (%r15,%r12,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm3
jne .LBB2_17
jnp .LBB2_18
.LBB2_17: # in Loop: Header=BB2_16 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
cvtss2sd %xmm2, %xmm2
movl $.L.str.3, %edi
movb $3, %al
callq printf
xorl %eax, %eax
jmp .LBB2_18
.LBB2_19:
testb $1, %al
je .LBB2_25
# %bb.20:
movq %rbx, 32(%rsp) # 8-byte Spill
movq %r15, %rbx
movl $.Lstr, %edi
callq puts@PLT
movq $-131072, %r12 # imm = 0xFFFE0000
xorl %ebp, %ebp
xorl %r13d, %r13d
jmp .LBB2_21
.p2align 4, 0x90
.LBB2_23: # in Loop: Header=BB2_21 Depth=1
decl %r13d
incl %ebp
addq $4, %r12
je .LBB2_24
.LBB2_21: # =>This Inner Loop Header: Depth=1
movl %ebp, %eax
movl $3435973837, %ecx # imm = 0xCCCCCCCD
imulq %rcx, %rax
shrq $35, %rax
leal (%rax,%rax,4), %r15d
addl %r15d, %r15d
movss 131072(%rbx,%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
addl %r13d, %r15d
jne .LBB2_23
# %bb.22: # in Loop: Header=BB2_21 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_23
.LBB2_24: # %_Z10printArrayPf.exit
movl $10, %edi
callq putchar@PLT
movq %rbx, %r15
movq 32(%rsp), %rbx # 8-byte Reload
.LBB2_25:
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_26
# %bb.27: # %_ZL11HandleError10hipError_tPKci.exit46
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_28
# %bb.29: # %_ZL11HandleError10hipError_tPKci.exit48
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_30
# %bb.31: # %_ZL11HandleError10hipError_tPKci.exit50
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_1:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $61, %ecx
jmp .LBB2_2
.LBB2_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $62, %ecx
jmp .LBB2_2
.LBB2_32:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $63, %ecx
jmp .LBB2_2
.LBB2_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $71, %ecx
jmp .LBB2_2
.LBB2_11:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $73, %ecx
jmp .LBB2_2
.LBB2_33:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $78, %ecx
jmp .LBB2_2
.LBB2_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $93, %ecx
jmp .LBB2_2
.LBB2_28:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $94, %ecx
jmp .LBB2_2
.LBB2_30:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %edi
movl $.L.str.2, %edx
movq %rax, %rsi
movl $95, %ecx
.LBB2_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPfS_S_,@object # @_Z3addPfS_S_
.section .rodata,"a",@progbits
.globl _Z3addPfS_S_
.p2align 3, 0x0
_Z3addPfS_S_:
.quad _Z18__device_stub__addPfS_S_
.size _Z3addPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/shade34321/cuda/master/vector_summation/vector_summation.hip"
.size .L.str.2, 118
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Error %f + %f != %f\n"
.size .L.str.3, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%s in %s at line %d\n"
.size .L.str.5, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "We did it!"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Threshold-based Contrasting GPU implementation
//
#include <unistd.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 128
// CUDA kernel declaration
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh);
// C/C++ Wrapper
unsigned char *gpu_flow_recogu8_bitmap(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
// Host memory
unsigned char *host_u8res;
// Device memory
unsigned char *dev_u8data;
unsigned char *dev_u8res;
size_t size = N * sizeof(unsigned char);
host_u8res = (unsigned char *)malloc(size);
// Allocated device memory
cudaMalloc((void **)&dev_u8data, size);
cudaMalloc((void **)&dev_u8res, size);
// Upload data to device memory
cudaMemcpy(dev_u8data, u8data, size, cudaMemcpyHostToDevice);
cuda_flow_bitmap_kernel<<<((N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dev_u8data, dev_u8res, N, thresh);
cudaMemcpy(host_u8res, dev_u8res, size, cudaMemcpyDeviceToHost);
cudaFree(dev_u8data);
cudaFree(dev_u8res);
return host_u8res;
}
// u8res contains a binary map of optical flow regions with motion intensity over the threshold
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
int idx = threadIdx.x + (blockDim.x *blockIdx.x);
if (idx < N) {
if (u8data[idx] >= thresh) {
u8res[idx] = 1;
}
else {
u8res[idx] = 0;
}
}
} | code for sm_80
Function : _Z23cuda_flow_bitmap_kernelPhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe20000011402 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R5, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003057a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IADD3 R2, P1, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe20007f3e0ff */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3.X R3, R3, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0003037a10 */
/* 0x000fe40000ffe4ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x004fda0003f06070 */
/*00f0*/ @P0 STG.E.U8 [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e2000c101104 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Threshold-based Contrasting GPU implementation
//
#include <unistd.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 128
// CUDA kernel declaration
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh);
// C/C++ Wrapper
unsigned char *gpu_flow_recogu8_bitmap(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
// Host memory
unsigned char *host_u8res;
// Device memory
unsigned char *dev_u8data;
unsigned char *dev_u8res;
size_t size = N * sizeof(unsigned char);
host_u8res = (unsigned char *)malloc(size);
// Allocated device memory
cudaMalloc((void **)&dev_u8data, size);
cudaMalloc((void **)&dev_u8res, size);
// Upload data to device memory
cudaMemcpy(dev_u8data, u8data, size, cudaMemcpyHostToDevice);
cuda_flow_bitmap_kernel<<<((N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dev_u8data, dev_u8res, N, thresh);
cudaMemcpy(host_u8res, dev_u8res, size, cudaMemcpyDeviceToHost);
cudaFree(dev_u8data);
cudaFree(dev_u8res);
return host_u8res;
}
// u8res contains a binary map of optical flow regions with motion intensity over the threshold
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
int idx = threadIdx.x + (blockDim.x *blockIdx.x);
if (idx < N) {
if (u8data[idx] >= thresh) {
u8res[idx] = 1;
}
else {
u8res[idx] = 0;
}
}
} | .file "tmpxft_0003bb70_00000000-6_gpu_flow_recogu8.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2043:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2043:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj
.type _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj, @function
_Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj:
.LFB2065:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23cuda_flow_bitmap_kernelPhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj, .-_Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj
.globl _Z23cuda_flow_bitmap_kernelPhS_jj
.type _Z23cuda_flow_bitmap_kernelPhS_jj, @function
_Z23cuda_flow_bitmap_kernelPhS_jj:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z23cuda_flow_bitmap_kernelPhS_jj, .-_Z23cuda_flow_bitmap_kernelPhS_jj
.globl _Z23gpu_flow_recogu8_bitmapPhS_jj
.type _Z23gpu_flow_recogu8_bitmapPhS_jj, @function
_Z23gpu_flow_recogu8_bitmapPhS_jj:
.LFB2040:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movl %edx, %ebp
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edx, %ebx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
leal 127(%rbp), %eax
shrl $7, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movq %r12, %rax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r13d, %ecx
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2040:
.size _Z23gpu_flow_recogu8_bitmapPhS_jj, .-_Z23gpu_flow_recogu8_bitmapPhS_jj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cuda_flow_bitmap_kernelPhS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cuda_flow_bitmap_kernelPhS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Threshold-based Contrasting GPU implementation
//
#include <unistd.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 128
// CUDA kernel declaration
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh);
// C/C++ Wrapper
unsigned char *gpu_flow_recogu8_bitmap(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
// Host memory
unsigned char *host_u8res;
// Device memory
unsigned char *dev_u8data;
unsigned char *dev_u8res;
size_t size = N * sizeof(unsigned char);
host_u8res = (unsigned char *)malloc(size);
// Allocated device memory
cudaMalloc((void **)&dev_u8data, size);
cudaMalloc((void **)&dev_u8res, size);
// Upload data to device memory
cudaMemcpy(dev_u8data, u8data, size, cudaMemcpyHostToDevice);
cuda_flow_bitmap_kernel<<<((N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dev_u8data, dev_u8res, N, thresh);
cudaMemcpy(host_u8res, dev_u8res, size, cudaMemcpyDeviceToHost);
cudaFree(dev_u8data);
cudaFree(dev_u8res);
return host_u8res;
}
// u8res contains a binary map of optical flow regions with motion intensity over the threshold
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
int idx = threadIdx.x + (blockDim.x *blockIdx.x);
if (idx < N) {
if (u8data[idx] >= thresh) {
u8res[idx] = 1;
}
else {
u8res[idx] = 0;
}
}
} | //
// Threshold-based Contrasting GPU implementation
//
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 128
// CUDA kernel declaration
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh);
// C/C++ Wrapper
unsigned char *gpu_flow_recogu8_bitmap(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
// Host memory
unsigned char *host_u8res;
// Device memory
unsigned char *dev_u8data;
unsigned char *dev_u8res;
size_t size = N * sizeof(unsigned char);
host_u8res = (unsigned char *)malloc(size);
// Allocated device memory
hipMalloc((void **)&dev_u8data, size);
hipMalloc((void **)&dev_u8res, size);
// Upload data to device memory
hipMemcpy(dev_u8data, u8data, size, hipMemcpyHostToDevice);
cuda_flow_bitmap_kernel<<<((N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dev_u8data, dev_u8res, N, thresh);
hipMemcpy(host_u8res, dev_u8res, size, hipMemcpyDeviceToHost);
hipFree(dev_u8data);
hipFree(dev_u8res);
return host_u8res;
}
// u8res contains a binary map of optical flow regions with motion intensity over the threshold
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
int idx = threadIdx.x + (blockDim.x *blockIdx.x);
if (idx < N) {
if (u8data[idx] >= thresh) {
u8res[idx] = 1;
}
else {
u8res[idx] = 0;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Threshold-based Contrasting GPU implementation
//
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 128
// CUDA kernel declaration
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh);
// C/C++ Wrapper
unsigned char *gpu_flow_recogu8_bitmap(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
// Host memory
unsigned char *host_u8res;
// Device memory
unsigned char *dev_u8data;
unsigned char *dev_u8res;
size_t size = N * sizeof(unsigned char);
host_u8res = (unsigned char *)malloc(size);
// Allocated device memory
hipMalloc((void **)&dev_u8data, size);
hipMalloc((void **)&dev_u8res, size);
// Upload data to device memory
hipMemcpy(dev_u8data, u8data, size, hipMemcpyHostToDevice);
cuda_flow_bitmap_kernel<<<((N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dev_u8data, dev_u8res, N, thresh);
hipMemcpy(host_u8res, dev_u8res, size, hipMemcpyDeviceToHost);
hipFree(dev_u8data);
hipFree(dev_u8res);
return host_u8res;
}
// u8res contains a binary map of optical flow regions with motion intensity over the threshold
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
int idx = threadIdx.x + (blockDim.x *blockIdx.x);
if (idx < N) {
if (u8data[idx] >= thresh) {
u8res[idx] = 1;
}
else {
u8res[idx] = 0;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cuda_flow_bitmap_kernelPhS_jj
.globl _Z23cuda_flow_bitmap_kernelPhS_jj
.p2align 8
.type _Z23cuda_flow_bitmap_kernelPhS_jj,@function
_Z23cuda_flow_bitmap_kernelPhS_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v1
s_load_b32 s0, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_le_u32_e32 vcc_lo, s0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cuda_flow_bitmap_kernelPhS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cuda_flow_bitmap_kernelPhS_jj, .Lfunc_end0-_Z23cuda_flow_bitmap_kernelPhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cuda_flow_bitmap_kernelPhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23cuda_flow_bitmap_kernelPhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Threshold-based Contrasting GPU implementation
//
#include <hip/hip_runtime.h>
#include <unistd.h>
#include <stdlib.h>
#define THREADS_PER_BLOCK 128
// CUDA kernel declaration
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh);
// C/C++ Wrapper
unsigned char *gpu_flow_recogu8_bitmap(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
// Host memory
unsigned char *host_u8res;
// Device memory
unsigned char *dev_u8data;
unsigned char *dev_u8res;
size_t size = N * sizeof(unsigned char);
host_u8res = (unsigned char *)malloc(size);
// Allocated device memory
hipMalloc((void **)&dev_u8data, size);
hipMalloc((void **)&dev_u8res, size);
// Upload data to device memory
hipMemcpy(dev_u8data, u8data, size, hipMemcpyHostToDevice);
cuda_flow_bitmap_kernel<<<((N + THREADS_PER_BLOCK - 1) / THREADS_PER_BLOCK), THREADS_PER_BLOCK>>>(dev_u8data, dev_u8res, N, thresh);
hipMemcpy(host_u8res, dev_u8res, size, hipMemcpyDeviceToHost);
hipFree(dev_u8data);
hipFree(dev_u8res);
return host_u8res;
}
// u8res contains a binary map of optical flow regions with motion intensity over the threshold
__global__ void cuda_flow_bitmap_kernel(unsigned char *u8data, unsigned char *u8res, unsigned int N, unsigned int thresh)
{
int idx = threadIdx.x + (blockDim.x *blockIdx.x);
if (idx < N) {
if (u8data[idx] >= thresh) {
u8res[idx] = 1;
}
else {
u8res[idx] = 0;
}
}
} | .text
.file "gpu_flow_recogu8.hip"
.globl _Z23gpu_flow_recogu8_bitmapPhS_jj # -- Begin function _Z23gpu_flow_recogu8_bitmapPhS_jj
.p2align 4, 0x90
.type _Z23gpu_flow_recogu8_bitmapPhS_jj,@function
_Z23gpu_flow_recogu8_bitmapPhS_jj: # @_Z23gpu_flow_recogu8_bitmapPhS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rdi, %r12
movl %edx, %r14d
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 127(%r15), %edi
shrl $7, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
movl %ebp, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23cuda_flow_bitmap_kernelPhS_jj, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23gpu_flow_recogu8_bitmapPhS_jj, .Lfunc_end0-_Z23gpu_flow_recogu8_bitmapPhS_jj
.cfi_endproc
# -- End function
.globl _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj # -- Begin function _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.p2align 4, 0x90
.type _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj,@function
_Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj: # @_Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23cuda_flow_bitmap_kernelPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj, .Lfunc_end1-_Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cuda_flow_bitmap_kernelPhS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23cuda_flow_bitmap_kernelPhS_jj,@object # @_Z23cuda_flow_bitmap_kernelPhS_jj
.section .rodata,"a",@progbits
.globl _Z23cuda_flow_bitmap_kernelPhS_jj
.p2align 3, 0x0
_Z23cuda_flow_bitmap_kernelPhS_jj:
.quad _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.size _Z23cuda_flow_bitmap_kernelPhS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23cuda_flow_bitmap_kernelPhS_jj"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23cuda_flow_bitmap_kernelPhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23cuda_flow_bitmap_kernelPhS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe20000011402 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IADD3 R4, P0, R2, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ IADD3.X R5, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003057a10 */
/* 0x000fca00007fe4ff */
/*00a0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IADD3 R2, P1, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fe20007f3e0ff */
/*00c0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc600078e00ff */
/*00d0*/ IADD3.X R3, R3, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0003037a10 */
/* 0x000fe40000ffe4ff */
/*00e0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x174], PT ; /* 0x00005d0004007a0c */
/* 0x004fda0003f06070 */
/*00f0*/ @P0 STG.E.U8 [R2.64], R0 ; /* 0x0000000002000986 */
/* 0x0001e2000c101104 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ STG.E.U8 [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101104 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23cuda_flow_bitmap_kernelPhS_jj
.globl _Z23cuda_flow_bitmap_kernelPhS_jj
.p2align 8
.type _Z23cuda_flow_bitmap_kernelPhS_jj,@function
_Z23cuda_flow_bitmap_kernelPhS_jj:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v4, 31, v1
s_load_b32 s0, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v4, vcc_lo
global_load_u8 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_le_u32_e32 vcc_lo, s0, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23cuda_flow_bitmap_kernelPhS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23cuda_flow_bitmap_kernelPhS_jj, .Lfunc_end0-_Z23cuda_flow_bitmap_kernelPhS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23cuda_flow_bitmap_kernelPhS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z23cuda_flow_bitmap_kernelPhS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003bb70_00000000-6_gpu_flow_recogu8.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2043:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2043:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj
.type _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj, @function
_Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj:
.LFB2065:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z23cuda_flow_bitmap_kernelPhS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj, .-_Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj
.globl _Z23cuda_flow_bitmap_kernelPhS_jj
.type _Z23cuda_flow_bitmap_kernelPhS_jj, @function
_Z23cuda_flow_bitmap_kernelPhS_jj:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _Z23cuda_flow_bitmap_kernelPhS_jj, .-_Z23cuda_flow_bitmap_kernelPhS_jj
.globl _Z23gpu_flow_recogu8_bitmapPhS_jj
.type _Z23gpu_flow_recogu8_bitmapPhS_jj, @function
_Z23gpu_flow_recogu8_bitmapPhS_jj:
.LFB2040:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r14
movl %edx, %ebp
movl %ecx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edx, %ebx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 28(%rsp)
movl $1, 32(%rsp)
leal 127(%rbp), %eax
shrl $7, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
movq %r12, %rax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r13d, %ecx
movl %ebp, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z47__device_stub__Z23cuda_flow_bitmap_kernelPhS_jjPhS_jj
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2040:
.size _Z23gpu_flow_recogu8_bitmapPhS_jj, .-_Z23gpu_flow_recogu8_bitmapPhS_jj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23cuda_flow_bitmap_kernelPhS_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23cuda_flow_bitmap_kernelPhS_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_flow_recogu8.hip"
.globl _Z23gpu_flow_recogu8_bitmapPhS_jj # -- Begin function _Z23gpu_flow_recogu8_bitmapPhS_jj
.p2align 4, 0x90
.type _Z23gpu_flow_recogu8_bitmapPhS_jj,@function
_Z23gpu_flow_recogu8_bitmapPhS_jj: # @_Z23gpu_flow_recogu8_bitmapPhS_jj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebp
movl %edx, %r15d
movq %rdi, %r12
movl %edx, %r14d
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
leal 127(%r15), %edi
shrl $7, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $128, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl %r15d, 28(%rsp)
movl %ebp, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23cuda_flow_bitmap_kernelPhS_jj, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rax
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z23gpu_flow_recogu8_bitmapPhS_jj, .Lfunc_end0-_Z23gpu_flow_recogu8_bitmapPhS_jj
.cfi_endproc
# -- End function
.globl _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj # -- Begin function _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.p2align 4, 0x90
.type _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj,@function
_Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj: # @_Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z23cuda_flow_bitmap_kernelPhS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj, .Lfunc_end1-_Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23cuda_flow_bitmap_kernelPhS_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23cuda_flow_bitmap_kernelPhS_jj,@object # @_Z23cuda_flow_bitmap_kernelPhS_jj
.section .rodata,"a",@progbits
.globl _Z23cuda_flow_bitmap_kernelPhS_jj
.p2align 3, 0x0
_Z23cuda_flow_bitmap_kernelPhS_jj:
.quad _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.size _Z23cuda_flow_bitmap_kernelPhS_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23cuda_flow_bitmap_kernelPhS_jj"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__cuda_flow_bitmap_kernelPhS_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23cuda_flow_bitmap_kernelPhS_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdlib>
#include <cstdio>
#include <cassert>
#include <iostream>
#define ULI unsigned long int
__global__ void fibonacci_kernel(ULI* a, int start) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int index = i + start;
if (i < 2 * start - 1)
a[index] = (a[start - 2] * a[i]) + (a[start - 1] * a[i + 1]);
}
class FibonacciDynamicProgramming {
public:
int numElements, sizeInBytes;
explicit FibonacciDynamicProgramming(int numElements);
void run(int numThreads) const;
};
FibonacciDynamicProgramming::FibonacciDynamicProgramming(int numElements) {
this->numElements = numElements;
this->sizeInBytes = numElements * sizeof(ULI);
}
void FibonacciDynamicProgramming::run(int numThreads) const {
int deviceId = cudaGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", cudaCpuDeviceId);
ULI startingElements[3] = {1, 1, 2};
ULI* deviceArray;
ULI resultArray[numThreads];
cudaMalloc(&deviceArray, sizeInBytes);
cudaMemcpy(deviceArray, startingElements, sizeof(startingElements), cudaMemcpyHostToDevice);
unsigned int start = 3;
while (start <= numElements / 2 ) {
unsigned int numBlocks = (start - 1) / numThreads;
if ((start - 1) % numThreads != 0)
numBlocks++;
fibonacci_kernel<<<numBlocks, numThreads>>>(deviceArray, start);
start = 2 * start - 1;
}
cudaMemcpy(resultArray, deviceArray, sizeInBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < numElements; i++) {
printf("%d:\t%lu \n", i + 1, resultArray[i]);
}
cudaFree(deviceArray);
}
int main() {
FibonacciDynamicProgramming program(16);
program.run(16);
} | code for sm_80
Function : _Z16fibonacci_kernelPmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fe200078e0200 */
/*0050*/ LEA R0, R5, 0xffffffff, 0x1 ; /* 0xffffffff05007811 */
/* 0x000fc800078e08ff */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff007435 */
/* 0x000fe200000001ff */
/*0090*/ IADD3 R5, R5, -0x2, RZ ; /* 0xfffffffe05057810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IADD3 R11, R3, 0x1, RZ ; /* 0x00000001030b7810 */
/* 0x000fce0007ffe0ff */
/*00c0*/ IMAD.WIDE.U32 R6, R3, R0, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0000 */
/*00d0*/ IMAD.WIDE R4, R5, R0.reuse, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x080fe400078e0200 */
/*00e0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ IMAD.WIDE.U32 R10, R11, R0, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fc600078e0000 */
/*0110*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ee8000c1e1b00 */
/*0120*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1b00 */
/*0130*/ IADD3 R3, R3, c[0x0][0x168], RZ ; /* 0x00005a0003037a10 */
/* 0x000fca0007ffe0ff */
/*0140*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0000 */
/*0150*/ IMAD R17, R7, R8.reuse, RZ ; /* 0x0000000807117224 */
/* 0x084fe400078e02ff */
/*0160*/ IMAD.WIDE.U32 R14, R6, R8, RZ ; /* 0x00000008060e7225 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD R17, R6, R9, R17 ; /* 0x0000000906117224 */
/* 0x000fe400078e0211 */
/*0180*/ IMAD R9, R11, R12, RZ ; /* 0x0000000c0b097224 */
/* 0x008fc600078e02ff */
/*0190*/ IADD3 R15, R15, R17, RZ ; /* 0x000000110f0f7210 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD R9, R10, R13, R9 ; /* 0x0000000d0a097224 */
/* 0x000fc800078e0209 */
/*01b0*/ IMAD.WIDE.U32 R12, R10, R12, R14 ; /* 0x0000000c0a0c7225 */
/* 0x000fca00078e000e */
/*01c0*/ IADD3 R13, R13, R9, RZ ; /* 0x000000090d0d7210 */
/* 0x000fca0007ffe0ff */
/*01d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101b04 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdlib>
#include <cstdio>
#include <cassert>
#include <iostream>
#define ULI unsigned long int
__global__ void fibonacci_kernel(ULI* a, int start) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int index = i + start;
if (i < 2 * start - 1)
a[index] = (a[start - 2] * a[i]) + (a[start - 1] * a[i + 1]);
}
class FibonacciDynamicProgramming {
public:
int numElements, sizeInBytes;
explicit FibonacciDynamicProgramming(int numElements);
void run(int numThreads) const;
};
FibonacciDynamicProgramming::FibonacciDynamicProgramming(int numElements) {
this->numElements = numElements;
this->sizeInBytes = numElements * sizeof(ULI);
}
void FibonacciDynamicProgramming::run(int numThreads) const {
int deviceId = cudaGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", cudaCpuDeviceId);
ULI startingElements[3] = {1, 1, 2};
ULI* deviceArray;
ULI resultArray[numThreads];
cudaMalloc(&deviceArray, sizeInBytes);
cudaMemcpy(deviceArray, startingElements, sizeof(startingElements), cudaMemcpyHostToDevice);
unsigned int start = 3;
while (start <= numElements / 2 ) {
unsigned int numBlocks = (start - 1) / numThreads;
if ((start - 1) % numThreads != 0)
numBlocks++;
fibonacci_kernel<<<numBlocks, numThreads>>>(deviceArray, start);
start = 2 * start - 1;
}
cudaMemcpy(resultArray, deviceArray, sizeInBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < numElements; i++) {
printf("%d:\t%lu \n", i + 1, resultArray[i]);
}
cudaFree(deviceArray);
}
int main() {
FibonacciDynamicProgramming program(16);
program.run(16);
} | .file "tmpxft_000f723a_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN27FibonacciDynamicProgrammingC2Ei
.type _ZN27FibonacciDynamicProgrammingC2Ei, @function
_ZN27FibonacciDynamicProgrammingC2Ei:
.LFB3670:
.cfi_startproc
endbr64
movl %esi, (%rdi)
sall $3, %esi
movl %esi, 4(%rdi)
ret
.cfi_endproc
.LFE3670:
.size _ZN27FibonacciDynamicProgrammingC2Ei, .-_ZN27FibonacciDynamicProgrammingC2Ei
.globl _ZN27FibonacciDynamicProgrammingC1Ei
.set _ZN27FibonacciDynamicProgrammingC1Ei,_ZN27FibonacciDynamicProgrammingC2Ei
.globl _Z37__device_stub__Z16fibonacci_kernelPmiPmi
.type _Z37__device_stub__Z16fibonacci_kernelPmiPmi, @function
_Z37__device_stub__Z16fibonacci_kernelPmiPmi:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16fibonacci_kernelPmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z37__device_stub__Z16fibonacci_kernelPmiPmi, .-_Z37__device_stub__Z16fibonacci_kernelPmiPmi
.globl _Z16fibonacci_kernelPmi
.type _Z16fibonacci_kernelPmi, @function
_Z16fibonacci_kernelPmi:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16fibonacci_kernelPmiPmi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z16fibonacci_kernelPmi, .-_Z16fibonacci_kernelPmi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPU Device ID: %d\n"
.LC1:
.string "CPU Device ID: %d\n\n"
.LC2:
.string "%d:\t%lu \n"
.text
.align 2
.globl _ZNK27FibonacciDynamicProgramming3runEi
.type _ZNK27FibonacciDynamicProgramming3runEi, @function
_ZNK27FibonacciDynamicProgramming3runEi:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $80, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %rdi, %r14
movl %esi, %r12d
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq -100(%rbp), %rdi
call cudaGetDevice@PLT
movl %eax, %edx
movl %eax, -100(%rbp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $1, -64(%rbp)
movq $1, -56(%rbp)
movq $2, -48(%rbp)
movslq %r12d, %rax
leaq 15(,%rax,8), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L13:
cmpq %rdx, %rsp
je .L14
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L13
.L14:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L15
orq $0, -8(%rsp,%rax)
.L15:
movq %rsp, %r13
movslq 4(%r14), %rsi
leaq -96(%rbp), %rdi
call cudaMalloc@PLT
leaq -64(%rbp), %rsi
movl $1, %ecx
movl $24, %edx
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl (%r14), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
cmpl $5, %eax
jbe .L16
movl $3, %ebx
jmp .L19
.L18:
leal -1(%rbx,%rbx), %ebx
movl (%r14), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
cmpl %ebx, %eax
jb .L16
.L19:
leal -1(%rbx), %eax
movl $0, %edx
divl %r12d
cmpl $1, %edx
sbbl $-1, %eax
movl %r12d, -76(%rbp)
movl $1, -72(%rbp)
movl $1, -68(%rbp)
movl %eax, -88(%rbp)
movl $1, -84(%rbp)
movl $1, -80(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -76(%rbp), %rdx
movl $1, %ecx
movq -88(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movl %ebx, %esi
movq -96(%rbp), %rdi
call _Z37__device_stub__Z16fibonacci_kernelPmiPmi
jmp .L18
.L16:
movslq 4(%r14), %rdx
movl $2, %ecx
movq -96(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $0, (%r14)
jle .L20
movl $0, %ebx
leaq .LC2(%rip), %r12
.L21:
addl $1, %ebx
movq 0(%r13), %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %r13
cmpl (%r14), %ebx
jl .L21
.L20:
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L26
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _ZNK27FibonacciDynamicProgramming3runEi, .-_ZNK27FibonacciDynamicProgramming3runEi
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $16, %esi
movq %rbx, %rdi
call _ZN27FibonacciDynamicProgrammingC1Ei
movl $16, %esi
movq %rbx, %rdi
call _ZNK27FibonacciDynamicProgramming3runEi
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z16fibonacci_kernelPmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16fibonacci_kernelPmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdlib>
#include <cstdio>
#include <cassert>
#include <iostream>
#define ULI unsigned long int
__global__ void fibonacci_kernel(ULI* a, int start) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int index = i + start;
if (i < 2 * start - 1)
a[index] = (a[start - 2] * a[i]) + (a[start - 1] * a[i + 1]);
}
class FibonacciDynamicProgramming {
public:
int numElements, sizeInBytes;
explicit FibonacciDynamicProgramming(int numElements);
void run(int numThreads) const;
};
FibonacciDynamicProgramming::FibonacciDynamicProgramming(int numElements) {
this->numElements = numElements;
this->sizeInBytes = numElements * sizeof(ULI);
}
void FibonacciDynamicProgramming::run(int numThreads) const {
int deviceId = cudaGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", cudaCpuDeviceId);
ULI startingElements[3] = {1, 1, 2};
ULI* deviceArray;
ULI resultArray[numThreads];
cudaMalloc(&deviceArray, sizeInBytes);
cudaMemcpy(deviceArray, startingElements, sizeof(startingElements), cudaMemcpyHostToDevice);
unsigned int start = 3;
while (start <= numElements / 2 ) {
unsigned int numBlocks = (start - 1) / numThreads;
if ((start - 1) % numThreads != 0)
numBlocks++;
fibonacci_kernel<<<numBlocks, numThreads>>>(deviceArray, start);
start = 2 * start - 1;
}
cudaMemcpy(resultArray, deviceArray, sizeInBytes, cudaMemcpyDeviceToHost);
for (int i = 0; i < numElements; i++) {
printf("%d:\t%lu \n", i + 1, resultArray[i]);
}
cudaFree(deviceArray);
}
int main() {
FibonacciDynamicProgramming program(16);
program.run(16);
} | #include "hip/hip_runtime.h"
#include <cstdlib>
#include <cstdio>
#include <cassert>
#include <iostream>
#define ULI unsigned long int
__global__ void fibonacci_kernel(ULI* a, int start) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int index = i + start;
if (i < 2 * start - 1)
a[index] = (a[start - 2] * a[i]) + (a[start - 1] * a[i + 1]);
}
class FibonacciDynamicProgramming {
public:
int numElements, sizeInBytes;
explicit FibonacciDynamicProgramming(int numElements);
void run(int numThreads) const;
};
FibonacciDynamicProgramming::FibonacciDynamicProgramming(int numElements) {
this->numElements = numElements;
this->sizeInBytes = numElements * sizeof(ULI);
}
void FibonacciDynamicProgramming::run(int numThreads) const {
int deviceId = hipGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", hipCpuDeviceId);
ULI startingElements[3] = {1, 1, 2};
ULI* deviceArray;
ULI resultArray[numThreads];
hipMalloc(&deviceArray, sizeInBytes);
hipMemcpy(deviceArray, startingElements, sizeof(startingElements), hipMemcpyHostToDevice);
unsigned int start = 3;
while (start <= numElements / 2 ) {
unsigned int numBlocks = (start - 1) / numThreads;
if ((start - 1) % numThreads != 0)
numBlocks++;
fibonacci_kernel<<<numBlocks, numThreads>>>(deviceArray, start);
start = 2 * start - 1;
}
hipMemcpy(resultArray, deviceArray, sizeInBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < numElements; i++) {
printf("%d:\t%lu \n", i + 1, resultArray[i]);
}
hipFree(deviceArray);
}
int main() {
FibonacciDynamicProgramming program(16);
program.run(16);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <cstdlib>
#include <cstdio>
#include <cassert>
#include <iostream>
#define ULI unsigned long int
__global__ void fibonacci_kernel(ULI* a, int start) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int index = i + start;
if (i < 2 * start - 1)
a[index] = (a[start - 2] * a[i]) + (a[start - 1] * a[i + 1]);
}
class FibonacciDynamicProgramming {
public:
int numElements, sizeInBytes;
explicit FibonacciDynamicProgramming(int numElements);
void run(int numThreads) const;
};
FibonacciDynamicProgramming::FibonacciDynamicProgramming(int numElements) {
this->numElements = numElements;
this->sizeInBytes = numElements * sizeof(ULI);
}
void FibonacciDynamicProgramming::run(int numThreads) const {
int deviceId = hipGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", hipCpuDeviceId);
ULI startingElements[3] = {1, 1, 2};
ULI* deviceArray;
ULI resultArray[numThreads];
hipMalloc(&deviceArray, sizeInBytes);
hipMemcpy(deviceArray, startingElements, sizeof(startingElements), hipMemcpyHostToDevice);
unsigned int start = 3;
while (start <= numElements / 2 ) {
unsigned int numBlocks = (start - 1) / numThreads;
if ((start - 1) % numThreads != 0)
numBlocks++;
fibonacci_kernel<<<numBlocks, numThreads>>>(deviceArray, start);
start = 2 * start - 1;
}
hipMemcpy(resultArray, deviceArray, sizeInBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < numElements; i++) {
printf("%d:\t%lu \n", i + 1, resultArray[i]);
}
hipFree(deviceArray);
}
int main() {
FibonacciDynamicProgramming program(16);
program.run(16);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16fibonacci_kernelPmi
.globl _Z16fibonacci_kernelPmi
.p2align 8
.type _Z16fibonacci_kernelPmi,@function
_Z16fibonacci_kernelPmi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_lshl_b32 s3, s2, 1
s_add_i32 s3, s3, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v0, s2, v1
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshl_b64 s[2:3], s[2:3], 3
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
global_load_b64 v[5:6], v[5:6], off
s_add_u32 s2, s4, -16
s_addc_u32 s3, s5, -1
s_add_u32 s4, s4, -8
s_load_b64 s[2:3], s[2:3], 0x0
s_addc_u32 s5, s5, -1
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_lo_u32 v1, v4, s2
v_mul_lo_u32 v4, v3, s3
v_mad_u64_u32 v[7:8], null, v3, s2, 0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v6, v6, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v8, v8, v4, v1
v_mov_b32_e32 v1, v2
v_mul_lo_u32 v4, v5, s5
v_mad_u64_u32 v[2:3], null, v5, s4, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v3, v6, v3, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16fibonacci_kernelPmi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16fibonacci_kernelPmi, .Lfunc_end0-_Z16fibonacci_kernelPmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16fibonacci_kernelPmi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16fibonacci_kernelPmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <cstdlib>
#include <cstdio>
#include <cassert>
#include <iostream>
#define ULI unsigned long int
__global__ void fibonacci_kernel(ULI* a, int start) {
unsigned int i = blockIdx.x * blockDim.x + threadIdx.x;
unsigned int index = i + start;
if (i < 2 * start - 1)
a[index] = (a[start - 2] * a[i]) + (a[start - 1] * a[i + 1]);
}
class FibonacciDynamicProgramming {
public:
int numElements, sizeInBytes;
explicit FibonacciDynamicProgramming(int numElements);
void run(int numThreads) const;
};
FibonacciDynamicProgramming::FibonacciDynamicProgramming(int numElements) {
this->numElements = numElements;
this->sizeInBytes = numElements * sizeof(ULI);
}
void FibonacciDynamicProgramming::run(int numThreads) const {
int deviceId = hipGetDevice(&deviceId);
printf("GPU Device ID: %d\n", deviceId);
printf("CPU Device ID: %d\n\n", hipCpuDeviceId);
ULI startingElements[3] = {1, 1, 2};
ULI* deviceArray;
ULI resultArray[numThreads];
hipMalloc(&deviceArray, sizeInBytes);
hipMemcpy(deviceArray, startingElements, sizeof(startingElements), hipMemcpyHostToDevice);
unsigned int start = 3;
while (start <= numElements / 2 ) {
unsigned int numBlocks = (start - 1) / numThreads;
if ((start - 1) % numThreads != 0)
numBlocks++;
fibonacci_kernel<<<numBlocks, numThreads>>>(deviceArray, start);
start = 2 * start - 1;
}
hipMemcpy(resultArray, deviceArray, sizeInBytes, hipMemcpyDeviceToHost);
for (int i = 0; i < numElements; i++) {
printf("%d:\t%lu \n", i + 1, resultArray[i]);
}
hipFree(deviceArray);
}
int main() {
FibonacciDynamicProgramming program(16);
program.run(16);
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__fibonacci_kernelPmi # -- Begin function _Z31__device_stub__fibonacci_kernelPmi
.p2align 4, 0x90
.type _Z31__device_stub__fibonacci_kernelPmi,@function
_Z31__device_stub__fibonacci_kernelPmi: # @_Z31__device_stub__fibonacci_kernelPmi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16fibonacci_kernelPmi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__fibonacci_kernelPmi, .Lfunc_end0-_Z31__device_stub__fibonacci_kernelPmi
.cfi_endproc
# -- End function
.globl _ZN27FibonacciDynamicProgrammingC2Ei # -- Begin function _ZN27FibonacciDynamicProgrammingC2Ei
.p2align 4, 0x90
.type _ZN27FibonacciDynamicProgrammingC2Ei,@function
_ZN27FibonacciDynamicProgrammingC2Ei: # @_ZN27FibonacciDynamicProgrammingC2Ei
.cfi_startproc
# %bb.0:
movl %esi, (%rdi)
shll $3, %esi
movl %esi, 4(%rdi)
retq
.Lfunc_end1:
.size _ZN27FibonacciDynamicProgrammingC2Ei, .Lfunc_end1-_ZN27FibonacciDynamicProgrammingC2Ei
.cfi_endproc
# -- End function
.globl _ZNK27FibonacciDynamicProgramming3runEi # -- Begin function _ZNK27FibonacciDynamicProgramming3runEi
.p2align 4, 0x90
.type _ZNK27FibonacciDynamicProgramming3runEi,@function
_ZNK27FibonacciDynamicProgramming3runEi: # @_ZNK27FibonacciDynamicProgramming3runEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl %esi, %r14d
movq %rdi, %rbx
leaq -52(%rbp), %rdi
callq hipGetDevice
movl %eax, -52(%rbp)
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $-1, %esi
xorl %eax, %eax
callq printf
movq %rsp, -64(%rbp) # 8-byte Spill
movq $1, -176(%rbp)
movq $1, -168(%rbp)
movq $2, -160(%rbp)
movl %r14d, %r12d
movq %rsp, %r15
leaq 15(,%r12,8), %rax
andq $-16, %rax
subq %rax, %r15
movq %r15, %rsp
movslq 4(%rbx), %rsi
leaq -48(%rbp), %rdi
callq hipMalloc
movq -48(%rbp), %rdi
leaq -176(%rbp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movl (%rbx), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
cmpl $3, %ecx
jae .LBB2_1
.LBB2_5: # %._crit_edge
movq -48(%rbp), %rsi
movslq 4(%rbx), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, (%rbx)
jle .LBB2_8
# %bb.6: # %.lr.ph29.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph29
# =>This Inner Loop Header: Depth=1
movq (%r15,%r14,8), %rdx
incq %r14
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movslq (%rbx), %rax
cmpq %rax, %r14
jl .LBB2_7
.LBB2_8: # %._crit_edge30
movq -48(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rsp # 8-byte Reload
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB2_1: # %.lr.ph
.cfi_def_cfa %rbp, 16
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movl $3, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
leal -1(,%r13,2), %r13d
movl (%rbx), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
cmpl %ecx, %r13d
ja .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
leal -1(%r13), %eax
xorl %edx, %edx
divl %r14d
# kill: def $eax killed $eax def $rax
cmpl $1, %edx
sbbl $-1, %eax
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rax
movq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq -48(%rbp), %rax
movq %rax, -120(%rbp)
movl %r13d, -56(%rbp)
leaq -120(%rbp), %rax
movq %rax, -144(%rbp)
leaq -56(%rbp), %rax
movq %rax, -136(%rbp)
leaq -112(%rbp), %rdi
leaq -96(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -72(%rbp), %rcx
callq __hipPopCallConfiguration
movq -112(%rbp), %rsi
movl -104(%rbp), %edx
movq -96(%rbp), %rcx
movl -88(%rbp), %r8d
movl $_Z16fibonacci_kernelPmi, %edi
leaq -144(%rbp), %r9
pushq -72(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB2_4
.Lfunc_end2:
.size _ZNK27FibonacciDynamicProgramming3runEi, .Lfunc_end2-_ZNK27FibonacciDynamicProgramming3runEi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movabsq $549755813904, %rax # imm = 0x8000000010
movq %rax, (%rsp)
movq %rsp, %rdi
movl $16, %esi
callq _ZNK27FibonacciDynamicProgramming3runEi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16fibonacci_kernelPmi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16fibonacci_kernelPmi,@object # @_Z16fibonacci_kernelPmi
.section .rodata,"a",@progbits
.globl _Z16fibonacci_kernelPmi
.p2align 3, 0x0
_Z16fibonacci_kernelPmi:
.quad _Z31__device_stub__fibonacci_kernelPmi
.size _Z16fibonacci_kernelPmi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Device ID: %d\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU Device ID: %d\n\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d:\t%lu \n"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16fibonacci_kernelPmi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN27FibonacciDynamicProgrammingC1Ei
.type _ZN27FibonacciDynamicProgrammingC1Ei,@function
.set _ZN27FibonacciDynamicProgrammingC1Ei, _ZN27FibonacciDynamicProgrammingC2Ei
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__fibonacci_kernelPmi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16fibonacci_kernelPmi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16fibonacci_kernelPmi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x168] ; /* 0x00005a0000057a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fe200078e0200 */
/*0050*/ LEA R0, R5, 0xffffffff, 0x1 ; /* 0xffffffff05007811 */
/* 0x000fc800078e08ff */
/*0060*/ ISETP.GE.U32.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff007435 */
/* 0x000fe200000001ff */
/*0090*/ IADD3 R5, R5, -0x2, RZ ; /* 0xfffffffe05057810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IADD3 R11, R3, 0x1, RZ ; /* 0x00000001030b7810 */
/* 0x000fce0007ffe0ff */
/*00c0*/ IMAD.WIDE.U32 R6, R3, R0, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0000 */
/*00d0*/ IMAD.WIDE R4, R5, R0.reuse, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x080fe400078e0200 */
/*00e0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*00f0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea2000c1e1b00 */
/*0100*/ IMAD.WIDE.U32 R10, R11, R0, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fc600078e0000 */
/*0110*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x000ee8000c1e1b00 */
/*0120*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1b00 */
/*0130*/ IADD3 R3, R3, c[0x0][0x168], RZ ; /* 0x00005a0003037a10 */
/* 0x000fca0007ffe0ff */
/*0140*/ IMAD.WIDE.U32 R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0000 */
/*0150*/ IMAD R17, R7, R8.reuse, RZ ; /* 0x0000000807117224 */
/* 0x084fe400078e02ff */
/*0160*/ IMAD.WIDE.U32 R14, R6, R8, RZ ; /* 0x00000008060e7225 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD R17, R6, R9, R17 ; /* 0x0000000906117224 */
/* 0x000fe400078e0211 */
/*0180*/ IMAD R9, R11, R12, RZ ; /* 0x0000000c0b097224 */
/* 0x008fc600078e02ff */
/*0190*/ IADD3 R15, R15, R17, RZ ; /* 0x000000110f0f7210 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD R9, R10, R13, R9 ; /* 0x0000000d0a097224 */
/* 0x000fc800078e0209 */
/*01b0*/ IMAD.WIDE.U32 R12, R10, R12, R14 ; /* 0x0000000c0a0c7225 */
/* 0x000fca00078e000e */
/*01c0*/ IADD3 R13, R13, R9, RZ ; /* 0x000000090d0d7210 */
/* 0x000fca0007ffe0ff */
/*01d0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x000fe2000c101b04 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16fibonacci_kernelPmi
.globl _Z16fibonacci_kernelPmi
.p2align 8
.type _Z16fibonacci_kernelPmi,@function
_Z16fibonacci_kernelPmi:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_lshl_b32 s3, s2, 1
s_add_i32 s3, s3, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v0, s2, v1
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_lshl_b64 s[2:3], s[2:3], 3
v_lshlrev_b64 v[3:4], 3, v[1:2]
v_add_nc_u32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b64 v[3:4], v[3:4], off
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
global_load_b64 v[5:6], v[5:6], off
s_add_u32 s2, s4, -16
s_addc_u32 s3, s5, -1
s_add_u32 s4, s4, -8
s_load_b64 s[2:3], s[2:3], 0x0
s_addc_u32 s5, s5, -1
s_load_b64 s[4:5], s[4:5], 0x0
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_lo_u32 v1, v4, s2
v_mul_lo_u32 v4, v3, s3
v_mad_u64_u32 v[7:8], null, v3, s2, 0
s_waitcnt vmcnt(0)
v_mul_lo_u32 v6, v6, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add3_u32 v8, v8, v4, v1
v_mov_b32_e32 v1, v2
v_mul_lo_u32 v4, v5, s5
v_mad_u64_u32 v[2:3], null, v5, s4, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add3_u32 v3, v6, v3, v4
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16fibonacci_kernelPmi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16fibonacci_kernelPmi, .Lfunc_end0-_Z16fibonacci_kernelPmi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16fibonacci_kernelPmi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16fibonacci_kernelPmi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f723a_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3676:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3676:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN27FibonacciDynamicProgrammingC2Ei
.type _ZN27FibonacciDynamicProgrammingC2Ei, @function
_ZN27FibonacciDynamicProgrammingC2Ei:
.LFB3670:
.cfi_startproc
endbr64
movl %esi, (%rdi)
sall $3, %esi
movl %esi, 4(%rdi)
ret
.cfi_endproc
.LFE3670:
.size _ZN27FibonacciDynamicProgrammingC2Ei, .-_ZN27FibonacciDynamicProgrammingC2Ei
.globl _ZN27FibonacciDynamicProgrammingC1Ei
.set _ZN27FibonacciDynamicProgrammingC1Ei,_ZN27FibonacciDynamicProgrammingC2Ei
.globl _Z37__device_stub__Z16fibonacci_kernelPmiPmi
.type _Z37__device_stub__Z16fibonacci_kernelPmiPmi, @function
_Z37__device_stub__Z16fibonacci_kernelPmiPmi:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L8
.L4:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L9
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16fibonacci_kernelPmi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L4
.L9:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z37__device_stub__Z16fibonacci_kernelPmiPmi, .-_Z37__device_stub__Z16fibonacci_kernelPmiPmi
.globl _Z16fibonacci_kernelPmi
.type _Z16fibonacci_kernelPmi, @function
_Z16fibonacci_kernelPmi:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z16fibonacci_kernelPmiPmi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z16fibonacci_kernelPmi, .-_Z16fibonacci_kernelPmi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "GPU Device ID: %d\n"
.LC1:
.string "CPU Device ID: %d\n\n"
.LC2:
.string "%d:\t%lu \n"
.text
.align 2
.globl _ZNK27FibonacciDynamicProgramming3runEi
.type _ZNK27FibonacciDynamicProgramming3runEi, @function
_ZNK27FibonacciDynamicProgramming3runEi:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
movq %rsp, %rbp
.cfi_def_cfa_register 6
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $80, %rsp
.cfi_offset 14, -24
.cfi_offset 13, -32
.cfi_offset 12, -40
.cfi_offset 3, -48
movq %rdi, %r14
movl %esi, %r12d
movq %fs:40, %rax
movq %rax, -40(%rbp)
xorl %eax, %eax
leaq -100(%rbp), %rdi
call cudaGetDevice@PLT
movl %eax, %edx
movl %eax, -100(%rbp)
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq $1, -64(%rbp)
movq $1, -56(%rbp)
movq $2, -48(%rbp)
movslq %r12d, %rax
leaq 15(,%rax,8), %rax
movq %rax, %rcx
andq $-16, %rcx
andq $-4096, %rax
movq %rsp, %rdx
subq %rax, %rdx
.L13:
cmpq %rdx, %rsp
je .L14
subq $4096, %rsp
orq $0, 4088(%rsp)
jmp .L13
.L14:
movq %rcx, %rax
andl $4095, %eax
subq %rax, %rsp
testq %rax, %rax
je .L15
orq $0, -8(%rsp,%rax)
.L15:
movq %rsp, %r13
movslq 4(%r14), %rsi
leaq -96(%rbp), %rdi
call cudaMalloc@PLT
leaq -64(%rbp), %rsi
movl $1, %ecx
movl $24, %edx
movq -96(%rbp), %rdi
call cudaMemcpy@PLT
movl (%r14), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
cmpl $5, %eax
jbe .L16
movl $3, %ebx
jmp .L19
.L18:
leal -1(%rbx,%rbx), %ebx
movl (%r14), %edx
movl %edx, %eax
shrl $31, %eax
addl %edx, %eax
sarl %eax
cmpl %ebx, %eax
jb .L16
.L19:
leal -1(%rbx), %eax
movl $0, %edx
divl %r12d
cmpl $1, %edx
sbbl $-1, %eax
movl %r12d, -76(%rbp)
movl $1, -72(%rbp)
movl $1, -68(%rbp)
movl %eax, -88(%rbp)
movl $1, -84(%rbp)
movl $1, -80(%rbp)
movl $0, %r9d
movl $0, %r8d
movq -76(%rbp), %rdx
movl $1, %ecx
movq -88(%rbp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L18
movl %ebx, %esi
movq -96(%rbp), %rdi
call _Z37__device_stub__Z16fibonacci_kernelPmiPmi
jmp .L18
.L16:
movslq 4(%r14), %rdx
movl $2, %ecx
movq -96(%rbp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
cmpl $0, (%r14)
jle .L20
movl $0, %ebx
leaq .LC2(%rip), %r12
.L21:
addl $1, %ebx
movq 0(%r13), %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %r13
cmpl (%r14), %ebx
jl .L21
.L20:
movq -96(%rbp), %rdi
call cudaFree@PLT
movq -40(%rbp), %rax
subq %fs:40, %rax
jne .L26
leaq -32(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %rbp
.cfi_remember_state
.cfi_def_cfa 7, 8
ret
.L26:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size _ZNK27FibonacciDynamicProgramming3runEi, .-_ZNK27FibonacciDynamicProgramming3runEi
.globl main
.type main, @function
main:
.LFB3673:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $16, %esi
movq %rbx, %rdi
call _ZN27FibonacciDynamicProgrammingC1Ei
movl $16, %esi
movq %rbx, %rdi
call _ZNK27FibonacciDynamicProgramming3runEi
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3673:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z16fibonacci_kernelPmi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16fibonacci_kernelPmi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z31__device_stub__fibonacci_kernelPmi # -- Begin function _Z31__device_stub__fibonacci_kernelPmi
.p2align 4, 0x90
.type _Z31__device_stub__fibonacci_kernelPmi,@function
_Z31__device_stub__fibonacci_kernelPmi: # @_Z31__device_stub__fibonacci_kernelPmi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z16fibonacci_kernelPmi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z31__device_stub__fibonacci_kernelPmi, .Lfunc_end0-_Z31__device_stub__fibonacci_kernelPmi
.cfi_endproc
# -- End function
.globl _ZN27FibonacciDynamicProgrammingC2Ei # -- Begin function _ZN27FibonacciDynamicProgrammingC2Ei
.p2align 4, 0x90
.type _ZN27FibonacciDynamicProgrammingC2Ei,@function
_ZN27FibonacciDynamicProgrammingC2Ei: # @_ZN27FibonacciDynamicProgrammingC2Ei
.cfi_startproc
# %bb.0:
movl %esi, (%rdi)
shll $3, %esi
movl %esi, 4(%rdi)
retq
.Lfunc_end1:
.size _ZN27FibonacciDynamicProgrammingC2Ei, .Lfunc_end1-_ZN27FibonacciDynamicProgrammingC2Ei
.cfi_endproc
# -- End function
.globl _ZNK27FibonacciDynamicProgramming3runEi # -- Begin function _ZNK27FibonacciDynamicProgramming3runEi
.p2align 4, 0x90
.type _ZNK27FibonacciDynamicProgramming3runEi,@function
_ZNK27FibonacciDynamicProgramming3runEi: # @_ZNK27FibonacciDynamicProgramming3runEi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset %rbp, -16
movq %rsp, %rbp
.cfi_def_cfa_register %rbp
pushq %r15
pushq %r14
pushq %r13
pushq %r12
pushq %rbx
subq $136, %rsp
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
movl %esi, %r14d
movq %rdi, %rbx
leaq -52(%rbp), %rdi
callq hipGetDevice
movl %eax, -52(%rbp)
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $.L.str.1, %edi
movl $-1, %esi
xorl %eax, %eax
callq printf
movq %rsp, -64(%rbp) # 8-byte Spill
movq $1, -176(%rbp)
movq $1, -168(%rbp)
movq $2, -160(%rbp)
movl %r14d, %r12d
movq %rsp, %r15
leaq 15(,%r12,8), %rax
andq $-16, %rax
subq %rax, %r15
movq %r15, %rsp
movslq 4(%rbx), %rsi
leaq -48(%rbp), %rdi
callq hipMalloc
movq -48(%rbp), %rdi
leaq -176(%rbp), %rsi
movl $24, %edx
movl $1, %ecx
callq hipMemcpy
movl (%rbx), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
cmpl $3, %ecx
jae .LBB2_1
.LBB2_5: # %._crit_edge
movq -48(%rbp), %rsi
movslq 4(%rbx), %rdx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $0, (%rbx)
jle .LBB2_8
# %bb.6: # %.lr.ph29.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_7: # %.lr.ph29
# =>This Inner Loop Header: Depth=1
movq (%r15,%r14,8), %rdx
incq %r14
movl $.L.str.2, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movslq (%rbx), %rax
cmpq %rax, %r14
jl .LBB2_7
.LBB2_8: # %._crit_edge30
movq -48(%rbp), %rdi
callq hipFree
movq -64(%rbp), %rsp # 8-byte Reload
leaq -40(%rbp), %rsp
popq %rbx
popq %r12
popq %r13
popq %r14
popq %r15
popq %rbp
.cfi_def_cfa %rsp, 8
retq
.LBB2_1: # %.lr.ph
.cfi_def_cfa %rbp, 16
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %r12
movl $3, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_4: # in Loop: Header=BB2_2 Depth=1
leal -1(,%r13,2), %r13d
movl (%rbx), %eax
movl %eax, %ecx
shrl $31, %ecx
addl %eax, %ecx
sarl %ecx
cmpl %ecx, %r13d
ja .LBB2_5
.LBB2_2: # =>This Inner Loop Header: Depth=1
leal -1(%r13), %eax
xorl %edx, %edx
divl %r14d
# kill: def $eax killed $eax def $rax
cmpl $1, %edx
sbbl $-1, %eax
movabsq $4294967296, %rcx # imm = 0x100000000
orq %rcx, %rax
movq %rax, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3: # in Loop: Header=BB2_2 Depth=1
movq -48(%rbp), %rax
movq %rax, -120(%rbp)
movl %r13d, -56(%rbp)
leaq -120(%rbp), %rax
movq %rax, -144(%rbp)
leaq -56(%rbp), %rax
movq %rax, -136(%rbp)
leaq -112(%rbp), %rdi
leaq -96(%rbp), %rsi
leaq -80(%rbp), %rdx
leaq -72(%rbp), %rcx
callq __hipPopCallConfiguration
movq -112(%rbp), %rsi
movl -104(%rbp), %edx
movq -96(%rbp), %rcx
movl -88(%rbp), %r8d
movl $_Z16fibonacci_kernelPmi, %edi
leaq -144(%rbp), %r9
pushq -72(%rbp)
pushq -80(%rbp)
callq hipLaunchKernel
addq $16, %rsp
jmp .LBB2_4
.Lfunc_end2:
.size _ZNK27FibonacciDynamicProgramming3runEi, .Lfunc_end2-_ZNK27FibonacciDynamicProgramming3runEi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movabsq $549755813904, %rax # imm = 0x8000000010
movq %rax, (%rsp)
movq %rsp, %rdi
movl $16, %esi
callq _ZNK27FibonacciDynamicProgramming3runEi
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16fibonacci_kernelPmi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16fibonacci_kernelPmi,@object # @_Z16fibonacci_kernelPmi
.section .rodata,"a",@progbits
.globl _Z16fibonacci_kernelPmi
.p2align 3, 0x0
_Z16fibonacci_kernelPmi:
.quad _Z31__device_stub__fibonacci_kernelPmi
.size _Z16fibonacci_kernelPmi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "GPU Device ID: %d\n"
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CPU Device ID: %d\n\n"
.size .L.str.1, 20
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%d:\t%lu \n"
.size .L.str.2, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z16fibonacci_kernelPmi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.globl _ZN27FibonacciDynamicProgrammingC1Ei
.type _ZN27FibonacciDynamicProgrammingC1Ei,@function
.set _ZN27FibonacciDynamicProgrammingC1Ei, _ZN27FibonacciDynamicProgrammingC2Ei
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__fibonacci_kernelPmi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16fibonacci_kernelPmi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <string.h>
void __global__ run(float * h)
{
int idx = blockIdx.x*64+threadIdx.x;
if (idx > 10000) return;
h[idx] += 1.3f;
}
int main(int argc, char ** argv)
{
int times = atoi(argv[1]);
float * h_d;
cudaMalloc(&h_d, 10000*sizeof(float));
for (int i = 0; i < times; ++i)
run<<<157, 64>>>(h_d);
return 0;
} | code for sm_80
Function : _Z3runPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ LEA R2, R2, R3, 0x6 ; /* 0x0000000302027211 */
/* 0x001fc800078e30ff */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x2710, PT ; /* 0x000027100200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R5, R0, 1.2999999523162841797 ; /* 0x3fa6666600057421 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <string.h>
void __global__ run(float * h)
{
int idx = blockIdx.x*64+threadIdx.x;
if (idx > 10000) return;
h[idx] += 1.3f;
}
int main(int argc, char ** argv)
{
int times = atoi(argv[1]);
float * h_d;
cudaMalloc(&h_d, 10000*sizeof(float));
for (int i = 0; i < times; ++i)
run<<<157, 64>>>(h_d);
return 0;
} | .file "tmpxft_00189640_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3runPfPf
.type _Z22__device_stub__Z3runPfPf, @function
_Z22__device_stub__Z3runPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3runPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z3runPfPf, .-_Z22__device_stub__Z3runPfPf
.globl _Z3runPf
.type _Z3runPf, @function
_Z3runPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3runPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3runPf, .-_Z3runPf
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %ebx, %ebx
jle .L12
movl $0, %ebx
jmp .L14
.L13:
addl $1, %ebx
cmpl %ebp, %ebx
je .L12
.L14:
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $157, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rdi
call _Z22__device_stub__Z3runPfPf
jmp .L13
.L12:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3runPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3runPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <string.h>
void __global__ run(float * h)
{
int idx = blockIdx.x*64+threadIdx.x;
if (idx > 10000) return;
h[idx] += 1.3f;
}
int main(int argc, char ** argv)
{
int times = atoi(argv[1]);
float * h_d;
cudaMalloc(&h_d, 10000*sizeof(float));
for (int i = 0; i < times; ++i)
run<<<157, 64>>>(h_d);
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
void __global__ run(float * h)
{
int idx = blockIdx.x*64+threadIdx.x;
if (idx > 10000) return;
h[idx] += 1.3f;
}
int main(int argc, char ** argv)
{
int times = atoi(argv[1]);
float * h_d;
hipMalloc(&h_d, 10000*sizeof(float));
for (int i = 0; i < times; ++i)
run<<<157, 64>>>(h_d);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
void __global__ run(float * h)
{
int idx = blockIdx.x*64+threadIdx.x;
if (idx > 10000) return;
h[idx] += 1.3f;
}
int main(int argc, char ** argv)
{
int times = atoi(argv[1]);
float * h_d;
hipMalloc(&h_d, 10000*sizeof(float));
for (int i = 0; i < times; ++i)
run<<<157, 64>>>(h_d);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3runPf
.globl _Z3runPf
.p2align 8
.type _Z3runPf,@function
_Z3runPf:
v_lshl_add_u32 v0, s15, 6, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2711, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 0x3fa66666, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3runPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3runPf, .Lfunc_end0-_Z3runPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3runPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3runPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
void __global__ run(float * h)
{
int idx = blockIdx.x*64+threadIdx.x;
if (idx > 10000) return;
h[idx] += 1.3f;
}
int main(int argc, char ** argv)
{
int times = atoi(argv[1]);
float * h_d;
hipMalloc(&h_d, 10000*sizeof(float));
for (int i = 0; i < times; ++i)
run<<<157, 64>>>(h_d);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__runPf # -- Begin function _Z18__device_stub__runPf
.p2align 4, 0x90
.type _Z18__device_stub__runPf,@function
_Z18__device_stub__runPf: # @_Z18__device_stub__runPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3runPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__runPf, .Lfunc_end0-_Z18__device_stub__runPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %ebx, %ebx
jle .LBB1_5
# %bb.1: # %.lr.ph
movabsq $4294967360, %r14 # imm = 0x100000040
leaq 93(%r14), %r15
leaq 24(%rsp), %rbp
leaq 16(%rsp), %r12
movq %rsp, %r13
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
decl %ebx
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq 8(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %rbp, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z3runPf, %edi
movq %r13, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_4
.LBB1_5: # %._crit_edge
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3runPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3runPf,@object # @_Z3runPf
.section .rodata,"a",@progbits
.globl _Z3runPf
.p2align 3, 0x0
_Z3runPf:
.quad _Z18__device_stub__runPf
.size _Z3runPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3runPf"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__runPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3runPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3runPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ LEA R2, R2, R3, 0x6 ; /* 0x0000000302027211 */
/* 0x001fc800078e30ff */
/*0040*/ ISETP.GT.AND P0, PT, R2, 0x2710, PT ; /* 0x000027100200780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FADD R5, R0, 1.2999999523162841797 ; /* 0x3fa6666600057421 */
/* 0x004fca0000000000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3runPf
.globl _Z3runPf
.p2align 8
.type _Z3runPf,@function
_Z3runPf:
v_lshl_add_u32 v0, s15, 6, v0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2711, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, 0x3fa66666, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3runPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3runPf, .Lfunc_end0-_Z3runPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3runPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3runPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00189640_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z3runPfPf
.type _Z22__device_stub__Z3runPfPf, @function
_Z22__device_stub__Z3runPfPf:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3runPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z22__device_stub__Z3runPfPf, .-_Z22__device_stub__Z3runPfPf
.globl _Z3runPf
.type _Z3runPf, @function
_Z3runPf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z3runPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z3runPf, .-_Z3runPf
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, %ebp
leaq 8(%rsp), %rdi
movl $40000, %esi
call cudaMalloc@PLT
testl %ebx, %ebx
jle .L12
movl $0, %ebx
jmp .L14
.L13:
addl $1, %ebx
cmpl %ebp, %ebx
je .L12
.L14:
movl $64, 28(%rsp)
movl $1, 32(%rsp)
movl $157, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movq 8(%rsp), %rdi
call _Z22__device_stub__Z3runPfPf
jmp .L13
.L12:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3runPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3runPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z18__device_stub__runPf # -- Begin function _Z18__device_stub__runPf
.p2align 4, 0x90
.type _Z18__device_stub__runPf,@function
_Z18__device_stub__runPf: # @_Z18__device_stub__runPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z3runPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z18__device_stub__runPf, .Lfunc_end0-_Z18__device_stub__runPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $40000, %esi # imm = 0x9C40
callq hipMalloc
testl %ebx, %ebx
jle .LBB1_5
# %bb.1: # %.lr.ph
movabsq $4294967360, %r14 # imm = 0x100000040
leaq 93(%r14), %r15
leaq 24(%rsp), %rbp
leaq 16(%rsp), %r12
movq %rsp, %r13
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_4: # in Loop: Header=BB1_2 Depth=1
decl %ebx
je .LBB1_5
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3: # in Loop: Header=BB1_2 Depth=1
movq 8(%rsp), %rax
movq %rax, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
movq %rbp, %rdx
movq %r12, %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z3runPf, %edi
movq %r13, %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_4
.LBB1_5: # %._crit_edge
xorl %eax, %eax
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3runPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3runPf,@object # @_Z3runPf
.section .rodata,"a",@progbits
.globl _Z3runPf
.p2align 3, 0x0
_Z3runPf:
.quad _Z18__device_stub__runPf
.size _Z3runPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3runPf"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__runPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3runPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
// CUDA runtime
// helper functions and utilities to work with CUDA
extern "C"
__global__ void kernel(int* data, int size)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
data[id] = id;
} | code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
// CUDA runtime
// helper functions and utilities to work with CUDA
extern "C"
__global__ void kernel(int* data, int size)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
data[id] = id;
} | .file "tmpxft_00192687_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl kernel
.type kernel, @function
kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
// CUDA runtime
// helper functions and utilities to work with CUDA
extern "C"
__global__ void kernel(int* data, int size)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
data[id] = id;
} | #include <hip/hip_runtime.h>
#include "includes.h"
// CUDA runtime
// helper functions and utilities to work with CUDA
extern "C"
__global__ void kernel(int* data, int size)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
data[id] = id;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// CUDA runtime
// helper functions and utilities to work with CUDA
extern "C"
__global__ void kernel(int* data, int size)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
data[id] = id;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel, .Lfunc_end0-kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
// CUDA runtime
// helper functions and utilities to work with CUDA
extern "C"
__global__ void kernel(int* data, int size)
{
int id = blockDim.x * blockIdx.x + threadIdx.x;
data[id] = id;
} | .text
.file "kernel.hip"
.globl __device_stub__kernel # -- Begin function __device_stub__kernel
.p2align 4, 0x90
.type __device_stub__kernel,@function
__device_stub__kernel: # @__device_stub__kernel
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : kernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0060*/ IMAD.WIDE R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0202 */
/*0070*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected kernel
.globl kernel
.p2align 8
.type kernel,@function
kernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel kernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size kernel, .Lfunc_end0-kernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: kernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: kernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00192687_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z6kernelPiiPii
.type _Z26__device_stub__Z6kernelPiiPii, @function
_Z26__device_stub__Z6kernelPiiPii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq kernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z26__device_stub__Z6kernelPiiPii, .-_Z26__device_stub__Z6kernelPiiPii
.globl kernel
.type kernel, @function
kernel:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6kernelPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size kernel, .-kernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "kernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq kernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl __device_stub__kernel # -- Begin function __device_stub__kernel
.p2align 4, 0x90
.type __device_stub__kernel,@function
__device_stub__kernel: # @__device_stub__kernel
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $kernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size __device_stub__kernel, .Lfunc_end0-__device_stub__kernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $kernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type kernel,@object # @kernel
.section .rodata,"a",@progbits
.globl kernel
.p2align 3, 0x0
kernel:
.quad __device_stub__kernel
.size kernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "kernel"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__kernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym kernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <sys/time.h>
#define P (1 << 14)
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
void copymat_host_x(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(iy = 0; iy < n; iy++)
for(ix = 0; ix < m; ix++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
void copymat_host_y(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(ix = 0; ix < m; ix++)
for(iy = 0; iy < n; iy++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
int main(int argc, char** argv)
{
int *A, *B;
size_t m, n, nbytes;
double etime, start;
m = 1 << 14;
n = 1 << 14;
nbytes = m*n*sizeof(int);
printf("P = %d\n",P);
A = (int*) malloc(nbytes);
B = (int*) malloc(nbytes);
start = cpuSecond();
#if 0
copymat_host_x(m,n,A,B);
#else
copymat_host_y(m,n,A,B);
#endif
etime = cpuSecond() - start;
printf("Host %10.3g (s)\n",etime);
free(A);
free(B);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <sys/time.h>
#define P (1 << 14)
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
void copymat_host_x(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(iy = 0; iy < n; iy++)
for(ix = 0; ix < m; ix++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
void copymat_host_y(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(ix = 0; ix < m; ix++)
for(iy = 0; iy < n; iy++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
int main(int argc, char** argv)
{
int *A, *B;
size_t m, n, nbytes;
double etime, start;
m = 1 << 14;
n = 1 << 14;
nbytes = m*n*sizeof(int);
printf("P = %d\n",P);
A = (int*) malloc(nbytes);
B = (int*) malloc(nbytes);
start = cpuSecond();
#if 0
copymat_host_x(m,n,A,B);
#else
copymat_host_y(m,n,A,B);
#endif
etime = cpuSecond() - start;
printf("Host %10.3g (s)\n",etime);
free(A);
free(B);
} | .file "tmpxft_0014976a_00000000-6_host.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z14copymat_host_xiiPiS_
.type _Z14copymat_host_xiiPiS_, @function
_Z14copymat_host_xiiPiS_:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %r10d
movl %esi, %r11d
movl $0, %r9d
movl $0, %r8d
movslq %edi, %rbx
jmp .L9
.L11:
movslq %r9d, %rdi
leaq 0(,%rdi,4), %rax
addq %rbx, %rdi
salq $2, %rdi
.L10:
movl (%rdx,%rax), %esi
movl %esi, (%rcx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L10
.L12:
addl $1, %r8d
addl %r10d, %r9d
cmpl %r8d, %r11d
je .L7
.L9:
testl %r10d, %r10d
jg .L11
jmp .L12
.L7:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
ret
.cfi_endproc
.LFE2058:
.size _Z14copymat_host_xiiPiS_, .-_Z14copymat_host_xiiPiS_
.globl _Z14copymat_host_yiiPiS_
.type _Z14copymat_host_yiiPiS_, @function
_Z14copymat_host_yiiPiS_:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L18
movslq %edi, %r11
leaq 0(,%r11,4), %r9
movl $0, %r10d
jmp .L20
.L21:
movl (%rdx,%rax), %r8d
movl %r8d, (%rcx,%rax)
addl $1, %edi
addq %r9, %rax
cmpl %edi, %esi
jne .L21
.L23:
addq $1, %r10
cmpq %r11, %r10
je .L18
.L20:
leaq 0(,%r10,4), %rax
movl $0, %edi
testl %esi, %esi
jg .L21
jmp .L23
.L18:
ret
.cfi_endproc
.LFE2059:
.size _Z14copymat_host_yiiPiS_, .-_Z14copymat_host_yiiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "P = %d\n"
.LC2:
.string "Host %10.3g (s)\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movl $16384, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movq %rbx, %rcx
movq %rbp, %rdx
movl $16384, %esi
movl $16384, %edi
call _Z14copymat_host_yiiPiS_
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <sys/time.h>
#define P (1 << 14)
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
void copymat_host_x(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(iy = 0; iy < n; iy++)
for(ix = 0; ix < m; ix++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
void copymat_host_y(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(ix = 0; ix < m; ix++)
for(iy = 0; iy < n; iy++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
int main(int argc, char** argv)
{
int *A, *B;
size_t m, n, nbytes;
double etime, start;
m = 1 << 14;
n = 1 << 14;
nbytes = m*n*sizeof(int);
printf("P = %d\n",P);
A = (int*) malloc(nbytes);
B = (int*) malloc(nbytes);
start = cpuSecond();
#if 0
copymat_host_x(m,n,A,B);
#else
copymat_host_y(m,n,A,B);
#endif
etime = cpuSecond() - start;
printf("Host %10.3g (s)\n",etime);
free(A);
free(B);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define P (1 << 14)
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
void copymat_host_x(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(iy = 0; iy < n; iy++)
for(ix = 0; ix < m; ix++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
void copymat_host_y(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(ix = 0; ix < m; ix++)
for(iy = 0; iy < n; iy++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
int main(int argc, char** argv)
{
int *A, *B;
size_t m, n, nbytes;
double etime, start;
m = 1 << 14;
n = 1 << 14;
nbytes = m*n*sizeof(int);
printf("P = %d\n",P);
A = (int*) malloc(nbytes);
B = (int*) malloc(nbytes);
start = cpuSecond();
#if 0
copymat_host_x(m,n,A,B);
#else
copymat_host_y(m,n,A,B);
#endif
etime = cpuSecond() - start;
printf("Host %10.3g (s)\n",etime);
free(A);
free(B);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define P (1 << 14)
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
void copymat_host_x(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(iy = 0; iy < n; iy++)
for(ix = 0; ix < m; ix++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
void copymat_host_y(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(ix = 0; ix < m; ix++)
for(iy = 0; iy < n; iy++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
int main(int argc, char** argv)
{
int *A, *B;
size_t m, n, nbytes;
double etime, start;
m = 1 << 14;
n = 1 << 14;
nbytes = m*n*sizeof(int);
printf("P = %d\n",P);
A = (int*) malloc(nbytes);
B = (int*) malloc(nbytes);
start = cpuSecond();
#if 0
copymat_host_x(m,n,A,B);
#else
copymat_host_y(m,n,A,B);
#endif
etime = cpuSecond() - start;
printf("Host %10.3g (s)\n",etime);
free(A);
free(B);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <sys/time.h>
#define P (1 << 14)
double cpuSecond()
{
struct timeval tp;
gettimeofday(&tp,NULL);
return (double) tp.tv_sec + (double)tp.tv_usec*1e-6;
}
void copymat_host_x(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(iy = 0; iy < n; iy++)
for(ix = 0; ix < m; ix++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
void copymat_host_y(int m, int n, int* A, int *B)
{
int ix,iy,idx;
for(ix = 0; ix < m; ix++)
for(iy = 0; iy < n; iy++)
{
idx = iy*m + ix;
B[idx] = A[idx];
}
}
int main(int argc, char** argv)
{
int *A, *B;
size_t m, n, nbytes;
double etime, start;
m = 1 << 14;
n = 1 << 14;
nbytes = m*n*sizeof(int);
printf("P = %d\n",P);
A = (int*) malloc(nbytes);
B = (int*) malloc(nbytes);
start = cpuSecond();
#if 0
copymat_host_x(m,n,A,B);
#else
copymat_host_y(m,n,A,B);
#endif
etime = cpuSecond() - start;
printf("Host %10.3g (s)\n",etime);
free(A);
free(B);
} | .text
.file "host.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z14copymat_host_xiiPiS_ # -- Begin function _Z14copymat_host_xiiPiS_
.p2align 4, 0x90
.type _Z14copymat_host_xiiPiS_,@function
_Z14copymat_host_xiiPiS_: # @_Z14copymat_host_xiiPiS_
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %eax
movl %edi, %esi
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r9
addl %edi, %r8d
cmpq %rax, %r9
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edi, %edi
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r8d, %r11d
leaq (%rcx,%r11,4), %r10
leaq (%rdx,%r11,4), %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r11,%rbx,4), %ebp
movl %ebp, (%r10,%rbx,4)
incq %rbx
cmpq %rbx, %rsi
jne .LBB1_4
jmp .LBB1_5
.LBB1_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB1_7: # %._crit_edge16
retq
.Lfunc_end1:
.size _Z14copymat_host_xiiPiS_, .Lfunc_end1-_Z14copymat_host_xiiPiS_
.cfi_endproc
# -- End function
.globl _Z14copymat_host_yiiPiS_ # -- Begin function _Z14copymat_host_yiiPiS_
.p2align 4, 0x90
.type _Z14copymat_host_yiiPiS_,@function
_Z14copymat_host_yiiPiS_: # @_Z14copymat_host_yiiPiS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %eax
movl %esi, %edi
leaq (,%rax,4), %r8
xorl %r9d, %r9d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r9
addq $4, %rcx
addq $4, %rdx
cmpq %rax, %r9
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %esi, %esi
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
movq %rdi, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%r11), %ebx
movl %ebx, (%rcx,%r11)
addq %r8, %r11
decq %r10
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB2_7: # %._crit_edge16
retq
.Lfunc_end2:
.size _Z14copymat_host_yiiPiS_, .Lfunc_end2-_Z14copymat_host_yiiPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z14copymat_host_yiiPiS_.exit
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $.L.str, %edi
movl $16384, %esi # imm = 0x4000
xorl %eax, %eax
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq (%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "P = %d\n"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Host %10.3g (s)\n"
.size .L.str.1, 23
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014976a_00000000-6_host.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9cpuSecondv
.type _Z9cpuSecondv, @function
_Z9cpuSecondv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9cpuSecondv, .-_Z9cpuSecondv
.globl _Z14copymat_host_xiiPiS_
.type _Z14copymat_host_xiiPiS_, @function
_Z14copymat_host_xiiPiS_:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L15
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl %edi, %r10d
movl %esi, %r11d
movl $0, %r9d
movl $0, %r8d
movslq %edi, %rbx
jmp .L9
.L11:
movslq %r9d, %rdi
leaq 0(,%rdi,4), %rax
addq %rbx, %rdi
salq $2, %rdi
.L10:
movl (%rdx,%rax), %esi
movl %esi, (%rcx,%rax)
addq $4, %rax
cmpq %rdi, %rax
jne .L10
.L12:
addl $1, %r8d
addl %r10d, %r9d
cmpl %r8d, %r11d
je .L7
.L9:
testl %r10d, %r10d
jg .L11
jmp .L12
.L7:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
ret
.cfi_endproc
.LFE2058:
.size _Z14copymat_host_xiiPiS_, .-_Z14copymat_host_xiiPiS_
.globl _Z14copymat_host_yiiPiS_
.type _Z14copymat_host_yiiPiS_, @function
_Z14copymat_host_yiiPiS_:
.LFB2059:
.cfi_startproc
endbr64
testl %edi, %edi
jle .L18
movslq %edi, %r11
leaq 0(,%r11,4), %r9
movl $0, %r10d
jmp .L20
.L21:
movl (%rdx,%rax), %r8d
movl %r8d, (%rcx,%rax)
addl $1, %edi
addq %r9, %rax
cmpl %edi, %esi
jne .L21
.L23:
addq $1, %r10
cmpq %r11, %r10
je .L18
.L20:
leaq 0(,%r10,4), %rax
movl $0, %edi
testl %esi, %esi
jg .L21
jmp .L23
.L18:
ret
.cfi_endproc
.LFE2059:
.size _Z14copymat_host_yiiPiS_, .-_Z14copymat_host_yiiPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "P = %d\n"
.LC2:
.string "Host %10.3g (s)\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movl $16384, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbp
movl $1073741824, %edi
call malloc@PLT
movq %rax, %rbx
call _Z9cpuSecondv
movsd %xmm0, 8(%rsp)
movq %rbx, %rcx
movq %rbp, %rdx
movl $16384, %esi
movl $16384, %edi
call _Z14copymat_host_yiiPiS_
call _Z9cpuSecondv
subsd 8(%rsp), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "host.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9cpuSecondv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9cpuSecondv
.p2align 4, 0x90
.type _Z9cpuSecondv,@function
_Z9cpuSecondv: # @_Z9cpuSecondv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9cpuSecondv, .Lfunc_end0-_Z9cpuSecondv
.cfi_endproc
# -- End function
.globl _Z14copymat_host_xiiPiS_ # -- Begin function _Z14copymat_host_xiiPiS_
.p2align 4, 0x90
.type _Z14copymat_host_xiiPiS_,@function
_Z14copymat_host_xiiPiS_: # @_Z14copymat_host_xiiPiS_
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movl %esi, %eax
movl %edi, %esi
xorl %r8d, %r8d
xorl %r9d, %r9d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r9
addl %edi, %r8d
cmpq %rax, %r9
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %edi, %edi
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r8d, %r11d
leaq (%rcx,%r11,4), %r10
leaq (%rdx,%r11,4), %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r11,%rbx,4), %ebp
movl %ebp, (%r10,%rbx,4)
incq %rbx
cmpq %rbx, %rsi
jne .LBB1_4
jmp .LBB1_5
.LBB1_6:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %rbp
.LBB1_7: # %._crit_edge16
retq
.Lfunc_end1:
.size _Z14copymat_host_xiiPiS_, .Lfunc_end1-_Z14copymat_host_xiiPiS_
.cfi_endproc
# -- End function
.globl _Z14copymat_host_yiiPiS_ # -- Begin function _Z14copymat_host_yiiPiS_
.p2align 4, 0x90
.type _Z14copymat_host_yiiPiS_,@function
_Z14copymat_host_yiiPiS_: # @_Z14copymat_host_yiiPiS_
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB2_7
# %bb.1: # %.preheader.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl %edi, %eax
movl %esi, %edi
leaq (,%rax,4), %r8
xorl %r9d, %r9d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r9
addq $4, %rcx
addq $4, %rdx
cmpq %rax, %r9
je .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
testl %esi, %esi
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
movq %rdi, %r10
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rdx,%r11), %ebx
movl %ebx, (%rcx,%r11)
addq %r8, %r11
decq %r10
jne .LBB2_4
jmp .LBB2_5
.LBB2_6:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB2_7: # %._crit_edge16
retq
.Lfunc_end2:
.size _Z14copymat_host_yiiPiS_, .Lfunc_end2-_Z14copymat_host_yiiPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0: # %_Z14copymat_host_yiiPiS_.exit
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $.L.str, %edi
movl $16384, %esi # imm = 0x4000
xorl %eax, %eax
callq printf
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq (%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI3_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "P = %d\n"
.size .L.str, 8
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Host %10.3g (s)\n"
.size .L.str.1, 23
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define CHECK(call) { const cudaError_t error = call; if (error != cudaSuccess) { printf("Error: %s:%d, ", __FILE__, __LINE__); printf("code:%d, reason: %s\n", error, cudaGetErrorString(error)); exit(1); }}
__global__ void compute_displacement (float *projection_mat,float *projection_dis,float *eigenvec,int frame_min,int frame_max,int points){
int k=threadIdx.x + blockDim.x * blockIdx.x;
int kk,bin_num;
if(k>=frame_min && k<frame_max){
for(kk=0;kk<points;kk++){
bin_num=k+(frame_max*kk);
projection_dis[k]+=(projection_mat[bin_num]*eigenvec[kk]);
}
}
} // End of Global
int main ()
{
int devCount,blocks,threads,i,frame_number,counter_cov,max_frame,min_frame,reso_count,bin_number,frame_dimension,points,projection_value,frame,atom_index,curr_frame;
float variance_value,position,bias;
float *eigenvector,*projection_matrix,*projection_displacement;
float *dev_eigenvector,*dev_projection_matrix,*dev_projection_displacement;
char buf[256];
FILE* file=fopen("selection_coords.dat","r");
FILE* file2=fopen("eigenvector.dat","r");
FILE* file3=fopen("atomic_count_matrix.dat","r");
FILE *ofp;
char outputFilename[] = "displacement.dat";
CHECK (cudaSetDevice ( 0 ) );
printf("Initilizing...\n");
points=0;
max_frame=0;
while (fgets(buf, sizeof (buf), file)) {
sscanf (buf, "%i\t%i\t%f\t%f",&frame,&atom_index,&position,&bias);
if(points==0){curr_frame=frame;}
if(curr_frame==frame){points+=1;}
max_frame=frame;
}
fclose(file);
printf("Number of Atoms=%i\n",points/3);
printf("Max Frame=%i\n",max_frame);
printf("Points=%i\n",points);
printf("Points*max_frame=%i\n",points*max_frame);
////////////////////////////////
//Allocate Eigenvector Array
eigenvector=(float *)malloc(points*sizeof(float));
if(eigenvector == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(eigenvector,0,points*sizeof(float));
counter_cov=0;
printf("Reading Input...\n");
//Fill Eigenvector Array
while (fgets(buf, sizeof (buf), file2)) {
sscanf (buf, "%f",&variance_value);
eigenvector[counter_cov]=variance_value;
counter_cov+=1;
}
fclose (file2);
//Determine Max Frame
counter_cov=0;
reso_count=0;
min_frame=99999999;
counter_cov=0;
max_frame=-1;
frame_dimension=0;
frame_dimension=max_frame;
//Allocate Projection Matrix
projection_matrix=(float *)malloc(frame_dimension*points*sizeof(float));
if(projection_matrix == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_matrix,0,frame_dimension*points*sizeof(float));
printf("Fill Matrix...\n");
//Fill Projection Matrix
max_frame=-1;
min_frame=99999999;
while (fgets(buf, sizeof (buf), file3)) {
sscanf (buf, "%i\t%i",&frame_number,&projection_value);
if(max_frame!=frame_number){
counter_cov=0;
reso_count=0;}
bin_number=(frame_number)+(frame_dimension*reso_count);
projection_matrix[bin_number]=float(projection_value);
reso_count+=1;
if(frame_number < min_frame){
min_frame=frame_number;}
max_frame=frame_number;
counter_cov+=1;
}
fclose (file3);
counter_cov=counter_cov-1;
//Allocate Projection Displacement Array
projection_displacement=(float *)malloc(frame_dimension*sizeof(float));
if(projection_displacement == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_displacement,0,frame_dimension*sizeof(float));
//Prepare Device Parameters
cudaGetDeviceCount(&devCount);
for (int i = 0; i < devCount; ++i){
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
threads=devProp.maxThreadsPerBlock;
}
blocks=ceil(float(frame_dimension)/float(threads))+1;
printf("Threads=%i\n",threads);
printf("Blocks=%i\n",blocks);
//Allocate Device Arrays
CHECK (cudaMalloc((void **) &dev_projection_matrix, frame_dimension*points*sizeof(float)) );
CHECK (cudaMalloc((void **) &dev_projection_displacement, frame_dimension*sizeof(float)) );
CHECK (cudaMalloc((void **) &dev_eigenvector, points*sizeof(float)) );
CHECK (cudaMemcpy(dev_projection_matrix, projection_matrix, frame_dimension*points*sizeof(float), cudaMemcpyHostToDevice) );
CHECK (cudaMemcpy(dev_eigenvector,eigenvector, points*sizeof(float), cudaMemcpyHostToDevice) );
CHECK (cudaMemcpy(dev_projection_displacement, projection_displacement, frame_dimension*sizeof(float), cudaMemcpyHostToDevice) );
compute_displacement<<<blocks,threads>>>(dev_projection_matrix,dev_projection_displacement,dev_eigenvector,min_frame,frame_dimension,points);
CHECK (cudaMemcpy(projection_displacement, dev_projection_displacement, (frame_dimension)*sizeof(float), cudaMemcpyDeviceToHost) );
CHECK (cudaFree(dev_projection_matrix) );
CHECK (cudaFree(dev_projection_displacement) );
CHECK (cudaFree(dev_eigenvector) );
cudaDeviceReset();
//Write a File
ofp=fopen(outputFilename, "w");
for (i=min_frame;i<frame_dimension;i++){
fprintf(ofp,"%i\t%f\n",i,projection_displacement[i]);
}
fclose(ofp);
//Free Allocated Arrays
free(projection_matrix);
free(projection_displacement);
free(eigenvector);
printf("Complete!\n");
return 0;
} | code for sm_80
Function : _Z20compute_displacementPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fc80003f06270 */
/*0060*/ ISETP.LT.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x000fc80000701670 */
/*0070*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00e0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fc80000000f00 */
/*00f0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fce00078e0207 */
/*0100*/ @!P0 BRA 0xc70 ; /* 0x00000b6000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R9, -R0, c[0x0][0x180], RZ ; /* 0x0000600000097a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0130*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0140*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f04270 */
/*0150*/ LEA R12, P1, R6.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800060c7a11 */
/* 0x040fe400078210ff */
/*0160*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0170*/ LEA.HI.X R13, R6, c[0x0][0x164], R5, 0x2, P1 ; /* 0x00005900060d7a11 */
/* 0x000fc400008f1405 */
/*0180*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fc60000000f00 */
/*01a0*/ @!P0 BRA 0xab0 ; /* 0x0000090000008947 */
/* 0x001fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x780 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ MOV R10, c[0x0][0x17c] ; /* 0x00005f00000a7a02 */
/* 0x000fe20000000f00 */
/*0220*/ FFMA R11, R14, R11, R15 ; /* 0x0000000b0e0b7223 */
/* 0x024fc8000000000f */
/*0230*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x002fe200078e020c */
/*0240*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0250*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x000ea4000c1e1900 */
/*0270*/ FFMA R19, R16, R17, R11 ; /* 0x0000001110137223 */
/* 0x004fc4000000000b */
/*0280*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*0290*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*02a0*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ FFMA R21, R18, R12, R19 ; /* 0x0000000c12157223 */
/* 0x004fc40000000013 */
/*02d0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*02e0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*02f0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001ee8000c1e1900 */
/*0300*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000ee2000c1e1900 */
/*0310*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0320*/ FFMA R11, R18, R11, R21 ; /* 0x0000000b120b7223 */
/* 0x008fca0000000015 */
/*0330*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x002ee2000c1e1900 */
/*0360*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc800078e020e */
/*0370*/ FFMA R19, R18, R19, R11 ; /* 0x0000001312137223 */
/* 0x008fca000000000b */
/*0380*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0390*/ LDG.E R18, [R4.64+0x14] ; /* 0x0000140404127981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ FFMA R21, R18, R12, R19 ; /* 0x0000000c12157223 */
/* 0x004fc40000000013 */
/*03c0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*03d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*03e0*/ LDG.E R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001ee2000c1e1900 */
/*0400*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0410*/ FFMA R11, R18, R11, R21 ; /* 0x0000000b120b7223 */
/* 0x008fca0000000015 */
/*0420*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0430*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x002ee8000c1e1900 */
/*0440*/ LDG.E R18, [R4.64+0x1c] ; /* 0x00001c0404127981 */
/* 0x000ee2000c1e1900 */
/*0450*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc800078e020e */
/*0460*/ FFMA R19, R18, R19, R11 ; /* 0x0000001312137223 */
/* 0x008fca000000000b */
/*0470*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc800078e0210 */
/*04b0*/ FFMA R21, R18, R20, R19 ; /* 0x0000001412157223 */
/* 0x004fca0000000013 */
/*04c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*04d0*/ LDG.E R18, [R4.64+0x24] ; /* 0x0000240404127981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001ee2000c1e1900 */
/*04f0*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0500*/ FFMA R11, R18, R11, R21 ; /* 0x0000000b120b7223 */
/* 0x008fca0000000015 */
/*0510*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0520*/ LDG.E R18, [R4.64+0x28] ; /* 0x0000280404127981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x002ee2000c1e1900 */
/*0540*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc800078e020e */
/*0550*/ FFMA R19, R18, R19, R11 ; /* 0x0000001312137223 */
/* 0x008fca000000000b */
/*0560*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0570*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R18, [R4.64+0x2c] ; /* 0x00002c0404127981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc800078e0210 */
/*05a0*/ FFMA R21, R18, R20, R19 ; /* 0x0000001412157223 */
/* 0x004fca0000000013 */
/*05b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*05c0*/ LDG.E R18, [R4.64+0x30] ; /* 0x0000300404127981 */
/* 0x000ee8000c1e1900 */
/*05d0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001ee2000c1e1900 */
/*05e0*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*05f0*/ FFMA R11, R18, R11, R21 ; /* 0x0000000b120b7223 */
/* 0x008fca0000000015 */
/*0600*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0610*/ LDG.E R18, [R4.64+0x34] ; /* 0x0000340404127981 */
/* 0x000ee8000c1e1900 */
/*0620*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee4000c1e1900 */
/*0630*/ FFMA R23, R18, R16, R11 ; /* 0x0000001012177223 */
/* 0x008fc4000000000b */
/*0640*/ IMAD.WIDE R18, R10, 0x4, R14 ; /* 0x000000040a127825 */
/* 0x002fc600078e020e */
/*0650*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0660*/ LDG.E R16, [R4.64+0x38] ; /* 0x0000380404107981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fe20007ffe0ff */
/*0690*/ FFMA R21, R16, R17, R23 ; /* 0x0000001110157223 */
/* 0x004fc40000000017 */
/*06a0*/ IMAD.WIDE R16, R10, 0x4, R18 ; /* 0x000000040a107825 */
/* 0x000fc600078e0212 */
/*06b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*06c0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x001ea8000c1e1900 */
/*06d0*/ LDG.E R12, [R4.64+0x3c] ; /* 0x00003c04040c7981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*06f0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007ffe0ff */
/*0700*/ FFMA R15, R12, R11, R21 ; /* 0x0000000b0c0f7223 */
/* 0x004fe20000000015 */
/*0710*/ IADD3 R11, P2, R4, 0x40, RZ ; /* 0x00000040040b7810 */
/* 0x000fe20007f5e0ff */
/*0720*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*0730*/ IADD3.X R14, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0e7210 */
/* 0x000fe200017fe4ff */
/*0740*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e2000c101904 */
/*0750*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x000fe40000000f00 */
/*0760*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fe20000000f00 */
/*0770*/ @P1 BRA 0x1f0 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0790*/ @!P1 BRA 0xa90 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*07a0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*07b0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe20000000f00 */
/*07d0*/ FFMA R19, R10, R14, R15 ; /* 0x0000000e0a137223 */
/* 0x024fc8000000000f */
/*07e0*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x002fe200078e020c */
/*07f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0800*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1900 */
/*0820*/ FFMA R21, R10, R16, R19 ; /* 0x000000100a157223 */
/* 0x004fc40000000013 */
/*0830*/ IMAD.WIDE R16, R11, 0x4, R14 ; /* 0x000000040b107825 */
/* 0x000fc600078e020e */
/*0840*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0850*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea4000c1e1900 */
/*0870*/ FFMA R23, R10, R12, R21 ; /* 0x0000000c0a177223 */
/* 0x004fc40000000015 */
/*0880*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0210 */
/*0890*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*08a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R25, R10, R18, R23 ; /* 0x000000120a197223 */
/* 0x004fca0000000017 */
/*08e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*08f0*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000e28000c1e1900 */
/*0900*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e24000c1e1900 */
/*0910*/ FFMA R21, R10, R18, R25 ; /* 0x000000120a157223 */
/* 0x001fc40000000019 */
/*0920*/ IMAD.WIDE R18, R11, 0x4, R14 ; /* 0x000000040b127825 */
/* 0x000fc600078e020e */
/*0930*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0940*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e68000c1e1900 */
/*0950*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000e64000c1e1900 */
/*0960*/ FFMA R23, R10, R12, R21 ; /* 0x0000000c0a177223 */
/* 0x002fc40000000015 */
/*0970*/ IMAD.WIDE R12, R11, 0x4, R18 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0212 */
/*0980*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0990*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FFMA R25, R10, R16, R23 ; /* 0x000000100a197223 */
/* 0x004fc40000000017 */
/*09c0*/ IMAD.WIDE R16, R11, 0x4, R12 ; /* 0x000000040b107825 */
/* 0x000fc600078e020c */
/*09d0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*09e0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a10*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fe200078e0210 */
/*0a20*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fc40007ffe0ff */
/*0a30*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ FFMA R15, R10, R15, R25 ; /* 0x0000000f0a0f7223 */
/* 0x004fe20000000019 */
/*0a50*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fc80007f3e0ff */
/*0a60*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e2000c101904 */
/*0a70*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0a80*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0a90*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0aa0*/ @!P0 BRA 0xc70 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0ad0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe20000000f00 */
/*0ae0*/ FFMA R21, R10, R14, R15 ; /* 0x0000000e0a157223 */
/* 0x027fc8000000000f */
/*0af0*/ IMAD.WIDE R14, R11.reuse, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x040fe200078e020c */
/*0b00*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0b10*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea2000c1e1900 */
/*0b30*/ IMAD.WIDE R18, R11, 0x4, R14 ; /* 0x000000040b127825 */
/* 0x000fc800078e020e */
/*0b40*/ FFMA R23, R10, R16, R21 ; /* 0x000000100a177223 */
/* 0x004fca0000000015 */
/*0b50*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0b80*/ IMAD.WIDE R16, R11, 0x4, R18 ; /* 0x000000040b107825 */
/* 0x000fe200078e0212 */
/*0b90*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc60007ffe0ff */
/*0ba0*/ FFMA R25, R10, R12, R23 ; /* 0x0000000c0a197223 */
/* 0x004fca0000000017 */
/*0bb0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0bc0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*0bd0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea2000c1e1900 */
/*0be0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0bf0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ FFMA R15, R10, R12, R25 ; /* 0x0000000c0a0f7223 */
/* 0x004fe20000000019 */
/*0c10*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fe20007f3e0ff */
/*0c20*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0210 */
/*0c30*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e2000c101904 */
/*0c40*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0c50*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0c60*/ @P0 BRA 0xab0 ; /* 0xfffffe4000000947 */
/* 0x001fea000383ffff */
/*0c70*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0c80*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c90*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000562000c1e1900 */
/*0ca0*/ IMAD.WIDE R4, R8, R7, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fc800078e0207 */
/*0cb0*/ IMAD R6, R8, c[0x0][0x17c], R6 ; /* 0x00005f0008067a24 */
/* 0x000fe200078e0206 */
/*0cc0*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fe40000000f00 */
/*0cd0*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fe20000000f00 */
/*0ce0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0207 */
/*0cf0*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0d00*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x008722000c1e1900 */
/*0d10*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fca0000000f00 */
/*0d20*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0d30*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0d40*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe40000000f00 */
/*0d50*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0d60*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007f3e0ff */
/*0d70*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x008fc600078e0204 */
/*0d80*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0d90*/ FFMA R9, R6, R8, R9 ; /* 0x0000000806097223 */
/* 0x030fca0000000009 */
/*0da0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e2000c101904 */
/*0db0*/ @P0 BRA 0xcf0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define CHECK(call) { const cudaError_t error = call; if (error != cudaSuccess) { printf("Error: %s:%d, ", __FILE__, __LINE__); printf("code:%d, reason: %s\n", error, cudaGetErrorString(error)); exit(1); }}
__global__ void compute_displacement (float *projection_mat,float *projection_dis,float *eigenvec,int frame_min,int frame_max,int points){
int k=threadIdx.x + blockDim.x * blockIdx.x;
int kk,bin_num;
if(k>=frame_min && k<frame_max){
for(kk=0;kk<points;kk++){
bin_num=k+(frame_max*kk);
projection_dis[k]+=(projection_mat[bin_num]*eigenvec[kk]);
}
}
} // End of Global
int main ()
{
int devCount,blocks,threads,i,frame_number,counter_cov,max_frame,min_frame,reso_count,bin_number,frame_dimension,points,projection_value,frame,atom_index,curr_frame;
float variance_value,position,bias;
float *eigenvector,*projection_matrix,*projection_displacement;
float *dev_eigenvector,*dev_projection_matrix,*dev_projection_displacement;
char buf[256];
FILE* file=fopen("selection_coords.dat","r");
FILE* file2=fopen("eigenvector.dat","r");
FILE* file3=fopen("atomic_count_matrix.dat","r");
FILE *ofp;
char outputFilename[] = "displacement.dat";
CHECK (cudaSetDevice ( 0 ) );
printf("Initilizing...\n");
points=0;
max_frame=0;
while (fgets(buf, sizeof (buf), file)) {
sscanf (buf, "%i\t%i\t%f\t%f",&frame,&atom_index,&position,&bias);
if(points==0){curr_frame=frame;}
if(curr_frame==frame){points+=1;}
max_frame=frame;
}
fclose(file);
printf("Number of Atoms=%i\n",points/3);
printf("Max Frame=%i\n",max_frame);
printf("Points=%i\n",points);
printf("Points*max_frame=%i\n",points*max_frame);
////////////////////////////////
//Allocate Eigenvector Array
eigenvector=(float *)malloc(points*sizeof(float));
if(eigenvector == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(eigenvector,0,points*sizeof(float));
counter_cov=0;
printf("Reading Input...\n");
//Fill Eigenvector Array
while (fgets(buf, sizeof (buf), file2)) {
sscanf (buf, "%f",&variance_value);
eigenvector[counter_cov]=variance_value;
counter_cov+=1;
}
fclose (file2);
//Determine Max Frame
counter_cov=0;
reso_count=0;
min_frame=99999999;
counter_cov=0;
max_frame=-1;
frame_dimension=0;
frame_dimension=max_frame;
//Allocate Projection Matrix
projection_matrix=(float *)malloc(frame_dimension*points*sizeof(float));
if(projection_matrix == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_matrix,0,frame_dimension*points*sizeof(float));
printf("Fill Matrix...\n");
//Fill Projection Matrix
max_frame=-1;
min_frame=99999999;
while (fgets(buf, sizeof (buf), file3)) {
sscanf (buf, "%i\t%i",&frame_number,&projection_value);
if(max_frame!=frame_number){
counter_cov=0;
reso_count=0;}
bin_number=(frame_number)+(frame_dimension*reso_count);
projection_matrix[bin_number]=float(projection_value);
reso_count+=1;
if(frame_number < min_frame){
min_frame=frame_number;}
max_frame=frame_number;
counter_cov+=1;
}
fclose (file3);
counter_cov=counter_cov-1;
//Allocate Projection Displacement Array
projection_displacement=(float *)malloc(frame_dimension*sizeof(float));
if(projection_displacement == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_displacement,0,frame_dimension*sizeof(float));
//Prepare Device Parameters
cudaGetDeviceCount(&devCount);
for (int i = 0; i < devCount; ++i){
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
threads=devProp.maxThreadsPerBlock;
}
blocks=ceil(float(frame_dimension)/float(threads))+1;
printf("Threads=%i\n",threads);
printf("Blocks=%i\n",blocks);
//Allocate Device Arrays
CHECK (cudaMalloc((void **) &dev_projection_matrix, frame_dimension*points*sizeof(float)) );
CHECK (cudaMalloc((void **) &dev_projection_displacement, frame_dimension*sizeof(float)) );
CHECK (cudaMalloc((void **) &dev_eigenvector, points*sizeof(float)) );
CHECK (cudaMemcpy(dev_projection_matrix, projection_matrix, frame_dimension*points*sizeof(float), cudaMemcpyHostToDevice) );
CHECK (cudaMemcpy(dev_eigenvector,eigenvector, points*sizeof(float), cudaMemcpyHostToDevice) );
CHECK (cudaMemcpy(dev_projection_displacement, projection_displacement, frame_dimension*sizeof(float), cudaMemcpyHostToDevice) );
compute_displacement<<<blocks,threads>>>(dev_projection_matrix,dev_projection_displacement,dev_eigenvector,min_frame,frame_dimension,points);
CHECK (cudaMemcpy(projection_displacement, dev_projection_displacement, (frame_dimension)*sizeof(float), cudaMemcpyDeviceToHost) );
CHECK (cudaFree(dev_projection_matrix) );
CHECK (cudaFree(dev_projection_displacement) );
CHECK (cudaFree(dev_eigenvector) );
cudaDeviceReset();
//Write a File
ofp=fopen(outputFilename, "w");
for (i=min_frame;i<frame_dimension;i++){
fprintf(ofp,"%i\t%f\n",i,projection_displacement[i]);
}
fclose(ofp);
//Free Allocated Arrays
free(projection_matrix);
free(projection_displacement);
free(eigenvector);
printf("Complete!\n");
return 0;
} | .file "tmpxft_000850ea_00000000-6_projection_r.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii
.type _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii, @function
_Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20compute_displacementPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii, .-_Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii
.globl _Z20compute_displacementPfS_S_iii
.type _Z20compute_displacementPfS_S_iii, @function
_Z20compute_displacementPfS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20compute_displacementPfS_S_iii, .-_Z20compute_displacementPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "selection_coords.dat"
.LC2:
.string "eigenvector.dat"
.LC3:
.string "atomic_count_matrix.dat"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/slaustin/gpu_sources/master/projection_r.cu"
.section .rodata.str1.1
.LC5:
.string "Error: %s:%d, "
.LC6:
.string "code:%d, reason: %s\n"
.LC7:
.string "Initilizing...\n"
.LC8:
.string "%i\t%i\t%f\t%f"
.LC9:
.string "Number of Atoms=%i\n"
.LC10:
.string "Max Frame=%i\n"
.LC11:
.string "Points=%i\n"
.LC12:
.string "Points*max_frame=%i\n"
.LC13:
.string "Reading Input...\n"
.LC14:
.string "%f"
.LC15:
.string "Fill Matrix...\n"
.LC16:
.string "%i\t%i"
.LC21:
.string "Threads=%i\n"
.LC22:
.string "Blocks=%i\n"
.LC23:
.string "w"
.LC24:
.string "%i\t%f\n"
.LC25:
.string "Complete!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1480, %rsp
.cfi_def_cfa_offset 1536
movq %fs:40, %rax
movq %rax, 1464(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %rbx, %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, 32(%rsp)
movabsq $7305790138896050532, %rax
movabsq $8386094131825239405, %rdx
movq %rax, 1168(%rsp)
movq %rdx, 1176(%rsp)
movb $0, 1184(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L47
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
movl $0, %ebx
leaq .LC8(%rip), %r14
jmp .L13
.L47:
movl %eax, %ebx
movl $38, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
movl 60(%rsp), %ebx
cmpl %r15d, %ebx
je .L48
.L13:
leaq 1200(%rsp), %rdi
movq %r12, %rcx
movl $256, %edx
movl $256, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L49
leaq 64(%rsp), %rcx
leaq 60(%rsp), %rdx
leaq 1200(%rsp), %rdi
leaq 76(%rsp), %r9
leaq 72(%rsp), %r8
movq %r14, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
testl %ebp, %ebp
jne .L14
movl 60(%rsp), %ebx
.L15:
addl $1, %ebp
movl %ebx, %r15d
jmp .L13
.L48:
movl %r15d, %ebx
jmp .L15
.L49:
movq %r12, %rdi
call fclose@PLT
movslq %ebp, %r12
imulq $1431655766, %r12, %rdx
shrq $32, %rdx
movl %ebp, %eax
sarl $31, %eax
subl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imull %ebp, %ebx
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(,%r12,4), %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testq %rax, %rax
je .L50
movq 8(%rsp), %rcx
movq %rcx, %rdx
movl $0, %esi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call __memset_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %r12
jmp .L19
.L50:
movl $63, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
leaq 68(%rsp), %rdx
leaq 1200(%rsp), %rdi
movq %r12, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movss 68(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
.L19:
leaq 1200(%rsp), %rdi
movq %r13, %rcx
movl $256, %edx
movl $256, %esi
call __fgets_chk@PLT
testq %rax, %rax
jne .L20
movq %r13, %rdi
call fclose@PLT
movq 8(%rsp), %rax
negq %rax
movq %rax, 24(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r14
testq %rax, %rax
je .L51
movq 24(%rsp), %rcx
movq %rcx, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
movl $99999999, %ebx
movl $-1, %r13d
leaq .LC16(%rip), %r15
movl %ebp, 44(%rsp)
movq 32(%rsp), %rbp
jmp .L22
.L51:
movl $91, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
leaq 56(%rsp), %rcx
leaq 52(%rsp), %rdx
leaq 1200(%rsp), %rdi
movq %r15, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movl 52(%rsp), %eax
cmpl %r13d, %eax
movl $0, %edx
cmovne %edx, %r12d
movl %eax, %edx
subl %r12d, %edx
movslq %edx, %rdx
pxor %xmm0, %xmm0
cvtsi2ssl 56(%rsp), %xmm0
movss %xmm0, (%r14,%rdx,4)
addl $1, %r12d
cmpl %eax, %ebx
cmovg %eax, %ebx
movl %eax, %r13d
.L22:
leaq 1200(%rsp), %rdi
movq %rbp, %rcx
movl $256, %edx
movl $256, %esi
call __fgets_chk@PLT
testq %rax, %rax
jne .L24
movl 44(%rsp), %ebp
movq 32(%rsp), %rdi
call fclose@PLT
movq $-4, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L52
movq $-4, %rdx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
leaq 48(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 48(%rsp)
jle .L26
movl $0, %r12d
leaq 128(%rsp), %r15
.L27:
movl %r12d, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 448(%rsp), %eax
addl $1, %r12d
cmpl %r12d, 48(%rsp)
jg .L27
movl %eax, 40(%rsp)
.L26:
pxor %xmm1, %xmm1
cvtsi2ssl 40(%rsp), %xmm1
movss .LC17(%rip), %xmm0
divss %xmm1, %xmm0
movaps %xmm0, %xmm1
movss .LC26(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC18(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L28
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC20(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L28:
addss .LC20(%rip), %xmm1
cvttss2sil %xmm1, %r12d
movl 40(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 88(%rsp), %rdi
movq 24(%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L53
leaq 96(%rsp), %rdi
movq $-4, %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L54
leaq 80(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L55
movl $1, %ecx
movq 24(%rsp), %rdx
movq %r14, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L56
movl $1, %ecx
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L57
movl $1, %ecx
movq $-4, %rdx
movq %r13, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L58
movl 40(%rsp), %eax
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
movl %r12d, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L35:
movl $2, %ecx
movq $-4, %rdx
movq 96(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L60
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L61
movq 96(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L62
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L63
call cudaDeviceReset@PLT
leaq 1168(%rsp), %rdi
leaq .LC23(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
cmpl $-1, %ebx
jge .L40
movslq %ebx, %rbx
leaq .LC24(%rip), %r12
.L41:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movl %ebx, %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl $-1, %ebx
jl .L41
.L40:
movq %rbp, %rdi
call fclose@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1464(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $1480, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl $122, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl $140, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl $141, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl $142, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl $144, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl $146, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl $148, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl %ebp, %r9d
movl $-1, %r8d
movl %ebx, %ecx
movq 80(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii
jmp .L35
.L60:
movl $152, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl $154, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movl $155, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movl $156, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC27:
.string "_Z20compute_displacementPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z20compute_displacementPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long -1082130432
.align 4
.LC18:
.long 1258291200
.align 4
.LC20:
.long 1065353216
.align 4
.LC26:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define CHECK(call) { const cudaError_t error = call; if (error != cudaSuccess) { printf("Error: %s:%d, ", __FILE__, __LINE__); printf("code:%d, reason: %s\n", error, cudaGetErrorString(error)); exit(1); }}
__global__ void compute_displacement (float *projection_mat,float *projection_dis,float *eigenvec,int frame_min,int frame_max,int points){
int k=threadIdx.x + blockDim.x * blockIdx.x;
int kk,bin_num;
if(k>=frame_min && k<frame_max){
for(kk=0;kk<points;kk++){
bin_num=k+(frame_max*kk);
projection_dis[k]+=(projection_mat[bin_num]*eigenvec[kk]);
}
}
} // End of Global
int main ()
{
int devCount,blocks,threads,i,frame_number,counter_cov,max_frame,min_frame,reso_count,bin_number,frame_dimension,points,projection_value,frame,atom_index,curr_frame;
float variance_value,position,bias;
float *eigenvector,*projection_matrix,*projection_displacement;
float *dev_eigenvector,*dev_projection_matrix,*dev_projection_displacement;
char buf[256];
FILE* file=fopen("selection_coords.dat","r");
FILE* file2=fopen("eigenvector.dat","r");
FILE* file3=fopen("atomic_count_matrix.dat","r");
FILE *ofp;
char outputFilename[] = "displacement.dat";
CHECK (cudaSetDevice ( 0 ) );
printf("Initilizing...\n");
points=0;
max_frame=0;
while (fgets(buf, sizeof (buf), file)) {
sscanf (buf, "%i\t%i\t%f\t%f",&frame,&atom_index,&position,&bias);
if(points==0){curr_frame=frame;}
if(curr_frame==frame){points+=1;}
max_frame=frame;
}
fclose(file);
printf("Number of Atoms=%i\n",points/3);
printf("Max Frame=%i\n",max_frame);
printf("Points=%i\n",points);
printf("Points*max_frame=%i\n",points*max_frame);
////////////////////////////////
//Allocate Eigenvector Array
eigenvector=(float *)malloc(points*sizeof(float));
if(eigenvector == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(eigenvector,0,points*sizeof(float));
counter_cov=0;
printf("Reading Input...\n");
//Fill Eigenvector Array
while (fgets(buf, sizeof (buf), file2)) {
sscanf (buf, "%f",&variance_value);
eigenvector[counter_cov]=variance_value;
counter_cov+=1;
}
fclose (file2);
//Determine Max Frame
counter_cov=0;
reso_count=0;
min_frame=99999999;
counter_cov=0;
max_frame=-1;
frame_dimension=0;
frame_dimension=max_frame;
//Allocate Projection Matrix
projection_matrix=(float *)malloc(frame_dimension*points*sizeof(float));
if(projection_matrix == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_matrix,0,frame_dimension*points*sizeof(float));
printf("Fill Matrix...\n");
//Fill Projection Matrix
max_frame=-1;
min_frame=99999999;
while (fgets(buf, sizeof (buf), file3)) {
sscanf (buf, "%i\t%i",&frame_number,&projection_value);
if(max_frame!=frame_number){
counter_cov=0;
reso_count=0;}
bin_number=(frame_number)+(frame_dimension*reso_count);
projection_matrix[bin_number]=float(projection_value);
reso_count+=1;
if(frame_number < min_frame){
min_frame=frame_number;}
max_frame=frame_number;
counter_cov+=1;
}
fclose (file3);
counter_cov=counter_cov-1;
//Allocate Projection Displacement Array
projection_displacement=(float *)malloc(frame_dimension*sizeof(float));
if(projection_displacement == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_displacement,0,frame_dimension*sizeof(float));
//Prepare Device Parameters
cudaGetDeviceCount(&devCount);
for (int i = 0; i < devCount; ++i){
cudaDeviceProp devProp;
cudaGetDeviceProperties(&devProp, i);
threads=devProp.maxThreadsPerBlock;
}
blocks=ceil(float(frame_dimension)/float(threads))+1;
printf("Threads=%i\n",threads);
printf("Blocks=%i\n",blocks);
//Allocate Device Arrays
CHECK (cudaMalloc((void **) &dev_projection_matrix, frame_dimension*points*sizeof(float)) );
CHECK (cudaMalloc((void **) &dev_projection_displacement, frame_dimension*sizeof(float)) );
CHECK (cudaMalloc((void **) &dev_eigenvector, points*sizeof(float)) );
CHECK (cudaMemcpy(dev_projection_matrix, projection_matrix, frame_dimension*points*sizeof(float), cudaMemcpyHostToDevice) );
CHECK (cudaMemcpy(dev_eigenvector,eigenvector, points*sizeof(float), cudaMemcpyHostToDevice) );
CHECK (cudaMemcpy(dev_projection_displacement, projection_displacement, frame_dimension*sizeof(float), cudaMemcpyHostToDevice) );
compute_displacement<<<blocks,threads>>>(dev_projection_matrix,dev_projection_displacement,dev_eigenvector,min_frame,frame_dimension,points);
CHECK (cudaMemcpy(projection_displacement, dev_projection_displacement, (frame_dimension)*sizeof(float), cudaMemcpyDeviceToHost) );
CHECK (cudaFree(dev_projection_matrix) );
CHECK (cudaFree(dev_projection_displacement) );
CHECK (cudaFree(dev_eigenvector) );
cudaDeviceReset();
//Write a File
ofp=fopen(outputFilename, "w");
for (i=min_frame;i<frame_dimension;i++){
fprintf(ofp,"%i\t%f\n",i,projection_displacement[i]);
}
fclose(ofp);
//Free Allocated Arrays
free(projection_matrix);
free(projection_displacement);
free(eigenvector);
printf("Complete!\n");
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define CHECK(call) { const hipError_t error = call; if (error != hipSuccess) { printf("Error: %s:%d, ", __FILE__, __LINE__); printf("code:%d, reason: %s\n", error, hipGetErrorString(error)); exit(1); }}
__global__ void compute_displacement (float *projection_mat,float *projection_dis,float *eigenvec,int frame_min,int frame_max,int points){
int k=threadIdx.x + blockDim.x * blockIdx.x;
int kk,bin_num;
if(k>=frame_min && k<frame_max){
for(kk=0;kk<points;kk++){
bin_num=k+(frame_max*kk);
projection_dis[k]+=(projection_mat[bin_num]*eigenvec[kk]);
}
}
} // End of Global
int main ()
{
int devCount,blocks,threads,i,frame_number,counter_cov,max_frame,min_frame,reso_count,bin_number,frame_dimension,points,projection_value,frame,atom_index,curr_frame;
float variance_value,position,bias;
float *eigenvector,*projection_matrix,*projection_displacement;
float *dev_eigenvector,*dev_projection_matrix,*dev_projection_displacement;
char buf[256];
FILE* file=fopen("selection_coords.dat","r");
FILE* file2=fopen("eigenvector.dat","r");
FILE* file3=fopen("atomic_count_matrix.dat","r");
FILE *ofp;
char outputFilename[] = "displacement.dat";
CHECK (hipSetDevice ( 0 ) );
printf("Initilizing...\n");
points=0;
max_frame=0;
while (fgets(buf, sizeof (buf), file)) {
sscanf (buf, "%i\t%i\t%f\t%f",&frame,&atom_index,&position,&bias);
if(points==0){curr_frame=frame;}
if(curr_frame==frame){points+=1;}
max_frame=frame;
}
fclose(file);
printf("Number of Atoms=%i\n",points/3);
printf("Max Frame=%i\n",max_frame);
printf("Points=%i\n",points);
printf("Points*max_frame=%i\n",points*max_frame);
////////////////////////////////
//Allocate Eigenvector Array
eigenvector=(float *)malloc(points*sizeof(float));
if(eigenvector == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(eigenvector,0,points*sizeof(float));
counter_cov=0;
printf("Reading Input...\n");
//Fill Eigenvector Array
while (fgets(buf, sizeof (buf), file2)) {
sscanf (buf, "%f",&variance_value);
eigenvector[counter_cov]=variance_value;
counter_cov+=1;
}
fclose (file2);
//Determine Max Frame
counter_cov=0;
reso_count=0;
min_frame=99999999;
counter_cov=0;
max_frame=-1;
frame_dimension=0;
frame_dimension=max_frame;
//Allocate Projection Matrix
projection_matrix=(float *)malloc(frame_dimension*points*sizeof(float));
if(projection_matrix == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_matrix,0,frame_dimension*points*sizeof(float));
printf("Fill Matrix...\n");
//Fill Projection Matrix
max_frame=-1;
min_frame=99999999;
while (fgets(buf, sizeof (buf), file3)) {
sscanf (buf, "%i\t%i",&frame_number,&projection_value);
if(max_frame!=frame_number){
counter_cov=0;
reso_count=0;}
bin_number=(frame_number)+(frame_dimension*reso_count);
projection_matrix[bin_number]=float(projection_value);
reso_count+=1;
if(frame_number < min_frame){
min_frame=frame_number;}
max_frame=frame_number;
counter_cov+=1;
}
fclose (file3);
counter_cov=counter_cov-1;
//Allocate Projection Displacement Array
projection_displacement=(float *)malloc(frame_dimension*sizeof(float));
if(projection_displacement == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_displacement,0,frame_dimension*sizeof(float));
//Prepare Device Parameters
hipGetDeviceCount(&devCount);
for (int i = 0; i < devCount; ++i){
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
threads=devProp.maxThreadsPerBlock;
}
blocks=ceil(float(frame_dimension)/float(threads))+1;
printf("Threads=%i\n",threads);
printf("Blocks=%i\n",blocks);
//Allocate Device Arrays
CHECK (hipMalloc((void **) &dev_projection_matrix, frame_dimension*points*sizeof(float)) );
CHECK (hipMalloc((void **) &dev_projection_displacement, frame_dimension*sizeof(float)) );
CHECK (hipMalloc((void **) &dev_eigenvector, points*sizeof(float)) );
CHECK (hipMemcpy(dev_projection_matrix, projection_matrix, frame_dimension*points*sizeof(float), hipMemcpyHostToDevice) );
CHECK (hipMemcpy(dev_eigenvector,eigenvector, points*sizeof(float), hipMemcpyHostToDevice) );
CHECK (hipMemcpy(dev_projection_displacement, projection_displacement, frame_dimension*sizeof(float), hipMemcpyHostToDevice) );
compute_displacement<<<blocks,threads>>>(dev_projection_matrix,dev_projection_displacement,dev_eigenvector,min_frame,frame_dimension,points);
CHECK (hipMemcpy(projection_displacement, dev_projection_displacement, (frame_dimension)*sizeof(float), hipMemcpyDeviceToHost) );
CHECK (hipFree(dev_projection_matrix) );
CHECK (hipFree(dev_projection_displacement) );
CHECK (hipFree(dev_eigenvector) );
hipDeviceReset();
//Write a File
ofp=fopen(outputFilename, "w");
for (i=min_frame;i<frame_dimension;i++){
fprintf(ofp,"%i\t%f\n",i,projection_displacement[i]);
}
fclose(ofp);
//Free Allocated Arrays
free(projection_matrix);
free(projection_displacement);
free(eigenvector);
printf("Complete!\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define CHECK(call) { const hipError_t error = call; if (error != hipSuccess) { printf("Error: %s:%d, ", __FILE__, __LINE__); printf("code:%d, reason: %s\n", error, hipGetErrorString(error)); exit(1); }}
__global__ void compute_displacement (float *projection_mat,float *projection_dis,float *eigenvec,int frame_min,int frame_max,int points){
int k=threadIdx.x + blockDim.x * blockIdx.x;
int kk,bin_num;
if(k>=frame_min && k<frame_max){
for(kk=0;kk<points;kk++){
bin_num=k+(frame_max*kk);
projection_dis[k]+=(projection_mat[bin_num]*eigenvec[kk]);
}
}
} // End of Global
int main ()
{
int devCount,blocks,threads,i,frame_number,counter_cov,max_frame,min_frame,reso_count,bin_number,frame_dimension,points,projection_value,frame,atom_index,curr_frame;
float variance_value,position,bias;
float *eigenvector,*projection_matrix,*projection_displacement;
float *dev_eigenvector,*dev_projection_matrix,*dev_projection_displacement;
char buf[256];
FILE* file=fopen("selection_coords.dat","r");
FILE* file2=fopen("eigenvector.dat","r");
FILE* file3=fopen("atomic_count_matrix.dat","r");
FILE *ofp;
char outputFilename[] = "displacement.dat";
CHECK (hipSetDevice ( 0 ) );
printf("Initilizing...\n");
points=0;
max_frame=0;
while (fgets(buf, sizeof (buf), file)) {
sscanf (buf, "%i\t%i\t%f\t%f",&frame,&atom_index,&position,&bias);
if(points==0){curr_frame=frame;}
if(curr_frame==frame){points+=1;}
max_frame=frame;
}
fclose(file);
printf("Number of Atoms=%i\n",points/3);
printf("Max Frame=%i\n",max_frame);
printf("Points=%i\n",points);
printf("Points*max_frame=%i\n",points*max_frame);
////////////////////////////////
//Allocate Eigenvector Array
eigenvector=(float *)malloc(points*sizeof(float));
if(eigenvector == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(eigenvector,0,points*sizeof(float));
counter_cov=0;
printf("Reading Input...\n");
//Fill Eigenvector Array
while (fgets(buf, sizeof (buf), file2)) {
sscanf (buf, "%f",&variance_value);
eigenvector[counter_cov]=variance_value;
counter_cov+=1;
}
fclose (file2);
//Determine Max Frame
counter_cov=0;
reso_count=0;
min_frame=99999999;
counter_cov=0;
max_frame=-1;
frame_dimension=0;
frame_dimension=max_frame;
//Allocate Projection Matrix
projection_matrix=(float *)malloc(frame_dimension*points*sizeof(float));
if(projection_matrix == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_matrix,0,frame_dimension*points*sizeof(float));
printf("Fill Matrix...\n");
//Fill Projection Matrix
max_frame=-1;
min_frame=99999999;
while (fgets(buf, sizeof (buf), file3)) {
sscanf (buf, "%i\t%i",&frame_number,&projection_value);
if(max_frame!=frame_number){
counter_cov=0;
reso_count=0;}
bin_number=(frame_number)+(frame_dimension*reso_count);
projection_matrix[bin_number]=float(projection_value);
reso_count+=1;
if(frame_number < min_frame){
min_frame=frame_number;}
max_frame=frame_number;
counter_cov+=1;
}
fclose (file3);
counter_cov=counter_cov-1;
//Allocate Projection Displacement Array
projection_displacement=(float *)malloc(frame_dimension*sizeof(float));
if(projection_displacement == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_displacement,0,frame_dimension*sizeof(float));
//Prepare Device Parameters
hipGetDeviceCount(&devCount);
for (int i = 0; i < devCount; ++i){
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
threads=devProp.maxThreadsPerBlock;
}
blocks=ceil(float(frame_dimension)/float(threads))+1;
printf("Threads=%i\n",threads);
printf("Blocks=%i\n",blocks);
//Allocate Device Arrays
CHECK (hipMalloc((void **) &dev_projection_matrix, frame_dimension*points*sizeof(float)) );
CHECK (hipMalloc((void **) &dev_projection_displacement, frame_dimension*sizeof(float)) );
CHECK (hipMalloc((void **) &dev_eigenvector, points*sizeof(float)) );
CHECK (hipMemcpy(dev_projection_matrix, projection_matrix, frame_dimension*points*sizeof(float), hipMemcpyHostToDevice) );
CHECK (hipMemcpy(dev_eigenvector,eigenvector, points*sizeof(float), hipMemcpyHostToDevice) );
CHECK (hipMemcpy(dev_projection_displacement, projection_displacement, frame_dimension*sizeof(float), hipMemcpyHostToDevice) );
compute_displacement<<<blocks,threads>>>(dev_projection_matrix,dev_projection_displacement,dev_eigenvector,min_frame,frame_dimension,points);
CHECK (hipMemcpy(projection_displacement, dev_projection_displacement, (frame_dimension)*sizeof(float), hipMemcpyDeviceToHost) );
CHECK (hipFree(dev_projection_matrix) );
CHECK (hipFree(dev_projection_displacement) );
CHECK (hipFree(dev_eigenvector) );
hipDeviceReset();
//Write a File
ofp=fopen(outputFilename, "w");
for (i=min_frame;i<frame_dimension;i++){
fprintf(ofp,"%i\t%f\n",i,projection_displacement[i]);
}
fclose(ofp);
//Free Allocated Arrays
free(projection_matrix);
free(projection_displacement);
free(eigenvector);
printf("Complete!\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20compute_displacementPfS_S_iii
.globl _Z20compute_displacementPfS_S_iii
.p2align 8
.type _Z20compute_displacementPfS_S_iii,@function
_Z20compute_displacementPfS_S_iii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_le_i32_e32 vcc_lo, s2, v1
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s8, 0
s_cselect_b32 s4, -1, 0
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s8, s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v2, v5, s[0:1]
global_load_b32 v6, v[6:7], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s8, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v6, v2
global_store_b32 v[3:4], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20compute_displacementPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20compute_displacementPfS_S_iii, .Lfunc_end0-_Z20compute_displacementPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20compute_displacementPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20compute_displacementPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hip/hip_runtime.h>
#define CHECK(call) { const hipError_t error = call; if (error != hipSuccess) { printf("Error: %s:%d, ", __FILE__, __LINE__); printf("code:%d, reason: %s\n", error, hipGetErrorString(error)); exit(1); }}
__global__ void compute_displacement (float *projection_mat,float *projection_dis,float *eigenvec,int frame_min,int frame_max,int points){
int k=threadIdx.x + blockDim.x * blockIdx.x;
int kk,bin_num;
if(k>=frame_min && k<frame_max){
for(kk=0;kk<points;kk++){
bin_num=k+(frame_max*kk);
projection_dis[k]+=(projection_mat[bin_num]*eigenvec[kk]);
}
}
} // End of Global
int main ()
{
int devCount,blocks,threads,i,frame_number,counter_cov,max_frame,min_frame,reso_count,bin_number,frame_dimension,points,projection_value,frame,atom_index,curr_frame;
float variance_value,position,bias;
float *eigenvector,*projection_matrix,*projection_displacement;
float *dev_eigenvector,*dev_projection_matrix,*dev_projection_displacement;
char buf[256];
FILE* file=fopen("selection_coords.dat","r");
FILE* file2=fopen("eigenvector.dat","r");
FILE* file3=fopen("atomic_count_matrix.dat","r");
FILE *ofp;
char outputFilename[] = "displacement.dat";
CHECK (hipSetDevice ( 0 ) );
printf("Initilizing...\n");
points=0;
max_frame=0;
while (fgets(buf, sizeof (buf), file)) {
sscanf (buf, "%i\t%i\t%f\t%f",&frame,&atom_index,&position,&bias);
if(points==0){curr_frame=frame;}
if(curr_frame==frame){points+=1;}
max_frame=frame;
}
fclose(file);
printf("Number of Atoms=%i\n",points/3);
printf("Max Frame=%i\n",max_frame);
printf("Points=%i\n",points);
printf("Points*max_frame=%i\n",points*max_frame);
////////////////////////////////
//Allocate Eigenvector Array
eigenvector=(float *)malloc(points*sizeof(float));
if(eigenvector == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(eigenvector,0,points*sizeof(float));
counter_cov=0;
printf("Reading Input...\n");
//Fill Eigenvector Array
while (fgets(buf, sizeof (buf), file2)) {
sscanf (buf, "%f",&variance_value);
eigenvector[counter_cov]=variance_value;
counter_cov+=1;
}
fclose (file2);
//Determine Max Frame
counter_cov=0;
reso_count=0;
min_frame=99999999;
counter_cov=0;
max_frame=-1;
frame_dimension=0;
frame_dimension=max_frame;
//Allocate Projection Matrix
projection_matrix=(float *)malloc(frame_dimension*points*sizeof(float));
if(projection_matrix == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_matrix,0,frame_dimension*points*sizeof(float));
printf("Fill Matrix...\n");
//Fill Projection Matrix
max_frame=-1;
min_frame=99999999;
while (fgets(buf, sizeof (buf), file3)) {
sscanf (buf, "%i\t%i",&frame_number,&projection_value);
if(max_frame!=frame_number){
counter_cov=0;
reso_count=0;}
bin_number=(frame_number)+(frame_dimension*reso_count);
projection_matrix[bin_number]=float(projection_value);
reso_count+=1;
if(frame_number < min_frame){
min_frame=frame_number;}
max_frame=frame_number;
counter_cov+=1;
}
fclose (file3);
counter_cov=counter_cov-1;
//Allocate Projection Displacement Array
projection_displacement=(float *)malloc(frame_dimension*sizeof(float));
if(projection_displacement == NULL){
printf("Error: %s:%d, ", __FILE__, __LINE__);
exit(1);}
memset(projection_displacement,0,frame_dimension*sizeof(float));
//Prepare Device Parameters
hipGetDeviceCount(&devCount);
for (int i = 0; i < devCount; ++i){
hipDeviceProp_t devProp;
hipGetDeviceProperties(&devProp, i);
threads=devProp.maxThreadsPerBlock;
}
blocks=ceil(float(frame_dimension)/float(threads))+1;
printf("Threads=%i\n",threads);
printf("Blocks=%i\n",blocks);
//Allocate Device Arrays
CHECK (hipMalloc((void **) &dev_projection_matrix, frame_dimension*points*sizeof(float)) );
CHECK (hipMalloc((void **) &dev_projection_displacement, frame_dimension*sizeof(float)) );
CHECK (hipMalloc((void **) &dev_eigenvector, points*sizeof(float)) );
CHECK (hipMemcpy(dev_projection_matrix, projection_matrix, frame_dimension*points*sizeof(float), hipMemcpyHostToDevice) );
CHECK (hipMemcpy(dev_eigenvector,eigenvector, points*sizeof(float), hipMemcpyHostToDevice) );
CHECK (hipMemcpy(dev_projection_displacement, projection_displacement, frame_dimension*sizeof(float), hipMemcpyHostToDevice) );
compute_displacement<<<blocks,threads>>>(dev_projection_matrix,dev_projection_displacement,dev_eigenvector,min_frame,frame_dimension,points);
CHECK (hipMemcpy(projection_displacement, dev_projection_displacement, (frame_dimension)*sizeof(float), hipMemcpyDeviceToHost) );
CHECK (hipFree(dev_projection_matrix) );
CHECK (hipFree(dev_projection_displacement) );
CHECK (hipFree(dev_eigenvector) );
hipDeviceReset();
//Write a File
ofp=fopen(outputFilename, "w");
for (i=min_frame;i<frame_dimension;i++){
fprintf(ofp,"%i\t%f\n",i,projection_displacement[i]);
}
fclose(ofp);
//Free Allocated Arrays
free(projection_matrix);
free(projection_displacement);
free(eigenvector);
printf("Complete!\n");
return 0;
} | .text
.file "projection_r.hip"
.globl _Z35__device_stub__compute_displacementPfS_S_iii # -- Begin function _Z35__device_stub__compute_displacementPfS_S_iii
.p2align 4, 0x90
.type _Z35__device_stub__compute_displacementPfS_S_iii,@function
_Z35__device_stub__compute_displacementPfS_S_iii: # @_Z35__device_stub__compute_displacementPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20compute_displacementPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__compute_displacementPfS_S_iii, .Lfunc_end0-_Z35__device_stub__compute_displacementPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.byte 100 # 0x64
.byte 105 # 0x69
.byte 115 # 0x73
.byte 112 # 0x70
.byte 108 # 0x6c
.byte 97 # 0x61
.byte 99 # 0x63
.byte 101 # 0x65
.byte 109 # 0x6d
.byte 101 # 0x65
.byte 110 # 0x6e
.byte 116 # 0x74
.byte 46 # 0x2e
.byte 100 # 0x64
.byte 97 # 0x61
.byte 116 # 0x74
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0xbf800000 # float -1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1960, %rsp # imm = 0x7A8
.cfi_def_cfa_offset 2016
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movl $.L.str.2, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, (%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 24(%rsp) # 8-byte Spill
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [100,105,115,112,108,97,99,101,109,101,110,116,46,100,97,116]
movaps %xmm0, 192(%rsp)
movb $0, 208(%rsp)
xorl %ebp, %ebp
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movl $.Lstr, %edi
callq puts@PLT
leaq 224(%rsp), %rdi
movl $256, %esi # imm = 0x100
movq %r14, %rdx
callq fgets
movl $0, %r15d
testq %rax, %rax
je .LBB1_6
# %bb.4: # %.lr.ph.preheader
leaq 224(%rsp), %r12
leaq 180(%rsp), %rbx
xorl %ebp, %ebp
# implicit-def: $r13d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.8, %esi
movq %r12, %rdi
leaq 56(%rsp), %rdx
leaq 188(%rsp), %rcx
leaq 184(%rsp), %r8
movq %rbx, %r9
xorl %eax, %eax
callq __isoc23_sscanf
testl %ebp, %ebp
movl 56(%rsp), %r15d
cmovel %r15d, %r13d
xorl %eax, %eax
cmpl %r15d, %r13d
sete %al
addl %eax, %ebp
movq %r12, %rdi
movl $256, %esi # imm = 0x100
movq %r14, %rdx
callq fgets
testq %rax, %rax
jne .LBB1_5
.LBB1_6: # %._crit_edge
movq %r14, %rdi
callq fclose
movl %ebp, %ebx
movl $2863311531, %esi # imm = 0xAAAAAAAB
imulq %rbx, %rsi
shrq $33, %rsi
movl $.L.str.9, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.11, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
imull %ebp, %r15d
movl $.L.str.12, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
testq %rax, %rax
je .LBB1_7
# %bb.9:
movq %rax, %r12
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, 96(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq memset@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 224(%rsp), %rdi
movl $256, %esi # imm = 0x100
movq (%rsp), %r13 # 8-byte Reload
movq %r13, %rdx
callq fgets
testq %rax, %rax
je .LBB1_12
# %bb.10: # %.lr.ph170.preheader
leaq 224(%rsp), %rbx
leaq 52(%rsp), %r14
movq %r12, %r15
.p2align 4, 0x90
.LBB1_11: # %.lr.ph170
# =>This Inner Loop Header: Depth=1
movl $.L.str.14, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_sscanf
movss 52(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r15)
movq %rbx, %rdi
movl $256, %esi # imm = 0x100
movq %r13, %rdx
callq fgets
addq $4, %r15
testq %rax, %rax
jne .LBB1_11
.LBB1_12: # %._crit_edge171
movq %r13, %rdi
callq fclose
movl %ebp, %eax
negl %eax
movslq %eax, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
testq %rax, %rax
je .LBB1_13
# %bb.14:
movl %ebp, 48(%rsp) # 4-byte Spill
movq %r12, 80(%rsp) # 8-byte Spill
movq %rax, (%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, 88(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq memset@PLT
movl $.Lstr.2, %edi
callq puts@PLT
leaq 224(%rsp), %rdi
movl $256, %esi # imm = 0x100
movq 24(%rsp), %rdx # 8-byte Reload
callq fgets
movl $99999999, %r15d # imm = 0x5F5E0FF
testq %rax, %rax
je .LBB1_15
# %bb.16: # %.lr.ph178.preheader
movl $-1, %r14d
xorl %r13d, %r13d
movq 24(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB1_17: # %.lr.ph178
# =>This Inner Loop Header: Depth=1
movl $.L.str.16, %esi
leaq 224(%rsp), %r12
movq %r12, %rdi
leaq 64(%rsp), %rdx
leaq 60(%rsp), %rcx
xorl %eax, %eax
callq __isoc23_sscanf
movl 64(%rsp), %ebx
cmpl %ebx, %r14d
movl $0, %eax
cmovnel %eax, %r13d
xorps %xmm0, %xmm0
cvtsi2ssl 60(%rsp), %xmm0
movl %ebx, %eax
subl %r13d, %eax
cltq
movq (%rsp), %rcx # 8-byte Reload
movss %xmm0, (%rcx,%rax,4)
incl %r13d
cmpl %r15d, %ebx
cmovll %ebx, %r15d
movq %r12, %rdi
movl $256, %esi # imm = 0x100
movq %rbp, %rdx
callq fgets
movl %ebx, %r14d
testq %rax, %rax
jne .LBB1_17
jmp .LBB1_18
.LBB1_15:
movq 24(%rsp), %rbp # 8-byte Reload
.LBB1_18: # %._crit_edge179
movq %rbp, %rdi
callq fclose
movq $-4, %rdi
callq malloc
testq %rax, %rax
je .LBB1_19
# %bb.20:
movq %rax, %r13
xorl %ebx, %ebx
movq %rax, %rdi
xorl %esi, %esi
movq $-4, %rdx
callq memset@PLT
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB1_21
# %bb.24: # %.lr.ph183
leaq 480(%rsp), %r14
.p2align 4, 0x90
.LBB1_25: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
cmpl 12(%rsp), %ebx
jl .LBB1_25
# %bb.26:
movl 800(%rsp), %r12d
jmp .LBB1_22
.LBB1_21:
# implicit-def: $r12d
.LBB1_22: # %._crit_edge184
cvtsi2ss %r12d, %xmm1
movss .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
callq ceilf@PLT
cvtss2sd %xmm0, %xmm0
addsd .LCPI1_2(%rip), %xmm0
cvttsd2si %xmm0, %ebx
movl $.L.str.17, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.18, %edi
movl %ebx, %ebp
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
movq (%rsp), %rbx # 8-byte Reload
movq 96(%rsp), %r14 # 8-byte Reload
jne .LBB1_23
# %bb.27:
leaq 16(%rsp), %rdi
movq $-4, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_28
# %bb.29:
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_30
# %bb.31:
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq 88(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_32
# %bb.33:
movq 40(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_34
# %bb.35:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq $-4, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_36
# %bb.37:
movl %ebp, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_39
# %bb.38:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r15d, 76(%rsp)
movl $-1, 72(%rsp)
movl 48(%rsp), %eax # 4-byte Reload
movl %eax, 68(%rsp)
leaq 168(%rsp), %rax
movq %rax, 480(%rsp)
leaq 160(%rsp), %rax
movq %rax, 488(%rsp)
leaq 152(%rsp), %rax
movq %rax, 496(%rsp)
leaq 76(%rsp), %rax
movq %rax, 504(%rsp)
leaq 72(%rsp), %rax
movq %rax, 512(%rsp)
leaq 68(%rsp), %rax
movq %rax, 520(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 480(%rsp), %r9
movl $_Z20compute_displacementPfS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_39:
movq 16(%rsp), %rsi
movq %r13, %rdi
movq $-4, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_40
# %bb.41:
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_42
# %bb.43:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_44
# %bb.45:
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_46
# %bb.47:
callq hipDeviceReset
leaq 192(%rsp), %rdi
movl $.L.str.19, %esi
callq fopen
movq %rax, %rbx
cmpl $-2, %r15d
jg .LBB1_50
# %bb.48: # %.lr.ph188.preheader
movslq %r15d, %r14
incq %r14
movq %r14, %r12
.p2align 4, 0x90
.LBB1_49: # %.lr.ph188
# =>This Inner Loop Header: Depth=1
movss -4(%r13,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %esi
movq %rbx, %rdi
movl %r15d, %edx
movb $1, %al
callq fprintf
incl %r15d
incq %r12
cmpl $-1, %r14d
movq %r12, %r14
jne .LBB1_49
.LBB1_50: # %._crit_edge189
movq %rbx, %rdi
callq fclose
movq (%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq 80(%rsp), %rdi # 8-byte Reload
callq free
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $1960, %rsp # imm = 0x7A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 2016
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $38, %edx
jmp .LBB1_2
.LBB1_7:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $63, %edx
jmp .LBB1_8
.LBB1_13:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $91, %edx
jmp .LBB1_8
.LBB1_19:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $122, %edx
.LBB1_8:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_23:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $140, %edx
jmp .LBB1_2
.LBB1_28:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $141, %edx
jmp .LBB1_2
.LBB1_30:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $142, %edx
jmp .LBB1_2
.LBB1_32:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $144, %edx
jmp .LBB1_2
.LBB1_34:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $146, %edx
jmp .LBB1_2
.LBB1_36:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $148, %edx
jmp .LBB1_2
.LBB1_40:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $152, %edx
jmp .LBB1_2
.LBB1_42:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $154, %edx
jmp .LBB1_2
.LBB1_44:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $155, %edx
jmp .LBB1_2
.LBB1_46:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $156, %edx
.LBB1_2:
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20compute_displacementPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20compute_displacementPfS_S_iii,@object # @_Z20compute_displacementPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z20compute_displacementPfS_S_iii
.p2align 3, 0x0
_Z20compute_displacementPfS_S_iii:
.quad _Z35__device_stub__compute_displacementPfS_S_iii
.size _Z20compute_displacementPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "selection_coords.dat"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "eigenvector.dat"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "atomic_count_matrix.dat"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error: %s:%d, "
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/slaustin/gpu_sources/master/projection_r.hip"
.size .L.str.5, 102
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "code:%d, reason: %s\n"
.size .L.str.6, 21
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%i\t%i\t%f\t%f"
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Number of Atoms=%i\n"
.size .L.str.9, 20
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Max Frame=%i\n"
.size .L.str.10, 14
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Points=%i\n"
.size .L.str.11, 11
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Points*max_frame=%i\n"
.size .L.str.12, 21
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%f"
.size .L.str.14, 3
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%i\t%i"
.size .L.str.16, 6
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Threads=%i\n"
.size .L.str.17, 12
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Blocks=%i\n"
.size .L.str.18, 11
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "w"
.size .L.str.19, 2
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%i\t%f\n"
.size .L.str.20, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20compute_displacementPfS_S_iii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initilizing..."
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Reading Input..."
.size .Lstr.1, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Fill Matrix..."
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Complete!"
.size .Lstr.3, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__compute_displacementPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20compute_displacementPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20compute_displacementPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x180] ; /* 0x0000600000007a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0050*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fc80003f06270 */
/*0060*/ ISETP.LT.OR P0, PT, R6, c[0x0][0x178], P0 ; /* 0x00005e0006007a0c */
/* 0x000fc80000701670 */
/*0070*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R2, R0.reuse, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x040fe20007ffe0ff */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe400078ec0ff */
/*00d0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*00e0*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fc80000000f00 */
/*00f0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fce00078e0207 */
/*0100*/ @!P0 BRA 0xc70 ; /* 0x00000b6000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R9, -R0, c[0x0][0x180], RZ ; /* 0x0000600000097a10 */
/* 0x000fe20007ffe1ff */
/*0120*/ LDG.E R15, [R2.64] ; /* 0x00000004020f7981 */
/* 0x000162000c1e1900 */
/*0130*/ SHF.R.S32.HI R5, RZ, 0x1f, R6 ; /* 0x0000001fff057819 */
/* 0x000fe40000011406 */
/*0140*/ ISETP.GT.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f04270 */
/*0150*/ LEA R12, P1, R6.reuse, c[0x0][0x160], 0x2 ; /* 0x00005800060c7a11 */
/* 0x040fe400078210ff */
/*0160*/ MOV R8, RZ ; /* 0x000000ff00087202 */
/* 0x000fe40000000f00 */
/*0170*/ LEA.HI.X R13, R6, c[0x0][0x164], R5, 0x2, P1 ; /* 0x00005900060d7a11 */
/* 0x000fc400008f1405 */
/*0180*/ MOV R4, c[0x0][0x170] ; /* 0x00005c0000047a02 */
/* 0x000fe40000000f00 */
/*0190*/ MOV R5, c[0x0][0x174] ; /* 0x00005d0000057a02 */
/* 0x000fc60000000f00 */
/*01a0*/ @!P0 BRA 0xab0 ; /* 0x0000090000008947 */
/* 0x001fea0003800000 */
/*01b0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01d0*/ @!P1 BRA 0x780 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01f0*/ LDG.E R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1900 */
/*0200*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x000ea2000c1e1900 */
/*0210*/ MOV R10, c[0x0][0x17c] ; /* 0x00005f00000a7a02 */
/* 0x000fe20000000f00 */
/*0220*/ FFMA R11, R14, R11, R15 ; /* 0x0000000b0e0b7223 */
/* 0x024fc8000000000f */
/*0230*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x002fe200078e020c */
/*0240*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0250*/ LDG.E R16, [R4.64+0x4] ; /* 0x0000040404107981 */
/* 0x000ea8000c1e1900 */
/*0260*/ LDG.E R17, [R14.64] ; /* 0x000000040e117981 */
/* 0x000ea4000c1e1900 */
/*0270*/ FFMA R19, R16, R17, R11 ; /* 0x0000001110137223 */
/* 0x004fc4000000000b */
/*0280*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc600078e020e */
/*0290*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*02a0*/ LDG.E R18, [R4.64+0x8] ; /* 0x0000080404127981 */
/* 0x000ea8000c1e1900 */
/*02b0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ FFMA R21, R18, R12, R19 ; /* 0x0000000c12157223 */
/* 0x004fc40000000013 */
/*02d0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*02e0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*02f0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001ee8000c1e1900 */
/*0300*/ LDG.E R18, [R4.64+0xc] ; /* 0x00000c0404127981 */
/* 0x000ee2000c1e1900 */
/*0310*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0320*/ FFMA R11, R18, R11, R21 ; /* 0x0000000b120b7223 */
/* 0x008fca0000000015 */
/*0330*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0340*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000ee8000c1e1900 */
/*0350*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x002ee2000c1e1900 */
/*0360*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc800078e020e */
/*0370*/ FFMA R19, R18, R19, R11 ; /* 0x0000001312137223 */
/* 0x008fca000000000b */
/*0380*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0390*/ LDG.E R18, [R4.64+0x14] ; /* 0x0000140404127981 */
/* 0x000ea8000c1e1900 */
/*03a0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ FFMA R21, R18, R12, R19 ; /* 0x0000000c12157223 */
/* 0x004fc40000000013 */
/*03c0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*03d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*03e0*/ LDG.E R18, [R4.64+0x18] ; /* 0x0000180404127981 */
/* 0x000ee8000c1e1900 */
/*03f0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001ee2000c1e1900 */
/*0400*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0410*/ FFMA R11, R18, R11, R21 ; /* 0x0000000b120b7223 */
/* 0x008fca0000000015 */
/*0420*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0430*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x002ee8000c1e1900 */
/*0440*/ LDG.E R18, [R4.64+0x1c] ; /* 0x00001c0404127981 */
/* 0x000ee2000c1e1900 */
/*0450*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc800078e020e */
/*0460*/ FFMA R19, R18, R19, R11 ; /* 0x0000001312137223 */
/* 0x008fca000000000b */
/*0470*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0480*/ LDG.E R18, [R4.64+0x20] ; /* 0x0000200404127981 */
/* 0x000ea8000c1e1900 */
/*0490*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea2000c1e1900 */
/*04a0*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc800078e0210 */
/*04b0*/ FFMA R21, R18, R20, R19 ; /* 0x0000001412157223 */
/* 0x004fca0000000013 */
/*04c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*04d0*/ LDG.E R18, [R4.64+0x24] ; /* 0x0000240404127981 */
/* 0x000ee8000c1e1900 */
/*04e0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001ee2000c1e1900 */
/*04f0*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*0500*/ FFMA R11, R18, R11, R21 ; /* 0x0000000b120b7223 */
/* 0x008fca0000000015 */
/*0510*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0520*/ LDG.E R18, [R4.64+0x28] ; /* 0x0000280404127981 */
/* 0x000ee8000c1e1900 */
/*0530*/ LDG.E R19, [R14.64] ; /* 0x000000040e137981 */
/* 0x002ee2000c1e1900 */
/*0540*/ IMAD.WIDE R16, R10, 0x4, R14 ; /* 0x000000040a107825 */
/* 0x000fc800078e020e */
/*0550*/ FFMA R19, R18, R19, R11 ; /* 0x0000001312137223 */
/* 0x008fca000000000b */
/*0560*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0570*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R18, [R4.64+0x2c] ; /* 0x00002c0404127981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc800078e0210 */
/*05a0*/ FFMA R21, R18, R20, R19 ; /* 0x0000001412157223 */
/* 0x004fca0000000013 */
/*05b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*05c0*/ LDG.E R18, [R4.64+0x30] ; /* 0x0000300404127981 */
/* 0x000ee8000c1e1900 */
/*05d0*/ LDG.E R11, [R12.64] ; /* 0x000000040c0b7981 */
/* 0x001ee2000c1e1900 */
/*05e0*/ IMAD.WIDE R14, R10, 0x4, R12 ; /* 0x000000040a0e7825 */
/* 0x000fc800078e020c */
/*05f0*/ FFMA R11, R18, R11, R21 ; /* 0x0000000b120b7223 */
/* 0x008fca0000000015 */
/*0600*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e8000c101904 */
/*0610*/ LDG.E R18, [R4.64+0x34] ; /* 0x0000340404127981 */
/* 0x000ee8000c1e1900 */
/*0620*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee4000c1e1900 */
/*0630*/ FFMA R23, R18, R16, R11 ; /* 0x0000001012177223 */
/* 0x008fc4000000000b */
/*0640*/ IMAD.WIDE R18, R10, 0x4, R14 ; /* 0x000000040a127825 */
/* 0x002fc600078e020e */
/*0650*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0660*/ LDG.E R16, [R4.64+0x38] ; /* 0x0000380404107981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R17, [R18.64] ; /* 0x0000000412117981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IADD3 R9, R9, -0x10, RZ ; /* 0xfffffff009097810 */
/* 0x000fe20007ffe0ff */
/*0690*/ FFMA R21, R16, R17, R23 ; /* 0x0000001110157223 */
/* 0x004fc40000000017 */
/*06a0*/ IMAD.WIDE R16, R10, 0x4, R18 ; /* 0x000000040a107825 */
/* 0x000fc600078e0212 */
/*06b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*06c0*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x001ea8000c1e1900 */
/*06d0*/ LDG.E R12, [R4.64+0x3c] ; /* 0x00003c04040c7981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*06f0*/ IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008087810 */
/* 0x000fe20007ffe0ff */
/*0700*/ FFMA R15, R12, R11, R21 ; /* 0x0000000b0c0f7223 */
/* 0x004fe20000000015 */
/*0710*/ IADD3 R11, P2, R4, 0x40, RZ ; /* 0x00000040040b7810 */
/* 0x000fe20007f5e0ff */
/*0720*/ IMAD.WIDE R12, R10, 0x4, R16 ; /* 0x000000040a0c7825 */
/* 0x000fc600078e0210 */
/*0730*/ IADD3.X R14, RZ, R5, RZ, P2, !PT ; /* 0x00000005ff0e7210 */
/* 0x000fe200017fe4ff */
/*0740*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0003e2000c101904 */
/*0750*/ MOV R4, R11 ; /* 0x0000000b00047202 */
/* 0x000fe40000000f00 */
/*0760*/ MOV R5, R14 ; /* 0x0000000e00057202 */
/* 0x000fe20000000f00 */
/*0770*/ @P1 BRA 0x1f0 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*0780*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0790*/ @!P1 BRA 0xa90 ; /* 0x000002f000009947 */
/* 0x000fea0003800000 */
/*07a0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*07b0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*07c0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe20000000f00 */
/*07d0*/ FFMA R19, R10, R14, R15 ; /* 0x0000000e0a137223 */
/* 0x024fc8000000000f */
/*07e0*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x002fe200078e020c */
/*07f0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0800*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea8000c1e1900 */
/*0810*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea4000c1e1900 */
/*0820*/ FFMA R21, R10, R16, R19 ; /* 0x000000100a157223 */
/* 0x004fc40000000013 */
/*0830*/ IMAD.WIDE R16, R11, 0x4, R14 ; /* 0x000000040b107825 */
/* 0x000fc600078e020e */
/*0840*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0850*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea4000c1e1900 */
/*0870*/ FFMA R23, R10, R12, R21 ; /* 0x0000000c0a177223 */
/* 0x004fc40000000015 */
/*0880*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0210 */
/*0890*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*08a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*08b0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea2000c1e1900 */
/*08c0*/ IMAD.WIDE R14, R11, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x000fc800078e020c */
/*08d0*/ FFMA R25, R10, R18, R23 ; /* 0x000000120a197223 */
/* 0x004fca0000000017 */
/*08e0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*08f0*/ LDG.E R10, [R4.64+0x10] ; /* 0x00001004040a7981 */
/* 0x000e28000c1e1900 */
/*0900*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e24000c1e1900 */
/*0910*/ FFMA R21, R10, R18, R25 ; /* 0x000000120a157223 */
/* 0x001fc40000000019 */
/*0920*/ IMAD.WIDE R18, R11, 0x4, R14 ; /* 0x000000040b127825 */
/* 0x000fc600078e020e */
/*0930*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0940*/ LDG.E R10, [R4.64+0x14] ; /* 0x00001404040a7981 */
/* 0x000e68000c1e1900 */
/*0950*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000e64000c1e1900 */
/*0960*/ FFMA R23, R10, R12, R21 ; /* 0x0000000c0a177223 */
/* 0x002fc40000000015 */
/*0970*/ IMAD.WIDE R12, R11, 0x4, R18 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0212 */
/*0980*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0990*/ LDG.E R10, [R4.64+0x18] ; /* 0x00001804040a7981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea4000c1e1900 */
/*09b0*/ FFMA R25, R10, R16, R23 ; /* 0x000000100a197223 */
/* 0x004fc40000000017 */
/*09c0*/ IMAD.WIDE R16, R11, 0x4, R12 ; /* 0x000000040b107825 */
/* 0x000fc600078e020c */
/*09d0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*09e0*/ LDG.E R15, [R16.64] ; /* 0x00000004100f7981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R10, [R4.64+0x1c] ; /* 0x00001c04040a7981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a10*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fe200078e0210 */
/*0a20*/ IADD3 R8, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fc40007ffe0ff */
/*0a30*/ IADD3 R9, R9, -0x8, RZ ; /* 0xfffffff809097810 */
/* 0x000fe20007ffe0ff */
/*0a40*/ FFMA R15, R10, R15, R25 ; /* 0x0000000f0a0f7223 */
/* 0x004fe20000000019 */
/*0a50*/ IADD3 R10, P1, R4, 0x20, RZ ; /* 0x00000020040a7810 */
/* 0x000fc80007f3e0ff */
/*0a60*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e2000c101904 */
/*0a70*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0a80*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0a90*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0aa0*/ @!P0 BRA 0xc70 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0ab0*/ LDG.E R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ea8000c1e1900 */
/*0ac0*/ LDG.E R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1900 */
/*0ad0*/ MOV R11, c[0x0][0x17c] ; /* 0x00005f00000b7a02 */
/* 0x000fe20000000f00 */
/*0ae0*/ FFMA R21, R10, R14, R15 ; /* 0x0000000e0a157223 */
/* 0x027fc8000000000f */
/*0af0*/ IMAD.WIDE R14, R11.reuse, 0x4, R12 ; /* 0x000000040b0e7825 */
/* 0x040fe200078e020c */
/*0b00*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0001e8000c101904 */
/*0b10*/ LDG.E R10, [R4.64+0x4] ; /* 0x00000404040a7981 */
/* 0x000ea8000c1e1900 */
/*0b20*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ea2000c1e1900 */
/*0b30*/ IMAD.WIDE R18, R11, 0x4, R14 ; /* 0x000000040b127825 */
/* 0x000fc800078e020e */
/*0b40*/ FFMA R23, R10, R16, R21 ; /* 0x000000100a177223 */
/* 0x004fca0000000015 */
/*0b50*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R10, [R4.64+0x8] ; /* 0x00000804040a7981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0b80*/ IMAD.WIDE R16, R11, 0x4, R18 ; /* 0x000000040b107825 */
/* 0x000fe200078e0212 */
/*0b90*/ IADD3 R9, R9, -0x4, RZ ; /* 0xfffffffc09097810 */
/* 0x000fc60007ffe0ff */
/*0ba0*/ FFMA R25, R10, R12, R23 ; /* 0x0000000c0a197223 */
/* 0x004fca0000000017 */
/*0bb0*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0001e8000c101904 */
/*0bc0*/ LDG.E R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x000ea8000c1e1900 */
/*0bd0*/ LDG.E R10, [R4.64+0xc] ; /* 0x00000c04040a7981 */
/* 0x000ea2000c1e1900 */
/*0be0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0bf0*/ IADD3 R8, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fe20007ffe0ff */
/*0c00*/ FFMA R15, R10, R12, R25 ; /* 0x0000000c0a0f7223 */
/* 0x004fe20000000019 */
/*0c10*/ IADD3 R10, P1, R4, 0x10, RZ ; /* 0x00000010040a7810 */
/* 0x000fe20007f3e0ff */
/*0c20*/ IMAD.WIDE R12, R11, 0x4, R16 ; /* 0x000000040b0c7825 */
/* 0x000fc600078e0210 */
/*0c30*/ STG.E [R2.64], R15 ; /* 0x0000000f02007986 */
/* 0x0001e2000c101904 */
/*0c40*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe40000ffe4ff */
/*0c50*/ MOV R4, R10 ; /* 0x0000000a00047202 */
/* 0x000fe40000000f00 */
/*0c60*/ @P0 BRA 0xab0 ; /* 0xfffffe4000000947 */
/* 0x001fea000383ffff */
/*0c70*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0c80*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0c90*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000562000c1e1900 */
/*0ca0*/ IMAD.WIDE R4, R8, R7, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fc800078e0207 */
/*0cb0*/ IMAD R6, R8, c[0x0][0x17c], R6 ; /* 0x00005f0008067a24 */
/* 0x000fe200078e0206 */
/*0cc0*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fe40000000f00 */
/*0cd0*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fe20000000f00 */
/*0ce0*/ IMAD.WIDE R4, R6, R7, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fc800078e0207 */
/*0cf0*/ MOV R6, R10 ; /* 0x0000000a00067202 */
/* 0x000fe20000000f00 */
/*0d00*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x008722000c1e1900 */
/*0d10*/ MOV R7, R11 ; /* 0x0000000b00077202 */
/* 0x000fca0000000f00 */
/*0d20*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f22000c1e1900 */
/*0d30*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0d40*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fe40000000f00 */
/*0d50*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05270 */
/*0d60*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fe20007f3e0ff */
/*0d70*/ IMAD.WIDE R4, R13, 0x4, R4 ; /* 0x000000040d047825 */
/* 0x008fc600078e0204 */
/*0d80*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0d90*/ FFMA R9, R6, R8, R9 ; /* 0x0000000806097223 */
/* 0x030fca0000000009 */
/*0da0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0007e2000c101904 */
/*0db0*/ @P0 BRA 0xcf0 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0dc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0dd0*/ BRA 0xdd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20compute_displacementPfS_S_iii
.globl _Z20compute_displacementPfS_S_iii
.p2align 8
.type _Z20compute_displacementPfS_S_iii,@function
_Z20compute_displacementPfS_S_iii:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_le_i32_e32 vcc_lo, s2, v1
v_cmp_gt_i32_e64 s2, s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s8, 0
s_cselect_b32 s4, -1, 0
s_and_b32 s2, s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[3:4], off
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_add_i32 s8, s8, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_add_nc_u32_e32 v1, s3, v1
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_load_b32 v2, v5, s[0:1]
global_load_b32 v6, v[6:7], off
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s8, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, v6, v2
global_store_b32 v[3:4], v0, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20compute_displacementPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20compute_displacementPfS_S_iii, .Lfunc_end0-_Z20compute_displacementPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20compute_displacementPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20compute_displacementPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000850ea_00000000-6_projection_r.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii
.type _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii, @function
_Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z20compute_displacementPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii, .-_Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii
.globl _Z20compute_displacementPfS_S_iii
.type _Z20compute_displacementPfS_S_iii, @function
_Z20compute_displacementPfS_S_iii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z20compute_displacementPfS_S_iii, .-_Z20compute_displacementPfS_S_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "selection_coords.dat"
.LC2:
.string "eigenvector.dat"
.LC3:
.string "atomic_count_matrix.dat"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/slaustin/gpu_sources/master/projection_r.cu"
.section .rodata.str1.1
.LC5:
.string "Error: %s:%d, "
.LC6:
.string "code:%d, reason: %s\n"
.LC7:
.string "Initilizing...\n"
.LC8:
.string "%i\t%i\t%f\t%f"
.LC9:
.string "Number of Atoms=%i\n"
.LC10:
.string "Max Frame=%i\n"
.LC11:
.string "Points=%i\n"
.LC12:
.string "Points*max_frame=%i\n"
.LC13:
.string "Reading Input...\n"
.LC14:
.string "%f"
.LC15:
.string "Fill Matrix...\n"
.LC16:
.string "%i\t%i"
.LC21:
.string "Threads=%i\n"
.LC22:
.string "Blocks=%i\n"
.LC23:
.string "w"
.LC24:
.string "%i\t%f\n"
.LC25:
.string "Complete!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1480, %rsp
.cfi_def_cfa_offset 1536
movq %fs:40, %rax
movq %rax, 1464(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
leaq .LC1(%rip), %rdi
call fopen@PLT
movq %rax, %r12
movq %rbx, %rsi
leaq .LC2(%rip), %rdi
call fopen@PLT
movq %rax, %r13
movq %rbx, %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, 32(%rsp)
movabsq $7305790138896050532, %rax
movabsq $8386094131825239405, %rdx
movq %rax, 1168(%rsp)
movq %rdx, 1176(%rsp)
movb $0, 1184(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
testl %eax, %eax
jne .L47
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
movl $0, %ebx
leaq .LC8(%rip), %r14
jmp .L13
.L47:
movl %eax, %ebx
movl $38, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L14:
movl 60(%rsp), %ebx
cmpl %r15d, %ebx
je .L48
.L13:
leaq 1200(%rsp), %rdi
movq %r12, %rcx
movl $256, %edx
movl $256, %esi
call __fgets_chk@PLT
testq %rax, %rax
je .L49
leaq 64(%rsp), %rcx
leaq 60(%rsp), %rdx
leaq 1200(%rsp), %rdi
leaq 76(%rsp), %r9
leaq 72(%rsp), %r8
movq %r14, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
testl %ebp, %ebp
jne .L14
movl 60(%rsp), %ebx
.L15:
addl $1, %ebp
movl %ebx, %r15d
jmp .L13
.L48:
movl %r15d, %ebx
jmp .L15
.L49:
movq %r12, %rdi
call fclose@PLT
movslq %ebp, %r12
imulq $1431655766, %r12, %rdx
shrq $32, %rdx
movl %ebp, %eax
sarl $31, %eax
subl %eax, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imull %ebp, %ebx
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(,%r12,4), %rax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
testq %rax, %rax
je .L50
movq 8(%rsp), %rcx
movq %rcx, %rdx
movl $0, %esi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call __memset_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC14(%rip), %r12
jmp .L19
.L50:
movl $63, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
leaq 68(%rsp), %rdx
leaq 1200(%rsp), %rdi
movq %r12, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movss 68(%rsp), %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
.L19:
leaq 1200(%rsp), %rdi
movq %r13, %rcx
movl $256, %edx
movl $256, %esi
call __fgets_chk@PLT
testq %rax, %rax
jne .L20
movq %r13, %rdi
call fclose@PLT
movq 8(%rsp), %rax
negq %rax
movq %rax, 24(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r14
testq %rax, %rax
je .L51
movq 24(%rsp), %rcx
movq %rcx, %rdx
movl $0, %esi
movq %rax, %rdi
call __memset_chk@PLT
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
movl $99999999, %ebx
movl $-1, %r13d
leaq .LC16(%rip), %r15
movl %ebp, 44(%rsp)
movq 32(%rsp), %rbp
jmp .L22
.L51:
movl $91, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L24:
leaq 56(%rsp), %rcx
leaq 52(%rsp), %rdx
leaq 1200(%rsp), %rdi
movq %r15, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movl 52(%rsp), %eax
cmpl %r13d, %eax
movl $0, %edx
cmovne %edx, %r12d
movl %eax, %edx
subl %r12d, %edx
movslq %edx, %rdx
pxor %xmm0, %xmm0
cvtsi2ssl 56(%rsp), %xmm0
movss %xmm0, (%r14,%rdx,4)
addl $1, %r12d
cmpl %eax, %ebx
cmovg %eax, %ebx
movl %eax, %r13d
.L22:
leaq 1200(%rsp), %rdi
movq %rbp, %rcx
movl $256, %edx
movl $256, %esi
call __fgets_chk@PLT
testq %rax, %rax
jne .L24
movl 44(%rsp), %ebp
movq 32(%rsp), %rdi
call fclose@PLT
movq $-4, %rdi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L52
movq $-4, %rdx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
leaq 48(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 48(%rsp)
jle .L26
movl $0, %r12d
leaq 128(%rsp), %r15
.L27:
movl %r12d, %esi
movq %r15, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 448(%rsp), %eax
addl $1, %r12d
cmpl %r12d, 48(%rsp)
jg .L27
movl %eax, 40(%rsp)
.L26:
pxor %xmm1, %xmm1
cvtsi2ssl 40(%rsp), %xmm1
movss .LC17(%rip), %xmm0
divss %xmm1, %xmm0
movaps %xmm0, %xmm1
movss .LC26(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC18(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L28
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC20(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L28:
addss .LC20(%rip), %xmm1
cvttss2sil %xmm1, %r12d
movl 40(%rsp), %edx
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, %edx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 88(%rsp), %rdi
movq 24(%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L53
leaq 96(%rsp), %rdi
movq $-4, %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L54
leaq 80(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L55
movl $1, %ecx
movq 24(%rsp), %rdx
movq %r14, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L56
movl $1, %ecx
movq 8(%rsp), %rdx
movq 16(%rsp), %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L57
movl $1, %ecx
movq $-4, %rdx
movq %r13, %rsi
movq 96(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r15d
testl %eax, %eax
jne .L58
movl 40(%rsp), %eax
movl %eax, 116(%rsp)
movl $1, 120(%rsp)
movl %r12d, 104(%rsp)
movl $1, 108(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 116(%rsp), %rdx
movl $1, %ecx
movq 104(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L35:
movl $2, %ecx
movq $-4, %rdx
movq 96(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L60
movq 88(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L61
movq 96(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L62
movq 80(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L63
call cudaDeviceReset@PLT
leaq 1168(%rsp), %rdi
leaq .LC23(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
cmpl $-1, %ebx
jge .L40
movslq %ebx, %rbx
leaq .LC24(%rip), %r12
.L41:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movl %ebx, %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $1, %eax
call __fprintf_chk@PLT
addq $1, %rbx
cmpl $-1, %ebx
jl .L41
.L40:
movq %rbp, %rdi
call fclose@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 16(%rsp), %rdi
call free@PLT
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 1464(%rsp), %rax
subq %fs:40, %rax
jne .L64
movl $0, %eax
addq $1480, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl $122, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl $140, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl $141, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
movl $142, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movl $144, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L57:
movl $146, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
movl $148, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %r15d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl %ebp, %r9d
movl $-1, %r8d
movl %ebx, %ecx
movq 80(%rsp), %rdx
movq 96(%rsp), %rsi
movq 88(%rsp), %rdi
call _Z47__device_stub__Z20compute_displacementPfS_S_iiiPfS_S_iii
jmp .L35
.L60:
movl $152, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl $154, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L62:
movl $155, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L63:
movl $156, %ecx
leaq .LC4(%rip), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC27:
.string "_Z20compute_displacementPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC27(%rip), %rdx
movq %rdx, %rcx
leaq _Z20compute_displacementPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long -1082130432
.align 4
.LC18:
.long 1258291200
.align 4
.LC20:
.long 1065353216
.align 4
.LC26:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "projection_r.hip"
.globl _Z35__device_stub__compute_displacementPfS_S_iii # -- Begin function _Z35__device_stub__compute_displacementPfS_S_iii
.p2align 4, 0x90
.type _Z35__device_stub__compute_displacementPfS_S_iii,@function
_Z35__device_stub__compute_displacementPfS_S_iii: # @_Z35__device_stub__compute_displacementPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z20compute_displacementPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z35__device_stub__compute_displacementPfS_S_iii, .Lfunc_end0-_Z35__device_stub__compute_displacementPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.byte 100 # 0x64
.byte 105 # 0x69
.byte 115 # 0x73
.byte 112 # 0x70
.byte 108 # 0x6c
.byte 97 # 0x61
.byte 99 # 0x63
.byte 101 # 0x65
.byte 109 # 0x6d
.byte 101 # 0x65
.byte 110 # 0x6e
.byte 116 # 0x74
.byte 46 # 0x2e
.byte 100 # 0x64
.byte 97 # 0x61
.byte 116 # 0x74
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_1:
.long 0xbf800000 # float -1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1960, %rsp # imm = 0x7A8
.cfi_def_cfa_offset 2016
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, %r14
movl $.L.str.2, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, (%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movl $.L.str.1, %esi
callq fopen
movq %rax, 24(%rsp) # 8-byte Spill
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [100,105,115,112,108,97,99,101,109,101,110,116,46,100,97,116]
movaps %xmm0, 192(%rsp)
movb $0, 208(%rsp)
xorl %ebp, %ebp
xorl %edi, %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB1_1
# %bb.3:
movl $.Lstr, %edi
callq puts@PLT
leaq 224(%rsp), %rdi
movl $256, %esi # imm = 0x100
movq %r14, %rdx
callq fgets
movl $0, %r15d
testq %rax, %rax
je .LBB1_6
# %bb.4: # %.lr.ph.preheader
leaq 224(%rsp), %r12
leaq 180(%rsp), %rbx
xorl %ebp, %ebp
# implicit-def: $r13d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.8, %esi
movq %r12, %rdi
leaq 56(%rsp), %rdx
leaq 188(%rsp), %rcx
leaq 184(%rsp), %r8
movq %rbx, %r9
xorl %eax, %eax
callq __isoc23_sscanf
testl %ebp, %ebp
movl 56(%rsp), %r15d
cmovel %r15d, %r13d
xorl %eax, %eax
cmpl %r15d, %r13d
sete %al
addl %eax, %ebp
movq %r12, %rdi
movl $256, %esi # imm = 0x100
movq %r14, %rdx
callq fgets
testq %rax, %rax
jne .LBB1_5
.LBB1_6: # %._crit_edge
movq %r14, %rdi
callq fclose
movl %ebp, %ebx
movl $2863311531, %esi # imm = 0xAAAAAAAB
imulq %rbx, %rsi
shrq $33, %rsi
movl $.L.str.9, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.10, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.11, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
imull %ebp, %r15d
movl $.L.str.12, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
testq %rax, %rax
je .LBB1_7
# %bb.9:
movq %rax, %r12
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, 96(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq memset@PLT
movl $.Lstr.1, %edi
callq puts@PLT
leaq 224(%rsp), %rdi
movl $256, %esi # imm = 0x100
movq (%rsp), %r13 # 8-byte Reload
movq %r13, %rdx
callq fgets
testq %rax, %rax
je .LBB1_12
# %bb.10: # %.lr.ph170.preheader
leaq 224(%rsp), %rbx
leaq 52(%rsp), %r14
movq %r12, %r15
.p2align 4, 0x90
.LBB1_11: # %.lr.ph170
# =>This Inner Loop Header: Depth=1
movl $.L.str.14, %esi
movq %rbx, %rdi
movq %r14, %rdx
xorl %eax, %eax
callq __isoc23_sscanf
movss 52(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%r15)
movq %rbx, %rdi
movl $256, %esi # imm = 0x100
movq %r13, %rdx
callq fgets
addq $4, %r15
testq %rax, %rax
jne .LBB1_11
.LBB1_12: # %._crit_edge171
movq %r13, %rdi
callq fclose
movl %ebp, %eax
negl %eax
movslq %eax, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
testq %rax, %rax
je .LBB1_13
# %bb.14:
movl %ebp, 48(%rsp) # 4-byte Spill
movq %r12, 80(%rsp) # 8-byte Spill
movq %rax, (%rsp) # 8-byte Spill
movq %rax, %rdi
xorl %esi, %esi
movq %rbx, 88(%rsp) # 8-byte Spill
movq %rbx, %rdx
callq memset@PLT
movl $.Lstr.2, %edi
callq puts@PLT
leaq 224(%rsp), %rdi
movl $256, %esi # imm = 0x100
movq 24(%rsp), %rdx # 8-byte Reload
callq fgets
movl $99999999, %r15d # imm = 0x5F5E0FF
testq %rax, %rax
je .LBB1_15
# %bb.16: # %.lr.ph178.preheader
movl $-1, %r14d
xorl %r13d, %r13d
movq 24(%rsp), %rbp # 8-byte Reload
.p2align 4, 0x90
.LBB1_17: # %.lr.ph178
# =>This Inner Loop Header: Depth=1
movl $.L.str.16, %esi
leaq 224(%rsp), %r12
movq %r12, %rdi
leaq 64(%rsp), %rdx
leaq 60(%rsp), %rcx
xorl %eax, %eax
callq __isoc23_sscanf
movl 64(%rsp), %ebx
cmpl %ebx, %r14d
movl $0, %eax
cmovnel %eax, %r13d
xorps %xmm0, %xmm0
cvtsi2ssl 60(%rsp), %xmm0
movl %ebx, %eax
subl %r13d, %eax
cltq
movq (%rsp), %rcx # 8-byte Reload
movss %xmm0, (%rcx,%rax,4)
incl %r13d
cmpl %r15d, %ebx
cmovll %ebx, %r15d
movq %r12, %rdi
movl $256, %esi # imm = 0x100
movq %rbp, %rdx
callq fgets
movl %ebx, %r14d
testq %rax, %rax
jne .LBB1_17
jmp .LBB1_18
.LBB1_15:
movq 24(%rsp), %rbp # 8-byte Reload
.LBB1_18: # %._crit_edge179
movq %rbp, %rdi
callq fclose
movq $-4, %rdi
callq malloc
testq %rax, %rax
je .LBB1_19
# %bb.20:
movq %rax, %r13
xorl %ebx, %ebx
movq %rax, %rdi
xorl %esi, %esi
movq $-4, %rdx
callq memset@PLT
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB1_21
# %bb.24: # %.lr.ph183
leaq 480(%rsp), %r14
.p2align 4, 0x90
.LBB1_25: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebx, %esi
callq hipGetDevicePropertiesR0600
incl %ebx
cmpl 12(%rsp), %ebx
jl .LBB1_25
# %bb.26:
movl 800(%rsp), %r12d
jmp .LBB1_22
.LBB1_21:
# implicit-def: $r12d
.LBB1_22: # %._crit_edge184
cvtsi2ss %r12d, %xmm1
movss .LCPI1_1(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss %xmm1, %xmm0
callq ceilf@PLT
cvtss2sd %xmm0, %xmm0
addsd .LCPI1_2(%rip), %xmm0
cvttsd2si %xmm0, %ebx
movl $.L.str.17, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl $.L.str.18, %edi
movl %ebx, %ebp
movl %ebx, %esi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movq 88(%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
movq (%rsp), %rbx # 8-byte Reload
movq 96(%rsp), %r14 # 8-byte Reload
jne .LBB1_23
# %bb.27:
leaq 16(%rsp), %rdi
movq $-4, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_28
# %bb.29:
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_30
# %bb.31:
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq 88(%rsp), %rdx # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_32
# %bb.33:
movq 40(%rsp), %rdi
movq 80(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_34
# %bb.35:
movq 16(%rsp), %rdi
movq %r13, %rsi
movq $-4, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_36
# %bb.37:
movl %ebp, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r12d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_39
# %bb.38:
movq 32(%rsp), %rax
movq 16(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %r15d, 76(%rsp)
movl $-1, 72(%rsp)
movl 48(%rsp), %eax # 4-byte Reload
movl %eax, 68(%rsp)
leaq 168(%rsp), %rax
movq %rax, 480(%rsp)
leaq 160(%rsp), %rax
movq %rax, 488(%rsp)
leaq 152(%rsp), %rax
movq %rax, 496(%rsp)
leaq 76(%rsp), %rax
movq %rax, 504(%rsp)
leaq 72(%rsp), %rax
movq %rax, 512(%rsp)
leaq 68(%rsp), %rax
movq %rax, 520(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 480(%rsp), %r9
movl $_Z20compute_displacementPfS_S_iii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_39:
movq 16(%rsp), %rsi
movq %r13, %rdi
movq $-4, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_40
# %bb.41:
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_42
# %bb.43:
movq 16(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_44
# %bb.45:
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB1_46
# %bb.47:
callq hipDeviceReset
leaq 192(%rsp), %rdi
movl $.L.str.19, %esi
callq fopen
movq %rax, %rbx
cmpl $-2, %r15d
jg .LBB1_50
# %bb.48: # %.lr.ph188.preheader
movslq %r15d, %r14
incq %r14
movq %r14, %r12
.p2align 4, 0x90
.LBB1_49: # %.lr.ph188
# =>This Inner Loop Header: Depth=1
movss -4(%r13,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.20, %esi
movq %rbx, %rdi
movl %r15d, %edx
movb $1, %al
callq fprintf
incl %r15d
incq %r12
cmpl $-1, %r14d
movq %r12, %r14
jne .LBB1_49
.LBB1_50: # %._crit_edge189
movq %rbx, %rdi
callq fclose
movq (%rsp), %rdi # 8-byte Reload
callq free
movq %r13, %rdi
callq free
movq 80(%rsp), %rdi # 8-byte Reload
callq free
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $1960, %rsp # imm = 0x7A8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 2016
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $38, %edx
jmp .LBB1_2
.LBB1_7:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $63, %edx
jmp .LBB1_8
.LBB1_13:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $91, %edx
jmp .LBB1_8
.LBB1_19:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $122, %edx
.LBB1_8:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB1_23:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $140, %edx
jmp .LBB1_2
.LBB1_28:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $141, %edx
jmp .LBB1_2
.LBB1_30:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $142, %edx
jmp .LBB1_2
.LBB1_32:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $144, %edx
jmp .LBB1_2
.LBB1_34:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $146, %edx
jmp .LBB1_2
.LBB1_36:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $148, %edx
jmp .LBB1_2
.LBB1_40:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $152, %edx
jmp .LBB1_2
.LBB1_42:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $154, %edx
jmp .LBB1_2
.LBB1_44:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $155, %edx
jmp .LBB1_2
.LBB1_46:
movl $.L.str.4, %edi
movl $.L.str.5, %esi
movl $156, %edx
.LBB1_2:
movl %eax, %ebx
xorl %eax, %eax
callq printf
movl %ebx, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20compute_displacementPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20compute_displacementPfS_S_iii,@object # @_Z20compute_displacementPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z20compute_displacementPfS_S_iii
.p2align 3, 0x0
_Z20compute_displacementPfS_S_iii:
.quad _Z35__device_stub__compute_displacementPfS_S_iii
.size _Z20compute_displacementPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "selection_coords.dat"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "r"
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "eigenvector.dat"
.size .L.str.2, 16
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "atomic_count_matrix.dat"
.size .L.str.3, 24
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error: %s:%d, "
.size .L.str.4, 15
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/slaustin/gpu_sources/master/projection_r.hip"
.size .L.str.5, 102
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "code:%d, reason: %s\n"
.size .L.str.6, 21
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%i\t%i\t%f\t%f"
.size .L.str.8, 12
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Number of Atoms=%i\n"
.size .L.str.9, 20
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Max Frame=%i\n"
.size .L.str.10, 14
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Points=%i\n"
.size .L.str.11, 11
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Points*max_frame=%i\n"
.size .L.str.12, 21
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "%f"
.size .L.str.14, 3
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "%i\t%i"
.size .L.str.16, 6
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Threads=%i\n"
.size .L.str.17, 12
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Blocks=%i\n"
.size .L.str.18, 11
.type .L.str.19,@object # @.str.19
.L.str.19:
.asciz "w"
.size .L.str.19, 2
.type .L.str.20,@object # @.str.20
.L.str.20:
.asciz "%i\t%f\n"
.size .L.str.20, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20compute_displacementPfS_S_iii"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Initilizing..."
.size .Lstr, 15
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Reading Input..."
.size .Lstr.1, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Fill Matrix..."
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "Complete!"
.size .Lstr.3, 10
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__compute_displacementPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20compute_displacementPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
/*
__global__ static inline int mandel(float c_re, float c_im, int count)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < count; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
*/
__global__ void mandelKernel( int* d_data,float stepX, float stepY,float lowerX,float lowerY ,int width, int maxIterations, size_t pitch) {
// To avoid error caused by the floating number, use the following pseudo code
//
int thisX= blockIdx.x * blockDim.x + threadIdx.x;
int thisY= blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x, c_im = y;
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
int *ptr = (int *)((char*)d_data+thisY*pitch);
ptr[thisX] = i;
//d_data[ thisX + thisY * width ] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *data, *d_data;
dim3 threadPerBlock(25,25);
dim3 numBlocks(resX/threadPerBlock.x,resY/threadPerBlock.y);
size_t pitch;
//data = (int*)malloc( sizeof(int)*resX*resY );
cudaHostAlloc(&data, sizeof(int) * resX*resY, cudaHostAllocMapped);
cudaMallocPitch((void **)&d_data, &pitch, sizeof(int)*resX, resY);
// cudaMalloc((void**)&d_data, sizeof(int)*resX*resY );
mandelKernel<<<numBlocks,threadPerBlock>>>(d_data,stepX,stepY,lowerX,lowerY,resX,maxIterations,pitch);
cudaMemcpy2D(data, sizeof(int)*resX, d_data, pitch, sizeof(int)*resX, resY, cudaMemcpyDeviceToHost);
memcpy(img,data,sizeof(int)*resX*resY);
cudaFreeHost(data);
cudaFree(d_data);
} | code for sm_80
Function : _Z12mandelKernelPiffffiim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fc800078e0200 */
/*0080*/ I2F R2, R5 ; /* 0x0000000500027306 */
/* 0x000e220000201400 */
/*0090*/ IMAD R0, R3, c[0x0][0x4], R4 ; /* 0x0000010003007a24 */
/* 0x002fe200078e0204 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fcc0000000f00 */
/*00b0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*00c0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f06270 */
/*00d0*/ MOV R4, c[0x0][0x16c] ; /* 0x00005b0000047a02 */
/* 0x000fe20000000f00 */
/*00e0*/ FFMA R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027623 */
/* 0x001fe20000000007 */
/*00f0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fc600000001ff */
/*0100*/ FFMA R3, R3, R4, c[0x0][0x174] ; /* 0x00005d0003037623 */
/* 0x002fcc0000000004 */
/*0110*/ @!P0 BRA 0x230 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x230 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0130*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc60000000f00 */
/*0160*/ FMUL R9, R4, R4 ; /* 0x0000000404097220 */
/* 0x000fe40000400000 */
/*0170*/ FMUL R8, R6, R6 ; /* 0x0000000606087220 */
/* 0x000fc80000400000 */
/*0180*/ FADD R10, R9, R8 ; /* 0x00000008090a7221 */
/* 0x000fca0000000000 */
/*0190*/ FSETP.GT.AND P0, PT, R10, 4, PT ; /* 0x408000000a00780b */
/* 0x000fda0003f04000 */
/*01a0*/ @P0 BRA 0x220 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ FADD R6, R6, R6 ; /* 0x0000000606067221 */
/* 0x000fe40000000000 */
/*01d0*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fe20000000100 */
/*01e0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ FFMA R4, R6, R4, R3 ; /* 0x0000000406047223 */
/* 0x000fe40000000003 */
/*0200*/ FADD R6, R2, R9 ; /* 0x0000000902067221 */
/* 0x000fd40000000000 */
/*0210*/ @!P0 BRA 0x160 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fe40000011400 */
/*0240*/ MOV R3, c[0x0][0x180] ; /* 0x0000600000037a02 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD R9, R2, c[0x0][0x180], RZ ; /* 0x0000600002097a24 */
/* 0x000fe400078e02ff */
/*0260*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*0270*/ IMAD R9, R0, c[0x0][0x184], R9 ; /* 0x0000610000097a24 */
/* 0x000fca00078e0209 */
/*0280*/ IADD3 R3, R3, R9, RZ ; /* 0x0000000903037210 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD.WIDE R2, R5, 0x4, R2 ; /* 0x0000000405027825 */
/* 0x000fca00078e0202 */
/*02a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
/*
__global__ static inline int mandel(float c_re, float c_im, int count)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < count; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
*/
__global__ void mandelKernel( int* d_data,float stepX, float stepY,float lowerX,float lowerY ,int width, int maxIterations, size_t pitch) {
// To avoid error caused by the floating number, use the following pseudo code
//
int thisX= blockIdx.x * blockDim.x + threadIdx.x;
int thisY= blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x, c_im = y;
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
int *ptr = (int *)((char*)d_data+thisY*pitch);
ptr[thisX] = i;
//d_data[ thisX + thisY * width ] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *data, *d_data;
dim3 threadPerBlock(25,25);
dim3 numBlocks(resX/threadPerBlock.x,resY/threadPerBlock.y);
size_t pitch;
//data = (int*)malloc( sizeof(int)*resX*resY );
cudaHostAlloc(&data, sizeof(int) * resX*resY, cudaHostAllocMapped);
cudaMallocPitch((void **)&d_data, &pitch, sizeof(int)*resX, resY);
// cudaMalloc((void**)&d_data, sizeof(int)*resX*resY );
mandelKernel<<<numBlocks,threadPerBlock>>>(d_data,stepX,stepY,lowerX,lowerY,resX,maxIterations,pitch);
cudaMemcpy2D(data, sizeof(int)*resX, d_data, pitch, sizeof(int)*resX, resY, cudaMemcpyDeviceToHost);
memcpy(img,data,sizeof(int)*resX*resY);
cudaFreeHost(data);
cudaFree(d_data);
} | .file "tmpxft_00047da1_00000000-6_kernel2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim
.type _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim, @function
_Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mandelKernelPiffffiim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim, .-_Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim
.globl _Z12mandelKernelPiffffiim
.type _Z12mandelKernelPiffffiim, @function
_Z12mandelKernelPiffffiim:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mandelKernelPiffffiim, .-_Z12mandelKernelPiffffiim
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 24(%rsp)
movq %rdi, %r14
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, 28(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 72(%rsp)
movl %esi, %eax
imulq $1374389535, %rax, %rax
shrq $35, %rax
movl %eax, 76(%rsp)
movl %edx, %eax
imulq $1374389535, %rax, %rax
shrq $35, %rax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movslq %esi, %rbx
movslq %edx, %r15
movq %rbx, %r13
imulq %r15, %r13
salq $2, %r13
leaq 40(%rsp), %rdi
movl $2, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
salq $2, %rbx
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %r15, %rcx
movq %rbx, %rdx
call cudaMallocPitch@PLT
movl $25, 64(%rsp)
movl $25, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %r15, %r9
movq %rbx, %r8
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy2D@PLT
movq 56(%rsp), %rbx
movq %r13, %rdx
movq %rbx, %rsi
movq %r14, %rdi
call memcpy@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq %rbx, %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movss 16(%rsp), %xmm1
movss 24(%rsp), %xmm3
subss %xmm3, %xmm1
pxor %xmm4, %xmm4
cvtsi2ssl %r12d, %xmm4
movss 12(%rsp), %xmm0
movss 20(%rsp), %xmm5
subss %xmm5, %xmm0
pxor %xmm2, %xmm2
cvtsi2ssl %ebp, %xmm2
divss %xmm2, %xmm0
movq 56(%rsp), %rcx
movl 28(%rsp), %edx
movl %ebp, %esi
movaps %xmm5, %xmm2
divss %xmm4, %xmm1
movq 48(%rsp), %rdi
call _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelPiffffiim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelPiffffiim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
#include <stdlib.h>
/*
__global__ static inline int mandel(float c_re, float c_im, int count)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < count; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
*/
__global__ void mandelKernel( int* d_data,float stepX, float stepY,float lowerX,float lowerY ,int width, int maxIterations, size_t pitch) {
// To avoid error caused by the floating number, use the following pseudo code
//
int thisX= blockIdx.x * blockDim.x + threadIdx.x;
int thisY= blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x, c_im = y;
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
int *ptr = (int *)((char*)d_data+thisY*pitch);
ptr[thisX] = i;
//d_data[ thisX + thisY * width ] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *data, *d_data;
dim3 threadPerBlock(25,25);
dim3 numBlocks(resX/threadPerBlock.x,resY/threadPerBlock.y);
size_t pitch;
//data = (int*)malloc( sizeof(int)*resX*resY );
cudaHostAlloc(&data, sizeof(int) * resX*resY, cudaHostAllocMapped);
cudaMallocPitch((void **)&d_data, &pitch, sizeof(int)*resX, resY);
// cudaMalloc((void**)&d_data, sizeof(int)*resX*resY );
mandelKernel<<<numBlocks,threadPerBlock>>>(d_data,stepX,stepY,lowerX,lowerY,resX,maxIterations,pitch);
cudaMemcpy2D(data, sizeof(int)*resX, d_data, pitch, sizeof(int)*resX, resY, cudaMemcpyDeviceToHost);
memcpy(img,data,sizeof(int)*resX*resY);
cudaFreeHost(data);
cudaFree(d_data);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
__global__ static inline int mandel(float c_re, float c_im, int count)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < count; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
*/
__global__ void mandelKernel( int* d_data,float stepX, float stepY,float lowerX,float lowerY ,int width, int maxIterations, size_t pitch) {
// To avoid error caused by the floating number, use the following pseudo code
//
int thisX= blockIdx.x * blockDim.x + threadIdx.x;
int thisY= blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x, c_im = y;
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
int *ptr = (int *)((char*)d_data+thisY*pitch);
ptr[thisX] = i;
//d_data[ thisX + thisY * width ] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *data, *d_data;
dim3 threadPerBlock(25,25);
dim3 numBlocks(resX/threadPerBlock.x,resY/threadPerBlock.y);
size_t pitch;
//data = (int*)malloc( sizeof(int)*resX*resY );
hipHostAlloc(&data, sizeof(int) * resX*resY, hipHostMallocMapped);
hipMallocPitch((void **)&d_data, &pitch, sizeof(int)*resX, resY);
// cudaMalloc((void**)&d_data, sizeof(int)*resX*resY );
mandelKernel<<<numBlocks,threadPerBlock>>>(d_data,stepX,stepY,lowerX,lowerY,resX,maxIterations,pitch);
hipMemcpy2D(data, sizeof(int)*resX, d_data, pitch, sizeof(int)*resX, resY, hipMemcpyDeviceToHost);
memcpy(img,data,sizeof(int)*resX*resY);
hipHostFree(data);
hipFree(d_data);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
__global__ static inline int mandel(float c_re, float c_im, int count)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < count; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
*/
__global__ void mandelKernel( int* d_data,float stepX, float stepY,float lowerX,float lowerY ,int width, int maxIterations, size_t pitch) {
// To avoid error caused by the floating number, use the following pseudo code
//
int thisX= blockIdx.x * blockDim.x + threadIdx.x;
int thisY= blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x, c_im = y;
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
int *ptr = (int *)((char*)d_data+thisY*pitch);
ptr[thisX] = i;
//d_data[ thisX + thisY * width ] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *data, *d_data;
dim3 threadPerBlock(25,25);
dim3 numBlocks(resX/threadPerBlock.x,resY/threadPerBlock.y);
size_t pitch;
//data = (int*)malloc( sizeof(int)*resX*resY );
hipHostAlloc(&data, sizeof(int) * resX*resY, hipHostMallocMapped);
hipMallocPitch((void **)&d_data, &pitch, sizeof(int)*resX, resY);
// cudaMalloc((void**)&d_data, sizeof(int)*resX*resY );
mandelKernel<<<numBlocks,threadPerBlock>>>(d_data,stepX,stepY,lowerX,lowerY,resX,maxIterations,pitch);
hipMemcpy2D(data, sizeof(int)*resX, d_data, pitch, sizeof(int)*resX, resY, hipMemcpyDeviceToHost);
memcpy(img,data,sizeof(int)*resX*resY);
hipHostFree(data);
hipFree(d_data);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelPiffffiim
.globl _Z12mandelKernelPiffffiim
.p2align 8
.type _Z12mandelKernelPiffffiim,@function
_Z12mandelKernelPiffffiim:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, s4, s6
v_fma_f32 v3, v3, s5, s7
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v6
s_or_b32 s5, s5, exec_lo
v_fma_f32 v4, v5, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v4
v_mov_b32_e32 v4, s4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_mul_f32_e32 v4, v5, v5
v_add_f32_e32 v6, v6, v6
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, s4
v_sub_f32_e32 v7, v7, v4
s_cselect_b32 s7, -1, 0
v_mov_b32_e32 v4, s2
v_fma_f32 v5, v5, v6, v3
s_and_not1_b32 s5, s5, exec_lo
v_add_f32_e32 v6, v2, v7
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v4, 0
.LBB0_7:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s0, s[2:3]
v_mul_lo_u32 v6, v1, s1
v_mul_lo_u32 v5, v5, s0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add3_u32 v3, v5, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelPiffffiim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelPiffffiim, .Lfunc_end0-_Z12mandelKernelPiffffiim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelPiffffiim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelPiffffiim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
/*
__global__ static inline int mandel(float c_re, float c_im, int count)
{
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < count; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
return i;
}
*/
__global__ void mandelKernel( int* d_data,float stepX, float stepY,float lowerX,float lowerY ,int width, int maxIterations, size_t pitch) {
// To avoid error caused by the floating number, use the following pseudo code
//
int thisX= blockIdx.x * blockDim.x + threadIdx.x;
int thisY= blockIdx.y * blockDim.y + threadIdx.y;
float x = lowerX + thisX * stepX;
float y = lowerY + thisY * stepY;
float c_re = x, c_im = y;
float z_re = c_re, z_im = c_im;
int i;
for (i = 0; i < maxIterations; ++i)
{
if (z_re * z_re + z_im * z_im > 4.f)
break;
float new_re = z_re * z_re - z_im * z_im;
float new_im = 2.f * z_re * z_im;
z_re = c_re + new_re;
z_im = c_im + new_im;
}
int *ptr = (int *)((char*)d_data+thisY*pitch);
ptr[thisX] = i;
//d_data[ thisX + thisY * width ] = i;
}
// Host front-end function that allocates the memory and launches the GPU kernel
void hostFE (float upperX, float upperY, float lowerX, float lowerY, int* img, int resX, int resY, int maxIterations)
{
float stepX = (upperX - lowerX) / resX;
float stepY = (upperY - lowerY) / resY;
int *data, *d_data;
dim3 threadPerBlock(25,25);
dim3 numBlocks(resX/threadPerBlock.x,resY/threadPerBlock.y);
size_t pitch;
//data = (int*)malloc( sizeof(int)*resX*resY );
hipHostAlloc(&data, sizeof(int) * resX*resY, hipHostMallocMapped);
hipMallocPitch((void **)&d_data, &pitch, sizeof(int)*resX, resY);
// cudaMalloc((void**)&d_data, sizeof(int)*resX*resY );
mandelKernel<<<numBlocks,threadPerBlock>>>(d_data,stepX,stepY,lowerX,lowerY,resX,maxIterations,pitch);
hipMemcpy2D(data, sizeof(int)*resX, d_data, pitch, sizeof(int)*resX, resY, hipMemcpyDeviceToHost);
memcpy(img,data,sizeof(int)*resX*resY);
hipHostFree(data);
hipFree(d_data);
} | .text
.file "kernel2.hip"
.globl _Z27__device_stub__mandelKernelPiffffiim # -- Begin function _Z27__device_stub__mandelKernelPiffffiim
.p2align 4, 0x90
.type _Z27__device_stub__mandelKernelPiffffiim,@function
_Z27__device_stub__mandelKernelPiffffiim: # @_Z27__device_stub__mandelKernelPiffffiim
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mandelKernelPiffffiim, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelPiffffiim, .Lfunc_end0-_Z27__device_stub__mandelKernelPiffffiim
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, 28(%rsp) # 4-byte Spill
movl %edx, %ebx
movl %esi, %r13d
movq %rdi, 72(%rsp) # 8-byte Spill
movss %xmm3, 24(%rsp) # 4-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %esi, %eax
imulq $1374389535, %rax, %rax # imm = 0x51EB851F
shrq $35, %rax
movl %edx, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $3, %rcx
movabsq $1152921500311879680, %rbp # imm = 0xFFFFFFF00000000
andq %rcx, %rbp
orq %rax, %rbp
movslq %esi, %r15
shlq $2, %r15
movslq %edx, %r12
movq %r15, %r14
imulq %r12, %r14
leaq 64(%rsp), %rdi
movq %r14, %rsi
movl $2, %edx
callq hipHostAlloc
movq %rsp, %rdi
leaq 56(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq hipMallocPitch
movabsq $107374182425, %rdx # imm = 0x1900000019
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movss 24(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
subss %xmm1, %xmm3
cvtsi2ss %ebx, %xmm0
divss %xmm0, %xmm3
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
movss 20(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
subss %xmm2, %xmm4
divss %xmm0, %xmm4
movq (%rsp), %rax
movq 56(%rsp), %rcx
movq %rax, 136(%rsp)
movss %xmm4, 52(%rsp)
movss %xmm3, 48(%rsp)
movss %xmm2, 44(%rsp)
movss %xmm1, 40(%rsp)
movl %r13d, 36(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 32(%rsp)
movq %rcx, 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 128(%rsp), %rax
movq %rax, 200(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z12mandelKernelPiffffiim, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 64(%rsp), %rdi
movq (%rsp), %rdx
movq 56(%rsp), %rcx
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %r15, %rsi
movq %r15, %r8
movq %r12, %r9
pushq $2
.cfi_adjust_cfa_offset 8
callq hipMemcpy2D
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movq 64(%rsp), %rbx
movq 72(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %rbx, %rdi
callq hipHostFree
movq (%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelPiffffiim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelPiffffiim,@object # @_Z12mandelKernelPiffffiim
.section .rodata,"a",@progbits
.globl _Z12mandelKernelPiffffiim
.p2align 3, 0x0
_Z12mandelKernelPiffffiim:
.quad _Z27__device_stub__mandelKernelPiffffiim
.size _Z12mandelKernelPiffffiim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mandelKernelPiffffiim"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelPiffffiim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelPiffffiim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12mandelKernelPiffffiim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ MOV R7, c[0x0][0x168] ; /* 0x00005a0000077a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fc800078e0200 */
/*0080*/ I2F R2, R5 ; /* 0x0000000500027306 */
/* 0x000e220000201400 */
/*0090*/ IMAD R0, R3, c[0x0][0x4], R4 ; /* 0x0000010003007a24 */
/* 0x002fe200078e0204 */
/*00a0*/ MOV R4, c[0x0][0x17c] ; /* 0x00005f0000047a02 */
/* 0x000fcc0000000f00 */
/*00b0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*00c0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f06270 */
/*00d0*/ MOV R4, c[0x0][0x16c] ; /* 0x00005b0000047a02 */
/* 0x000fe20000000f00 */
/*00e0*/ FFMA R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027623 */
/* 0x001fe20000000007 */
/*00f0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fc600000001ff */
/*0100*/ FFMA R3, R3, R4, c[0x0][0x174] ; /* 0x00005d0003037623 */
/* 0x002fcc0000000004 */
/*0110*/ @!P0 BRA 0x230 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B0, 0x230 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0130*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R6, R2 ; /* 0x0000000200067202 */
/* 0x000fc60000000f00 */
/*0160*/ FMUL R9, R4, R4 ; /* 0x0000000404097220 */
/* 0x000fe40000400000 */
/*0170*/ FMUL R8, R6, R6 ; /* 0x0000000606087220 */
/* 0x000fc80000400000 */
/*0180*/ FADD R10, R9, R8 ; /* 0x00000008090a7221 */
/* 0x000fca0000000000 */
/*0190*/ FSETP.GT.AND P0, PT, R10, 4, PT ; /* 0x408000000a00780b */
/* 0x000fda0003f04000 */
/*01a0*/ @P0 BRA 0x220 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*01b0*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*01c0*/ FADD R6, R6, R6 ; /* 0x0000000606067221 */
/* 0x000fe40000000000 */
/*01d0*/ FADD R9, -R9, R8 ; /* 0x0000000809097221 */
/* 0x000fe20000000100 */
/*01e0*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x17c], PT ; /* 0x00005f0007007a0c */
/* 0x000fe20003f06270 */
/*01f0*/ FFMA R4, R6, R4, R3 ; /* 0x0000000406047223 */
/* 0x000fe40000000003 */
/*0200*/ FADD R6, R2, R9 ; /* 0x0000000902067221 */
/* 0x000fd40000000000 */
/*0210*/ @!P0 BRA 0x160 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fe40000011400 */
/*0240*/ MOV R3, c[0x0][0x180] ; /* 0x0000600000037a02 */
/* 0x000fc60000000f00 */
/*0250*/ IMAD R9, R2, c[0x0][0x180], RZ ; /* 0x0000600002097a24 */
/* 0x000fe400078e02ff */
/*0260*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*0270*/ IMAD R9, R0, c[0x0][0x184], R9 ; /* 0x0000610000097a24 */
/* 0x000fca00078e0209 */
/*0280*/ IADD3 R3, R3, R9, RZ ; /* 0x0000000903037210 */
/* 0x000fca0007ffe0ff */
/*0290*/ IMAD.WIDE R2, R5, 0x4, R2 ; /* 0x0000000405027825 */
/* 0x000fca00078e0202 */
/*02a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mandelKernelPiffffiim
.globl _Z12mandelKernelPiffffiim
.p2align 8
.type _Z12mandelKernelPiffffiim,@function
_Z12mandelKernelPiffffiim:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x34
s_load_b32 s2, s[0:1], 0x1c
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v2, v0
v_cvt_f32_i32_e32 v3, v1
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v2, v2, s4, s6
v_fma_f32 v3, v3, s5, s7
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v5, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s6, exec_lo, s5
s_or_b32 s3, s6, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_5
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v6
s_or_b32 s5, s5, exec_lo
v_fma_f32 v4, v5, v5, v7
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nlt_f32_e32 vcc_lo, 4.0, v4
v_mov_b32_e32 v4, s4
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
v_mul_f32_e32 v4, v5, v5
v_add_f32_e32 v6, v6, v6
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, s4
v_sub_f32_e32 v7, v7, v4
s_cselect_b32 s7, -1, 0
v_mov_b32_e32 v4, s2
v_fma_f32 v5, v5, v6, v3
s_and_not1_b32 s5, s5, exec_lo
v_add_f32_e32 v6, v2, v7
s_and_b32 s7, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s5, s5, s7
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v4, 0
.LBB0_7:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v1
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[2:3], null, v1, s0, s[2:3]
v_mul_lo_u32 v6, v1, s1
v_mul_lo_u32 v5, v5, s0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add3_u32 v3, v5, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
global_store_b32 v[0:1], v4, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mandelKernelPiffffiim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mandelKernelPiffffiim, .Lfunc_end0-_Z12mandelKernelPiffffiim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mandelKernelPiffffiim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mandelKernelPiffffiim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00047da1_00000000-6_kernel2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim
.type _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim, @function
_Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movss %xmm3, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 28(%rsp), %rax
movq %rax, 136(%rsp)
leaq 24(%rsp), %rax
movq %rax, 144(%rsp)
leaq 20(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z12mandelKernelPiffffiim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim, .-_Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim
.globl _Z12mandelKernelPiffffiim
.type _Z12mandelKernelPiffffiim, @function
_Z12mandelKernelPiffffiim:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mandelKernelPiffffiim, .-_Z12mandelKernelPiffffiim
.globl _Z6hostFEffffPiiii
.type _Z6hostFEffffPiiii, @function
_Z6hostFEffffPiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 24(%rsp)
movq %rdi, %r14
movl %esi, %ebp
movl %edx, %r12d
movl %ecx, 28(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 72(%rsp)
movl %esi, %eax
imulq $1374389535, %rax, %rax
shrq $35, %rax
movl %eax, 76(%rsp)
movl %edx, %eax
imulq $1374389535, %rax, %rax
shrq $35, %rax
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
movslq %esi, %rbx
movslq %edx, %r15
movq %rbx, %r13
imulq %r15, %r13
salq $2, %r13
leaq 40(%rsp), %rdi
movl $2, %edx
movq %r13, %rsi
call cudaHostAlloc@PLT
salq $2, %rbx
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdi
movq %r15, %rcx
movq %rbx, %rdx
call cudaMallocPitch@PLT
movl $25, 64(%rsp)
movl $25, 68(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq $2
.cfi_def_cfa_offset 176
movq %r15, %r9
movq %rbx, %r8
movq 72(%rsp), %rcx
movq 64(%rsp), %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy2D@PLT
movq 56(%rsp), %rbx
movq %r13, %rdx
movq %rbx, %rsi
movq %r14, %rdi
call memcpy@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movq %rbx, %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movss 16(%rsp), %xmm1
movss 24(%rsp), %xmm3
subss %xmm3, %xmm1
pxor %xmm4, %xmm4
cvtsi2ssl %r12d, %xmm4
movss 12(%rsp), %xmm0
movss 20(%rsp), %xmm5
subss %xmm5, %xmm0
pxor %xmm2, %xmm2
cvtsi2ssl %ebp, %xmm2
divss %xmm2, %xmm0
movq 56(%rsp), %rcx
movl 28(%rsp), %edx
movl %ebp, %esi
movaps %xmm5, %xmm2
divss %xmm4, %xmm1
movq 48(%rsp), %rdi
call _Z39__device_stub__Z12mandelKernelPiffffiimPiffffiim
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z6hostFEffffPiiii, .-_Z6hostFEffffPiiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mandelKernelPiffffiim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mandelKernelPiffffiim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel2.hip"
.globl _Z27__device_stub__mandelKernelPiffffiim # -- Begin function _Z27__device_stub__mandelKernelPiffffiim
.p2align 4, 0x90
.type _Z27__device_stub__mandelKernelPiffffiim,@function
_Z27__device_stub__mandelKernelPiffffiim: # @_Z27__device_stub__mandelKernelPiffffiim
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movss %xmm0, 28(%rsp)
movss %xmm1, 24(%rsp)
movss %xmm2, 20(%rsp)
movss %xmm3, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12mandelKernelPiffffiim, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z27__device_stub__mandelKernelPiffffiim, .Lfunc_end0-_Z27__device_stub__mandelKernelPiffffiim
.cfi_endproc
# -- End function
.globl _Z6hostFEffffPiiii # -- Begin function _Z6hostFEffffPiiii
.p2align 4, 0x90
.type _Z6hostFEffffPiiii,@function
_Z6hostFEffffPiiii: # @_Z6hostFEffffPiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, 28(%rsp) # 4-byte Spill
movl %edx, %ebx
movl %esi, %r13d
movq %rdi, 72(%rsp) # 8-byte Spill
movss %xmm3, 24(%rsp) # 4-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm0, 12(%rsp) # 4-byte Spill
movl %esi, %eax
imulq $1374389535, %rax, %rax # imm = 0x51EB851F
shrq $35, %rax
movl %edx, %ecx
imulq $1374389535, %rcx, %rcx # imm = 0x51EB851F
shrq $3, %rcx
movabsq $1152921500311879680, %rbp # imm = 0xFFFFFFF00000000
andq %rcx, %rbp
orq %rax, %rbp
movslq %esi, %r15
shlq $2, %r15
movslq %edx, %r12
movq %r15, %r14
imulq %r12, %r14
leaq 64(%rsp), %rdi
movq %r14, %rsi
movl $2, %edx
callq hipHostAlloc
movq %rsp, %rdi
leaq 56(%rsp), %rsi
movq %r15, %rdx
movq %r12, %rcx
callq hipMallocPitch
movabsq $107374182425, %rdx # imm = 0x1900000019
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movss 24(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movss 16(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
subss %xmm1, %xmm3
cvtsi2ss %ebx, %xmm0
divss %xmm0, %xmm3
xorps %xmm0, %xmm0
cvtsi2ss %r13d, %xmm0
movss 20(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movss 12(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
subss %xmm2, %xmm4
divss %xmm0, %xmm4
movq (%rsp), %rax
movq 56(%rsp), %rcx
movq %rax, 136(%rsp)
movss %xmm4, 52(%rsp)
movss %xmm3, 48(%rsp)
movss %xmm2, 44(%rsp)
movss %xmm1, 40(%rsp)
movl %r13d, 36(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 32(%rsp)
movq %rcx, 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 52(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rax
movq %rax, 160(%rsp)
leaq 44(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 36(%rsp), %rax
movq %rax, 184(%rsp)
leaq 32(%rsp), %rax
movq %rax, 192(%rsp)
leaq 128(%rsp), %rax
movq %rax, 200(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z12mandelKernelPiffffiim, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 64(%rsp), %rdi
movq (%rsp), %rdx
movq 56(%rsp), %rcx
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movq %r15, %rsi
movq %r15, %r8
movq %r12, %r9
pushq $2
.cfi_adjust_cfa_offset 8
callq hipMemcpy2D
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movq 64(%rsp), %rbx
movq 72(%rsp), %rdi # 8-byte Reload
movq %rbx, %rsi
movq %r14, %rdx
callq memcpy@PLT
movq %rbx, %rdi
callq hipHostFree
movq (%rsp), %rdi
callq hipFree
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6hostFEffffPiiii, .Lfunc_end1-_Z6hostFEffffPiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mandelKernelPiffffiim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mandelKernelPiffffiim,@object # @_Z12mandelKernelPiffffiim
.section .rodata,"a",@progbits
.globl _Z12mandelKernelPiffffiim
.p2align 3, 0x0
_Z12mandelKernelPiffffiim:
.quad _Z27__device_stub__mandelKernelPiffffiim
.size _Z12mandelKernelPiffffiim, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mandelKernelPiffffiim"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mandelKernelPiffffiim
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mandelKernelPiffffiim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<iostream>
#include<cuda.h>
int main(int argc, char* argv[]){
if(argc!=3){
std::cout<<"Usage: "<<argv[0]<<" Numblocks BlockDim\n";
return 0;
}
int nBlocks= atoi(argv[1]);
int bDim = atoi(argv[2]);
if(bDim>1024){
std::cout<<"BlockDim should be less than or equal to 1024\n";
return 0;
}
std::cout<<"Lets do this!!!\n";
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<iostream>
#include<cuda.h>
int main(int argc, char* argv[]){
if(argc!=3){
std::cout<<"Usage: "<<argv[0]<<" Numblocks BlockDim\n";
return 0;
}
int nBlocks= atoi(argv[1]);
int bDim = atoi(argv[2]);
if(bDim>1024){
std::cout<<"BlockDim should be less than or equal to 1024\n";
return 0;
}
std::cout<<"Lets do this!!!\n";
} | .file "tmpxft_0007504c_00000000-6_example1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: "
.LC1:
.string " Numblocks BlockDim\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "BlockDim should be less than or equal to 1024\n"
.section .rodata.str1.1
.LC3:
.string "Lets do this!!!\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rsi, %rbx
cmpl $3, %edi
je .L4
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rbx), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.L5:
movl $0, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L4:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cmpl $1024, %eax
jg .L8
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L5
.L8:
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L5
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<iostream>
#include<cuda.h>
int main(int argc, char* argv[]){
if(argc!=3){
std::cout<<"Usage: "<<argv[0]<<" Numblocks BlockDim\n";
return 0;
}
int nBlocks= atoi(argv[1]);
int bDim = atoi(argv[2]);
if(bDim>1024){
std::cout<<"BlockDim should be less than or equal to 1024\n";
return 0;
}
std::cout<<"Lets do this!!!\n";
} | #include<stdio.h>
#include<iostream>
#include<hip/hip_runtime.h>
int main(int argc, char* argv[]){
if(argc!=3){
std::cout<<"Usage: "<<argv[0]<<" Numblocks BlockDim\n";
return 0;
}
int nBlocks= atoi(argv[1]);
int bDim = atoi(argv[2]);
if(bDim>1024){
std::cout<<"BlockDim should be less than or equal to 1024\n";
return 0;
}
std::cout<<"Lets do this!!!\n";
} |
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