system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include "functions.cuh"
__global__
void KernelAdd(int n, float * p_sum, float * x, float * y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n )
p_sum[i] = x[i] + y[i];
}
void DeviceKernel(int numBlocks, int sizeBlock, int n, float * p_sum, float * x, float * y){
KernelAdd <<<numBlocks, sizeBlock>>> (n, p_sum, x, y); // vector addition on DEVICE simple
} | .file "tmpxft_0002a57a_00000000-6_functions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_
.type _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_, @function
_Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9KernelAddiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_, .-_Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_
.globl _Z9KernelAddiPfS_S_
.type _Z9KernelAddiPfS_S_, @function
_Z9KernelAddiPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9KernelAddiPfS_S_, .-_Z9KernelAddiPfS_S_
.globl _Z12DeviceKerneliiiPfS_S_
.type _Z12DeviceKerneliiiPfS_S_, @function
_Z12DeviceKerneliiiPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edx, %ebx
movq %rcx, %rbp
movq %r8, %r12
movq %r9, %r13
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z12DeviceKerneliiiPfS_S_, .-_Z12DeviceKerneliiiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9KernelAddiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9KernelAddiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include "functions.cuh"
__global__
void KernelAdd(int n, float * p_sum, float * x, float * y){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if ( i < n )
p_sum[i] = x[i] + y[i];
}
void DeviceKernel(int numBlocks, int sizeBlock, int n, float * p_sum, float * x, float * y){
KernelAdd <<<numBlocks, sizeBlock>>> (n, p_sum, x, y); // vector addition on DEVICE simple
} | #ifndef FUNCTIONS_CUH
#define FUNCTIONS_CUH
void DeviceKernel(int numBlocks, int sizeBlock, int n, float * p_sum, float * x, float * y);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef FUNCTIONS_CUH
#define FUNCTIONS_CUH
void DeviceKernel(int numBlocks, int sizeBlock, int n, float * p_sum, float * x, float * y);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef FUNCTIONS_CUH
#define FUNCTIONS_CUH
void DeviceKernel(int numBlocks, int sizeBlock, int n, float * p_sum, float * x, float * y);
#endif | .text
.file "functions.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9KernelAddiPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x178] ; /* 0x00005e0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002a57a_00000000-6_functions.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_
.type _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_, @function
_Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9KernelAddiPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_, .-_Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_
.globl _Z9KernelAddiPfS_S_
.type _Z9KernelAddiPfS_S_, @function
_Z9KernelAddiPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9KernelAddiPfS_S_, .-_Z9KernelAddiPfS_S_
.globl _Z12DeviceKerneliiiPfS_S_
.type _Z12DeviceKerneliiiPfS_S_, @function
_Z12DeviceKerneliiiPfS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl %edx, %ebx
movq %rcx, %rbp
movq %r8, %r12
movq %r9, %r13
movl %esi, 20(%rsp)
movl $1, 24(%rsp)
movl %edi, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq %r13, %rcx
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call _Z33__device_stub__Z9KernelAddiPfS_S_iPfS_S_
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z12DeviceKerneliiiPfS_S_, .-_Z12DeviceKerneliiiPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9KernelAddiPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9KernelAddiPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "functions.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //****************************************************************************
// Also note that we've supplied a helpful debugging function called checkCudaErrors.
// You should wrap your allocation and copying statements like we've done in the
// code we're supplying you. Here is an example of the unsafe way to allocate
// memory on the GPU:
//
// cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols);
//
// Here is an example of the safe way to do the same thing:
//
// checkCudaErrors(cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols));
//****************************************************************************
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <iostream>
#include <iomanip>
#include <algorithm> // std::max
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
typedef unsigned char uchar;
#define FILTER_WIDTH 3
#define NTHREADS 32
#define checkCudaErrors(val) check( (val), #val, __FILE__, __LINE__)
template<typename T>
void check(T err, const char* const func, const char* const file, const int line) {
if (err != cudaSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << cudaGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
__constant__ float filtro[FILTER_WIDTH * FILTER_WIDTH];
__global__ void box_filter(const unsigned char* const inputChannel, unsigned char* const outputChannel,
int numRows, int numCols, const float* __restrict__ filter, const int filterWidth)
{
// Aplicar el filtro a cada pixel de la imagen...
// NOTA: Que un thread tenga una posición correcta en 2D no quiere decir que al aplicar el filtro
// los valores de sus vecinos sean correctos, ya que pueden salirse de la imagen.
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
float c = 0.0f;
for (int fx = 0; fx < filterWidth; ++fx) {
for (int fy = 0; fy < filterWidth; ++fy) {
int imagex = idx + fx - filterWidth / 2;
int imagey = idy + fy - filterWidth / 2;
imagex = min(max(imagex, 0), numCols - 1); // Limit image on borders...
imagey = min(max(imagey, 0), numRows - 1); // Limit image on borders...
c += (filter[fy * filterWidth + fx] * inputChannel[imagey * numCols + imagex]);
}
}
outputChannel[idy * numCols + idx] = c;
}
// This kernel takes in an image represented as a uchar4 and splits
// it into three images consisting of only one color channel each
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
int id = idy * numCols + idx;
redChannel[id] = inputImageRGBA[id].x;
greenChannel[id] = inputImageRGBA[id].y;
blueChannel[id] = inputImageRGBA[id].z;
}
// This kernel takes in three color channels and recombines them
// into one image. The alpha channel is set to 255 to represent
// that this image has no transparency.
__global__ void recombineChannels(const unsigned char* const redChannel,
const unsigned char* const greenChannel,
const unsigned char* const blueChannel,
uchar4* const outputImageRGBA,
int numRows,
int numCols)
{
const int2 thread_2D_pos = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
const int thread_1D_pos = thread_2D_pos.y * numCols + thread_2D_pos.x;
// make sure we don't try and access memory outside the image
//by having any threads mapped there return early...
if (thread_2D_pos.x >= numCols || thread_2D_pos.y >= numRows) return;
unsigned char red = redChannel[thread_1D_pos];
unsigned char green = greenChannel[thread_1D_pos];
unsigned char blue = blueChannel[thread_1D_pos];
// Alpha should be 255 for no transparency
uchar4 outputPixel = make_uchar4(red, green, blue, 255);
outputImageRGBA[thread_1D_pos] = outputPixel;
}
unsigned char *d_red, *d_green, *d_blue;
float *d_filter;
void allocateMemoryAndCopyToGPU(const size_t numRowsImage, const size_t numColsImage, const float* const h_filter, const size_t filterWidth)
{
int sizeImg = sizeof(uchar4) * numRowsImage * numColsImage;
int sizeFilter = sizeof(uchar4) * filterWidth * filterWidth;
cudaMalloc(&d_red, sizeImg);
cudaMalloc(&d_green, sizeImg);
cudaMalloc(&d_blue, sizeImg);
cudaMalloc(&d_filter, sizeFilter);
cudaMemcpy(d_filter, h_filter, sizeFilter, cudaMemcpyHostToDevice);
cudaMemset(d_red, 0, sizeImg);
cudaMemset(d_green, 0, sizeImg);
cudaMemset(d_blue, 0, sizeImg);
}
// Crear el filtro se que va a aplicar (en CPU) y almacenar su tamaño...
void create_filter(float **d_filter, const float *mask, const int size)
{
float *h_filter = (float *) malloc(sizeof(float) * size);
if (!h_filter) {
std::cerr << "Error creating filter.." << strerror(errno) << '\n';
exit(1);
}
for (int i = 0; i < size; ++i) {
h_filter[i] = mask[i];
}
cudaMalloc(d_filter, sizeof(float) * size);
cudaMemcpy(*d_filter, h_filter, sizeof(float) * size, cudaMemcpyHostToDevice);
}
void open_mpi_separate_channels(uchar4* const d_inputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_red,
unsigned char *d_green,
unsigned char *d_blue)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void open_mpi_box_filter(const unsigned char *channel,
unsigned char *filter_channel,
const size_t numRows,
const size_t numCols,
float* d_filter,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
box_filter<<<gridSize, blockSize>>>(channel, filter_channel, numRows, numCols, d_filter, filterWidth);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void open_mpi_recombine_channels(const unsigned char* d_redFiltered,
const unsigned char* d_greenFiltered,
const unsigned char* d_blueFiltered,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void convolution(uchar4* const d_inputImageRGBA,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_redFiltered,
unsigned char *d_greenFiltered,
unsigned char *d_blueFiltered,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
// Call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
box_filter<<<gridSize, blockSize>>>(d_red, d_redFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_blue, d_blueFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_green, d_greenFiltered, numRows, numCols, d_filter, filterWidth);
// Again, call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
//Free all the memory that we allocated
// TODO: make sure you free any arrays that you allocated
void cleanup() {
checkCudaErrors(cudaFree(d_red));
checkCudaErrors(cudaFree(d_green));
checkCudaErrors(cudaFree(d_blue));
checkCudaErrors(cudaFree(d_filter));
} | code for sm_80
Function : _Z17recombineChannelsPKhS0_S0_P6uchar4ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3.reuse, c[0x0][0x180], P0 ; /* 0x0000600003007a0c */
/* 0x040fe20000706670 */
/*0090*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fd800078e0200 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fe20000011403 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ IADD3 R8, P0, R3.reuse, c[0x0][0x160], RZ ; /* 0x0000580003087a10 */
/* 0x040fe40007f1e0ff */
/*00e0*/ IADD3 R6, P1, R3.reuse, c[0x0][0x168], RZ ; /* 0x00005a0003067a10 */
/* 0x040fe40007f3e0ff */
/*00f0*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000097a10 */
/* 0x040fe400007fe4ff */
/*0100*/ IADD3 R4, P2, R3, c[0x0][0x170], RZ ; /* 0x00005c0003047a10 */
/* 0x000fe40007f5e0ff */
/*0110*/ IADD3.X R7, R0, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000077a10 */
/* 0x000fc40000ffe4ff */
/*0120*/ IADD3.X R5, R0, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d0000057a10 */
/* 0x000fe200017fe4ff */
/*0130*/ LDG.E.U8 R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1100 */
/*0140*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1100 */
/*0150*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1100 */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, 0xff ; /* 0x000000ffff007424 */
/* 0x000fc400078e00ff */
/*0170*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*0180*/ IMAD.WIDE R2, R3, R2, c[0x0][0x178] ; /* 0x00005e0003027625 */
/* 0x000fe200078e0202 */
/*0190*/ PRMT R11, R6, 0x7604, R9 ; /* 0x00007604060b7816 */
/* 0x004fc80000000009 */
/*01a0*/ PRMT R11, R4, 0x7054, R11 ; /* 0x00007054040b7816 */
/* 0x008fc8000000000b */
/*01b0*/ PRMT R11, R0, 0x654, R11 ; /* 0x00000654000b7816 */
/* 0x000fca000000000b */
/*01c0*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16separateChannelsPK6uchar4iiPhS2_S2_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x4], R5 ; /* 0x0000010002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x168], P0 ; /* 0x00005a0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003007a24 */
/* 0x000fc800078e0200 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0205 */
/*00e0*/ LDG.E.U8 R11, [R2.64] ; /* 0x00000004020b7981 */
/* 0x000ea2000c1e1100 */
/*00f0*/ SHF.R.S32.HI R9, RZ, 0x1f, R0 ; /* 0x0000001fff097819 */
/* 0x000fe40000011400 */
/*0100*/ IADD3 R4, P0, R0, c[0x0][0x170], RZ ; /* 0x00005c0000047a10 */
/* 0x000fc80007f1e0ff */
/*0110*/ IADD3.X R5, R9, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0009057a10 */
/* 0x000fca00007fe4ff */
/*0120*/ STG.E.U8 [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x004fe8000c101104 */
/*0130*/ LDG.E.U8 R13, [R2.64+0x1] ; /* 0x00000104020d7981 */
/* 0x000ea2000c1e1100 */
/*0140*/ IADD3 R6, P0, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a10 */
/* 0x000fc80007f1e0ff */
/*0150*/ IADD3.X R7, R9, c[0x0][0x17c], RZ, P0, !PT ; /* 0x00005f0009077a10 */
/* 0x000fe400007fe4ff */
/*0160*/ IADD3 R8, P0, R0, c[0x0][0x180], RZ ; /* 0x0000600000087a10 */
/* 0x000fc60007f1e0ff */
/*0170*/ STG.E.U8 [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x004fe8000c101104 */
/*0180*/ LDG.E.U8 R15, [R2.64+0x2] ; /* 0x00000204020f7981 */
/* 0x000ea2000c1e1100 */
/*0190*/ IADD3.X R9, R9, c[0x0][0x184], RZ, P0, !PT ; /* 0x0000610009097a10 */
/* 0x000fca00007fe4ff */
/*01a0*/ STG.E.U8 [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x004fe2000c101104 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10box_filterPKhPhiiPKfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R4, SR_CTAID.Y ; /* 0x0000000000047919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R19, R4, c[0x0][0x4], R5 ; /* 0x0000010004137a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x170], P0 ; /* 0x00005c0013007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R21, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff157624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fc600078e00ff */
/*00d0*/ ISETP.GE.AND P0, PT, R21, 0x1, PT ; /* 0x000000011500780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x8a0 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*00f0*/ LEA.HI R2, R21.reuse, c[0x0][0x180], RZ, 0x1 ; /* 0x0000600015027a11 */
/* 0x040fe200078f08ff */
/*0100*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe20000000000 */
/*0110*/ IADD3 R6, R21.reuse, -0x1, RZ ; /* 0xffffffff15067810 */
/* 0x040fe20007ffe0ff */
/*0120*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ SHF.R.S32.HI R2, RZ, 0x1, R2 ; /* 0x00000001ff027819 */
/* 0x000fe20000011402 */
/*0140*/ IMAD.MOV.U32 R27, RZ, RZ, RZ ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e00ff */
/*0150*/ LOP3.LUT R28, R21.reuse, 0x3, RZ, 0xc0, !PT ; /* 0x00000003151c7812 */
/* 0x040fe200078ec0ff */
/*0160*/ IMAD.SHL.U32 R21, R21, 0x4, RZ ; /* 0x0000000415157824 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GE.U32.AND P0, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f06070 */
/*0180*/ IMAD.IADD R3, R5, 0x1, -R2.reuse ; /* 0x0000000105037824 */
/* 0x100fe200078e0a02 */
/*0190*/ IADD3 R20, R28, -c[0x0][0x180], RZ ; /* 0x800060001c147a10 */
/* 0x000fe20007ffe0ff */
/*01a0*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe200078e00ff */
/*01b0*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe2000fffe13f */
/*01c0*/ IMAD R3, R4, c[0x0][0x4], R3 ; /* 0x0000010004037a24 */
/* 0x000fe200078e0203 */
/*01d0*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fe2000fffe13f */
/*01e0*/ IMAD.IADD R23, R0, 0x1, -R2 ; /* 0x0000000100177824 */
/* 0x000fc400078e0a02 */
/*01f0*/ IMAD.IADD R22, R19, 0x1, -R2 ; /* 0x0000000113167824 */
/* 0x000fe200078e0a02 */
/*0200*/ IADD3 R24, R3, 0x3, RZ ; /* 0x0000000303187810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IMAD.IADD R2, R23, 0x1, R18 ; /* 0x0000000117027824 */
/* 0x000fe200078e0212 */
/*0220*/ ISETP.NE.AND P1, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe20003f25270 */
/*0230*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fc600078e00ff */
/*0240*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fc80007800200 */
/*0250*/ IMNMX R25, R2, UR4, PT ; /* 0x0000000402197c17 */
/* 0x000fe2000b800200 */
/*0260*/ @!P0 BRA 0x5e0 ; /* 0x0000037000008947 */
/* 0x000fea0003800000 */
/*0270*/ IADD3 R2, R18, c[0x0][0x180], RZ ; /* 0x0000600012027a10 */
/* 0x000fe20007ffe0ff */
/*0280*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0290*/ IMAD.MOV.U32 R29, RZ, RZ, RZ ; /* 0x000000ffff1d7224 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x178] ; /* 0x00005e0002027625 */
/* 0x000fc800078e0205 */
/*02b0*/ IMAD.MOV.U32 R26, RZ, RZ, R24 ; /* 0x000000ffff1a7224 */
/* 0x000fe400078e0018 */
/*02c0*/ IMAD.WIDE R4, R18, R5, c[0x0][0x178] ; /* 0x00005e0012047625 */
/* 0x000fc800078e0205 */
/*02d0*/ IADD3 R6, R26.reuse, -0x3, RZ ; /* 0xfffffffd1a067810 */
/* 0x040fe40007ffe0ff */
/*02e0*/ IADD3 R7, R26.reuse, -0x2, RZ ; /* 0xfffffffe1a077810 */
/* 0x040fe40007ffe0ff */
/*02f0*/ IMNMX R6, RZ, R6, !PT ; /* 0x00000006ff067217 */
/* 0x000fe40007800200 */
/*0300*/ IADD3 R8, R26, -0x1, RZ ; /* 0xffffffff1a087810 */
/* 0x000fe40007ffe0ff */
/*0310*/ IMNMX R7, RZ, R7, !PT ; /* 0x00000007ff077217 */
/* 0x000fc40007800200 */
/*0320*/ IMNMX R6, R6, UR5, PT ; /* 0x0000000506067c17 */
/* 0x000fe4000b800200 */
/*0330*/ IMNMX R9, RZ, R8, !PT ; /* 0x00000008ff097217 */
/* 0x000fe40007800200 */
/*0340*/ IMNMX R10, R7, UR5, PT ; /* 0x00000005070a7c17 */
/* 0x000fe2000b800200 */
/*0350*/ IMAD R8, R6, c[0x0][0x174], R25.reuse ; /* 0x00005d0006087a24 */
/* 0x100fe200078e0219 */
/*0360*/ IMNMX R11, RZ, R26, !PT ; /* 0x0000001aff0b7217 */
/* 0x000fe40007800200 */
/*0370*/ IMNMX R6, R9, UR5, PT ; /* 0x0000000509067c17 */
/* 0x000fe2000b800200 */
/*0380*/ IMAD R7, R10, c[0x0][0x174], R25 ; /* 0x00005d000a077a24 */
/* 0x000fe200078e0219 */
/*0390*/ IADD3 R12, P3, R8, c[0x0][0x160], RZ ; /* 0x00005800080c7a10 */
/* 0x000fc40007f7e0ff */
/*03a0*/ IMNMX R10, R11, UR5, PT ; /* 0x000000050b0a7c17 */
/* 0x000fe2000b800200 */
/*03b0*/ IMAD R9, R6, c[0x0][0x174], R25.reuse ; /* 0x00005d0006097a24 */
/* 0x100fe200078e0219 */
/*03c0*/ IADD3 R6, P2, R7, c[0x0][0x160], RZ ; /* 0x0000580007067a10 */
/* 0x000fe40007f5e0ff */
/*03d0*/ LEA.HI.X.SX32 R13, R8, c[0x0][0x164], 0x1, P3 ; /* 0x00005900080d7a11 */
/* 0x000fe200018f0eff */
/*03e0*/ IMAD R11, R10, c[0x0][0x174], R25 ; /* 0x00005d000a0b7a24 */
/* 0x000fe200078e0219 */
/*03f0*/ IADD3 R8, P3, R9, c[0x0][0x160], RZ ; /* 0x0000580009087a10 */
/* 0x000fe40007f7e0ff */
/*0400*/ LEA.HI.X.SX32 R7, R7, c[0x0][0x164], 0x1, P2 ; /* 0x0000590007077a11 */
/* 0x000fe200010f0eff */
/*0410*/ LDG.E.U8 R12, [R12.64] ; /* 0x000000080c0c7981 */
/* 0x0000a2000c1e1100 */
/*0420*/ IADD3 R10, P2, R11, c[0x0][0x160], RZ ; /* 0x000058000b0a7a10 */
/* 0x000fc40007f5e0ff */
/*0430*/ LEA.HI.X.SX32 R9, R9, c[0x0][0x164], 0x1, P3 ; /* 0x0000590009097a11 */
/* 0x000fe200018f0eff */
/*0440*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x0002e2000c1e1100 */
/*0450*/ LEA.HI.X.SX32 R11, R11, c[0x0][0x164], 0x1, P2 ; /* 0x000059000b0b7a11 */
/* 0x000fe200010f0eff */
/*0460*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff117624 */
/* 0x000fe400078e00ff */
/*0470*/ LDG.E.U8 R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000964000c1e1100 */
/*0480*/ IMAD.WIDE R14, R17.reuse, 0x4, R2 ; /* 0x00000004110e7825 */
/* 0x040fe400078e0202 */
/*0490*/ LDG.E.U8 R10, [R10.64] ; /* 0x000000080a0a7981 */
/* 0x000368000c1e1100 */
/*04a0*/ LDG.E.CONSTANT R13, [R4.64] ; /* 0x00000008040d7981 */
/* 0x001162000c1e9900 */
/*04b0*/ IMAD.WIDE R16, R17, 0x4, R14 ; /* 0x0000000411107825 */
/* 0x000fc600078e020e */
/*04c0*/ LDG.E.CONSTANT R9, [R2.64] ; /* 0x0000000802097981 */
/* 0x010968000c1e9900 */
/*04d0*/ LDG.E.CONSTANT R7, [R14.64] ; /* 0x000000080e077981 */
/* 0x002368000c1e9900 */
/*04e0*/ LDG.E.CONSTANT R16, [R16.64] ; /* 0x0000000810107981 */
/* 0x000f62000c1e9900 */
/*04f0*/ IADD3 R29, R29, 0x4, RZ ; /* 0x000000041d1d7810 */
/* 0x000fca0007ffe0ff */
/*0500*/ IMAD.IADD R11, R20, 0x1, R29 ; /* 0x00000001140b7824 */
/* 0x000fca00078e021d */
/*0510*/ ISETP.NE.AND P2, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe20003f45270 */
/*0520*/ IMAD.WIDE R4, R21, 0x4, R4 ; /* 0x0000000415047825 */
/* 0x001fe200078e0204 */
/*0530*/ IADD3 R26, R26, 0x4, RZ ; /* 0x000000041a1a7810 */
/* 0x000fc60007ffe0ff */
/*0540*/ IMAD.WIDE R2, R21, 0x4, R2 ; /* 0x0000000415027825 */
/* 0x010fe200078e0202 */
/*0550*/ I2F.U16 R12, R12 ; /* 0x0000000c000c7306 */
/* 0x004e300000101000 */
/*0560*/ I2F.U16 R6, R6 ; /* 0x0000000600067306 */
/* 0x008e700000101000 */
/*0570*/ I2F.U16 R8, R8 ; /* 0x0000000800087306 */
/* 0x020ea20000101000 */
/*0580*/ FFMA R13, R12, R13, R27 ; /* 0x0000000d0c0d7223 */
/* 0x001fce000000001b */
/*0590*/ I2F.U16 R10, R10 ; /* 0x0000000a000a7306 */
/* 0x000e220000101000 */
/*05a0*/ FFMA R14, R6, R9, R13 ; /* 0x00000009060e7223 */
/* 0x002fc8000000000d */
/*05b0*/ FFMA R7, R8, R7, R14 ; /* 0x0000000708077223 */
/* 0x004fc8000000000e */
/*05c0*/ FFMA R27, R10, R16, R7 ; /* 0x000000100a1b7223 */
/* 0x001fe20000000007 */
/*05d0*/ @P2 BRA 0x2d0 ; /* 0xfffffcf000002947 */
/* 0x000fea000383ffff */
/*05e0*/ @!P1 BRA 0x870 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*05f0*/ IMAD.IADD R5, R22, 0x1, R29 ; /* 0x0000000116057824 */
/* 0x000fca00078e021d */
/*0600*/ IMNMX R2, RZ, R5, !PT ; /* 0x00000005ff027217 */
/* 0x000fc80007800200 */
/*0610*/ IMNMX R2, R2, UR5, PT ; /* 0x0000000502027c17 */
/* 0x000fca000b800200 */
/*0620*/ IMAD R2, R2, c[0x0][0x174], R25 ; /* 0x00005d0002027a24 */
/* 0x000fca00078e0219 */
/*0630*/ IADD3 R6, P1, R2, c[0x0][0x160], RZ ; /* 0x0000580002067a10 */
/* 0x000fc80007f3e0ff */
/*0640*/ LEA.HI.X.SX32 R7, R2, c[0x0][0x164], 0x1, P1 ; /* 0x0000590002077a11 */
/* 0x000fca00008f0eff */
/*0650*/ LDG.E.U8 R6, [R6.64] ; /* 0x0000000806067981 */
/* 0x000ea2000c1e1100 */
/*0660*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe400078e00ff */
/*0670*/ IMAD R29, R29, c[0x0][0x180], R18 ; /* 0x000060001d1d7a24 */
/* 0x000fc800078e0212 */
/*0680*/ IMAD.WIDE R2, R29, R4, c[0x0][0x178] ; /* 0x00005e001d027625 */
/* 0x000fcc00078e0204 */
/*0690*/ LDG.E.CONSTANT R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ee2000c1e9900 */
/*06a0*/ ISETP.NE.AND P1, PT, R28, 0x1, PT ; /* 0x000000011c00780c */
/* 0x000fe20003f25270 */
/*06b0*/ I2F.U16 R8, R6 ; /* 0x0000000600087306 */
/* 0x004ee40000101000 */
/*06c0*/ FFMA R27, R8, R2, R27 ; /* 0x00000002081b7223 */
/* 0x008fd4000000001b */
/*06d0*/ @!P1 BRA 0x870 ; /* 0x0000019000009947 */
/* 0x000fea0003800000 */
/*06e0*/ ISETP.NE.AND P1, PT, R28, 0x2, PT ; /* 0x000000021c00780c */
/* 0x000fe40003f25270 */
/*06f0*/ IADD3 R2, R5, 0x1, RZ ; /* 0x0000000105027810 */
/* 0x000fc80007ffe0ff */
/*0700*/ IMNMX R2, RZ, R2, !PT ; /* 0x00000002ff027217 */
/* 0x000fc80007800200 */
/*0710*/ IMNMX R2, R2, UR5, PT ; /* 0x0000000502027c17 */
/* 0x000fc6000b800200 */
/*0720*/ @P1 IADD3 R3, R5, 0x2, RZ ; /* 0x0000000205031810 */
/* 0x000fc80007ffe0ff */
/*0730*/ @P1 IMNMX R3, RZ, R3, !PT ; /* 0x00000003ff031217 */
/* 0x000fc80007800200 */
/*0740*/ @P1 IMNMX R6, R3, UR5, PT ; /* 0x0000000503061c17 */
/* 0x000fe2000b800200 */
/*0750*/ IMAD R3, R2, c[0x0][0x174], R25 ; /* 0x00005d0002037a24 */
/* 0x000fc800078e0219 */
/*0760*/ @P1 IMAD R25, R6, c[0x0][0x174], R25 ; /* 0x00005d0006191a24 */
/* 0x000fe200078e0219 */
/*0770*/ IADD3 R2, P2, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f5e0ff */
/*0780*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P2 ; /* 0x0000590003037a11 */
/* 0x000fe400010f0eff */
/*0790*/ @P1 IADD3 R6, P2, R25, c[0x0][0x160], RZ ; /* 0x0000580019061a10 */
/* 0x000fc60007f5e0ff */
/*07a0*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea2000c1e1100 */
/*07b0*/ @P1 LEA.HI.X.SX32 R7, R25, c[0x0][0x164], 0x1, P2 ; /* 0x0000590019071a11 */
/* 0x000fe400010f0eff */
/*07c0*/ IADD3 R9, R29, c[0x0][0x180], RZ ; /* 0x000060001d097a10 */
/* 0x000fc60007ffe0ff */
/*07d0*/ @P1 LDG.E.U8 R6, [R6.64] ; /* 0x0000000806061981 */
/* 0x000ee2000c1e1100 */
/*07e0*/ @P1 IADD3 R5, R9.reuse, c[0x0][0x180], RZ ; /* 0x0000600009051a10 */
/* 0x040fe20007ffe0ff */
/*07f0*/ IMAD.WIDE R8, R9, R4, c[0x0][0x178] ; /* 0x00005e0009087625 */
/* 0x000fc800078e0204 */
/*0800*/ @P1 IMAD.WIDE R4, R5, R4, c[0x0][0x178] ; /* 0x00005e0005041625 */
/* 0x000fe400078e0204 */
/*0810*/ LDG.E.CONSTANT R8, [R8.64] ; /* 0x0000000808087981 */
/* 0x000f28000c1e9900 */
/*0820*/ @P1 LDG.E.CONSTANT R4, [R4.64] ; /* 0x0000000804041981 */
/* 0x000f62000c1e9900 */
/*0830*/ I2F.U16 R10, R2 ; /* 0x00000002000a7306 */
/* 0x004f300000101000 */
/*0840*/ @P1 I2F.U16 R12, R6 ; /* 0x00000006000c1306 */
/* 0x008f620000101000 */
/*0850*/ FFMA R27, R10, R8, R27 ; /* 0x000000080a1b7223 */
/* 0x010fc8000000001b */
/*0860*/ @P1 FFMA R27, R12, R4, R27 ; /* 0x000000040c1b1223 */
/* 0x020fc6000000001b */
/*0870*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fc80007ffe0ff */
/*0880*/ ISETP.GE.AND P1, PT, R18, c[0x0][0x180], PT ; /* 0x0000600012007a0c */
/* 0x000fda0003f26270 */
/*0890*/ @!P1 BRA 0x210 ; /* 0xfffff97000009947 */
/* 0x000fea000383ffff */
/*08a0*/ F2I.U32.TRUNC.NTZ R27, R27 ; /* 0x0000001b001b7305 */
/* 0x000e22000020f000 */
/*08b0*/ IMAD R0, R19, c[0x0][0x174], R0 ; /* 0x00005d0013007a24 */
/* 0x000fca00078e0200 */
/*08c0*/ IADD3 R2, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x000fc80007f1e0ff */
/*08d0*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f0eff */
/*08e0*/ STG.E.U8 [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x001fe2000c101108 */
/*08f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //****************************************************************************
// Also note that we've supplied a helpful debugging function called checkCudaErrors.
// You should wrap your allocation and copying statements like we've done in the
// code we're supplying you. Here is an example of the unsafe way to allocate
// memory on the GPU:
//
// cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols);
//
// Here is an example of the safe way to do the same thing:
//
// checkCudaErrors(cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols));
//****************************************************************************
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <iostream>
#include <iomanip>
#include <algorithm> // std::max
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
typedef unsigned char uchar;
#define FILTER_WIDTH 3
#define NTHREADS 32
#define checkCudaErrors(val) check( (val), #val, __FILE__, __LINE__)
template<typename T>
void check(T err, const char* const func, const char* const file, const int line) {
if (err != cudaSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << cudaGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
__constant__ float filtro[FILTER_WIDTH * FILTER_WIDTH];
__global__ void box_filter(const unsigned char* const inputChannel, unsigned char* const outputChannel,
int numRows, int numCols, const float* __restrict__ filter, const int filterWidth)
{
// Aplicar el filtro a cada pixel de la imagen...
// NOTA: Que un thread tenga una posición correcta en 2D no quiere decir que al aplicar el filtro
// los valores de sus vecinos sean correctos, ya que pueden salirse de la imagen.
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
float c = 0.0f;
for (int fx = 0; fx < filterWidth; ++fx) {
for (int fy = 0; fy < filterWidth; ++fy) {
int imagex = idx + fx - filterWidth / 2;
int imagey = idy + fy - filterWidth / 2;
imagex = min(max(imagex, 0), numCols - 1); // Limit image on borders...
imagey = min(max(imagey, 0), numRows - 1); // Limit image on borders...
c += (filter[fy * filterWidth + fx] * inputChannel[imagey * numCols + imagex]);
}
}
outputChannel[idy * numCols + idx] = c;
}
// This kernel takes in an image represented as a uchar4 and splits
// it into three images consisting of only one color channel each
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
int id = idy * numCols + idx;
redChannel[id] = inputImageRGBA[id].x;
greenChannel[id] = inputImageRGBA[id].y;
blueChannel[id] = inputImageRGBA[id].z;
}
// This kernel takes in three color channels and recombines them
// into one image. The alpha channel is set to 255 to represent
// that this image has no transparency.
__global__ void recombineChannels(const unsigned char* const redChannel,
const unsigned char* const greenChannel,
const unsigned char* const blueChannel,
uchar4* const outputImageRGBA,
int numRows,
int numCols)
{
const int2 thread_2D_pos = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
const int thread_1D_pos = thread_2D_pos.y * numCols + thread_2D_pos.x;
// make sure we don't try and access memory outside the image
//by having any threads mapped there return early...
if (thread_2D_pos.x >= numCols || thread_2D_pos.y >= numRows) return;
unsigned char red = redChannel[thread_1D_pos];
unsigned char green = greenChannel[thread_1D_pos];
unsigned char blue = blueChannel[thread_1D_pos];
// Alpha should be 255 for no transparency
uchar4 outputPixel = make_uchar4(red, green, blue, 255);
outputImageRGBA[thread_1D_pos] = outputPixel;
}
unsigned char *d_red, *d_green, *d_blue;
float *d_filter;
void allocateMemoryAndCopyToGPU(const size_t numRowsImage, const size_t numColsImage, const float* const h_filter, const size_t filterWidth)
{
int sizeImg = sizeof(uchar4) * numRowsImage * numColsImage;
int sizeFilter = sizeof(uchar4) * filterWidth * filterWidth;
cudaMalloc(&d_red, sizeImg);
cudaMalloc(&d_green, sizeImg);
cudaMalloc(&d_blue, sizeImg);
cudaMalloc(&d_filter, sizeFilter);
cudaMemcpy(d_filter, h_filter, sizeFilter, cudaMemcpyHostToDevice);
cudaMemset(d_red, 0, sizeImg);
cudaMemset(d_green, 0, sizeImg);
cudaMemset(d_blue, 0, sizeImg);
}
// Crear el filtro se que va a aplicar (en CPU) y almacenar su tamaño...
void create_filter(float **d_filter, const float *mask, const int size)
{
float *h_filter = (float *) malloc(sizeof(float) * size);
if (!h_filter) {
std::cerr << "Error creating filter.." << strerror(errno) << '\n';
exit(1);
}
for (int i = 0; i < size; ++i) {
h_filter[i] = mask[i];
}
cudaMalloc(d_filter, sizeof(float) * size);
cudaMemcpy(*d_filter, h_filter, sizeof(float) * size, cudaMemcpyHostToDevice);
}
void open_mpi_separate_channels(uchar4* const d_inputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_red,
unsigned char *d_green,
unsigned char *d_blue)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void open_mpi_box_filter(const unsigned char *channel,
unsigned char *filter_channel,
const size_t numRows,
const size_t numCols,
float* d_filter,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
box_filter<<<gridSize, blockSize>>>(channel, filter_channel, numRows, numCols, d_filter, filterWidth);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void open_mpi_recombine_channels(const unsigned char* d_redFiltered,
const unsigned char* d_greenFiltered,
const unsigned char* d_blueFiltered,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void convolution(uchar4* const d_inputImageRGBA,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_redFiltered,
unsigned char *d_greenFiltered,
unsigned char *d_blueFiltered,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
// Call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
box_filter<<<gridSize, blockSize>>>(d_red, d_redFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_blue, d_blueFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_green, d_greenFiltered, numRows, numCols, d_filter, filterWidth);
// Again, call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
//Free all the memory that we allocated
// TODO: make sure you free any arrays that you allocated
void cleanup() {
checkCudaErrors(cudaFree(d_red));
checkCudaErrors(cudaFree(d_green));
checkCudaErrors(cudaFree(d_blue));
checkCudaErrors(cudaFree(d_filter));
} | .file "tmpxft_001304c5_00000000-6_func.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4213:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4213:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26allocateMemoryAndCopyToGPUmmPKfm
.type _Z26allocateMemoryAndCopyToGPUmmPKfm, @function
_Z26allocateMemoryAndCopyToGPUmmPKfm:
.LFB4204:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdx, %r12
movq %rcx, %rbp
imull %esi, %edi
leal 0(,%rdi,4), %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
leaq d_red(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rsi
leaq d_green(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rsi
leaq d_blue(%rip), %rdi
call cudaMalloc@PLT
imull %ebp, %ebp
sall $2, %ebp
movslq %ebp, %rbp
movq %rbp, %rsi
leaq d_filter(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq d_filter(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
movl $0, %esi
movq d_red(%rip), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movl $0, %esi
movq d_green(%rip), %rdi
call cudaMemset@PLT
movq %rbx, %rdx
movl $0, %esi
movq d_blue(%rip), %rdi
call cudaMemset@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4204:
.size _Z26allocateMemoryAndCopyToGPUmmPKfm, .-_Z26allocateMemoryAndCopyToGPUmmPKfm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error creating filter.."
.text
.globl _Z13create_filterPPfPKfi
.type _Z13create_filterPPfPKfi, @function
_Z13create_filterPPfPKfi:
.LFB4205:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
movq %rsi, %r12
movl %edx, %r14d
movslq %edx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
testq %rax, %rax
je .L6
movq %rax, %rbp
movl $0, %eax
testl %r14d, %r14d
jle .L8
.L7:
movss (%r12,%rax), %xmm0
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq %rax, %rbx
jne .L7
.L8:
movq %rbx, %rsi
movq %r13, %rdi
call cudaMalloc@PLT
movq 0(%r13), %rdi
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
call cudaMemcpy@PLT
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
leaq .LC0(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rbx
call __errno_location@PLT
movl (%rax), %edi
call strerror@PLT
movq %rax, %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $10, %esi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4205:
.size _Z13create_filterPPfPKfi, .-_Z13create_filterPPfPKfi
.globl _Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi
.type _Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi, @function
_Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi:
.LFB4235:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
movq %r8, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10box_filterPKhPhiiPKfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4235:
.size _Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi, .-_Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi
.globl _Z10box_filterPKhPhiiPKfi
.type _Z10box_filterPKhPhiiPKfi, @function
_Z10box_filterPKhPhiiPKfi:
.LFB4236:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4236:
.size _Z10box_filterPKhPhiiPKfi, .-_Z10box_filterPKhPhiiPKfi
.globl _Z53__device_stub__Z16separateChannelsPK6uchar4iiPhS2_S2_PK6uchar4iiPhS2_S2_
.type _Z53__device_stub__Z16separateChannelsPK6uchar4iiPhS2_S2_PK6uchar4iiPhS2_S2_, @function
_Z53__device_stub__Z16separateChannelsPK6uchar4iiPhS2_S2_PK6uchar4iiPhS2_S2_:
.LFB4237:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z16separateChannelsPK6uchar4iiPhS2_S2_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4237:
.size _Z53__device_stub__Z16separateChannelsPK6uchar4iiPhS2_S2_PK6uchar4iiPhS2_S2_, .-_Z53__device_stub__Z16separateChannelsPK6uchar4iiPhS2_S2_PK6uchar4iiPhS2_S2_
.globl _Z16separateChannelsPK6uchar4iiPhS2_S2_
.type _Z16separateChannelsPK6uchar4iiPhS2_S2_, @function
_Z16separateChannelsPK6uchar4iiPhS2_S2_:
.LFB4238:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z16separateChannelsPK6uchar4iiPhS2_S2_PK6uchar4iiPhS2_S2_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4238:
.size _Z16separateChannelsPK6uchar4iiPhS2_S2_, .-_Z16separateChannelsPK6uchar4iiPhS2_S2_
.globl _Z54__device_stub__Z17recombineChannelsPKhS0_S0_P6uchar4iiPKhS0_S0_P6uchar4ii
.type _Z54__device_stub__Z17recombineChannelsPKhS0_S0_P6uchar4iiPKhS0_S0_P6uchar4ii, @function
_Z54__device_stub__Z17recombineChannelsPKhS0_S0_P6uchar4iiPKhS0_S0_P6uchar4ii:
.LFB4239:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17recombineChannelsPKhS0_S0_P6uchar4ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4239:
.size _Z54__device_stub__Z17recombineChannelsPKhS0_S0_P6uchar4iiPKhS0_S0_P6uchar4ii, .-_Z54__device_stub__Z17recombineChannelsPKhS0_S0_P6uchar4iiPKhS0_S0_P6uchar4ii
.globl _Z17recombineChannelsPKhS0_S0_P6uchar4ii
.type _Z17recombineChannelsPKhS0_S0_P6uchar4ii, @function
_Z17recombineChannelsPKhS0_S0_P6uchar4ii:
.LFB4240:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z17recombineChannelsPKhS0_S0_P6uchar4iiPKhS0_S0_P6uchar4ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4240:
.size _Z17recombineChannelsPKhS0_S0_P6uchar4ii, .-_Z17recombineChannelsPKhS0_S0_P6uchar4ii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z17recombineChannelsPKhS0_S0_P6uchar4ii"
.align 8
.LC2:
.string "_Z16separateChannelsPK6uchar4iiPhS2_S2_"
.section .rodata.str1.1
.LC3:
.string "_Z10box_filterPKhPhiiPKfi"
.LC4:
.string "filtro"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4242:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17recombineChannelsPKhS0_S0_P6uchar4ii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16separateChannelsPK6uchar4iiPhS2_S2_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10box_filterPKhPhiiPKfi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $36, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL6filtro(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4242:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z5checkI9cudaErrorEvT_PKcS3_i.str1.1,"aMS",@progbits,1
.LC5:
.string "CUDA error at: "
.LC6:
.string ":"
.LC7:
.string " "
.section .text._Z5checkI9cudaErrorEvT_PKcS3_i,"axG",@progbits,_Z5checkI9cudaErrorEvT_PKcS3_i,comdat
.weak _Z5checkI9cudaErrorEvT_PKcS3_i
.type _Z5checkI9cudaErrorEvT_PKcS3_i, @function
_Z5checkI9cudaErrorEvT_PKcS3_i:
.LFB4560:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L44
ret
.L44:
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movl %edi, %ebx
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
leaq .LC5(%rip), %rsi
leaq _ZSt4cerr(%rip), %r14
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC6(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl %ebp, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %rsi
movq %r14, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC7(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE4560:
.size _Z5checkI9cudaErrorEvT_PKcS3_i, .-_Z5checkI9cudaErrorEvT_PKcS3_i
.section .rodata.str1.8
.align 8
.LC8:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jgmatu/CUDAMPI/master/3/color-filter-cuda/func.cu"
.section .rodata.str1.1
.LC9:
.string "cudaGetLastError()"
.text
.globl _Z26open_mpi_separate_channelsP6uchar4mmPhS1_S1_
.type _Z26open_mpi_separate_channelsP6uchar4mmPhS1_S1_, @function
_Z26open_mpi_separate_channelsP6uchar4mmPhS1_S1_:
.LFB4206:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %rbp
movq %rcx, %r13
movq %r8, %r14
movq %r9, %r15
leaq -1(%rdx), %rax
shrq $5, %rax
addl $1, %eax
movl %eax, 20(%rsp)
leaq -1(%rsi), %rax
shrq $5, %rax
addl $1, %eax
movl %eax, 24(%rsp)
movl $32, 8(%rsp)
movl $32, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L48
.L46:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
movl $157, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movq %r15, %r9
movq %r14, %r8
movq %r13, %rcx
movl %ebp, %edx
movl %ebx, %esi
movq %r12, %rdi
call _Z53__device_stub__Z16separateChannelsPK6uchar4iiPhS2_S2_PK6uchar4iiPhS2_S2_
jmp .L46
.cfi_endproc
.LFE4206:
.size _Z26open_mpi_separate_channelsP6uchar4mmPhS1_S1_, .-_Z26open_mpi_separate_channelsP6uchar4mmPhS1_S1_
.globl _Z19open_mpi_box_filterPKhPhmmPfi
.type _Z19open_mpi_box_filterPKhPhmmPfi, @function
_Z19open_mpi_box_filterPKhPhmmPfi:
.LFB4207:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r14
movl %r9d, %r15d
leaq -1(%rcx), %rax
shrq $5, %rax
addl $1, %eax
movl %eax, 20(%rsp)
leaq -1(%rdx), %rax
shrq $5, %rax
addl $1, %eax
movl %eax, 24(%rsp)
movl $32, 8(%rsp)
movl $32, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L50:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
movl $171, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %r15d, %r9d
movq %r14, %r8
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq %r12, %rdi
call _Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi
jmp .L50
.cfi_endproc
.LFE4207:
.size _Z19open_mpi_box_filterPKhPhmmPfi, .-_Z19open_mpi_box_filterPKhPhmmPfi
.globl _Z27open_mpi_recombine_channelsPKhS0_S0_P6uchar4mm
.type _Z27open_mpi_recombine_channelsPKhS0_S0_P6uchar4mm, @function
_Z27open_mpi_recombine_channelsPKhS0_S0_P6uchar4mm:
.LFB4208:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r13
movq %rdx, %r14
movq %rcx, %r15
movq %r8, %rbx
movq %r9, %rbp
leaq -1(%r9), %rax
shrq $5, %rax
addl $1, %eax
movl %eax, 20(%rsp)
leaq -1(%r8), %rax
shrq $5, %rax
addl $1, %eax
movl %eax, 24(%rsp)
movl $32, 8(%rsp)
movl $32, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L54:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
movl $185, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L56:
.cfi_restore_state
movl %ebp, %r9d
movl %ebx, %r8d
movq %r15, %rcx
movq %r14, %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z54__device_stub__Z17recombineChannelsPKhS0_S0_P6uchar4iiPKhS0_S0_P6uchar4ii
jmp .L54
.cfi_endproc
.LFE4208:
.size _Z27open_mpi_recombine_channelsPKhS0_S0_P6uchar4mm, .-_Z27open_mpi_recombine_channelsPKhS0_S0_P6uchar4mm
.globl _Z11convolutionP6uchar4S0_mmPhS1_S1_i
.type _Z11convolutionP6uchar4S0_mmPhS1_S1_i, @function
_Z11convolutionP6uchar4S0_mmPhS1_S1_i:
.LFB4209:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r15
movq %rsi, %r14
movq %rdx, %rbx
movq %rcx, %rbp
movq %r8, %r12
movq %r9, %r13
movl $1, 16(%rsp)
leaq -1(%rcx), %rax
shrq $5, %rax
addl $1, %eax
movl %eax, 20(%rsp)
leaq -1(%rdx), %rax
shrq $5, %rax
addl $1, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $32, 8(%rsp)
movl $32, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L64
.L58:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
movl $204, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L59:
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L60:
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L61:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
movl $212, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L62:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %edi
movl $215, %ecx
leaq .LC8(%rip), %rdx
leaq .LC9(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L64:
.cfi_restore_state
movq d_blue(%rip), %r9
movq d_green(%rip), %r8
movq d_red(%rip), %rcx
movl %ebp, %edx
movl %ebx, %esi
movq %r15, %rdi
call _Z53__device_stub__Z16separateChannelsPK6uchar4iiPhS2_S2_PK6uchar4iiPhS2_S2_
jmp .L58
.L65:
movl 104(%rsp), %r9d
movq d_filter(%rip), %r8
movl %ebp, %ecx
movl %ebx, %edx
movq %r12, %rsi
movq d_red(%rip), %rdi
call _Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi
jmp .L59
.L66:
movl 104(%rsp), %r9d
movq d_filter(%rip), %r8
movl %ebp, %ecx
movl %ebx, %edx
movq 96(%rsp), %rsi
movq d_blue(%rip), %rdi
call _Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi
jmp .L60
.L67:
movl 104(%rsp), %r9d
movq d_filter(%rip), %r8
movl %ebp, %ecx
movl %ebx, %edx
movq %r13, %rsi
movq d_green(%rip), %rdi
call _Z39__device_stub__Z10box_filterPKhPhiiPKfiPKhPhiiPKfi
jmp .L61
.L68:
movl %ebp, %r9d
movl %ebx, %r8d
movq %r14, %rcx
movq 96(%rsp), %rdx
movq %r13, %rsi
movq %r12, %rdi
call _Z54__device_stub__Z17recombineChannelsPKhS0_S0_P6uchar4iiPKhS0_S0_P6uchar4ii
jmp .L62
.cfi_endproc
.LFE4209:
.size _Z11convolutionP6uchar4S0_mmPhS1_S1_i, .-_Z11convolutionP6uchar4S0_mmPhS1_S1_i
.section .rodata.str1.1
.LC10:
.string "cudaFree(d_red)"
.LC11:
.string "cudaFree(d_green)"
.LC12:
.string "cudaFree(d_blue)"
.LC13:
.string "cudaFree(d_filter)"
.text
.globl _Z7cleanupv
.type _Z7cleanupv, @function
_Z7cleanupv:
.LFB4210:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq d_red(%rip), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $221, %ecx
leaq .LC8(%rip), %rbx
movq %rbx, %rdx
leaq .LC10(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
movq d_green(%rip), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $222, %ecx
movq %rbx, %rdx
leaq .LC11(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
movq d_blue(%rip), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $223, %ecx
movq %rbx, %rdx
leaq .LC12(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
movq d_filter(%rip), %rdi
call cudaFree@PLT
movl %eax, %edi
movl $224, %ecx
movq %rbx, %rdx
leaq .LC13(%rip), %rsi
call _Z5checkI9cudaErrorEvT_PKcS3_i
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4210:
.size _Z7cleanupv, .-_Z7cleanupv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl d_filter
.bss
.align 8
.type d_filter, @object
.size d_filter, 8
d_filter:
.zero 8
.globl d_blue
.align 8
.type d_blue, @object
.size d_blue, 8
d_blue:
.zero 8
.globl d_green
.align 8
.type d_green, @object
.size d_green, 8
d_green:
.zero 8
.globl d_red
.align 8
.type d_red, @object
.size d_red, 8
d_red:
.zero 8
.local _ZL6filtro
.comm _ZL6filtro,36,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //****************************************************************************
// Also note that we've supplied a helpful debugging function called checkCudaErrors.
// You should wrap your allocation and copying statements like we've done in the
// code we're supplying you. Here is an example of the unsafe way to allocate
// memory on the GPU:
//
// cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols);
//
// Here is an example of the safe way to do the same thing:
//
// checkCudaErrors(cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols));
//****************************************************************************
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <iostream>
#include <iomanip>
#include <algorithm> // std::max
#include <cuda.h>
#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
typedef unsigned char uchar;
#define FILTER_WIDTH 3
#define NTHREADS 32
#define checkCudaErrors(val) check( (val), #val, __FILE__, __LINE__)
template<typename T>
void check(T err, const char* const func, const char* const file, const int line) {
if (err != cudaSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << cudaGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
__constant__ float filtro[FILTER_WIDTH * FILTER_WIDTH];
__global__ void box_filter(const unsigned char* const inputChannel, unsigned char* const outputChannel,
int numRows, int numCols, const float* __restrict__ filter, const int filterWidth)
{
// Aplicar el filtro a cada pixel de la imagen...
// NOTA: Que un thread tenga una posición correcta en 2D no quiere decir que al aplicar el filtro
// los valores de sus vecinos sean correctos, ya que pueden salirse de la imagen.
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
float c = 0.0f;
for (int fx = 0; fx < filterWidth; ++fx) {
for (int fy = 0; fy < filterWidth; ++fy) {
int imagex = idx + fx - filterWidth / 2;
int imagey = idy + fy - filterWidth / 2;
imagex = min(max(imagex, 0), numCols - 1); // Limit image on borders...
imagey = min(max(imagey, 0), numRows - 1); // Limit image on borders...
c += (filter[fy * filterWidth + fx] * inputChannel[imagey * numCols + imagex]);
}
}
outputChannel[idy * numCols + idx] = c;
}
// This kernel takes in an image represented as a uchar4 and splits
// it into three images consisting of only one color channel each
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
int id = idy * numCols + idx;
redChannel[id] = inputImageRGBA[id].x;
greenChannel[id] = inputImageRGBA[id].y;
blueChannel[id] = inputImageRGBA[id].z;
}
// This kernel takes in three color channels and recombines them
// into one image. The alpha channel is set to 255 to represent
// that this image has no transparency.
__global__ void recombineChannels(const unsigned char* const redChannel,
const unsigned char* const greenChannel,
const unsigned char* const blueChannel,
uchar4* const outputImageRGBA,
int numRows,
int numCols)
{
const int2 thread_2D_pos = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
const int thread_1D_pos = thread_2D_pos.y * numCols + thread_2D_pos.x;
// make sure we don't try and access memory outside the image
//by having any threads mapped there return early...
if (thread_2D_pos.x >= numCols || thread_2D_pos.y >= numRows) return;
unsigned char red = redChannel[thread_1D_pos];
unsigned char green = greenChannel[thread_1D_pos];
unsigned char blue = blueChannel[thread_1D_pos];
// Alpha should be 255 for no transparency
uchar4 outputPixel = make_uchar4(red, green, blue, 255);
outputImageRGBA[thread_1D_pos] = outputPixel;
}
unsigned char *d_red, *d_green, *d_blue;
float *d_filter;
void allocateMemoryAndCopyToGPU(const size_t numRowsImage, const size_t numColsImage, const float* const h_filter, const size_t filterWidth)
{
int sizeImg = sizeof(uchar4) * numRowsImage * numColsImage;
int sizeFilter = sizeof(uchar4) * filterWidth * filterWidth;
cudaMalloc(&d_red, sizeImg);
cudaMalloc(&d_green, sizeImg);
cudaMalloc(&d_blue, sizeImg);
cudaMalloc(&d_filter, sizeFilter);
cudaMemcpy(d_filter, h_filter, sizeFilter, cudaMemcpyHostToDevice);
cudaMemset(d_red, 0, sizeImg);
cudaMemset(d_green, 0, sizeImg);
cudaMemset(d_blue, 0, sizeImg);
}
// Crear el filtro se que va a aplicar (en CPU) y almacenar su tamaño...
void create_filter(float **d_filter, const float *mask, const int size)
{
float *h_filter = (float *) malloc(sizeof(float) * size);
if (!h_filter) {
std::cerr << "Error creating filter.." << strerror(errno) << '\n';
exit(1);
}
for (int i = 0; i < size; ++i) {
h_filter[i] = mask[i];
}
cudaMalloc(d_filter, sizeof(float) * size);
cudaMemcpy(*d_filter, h_filter, sizeof(float) * size, cudaMemcpyHostToDevice);
}
void open_mpi_separate_channels(uchar4* const d_inputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_red,
unsigned char *d_green,
unsigned char *d_blue)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void open_mpi_box_filter(const unsigned char *channel,
unsigned char *filter_channel,
const size_t numRows,
const size_t numCols,
float* d_filter,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
box_filter<<<gridSize, blockSize>>>(channel, filter_channel, numRows, numCols, d_filter, filterWidth);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void open_mpi_recombine_channels(const unsigned char* d_redFiltered,
const unsigned char* d_greenFiltered,
const unsigned char* d_blueFiltered,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
void convolution(uchar4* const d_inputImageRGBA,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_redFiltered,
unsigned char *d_greenFiltered,
unsigned char *d_blueFiltered,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
// Call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
box_filter<<<gridSize, blockSize>>>(d_red, d_redFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_blue, d_blueFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_green, d_greenFiltered, numRows, numCols, d_filter, filterWidth);
// Again, call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
}
//Free all the memory that we allocated
// TODO: make sure you free any arrays that you allocated
void cleanup() {
checkCudaErrors(cudaFree(d_red));
checkCudaErrors(cudaFree(d_green));
checkCudaErrors(cudaFree(d_blue));
checkCudaErrors(cudaFree(d_filter));
} | //****************************************************************************
// Also note that we've supplied a helpful debugging function called checkCudaErrors.
// You should wrap your allocation and copying statements like we've done in the
// code we're supplying you. Here is an example of the unsafe way to allocate
// memory on the GPU:
//
// cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols);
//
// Here is an example of the safe way to do the same thing:
//
// checkCudaErrors(cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols));
//****************************************************************************
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <iostream>
#include <iomanip>
#include <algorithm> // std::max
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
typedef unsigned char uchar;
#define FILTER_WIDTH 3
#define NTHREADS 32
#define checkCudaErrors(val) check( (val), #val, __FILE__, __LINE__)
template<typename T>
void check(T err, const char* const func, const char* const file, const int line) {
if (err != hipSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << hipGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
__constant__ float filtro[FILTER_WIDTH * FILTER_WIDTH];
__global__ void box_filter(const unsigned char* const inputChannel, unsigned char* const outputChannel,
int numRows, int numCols, const float* __restrict__ filter, const int filterWidth)
{
// Aplicar el filtro a cada pixel de la imagen...
// NOTA: Que un thread tenga una posición correcta en 2D no quiere decir que al aplicar el filtro
// los valores de sus vecinos sean correctos, ya que pueden salirse de la imagen.
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
float c = 0.0f;
for (int fx = 0; fx < filterWidth; ++fx) {
for (int fy = 0; fy < filterWidth; ++fy) {
int imagex = idx + fx - filterWidth / 2;
int imagey = idy + fy - filterWidth / 2;
imagex = min(max(imagex, 0), numCols - 1); // Limit image on borders...
imagey = min(max(imagey, 0), numRows - 1); // Limit image on borders...
c += (filter[fy * filterWidth + fx] * inputChannel[imagey * numCols + imagex]);
}
}
outputChannel[idy * numCols + idx] = c;
}
// This kernel takes in an image represented as a uchar4 and splits
// it into three images consisting of only one color channel each
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
int id = idy * numCols + idx;
redChannel[id] = inputImageRGBA[id].x;
greenChannel[id] = inputImageRGBA[id].y;
blueChannel[id] = inputImageRGBA[id].z;
}
// This kernel takes in three color channels and recombines them
// into one image. The alpha channel is set to 255 to represent
// that this image has no transparency.
__global__ void recombineChannels(const unsigned char* const redChannel,
const unsigned char* const greenChannel,
const unsigned char* const blueChannel,
uchar4* const outputImageRGBA,
int numRows,
int numCols)
{
const int2 thread_2D_pos = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
const int thread_1D_pos = thread_2D_pos.y * numCols + thread_2D_pos.x;
// make sure we don't try and access memory outside the image
//by having any threads mapped there return early...
if (thread_2D_pos.x >= numCols || thread_2D_pos.y >= numRows) return;
unsigned char red = redChannel[thread_1D_pos];
unsigned char green = greenChannel[thread_1D_pos];
unsigned char blue = blueChannel[thread_1D_pos];
// Alpha should be 255 for no transparency
uchar4 outputPixel = make_uchar4(red, green, blue, 255);
outputImageRGBA[thread_1D_pos] = outputPixel;
}
unsigned char *d_red, *d_green, *d_blue;
float *d_filter;
void allocateMemoryAndCopyToGPU(const size_t numRowsImage, const size_t numColsImage, const float* const h_filter, const size_t filterWidth)
{
int sizeImg = sizeof(uchar4) * numRowsImage * numColsImage;
int sizeFilter = sizeof(uchar4) * filterWidth * filterWidth;
hipMalloc(&d_red, sizeImg);
hipMalloc(&d_green, sizeImg);
hipMalloc(&d_blue, sizeImg);
hipMalloc(&d_filter, sizeFilter);
hipMemcpy(d_filter, h_filter, sizeFilter, hipMemcpyHostToDevice);
hipMemset(d_red, 0, sizeImg);
hipMemset(d_green, 0, sizeImg);
hipMemset(d_blue, 0, sizeImg);
}
// Crear el filtro se que va a aplicar (en CPU) y almacenar su tamaño...
void create_filter(float **d_filter, const float *mask, const int size)
{
float *h_filter = (float *) malloc(sizeof(float) * size);
if (!h_filter) {
std::cerr << "Error creating filter.." << strerror(errno) << '\n';
exit(1);
}
for (int i = 0; i < size; ++i) {
h_filter[i] = mask[i];
}
hipMalloc(d_filter, sizeof(float) * size);
hipMemcpy(*d_filter, h_filter, sizeof(float) * size, hipMemcpyHostToDevice);
}
void open_mpi_separate_channels(uchar4* const d_inputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_red,
unsigned char *d_green,
unsigned char *d_blue)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void open_mpi_box_filter(const unsigned char *channel,
unsigned char *filter_channel,
const size_t numRows,
const size_t numCols,
float* d_filter,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
box_filter<<<gridSize, blockSize>>>(channel, filter_channel, numRows, numCols, d_filter, filterWidth);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void open_mpi_recombine_channels(const unsigned char* d_redFiltered,
const unsigned char* d_greenFiltered,
const unsigned char* d_blueFiltered,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void convolution(uchar4* const d_inputImageRGBA,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_redFiltered,
unsigned char *d_greenFiltered,
unsigned char *d_blueFiltered,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
// Call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
box_filter<<<gridSize, blockSize>>>(d_red, d_redFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_blue, d_blueFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_green, d_greenFiltered, numRows, numCols, d_filter, filterWidth);
// Again, call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
//Free all the memory that we allocated
// TODO: make sure you free any arrays that you allocated
void cleanup() {
checkCudaErrors(hipFree(d_red));
checkCudaErrors(hipFree(d_green));
checkCudaErrors(hipFree(d_blue));
checkCudaErrors(hipFree(d_filter));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //****************************************************************************
// Also note that we've supplied a helpful debugging function called checkCudaErrors.
// You should wrap your allocation and copying statements like we've done in the
// code we're supplying you. Here is an example of the unsafe way to allocate
// memory on the GPU:
//
// cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols);
//
// Here is an example of the safe way to do the same thing:
//
// checkCudaErrors(cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols));
//****************************************************************************
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <iostream>
#include <iomanip>
#include <algorithm> // std::max
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
typedef unsigned char uchar;
#define FILTER_WIDTH 3
#define NTHREADS 32
#define checkCudaErrors(val) check( (val), #val, __FILE__, __LINE__)
template<typename T>
void check(T err, const char* const func, const char* const file, const int line) {
if (err != hipSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << hipGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
__constant__ float filtro[FILTER_WIDTH * FILTER_WIDTH];
__global__ void box_filter(const unsigned char* const inputChannel, unsigned char* const outputChannel,
int numRows, int numCols, const float* __restrict__ filter, const int filterWidth)
{
// Aplicar el filtro a cada pixel de la imagen...
// NOTA: Que un thread tenga una posición correcta en 2D no quiere decir que al aplicar el filtro
// los valores de sus vecinos sean correctos, ya que pueden salirse de la imagen.
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
float c = 0.0f;
for (int fx = 0; fx < filterWidth; ++fx) {
for (int fy = 0; fy < filterWidth; ++fy) {
int imagex = idx + fx - filterWidth / 2;
int imagey = idy + fy - filterWidth / 2;
imagex = min(max(imagex, 0), numCols - 1); // Limit image on borders...
imagey = min(max(imagey, 0), numRows - 1); // Limit image on borders...
c += (filter[fy * filterWidth + fx] * inputChannel[imagey * numCols + imagex]);
}
}
outputChannel[idy * numCols + idx] = c;
}
// This kernel takes in an image represented as a uchar4 and splits
// it into three images consisting of only one color channel each
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
int id = idy * numCols + idx;
redChannel[id] = inputImageRGBA[id].x;
greenChannel[id] = inputImageRGBA[id].y;
blueChannel[id] = inputImageRGBA[id].z;
}
// This kernel takes in three color channels and recombines them
// into one image. The alpha channel is set to 255 to represent
// that this image has no transparency.
__global__ void recombineChannels(const unsigned char* const redChannel,
const unsigned char* const greenChannel,
const unsigned char* const blueChannel,
uchar4* const outputImageRGBA,
int numRows,
int numCols)
{
const int2 thread_2D_pos = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
const int thread_1D_pos = thread_2D_pos.y * numCols + thread_2D_pos.x;
// make sure we don't try and access memory outside the image
//by having any threads mapped there return early...
if (thread_2D_pos.x >= numCols || thread_2D_pos.y >= numRows) return;
unsigned char red = redChannel[thread_1D_pos];
unsigned char green = greenChannel[thread_1D_pos];
unsigned char blue = blueChannel[thread_1D_pos];
// Alpha should be 255 for no transparency
uchar4 outputPixel = make_uchar4(red, green, blue, 255);
outputImageRGBA[thread_1D_pos] = outputPixel;
}
unsigned char *d_red, *d_green, *d_blue;
float *d_filter;
void allocateMemoryAndCopyToGPU(const size_t numRowsImage, const size_t numColsImage, const float* const h_filter, const size_t filterWidth)
{
int sizeImg = sizeof(uchar4) * numRowsImage * numColsImage;
int sizeFilter = sizeof(uchar4) * filterWidth * filterWidth;
hipMalloc(&d_red, sizeImg);
hipMalloc(&d_green, sizeImg);
hipMalloc(&d_blue, sizeImg);
hipMalloc(&d_filter, sizeFilter);
hipMemcpy(d_filter, h_filter, sizeFilter, hipMemcpyHostToDevice);
hipMemset(d_red, 0, sizeImg);
hipMemset(d_green, 0, sizeImg);
hipMemset(d_blue, 0, sizeImg);
}
// Crear el filtro se que va a aplicar (en CPU) y almacenar su tamaño...
void create_filter(float **d_filter, const float *mask, const int size)
{
float *h_filter = (float *) malloc(sizeof(float) * size);
if (!h_filter) {
std::cerr << "Error creating filter.." << strerror(errno) << '\n';
exit(1);
}
for (int i = 0; i < size; ++i) {
h_filter[i] = mask[i];
}
hipMalloc(d_filter, sizeof(float) * size);
hipMemcpy(*d_filter, h_filter, sizeof(float) * size, hipMemcpyHostToDevice);
}
void open_mpi_separate_channels(uchar4* const d_inputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_red,
unsigned char *d_green,
unsigned char *d_blue)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void open_mpi_box_filter(const unsigned char *channel,
unsigned char *filter_channel,
const size_t numRows,
const size_t numCols,
float* d_filter,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
box_filter<<<gridSize, blockSize>>>(channel, filter_channel, numRows, numCols, d_filter, filterWidth);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void open_mpi_recombine_channels(const unsigned char* d_redFiltered,
const unsigned char* d_greenFiltered,
const unsigned char* d_blueFiltered,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void convolution(uchar4* const d_inputImageRGBA,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_redFiltered,
unsigned char *d_greenFiltered,
unsigned char *d_blueFiltered,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
// Call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
box_filter<<<gridSize, blockSize>>>(d_red, d_redFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_blue, d_blueFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_green, d_greenFiltered, numRows, numCols, d_filter, filterWidth);
// Again, call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
//Free all the memory that we allocated
// TODO: make sure you free any arrays that you allocated
void cleanup() {
checkCudaErrors(hipFree(d_red));
checkCudaErrors(hipFree(d_green));
checkCudaErrors(hipFree(d_blue));
checkCudaErrors(hipFree(d_filter));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10box_filterPKhPhiiPKfi
.globl _Z10box_filterPKhPhiiPKfi
.p2align 8
.type _Z10box_filterPKhPhiiPKfi,@function
_Z10box_filterPKhPhiiPKfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
s_mul_i32 s15, s15, s2
v_add_nc_u32_e32 v2, s15, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_9
s_load_b32 s10, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s10, 1
s_cbranch_scc1 .LBB0_7
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x0
s_lshr_b32 s8, s10, 1
v_mov_b32_e32 v5, 0
v_subrev_nc_u32_e32 v3, s8, v0
v_subrev_nc_u32_e32 v4, s8, v2
s_add_i32 s11, s5, -1
s_add_i32 s4, s4, -1
s_mov_b32 s9, 0
s_mov_b32 s12, 0
.p2align 6
.LBB0_3:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s12, v3
s_mov_b32 s8, s12
s_mov_b32 s13, s9
v_maxmin_i32 v1, v1, 0, s11
.p2align 6
.LBB0_4:
v_add_nc_u32_e32 v6, s13, v4
s_lshl_b64 s[14:15], s[8:9], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s14, s2, s14
s_addc_u32 s15, s3, s15
v_maxmin_i32 v8, v6, 0, s4
s_load_b32 s14, s[14:15], 0x0
s_add_i32 s13, s13, 1
s_add_i32 s8, s8, s10
s_cmp_eq_u32 s10, s13
v_mad_u64_u32 v[6:7], null, v8, s5, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v7, 31, v6
v_add_co_u32 v6, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_u8 v6, v[6:7], off
s_waitcnt vmcnt(0)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, s14, v6
s_cbranch_scc0 .LBB0_4
s_add_i32 s12, s12, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s12, s10
s_cbranch_scc0 .LBB0_3
v_cvt_i32_f32_e32 v1, v5
s_branch .LBB0_8
.LBB0_7:
v_mov_b32_e32 v1, 0
.LBB0_8:
s_load_b64 s[0:1], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s5, v[0:1]
v_ashrrev_i32_e32 v0, 31, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v0, vcc_lo
global_store_b8 v[2:3], v1, off
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10box_filterPKhPhiiPKfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10box_filterPKhPhiiPKfi, .Lfunc_end0-_Z10box_filterPKhPhiiPKfi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.globl _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.p2align 8
.type _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_,@function
_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b128 s[4:7], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_load_b64 s[0:1], s[0:1], 0x20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s8, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
global_load_u8 v6, v[0:1], off
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v6, off
global_load_u8 v6, v[0:1], off offset:1
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v6, off
global_load_u8 v4, v[0:1], off offset:2
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v4, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, .Lfunc_end1-_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.globl _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.p2align 8
.type _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii,@function
_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x20
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB2_2
s_load_b256 s[4:11], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v1, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
global_load_u8 v4, v[4:5], off
global_load_u8 v5, v[6:7], off
global_load_u8 v0, v[0:1], off
s_waitcnt vmcnt(2)
v_lshlrev_b16 v1, 8, v4
s_waitcnt vmcnt(1)
v_or_b32_e32 v4, 0xffffff00, v5
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v0, v0, v1
v_lshlrev_b32_e32 v4, 16, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v5, 0xffff, v0
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_or_b32_e32 v2, v5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s10, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii, .Lfunc_end2-_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected filtro
.type filtro,@object
.section .bss,"aw",@nobits
.globl filtro
.p2align 4, 0x0
filtro:
.zero 36
.size filtro, 36
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .actual_access: read_only
.address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10box_filterPKhPhiiPKfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10box_filterPKhPhiiPKfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //****************************************************************************
// Also note that we've supplied a helpful debugging function called checkCudaErrors.
// You should wrap your allocation and copying statements like we've done in the
// code we're supplying you. Here is an example of the unsafe way to allocate
// memory on the GPU:
//
// cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols);
//
// Here is an example of the safe way to do the same thing:
//
// checkCudaErrors(cudaMalloc(&d_red, sizeof(unsigned char) * numRows * numCols));
//****************************************************************************
#include <stdio.h>
#include <errno.h>
#include <string.h>
#include <iostream>
#include <iomanip>
#include <algorithm> // std::max
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
typedef unsigned char uchar;
#define FILTER_WIDTH 3
#define NTHREADS 32
#define checkCudaErrors(val) check( (val), #val, __FILE__, __LINE__)
template<typename T>
void check(T err, const char* const func, const char* const file, const int line) {
if (err != hipSuccess) {
std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
std::cerr << hipGetErrorString(err) << " " << func << std::endl;
exit(1);
}
}
__constant__ float filtro[FILTER_WIDTH * FILTER_WIDTH];
__global__ void box_filter(const unsigned char* const inputChannel, unsigned char* const outputChannel,
int numRows, int numCols, const float* __restrict__ filter, const int filterWidth)
{
// Aplicar el filtro a cada pixel de la imagen...
// NOTA: Que un thread tenga una posición correcta en 2D no quiere decir que al aplicar el filtro
// los valores de sus vecinos sean correctos, ya que pueden salirse de la imagen.
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
float c = 0.0f;
for (int fx = 0; fx < filterWidth; ++fx) {
for (int fy = 0; fy < filterWidth; ++fy) {
int imagex = idx + fx - filterWidth / 2;
int imagey = idy + fy - filterWidth / 2;
imagex = min(max(imagex, 0), numCols - 1); // Limit image on borders...
imagey = min(max(imagey, 0), numRows - 1); // Limit image on borders...
c += (filter[fy * filterWidth + fx] * inputChannel[imagey * numCols + imagex]);
}
}
outputChannel[idy * numCols + idx] = c;
}
// This kernel takes in an image represented as a uchar4 and splits
// it into three images consisting of only one color channel each
__global__ void separateChannels(const uchar4* const inputImageRGBA,
int numRows,
int numCols,
unsigned char* const redChannel,
unsigned char* const greenChannel,
unsigned char* const blueChannel)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int idy = blockIdx.y * blockDim.y + threadIdx.y;
if (idx >= numCols || idy >= numRows) return;
int id = idy * numCols + idx;
redChannel[id] = inputImageRGBA[id].x;
greenChannel[id] = inputImageRGBA[id].y;
blueChannel[id] = inputImageRGBA[id].z;
}
// This kernel takes in three color channels and recombines them
// into one image. The alpha channel is set to 255 to represent
// that this image has no transparency.
__global__ void recombineChannels(const unsigned char* const redChannel,
const unsigned char* const greenChannel,
const unsigned char* const blueChannel,
uchar4* const outputImageRGBA,
int numRows,
int numCols)
{
const int2 thread_2D_pos = make_int2(blockIdx.x * blockDim.x + threadIdx.x, blockIdx.y * blockDim.y + threadIdx.y);
const int thread_1D_pos = thread_2D_pos.y * numCols + thread_2D_pos.x;
// make sure we don't try and access memory outside the image
//by having any threads mapped there return early...
if (thread_2D_pos.x >= numCols || thread_2D_pos.y >= numRows) return;
unsigned char red = redChannel[thread_1D_pos];
unsigned char green = greenChannel[thread_1D_pos];
unsigned char blue = blueChannel[thread_1D_pos];
// Alpha should be 255 for no transparency
uchar4 outputPixel = make_uchar4(red, green, blue, 255);
outputImageRGBA[thread_1D_pos] = outputPixel;
}
unsigned char *d_red, *d_green, *d_blue;
float *d_filter;
void allocateMemoryAndCopyToGPU(const size_t numRowsImage, const size_t numColsImage, const float* const h_filter, const size_t filterWidth)
{
int sizeImg = sizeof(uchar4) * numRowsImage * numColsImage;
int sizeFilter = sizeof(uchar4) * filterWidth * filterWidth;
hipMalloc(&d_red, sizeImg);
hipMalloc(&d_green, sizeImg);
hipMalloc(&d_blue, sizeImg);
hipMalloc(&d_filter, sizeFilter);
hipMemcpy(d_filter, h_filter, sizeFilter, hipMemcpyHostToDevice);
hipMemset(d_red, 0, sizeImg);
hipMemset(d_green, 0, sizeImg);
hipMemset(d_blue, 0, sizeImg);
}
// Crear el filtro se que va a aplicar (en CPU) y almacenar su tamaño...
void create_filter(float **d_filter, const float *mask, const int size)
{
float *h_filter = (float *) malloc(sizeof(float) * size);
if (!h_filter) {
std::cerr << "Error creating filter.." << strerror(errno) << '\n';
exit(1);
}
for (int i = 0; i < size; ++i) {
h_filter[i] = mask[i];
}
hipMalloc(d_filter, sizeof(float) * size);
hipMemcpy(*d_filter, h_filter, sizeof(float) * size, hipMemcpyHostToDevice);
}
void open_mpi_separate_channels(uchar4* const d_inputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_red,
unsigned char *d_green,
unsigned char *d_blue)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void open_mpi_box_filter(const unsigned char *channel,
unsigned char *filter_channel,
const size_t numRows,
const size_t numCols,
float* d_filter,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
box_filter<<<gridSize, blockSize>>>(channel, filter_channel, numRows, numCols, d_filter, filterWidth);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void open_mpi_recombine_channels(const unsigned char* d_redFiltered,
const unsigned char* d_greenFiltered,
const unsigned char* d_blueFiltered,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
void convolution(uchar4* const d_inputImageRGBA,
uchar4* const d_outputImageRGBA,
const size_t numRows,
const size_t numCols,
unsigned char *d_redFiltered,
unsigned char *d_greenFiltered,
unsigned char *d_blueFiltered,
const int filterWidth)
{
const dim3 blockSize(NTHREADS, NTHREADS, 1);
const dim3 gridSize((numCols - 1) / blockSize.x + 1, (numRows - 1) / blockSize.y + 1, 1);
separateChannels<<<gridSize, blockSize>>>(d_inputImageRGBA, numRows, numCols, d_red, d_green, d_blue);
// Call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
box_filter<<<gridSize, blockSize>>>(d_red, d_redFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_blue, d_blueFiltered, numRows, numCols, d_filter, filterWidth);
box_filter<<<gridSize, blockSize>>>(d_green, d_greenFiltered, numRows, numCols, d_filter, filterWidth);
// Again, call cudaDeviceSynchronize(), then call checkCudaErrors() immediately after
// launching your kernel to make sure that you didn't make any mistakes.
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
recombineChannels<<<gridSize, blockSize>>>(d_redFiltered, d_greenFiltered, d_blueFiltered, d_outputImageRGBA, numRows, numCols);
hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
}
//Free all the memory that we allocated
// TODO: make sure you free any arrays that you allocated
void cleanup() {
checkCudaErrors(hipFree(d_red));
checkCudaErrors(hipFree(d_green));
checkCudaErrors(hipFree(d_blue));
checkCudaErrors(hipFree(d_filter));
} | .text
.file "func.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z25__device_stub__box_filterPKhPhiiPKfi # -- Begin function _Z25__device_stub__box_filterPKhPhiiPKfi
.p2align 4, 0x90
.type _Z25__device_stub__box_filterPKhPhiiPKfi,@function
_Z25__device_stub__box_filterPKhPhiiPKfi: # @_Z25__device_stub__box_filterPKhPhiiPKfi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10box_filterPKhPhiiPKfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z25__device_stub__box_filterPKhPhiiPKfi, .Lfunc_end0-_Z25__device_stub__box_filterPKhPhiiPKfi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_ # -- Begin function _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.p2align 4, 0x90
.type _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_,@function
_Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_: # @_Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, .Lfunc_end1-_Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.cfi_endproc
# -- End function
.globl _Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii # -- Begin function _Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.p2align 4, 0x90
.type _Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii,@function
_Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii: # @_Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii, .Lfunc_end2-_Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.cfi_endproc
# -- End function
.globl _Z26allocateMemoryAndCopyToGPUmmPKfm # -- Begin function _Z26allocateMemoryAndCopyToGPUmmPKfm
.p2align 4, 0x90
.type _Z26allocateMemoryAndCopyToGPUmmPKfm,@function
_Z26allocateMemoryAndCopyToGPUmmPKfm: # @_Z26allocateMemoryAndCopyToGPUmmPKfm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rcx, %r14
movq %rdx, %r15
movq %rdi, %rbx
imull %esi, %ebx
shlq $34, %rbx
sarq $32, %rbx
movl $d_red, %edi
movq %rbx, %rsi
callq hipMalloc
movl $d_green, %edi
movq %rbx, %rsi
callq hipMalloc
movl $d_blue, %edi
movq %rbx, %rsi
callq hipMalloc
imull %r14d, %r14d
shlq $34, %r14
sarq $32, %r14
movl $d_filter, %edi
movq %r14, %rsi
callq hipMalloc
movq d_filter(%rip), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq d_red(%rip), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq d_green(%rip), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq d_blue(%rip), %rdi
xorl %esi, %esi
movq %rbx, %rdx
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp hipMemset # TAILCALL
.Lfunc_end3:
.size _Z26allocateMemoryAndCopyToGPUmmPKfm, .Lfunc_end3-_Z26allocateMemoryAndCopyToGPUmmPKfm
.cfi_endproc
# -- End function
.globl _Z13create_filterPPfPKfi # -- Begin function _Z13create_filterPPfPKfi
.p2align 4, 0x90
.type _Z13create_filterPPfPKfi,@function
_Z13create_filterPPfPKfi: # @_Z13create_filterPPfPKfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %r12
movq %rdi, %r14
movslq %edx, %rbx
shlq $2, %rbx
movq %rbx, %rdi
callq malloc
testq %rax, %rax
je .LBB4_4
# %bb.1: # %.preheader
movq %rax, %r15
testl %ebp, %ebp
jle .LBB4_3
# %bb.2: # %.lr.ph.preheader
movl %ebp, %edx
shlq $2, %rdx
movq %r15, %rdi
movq %r12, %rsi
callq memcpy@PLT
.LBB4_3: # %._crit_edge
movq %r14, %rdi
movq %rbx, %rsi
callq hipMalloc
movq (%r14), %rdi
movq %r15, %rsi
movq %rbx, %rdx
movl $1, %ecx
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp hipMemcpy # TAILCALL
.LBB4_4:
.cfi_def_cfa_offset 48
movl $_ZSt4cerr, %edi
movl $.L.str, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rbx
callq __errno_location
movl (%rax), %edi
callq strerror
movq %rbx, %rdi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl $10, %esi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c
movl $1, %edi
callq exit
.Lfunc_end4:
.size _Z13create_filterPPfPKfi, .Lfunc_end4-_Z13create_filterPPfPKfi
.cfi_endproc
# -- End function
.globl _Z26open_mpi_separate_channelsP15HIP_vector_typeIhLj4EEmmPhS2_S2_ # -- Begin function _Z26open_mpi_separate_channelsP15HIP_vector_typeIhLj4EEmmPhS2_S2_
.p2align 4, 0x90
.type _Z26open_mpi_separate_channelsP15HIP_vector_typeIhLj4EEmmPhS2_S2_,@function
_Z26open_mpi_separate_channelsP15HIP_vector_typeIhLj4EEmmPhS2_S2_: # @_Z26open_mpi_separate_channelsP15HIP_vector_typeIhLj4EEmmPhS2_S2_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
leaq -1(%rdx), %rax
shrq $5, %rax
incl %eax
movq %rsi, %rcx
shlq $27, %rcx
addq $-134217728, %rcx # imm = 0xF8000000
movabsq $-4294967296, %rdx # imm = 0xFFFFFFFF00000000
andq %rcx, %rdx
orq %rax, %rdx
movabsq $4294967296, %rdi # imm = 0x100000000
addq %rdx, %rdi
movabsq $137438953471, %rdx # imm = 0x1FFFFFFFFF
addq $33, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq %rbp, 88(%rsp)
movl %r13d, 12(%rsp)
movl %r12d, 8(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movq %rbx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
callq hipGetLastError
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $157, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z26open_mpi_separate_channelsP15HIP_vector_typeIhLj4EEmmPhS2_S2_, .Lfunc_end5-_Z26open_mpi_separate_channelsP15HIP_vector_typeIhLj4EEmmPhS2_S2_
.cfi_endproc
# -- End function
.section .text._Z5checkI10hipError_tEvT_PKcS3_i,"axG",@progbits,_Z5checkI10hipError_tEvT_PKcS3_i,comdat
.weak _Z5checkI10hipError_tEvT_PKcS3_i # -- Begin function _Z5checkI10hipError_tEvT_PKcS3_i
.p2align 4, 0x90
.type _Z5checkI10hipError_tEvT_PKcS3_i,@function
_Z5checkI10hipError_tEvT_PKcS3_i: # @_Z5checkI10hipError_tEvT_PKcS3_i
.cfi_startproc
# %bb.0:
testl %edi, %edi
jne .LBB6_2
# %bb.1:
retq
.LBB6_2:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edi, %ebp
movl $_ZSt4cerr, %edi
movq %rsi, %rbx
movl $.L.str.7, %esi
movl %ecx, %r14d
movq %rdx, %r15
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %r15, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.8, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movl %r14d, %esi
callq _ZNSolsEi
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl %ebp, %edi
callq hipGetErrorString
movl $_ZSt4cerr, %edi
movq %rax, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movl $.L.str.9, %esi
movq %rax, %rdi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
movq %rbx, %rsi
callq _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
movq %rax, %rdi
callq _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
movl $1, %edi
callq exit
.Lfunc_end6:
.size _Z5checkI10hipError_tEvT_PKcS3_i, .Lfunc_end6-_Z5checkI10hipError_tEvT_PKcS3_i
.cfi_endproc
# -- End function
.text
.globl _Z19open_mpi_box_filterPKhPhmmPfi # -- Begin function _Z19open_mpi_box_filterPKhPhmmPfi
.p2align 4, 0x90
.type _Z19open_mpi_box_filterPKhPhmmPfi,@function
_Z19open_mpi_box_filterPKhPhmmPfi: # @_Z19open_mpi_box_filterPKhPhmmPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
leaq -1(%rcx), %rax
shrq $5, %rax
incl %eax
movq %rdx, %rcx
shlq $27, %rcx
addq $-134217728, %rcx # imm = 0xF8000000
movabsq $-4294967296, %rdx # imm = 0xFFFFFFFF00000000
andq %rcx, %rdx
orq %rax, %rdx
movabsq $4294967296, %rdi # imm = 0x100000000
addq %rdx, %rdi
movabsq $137438953471, %rdx # imm = 0x1FFFFFFFFF
addq $33, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_2
# %bb.1:
movq %rbp, 88(%rsp)
movq %r13, 80(%rsp)
movl %r12d, 20(%rsp)
movl %r15d, 16(%rsp)
movq %r14, 72(%rsp)
movl %ebx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10box_filterPKhPhiiPKfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB7_2:
callq hipDeviceSynchronize
callq hipGetLastError
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $171, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end7:
.size _Z19open_mpi_box_filterPKhPhmmPfi, .Lfunc_end7-_Z19open_mpi_box_filterPKhPhmmPfi
.cfi_endproc
# -- End function
.globl _Z27open_mpi_recombine_channelsPKhS0_S0_P15HIP_vector_typeIhLj4EEmm # -- Begin function _Z27open_mpi_recombine_channelsPKhS0_S0_P15HIP_vector_typeIhLj4EEmm
.p2align 4, 0x90
.type _Z27open_mpi_recombine_channelsPKhS0_S0_P15HIP_vector_typeIhLj4EEmm,@function
_Z27open_mpi_recombine_channelsPKhS0_S0_P15HIP_vector_typeIhLj4EEmm: # @_Z27open_mpi_recombine_channelsPKhS0_S0_P15HIP_vector_typeIhLj4EEmm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, %rbx
movq %r8, %r14
movq %rcx, %r15
movq %rdx, %r12
movq %rsi, %r13
movq %rdi, %rbp
leaq -1(%r9), %rax
shrq $5, %rax
incl %eax
movq %r8, %rcx
shlq $27, %rcx
addq $-134217728, %rcx # imm = 0xF8000000
movabsq $-4294967296, %rdx # imm = 0xFFFFFFFF00000000
andq %rcx, %rdx
orq %rax, %rdx
movabsq $4294967296, %rdi # imm = 0x100000000
addq %rdx, %rdi
movabsq $137438953471, %rdx # imm = 0x1FFFFFFFFF
addq $33, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_2
# %bb.1:
movq %rbp, 88(%rsp)
movq %r13, 80(%rsp)
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_2:
callq hipDeviceSynchronize
callq hipGetLastError
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $185, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z27open_mpi_recombine_channelsPKhS0_S0_P15HIP_vector_typeIhLj4EEmm, .Lfunc_end8-_Z27open_mpi_recombine_channelsPKhS0_S0_P15HIP_vector_typeIhLj4EEmm
.cfi_endproc
# -- End function
.globl _Z11convolutionP15HIP_vector_typeIhLj4EES1_mmPhS2_S2_i # -- Begin function _Z11convolutionP15HIP_vector_typeIhLj4EES1_mmPhS2_S2_i
.p2align 4, 0x90
.type _Z11convolutionP15HIP_vector_typeIhLj4EES1_mmPhS2_S2_i,@function
_Z11convolutionP15HIP_vector_typeIhLj4EES1_mmPhS2_S2_i: # @_Z11convolutionP15HIP_vector_typeIhLj4EES1_mmPhS2_S2_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 152(%rsp) # 8-byte Spill
movq %r8, %r13
movq %rcx, %rbx
movq %rdx, %r14
movq %rsi, 160(%rsp) # 8-byte Spill
movq %rdi, %r15
movabsq $137438953504, %rbp # imm = 0x2000000020
leaq (%rcx,%rbp), %rax
addq $-33, %rax
shrq $5, %rax
incl %eax
movq %rdx, %rcx
shlq $27, %rcx
addq $-134217728, %rcx # imm = 0xF8000000
movabsq $-4294967296, %rdx # imm = 0xFFFFFFFF00000000
andq %rcx, %rdx
orq %rax, %rdx
movabsq $4294967296, %r12 # imm = 0x100000000
addq %rdx, %r12
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_2
# %bb.1:
movq d_red(%rip), %rax
movq d_green(%rip), %rcx
movq d_blue(%rip), %rdx
movq %r15, 88(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_2:
movl 232(%rsp), %r15d
callq hipDeviceSynchronize
callq hipGetLastError
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $204, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_4
# %bb.3:
movq d_red(%rip), %rax
movq d_filter(%rip), %rcx
movq %rax, 88(%rsp)
movq %r13, 80(%rsp)
movl %r14d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
movl %r15d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10box_filterPKhPhiiPKfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_4:
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_6
# %bb.5:
movq d_blue(%rip), %rax
movq d_filter(%rip), %rcx
movq %rax, 88(%rsp)
movq 224(%rsp), %rax
movq %rax, 80(%rsp)
movl %r14d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
movl %r15d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10box_filterPKhPhiiPKfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_6:
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_8
# %bb.7:
movq d_green(%rip), %rax
movq d_filter(%rip), %rcx
movq %rax, 88(%rsp)
movq 152(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movl %r14d, 16(%rsp)
movl %ebx, 12(%rsp)
movq %rcx, 72(%rsp)
movl %r15d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10box_filterPKhPhiiPKfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_8:
callq hipDeviceSynchronize
callq hipGetLastError
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $212, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
movq %r12, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_10
# %bb.9:
movq %r13, 88(%rsp)
movq 152(%rsp), %rax # 8-byte Reload
movq %rax, 80(%rsp)
movq 224(%rsp), %rax
movq %rax, 72(%rsp)
movq 160(%rsp), %rax # 8-byte Reload
movq %rax, 64(%rsp)
movl %r14d, 12(%rsp)
movl %ebx, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_10:
callq hipDeviceSynchronize
callq hipGetLastError
movl $.L.str.1, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $215, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z11convolutionP15HIP_vector_typeIhLj4EES1_mmPhS2_S2_i, .Lfunc_end9-_Z11convolutionP15HIP_vector_typeIhLj4EES1_mmPhS2_S2_i
.cfi_endproc
# -- End function
.globl _Z7cleanupv # -- Begin function _Z7cleanupv
.p2align 4, 0x90
.type _Z7cleanupv,@function
_Z7cleanupv: # @_Z7cleanupv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq d_red(%rip), %rdi
callq hipFree
movl $.L.str.3, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $221, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
movq d_green(%rip), %rdi
callq hipFree
movl $.L.str.4, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $222, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
movq d_blue(%rip), %rdi
callq hipFree
movl $.L.str.5, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $223, %ecx
callq _Z5checkI10hipError_tEvT_PKcS3_i
movq d_filter(%rip), %rdi
callq hipFree
movl $.L.str.6, %esi
movl $.L.str.2, %edx
movl %eax, %edi
movl $224, %ecx
popq %rax
.cfi_def_cfa_offset 8
jmp _Z5checkI10hipError_tEvT_PKcS3_i # TAILCALL
.Lfunc_end10:
.size _Z7cleanupv, .Lfunc_end10-_Z7cleanupv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB11_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB11_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10box_filterPKhPhiiPKfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $filtro, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $36, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end11:
.size __hip_module_ctor, .Lfunc_end11-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB12_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB12_2:
retq
.Lfunc_end12:
.size __hip_module_dtor, .Lfunc_end12-__hip_module_dtor
.cfi_endproc
# -- End function
.type filtro,@object # @filtro
.local filtro
.comm filtro,36,16
.type _Z10box_filterPKhPhiiPKfi,@object # @_Z10box_filterPKhPhiiPKfi
.section .rodata,"a",@progbits
.globl _Z10box_filterPKhPhiiPKfi
.p2align 3, 0x0
_Z10box_filterPKhPhiiPKfi:
.quad _Z25__device_stub__box_filterPKhPhiiPKfi
.size _Z10box_filterPKhPhiiPKfi, 8
.type _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_,@object # @_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.globl _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.p2align 3, 0x0
_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_:
.quad _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.size _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_, 8
.type _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii,@object # @_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.globl _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.p2align 3, 0x0
_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii:
.quad _Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.size _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii, 8
.type d_red,@object # @d_red
.bss
.globl d_red
.p2align 3, 0x0
d_red:
.quad 0
.size d_red, 8
.type d_green,@object # @d_green
.globl d_green
.p2align 3, 0x0
d_green:
.quad 0
.size d_green, 8
.type d_blue,@object # @d_blue
.globl d_blue
.p2align 3, 0x0
d_blue:
.quad 0
.size d_blue, 8
.type d_filter,@object # @d_filter
.globl d_filter
.p2align 3, 0x0
d_filter:
.quad 0
.size d_filter, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error creating filter.."
.size .L.str, 24
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipGetLastError()"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jgmatu/CUDAMPI/master/3/color-filter-cuda/func.hip"
.size .L.str.2, 108
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "hipFree(d_red)"
.size .L.str.3, 15
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipFree(d_green)"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipFree(d_blue)"
.size .L.str.5, 16
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "hipFree(d_filter)"
.size .L.str.6, 18
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "CUDA error at: "
.size .L.str.7, 16
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz ":"
.size .L.str.8, 2
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz " "
.size .L.str.9, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10box_filterPKhPhiiPKfi"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_"
.size .L__unnamed_2, 57
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii"
.size .L__unnamed_3, 58
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "filtro"
.size .L__unnamed_4, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__box_filterPKhPhiiPKfi
.addrsig_sym _Z31__device_stub__separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.addrsig_sym _Z32__device_stub__recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym filtro
.addrsig_sym _Z10box_filterPKhPhiiPKfi
.addrsig_sym _Z16separateChannelsPK15HIP_vector_typeIhLj4EEiiPhS3_S3_
.addrsig_sym _Z17recombineChannelsPKhS0_S0_P15HIP_vector_typeIhLj4EEii
.addrsig_sym d_red
.addrsig_sym d_green
.addrsig_sym d_blue
.addrsig_sym d_filter
.addrsig_sym _ZSt4cerr
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
const unsigned int N_FIB = 12;
const unsigned int N_BYTES_FIB = N_FIB * sizeof(unsigned int);
const unsigned int N_THREAD = N_FIB;
unsigned int N_ELEM, N_BYTES_ARR, N_BLOCKS;
__constant__ unsigned int fib_const[N_FIB];
__device__ static unsigned int fib_gmem[N_FIB];
/* Print array of integers, 20 elements per line */
void printArray(unsigned int * a, const char* name, const unsigned int n) {
printf("Printing %s array:", name);
for (int i = 0; i < n; i++) {
if (i%20 == 0) {
printf("\n");
}
printf("%5u", a[i]);
}
printf("\n");
}
__host__ cudaEvent_t get_time(void) {
cudaEvent_t time;
cudaEventCreate(&time);
cudaEventRecord(time);
return time;
}
// Generate random integer array between 0 and 9
void genRandArray(unsigned int *arr, const unsigned int n) {
for (int i = 0; i < n; i++) {
arr[i] = rand() % 10;
}
}
// Generate fibonacci sequence
void genFibSequence(unsigned int* arr, int nMax) {
arr[0] = 1;
arr[1] = 1;
for (int n=2; n < nMax; n++) {
arr[n] = arr[n-1] + arr[n-2];
}
}
__global__ void calc_w_const(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_const[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_gmem(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_gmem[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_shared(unsigned int * const inArr, unsigned int *outArr,
unsigned int const *inFib, unsigned int const N) {
__shared__ unsigned int tmpSum[N_FIB]; // shared memory, size = nThreads
const unsigned int tid = threadIdx.x;
tmpSum[tid] = inFib[tid]; // initialize to same as fib sequence
__syncthreads();
if (tid < 2) { // add up all even or odd elements
for (int s=tid+2; s<blockDim.x; s+=2) { // start from elem 2 or 3
tmpSum[tid] += tmpSum[s];
}
}
__syncthreads();
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = inArr[idx] * tmpSum[idx%2]; // perform multiplication
}
}
void validate_output(unsigned int *o1, unsigned int *o2, unsigned int *o3) {
bool div = false;
for (unsigned int n=0; n<N_ELEM && !div ; n++) {
if ( (o1[n] != o2[n]) || (o2[n] != o3[n]) ) {
div = true;
printf("idx=%u: %u, %u, %u\n", n, o1[n], o2[n], o3[n]);
}
}
if (!div) {
printf("Results for all three runs are the identical!\n");
} else {
printf("Some results are different...\n");
}
}
int main(int argc, char* argv[]) {
if (argc != 2) { // expect 1 cmd line args: [arraySizeExponent]
printf("Usage: %s [arraySizeExponent].\n", argv[0]);
return EXIT_FAILURE;
}
unsigned int N_ELEM = 2 << atoi(argv[1]); // n input array
unsigned int N_BYTES_ARR = N_ELEM * sizeof(unsigned int);
unsigned int N_BLOCKS = (N_ELEM + N_THREAD-1) / N_THREAD;
printf("Running with %u elements in input array...\n", N_ELEM);
unsigned int *h_in, *h_out1, *h_out2, *h_out3, *h_fib;
unsigned int *d_in, *d_out, *d_fib;
h_fib = (unsigned int*) malloc(N_BYTES_FIB); // initialize fibonacci
genFibSequence(h_fib, N_FIB); // generate fibonacci sequence
h_in = (unsigned int*) malloc(N_BYTES_ARR); // allocate input
genRandArray(h_in, N_ELEM); // generate random input array
h_out1 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 1
h_out2 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 2
h_out3 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 3
cudaMallocHost((void**)&d_in, N_BYTES_ARR); // allocate input
cudaMallocHost((void**)&d_out, N_BYTES_ARR); // allocate output
cudaMallocHost((void**)&d_fib, N_BYTES_FIB); // allocate output
cudaMemcpy(d_in, h_in, N_BYTES_ARR, cudaMemcpyHostToDevice); // copy 2 dev
// Timing using constant memory to store Fibonacci sequence
cudaEvent_t start1 = get_time(); // start time
cudaMemcpyToSymbol(fib_const, h_fib, N_BYTES_FIB); // copy to constant
calc_w_const<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
cudaMemcpy( h_out1, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop1 = get_time(); // stop time
cudaEventSynchronize(stop1);
// Timing using global memory to store Fibonacci sequence
cudaEvent_t start2 = get_time(); // start time
cudaMemcpyToSymbol(fib_gmem, h_fib, N_BYTES_FIB); // copy to global mem
calc_w_gmem<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
cudaMemcpy( h_out2, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop2 = get_time(); // stop time
cudaEventSynchronize(stop2);
// Timing using shared memory to smartly calculate
cudaEvent_t start3 = get_time(); // start time
cudaMemcpy(d_fib, h_fib, N_BYTES_FIB, cudaMemcpyHostToDevice); //copy 2 dev
calc_w_shared<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, d_fib, N_ELEM);
cudaMemcpy(h_out3, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop3 = get_time(); // stop time
cudaEventSynchronize(stop3);
// Checking that the results of the three runs are identical
validate_output(h_out1, h_out2, h_out3);
// Free memory
cudaFree(d_in); cudaFree(d_out); cudaFree(d_fib);
free(h_in); free(h_out1); free(h_out2); free(h_out3); free(h_fib);
// Printing time benchmarks
float tmp = 0;
cudaEventElapsedTime(&tmp, start1, stop1);
printf("\tUsing constant memory: elapsed %.3f ms\n", tmp);
cudaEventElapsedTime(&tmp, start2, stop2);
printf("\tUsing global memory: elapsed %.3f ms\n", tmp);
cudaEventElapsedTime(&tmp, start3, stop3);
printf("\tUsing shared memory: elapsed %.3f ms\n", tmp);
printf("\n");
} | code for sm_80
Function : _Z13calc_w_sharedPjS_PKjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R7, R9, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x001fcc00078e0009 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fe20003f06070 */
/*0070*/ BSSY B0, 0x180 ; /* 0x0000010000007945 */
/* 0x000fe40003800000 */
/*0080*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ @P0 BRA 0x170 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R7, 0x2, RZ ; /* 0x0000000207007810 */
/* 0x001fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*00d0*/ @P0 BRA 0x170 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LDS R2, [R7.X4] ; /* 0x0000000007027984 */
/* 0x0000620000004800 */
/*00f0*/ SHF.L.U32 R3, R0, 0x2, RZ ; /* 0x0000000200037819 */
/* 0x000fca00000006ff */
/*0100*/ LDS R5, [R3] ; /* 0x0000000003057984 */
/* 0x0004e20000000800 */
/*0110*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe40003f06070 */
/*0130*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x004fe20007ffe0ff */
/*0140*/ IMAD.IADD R2, R5, 0x1, R2 ; /* 0x0000000105027824 */
/* 0x00afca00078e0202 */
/*0150*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0003ea0000004800 */
/*0160*/ @!P0 BRA 0x100 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0180*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ IMAD R4, R4, c[0x0][0x0], R7 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0207 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.WIDE.U32 R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x002fcc00078e0009 */
/*01e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ SHF.L.U32 R0, R4.reuse, 0x2, RZ ; /* 0x0000000204007819 */
/* 0x040fe200000006ff */
/*0200*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0009 */
/*0210*/ LOP3.LUT R0, R0, 0x4, RZ, 0xc0, !PT ; /* 0x0000000400007812 */
/* 0x000fcc00078ec0ff */
/*0220*/ LDS R0, [R0] ; /* 0x0000000000007984 */
/* 0x000ea40000000800 */
/*0230*/ IMAD R7, R0, R3, RZ ; /* 0x0000000300077224 */
/* 0x004fca00078e02ff */
/*0240*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11calc_w_gmemPjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LOP3.LUT R6, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100067812 */
/* 0x040fe200078ec0ff */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0005 */
/*00b0*/ IMAD.WIDE.U32 R4, R6, R5, c[0x4][0x0] ; /* 0x0100000006047625 */
/* 0x000fe200078e0005 */
/*00c0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c101904 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00e0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*00f0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fcc0000000f00 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0022a2000c1e1900 */
/*0110*/ IADD3 R6, R6, 0x2, RZ ; /* 0x0000000206067810 */
/* 0x000fe40007ffe0ff */
/*0120*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007f3e0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f06070 */
/*0140*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x002fe20000ffe4ff */
/*0150*/ IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104077824 */
/* 0x004fca00078e0207 */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003ea000c101904 */
/*0170*/ @!P0 BRA 0xf0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*01a0*/ LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f14ff */
/*01b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x006fca00078e02ff */
/*01d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12calc_w_constPjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fe200078ec0ff */
/*0070*/ BSSY B0, 0x1b0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2.reuse, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x040fe20003f06070 */
/*00a0*/ IMAD.SHL.U32 R8, R2.reuse, 0x4, RZ ; /* 0x0000000402087824 */
/* 0x040fe200078e00ff */
/*00b0*/ IADD3 R3, -R2, 0xc, RZ ; /* 0x0000000c02037810 */
/* 0x000fc80007ffe1ff */
/*00c0*/ ISETP.LE.U32.OR P1, PT, R3, 0x6, P0 ; /* 0x000000060300780c */
/* 0x000fe40000723470 */
/*00d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*00e0*/ @P1 BRA 0x1a0 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*00f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0100*/ LDC R4, c[0x3][R8] ; /* 0x00c0000008047b82 */
/* 0x0000620000000800 */
/*0110*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.U32.AND P1, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fc60003f26070 */
/*0130*/ LDC R3, c[0x3][R8+0x8] ; /* 0x00c0020008037b82 */
/* 0x0000700000000800 */
/*0140*/ LDC R6, c[0x3][R8+0x10] ; /* 0x00c0040008067b82 */
/* 0x0000b00000000800 */
/*0150*/ LDC R5, c[0x3][R8+0x18] ; /* 0x00c0060008057b82 */
/* 0x0000a40000000800 */
/*0160*/ IADD3 R8, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x001fc40007ffe0ff */
/*0170*/ IADD3 R3, R3, R7, R4 ; /* 0x0000000703037210 */
/* 0x002fc80007ffe004 */
/*0180*/ IADD3 R7, R5, R3, R6 ; /* 0x0000000305077210 */
/* 0x004fe20007ffe006 */
/*0190*/ @!P1 BRA 0x100 ; /* 0xffffff6000009947 */
/* 0x000fea000383ffff */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R2.reuse, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x040fe20003f26070 */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*01d0*/ IADD3 R3, -R2, 0xc, RZ ; /* 0x0000000c02037810 */
/* 0x000fe20007ffe1ff */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01f0*/ LEA R4, P2, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fe400078410ff */
/*0200*/ ISETP.LE.U32.OR P1, PT, R3, 0x2, P1 ; /* 0x000000020300780c */
/* 0x000fda0000f23470 */
/*0210*/ @!P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000981c */
/* 0x000fe20003f0e170 */
/*0220*/ @!P1 LDC R3, c[0x3][R8+0x8] ; /* 0x00c0020008039b82 */
/* 0x0000620000000800 */
/*0230*/ @!P1 IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402029810 */
/* 0x000fd60007ffe0ff */
/*0240*/ ISETP.LT.U32.OR P0, PT, R2, 0xc, P0 ; /* 0x0000000c0200780c */
/* 0x000fe40000701470 */
/*0250*/ @!P1 LDC R2, c[0x3][R8] ; /* 0x00c0000008029b82 */
/* 0x0000640000000800 */
/*0260*/ @!P1 IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008089810 */
/* 0x001fd20007ffe0ff */
/*0270*/ @P0 LDC R6, c[0x3][R8] ; /* 0x00c0000008060b82 */
/* 0x000e220000000800 */
/*0280*/ @!P1 IADD3 R7, R3, R7, R2 ; /* 0x0000000703079210 */
/* 0x002fe20007ffe002 */
/*0290*/ IMAD.WIDE.U32 R2, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0005 */
/*02a0*/ LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x2, P2 ; /* 0x0000590000057a11 */
/* 0x000fc800010f14ff */
/*02b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*02c0*/ @P0 IMAD.IADD R7, R7, 0x1, R6 ; /* 0x0000000107070824 */
/* 0x001fca00078e0206 */
/*02d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*02e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD R9, R4, R7, RZ ; /* 0x0000000704097224 */
/* 0x004fca00078e02ff */
/*0300*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
const unsigned int N_FIB = 12;
const unsigned int N_BYTES_FIB = N_FIB * sizeof(unsigned int);
const unsigned int N_THREAD = N_FIB;
unsigned int N_ELEM, N_BYTES_ARR, N_BLOCKS;
__constant__ unsigned int fib_const[N_FIB];
__device__ static unsigned int fib_gmem[N_FIB];
/* Print array of integers, 20 elements per line */
void printArray(unsigned int * a, const char* name, const unsigned int n) {
printf("Printing %s array:", name);
for (int i = 0; i < n; i++) {
if (i%20 == 0) {
printf("\n");
}
printf("%5u", a[i]);
}
printf("\n");
}
__host__ cudaEvent_t get_time(void) {
cudaEvent_t time;
cudaEventCreate(&time);
cudaEventRecord(time);
return time;
}
// Generate random integer array between 0 and 9
void genRandArray(unsigned int *arr, const unsigned int n) {
for (int i = 0; i < n; i++) {
arr[i] = rand() % 10;
}
}
// Generate fibonacci sequence
void genFibSequence(unsigned int* arr, int nMax) {
arr[0] = 1;
arr[1] = 1;
for (int n=2; n < nMax; n++) {
arr[n] = arr[n-1] + arr[n-2];
}
}
__global__ void calc_w_const(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_const[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_gmem(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_gmem[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_shared(unsigned int * const inArr, unsigned int *outArr,
unsigned int const *inFib, unsigned int const N) {
__shared__ unsigned int tmpSum[N_FIB]; // shared memory, size = nThreads
const unsigned int tid = threadIdx.x;
tmpSum[tid] = inFib[tid]; // initialize to same as fib sequence
__syncthreads();
if (tid < 2) { // add up all even or odd elements
for (int s=tid+2; s<blockDim.x; s+=2) { // start from elem 2 or 3
tmpSum[tid] += tmpSum[s];
}
}
__syncthreads();
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = inArr[idx] * tmpSum[idx%2]; // perform multiplication
}
}
void validate_output(unsigned int *o1, unsigned int *o2, unsigned int *o3) {
bool div = false;
for (unsigned int n=0; n<N_ELEM && !div ; n++) {
if ( (o1[n] != o2[n]) || (o2[n] != o3[n]) ) {
div = true;
printf("idx=%u: %u, %u, %u\n", n, o1[n], o2[n], o3[n]);
}
}
if (!div) {
printf("Results for all three runs are the identical!\n");
} else {
printf("Some results are different...\n");
}
}
int main(int argc, char* argv[]) {
if (argc != 2) { // expect 1 cmd line args: [arraySizeExponent]
printf("Usage: %s [arraySizeExponent].\n", argv[0]);
return EXIT_FAILURE;
}
unsigned int N_ELEM = 2 << atoi(argv[1]); // n input array
unsigned int N_BYTES_ARR = N_ELEM * sizeof(unsigned int);
unsigned int N_BLOCKS = (N_ELEM + N_THREAD-1) / N_THREAD;
printf("Running with %u elements in input array...\n", N_ELEM);
unsigned int *h_in, *h_out1, *h_out2, *h_out3, *h_fib;
unsigned int *d_in, *d_out, *d_fib;
h_fib = (unsigned int*) malloc(N_BYTES_FIB); // initialize fibonacci
genFibSequence(h_fib, N_FIB); // generate fibonacci sequence
h_in = (unsigned int*) malloc(N_BYTES_ARR); // allocate input
genRandArray(h_in, N_ELEM); // generate random input array
h_out1 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 1
h_out2 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 2
h_out3 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 3
cudaMallocHost((void**)&d_in, N_BYTES_ARR); // allocate input
cudaMallocHost((void**)&d_out, N_BYTES_ARR); // allocate output
cudaMallocHost((void**)&d_fib, N_BYTES_FIB); // allocate output
cudaMemcpy(d_in, h_in, N_BYTES_ARR, cudaMemcpyHostToDevice); // copy 2 dev
// Timing using constant memory to store Fibonacci sequence
cudaEvent_t start1 = get_time(); // start time
cudaMemcpyToSymbol(fib_const, h_fib, N_BYTES_FIB); // copy to constant
calc_w_const<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
cudaMemcpy( h_out1, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop1 = get_time(); // stop time
cudaEventSynchronize(stop1);
// Timing using global memory to store Fibonacci sequence
cudaEvent_t start2 = get_time(); // start time
cudaMemcpyToSymbol(fib_gmem, h_fib, N_BYTES_FIB); // copy to global mem
calc_w_gmem<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
cudaMemcpy( h_out2, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop2 = get_time(); // stop time
cudaEventSynchronize(stop2);
// Timing using shared memory to smartly calculate
cudaEvent_t start3 = get_time(); // start time
cudaMemcpy(d_fib, h_fib, N_BYTES_FIB, cudaMemcpyHostToDevice); //copy 2 dev
calc_w_shared<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, d_fib, N_ELEM);
cudaMemcpy(h_out3, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop3 = get_time(); // stop time
cudaEventSynchronize(stop3);
// Checking that the results of the three runs are identical
validate_output(h_out1, h_out2, h_out3);
// Free memory
cudaFree(d_in); cudaFree(d_out); cudaFree(d_fib);
free(h_in); free(h_out1); free(h_out2); free(h_out3); free(h_fib);
// Printing time benchmarks
float tmp = 0;
cudaEventElapsedTime(&tmp, start1, stop1);
printf("\tUsing constant memory: elapsed %.3f ms\n", tmp);
cudaEventElapsedTime(&tmp, start2, stop2);
printf("\tUsing global memory: elapsed %.3f ms\n", tmp);
cudaEventElapsedTime(&tmp, start3, stop3);
printf("\tUsing shared memory: elapsed %.3f ms\n", tmp);
printf("\n");
} | .file "tmpxft_000c4e3d_00000000-6_const_v_shared_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Printing %s array:"
.LC1:
.string "\n"
.LC2:
.string "%5u"
.text
.globl _Z10printArrayPjPKcj
.type _Z10printArrayPjPKcj, @function
_Z10printArrayPjPKcj:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %edx, %ebp
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
je .L4
movl %ebp, %ebp
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
jmp .L6
.L5:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
je .L4
.L6:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
sall $2, %eax
cmpl %ebx, %eax
jne .L5
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10printArrayPjPKcj, .-_Z10printArrayPjPKcj
.globl _Z8get_timev
.type _Z8get_timev, @function
_Z8get_timev:
.LFB2058:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L12
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8get_timev, .-_Z8get_timev
.globl _Z12genRandArrayPjj
.type _Z12genRandArrayPjj, @function
_Z12genRandArrayPjj:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
je .L18
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %esi
leaq (%rdi,%rsi,4), %rbp
.L15:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z12genRandArrayPjj, .-_Z12genRandArrayPjj
.globl _Z14genFibSequencePji
.type _Z14genFibSequencePji, @function
_Z14genFibSequencePji:
.LFB2060:
.cfi_startproc
endbr64
movl $1, (%rdi)
movl $1, 4(%rdi)
cmpl $2, %esi
jle .L21
movq %rdi, %rax
leal -3(%rsi), %edx
leaq 4(%rdi,%rdx,4), %rcx
.L23:
movl (%rax), %edx
addl 4(%rax), %edx
movl %edx, 8(%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L23
.L21:
ret
.cfi_endproc
.LFE2060:
.size _Z14genFibSequencePji, .-_Z14genFibSequencePji
.section .rodata.str1.1
.LC3:
.string "idx=%u: %u, %u, %u\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Some results are different...\n"
.align 8
.LC5:
.string "Results for all three runs are the identical!\n"
.text
.globl _Z15validate_outputPjS_S_
.type _Z15validate_outputPjS_S_, @function
_Z15validate_outputPjS_S_:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl N_ELEM(%rip), %r9d
testl %r9d, %r9d
je .L26
movq %rdx, %rax
movl $0, %edx
jmp .L30
.L28:
addq $1, %rdx
cmpl %r9d, %edx
jnb .L26
.L30:
movl (%rdi,%rdx,4), %ecx
movl (%rsi,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .L27
cmpl (%rax,%rdx,4), %r8d
je .L28
.L27:
movl (%rax,%rdx,4), %r9d
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L25:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.cfi_endproc
.LFE2061:
.size _Z15validate_outputPjS_S_, .-_Z15validate_outputPjS_S_
.globl _Z35__device_stub__Z12calc_w_constPjS_jPjS_j
.type _Z35__device_stub__Z12calc_w_constPjS_jPjS_j, @function
_Z35__device_stub__Z12calc_w_constPjS_jPjS_j:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12calc_w_constPjS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z35__device_stub__Z12calc_w_constPjS_jPjS_j, .-_Z35__device_stub__Z12calc_w_constPjS_jPjS_j
.globl _Z12calc_w_constPjS_j
.type _Z12calc_w_constPjS_j, @function
_Z12calc_w_constPjS_j:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12calc_w_constPjS_jPjS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12calc_w_constPjS_j, .-_Z12calc_w_constPjS_j
.globl _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j
.type _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j, @function
_Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11calc_w_gmemPjS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j, .-_Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j
.globl _Z11calc_w_gmemPjS_j
.type _Z11calc_w_gmemPjS_j, @function
_Z11calc_w_gmemPjS_j:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z11calc_w_gmemPjS_j, .-_Z11calc_w_gmemPjS_j
.globl _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj
.type _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj, @function
_Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13calc_w_sharedPjS_PKjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj, .-_Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj
.globl _Z13calc_w_sharedPjS_PKjj
.type _Z13calc_w_sharedPjS_PKjj, @function
_Z13calc_w_sharedPjS_PKjj:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z13calc_w_sharedPjS_PKjj, .-_Z13calc_w_sharedPjS_PKjj
.section .rodata.str1.8
.align 8
.LC6:
.string "Usage: %s [arraySizeExponent].\n"
.align 8
.LC7:
.string "Running with %u elements in input array...\n"
.align 8
.LC9:
.string "\tUsing constant memory: elapsed %.3f ms\n"
.align 8
.LC10:
.string "\tUsing global memory: elapsed %.3f ms\n"
.align 8
.LC11:
.string "\tUsing shared memory: elapsed %.3f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L58
movq (%rsi), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L57:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L65
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $2, %r12d
movl %eax, %ecx
sall %cl, %r12d
leal 11(%r12), %eax
movl $12, %ecx
movl $0, %edx
divl %ecx
movl %eax, %r13d
movl %r12d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $48, %edi
call malloc@PLT
movq %rax, %rbp
movl $12, %esi
movq %rax, %rdi
call _Z14genFibSequencePji
leal 0(,%r12,4), %ebx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movl %r12d, %esi
movq %rax, %rdi
call _Z12genRandArrayPjj
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq 88(%rsp), %rdi
movl $48, %esi
call cudaMallocHost@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, 24(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $48, %edx
movq %rbp, %rsi
leaq _ZL9fib_const(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $12, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L60:
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, 32(%rsp)
movq %rax, %rdi
call cudaEventSynchronize@PLT
call _Z8get_timev
movq %rax, 40(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $48, %edx
movq %rbp, %rsi
leaq _ZL8fib_gmem(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $12, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L61:
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, 48(%rsp)
movq %rax, %rdi
call cudaEventSynchronize@PLT
call _Z8get_timev
movq %rax, 56(%rsp)
movl $1, %ecx
movl $48, %edx
movq %rbp, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $12, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L62:
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, %rbx
movq %rax, %rdi
call cudaEventSynchronize@PLT
movq %r15, %rdx
movq 16(%rsp), %r12
movq %r12, %rsi
movq 8(%rsp), %r13
movq %r13, %rdi
call _Z15validate_outputPjS_S_
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0x00000000, 108(%rsp)
leaq 108(%rsp), %rbp
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 108(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 108(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 108(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L57
.L66:
movl %r12d, %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z35__device_stub__Z12calc_w_constPjS_jPjS_j
jmp .L60
.L67:
movl %r12d, %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j
jmp .L61
.L68:
movl %r12d, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj
jmp .L62
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z13calc_w_sharedPjS_PKjj"
.LC13:
.string "_Z11calc_w_gmemPjS_j"
.LC14:
.string "_Z12calc_w_constPjS_j"
.LC15:
.string "fib_const"
.LC16:
.string "fib_gmem"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z13calc_w_sharedPjS_PKjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calc_w_gmemPjS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12calc_w_constPjS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $48, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9fib_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $48, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8fib_gmem(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8fib_gmem
.comm _ZL8fib_gmem,48,32
.local _ZL9fib_const
.comm _ZL9fib_const,48,32
.globl N_BLOCKS
.bss
.align 4
.type N_BLOCKS, @object
.size N_BLOCKS, 4
N_BLOCKS:
.zero 4
.globl N_BYTES_ARR
.align 4
.type N_BYTES_ARR, @object
.size N_BYTES_ARR, 4
N_BYTES_ARR:
.zero 4
.globl N_ELEM
.align 4
.type N_ELEM, @object
.size N_ELEM, 4
N_ELEM:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
const unsigned int N_FIB = 12;
const unsigned int N_BYTES_FIB = N_FIB * sizeof(unsigned int);
const unsigned int N_THREAD = N_FIB;
unsigned int N_ELEM, N_BYTES_ARR, N_BLOCKS;
__constant__ unsigned int fib_const[N_FIB];
__device__ static unsigned int fib_gmem[N_FIB];
/* Print array of integers, 20 elements per line */
void printArray(unsigned int * a, const char* name, const unsigned int n) {
printf("Printing %s array:", name);
for (int i = 0; i < n; i++) {
if (i%20 == 0) {
printf("\n");
}
printf("%5u", a[i]);
}
printf("\n");
}
__host__ cudaEvent_t get_time(void) {
cudaEvent_t time;
cudaEventCreate(&time);
cudaEventRecord(time);
return time;
}
// Generate random integer array between 0 and 9
void genRandArray(unsigned int *arr, const unsigned int n) {
for (int i = 0; i < n; i++) {
arr[i] = rand() % 10;
}
}
// Generate fibonacci sequence
void genFibSequence(unsigned int* arr, int nMax) {
arr[0] = 1;
arr[1] = 1;
for (int n=2; n < nMax; n++) {
arr[n] = arr[n-1] + arr[n-2];
}
}
__global__ void calc_w_const(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_const[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_gmem(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_gmem[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_shared(unsigned int * const inArr, unsigned int *outArr,
unsigned int const *inFib, unsigned int const N) {
__shared__ unsigned int tmpSum[N_FIB]; // shared memory, size = nThreads
const unsigned int tid = threadIdx.x;
tmpSum[tid] = inFib[tid]; // initialize to same as fib sequence
__syncthreads();
if (tid < 2) { // add up all even or odd elements
for (int s=tid+2; s<blockDim.x; s+=2) { // start from elem 2 or 3
tmpSum[tid] += tmpSum[s];
}
}
__syncthreads();
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = inArr[idx] * tmpSum[idx%2]; // perform multiplication
}
}
void validate_output(unsigned int *o1, unsigned int *o2, unsigned int *o3) {
bool div = false;
for (unsigned int n=0; n<N_ELEM && !div ; n++) {
if ( (o1[n] != o2[n]) || (o2[n] != o3[n]) ) {
div = true;
printf("idx=%u: %u, %u, %u\n", n, o1[n], o2[n], o3[n]);
}
}
if (!div) {
printf("Results for all three runs are the identical!\n");
} else {
printf("Some results are different...\n");
}
}
int main(int argc, char* argv[]) {
if (argc != 2) { // expect 1 cmd line args: [arraySizeExponent]
printf("Usage: %s [arraySizeExponent].\n", argv[0]);
return EXIT_FAILURE;
}
unsigned int N_ELEM = 2 << atoi(argv[1]); // n input array
unsigned int N_BYTES_ARR = N_ELEM * sizeof(unsigned int);
unsigned int N_BLOCKS = (N_ELEM + N_THREAD-1) / N_THREAD;
printf("Running with %u elements in input array...\n", N_ELEM);
unsigned int *h_in, *h_out1, *h_out2, *h_out3, *h_fib;
unsigned int *d_in, *d_out, *d_fib;
h_fib = (unsigned int*) malloc(N_BYTES_FIB); // initialize fibonacci
genFibSequence(h_fib, N_FIB); // generate fibonacci sequence
h_in = (unsigned int*) malloc(N_BYTES_ARR); // allocate input
genRandArray(h_in, N_ELEM); // generate random input array
h_out1 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 1
h_out2 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 2
h_out3 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 3
cudaMallocHost((void**)&d_in, N_BYTES_ARR); // allocate input
cudaMallocHost((void**)&d_out, N_BYTES_ARR); // allocate output
cudaMallocHost((void**)&d_fib, N_BYTES_FIB); // allocate output
cudaMemcpy(d_in, h_in, N_BYTES_ARR, cudaMemcpyHostToDevice); // copy 2 dev
// Timing using constant memory to store Fibonacci sequence
cudaEvent_t start1 = get_time(); // start time
cudaMemcpyToSymbol(fib_const, h_fib, N_BYTES_FIB); // copy to constant
calc_w_const<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
cudaMemcpy( h_out1, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop1 = get_time(); // stop time
cudaEventSynchronize(stop1);
// Timing using global memory to store Fibonacci sequence
cudaEvent_t start2 = get_time(); // start time
cudaMemcpyToSymbol(fib_gmem, h_fib, N_BYTES_FIB); // copy to global mem
calc_w_gmem<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
cudaMemcpy( h_out2, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop2 = get_time(); // stop time
cudaEventSynchronize(stop2);
// Timing using shared memory to smartly calculate
cudaEvent_t start3 = get_time(); // start time
cudaMemcpy(d_fib, h_fib, N_BYTES_FIB, cudaMemcpyHostToDevice); //copy 2 dev
calc_w_shared<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, d_fib, N_ELEM);
cudaMemcpy(h_out3, d_out, N_BYTES_ARR, cudaMemcpyDeviceToHost );
cudaEvent_t stop3 = get_time(); // stop time
cudaEventSynchronize(stop3);
// Checking that the results of the three runs are identical
validate_output(h_out1, h_out2, h_out3);
// Free memory
cudaFree(d_in); cudaFree(d_out); cudaFree(d_fib);
free(h_in); free(h_out1); free(h_out2); free(h_out3); free(h_fib);
// Printing time benchmarks
float tmp = 0;
cudaEventElapsedTime(&tmp, start1, stop1);
printf("\tUsing constant memory: elapsed %.3f ms\n", tmp);
cudaEventElapsedTime(&tmp, start2, stop2);
printf("\tUsing global memory: elapsed %.3f ms\n", tmp);
cudaEventElapsedTime(&tmp, start3, stop3);
printf("\tUsing shared memory: elapsed %.3f ms\n", tmp);
printf("\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
const unsigned int N_FIB = 12;
const unsigned int N_BYTES_FIB = N_FIB * sizeof(unsigned int);
const unsigned int N_THREAD = N_FIB;
unsigned int N_ELEM, N_BYTES_ARR, N_BLOCKS;
__constant__ unsigned int fib_const[N_FIB];
__device__ static unsigned int fib_gmem[N_FIB];
/* Print array of integers, 20 elements per line */
void printArray(unsigned int * a, const char* name, const unsigned int n) {
printf("Printing %s array:", name);
for (int i = 0; i < n; i++) {
if (i%20 == 0) {
printf("\n");
}
printf("%5u", a[i]);
}
printf("\n");
}
__host__ hipEvent_t get_time(void) {
hipEvent_t time;
hipEventCreate(&time);
hipEventRecord(time);
return time;
}
// Generate random integer array between 0 and 9
void genRandArray(unsigned int *arr, const unsigned int n) {
for (int i = 0; i < n; i++) {
arr[i] = rand() % 10;
}
}
// Generate fibonacci sequence
void genFibSequence(unsigned int* arr, int nMax) {
arr[0] = 1;
arr[1] = 1;
for (int n=2; n < nMax; n++) {
arr[n] = arr[n-1] + arr[n-2];
}
}
__global__ void calc_w_const(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_const[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_gmem(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_gmem[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_shared(unsigned int * const inArr, unsigned int *outArr,
unsigned int const *inFib, unsigned int const N) {
__shared__ unsigned int tmpSum[N_FIB]; // shared memory, size = nThreads
const unsigned int tid = threadIdx.x;
tmpSum[tid] = inFib[tid]; // initialize to same as fib sequence
__syncthreads();
if (tid < 2) { // add up all even or odd elements
for (int s=tid+2; s<blockDim.x; s+=2) { // start from elem 2 or 3
tmpSum[tid] += tmpSum[s];
}
}
__syncthreads();
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = inArr[idx] * tmpSum[idx%2]; // perform multiplication
}
}
void validate_output(unsigned int *o1, unsigned int *o2, unsigned int *o3) {
bool div = false;
for (unsigned int n=0; n<N_ELEM && !div ; n++) {
if ( (o1[n] != o2[n]) || (o2[n] != o3[n]) ) {
div = true;
printf("idx=%u: %u, %u, %u\n", n, o1[n], o2[n], o3[n]);
}
}
if (!div) {
printf("Results for all three runs are the identical!\n");
} else {
printf("Some results are different...\n");
}
}
int main(int argc, char* argv[]) {
if (argc != 2) { // expect 1 cmd line args: [arraySizeExponent]
printf("Usage: %s [arraySizeExponent].\n", argv[0]);
return EXIT_FAILURE;
}
unsigned int N_ELEM = 2 << atoi(argv[1]); // n input array
unsigned int N_BYTES_ARR = N_ELEM * sizeof(unsigned int);
unsigned int N_BLOCKS = (N_ELEM + N_THREAD-1) / N_THREAD;
printf("Running with %u elements in input array...\n", N_ELEM);
unsigned int *h_in, *h_out1, *h_out2, *h_out3, *h_fib;
unsigned int *d_in, *d_out, *d_fib;
h_fib = (unsigned int*) malloc(N_BYTES_FIB); // initialize fibonacci
genFibSequence(h_fib, N_FIB); // generate fibonacci sequence
h_in = (unsigned int*) malloc(N_BYTES_ARR); // allocate input
genRandArray(h_in, N_ELEM); // generate random input array
h_out1 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 1
h_out2 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 2
h_out3 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 3
hipHostMalloc((void**)&d_in, N_BYTES_ARR, hipHostMallocDefault); // allocate input
hipHostMalloc((void**)&d_out, N_BYTES_ARR, hipHostMallocDefault); // allocate output
hipHostMalloc((void**)&d_fib, N_BYTES_FIB, hipHostMallocDefault); // allocate output
hipMemcpy(d_in, h_in, N_BYTES_ARR, hipMemcpyHostToDevice); // copy 2 dev
// Timing using constant memory to store Fibonacci sequence
hipEvent_t start1 = get_time(); // start time
hipMemcpyToSymbol(HIP_SYMBOL(fib_const), h_fib, N_BYTES_FIB); // copy to constant
calc_w_const<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
hipMemcpy( h_out1, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop1 = get_time(); // stop time
hipEventSynchronize(stop1);
// Timing using global memory to store Fibonacci sequence
hipEvent_t start2 = get_time(); // start time
hipMemcpyToSymbol(HIP_SYMBOL(fib_gmem), h_fib, N_BYTES_FIB); // copy to global mem
calc_w_gmem<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
hipMemcpy( h_out2, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop2 = get_time(); // stop time
hipEventSynchronize(stop2);
// Timing using shared memory to smartly calculate
hipEvent_t start3 = get_time(); // start time
hipMemcpy(d_fib, h_fib, N_BYTES_FIB, hipMemcpyHostToDevice); //copy 2 dev
calc_w_shared<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, d_fib, N_ELEM);
hipMemcpy(h_out3, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop3 = get_time(); // stop time
hipEventSynchronize(stop3);
// Checking that the results of the three runs are identical
validate_output(h_out1, h_out2, h_out3);
// Free memory
hipFree(d_in); hipFree(d_out); hipFree(d_fib);
free(h_in); free(h_out1); free(h_out2); free(h_out3); free(h_fib);
// Printing time benchmarks
float tmp = 0;
hipEventElapsedTime(&tmp, start1, stop1);
printf("\tUsing constant memory: elapsed %.3f ms\n", tmp);
hipEventElapsedTime(&tmp, start2, stop2);
printf("\tUsing global memory: elapsed %.3f ms\n", tmp);
hipEventElapsedTime(&tmp, start3, stop3);
printf("\tUsing shared memory: elapsed %.3f ms\n", tmp);
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
const unsigned int N_FIB = 12;
const unsigned int N_BYTES_FIB = N_FIB * sizeof(unsigned int);
const unsigned int N_THREAD = N_FIB;
unsigned int N_ELEM, N_BYTES_ARR, N_BLOCKS;
__constant__ unsigned int fib_const[N_FIB];
__device__ static unsigned int fib_gmem[N_FIB];
/* Print array of integers, 20 elements per line */
void printArray(unsigned int * a, const char* name, const unsigned int n) {
printf("Printing %s array:", name);
for (int i = 0; i < n; i++) {
if (i%20 == 0) {
printf("\n");
}
printf("%5u", a[i]);
}
printf("\n");
}
__host__ hipEvent_t get_time(void) {
hipEvent_t time;
hipEventCreate(&time);
hipEventRecord(time);
return time;
}
// Generate random integer array between 0 and 9
void genRandArray(unsigned int *arr, const unsigned int n) {
for (int i = 0; i < n; i++) {
arr[i] = rand() % 10;
}
}
// Generate fibonacci sequence
void genFibSequence(unsigned int* arr, int nMax) {
arr[0] = 1;
arr[1] = 1;
for (int n=2; n < nMax; n++) {
arr[n] = arr[n-1] + arr[n-2];
}
}
__global__ void calc_w_const(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_const[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_gmem(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_gmem[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_shared(unsigned int * const inArr, unsigned int *outArr,
unsigned int const *inFib, unsigned int const N) {
__shared__ unsigned int tmpSum[N_FIB]; // shared memory, size = nThreads
const unsigned int tid = threadIdx.x;
tmpSum[tid] = inFib[tid]; // initialize to same as fib sequence
__syncthreads();
if (tid < 2) { // add up all even or odd elements
for (int s=tid+2; s<blockDim.x; s+=2) { // start from elem 2 or 3
tmpSum[tid] += tmpSum[s];
}
}
__syncthreads();
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = inArr[idx] * tmpSum[idx%2]; // perform multiplication
}
}
void validate_output(unsigned int *o1, unsigned int *o2, unsigned int *o3) {
bool div = false;
for (unsigned int n=0; n<N_ELEM && !div ; n++) {
if ( (o1[n] != o2[n]) || (o2[n] != o3[n]) ) {
div = true;
printf("idx=%u: %u, %u, %u\n", n, o1[n], o2[n], o3[n]);
}
}
if (!div) {
printf("Results for all three runs are the identical!\n");
} else {
printf("Some results are different...\n");
}
}
int main(int argc, char* argv[]) {
if (argc != 2) { // expect 1 cmd line args: [arraySizeExponent]
printf("Usage: %s [arraySizeExponent].\n", argv[0]);
return EXIT_FAILURE;
}
unsigned int N_ELEM = 2 << atoi(argv[1]); // n input array
unsigned int N_BYTES_ARR = N_ELEM * sizeof(unsigned int);
unsigned int N_BLOCKS = (N_ELEM + N_THREAD-1) / N_THREAD;
printf("Running with %u elements in input array...\n", N_ELEM);
unsigned int *h_in, *h_out1, *h_out2, *h_out3, *h_fib;
unsigned int *d_in, *d_out, *d_fib;
h_fib = (unsigned int*) malloc(N_BYTES_FIB); // initialize fibonacci
genFibSequence(h_fib, N_FIB); // generate fibonacci sequence
h_in = (unsigned int*) malloc(N_BYTES_ARR); // allocate input
genRandArray(h_in, N_ELEM); // generate random input array
h_out1 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 1
h_out2 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 2
h_out3 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 3
hipHostMalloc((void**)&d_in, N_BYTES_ARR, hipHostMallocDefault); // allocate input
hipHostMalloc((void**)&d_out, N_BYTES_ARR, hipHostMallocDefault); // allocate output
hipHostMalloc((void**)&d_fib, N_BYTES_FIB, hipHostMallocDefault); // allocate output
hipMemcpy(d_in, h_in, N_BYTES_ARR, hipMemcpyHostToDevice); // copy 2 dev
// Timing using constant memory to store Fibonacci sequence
hipEvent_t start1 = get_time(); // start time
hipMemcpyToSymbol(HIP_SYMBOL(fib_const), h_fib, N_BYTES_FIB); // copy to constant
calc_w_const<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
hipMemcpy( h_out1, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop1 = get_time(); // stop time
hipEventSynchronize(stop1);
// Timing using global memory to store Fibonacci sequence
hipEvent_t start2 = get_time(); // start time
hipMemcpyToSymbol(HIP_SYMBOL(fib_gmem), h_fib, N_BYTES_FIB); // copy to global mem
calc_w_gmem<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
hipMemcpy( h_out2, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop2 = get_time(); // stop time
hipEventSynchronize(stop2);
// Timing using shared memory to smartly calculate
hipEvent_t start3 = get_time(); // start time
hipMemcpy(d_fib, h_fib, N_BYTES_FIB, hipMemcpyHostToDevice); //copy 2 dev
calc_w_shared<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, d_fib, N_ELEM);
hipMemcpy(h_out3, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop3 = get_time(); // stop time
hipEventSynchronize(stop3);
// Checking that the results of the three runs are identical
validate_output(h_out1, h_out2, h_out3);
// Free memory
hipFree(d_in); hipFree(d_out); hipFree(d_fib);
free(h_in); free(h_out1); free(h_out2); free(h_out3); free(h_fib);
// Printing time benchmarks
float tmp = 0;
hipEventElapsedTime(&tmp, start1, stop1);
printf("\tUsing constant memory: elapsed %.3f ms\n", tmp);
hipEventElapsedTime(&tmp, start2, stop2);
printf("\tUsing global memory: elapsed %.3f ms\n", tmp);
hipEventElapsedTime(&tmp, start3, stop3);
printf("\tUsing shared memory: elapsed %.3f ms\n", tmp);
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12calc_w_constPjS_j
.globl _Z12calc_w_constPjS_j
.p2align 8
.type _Z12calc_w_constPjS_j,@function
_Z12calc_w_constPjS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_lo_u16 v2, s15, s2
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e64 s2, 1, v2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, v2 :: v_dual_and_b32 v0, 1, v0
v_cmp_eq_u32_e32 vcc_lo, 1, v0
v_or_b32_e32 v0, -2, v1
s_xor_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0, 1, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, fib_const@rel32@lo+4
s_addc_u32 s3, s3, fib_const@rel32@hi+12
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v5, s2, v5, s2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_ci_u32_e64 v6, null, 0, s3, s2
s_mov_b32 s3, 0
global_store_b32 v[3:4], v8, off
.LBB0_2:
global_load_b32 v8, v[5:6], off
v_add_nc_u32_e32 v0, 2, v0
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s2, 9, v0
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v7, v8
global_store_b32 v[3:4], v7, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v1, v0
global_store_b32 v[3:4], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12calc_w_constPjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12calc_w_constPjS_j, .Lfunc_end0-_Z12calc_w_constPjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11calc_w_gmemPjS_j
.globl _Z11calc_w_gmemPjS_j
.p2align 8
.type _Z11calc_w_gmemPjS_j,@function
_Z11calc_w_gmemPjS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_4
v_mul_lo_u16 v2, s15, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _ZL8fib_gmem@gotpcrel32@lo+4
s_addc_u32 s3, s3, _ZL8fib_gmem@gotpcrel32@hi+12
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[6:7], s[2:3], 0x0
v_mov_b32_e32 v8, 0
v_and_b32_e32 v2, 1, v2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 1, v2
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v7, v2 :: v_dual_and_b32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
v_or_b32_e32 v0, -2, v1
s_xor_b32 s2, s2, vcc_lo
v_cndmask_b32_e64 v5, 0, 1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s2, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_ci_u32_e64 v6, null, s7, 0, s2
global_store_b32 v[3:4], v8, off
.LBB1_2:
global_load_b32 v8, v[5:6], off
v_add_nc_u32_e32 v0, 2, v0
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s2, 9, v0
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v7, v8
global_store_b32 v[3:4], v7, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v1, v0
global_store_b32 v[3:4], v0, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11calc_w_gmemPjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11calc_w_gmemPjS_j, .Lfunc_end1-_Z11calc_w_gmemPjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13calc_w_sharedPjS_PKjj
.globl _Z13calc_w_sharedPjS_PKjj
.p2align 8
.type _Z13calc_w_sharedPjS_PKjj,@function
_Z13calc_w_sharedPjS_PKjj:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB2_4
s_load_b32 s3, s[0:1], 0x2c
v_or_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_4
ds_load_b32 v3, v1
v_lshl_add_u32 v4, v0, 2, 8
s_mov_b32 s4, 0
.LBB2_3:
ds_load_b32 v5, v4
v_add_nc_u32_e32 v2, 2, v2
v_add_nc_u32_e32 v4, 8, v4
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_or_b32 s4, vcc_lo, s4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v5
ds_store_b32 v1, v3
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB2_3
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB2_6
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
v_lshlrev_b32_e32 v1, 2, v1
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13calc_w_sharedPjS_PKjj
.amdhsa_group_segment_fixed_size 48
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13calc_w_sharedPjS_PKjj, .Lfunc_end2-_Z13calc_w_sharedPjS_PKjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected fib_const
.type fib_const,@object
.section .bss,"aw",@nobits
.globl fib_const
.p2align 4, 0x0
fib_const:
.zero 48
.size fib_const, 48
.type _ZL8fib_gmem,@object
.globl _ZL8fib_gmem
.p2align 4, 0x0
_ZL8fib_gmem:
.zero 48
.size _ZL8fib_gmem, 48
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym fib_const
.addrsig_sym _ZL8fib_gmem
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12calc_w_constPjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12calc_w_constPjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
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.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11calc_w_gmemPjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11calc_w_gmemPjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
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.name: _Z13calc_w_sharedPjS_PKjj
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.symbol: _Z13calc_w_sharedPjS_PKjj.kd
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.vgpr_spill_count: 0
.wavefront_size: 32
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amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
const unsigned int N_FIB = 12;
const unsigned int N_BYTES_FIB = N_FIB * sizeof(unsigned int);
const unsigned int N_THREAD = N_FIB;
unsigned int N_ELEM, N_BYTES_ARR, N_BLOCKS;
__constant__ unsigned int fib_const[N_FIB];
__device__ static unsigned int fib_gmem[N_FIB];
/* Print array of integers, 20 elements per line */
void printArray(unsigned int * a, const char* name, const unsigned int n) {
printf("Printing %s array:", name);
for (int i = 0; i < n; i++) {
if (i%20 == 0) {
printf("\n");
}
printf("%5u", a[i]);
}
printf("\n");
}
__host__ hipEvent_t get_time(void) {
hipEvent_t time;
hipEventCreate(&time);
hipEventRecord(time);
return time;
}
// Generate random integer array between 0 and 9
void genRandArray(unsigned int *arr, const unsigned int n) {
for (int i = 0; i < n; i++) {
arr[i] = rand() % 10;
}
}
// Generate fibonacci sequence
void genFibSequence(unsigned int* arr, int nMax) {
arr[0] = 1;
arr[1] = 1;
for (int n=2; n < nMax; n++) {
arr[n] = arr[n-1] + arr[n-2];
}
}
__global__ void calc_w_const(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_const[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_gmem(unsigned int * const inArr, unsigned int *outArr,
unsigned int const N) {
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = 0; // initialize 0
for (int i=(idx%2); i<N_FIB; i+=2) { // add up all even/odd elements
outArr[idx] += fib_gmem[i];
}
outArr[idx] *= inArr[idx];
}
}
__global__ void calc_w_shared(unsigned int * const inArr, unsigned int *outArr,
unsigned int const *inFib, unsigned int const N) {
__shared__ unsigned int tmpSum[N_FIB]; // shared memory, size = nThreads
const unsigned int tid = threadIdx.x;
tmpSum[tid] = inFib[tid]; // initialize to same as fib sequence
__syncthreads();
if (tid < 2) { // add up all even or odd elements
for (int s=tid+2; s<blockDim.x; s+=2) { // start from elem 2 or 3
tmpSum[tid] += tmpSum[s];
}
}
__syncthreads();
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
if (idx < N) {
outArr[idx] = inArr[idx] * tmpSum[idx%2]; // perform multiplication
}
}
void validate_output(unsigned int *o1, unsigned int *o2, unsigned int *o3) {
bool div = false;
for (unsigned int n=0; n<N_ELEM && !div ; n++) {
if ( (o1[n] != o2[n]) || (o2[n] != o3[n]) ) {
div = true;
printf("idx=%u: %u, %u, %u\n", n, o1[n], o2[n], o3[n]);
}
}
if (!div) {
printf("Results for all three runs are the identical!\n");
} else {
printf("Some results are different...\n");
}
}
int main(int argc, char* argv[]) {
if (argc != 2) { // expect 1 cmd line args: [arraySizeExponent]
printf("Usage: %s [arraySizeExponent].\n", argv[0]);
return EXIT_FAILURE;
}
unsigned int N_ELEM = 2 << atoi(argv[1]); // n input array
unsigned int N_BYTES_ARR = N_ELEM * sizeof(unsigned int);
unsigned int N_BLOCKS = (N_ELEM + N_THREAD-1) / N_THREAD;
printf("Running with %u elements in input array...\n", N_ELEM);
unsigned int *h_in, *h_out1, *h_out2, *h_out3, *h_fib;
unsigned int *d_in, *d_out, *d_fib;
h_fib = (unsigned int*) malloc(N_BYTES_FIB); // initialize fibonacci
genFibSequence(h_fib, N_FIB); // generate fibonacci sequence
h_in = (unsigned int*) malloc(N_BYTES_ARR); // allocate input
genRandArray(h_in, N_ELEM); // generate random input array
h_out1 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 1
h_out2 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 2
h_out3 = (unsigned int*) malloc(N_BYTES_ARR); // allocate output 3
hipHostMalloc((void**)&d_in, N_BYTES_ARR, hipHostMallocDefault); // allocate input
hipHostMalloc((void**)&d_out, N_BYTES_ARR, hipHostMallocDefault); // allocate output
hipHostMalloc((void**)&d_fib, N_BYTES_FIB, hipHostMallocDefault); // allocate output
hipMemcpy(d_in, h_in, N_BYTES_ARR, hipMemcpyHostToDevice); // copy 2 dev
// Timing using constant memory to store Fibonacci sequence
hipEvent_t start1 = get_time(); // start time
hipMemcpyToSymbol(HIP_SYMBOL(fib_const), h_fib, N_BYTES_FIB); // copy to constant
calc_w_const<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
hipMemcpy( h_out1, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop1 = get_time(); // stop time
hipEventSynchronize(stop1);
// Timing using global memory to store Fibonacci sequence
hipEvent_t start2 = get_time(); // start time
hipMemcpyToSymbol(HIP_SYMBOL(fib_gmem), h_fib, N_BYTES_FIB); // copy to global mem
calc_w_gmem<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, N_ELEM);
hipMemcpy( h_out2, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop2 = get_time(); // stop time
hipEventSynchronize(stop2);
// Timing using shared memory to smartly calculate
hipEvent_t start3 = get_time(); // start time
hipMemcpy(d_fib, h_fib, N_BYTES_FIB, hipMemcpyHostToDevice); //copy 2 dev
calc_w_shared<<<N_BLOCKS, N_THREAD>>>(d_in, d_out, d_fib, N_ELEM);
hipMemcpy(h_out3, d_out, N_BYTES_ARR, hipMemcpyDeviceToHost );
hipEvent_t stop3 = get_time(); // stop time
hipEventSynchronize(stop3);
// Checking that the results of the three runs are identical
validate_output(h_out1, h_out2, h_out3);
// Free memory
hipFree(d_in); hipFree(d_out); hipFree(d_fib);
free(h_in); free(h_out1); free(h_out2); free(h_out3); free(h_fib);
// Printing time benchmarks
float tmp = 0;
hipEventElapsedTime(&tmp, start1, stop1);
printf("\tUsing constant memory: elapsed %.3f ms\n", tmp);
hipEventElapsedTime(&tmp, start2, stop2);
printf("\tUsing global memory: elapsed %.3f ms\n", tmp);
hipEventElapsedTime(&tmp, start3, stop3);
printf("\tUsing shared memory: elapsed %.3f ms\n", tmp);
printf("\n");
} | .text
.file "const_v_shared_test.hip"
.globl _Z10printArrayPjPKcj # -- Begin function _Z10printArrayPjPKcj
.p2align 4, 0x90
.type _Z10printArrayPjPKcj,@function
_Z10printArrayPjPKcj: # @_Z10printArrayPjPKcj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
je .LBB0_5
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %ebp, %ebp
xorl %r12d, %r12d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
decl %ebp
cmpq %r12, %r14
je .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
imulq %r15, %rax
shrq $36, %rax
leal (%rax,%rax,4), %eax
shll $2, %eax
addl %ebp, %eax
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB0_4
.LBB0_5: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z10printArrayPjPKcj, .Lfunc_end0-_Z10printArrayPjPKcj
.cfi_endproc
# -- End function
.globl _Z8get_timev # -- Begin function _Z8get_timev
.p2align 4, 0x90
.type _Z8get_timev,@function
_Z8get_timev: # @_Z8get_timev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8get_timev, .Lfunc_end1-_Z8get_timev
.cfi_endproc
# -- End function
.globl _Z12genRandArrayPjj # -- Begin function _Z12genRandArrayPjj
.p2align 4, 0x90
.type _Z12genRandArrayPjj,@function
_Z12genRandArrayPjj: # @_Z12genRandArrayPjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z12genRandArrayPjj, .Lfunc_end2-_Z12genRandArrayPjj
.cfi_endproc
# -- End function
.globl _Z14genFibSequencePji # -- Begin function _Z14genFibSequencePji
.p2align 4, 0x90
.type _Z14genFibSequencePji,@function
_Z14genFibSequencePji: # @_Z14genFibSequencePji
.cfi_startproc
# %bb.0:
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, (%rdi)
cmpl $3, %esi
jl .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
movl 4(%rdi), %ecx
movl $2, %edx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl -8(%rdi,%rdx,4), %ecx
movl %ecx, (%rdi,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z14genFibSequencePji, .Lfunc_end3-_Z14genFibSequencePji
.cfi_endproc
# -- End function
.globl _Z27__device_stub__calc_w_constPjS_j # -- Begin function _Z27__device_stub__calc_w_constPjS_j
.p2align 4, 0x90
.type _Z27__device_stub__calc_w_constPjS_j,@function
_Z27__device_stub__calc_w_constPjS_j: # @_Z27__device_stub__calc_w_constPjS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12calc_w_constPjS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z27__device_stub__calc_w_constPjS_j, .Lfunc_end4-_Z27__device_stub__calc_w_constPjS_j
.cfi_endproc
# -- End function
.globl _Z26__device_stub__calc_w_gmemPjS_j # -- Begin function _Z26__device_stub__calc_w_gmemPjS_j
.p2align 4, 0x90
.type _Z26__device_stub__calc_w_gmemPjS_j,@function
_Z26__device_stub__calc_w_gmemPjS_j: # @_Z26__device_stub__calc_w_gmemPjS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11calc_w_gmemPjS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z26__device_stub__calc_w_gmemPjS_j, .Lfunc_end5-_Z26__device_stub__calc_w_gmemPjS_j
.cfi_endproc
# -- End function
.globl _Z28__device_stub__calc_w_sharedPjS_PKjj # -- Begin function _Z28__device_stub__calc_w_sharedPjS_PKjj
.p2align 4, 0x90
.type _Z28__device_stub__calc_w_sharedPjS_PKjj,@function
_Z28__device_stub__calc_w_sharedPjS_PKjj: # @_Z28__device_stub__calc_w_sharedPjS_PKjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13calc_w_sharedPjS_PKjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z28__device_stub__calc_w_sharedPjS_PKjj, .Lfunc_end6-_Z28__device_stub__calc_w_sharedPjS_PKjj
.cfi_endproc
# -- End function
.globl _Z15validate_outputPjS_S_ # -- Begin function _Z15validate_outputPjS_S_
.p2align 4, 0x90
.type _Z15validate_outputPjS_S_,@function
_Z15validate_outputPjS_S_: # @_Z15validate_outputPjS_S_
.cfi_startproc
# %bb.0:
cmpl $0, N_ELEM(%rip)
je .LBB7_1
# %bb.3: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
xorl %eax, %eax
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl (%r14,%r12,4), %ecx
cmpl %ecx, %edx
jne .LBB7_6
# %bb.5: # in Loop: Header=BB7_4 Depth=1
cmpl (%rbx,%r12,4), %ecx
je .LBB7_7
.LBB7_6: # in Loop: Header=BB7_4 Depth=1
movl (%rbx,%r12,4), %r8d
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movb $1, %al
.LBB7_7: # in Loop: Header=BB7_4 Depth=1
incq %r12
movl N_ELEM(%rip), %ecx
cmpq %rcx, %r12
jae .LBB7_9
# %bb.8: # in Loop: Header=BB7_4 Depth=1
movl %eax, %ecx
andb $1, %cl
je .LBB7_4
.LBB7_9: # %._crit_edge
testb $1, %al
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
jmp puts@PLT # TAILCALL
.LBB7_1:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end7:
.size _Z15validate_outputPjS_S_, .Lfunc_end7-_Z15validate_outputPjS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB8_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $2, %esi
movl %r15d, %ecx
shll %cl, %esi
leal 11(%rsi), %ebp
movl $.L.str.7, %edi
movq %rsi, 48(%rsp) # 8-byte Spill
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $48, %edi
callq malloc
movq %rax, %rbx
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, (%rbx)
movl $2, %eax
movl $1, %ecx
.p2align 4, 0x90
.LBB8_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl -8(%rbx,%rax,4), %ecx
movl %ecx, (%rbx,%rax,4)
incq %rax
cmpq $12, %rax
jne .LBB8_3
# %bb.4: # %_Z14genFibSequencePji.exit
movl $8, %edi
movl %r15d, %ecx
shll %cl, %edi
movl %ebp, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
imulq %rax, %rcx
shrq $35, %rcx
movq %rcx, 136(%rsp) # 8-byte Spill
movq %rdi, %r14
callq malloc
movq %rax, %rbp
cmpl $30, %r15d
ja .LBB8_7
# %bb.5: # %.lr.ph.preheader.i
movl 48(%rsp), %r15d # 4-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB8_6: # %.lr.ph.i62
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbp,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB8_6
.LBB8_7: # %_Z12genRandArrayPjj.exit
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r13
leaq 56(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 144(%rsp), %rdi
movl $48, %esi
xorl %edx, %edx
callq hipHostMalloc
movq 56(%rsp), %rdi
movq %rbp, 184(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
movq %rax, 192(%rsp) # 8-byte Spill
movl $fib_const, %edi
movl $48, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl 136(%rsp), %eax # 4-byte Reload
movabsq $4294967308, %rdx # imm = 0x10000000C
leaq (%rax,%rdx), %rbp
addq $-12, %rbp
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_9
# %bb.8:
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 120(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movq %rsp, %r9
movl $_Z12calc_w_constPjS_j, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_9:
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
movq %rdi, 160(%rsp) # 8-byte Spill
callq hipEventSynchronize
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
movq %rax, 136(%rsp) # 8-byte Spill
movl $_ZL8fib_gmem, %edi
movl $48, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967308, %rdx # imm = 0x10000000C
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_11
# %bb.10:
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 120(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movq %rsp, %r9
movl $_Z11calc_w_gmemPjS_j, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_11:
movq 40(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
movq %rdi, 176(%rsp) # 8-byte Spill
callq hipEventSynchronize
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
movq %rax, 168(%rsp) # 8-byte Spill
movq 144(%rsp), %rdi
movl $48, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967308, %rdx # imm = 0x10000000C
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_13
# %bb.12:
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq 144(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 156(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 120(%rsp), %rax
movq %rax, 8(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 156(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movq %rsp, %r9
movl $_Z13calc_w_sharedPjS_PKjj, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_13:
movq 40(%rsp), %rsi
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
movq %rdi, 48(%rsp) # 8-byte Spill
callq hipEventSynchronize
cmpl $0, N_ELEM(%rip)
je .LBB8_14
# %bb.15: # %.lr.ph.i78.preheader
movq 160(%rsp), %r14 # 8-byte Reload
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB8_16: # %.lr.ph.i78
# =>This Inner Loop Header: Depth=1
movl (%r15,%rbp,4), %edx
movl (%r12,%rbp,4), %ecx
cmpl %ecx, %edx
jne .LBB8_18
# %bb.17: # in Loop: Header=BB8_16 Depth=1
cmpl (%r13,%rbp,4), %ecx
je .LBB8_19
.LBB8_18: # in Loop: Header=BB8_16 Depth=1
movl (%r13,%rbp,4), %r8d
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movb $1, %al
.LBB8_19: # in Loop: Header=BB8_16 Depth=1
incq %rbp
movl N_ELEM(%rip), %ecx
cmpq %rcx, %rbp
jae .LBB8_21
# %bb.20: # in Loop: Header=BB8_16 Depth=1
movl %eax, %ecx
andb $1, %cl
je .LBB8_16
.LBB8_21: # %._crit_edge.i
testb $1, %al
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
xorl %ebp, %ebp
jmp .LBB8_22
.LBB8_1:
movq (%rsi), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $1, %ebp
jmp .LBB8_23
.LBB8_14:
movl $.Lstr, %edi
movq 160(%rsp), %r14 # 8-byte Reload
.LBB8_22: # %_Z15validate_outputPjS_S_.exit
callq puts@PLT
movq 56(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 184(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq %rbx, %rdi
callq free
movl $0, (%rsp)
movq %rsp, %rbx
movq %rbx, %rdi
movq 192(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
movq 136(%rsp), %rsi # 8-byte Reload
movq 176(%rsp), %rdx # 8-byte Reload
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
movq 168(%rsp), %rsi # 8-byte Reload
movq 48(%rsp), %rdx # 8-byte Reload
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
.LBB8_23:
movl %ebp, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12calc_w_constPjS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calc_w_gmemPjS_j, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13calc_w_sharedPjS_PKjj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $fib_const, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $48, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $_ZL8fib_gmem, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $48, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type N_ELEM,@object # @N_ELEM
.bss
.globl N_ELEM
.p2align 2, 0x0
N_ELEM:
.long 0 # 0x0
.size N_ELEM, 4
.type N_BYTES_ARR,@object # @N_BYTES_ARR
.globl N_BYTES_ARR
.p2align 2, 0x0
N_BYTES_ARR:
.long 0 # 0x0
.size N_BYTES_ARR, 4
.type N_BLOCKS,@object # @N_BLOCKS
.globl N_BLOCKS
.p2align 2, 0x0
N_BLOCKS:
.long 0 # 0x0
.size N_BLOCKS, 4
.type fib_const,@object # @fib_const
.local fib_const
.comm fib_const,48,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Printing %s array:"
.size .L.str, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%5u"
.size .L.str.2, 4
.type _Z12calc_w_constPjS_j,@object # @_Z12calc_w_constPjS_j
.section .rodata,"a",@progbits
.globl _Z12calc_w_constPjS_j
.p2align 3, 0x0
_Z12calc_w_constPjS_j:
.quad _Z27__device_stub__calc_w_constPjS_j
.size _Z12calc_w_constPjS_j, 8
.type _Z11calc_w_gmemPjS_j,@object # @_Z11calc_w_gmemPjS_j
.globl _Z11calc_w_gmemPjS_j
.p2align 3, 0x0
_Z11calc_w_gmemPjS_j:
.quad _Z26__device_stub__calc_w_gmemPjS_j
.size _Z11calc_w_gmemPjS_j, 8
.type _Z13calc_w_sharedPjS_PKjj,@object # @_Z13calc_w_sharedPjS_PKjj
.globl _Z13calc_w_sharedPjS_PKjj
.p2align 3, 0x0
_Z13calc_w_sharedPjS_PKjj:
.quad _Z28__device_stub__calc_w_sharedPjS_PKjj
.size _Z13calc_w_sharedPjS_PKjj, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "idx=%u: %u, %u, %u\n"
.size .L.str.3, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Usage: %s [arraySizeExponent].\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Running with %u elements in input array...\n"
.size .L.str.7, 44
.type _ZL8fib_gmem,@object # @_ZL8fib_gmem
.local _ZL8fib_gmem
.comm _ZL8fib_gmem,48,16
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tUsing constant memory: elapsed %.3f ms\n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tUsing global memory: elapsed %.3f ms\n"
.size .L.str.9, 39
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tUsing shared memory: elapsed %.3f ms\n"
.size .L.str.10, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12calc_w_constPjS_j"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11calc_w_gmemPjS_j"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13calc_w_sharedPjS_PKjj"
.size .L__unnamed_3, 26
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "fib_const"
.size .L__unnamed_4, 10
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_ZL8fib_gmem"
.size .L__unnamed_5, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Results for all three runs are the identical!"
.size .Lstr, 46
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Some results are different..."
.size .Lstr.1, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__calc_w_constPjS_j
.addrsig_sym _Z26__device_stub__calc_w_gmemPjS_j
.addrsig_sym _Z28__device_stub__calc_w_sharedPjS_PKjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fib_const
.addrsig_sym _Z12calc_w_constPjS_j
.addrsig_sym _Z11calc_w_gmemPjS_j
.addrsig_sym _Z13calc_w_sharedPjS_PKjj
.addrsig_sym _ZL8fib_gmem
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13calc_w_sharedPjS_PKjj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R7, R9, c[0x0][0x170] ; /* 0x00005c0007027625 */
/* 0x001fcc00078e0009 */
/*0050*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R7, 0x2, PT ; /* 0x000000020700780c */
/* 0x000fe20003f06070 */
/*0070*/ BSSY B0, 0x180 ; /* 0x0000010000007945 */
/* 0x000fe40003800000 */
/*0080*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0041e80000004800 */
/*0090*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00a0*/ @P0 BRA 0x170 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R7, 0x2, RZ ; /* 0x0000000207007810 */
/* 0x001fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fda0003f06070 */
/*00d0*/ @P0 BRA 0x170 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LDS R2, [R7.X4] ; /* 0x0000000007027984 */
/* 0x0000620000004800 */
/*00f0*/ SHF.L.U32 R3, R0, 0x2, RZ ; /* 0x0000000200037819 */
/* 0x000fca00000006ff */
/*0100*/ LDS R5, [R3] ; /* 0x0000000003057984 */
/* 0x0004e20000000800 */
/*0110*/ IADD3 R0, R0, 0x2, RZ ; /* 0x0000000200007810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x0], PT ; /* 0x0000000000007a0c */
/* 0x000fe40003f06070 */
/*0130*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x004fe20007ffe0ff */
/*0140*/ IMAD.IADD R2, R5, 0x1, R2 ; /* 0x0000000105027824 */
/* 0x00afca00078e0202 */
/*0150*/ STS [R7.X4], R2 ; /* 0x0000000207007388 */
/* 0x0003ea0000004800 */
/*0160*/ @!P0 BRA 0x100 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0180*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0190*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01a0*/ IMAD R4, R4, c[0x0][0x0], R7 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0207 */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fda0003f06070 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ IMAD.WIDE.U32 R2, R4, R9, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x002fcc00078e0009 */
/*01e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*01f0*/ SHF.L.U32 R0, R4.reuse, 0x2, RZ ; /* 0x0000000204007819 */
/* 0x040fe200000006ff */
/*0200*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0009 */
/*0210*/ LOP3.LUT R0, R0, 0x4, RZ, 0xc0, !PT ; /* 0x0000000400007812 */
/* 0x000fcc00078ec0ff */
/*0220*/ LDS R0, [R0] ; /* 0x0000000000007984 */
/* 0x000ea40000000800 */
/*0230*/ IMAD R7, R0, R3, RZ ; /* 0x0000000300077224 */
/* 0x004fca00078e02ff */
/*0240*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11calc_w_gmemPjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LOP3.LUT R6, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100067812 */
/* 0x040fe200078ec0ff */
/*0090*/ BSSY B0, 0x190 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0005 */
/*00b0*/ IMAD.WIDE.U32 R4, R6, R5, c[0x4][0x0] ; /* 0x0100000006047625 */
/* 0x000fe200078e0005 */
/*00c0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e6000c101904 */
/*00d0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*00e0*/ MOV R8, R4 ; /* 0x0000000400087202 */
/* 0x000fc80000000f00 */
/*00f0*/ MOV R4, R8 ; /* 0x0000000800047202 */
/* 0x000fcc0000000f00 */
/*0100*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x0022a2000c1e1900 */
/*0110*/ IADD3 R6, R6, 0x2, RZ ; /* 0x0000000206067810 */
/* 0x000fe40007ffe0ff */
/*0120*/ IADD3 R8, P1, R8, 0x8, RZ ; /* 0x0000000808087810 */
/* 0x000fe40007f3e0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f06070 */
/*0140*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x002fe20000ffe4ff */
/*0150*/ IMAD.IADD R7, R4, 0x1, R7 ; /* 0x0000000104077824 */
/* 0x004fca00078e0207 */
/*0160*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0003ea000c101904 */
/*0170*/ @!P0 BRA 0xf0 ; /* 0xffffff7000008947 */
/* 0x000fea000383ffff */
/*0180*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0190*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*01a0*/ LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fca00000f14ff */
/*01b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IMAD R7, R7, R4, RZ ; /* 0x0000000407077224 */
/* 0x006fca00078e02ff */
/*01d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12calc_w_constPjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R2, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100027812 */
/* 0x000fe200078ec0ff */
/*0070*/ BSSY B0, 0x1b0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0090*/ ISETP.GE.U32.AND P0, PT, R2.reuse, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x040fe20003f06070 */
/*00a0*/ IMAD.SHL.U32 R8, R2.reuse, 0x4, RZ ; /* 0x0000000402087824 */
/* 0x040fe200078e00ff */
/*00b0*/ IADD3 R3, -R2, 0xc, RZ ; /* 0x0000000c02037810 */
/* 0x000fc80007ffe1ff */
/*00c0*/ ISETP.LE.U32.OR P1, PT, R3, 0x6, P0 ; /* 0x000000060300780c */
/* 0x000fe40000723470 */
/*00d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*00e0*/ @P1 BRA 0x1a0 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*00f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0100*/ LDC R4, c[0x3][R8] ; /* 0x00c0000008047b82 */
/* 0x0000620000000800 */
/*0110*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fc80007ffe0ff */
/*0120*/ ISETP.GE.U32.AND P1, PT, R2, 0x6, PT ; /* 0x000000060200780c */
/* 0x000fc60003f26070 */
/*0130*/ LDC R3, c[0x3][R8+0x8] ; /* 0x00c0020008037b82 */
/* 0x0000700000000800 */
/*0140*/ LDC R6, c[0x3][R8+0x10] ; /* 0x00c0040008067b82 */
/* 0x0000b00000000800 */
/*0150*/ LDC R5, c[0x3][R8+0x18] ; /* 0x00c0060008057b82 */
/* 0x0000a40000000800 */
/*0160*/ IADD3 R8, R8, 0x20, RZ ; /* 0x0000002008087810 */
/* 0x001fc40007ffe0ff */
/*0170*/ IADD3 R3, R3, R7, R4 ; /* 0x0000000703037210 */
/* 0x002fc80007ffe004 */
/*0180*/ IADD3 R7, R5, R3, R6 ; /* 0x0000000305077210 */
/* 0x004fe20007ffe006 */
/*0190*/ @!P1 BRA 0x100 ; /* 0xffffff6000009947 */
/* 0x000fea000383ffff */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R2.reuse, 0xc, PT ; /* 0x0000000c0200780c */
/* 0x040fe20003f26070 */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*01d0*/ IADD3 R3, -R2, 0xc, RZ ; /* 0x0000000c02037810 */
/* 0x000fe20007ffe1ff */
/*01e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01f0*/ LEA R4, P2, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fe400078410ff */
/*0200*/ ISETP.LE.U32.OR P1, PT, R3, 0x2, P1 ; /* 0x000000020300780c */
/* 0x000fda0000f23470 */
/*0210*/ @!P1 PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000981c */
/* 0x000fe20003f0e170 */
/*0220*/ @!P1 LDC R3, c[0x3][R8+0x8] ; /* 0x00c0020008039b82 */
/* 0x0000620000000800 */
/*0230*/ @!P1 IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402029810 */
/* 0x000fd60007ffe0ff */
/*0240*/ ISETP.LT.U32.OR P0, PT, R2, 0xc, P0 ; /* 0x0000000c0200780c */
/* 0x000fe40000701470 */
/*0250*/ @!P1 LDC R2, c[0x3][R8] ; /* 0x00c0000008029b82 */
/* 0x0000640000000800 */
/*0260*/ @!P1 IADD3 R8, R8, 0x10, RZ ; /* 0x0000001008089810 */
/* 0x001fd20007ffe0ff */
/*0270*/ @P0 LDC R6, c[0x3][R8] ; /* 0x00c0000008060b82 */
/* 0x000e220000000800 */
/*0280*/ @!P1 IADD3 R7, R3, R7, R2 ; /* 0x0000000703079210 */
/* 0x002fe20007ffe002 */
/*0290*/ IMAD.WIDE.U32 R2, R0.reuse, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x040fe200078e0005 */
/*02a0*/ LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x2, P2 ; /* 0x0000590000057a11 */
/* 0x000fc800010f14ff */
/*02b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*02c0*/ @P0 IMAD.IADD R7, R7, 0x1, R6 ; /* 0x0000000107070824 */
/* 0x001fca00078e0206 */
/*02d0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*02e0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*02f0*/ IMAD R9, R4, R7, RZ ; /* 0x0000000704097224 */
/* 0x004fca00078e02ff */
/*0300*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12calc_w_constPjS_j
.globl _Z12calc_w_constPjS_j
.p2align 8
.type _Z12calc_w_constPjS_j,@function
_Z12calc_w_constPjS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_4
v_mul_lo_u16 v2, s15, s2
s_load_b64 s[4:5], s[0:1], 0x8
v_mov_b32_e32 v8, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, 1, v2
v_cmp_eq_u32_e64 s2, 1, v2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, v2 :: v_dual_and_b32 v0, 1, v0
v_cmp_eq_u32_e32 vcc_lo, 1, v0
v_or_b32_e32 v0, -2, v1
s_xor_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0, 1, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, fib_const@rel32@lo+4
s_addc_u32 s3, s3, fib_const@rel32@hi+12
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_u32 v5, s2, v5, s2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_ci_u32_e64 v6, null, 0, s3, s2
s_mov_b32 s3, 0
global_store_b32 v[3:4], v8, off
.LBB0_2:
global_load_b32 v8, v[5:6], off
v_add_nc_u32_e32 v0, 2, v0
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s2, 9, v0
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v7, v8
global_store_b32 v[3:4], v7, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v1, v0
global_store_b32 v[3:4], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12calc_w_constPjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12calc_w_constPjS_j, .Lfunc_end0-_Z12calc_w_constPjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11calc_w_gmemPjS_j
.globl _Z11calc_w_gmemPjS_j
.p2align 8
.type _Z11calc_w_gmemPjS_j,@function
_Z11calc_w_gmemPjS_j:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmp_gt_u32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB1_4
v_mul_lo_u16 v2, s15, s2
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, _ZL8fib_gmem@gotpcrel32@lo+4
s_addc_u32 s3, s3, _ZL8fib_gmem@gotpcrel32@hi+12
s_load_b64 s[4:5], s[0:1], 0x8
s_load_b64 s[6:7], s[2:3], 0x0
v_mov_b32_e32 v8, 0
v_and_b32_e32 v2, 1, v2
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s2, 1, v2
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v7, v2 :: v_dual_and_b32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
v_or_b32_e32 v0, -2, v1
s_xor_b32 s2, s2, vcc_lo
v_cndmask_b32_e64 v5, 0, 1, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, s2, s6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
v_add_co_ci_u32_e64 v6, null, s7, 0, s2
global_store_b32 v[3:4], v8, off
.LBB1_2:
global_load_b32 v8, v[5:6], off
v_add_nc_u32_e32 v0, 2, v0
v_add_co_u32 v5, vcc_lo, v5, 8
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_u32_e64 s2, 9, v0
s_or_b32 s3, s2, s3
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v7, v7, v8
global_store_b32 v[3:4], v7, off
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB1_2
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v1, v0
global_store_b32 v[3:4], v0, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11calc_w_gmemPjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z11calc_w_gmemPjS_j, .Lfunc_end1-_Z11calc_w_gmemPjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13calc_w_sharedPjS_PKjj
.globl _Z13calc_w_sharedPjS_PKjj
.p2align 8
.type _Z13calc_w_sharedPjS_PKjj,@function
_Z13calc_w_sharedPjS_PKjj:
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v1, 2, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v2, v1, s[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
ds_store_b32 v1, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB2_4
s_load_b32 s3, s[0:1], 0x2c
v_or_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s3, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_4
ds_load_b32 v3, v1
v_lshl_add_u32 v4, v0, 2, 8
s_mov_b32 s4, 0
.LBB2_3:
ds_load_b32 v5, v4
v_add_nc_u32_e32 v2, 2, v2
v_add_nc_u32_e32 v4, 8, v4
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_or_b32 s4, vcc_lo, s4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v3, v3, v5
ds_store_b32 v1, v3
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB2_3
.LBB2_4:
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB2_6
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_and_b32_e32 v1, 1, v1
v_lshlrev_b32_e32 v1, 2, v1
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v4, v1, v0
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB2_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13calc_w_sharedPjS_PKjj
.amdhsa_group_segment_fixed_size 48
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13calc_w_sharedPjS_PKjj, .Lfunc_end2-_Z13calc_w_sharedPjS_PKjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected fib_const
.type fib_const,@object
.section .bss,"aw",@nobits
.globl fib_const
.p2align 4, 0x0
fib_const:
.zero 48
.size fib_const, 48
.type _ZL8fib_gmem,@object
.globl _ZL8fib_gmem
.p2align 4, 0x0
_ZL8fib_gmem:
.zero 48
.size _ZL8fib_gmem, 48
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym fib_const
.addrsig_sym _ZL8fib_gmem
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12calc_w_constPjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12calc_w_constPjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11calc_w_gmemPjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11calc_w_gmemPjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 48
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13calc_w_sharedPjS_PKjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13calc_w_sharedPjS_PKjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c4e3d_00000000-6_const_v_shared_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Printing %s array:"
.LC1:
.string "\n"
.LC2:
.string "%5u"
.text
.globl _Z10printArrayPjPKcj
.type _Z10printArrayPjPKcj, @function
_Z10printArrayPjPKcj:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movl %edx, %ebp
movq %rsi, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
je .L4
movl %ebp, %ebp
movl $0, %ebx
leaq .LC1(%rip), %r14
leaq .LC2(%rip), %r13
jmp .L6
.L5:
movl (%r12,%rbx,4), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
je .L4
.L6:
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $35, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %eax
sall $2, %eax
cmpl %ebx, %eax
jne .L5
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z10printArrayPjPKcj, .-_Z10printArrayPjPKcj
.globl _Z8get_timev
.type _Z8get_timev, @function
_Z8get_timev:
.LFB2058:
.cfi_startproc
endbr64
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq (%rsp), %rdi
call cudaEventRecord@PLT
movq (%rsp), %rax
movq 8(%rsp), %rdx
subq %fs:40, %rdx
jne .L12
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z8get_timev, .-_Z8get_timev
.globl _Z12genRandArrayPjj
.type _Z12genRandArrayPjj, @function
_Z12genRandArrayPjj:
.LFB2059:
.cfi_startproc
endbr64
testl %esi, %esi
je .L18
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movl %esi, %esi
leaq (%rdi,%rsi,4), %rbp
.L15:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L15
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE2059:
.size _Z12genRandArrayPjj, .-_Z12genRandArrayPjj
.globl _Z14genFibSequencePji
.type _Z14genFibSequencePji, @function
_Z14genFibSequencePji:
.LFB2060:
.cfi_startproc
endbr64
movl $1, (%rdi)
movl $1, 4(%rdi)
cmpl $2, %esi
jle .L21
movq %rdi, %rax
leal -3(%rsi), %edx
leaq 4(%rdi,%rdx,4), %rcx
.L23:
movl (%rax), %edx
addl 4(%rax), %edx
movl %edx, 8(%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L23
.L21:
ret
.cfi_endproc
.LFE2060:
.size _Z14genFibSequencePji, .-_Z14genFibSequencePji
.section .rodata.str1.1
.LC3:
.string "idx=%u: %u, %u, %u\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Some results are different...\n"
.align 8
.LC5:
.string "Results for all three runs are the identical!\n"
.text
.globl _Z15validate_outputPjS_S_
.type _Z15validate_outputPjS_S_, @function
_Z15validate_outputPjS_S_:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl N_ELEM(%rip), %r9d
testl %r9d, %r9d
je .L26
movq %rdx, %rax
movl $0, %edx
jmp .L30
.L28:
addq $1, %rdx
cmpl %r9d, %edx
jnb .L26
.L30:
movl (%rdi,%rdx,4), %ecx
movl (%rsi,%rdx,4), %r8d
cmpl %r8d, %ecx
jne .L27
cmpl (%rax,%rdx,4), %r8d
je .L28
.L27:
movl (%rax,%rdx,4), %r9d
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L25:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L25
.cfi_endproc
.LFE2061:
.size _Z15validate_outputPjS_S_, .-_Z15validate_outputPjS_S_
.globl _Z35__device_stub__Z12calc_w_constPjS_jPjS_j
.type _Z35__device_stub__Z12calc_w_constPjS_jPjS_j, @function
_Z35__device_stub__Z12calc_w_constPjS_jPjS_j:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L37
.L33:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12calc_w_constPjS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L33
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z35__device_stub__Z12calc_w_constPjS_jPjS_j, .-_Z35__device_stub__Z12calc_w_constPjS_jPjS_j
.globl _Z12calc_w_constPjS_j
.type _Z12calc_w_constPjS_j, @function
_Z12calc_w_constPjS_j:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12calc_w_constPjS_jPjS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z12calc_w_constPjS_j, .-_Z12calc_w_constPjS_j
.globl _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j
.type _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j, @function
_Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j:
.LFB2089:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L45
.L41:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L46
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11calc_w_gmemPjS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L41
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j, .-_Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j
.globl _Z11calc_w_gmemPjS_j
.type _Z11calc_w_gmemPjS_j, @function
_Z11calc_w_gmemPjS_j:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z11calc_w_gmemPjS_j, .-_Z11calc_w_gmemPjS_j
.globl _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj
.type _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj, @function
_Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj:
.LFB2091:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L53
.L49:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L54
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13calc_w_sharedPjS_PKjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L49
.L54:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2091:
.size _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj, .-_Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj
.globl _Z13calc_w_sharedPjS_PKjj
.type _Z13calc_w_sharedPjS_PKjj, @function
_Z13calc_w_sharedPjS_PKjj:
.LFB2092:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _Z13calc_w_sharedPjS_PKjj, .-_Z13calc_w_sharedPjS_PKjj
.section .rodata.str1.8
.align 8
.LC6:
.string "Usage: %s [arraySizeExponent].\n"
.align 8
.LC7:
.string "Running with %u elements in input array...\n"
.align 8
.LC9:
.string "\tUsing constant memory: elapsed %.3f ms\n"
.align 8
.LC10:
.string "\tUsing global memory: elapsed %.3f ms\n"
.align 8
.LC11:
.string "\tUsing shared memory: elapsed %.3f ms\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L58
movq (%rsi), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L57:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L65
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $2, %r12d
movl %eax, %ecx
sall %cl, %r12d
leal 11(%r12), %eax
movl $12, %ecx
movl $0, %edx
divl %ecx
movl %eax, %r13d
movl %r12d, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $48, %edi
call malloc@PLT
movq %rax, %rbp
movl $12, %esi
movq %rax, %rdi
call _Z14genFibSequencePji
leal 0(,%r12,4), %ebx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movl %r12d, %esi
movq %rax, %rdi
call _Z12genRandArrayPjj
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 16(%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMallocHost@PLT
leaq 88(%rsp), %rdi
movl $48, %esi
call cudaMallocHost@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, 24(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $48, %edx
movq %rbp, %rsi
leaq _ZL9fib_const(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $12, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L60:
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, 32(%rsp)
movq %rax, %rdi
call cudaEventSynchronize@PLT
call _Z8get_timev
movq %rax, 40(%rsp)
movl $1, %r8d
movl $0, %ecx
movl $48, %edx
movq %rbp, %rsi
leaq _ZL8fib_gmem(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movl $12, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L67
.L61:
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, 48(%rsp)
movq %rax, %rdi
call cudaEventSynchronize@PLT
call _Z8get_timev
movq %rax, 56(%rsp)
movl $1, %ecx
movl $48, %edx
movq %rbp, %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl $12, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl %r13d, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L62:
movl $2, %ecx
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call _Z8get_timev
movq %rax, %rbx
movq %rax, %rdi
call cudaEventSynchronize@PLT
movq %r15, %rdx
movq 16(%rsp), %r12
movq %r12, %rsi
movq 8(%rsp), %r13
movq %r13, %rdi
call _Z15validate_outputPjS_S_
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movl $0x00000000, 108(%rsp)
leaq 108(%rsp), %rbp
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 108(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq %rbp, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 108(%rsp), %xmm0
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 108(%rsp), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L57
.L66:
movl %r12d, %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z35__device_stub__Z12calc_w_constPjS_jPjS_j
jmp .L60
.L67:
movl %r12d, %edx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z34__device_stub__Z11calc_w_gmemPjS_jPjS_j
jmp .L61
.L68:
movl %r12d, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z39__device_stub__Z13calc_w_sharedPjS_PKjjPjS_PKjj
jmp .L62
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z13calc_w_sharedPjS_PKjj"
.LC13:
.string "_Z11calc_w_gmemPjS_j"
.LC14:
.string "_Z12calc_w_constPjS_j"
.LC15:
.string "fib_const"
.LC16:
.string "fib_gmem"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2094:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z13calc_w_sharedPjS_PKjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calc_w_gmemPjS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z12calc_w_constPjS_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $48, %r9d
movl $0, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _ZL9fib_const(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $48, %r9d
movl $0, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8fib_gmem(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2094:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL8fib_gmem
.comm _ZL8fib_gmem,48,32
.local _ZL9fib_const
.comm _ZL9fib_const,48,32
.globl N_BLOCKS
.bss
.align 4
.type N_BLOCKS, @object
.size N_BLOCKS, 4
N_BLOCKS:
.zero 4
.globl N_BYTES_ARR
.align 4
.type N_BYTES_ARR, @object
.size N_BYTES_ARR, 4
N_BYTES_ARR:
.zero 4
.globl N_ELEM
.align 4
.type N_ELEM, @object
.size N_ELEM, 4
N_ELEM:
.zero 4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "const_v_shared_test.hip"
.globl _Z10printArrayPjPKcj # -- Begin function _Z10printArrayPjPKcj
.p2align 4, 0x90
.type _Z10printArrayPjPKcj,@function
_Z10printArrayPjPKcj: # @_Z10printArrayPjPKcj
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rdi, %rbx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
testl %ebp, %ebp
je .LBB0_5
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r14d
movl $3435973837, %r15d # imm = 0xCCCCCCCD
xorl %ebp, %ebp
xorl %r12d, %r12d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
movl (%rbx,%r12,4), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
incq %r12
decl %ebp
cmpq %r12, %r14
je .LBB0_5
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %r12d, %eax
imulq %r15, %rax
shrq $36, %rax
leal (%rax,%rax,4), %eax
shll $2, %eax
addl %ebp, %eax
jne .LBB0_4
# %bb.3: # in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB0_4
.LBB0_5: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end0:
.size _Z10printArrayPjPKcj, .Lfunc_end0-_Z10printArrayPjPKcj
.cfi_endproc
# -- End function
.globl _Z8get_timev # -- Begin function _Z8get_timev
.p2align 4, 0x90
.type _Z8get_timev,@function
_Z8get_timev: # @_Z8get_timev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8get_timev, .Lfunc_end1-_Z8get_timev
.cfi_endproc
# -- End function
.globl _Z12genRandArrayPjj # -- Begin function _Z12genRandArrayPjj
.p2align 4, 0x90
.type _Z12genRandArrayPjj,@function
_Z12genRandArrayPjj: # @_Z12genRandArrayPjj
.cfi_startproc
# %bb.0:
testl %esi, %esi
je .LBB2_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movl %esi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r14
jne .LBB2_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB2_4: # %._crit_edge
retq
.Lfunc_end2:
.size _Z12genRandArrayPjj, .Lfunc_end2-_Z12genRandArrayPjj
.cfi_endproc
# -- End function
.globl _Z14genFibSequencePji # -- Begin function _Z14genFibSequencePji
.p2align 4, 0x90
.type _Z14genFibSequencePji,@function
_Z14genFibSequencePji: # @_Z14genFibSequencePji
.cfi_startproc
# %bb.0:
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, (%rdi)
cmpl $3, %esi
jl .LBB3_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
movl 4(%rdi), %ecx
movl $2, %edx
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
addl -8(%rdi,%rdx,4), %ecx
movl %ecx, (%rdi,%rdx,4)
incq %rdx
cmpq %rdx, %rax
jne .LBB3_2
.LBB3_3: # %._crit_edge
retq
.Lfunc_end3:
.size _Z14genFibSequencePji, .Lfunc_end3-_Z14genFibSequencePji
.cfi_endproc
# -- End function
.globl _Z27__device_stub__calc_w_constPjS_j # -- Begin function _Z27__device_stub__calc_w_constPjS_j
.p2align 4, 0x90
.type _Z27__device_stub__calc_w_constPjS_j,@function
_Z27__device_stub__calc_w_constPjS_j: # @_Z27__device_stub__calc_w_constPjS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12calc_w_constPjS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end4:
.size _Z27__device_stub__calc_w_constPjS_j, .Lfunc_end4-_Z27__device_stub__calc_w_constPjS_j
.cfi_endproc
# -- End function
.globl _Z26__device_stub__calc_w_gmemPjS_j # -- Begin function _Z26__device_stub__calc_w_gmemPjS_j
.p2align 4, 0x90
.type _Z26__device_stub__calc_w_gmemPjS_j,@function
_Z26__device_stub__calc_w_gmemPjS_j: # @_Z26__device_stub__calc_w_gmemPjS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11calc_w_gmemPjS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z26__device_stub__calc_w_gmemPjS_j, .Lfunc_end5-_Z26__device_stub__calc_w_gmemPjS_j
.cfi_endproc
# -- End function
.globl _Z28__device_stub__calc_w_sharedPjS_PKjj # -- Begin function _Z28__device_stub__calc_w_sharedPjS_PKjj
.p2align 4, 0x90
.type _Z28__device_stub__calc_w_sharedPjS_PKjj,@function
_Z28__device_stub__calc_w_sharedPjS_PKjj: # @_Z28__device_stub__calc_w_sharedPjS_PKjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13calc_w_sharedPjS_PKjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z28__device_stub__calc_w_sharedPjS_PKjj, .Lfunc_end6-_Z28__device_stub__calc_w_sharedPjS_PKjj
.cfi_endproc
# -- End function
.globl _Z15validate_outputPjS_S_ # -- Begin function _Z15validate_outputPjS_S_
.p2align 4, 0x90
.type _Z15validate_outputPjS_S_,@function
_Z15validate_outputPjS_S_: # @_Z15validate_outputPjS_S_
.cfi_startproc
# %bb.0:
cmpl $0, N_ELEM(%rip)
je .LBB7_1
# %bb.3: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r15
xorl %eax, %eax
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl (%r14,%r12,4), %ecx
cmpl %ecx, %edx
jne .LBB7_6
# %bb.5: # in Loop: Header=BB7_4 Depth=1
cmpl (%rbx,%r12,4), %ecx
je .LBB7_7
.LBB7_6: # in Loop: Header=BB7_4 Depth=1
movl (%rbx,%r12,4), %r8d
movl $.L.str.3, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movb $1, %al
.LBB7_7: # in Loop: Header=BB7_4 Depth=1
incq %r12
movl N_ELEM(%rip), %ecx
cmpq %rcx, %r12
jae .LBB7_9
# %bb.8: # in Loop: Header=BB7_4 Depth=1
movl %eax, %ecx
andb $1, %cl
je .LBB7_4
.LBB7_9: # %._crit_edge
testb $1, %al
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
jmp puts@PLT # TAILCALL
.LBB7_1:
movl $.Lstr, %edi
jmp puts@PLT # TAILCALL
.Lfunc_end7:
.size _Z15validate_outputPjS_S_, .Lfunc_end7-_Z15validate_outputPjS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $2, %edi
jne .LBB8_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $2, %esi
movl %r15d, %ecx
shll %cl, %esi
leal 11(%rsi), %ebp
movl $.L.str.7, %edi
movq %rsi, 48(%rsp) # 8-byte Spill
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $48, %edi
callq malloc
movq %rax, %rbx
movabsq $4294967297, %rax # imm = 0x100000001
movq %rax, (%rbx)
movl $2, %eax
movl $1, %ecx
.p2align 4, 0x90
.LBB8_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
addl -8(%rbx,%rax,4), %ecx
movl %ecx, (%rbx,%rax,4)
incq %rax
cmpq $12, %rax
jne .LBB8_3
# %bb.4: # %_Z14genFibSequencePji.exit
movl $8, %edi
movl %r15d, %ecx
shll %cl, %edi
movl %ebp, %eax
movl $2863311531, %ecx # imm = 0xAAAAAAAB
imulq %rax, %rcx
shrq $35, %rcx
movq %rcx, 136(%rsp) # 8-byte Spill
movq %rdi, %r14
callq malloc
movq %rax, %rbp
cmpl $30, %r15d
ja .LBB8_7
# %bb.5: # %.lr.ph.preheader.i
movl 48(%rsp), %r15d # 4-byte Reload
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB8_6: # %.lr.ph.i62
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbp,%r12,4)
incq %r12
cmpq %r12, %r15
jne .LBB8_6
.LBB8_7: # %_Z12genRandArrayPjj.exit
movq %r14, %rdi
callq malloc
movq %rax, %r15
movq %r14, %rdi
callq malloc
movq %rax, %r12
movq %r14, %rdi
callq malloc
movq %rax, %r13
leaq 56(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 40(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 144(%rsp), %rdi
movl $48, %esi
xorl %edx, %edx
callq hipHostMalloc
movq 56(%rsp), %rdi
movq %rbp, 184(%rsp) # 8-byte Spill
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
movq %rax, 192(%rsp) # 8-byte Spill
movl $fib_const, %edi
movl $48, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl 136(%rsp), %eax # 4-byte Reload
movabsq $4294967308, %rdx # imm = 0x10000000C
leaq (%rax,%rdx), %rbp
addq $-12, %rbp
movq %rbp, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_9
# %bb.8:
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 120(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movq %rsp, %r9
movl $_Z12calc_w_constPjS_j, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_9:
movq 40(%rsp), %rsi
movq %r15, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
movq %rdi, 160(%rsp) # 8-byte Spill
callq hipEventSynchronize
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
movq %rax, 136(%rsp) # 8-byte Spill
movl $_ZL8fib_gmem, %edi
movl $48, %edx
movq %rbx, %rsi
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967308, %rdx # imm = 0x10000000C
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_11
# %bb.10:
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 120(%rsp), %rax
movq %rax, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 16(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movq %rsp, %r9
movl $_Z11calc_w_gmemPjS_j, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_11:
movq 40(%rsp), %rsi
movq %r12, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
movq %rdi, 176(%rsp) # 8-byte Spill
callq hipEventSynchronize
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rax
movq %rax, 168(%rsp) # 8-byte Spill
movq 144(%rsp), %rdi
movl $48, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967308, %rdx # imm = 0x10000000C
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_13
# %bb.12:
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq 144(%rsp), %rdx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq 48(%rsp), %rax # 8-byte Reload
movl %eax, 156(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 120(%rsp), %rax
movq %rax, 8(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 156(%rsp), %rax
movq %rax, 24(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movq %rsp, %r9
movl $_Z13calc_w_sharedPjS_PKjj, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_13:
movq 40(%rsp), %rsi
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq %rsp, %rdi
callq hipEventCreate
movq (%rsp), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
movq %rdi, 48(%rsp) # 8-byte Spill
callq hipEventSynchronize
cmpl $0, N_ELEM(%rip)
je .LBB8_14
# %bb.15: # %.lr.ph.i78.preheader
movq 160(%rsp), %r14 # 8-byte Reload
xorl %eax, %eax
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB8_16: # %.lr.ph.i78
# =>This Inner Loop Header: Depth=1
movl (%r15,%rbp,4), %edx
movl (%r12,%rbp,4), %ecx
cmpl %ecx, %edx
jne .LBB8_18
# %bb.17: # in Loop: Header=BB8_16 Depth=1
cmpl (%r13,%rbp,4), %ecx
je .LBB8_19
.LBB8_18: # in Loop: Header=BB8_16 Depth=1
movl (%r13,%rbp,4), %r8d
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movb $1, %al
.LBB8_19: # in Loop: Header=BB8_16 Depth=1
incq %rbp
movl N_ELEM(%rip), %ecx
cmpq %rcx, %rbp
jae .LBB8_21
# %bb.20: # in Loop: Header=BB8_16 Depth=1
movl %eax, %ecx
andb $1, %cl
je .LBB8_16
.LBB8_21: # %._crit_edge.i
testb $1, %al
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
xorl %ebp, %ebp
jmp .LBB8_22
.LBB8_1:
movq (%rsi), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl $1, %ebp
jmp .LBB8_23
.LBB8_14:
movl $.Lstr, %edi
movq 160(%rsp), %r14 # 8-byte Reload
.LBB8_22: # %_Z15validate_outputPjS_S_.exit
callq puts@PLT
movq 56(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
movq 144(%rsp), %rdi
callq hipFree
movq 184(%rsp), %rdi # 8-byte Reload
callq free
movq %r15, %rdi
callq free
movq %r12, %rdi
callq free
movq %r13, %rdi
callq free
movq %rbx, %rdi
callq free
movl $0, (%rsp)
movq %rsp, %rbx
movq %rbx, %rdi
movq 192(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
movq 136(%rsp), %rsi # 8-byte Reload
movq 176(%rsp), %rdx # 8-byte Reload
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.9, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
movq 168(%rsp), %rsi # 8-byte Reload
movq 48(%rsp), %rdx # 8-byte Reload
callq hipEventElapsedTime
movss (%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.10, %edi
movb $1, %al
callq printf
movl $10, %edi
callq putchar@PLT
.LBB8_23:
movl %ebp, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size main, .Lfunc_end8-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB9_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB9_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12calc_w_constPjS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11calc_w_gmemPjS_j, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13calc_w_sharedPjS_PKjj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $fib_const, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $48, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $0, 8(%rsp)
movl $0, (%rsp)
movl $_ZL8fib_gmem, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $48, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end9:
.size __hip_module_ctor, .Lfunc_end9-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB10_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB10_2:
retq
.Lfunc_end10:
.size __hip_module_dtor, .Lfunc_end10-__hip_module_dtor
.cfi_endproc
# -- End function
.type N_ELEM,@object # @N_ELEM
.bss
.globl N_ELEM
.p2align 2, 0x0
N_ELEM:
.long 0 # 0x0
.size N_ELEM, 4
.type N_BYTES_ARR,@object # @N_BYTES_ARR
.globl N_BYTES_ARR
.p2align 2, 0x0
N_BYTES_ARR:
.long 0 # 0x0
.size N_BYTES_ARR, 4
.type N_BLOCKS,@object # @N_BLOCKS
.globl N_BLOCKS
.p2align 2, 0x0
N_BLOCKS:
.long 0 # 0x0
.size N_BLOCKS, 4
.type fib_const,@object # @fib_const
.local fib_const
.comm fib_const,48,16
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Printing %s array:"
.size .L.str, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%5u"
.size .L.str.2, 4
.type _Z12calc_w_constPjS_j,@object # @_Z12calc_w_constPjS_j
.section .rodata,"a",@progbits
.globl _Z12calc_w_constPjS_j
.p2align 3, 0x0
_Z12calc_w_constPjS_j:
.quad _Z27__device_stub__calc_w_constPjS_j
.size _Z12calc_w_constPjS_j, 8
.type _Z11calc_w_gmemPjS_j,@object # @_Z11calc_w_gmemPjS_j
.globl _Z11calc_w_gmemPjS_j
.p2align 3, 0x0
_Z11calc_w_gmemPjS_j:
.quad _Z26__device_stub__calc_w_gmemPjS_j
.size _Z11calc_w_gmemPjS_j, 8
.type _Z13calc_w_sharedPjS_PKjj,@object # @_Z13calc_w_sharedPjS_PKjj
.globl _Z13calc_w_sharedPjS_PKjj
.p2align 3, 0x0
_Z13calc_w_sharedPjS_PKjj:
.quad _Z28__device_stub__calc_w_sharedPjS_PKjj
.size _Z13calc_w_sharedPjS_PKjj, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "idx=%u: %u, %u, %u\n"
.size .L.str.3, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Usage: %s [arraySizeExponent].\n"
.size .L.str.6, 32
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Running with %u elements in input array...\n"
.size .L.str.7, 44
.type _ZL8fib_gmem,@object # @_ZL8fib_gmem
.local _ZL8fib_gmem
.comm _ZL8fib_gmem,48,16
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tUsing constant memory: elapsed %.3f ms\n"
.size .L.str.8, 41
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tUsing global memory: elapsed %.3f ms\n"
.size .L.str.9, 39
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tUsing shared memory: elapsed %.3f ms\n"
.size .L.str.10, 39
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12calc_w_constPjS_j"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11calc_w_gmemPjS_j"
.size .L__unnamed_2, 21
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13calc_w_sharedPjS_PKjj"
.size .L__unnamed_3, 26
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "fib_const"
.size .L__unnamed_4, 10
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_ZL8fib_gmem"
.size .L__unnamed_5, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Results for all three runs are the identical!"
.size .Lstr, 46
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Some results are different..."
.size .Lstr.1, 30
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__calc_w_constPjS_j
.addrsig_sym _Z26__device_stub__calc_w_gmemPjS_j
.addrsig_sym _Z28__device_stub__calc_w_sharedPjS_PKjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym fib_const
.addrsig_sym _Z12calc_w_constPjS_j
.addrsig_sym _Z11calc_w_gmemPjS_j
.addrsig_sym _Z13calc_w_sharedPjS_PKjj
.addrsig_sym _ZL8fib_gmem
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void gpu_KIDepthToVertices(const float *depthIn,
float4 * vertOut, int *segMap,
const int width,
const int height,
const float2 pp,
const float2 fl) {
const int u = blockIdx.x*blockDim.x + threadIdx.x;
const int v = blockIdx.y*blockDim.y + threadIdx.y;
const int index = u + v*width;
if (u >= width || v >= height)
return;
float depth = depthIn[index];// / 1000.0;
vertOut[index] = make_float4( (u - pp.x)*(depth/fl.x),
(v - pp.y)*(depth/fl.y),
depth,
//segMap[index] == 20 ? 1.0f : 0.0f);
1.0f);
}
void KIDepthToVertices(const float *depthIn, float4 *vertOut, int *segMap
, const int width, const int height, const float2 pp, const float2 fl) {
dim3 block(16,8,1);
dim3 grid( ceil( width / (float)block.x), ceil( height / (float)block.y ));
gpu_KIDepthToVertices<<<grid,block>>>(depthIn, vertOut, segMap
, width, height, pp, fl);
} | code for sm_80
Function : _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R3 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R2, c[0x0][0x178], R5 ; /* 0x00005e0002007a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MUFU.RCP R3, c[0x0][0x188] ; /* 0x0000620000037b08 */
/* 0x000e220000001000 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff087624 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x200 ; /* 0x000000e000007945 */
/* 0x000fec0003800000 */
/*0120*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x000e620000201400 */
/*0130*/ FFMA R8, R3, -R8, 1 ; /* 0x3f80000003087423 */
/* 0x001fc80000000808 */
/*0140*/ FFMA R3, R3, R8, R3 ; /* 0x0000000803037223 */
/* 0x000fe40000000003 */
/*0150*/ FADD R4, R4, -c[0x0][0x180] ; /* 0x8000600004047621 */
/* 0x002fe20000000000 */
/*0160*/ FCHK P0, R6, c[0x0][0x188] ; /* 0x0000620006007b02 */
/* 0x004e220000000000 */
/*0170*/ FFMA R8, R6, R3, RZ ; /* 0x0000000306087223 */
/* 0x000fc800000000ff */
/*0180*/ FFMA R9, R8, -c[0x0][0x188], R6 ; /* 0x8000620008097a23 */
/* 0x000fc80000000006 */
/*0190*/ FFMA R3, R3, R9, R8 ; /* 0x0000000903037223 */
/* 0x000fe20000000008 */
/*01a0*/ @!P0 BRA 0x1f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0c7624 */
/* 0x000fe200078e00ff */
/*01c0*/ MOV R8, 0x1e0 ; /* 0x000001e000087802 */
/* 0x000fe40000000f00 */
/*01d0*/ CALL.REL.NOINC 0x380 ; /* 0x000001a000007944 */
/* 0x000fea0003c00000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x001fe400078e0007 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ MUFU.RCP R7, c[0x0][0x18c] ; /* 0x0000630000077b08 */
/* 0x000e220000001000 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff087624 */
/* 0x000fe200078e00ff */
/*0220*/ BSSY B0, 0x310 ; /* 0x000000e000007945 */
/* 0x000fec0003800000 */
/*0230*/ FCHK P0, R6, c[0x0][0x18c] ; /* 0x0000630006007b02 */
/* 0x000ff00000000000 */
/*0240*/ I2F R5, R2 ; /* 0x0000000200057306 */
/* 0x000e620000201400 */
/*0250*/ FFMA R8, R7, -R8, 1 ; /* 0x3f80000007087423 */
/* 0x001fc80000000808 */
/*0260*/ FFMA R7, R7, R8, R7 ; /* 0x0000000807077223 */
/* 0x000fc80000000007 */
/*0270*/ FFMA R8, R6, R7, RZ ; /* 0x0000000706087223 */
/* 0x000fc800000000ff */
/*0280*/ FFMA R9, R8, -c[0x0][0x18c], R6 ; /* 0x8000630008097a23 */
/* 0x000fe40000000006 */
/*0290*/ FADD R5, R5, -c[0x0][0x184] ; /* 0x8000610005057621 */
/* 0x002fe40000000000 */
/*02a0*/ FFMA R8, R7, R9, R8 ; /* 0x0000000907087223 */
/* 0x000fe20000000008 */
/*02b0*/ @!P0 BRA 0x300 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0c7624 */
/* 0x000fe200078e00ff */
/*02d0*/ MOV R8, 0x2f0 ; /* 0x000002f000087802 */
/* 0x000fe40000000f00 */
/*02e0*/ CALL.REL.NOINC 0x380 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*02f0*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0007 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R9, RZ, RZ, 0x10 ; /* 0x00000010ff097424 */
/* 0x000fe400078e00ff */
/*0320*/ FMUL R4, R4, R3 ; /* 0x0000000304047220 */
/* 0x000fe40000400000 */
/*0330*/ FMUL R5, R5, R8 ; /* 0x0000000805057220 */
/* 0x000fc40000400000 */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fe400078e00ff */
/*0350*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0209 */
/*0360*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101d04 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ SHF.R.U32.HI R10, RZ, 0x17, R12 ; /* 0x00000017ff0a7819 */
/* 0x000fe2000001160c */
/*0390*/ BSSY B1, 0x9d0 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*03a0*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe40000011606 */
/*03b0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fe400078ec0ff */
/*03c0*/ LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070f7812 */
/* 0x000fe200078ec0ff */
/*03d0*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0006 */
/*03e0*/ IADD3 R13, R10, -0x1, RZ ; /* 0xffffffff0a0d7810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ IADD3 R11, R15, -0x1, RZ ; /* 0xffffffff0f0b7810 */
/* 0x000fc40007ffe0ff */
/*0400*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fc80003f04070 */
/*0410*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0420*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0430*/ @!P0 BRA 0x5b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0440*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*0450*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fc80003f3c200 */
/*0460*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0470*/ @P0 BRA 0x9b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0480*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c807 */
/*0490*/ @!P0 BRA 0x990 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*04a0*/ FSETP.NEU.FTZ.AND P2, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f5d200 */
/*04b0*/ FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3d200 */
/*04c0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*04d0*/ @!P1 BRA !P2, 0x990 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*04e0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*04f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0500*/ @P1 BRA 0x970 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0510*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0520*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0530*/ @P0 BRA 0x940 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0550*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0560*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0570*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0580*/ @!P0 FFMA R7, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006078823 */
/* 0x000fe400000000ff */
/*0590*/ @!P1 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c0c9823 */
/* 0x000fe200000000ff */
/*05a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ LEA R11, R10, 0xc0800000, 0x17 ; /* 0xc08000000a0b7811 */
/* 0x000fe200078eb8ff */
/*05c0*/ BSSY B2, 0x930 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*05d0*/ IMAD.IADD R12, R12, 0x1, -R11 ; /* 0x000000010c0c7824 */
/* 0x000fe200078e0a0b */
/*05e0*/ IADD3 R11, R15, -0x7f, RZ ; /* 0xffffff810f0b7810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ MUFU.RCP R13, R12 ; /* 0x0000000c000d7308 */
/* 0x0000620000001000 */
/*0600*/ FADD.FTZ R14, -R12, -RZ ; /* 0x800000ff0c0e7221 */
/* 0x000fe40000010100 */
/*0610*/ IMAD R7, R11.reuse, -0x800000, R7 ; /* 0xff8000000b077824 */
/* 0x040fe200078e0207 */
/*0620*/ IADD3 R12, R11, 0x7f, -R10 ; /* 0x0000007f0b0c7810 */
/* 0x001fca0007ffe80a */
/*0630*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0209 */
/*0640*/ FFMA R16, R13, R14, 1 ; /* 0x3f8000000d107423 */
/* 0x002fc8000000000e */
/*0650*/ FFMA R18, R13, R16, R13 ; /* 0x000000100d127223 */
/* 0x000fc8000000000d */
/*0660*/ FFMA R13, R7, R18, RZ ; /* 0x00000012070d7223 */
/* 0x000fc800000000ff */
/*0670*/ FFMA R16, R14, R13, R7 ; /* 0x0000000d0e107223 */
/* 0x000fc80000000007 */
/*0680*/ FFMA R13, R18, R16, R13 ; /* 0x00000010120d7223 */
/* 0x000fc8000000000d */
/*0690*/ FFMA R14, R14, R13, R7 ; /* 0x0000000d0e0e7223 */
/* 0x000fc80000000007 */
/*06a0*/ FFMA R7, R18, R14, R13 ; /* 0x0000000e12077223 */
/* 0x000fca000000000d */
/*06b0*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fc80000011607 */
/*06c0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fca00078ec0ff */
/*06d0*/ IMAD.IADD R15, R10, 0x1, R12 ; /* 0x000000010a0f7824 */
/* 0x000fca00078e020c */
/*06e0*/ IADD3 R9, R15, -0x1, RZ ; /* 0xffffffff0f097810 */
/* 0x000fc80007ffe0ff */
/*06f0*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0700*/ @!P0 BRA 0x910 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GT.AND P0, PT, R15, 0xfe, PT ; /* 0x000000fe0f00780c */
/* 0x000fda0003f04270 */
/*0720*/ @P0 BRA 0x8e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f06270 */
/*0740*/ @P0 BRA 0x920 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.GE.AND P0, PT, R15, -0x18, PT ; /* 0xffffffe80f00780c */
/* 0x000fe40003f06270 */
/*0760*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0770*/ @!P0 BRA 0x920 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0780*/ FFMA.RZ R9, R18.reuse, R14.reuse, R13.reuse ; /* 0x0000000e12097223 */
/* 0x1c0fe2000000c00d */
/*0790*/ IADD3 R12, R15.reuse, 0x20, RZ ; /* 0x000000200f0c7810 */
/* 0x040fe20007ffe0ff */
/*07a0*/ FFMA.RM R10, R18.reuse, R14.reuse, R13.reuse ; /* 0x0000000e120a7223 */
/* 0x1c0fe2000000400d */
/*07b0*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f45270 */
/*07c0*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*07d0*/ FFMA.RP R9, R18, R14, R13 ; /* 0x0000000e12097223 */
/* 0x000fe2000000800d */
/*07e0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f25270 */
/*07f0*/ IMAD.MOV R13, RZ, RZ, -R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0f */
/*0800*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0810*/ FSETP.NEU.FTZ.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x000fc40003f1d000 */
/*0820*/ SHF.L.U32 R12, R11, R12, RZ ; /* 0x0000000c0b0c7219 */
/* 0x000fe400000006ff */
/*0830*/ SEL R10, R13, RZ, P2 ; /* 0x000000ff0d0a7207 */
/* 0x000fe40001000000 */
/*0840*/ ISETP.NE.AND P1, PT, R12, RZ, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40000f25270 */
/*0850*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0860*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0870*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ; /* 0x00000001ff0c7819 */
/* 0x000fc4000001160a */
/*0880*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0890*/ LOP3.LUT R9, R9, 0x1, R12, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80c */
/*08a0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09097212 */
/* 0x000fca00078ec0ff */
/*08b0*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0209 */
/*08c0*/ LOP3.LUT R7, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c077212 */
/* 0x000fe200078efcff */
/*08d0*/ BRA 0x920 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*08f0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0900*/ BRA 0x920 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0910*/ IMAD R7, R12, 0x800000, R7 ; /* 0x008000000c077824 */
/* 0x000fe400078e0207 */
/*0920*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x9c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fc800078e4807 */
/*0950*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0960*/ BRA 0x9c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0970*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fe200078e4807 */
/*0980*/ BRA 0x9c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0990*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*09a0*/ BRA 0x9c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*09b0*/ FADD.FTZ R7, R6, R12 ; /* 0x0000000c06077221 */
/* 0x000fe40000010000 */
/*09c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*09e0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff61008007950 */
/* 0x000fea0003c3ffff */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void gpu_KIDepthToVertices(const float *depthIn,
float4 * vertOut, int *segMap,
const int width,
const int height,
const float2 pp,
const float2 fl) {
const int u = blockIdx.x*blockDim.x + threadIdx.x;
const int v = blockIdx.y*blockDim.y + threadIdx.y;
const int index = u + v*width;
if (u >= width || v >= height)
return;
float depth = depthIn[index];// / 1000.0;
vertOut[index] = make_float4( (u - pp.x)*(depth/fl.x),
(v - pp.y)*(depth/fl.y),
depth,
//segMap[index] == 20 ? 1.0f : 0.0f);
1.0f);
}
void KIDepthToVertices(const float *depthIn, float4 *vertOut, int *segMap
, const int width, const int height, const float2 pp, const float2 fl) {
dim3 block(16,8,1);
dim3 grid( ceil( width / (float)block.x), ceil( height / (float)block.y ));
gpu_KIDepthToVertices<<<grid,block>>>(depthIn, vertOut, segMap
, width, height, pp, fl);
} | .file "tmpxft_0006bdef_00000000-6_PointCloud.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_
.type _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_, @function
_Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movq %r9, 136(%rsp)
movq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_, .-_Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_
.globl _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_
.type _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_, @function
_Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_:
.LFB2053:
.cfi_startproc
endbr64
subq $32, %rsp
.cfi_def_cfa_offset 40
movq %xmm0, 16(%rsp)
movq %xmm1, 8(%rsp)
leaq 8(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 48
leaq 24(%rsp), %r9
call _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_, .-_Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_
.globl _Z17KIDepthToVerticesPKfP6float4Piii6float2S4_
.type _Z17KIDepthToVerticesPKfP6float4Piii6float2S4_, @function
_Z17KIDepthToVerticesPKfP6float4Piii6float2S4_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movl %r8d, %ebp
movq %xmm0, %r15
movq %xmm1, %r14
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r8d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC5(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC1(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC4(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC5(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC1(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L13
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC3(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L13:
cvttss2siq %xmm4, %rax
movl %eax, 44(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 48(%rsp)
movl $16, 32(%rsp)
movl $8, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq %r15, 16(%rsp)
movq %r14, 24(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 136
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 144
leaq 32(%rsp), %r9
movl %ebp, %r8d
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z17KIDepthToVerticesPKfP6float4Piii6float2S4_, .-_Z17KIDepthToVerticesPKfP6float4Piii6float2S4_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1040187392
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1031798784
.align 4
.LC5:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void gpu_KIDepthToVertices(const float *depthIn,
float4 * vertOut, int *segMap,
const int width,
const int height,
const float2 pp,
const float2 fl) {
const int u = blockIdx.x*blockDim.x + threadIdx.x;
const int v = blockIdx.y*blockDim.y + threadIdx.y;
const int index = u + v*width;
if (u >= width || v >= height)
return;
float depth = depthIn[index];// / 1000.0;
vertOut[index] = make_float4( (u - pp.x)*(depth/fl.x),
(v - pp.y)*(depth/fl.y),
depth,
//segMap[index] == 20 ? 1.0f : 0.0f);
1.0f);
}
void KIDepthToVertices(const float *depthIn, float4 *vertOut, int *segMap
, const int width, const int height, const float2 pp, const float2 fl) {
dim3 block(16,8,1);
dim3 grid( ceil( width / (float)block.x), ceil( height / (float)block.y ));
gpu_KIDepthToVertices<<<grid,block>>>(depthIn, vertOut, segMap
, width, height, pp, fl);
} | #include <hip/hip_runtime.h>
__global__ void gpu_KIDepthToVertices(const float *depthIn,
float4 * vertOut, int *segMap,
const int width,
const int height,
const float2 pp,
const float2 fl) {
const int u = blockIdx.x*blockDim.x + threadIdx.x;
const int v = blockIdx.y*blockDim.y + threadIdx.y;
const int index = u + v*width;
if (u >= width || v >= height)
return;
float depth = depthIn[index];// / 1000.0;
vertOut[index] = make_float4( (u - pp.x)*(depth/fl.x),
(v - pp.y)*(depth/fl.y),
depth,
//segMap[index] == 20 ? 1.0f : 0.0f);
1.0f);
}
void KIDepthToVertices(const float *depthIn, float4 *vertOut, int *segMap
, const int width, const int height, const float2 pp, const float2 fl) {
dim3 block(16,8,1);
dim3 grid( ceil( width / (float)block.x), ceil( height / (float)block.y ));
gpu_KIDepthToVertices<<<grid,block>>>(depthIn, vertOut, segMap
, width, height, pp, fl);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void gpu_KIDepthToVertices(const float *depthIn,
float4 * vertOut, int *segMap,
const int width,
const int height,
const float2 pp,
const float2 fl) {
const int u = blockIdx.x*blockDim.x + threadIdx.x;
const int v = blockIdx.y*blockDim.y + threadIdx.y;
const int index = u + v*width;
if (u >= width || v >= height)
return;
float depth = depthIn[index];// / 1000.0;
vertOut[index] = make_float4( (u - pp.x)*(depth/fl.x),
(v - pp.y)*(depth/fl.y),
depth,
//segMap[index] == 20 ? 1.0f : 0.0f);
1.0f);
}
void KIDepthToVertices(const float *depthIn, float4 *vertOut, int *segMap
, const int width, const int height, const float2 pp, const float2 fl) {
dim3 block(16,8,1);
dim3 grid( ceil( width / (float)block.x), ceil( height / (float)block.y ));
gpu_KIDepthToVertices<<<grid,block>>>(depthIn, vertOut, segMap
, width, height, pp, fl);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.globl _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.p2align 8
.type _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_,@function
_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v2
v_cmp_gt_i32_e64 s2, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v0, s8, v[2:3]
s_load_b128 s[8:11], s[0:1], 0x20
v_cvt_f32_i32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_subrev_f32_e32 v2, s8, v2
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v1, null, s10, s10, v3
v_div_scale_f32 v6, null, s11, s11, v3
v_div_scale_f32 v11, vcc_lo, v3, s10, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v1
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v1, v7, 1.0
v_fma_f32 v10, -v6, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v7, v9, v7 :: v_dual_fmac_f32 v8, v10, v8
v_div_scale_f32 v9, s0, v3, s11, v3
v_mul_f32_e32 v10, v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v12, v9, v8
v_fma_f32 v13, -v1, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, -v6, v12, v9
v_fmac_f32_e32 v10, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v14, v8
v_fma_f32 v1, -v1, v10, v11
v_cvt_f32_i32_e32 v11, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v0, -v6, v12, v9
v_div_fmas_f32 v6, v1, v7, v10
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_div_fmas_f32 v7, v0, v8, v12
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_subrev_f32_e32 v4, s9, v11
v_div_fixup_f32 v8, v6, s10, v3
v_div_fixup_f32 v7, v7, s11, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
v_dual_mul_f32 v1, v2, v8 :: v_dual_mul_f32 v2, v4, v7
v_mov_b32_e32 v4, 1.0
global_store_b128 v[5:6], v[1:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, .Lfunc_end0-_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void gpu_KIDepthToVertices(const float *depthIn,
float4 * vertOut, int *segMap,
const int width,
const int height,
const float2 pp,
const float2 fl) {
const int u = blockIdx.x*blockDim.x + threadIdx.x;
const int v = blockIdx.y*blockDim.y + threadIdx.y;
const int index = u + v*width;
if (u >= width || v >= height)
return;
float depth = depthIn[index];// / 1000.0;
vertOut[index] = make_float4( (u - pp.x)*(depth/fl.x),
(v - pp.y)*(depth/fl.y),
depth,
//segMap[index] == 20 ? 1.0f : 0.0f);
1.0f);
}
void KIDepthToVertices(const float *depthIn, float4 *vertOut, int *segMap
, const int width, const int height, const float2 pp, const float2 fl) {
dim3 block(16,8,1);
dim3 grid( ceil( width / (float)block.x), ceil( height / (float)block.y ));
gpu_KIDepthToVertices<<<grid,block>>>(depthIn, vertOut, segMap
, width, height, pp, fl);
} | .text
.file "PointCloud.hip"
.globl _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_ # -- Begin function _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.p2align 4, 0x90
.type _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_,@function
_Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_: # @_Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, .Lfunc_end0-_Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.LCPI1_0:
.long 0x3d800000 # float 0.0625
.LCPI1_1:
.long 0x3e000000 # float 0.125
.text
.globl _Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.p2align 4, 0x90
.type _Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_,@function
_Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_: # @_Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl %r8d, %ebx
movl %ecx, %ebp
movq %rdx, %r14
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movq %rsi, %r15
movq %rdi, %r12
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
cvttss2si %xmm0, %r13
mulss .LCPI1_1(%rip), %xmm1
movaps %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r13d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 104(%rsp)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 96(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, .Lfunc_end1-_Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_,@object # @_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.section .rodata,"a",@progbits
.globl _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.p2align 3, 0x0
_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_:
.quad _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.size _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_"
.size .L__unnamed_1, 71
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R3 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x178], P0 ; /* 0x00005e0005007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R2, c[0x0][0x178], R5 ; /* 0x00005e0002007a24 */
/* 0x000fc800078e0205 */
/*00d0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fcc00078e0207 */
/*00e0*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ MUFU.RCP R3, c[0x0][0x188] ; /* 0x0000620000037b08 */
/* 0x000e220000001000 */
/*0100*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff087624 */
/* 0x000fe200078e00ff */
/*0110*/ BSSY B0, 0x200 ; /* 0x000000e000007945 */
/* 0x000fec0003800000 */
/*0120*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x000e620000201400 */
/*0130*/ FFMA R8, R3, -R8, 1 ; /* 0x3f80000003087423 */
/* 0x001fc80000000808 */
/*0140*/ FFMA R3, R3, R8, R3 ; /* 0x0000000803037223 */
/* 0x000fe40000000003 */
/*0150*/ FADD R4, R4, -c[0x0][0x180] ; /* 0x8000600004047621 */
/* 0x002fe20000000000 */
/*0160*/ FCHK P0, R6, c[0x0][0x188] ; /* 0x0000620006007b02 */
/* 0x004e220000000000 */
/*0170*/ FFMA R8, R6, R3, RZ ; /* 0x0000000306087223 */
/* 0x000fc800000000ff */
/*0180*/ FFMA R9, R8, -c[0x0][0x188], R6 ; /* 0x8000620008097a23 */
/* 0x000fc80000000006 */
/*0190*/ FFMA R3, R3, R9, R8 ; /* 0x0000000903037223 */
/* 0x000fe20000000008 */
/*01a0*/ @!P0 BRA 0x1f0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*01b0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0c7624 */
/* 0x000fe200078e00ff */
/*01c0*/ MOV R8, 0x1e0 ; /* 0x000001e000087802 */
/* 0x000fe40000000f00 */
/*01d0*/ CALL.REL.NOINC 0x380 ; /* 0x000001a000007944 */
/* 0x000fea0003c00000 */
/*01e0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x001fe400078e0007 */
/*01f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0200*/ MUFU.RCP R7, c[0x0][0x18c] ; /* 0x0000630000077b08 */
/* 0x000e220000001000 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff087624 */
/* 0x000fe200078e00ff */
/*0220*/ BSSY B0, 0x310 ; /* 0x000000e000007945 */
/* 0x000fec0003800000 */
/*0230*/ FCHK P0, R6, c[0x0][0x18c] ; /* 0x0000630006007b02 */
/* 0x000ff00000000000 */
/*0240*/ I2F R5, R2 ; /* 0x0000000200057306 */
/* 0x000e620000201400 */
/*0250*/ FFMA R8, R7, -R8, 1 ; /* 0x3f80000007087423 */
/* 0x001fc80000000808 */
/*0260*/ FFMA R7, R7, R8, R7 ; /* 0x0000000807077223 */
/* 0x000fc80000000007 */
/*0270*/ FFMA R8, R6, R7, RZ ; /* 0x0000000706087223 */
/* 0x000fc800000000ff */
/*0280*/ FFMA R9, R8, -c[0x0][0x18c], R6 ; /* 0x8000630008097a23 */
/* 0x000fe40000000006 */
/*0290*/ FADD R5, R5, -c[0x0][0x184] ; /* 0x8000610005057621 */
/* 0x002fe40000000000 */
/*02a0*/ FFMA R8, R7, R9, R8 ; /* 0x0000000907087223 */
/* 0x000fe20000000008 */
/*02b0*/ @!P0 BRA 0x300 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*02c0*/ IMAD.MOV.U32 R12, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff0c7624 */
/* 0x000fe200078e00ff */
/*02d0*/ MOV R8, 0x2f0 ; /* 0x000002f000087802 */
/* 0x000fe40000000f00 */
/*02e0*/ CALL.REL.NOINC 0x380 ; /* 0x0000009000007944 */
/* 0x000fea0003c00000 */
/*02f0*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0007 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ IMAD.MOV.U32 R9, RZ, RZ, 0x10 ; /* 0x00000010ff097424 */
/* 0x000fe400078e00ff */
/*0320*/ FMUL R4, R4, R3 ; /* 0x0000000304047220 */
/* 0x000fe40000400000 */
/*0330*/ FMUL R5, R5, R8 ; /* 0x0000000805057220 */
/* 0x000fc40000400000 */
/*0340*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3f800000 ; /* 0x3f800000ff077424 */
/* 0x000fe400078e00ff */
/*0350*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0209 */
/*0360*/ STG.E.128 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101d04 */
/*0370*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0380*/ SHF.R.U32.HI R10, RZ, 0x17, R12 ; /* 0x00000017ff0a7819 */
/* 0x000fe2000001160c */
/*0390*/ BSSY B1, 0x9d0 ; /* 0x0000063000017945 */
/* 0x000fe20003800000 */
/*03a0*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe40000011606 */
/*03b0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fe400078ec0ff */
/*03c0*/ LOP3.LUT R15, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff070f7812 */
/* 0x000fe200078ec0ff */
/*03d0*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0006 */
/*03e0*/ IADD3 R13, R10, -0x1, RZ ; /* 0xffffffff0a0d7810 */
/* 0x000fe40007ffe0ff */
/*03f0*/ IADD3 R11, R15, -0x1, RZ ; /* 0xffffffff0f0b7810 */
/* 0x000fc40007ffe0ff */
/*0400*/ ISETP.GT.U32.AND P0, PT, R13, 0xfd, PT ; /* 0x000000fd0d00780c */
/* 0x000fc80003f04070 */
/*0410*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0420*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0430*/ @!P0 BRA 0x5b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0440*/ FSETP.GTU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f1c200 */
/*0450*/ FSETP.GTU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fc80003f3c200 */
/*0460*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0470*/ @P0 BRA 0x9b0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0480*/ LOP3.LUT P0, RZ, R12, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fda000780c807 */
/*0490*/ @!P0 BRA 0x990 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*04a0*/ FSETP.NEU.FTZ.AND P2, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f5d200 */
/*04b0*/ FSETP.NEU.FTZ.AND P1, PT, |R12|, +INF , PT ; /* 0x7f8000000c00780b */
/* 0x000fe40003f3d200 */
/*04c0*/ FSETP.NEU.FTZ.AND P0, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fd60003f1d200 */
/*04d0*/ @!P1 BRA !P2, 0x990 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*04e0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*04f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0500*/ @P1 BRA 0x970 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0510*/ LOP3.LUT P1, RZ, R12, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0cff7812 */
/* 0x000fc8000782c0ff */
/*0520*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0530*/ @P0 BRA 0x940 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0540*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0550*/ ISETP.GE.AND P1, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fd60003f26270 */
/*0560*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0570*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0580*/ @!P0 FFMA R7, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006078823 */
/* 0x000fe400000000ff */
/*0590*/ @!P1 FFMA R12, R12, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000c0c9823 */
/* 0x000fe200000000ff */
/*05a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ LEA R11, R10, 0xc0800000, 0x17 ; /* 0xc08000000a0b7811 */
/* 0x000fe200078eb8ff */
/*05c0*/ BSSY B2, 0x930 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*05d0*/ IMAD.IADD R12, R12, 0x1, -R11 ; /* 0x000000010c0c7824 */
/* 0x000fe200078e0a0b */
/*05e0*/ IADD3 R11, R15, -0x7f, RZ ; /* 0xffffff810f0b7810 */
/* 0x000fc60007ffe0ff */
/*05f0*/ MUFU.RCP R13, R12 ; /* 0x0000000c000d7308 */
/* 0x0000620000001000 */
/*0600*/ FADD.FTZ R14, -R12, -RZ ; /* 0x800000ff0c0e7221 */
/* 0x000fe40000010100 */
/*0610*/ IMAD R7, R11.reuse, -0x800000, R7 ; /* 0xff8000000b077824 */
/* 0x040fe200078e0207 */
/*0620*/ IADD3 R12, R11, 0x7f, -R10 ; /* 0x0000007f0b0c7810 */
/* 0x001fca0007ffe80a */
/*0630*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fe400078e0209 */
/*0640*/ FFMA R16, R13, R14, 1 ; /* 0x3f8000000d107423 */
/* 0x002fc8000000000e */
/*0650*/ FFMA R18, R13, R16, R13 ; /* 0x000000100d127223 */
/* 0x000fc8000000000d */
/*0660*/ FFMA R13, R7, R18, RZ ; /* 0x00000012070d7223 */
/* 0x000fc800000000ff */
/*0670*/ FFMA R16, R14, R13, R7 ; /* 0x0000000d0e107223 */
/* 0x000fc80000000007 */
/*0680*/ FFMA R13, R18, R16, R13 ; /* 0x00000010120d7223 */
/* 0x000fc8000000000d */
/*0690*/ FFMA R14, R14, R13, R7 ; /* 0x0000000d0e0e7223 */
/* 0x000fc80000000007 */
/*06a0*/ FFMA R7, R18, R14, R13 ; /* 0x0000000e12077223 */
/* 0x000fca000000000d */
/*06b0*/ SHF.R.U32.HI R10, RZ, 0x17, R7 ; /* 0x00000017ff0a7819 */
/* 0x000fc80000011607 */
/*06c0*/ LOP3.LUT R10, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0a0a7812 */
/* 0x000fca00078ec0ff */
/*06d0*/ IMAD.IADD R15, R10, 0x1, R12 ; /* 0x000000010a0f7824 */
/* 0x000fca00078e020c */
/*06e0*/ IADD3 R9, R15, -0x1, RZ ; /* 0xffffffff0f097810 */
/* 0x000fc80007ffe0ff */
/*06f0*/ ISETP.GE.U32.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f06070 */
/*0700*/ @!P0 BRA 0x910 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0710*/ ISETP.GT.AND P0, PT, R15, 0xfe, PT ; /* 0x000000fe0f00780c */
/* 0x000fda0003f04270 */
/*0720*/ @P0 BRA 0x8e0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0730*/ ISETP.GE.AND P0, PT, R15, 0x1, PT ; /* 0x000000010f00780c */
/* 0x000fda0003f06270 */
/*0740*/ @P0 BRA 0x920 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0750*/ ISETP.GE.AND P0, PT, R15, -0x18, PT ; /* 0xffffffe80f00780c */
/* 0x000fe40003f06270 */
/*0760*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fd600078ec0ff */
/*0770*/ @!P0 BRA 0x920 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0780*/ FFMA.RZ R9, R18.reuse, R14.reuse, R13.reuse ; /* 0x0000000e12097223 */
/* 0x1c0fe2000000c00d */
/*0790*/ IADD3 R12, R15.reuse, 0x20, RZ ; /* 0x000000200f0c7810 */
/* 0x040fe20007ffe0ff */
/*07a0*/ FFMA.RM R10, R18.reuse, R14.reuse, R13.reuse ; /* 0x0000000e120a7223 */
/* 0x1c0fe2000000400d */
/*07b0*/ ISETP.NE.AND P2, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f45270 */
/*07c0*/ LOP3.LUT R11, R9, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff090b7812 */
/* 0x000fe200078ec0ff */
/*07d0*/ FFMA.RP R9, R18, R14, R13 ; /* 0x0000000e12097223 */
/* 0x000fe2000000800d */
/*07e0*/ ISETP.NE.AND P1, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f25270 */
/*07f0*/ IMAD.MOV R13, RZ, RZ, -R15 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0a0f */
/*0800*/ LOP3.LUT R11, R11, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000b0b7812 */
/* 0x000fe400078efcff */
/*0810*/ FSETP.NEU.FTZ.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720b */
/* 0x000fc40003f1d000 */
/*0820*/ SHF.L.U32 R12, R11, R12, RZ ; /* 0x0000000c0b0c7219 */
/* 0x000fe400000006ff */
/*0830*/ SEL R10, R13, RZ, P2 ; /* 0x000000ff0d0a7207 */
/* 0x000fe40001000000 */
/*0840*/ ISETP.NE.AND P1, PT, R12, RZ, P1 ; /* 0x000000ff0c00720c */
/* 0x000fe40000f25270 */
/*0850*/ SHF.R.U32.HI R10, RZ, R10, R11 ; /* 0x0000000aff0a7219 */
/* 0x000fe4000001160b */
/*0860*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0870*/ SHF.R.U32.HI R12, RZ, 0x1, R10 ; /* 0x00000001ff0c7819 */
/* 0x000fc4000001160a */
/*0880*/ SEL R9, RZ, 0x1, !P0 ; /* 0x00000001ff097807 */
/* 0x000fc80004000000 */
/*0890*/ LOP3.LUT R9, R9, 0x1, R12, 0xf8, !PT ; /* 0x0000000109097812 */
/* 0x000fc800078ef80c */
/*08a0*/ LOP3.LUT R9, R9, R10, RZ, 0xc0, !PT ; /* 0x0000000a09097212 */
/* 0x000fca00078ec0ff */
/*08b0*/ IMAD.IADD R12, R12, 0x1, R9 ; /* 0x000000010c0c7824 */
/* 0x000fca00078e0209 */
/*08c0*/ LOP3.LUT R7, R12, R7, RZ, 0xfc, !PT ; /* 0x000000070c077212 */
/* 0x000fe200078efcff */
/*08d0*/ BRA 0x920 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*08e0*/ LOP3.LUT R7, R7, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000007077812 */
/* 0x000fc800078ec0ff */
/*08f0*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0900*/ BRA 0x920 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0910*/ IMAD R7, R12, 0x800000, R7 ; /* 0x008000000c077824 */
/* 0x000fe400078e0207 */
/*0920*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0930*/ BRA 0x9c0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0940*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fc800078e4807 */
/*0950*/ LOP3.LUT R7, R7, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000007077812 */
/* 0x000fe200078efcff */
/*0960*/ BRA 0x9c0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0970*/ LOP3.LUT R7, R12, 0x80000000, R7, 0x48, !PT ; /* 0x800000000c077812 */
/* 0x000fe200078e4807 */
/*0980*/ BRA 0x9c0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0990*/ MUFU.RSQ R7, -QNAN ; /* 0xffc0000000077908 */
/* 0x000e220000001400 */
/*09a0*/ BRA 0x9c0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*09b0*/ FADD.FTZ R7, R6, R12 ; /* 0x0000000c06077221 */
/* 0x000fe40000010000 */
/*09c0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x0 ; /* 0x00000000ff097424 */
/* 0x000fc800078e00ff */
/*09e0*/ RET.REL.NODEC R8 0x0 ; /* 0xfffff61008007950 */
/* 0x000fea0003c3ffff */
/*09f0*/ BRA 0x9f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.globl _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.p2align 8
.type _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_,@function
_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v2
v_cmp_gt_i32_e64 s2, s9, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[4:5], null, v0, s8, v[2:3]
s_load_b128 s[8:11], s[0:1], 0x20
v_cvt_f32_i32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_subrev_f32_e32 v2, s8, v2
global_load_b32 v3, v[6:7], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v1, null, s10, s10, v3
v_div_scale_f32 v6, null, s11, s11, v3
v_div_scale_f32 v11, vcc_lo, v3, s10, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v1
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v1, v7, 1.0
v_fma_f32 v10, -v6, v8, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v7, v9, v7 :: v_dual_fmac_f32 v8, v10, v8
v_div_scale_f32 v9, s0, v3, s11, v3
v_mul_f32_e32 v10, v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v12, v9, v8
v_fma_f32 v13, -v1, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, -v6, v12, v9
v_fmac_f32_e32 v10, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v14, v8
v_fma_f32 v1, -v1, v10, v11
v_cvt_f32_i32_e32 v11, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v0, -v6, v12, v9
v_div_fmas_f32 v6, v1, v7, v10
s_mov_b32 vcc_lo, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_div_fmas_f32 v7, v0, v8, v12
v_lshlrev_b64 v[0:1], 4, v[4:5]
v_subrev_f32_e32 v4, s9, v11
v_div_fixup_f32 v8, v6, s10, v3
v_div_fixup_f32 v7, v7, s11, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v1, vcc_lo
v_dual_mul_f32 v1, v2, v8 :: v_dual_mul_f32 v2, v4, v7
v_mov_b32_e32 v4, 1.0
global_store_b128 v[5:6], v[1:4], off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, .Lfunc_end0-_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006bdef_00000000-6_PointCloud.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_
.type _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_, @function
_Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_:
.LFB2052:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movq %r9, 136(%rsp)
movq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_, .-_Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_
.globl _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_
.type _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_, @function
_Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_:
.LFB2053:
.cfi_startproc
endbr64
subq $32, %rsp
.cfi_def_cfa_offset 40
movq %xmm0, 16(%rsp)
movq %xmm1, 8(%rsp)
leaq 8(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 48
leaq 24(%rsp), %r9
call _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_, .-_Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_
.globl _Z17KIDepthToVerticesPKfP6float4Piii6float2S4_
.type _Z17KIDepthToVerticesPKfP6float4Piii6float2S4_, @function
_Z17KIDepthToVerticesPKfP6float4Piii6float2S4_:
.LFB2027:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movl %r8d, %ebp
movq %xmm0, %r15
movq %xmm1, %r14
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, 40(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r8d, %xmm0
mulss .LC0(%rip), %xmm0
movaps %xmm0, %xmm1
movss .LC5(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC1(%rip), %xmm4
ucomiss %xmm2, %xmm4
jbe .L12
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm1
movss .LC3(%rip), %xmm4
andps %xmm4, %xmm1
addss %xmm2, %xmm1
andnps %xmm0, %xmm3
orps %xmm3, %xmm1
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
mulss .LC4(%rip), %xmm0
movaps %xmm0, %xmm4
movss .LC5(%rip), %xmm3
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
movss .LC1(%rip), %xmm5
ucomiss %xmm2, %xmm5
jbe .L13
cvttss2sil %xmm0, %eax
pxor %xmm2, %xmm2
cvtsi2ssl %eax, %xmm2
cmpnless %xmm2, %xmm4
movss .LC3(%rip), %xmm5
andps %xmm5, %xmm4
addss %xmm2, %xmm4
andnps %xmm0, %xmm3
orps %xmm3, %xmm4
.L13:
cvttss2siq %xmm4, %rax
movl %eax, 44(%rsp)
cvttss2siq %xmm1, %rax
movl %eax, 48(%rsp)
movl $16, 32(%rsp)
movl $8, 36(%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L11:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq %r15, 16(%rsp)
movq %r14, 24(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 136
leaq 32(%rsp), %rax
pushq %rax
.cfi_def_cfa_offset 144
leaq 32(%rsp), %r9
movl %ebp, %r8d
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 24(%rsp), %rdi
call _Z64__device_stub__Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_PKfP6float4PiiiRK6float2S6_
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size _Z17KIDepthToVerticesPKfP6float4Piii6float2S4_, .-_Z17KIDepthToVerticesPKfP6float4Piii6float2S4_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "_Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z21gpu_KIDepthToVerticesPKfP6float4Piii6float2S4_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1040187392
.align 4
.LC1:
.long 1258291200
.align 4
.LC3:
.long 1065353216
.align 4
.LC4:
.long 1031798784
.align 4
.LC5:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "PointCloud.hip"
.globl _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_ # -- Begin function _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.p2align 4, 0x90
.type _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_,@function
_Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_: # @_Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movsd %xmm0, 88(%rsp)
movsd %xmm1, 80(%rsp)
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, .Lfunc_end0-_Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.LCPI1_0:
.long 0x3d800000 # float 0.0625
.LCPI1_1:
.long 0x3e000000 # float 0.125
.text
.globl _Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.p2align 4, 0x90
.type _Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_,@function
_Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_: # @_Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movsd %xmm1, 16(%rsp) # 8-byte Spill
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl %r8d, %ebx
movl %ecx, %ebp
movq %rdx, %r14
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movq %rsi, %r15
movq %rdi, %r12
mulss .LCPI1_0(%rip), %xmm0
callq ceilf@PLT
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
cvttss2si %xmm0, %r13
mulss .LCPI1_1(%rip), %xmm1
movaps %xmm1, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %rdi
movl %r13d, %eax
shlq $32, %rdi
orq %rax, %rdi
movabsq $34359738384, %rdx # imm = 0x800000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 104(%rsp)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movsd %xmm0, 96(%rsp)
movq %r12, 88(%rsp)
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movl %ebp, 4(%rsp)
movl %ebx, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
movq %rsp, %rax
movq %rax, 144(%rsp)
leaq 104(%rsp), %rax
movq %rax, 152(%rsp)
leaq 96(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, .Lfunc_end1-_Z17KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_,@object # @_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.section .rodata,"a",@progbits
.globl _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.p2align 3, 0x0
_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_:
.quad _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.size _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_"
.size .L__unnamed_1, 71
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21gpu_KIDepthToVerticesPKfP15HIP_vector_typeIfLj4EEPiiiS1_IfLj2EES5_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gaxpy(double *y, double *a, double *x, int m, int n){
int bid = blockIdx.x;
int tid = threadIdx.x;
extern __shared__ double dots_s[];
if(bid<m)
if(tid<n){
dots_s[bid*n+tid] = a[bid*n+tid] * *(x+tid);
__syncthreads();
if(tid == 0){
for(int i=1;i<n;i++){
dots_s[bid*n] +=dots_s[bid*n+i];
// printf("y=%d, dots_s=%d, bid=%d, tid=%d, i=%d, n=%d\n",dots_s[bid*n], dots_s[bid*n+i],bid,tid,i,n);
}
*(y+bid)=dots_s[bid*n];
// printf("y[%d]=%d, bid=%d, tid=%d\n",bid,y[bid],bid,tid);
}
}
} | code for sm_80
Function : _Z5gaxpyPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0030*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x001fc80003f06270 */
/*0040*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x002fda0000706670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R2, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000027a24 */
/* 0x000fe200078e02ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.IADD R10, R2, 0x1, R8 ; /* 0x00000001020a7824 */
/* 0x000fe400078e0208 */
/*00a0*/ IMAD.WIDE R6, R8, R3, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R4, R10, R3, c[0x0][0x168] ; /* 0x00005a000a047625 */
/* 0x000fe400078e0203 */
/*00c0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1b00 */
/*00d0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*00f0*/ DMUL R8, R6, R4 ; /* 0x0000000406087228 */
/* 0x004e0e0000000000 */
/*0100*/ STS.64 [R10.X8], R8 ; /* 0x000000080a007388 */
/* 0x0011e80000008a00 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.SHL.U32 R4, R2, 0x8, RZ ; /* 0x0000000802047824 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fc600078e00ff */
/*0150*/ LDS.64 R22, [R4] ; /* 0x0000000004167984 */
/* 0x0000640000000a00 */
/*0160*/ ISETP.GE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fda0003f06270 */
/*0170*/ @!P0 BRA 0x7e0 ; /* 0x0000066000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R5, R6.reuse, -0x2, RZ ; /* 0xfffffffe06057810 */
/* 0x041fe20007ffe0ff */
/*0190*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*01a0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*01c0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fd600078ec0ff */
/*01d0*/ @!P0 BRA 0x730 ; /* 0x0000055000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R7, -R6, c[0x0][0x17c], RZ ; /* 0x00005f0006077a10 */
/* 0x000fe20007ffe1ff */
/*01f0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0200*/ IADD3 R5, R4, 0x20, RZ ; /* 0x0000002004057810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04270 */
/*0220*/ @!P0 BRA 0x660 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0250*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*0260*/ @!P1 BRA 0x4d0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0280*/ LDS.64 R20, [R5+-0x18] ; /* 0xffffe80005147984 */
/* 0x001e220000000a00 */
/*0290*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*02b0*/ LDS.64 R10, [R5+-0x10] ; /* 0xfffff000050a7984 */
/* 0x000ea20000000a00 */
/*02c0*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fc60003f24270 */
/*02d0*/ LDS.64 R18, [R5+-0x8] ; /* 0xfffff80005127984 */
/* 0x000ee80000000a00 */
/*02e0*/ LDS.64 R16, [R5] ; /* 0x0000000005107984 */
/* 0x000f280000000a00 */
/*02f0*/ LDS.64 R14, [R5+0x8] ; /* 0x00000800050e7984 */
/* 0x000f680000000a00 */
/*0300*/ LDS.64 R12, [R5+0x10] ; /* 0x00001000050c7984 */
/* 0x002e680000000a00 */
/*0310*/ LDS.64 R8, [R5+0x18] ; /* 0x0000180005087984 */
/* 0x000e640000000a00 */
/*0320*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0030840000000016 */
/*0330*/ LDS.64 R20, [R5+0x20] ; /* 0x0000200005147984 */
/* 0x001e280000000a00 */
/*0340*/ DADD R10, R22, R10 ; /* 0x00000000160a7229 */
/* 0x0042c8000000000a */
/*0350*/ LDS.64 R22, [R5+0x28] ; /* 0x0000280005167984 */
/* 0x002e640000000a00 */
/*0360*/ DADD R18, R10, R18 ; /* 0x000000000a127229 */
/* 0x0085080000000012 */
/*0370*/ LDS.64 R10, [R5+0x30] ; /* 0x00003000050a7984 */
/* 0x004ea40000000a00 */
/*0380*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x0107480000000010 */
/*0390*/ LDS.64 R18, [R5+0x38] ; /* 0x0000380005127984 */
/* 0x008ee40000000a00 */
/*03a0*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x020948000000000e */
/*03b0*/ LDS.64 R16, [R5+0x40] ; /* 0x0000400005107984 */
/* 0x010f240000000a00 */
/*03c0*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x020b48000000000c */
/*03d0*/ LDS.64 R14, [R5+0x48] ; /* 0x00004800050e7984 */
/* 0x020f640000000a00 */
/*03e0*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x0000080000000008 */
/*03f0*/ LDS.64 R12, [R5+0x50] ; /* 0x00005000050c7984 */
/* 0x001e240000000a00 */
/*0400*/ DADD R20, R8, R20 ; /* 0x0000000008147229 */
/* 0x0002480000000014 */
/*0410*/ LDS.64 R8, [R5+0x58] ; /* 0x0000580005087984 */
/* 0x002e640000000a00 */
/*0420*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0004880000000016 */
/*0430*/ LDS.64 R20, [R5+0x60] ; /* 0x0000600005147984 */
/* 0x0044640000000a00 */
/*0440*/ DADD R10, R22, R10 ; /* 0x00000000160a7229 */
/* 0x000ee2000000000a */
/*0450*/ IADD3 R5, R5, 0x80, RZ ; /* 0x0000008005057810 */
/* 0x004fca0007ffe0ff */
/*0460*/ DADD R10, R10, R18 ; /* 0x000000000a0a7229 */
/* 0x008f0c0000000012 */
/*0470*/ DADD R10, R10, R16 ; /* 0x000000000a0a7229 */
/* 0x010f4c0000000010 */
/*0480*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x020e0c000000000e */
/*0490*/ DADD R10, R10, R12 ; /* 0x000000000a0a7229 */
/* 0x001e4c000000000c */
/*04a0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e0c0000000008 */
/*04b0*/ DADD R22, R8, R20 ; /* 0x0000000008167229 */
/* 0x0010620000000014 */
/*04c0*/ @P1 BRA 0x280 ; /* 0xfffffdb000001947 */
/* 0x000fea000383ffff */
/*04d0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x001fc80007ffe0ff */
/*04e0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*04f0*/ @!P1 BRA 0x640 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0500*/ LDS.64 R20, [R5+-0x18] ; /* 0xffffe80005147984 */
/* 0x000e220000000a00 */
/*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0520*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0530*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0540*/ LDS.64 R8, [R5+-0x10] ; /* 0xfffff00005087984 */
/* 0x000ea80000000a00 */
/*0550*/ LDS.64 R10, [R5+-0x8] ; /* 0xfffff800050a7984 */
/* 0x000ee80000000a00 */
/*0560*/ LDS.64 R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000f280000000a00 */
/*0570*/ LDS.64 R14, [R5+0x8] ; /* 0x00000800050e7984 */
/* 0x000f680000000a00 */
/*0580*/ LDS.64 R16, [R5+0x10] ; /* 0x0000100005107984 */
/* 0x000e680000000a00 */
/*0590*/ LDS.64 R18, [R5+0x18] ; /* 0x0000180005127984 */
/* 0x000e640000000a00 */
/*05a0*/ DADD R20, R22, R20 ; /* 0x0000000016147229 */
/* 0x0030840000000014 */
/*05b0*/ LDS.64 R22, [R5+0x20] ; /* 0x0000200005167984 */
/* 0x0010680000000a00 */
/*05c0*/ DADD R8, R20, R8 ; /* 0x0000000014087229 */
/* 0x004ee20000000008 */
/*05d0*/ IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005057810 */
/* 0x001fca0007ffe0ff */
/*05e0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x008f0c000000000a */
/*05f0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x010f4c000000000c */
/*0600*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x020e0c000000000e */
/*0610*/ DADD R8, R8, R16 ; /* 0x0000000008087229 */
/* 0x001e0c0000000010 */
/*0620*/ DADD R8, R8, R18 ; /* 0x0000000008087229 */
/* 0x001e4c0000000012 */
/*0630*/ DADD R22, R8, R22 ; /* 0x0000000008167229 */
/* 0x0020480000000016 */
/*0640*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0650*/ @!P0 BRA 0x730 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0660*/ LDS.64 R10, [R5+-0x18] ; /* 0xffffe800050a7984 */
/* 0x000ea20000000a00 */
/*0670*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0680*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0690*/ LDS.64 R12, [R5+-0x10] ; /* 0xfffff000050c7984 */
/* 0x000ee20000000a00 */
/*06a0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fc60003f05270 */
/*06b0*/ LDS.64 R14, [R5+-0x8] ; /* 0xfffff800050e7984 */
/* 0x000f280000000a00 */
/*06c0*/ LDS.64 R8, [R5] ; /* 0x0000000005087984 */
/* 0x0011640000000a00 */
/*06d0*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x001fe20007ffe0ff */
/*06e0*/ DADD R10, R10, R22 ; /* 0x000000000a0a7229 */
/* 0x006ecc0000000016 */
/*06f0*/ DADD R10, R10, R12 ; /* 0x000000000a0a7229 */
/* 0x008f0c000000000c */
/*0700*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x010f4c000000000e */
/*0710*/ DADD R22, R10, R8 ; /* 0x000000000a167229 */
/* 0x0200640000000008 */
/*0720*/ @P0 BRA 0x660 ; /* 0xffffff3000000947 */
/* 0x003fea000383ffff */
/*0730*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0740*/ @!P0 BRA 0x7d0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R2, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x000fca000fffe0ff */
/*0760*/ IMAD.SHL.U32 R2, R2, 0x8, RZ ; /* 0x0000000802027824 */
/* 0x000fca00078e00ff */
/*0770*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x0010a20000000a00 */
/*0780*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fc80007ffe0ff */
/*0790*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*07a0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x001fe20007ffe0ff */
/*07b0*/ DADD R22, R8, R22 ; /* 0x0000000008167229 */
/* 0x0060540000000016 */
/*07c0*/ @P0 BRA 0x770 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*07d0*/ STS.64 [R4], R22 ; /* 0x0000001604007388 */
/* 0x0023e40000000a00 */
/*07e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*07f0*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x002fe2000c101b06 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gaxpy(double *y, double *a, double *x, int m, int n){
int bid = blockIdx.x;
int tid = threadIdx.x;
extern __shared__ double dots_s[];
if(bid<m)
if(tid<n){
dots_s[bid*n+tid] = a[bid*n+tid] * *(x+tid);
__syncthreads();
if(tid == 0){
for(int i=1;i<n;i++){
dots_s[bid*n] +=dots_s[bid*n+i];
// printf("y=%d, dots_s=%d, bid=%d, tid=%d, i=%d, n=%d\n",dots_s[bid*n], dots_s[bid*n+i],bid,tid,i,n);
}
*(y+bid)=dots_s[bid*n];
// printf("y[%d]=%d, bid=%d, tid=%d\n",bid,y[bid],bid,tid);
}
}
} | .file "tmpxft_00103964_00000000-6_gaxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii
.type _Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii, @function
_Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5gaxpyPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii, .-_Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii
.globl _Z5gaxpyPdS_S_ii
.type _Z5gaxpyPdS_S_ii, @function
_Z5gaxpyPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5gaxpyPdS_S_ii, .-_Z5gaxpyPdS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5gaxpyPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5gaxpyPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gaxpy(double *y, double *a, double *x, int m, int n){
int bid = blockIdx.x;
int tid = threadIdx.x;
extern __shared__ double dots_s[];
if(bid<m)
if(tid<n){
dots_s[bid*n+tid] = a[bid*n+tid] * *(x+tid);
__syncthreads();
if(tid == 0){
for(int i=1;i<n;i++){
dots_s[bid*n] +=dots_s[bid*n+i];
// printf("y=%d, dots_s=%d, bid=%d, tid=%d, i=%d, n=%d\n",dots_s[bid*n], dots_s[bid*n+i],bid,tid,i,n);
}
*(y+bid)=dots_s[bid*n];
// printf("y[%d]=%d, bid=%d, tid=%d\n",bid,y[bid],bid,tid);
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gaxpy(double *y, double *a, double *x, int m, int n){
int bid = blockIdx.x;
int tid = threadIdx.x;
extern __shared__ double dots_s[];
if(bid<m)
if(tid<n){
dots_s[bid*n+tid] = a[bid*n+tid] * *(x+tid);
__syncthreads();
if(tid == 0){
for(int i=1;i<n;i++){
dots_s[bid*n] +=dots_s[bid*n+i];
// printf("y=%d, dots_s=%d, bid=%d, tid=%d, i=%d, n=%d\n",dots_s[bid*n], dots_s[bid*n+i],bid,tid,i,n);
}
*(y+bid)=dots_s[bid*n];
// printf("y[%d]=%d, bid=%d, tid=%d\n",bid,y[bid],bid,tid);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gaxpy(double *y, double *a, double *x, int m, int n){
int bid = blockIdx.x;
int tid = threadIdx.x;
extern __shared__ double dots_s[];
if(bid<m)
if(tid<n){
dots_s[bid*n+tid] = a[bid*n+tid] * *(x+tid);
__syncthreads();
if(tid == 0){
for(int i=1;i<n;i++){
dots_s[bid*n] +=dots_s[bid*n+i];
// printf("y=%d, dots_s=%d, bid=%d, tid=%d, i=%d, n=%d\n",dots_s[bid*n], dots_s[bid*n+i],bid,tid,i,n);
}
*(y+bid)=dots_s[bid*n];
// printf("y[%d]=%d, bid=%d, tid=%d\n",bid,y[bid],bid,tid);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5gaxpyPdS_S_ii
.globl _Z5gaxpyPdS_S_ii
.p2align 8
.type _Z5gaxpyPdS_S_ii,@function
_Z5gaxpyPdS_S_ii:
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_cmp_lt_i32 s15, s4
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_7
s_load_b128 s[8:11], s[0:1], 0x8
s_mul_i32 s3, s15, s5
v_lshlrev_b32_e32 v4, 3, v0
v_add_nc_u32_e32 v1, s3, v0
s_mov_b32 s2, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_lshl_add_u32 v1, v1, 3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
global_load_b64 v[4:5], v4, s[10:11]
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_cmp_lt_i32 s5, 2
s_cbranch_scc1 .LBB0_6
s_lshl_b32 s4, s3, 3
s_add_i32 s5, s5, -1
s_add_i32 s4, s4, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v0, s4
s_add_i32 s6, s4, 8
ds_load_b64 v[0:1], v0
.LBB0_4:
v_mov_b32_e32 v2, s6
s_add_i32 s5, s5, -1
s_add_i32 s6, s6, 8
s_cmp_eq_u32 s5, 0
ds_load_b64 v[2:3], v2
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], v[2:3], v[0:1]
s_cbranch_scc0 .LBB0_4
v_mov_b32_e32 v2, s4
ds_store_b64 v2, v[0:1]
.LBB0_6:
s_lshl_b32 s3, s3, 3
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s3, s3, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v0, s3
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 3
ds_load_b64 v[0:1], v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5gaxpyPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5gaxpyPdS_S_ii, .Lfunc_end0-_Z5gaxpyPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5gaxpyPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5gaxpyPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gaxpy(double *y, double *a, double *x, int m, int n){
int bid = blockIdx.x;
int tid = threadIdx.x;
extern __shared__ double dots_s[];
if(bid<m)
if(tid<n){
dots_s[bid*n+tid] = a[bid*n+tid] * *(x+tid);
__syncthreads();
if(tid == 0){
for(int i=1;i<n;i++){
dots_s[bid*n] +=dots_s[bid*n+i];
// printf("y=%d, dots_s=%d, bid=%d, tid=%d, i=%d, n=%d\n",dots_s[bid*n], dots_s[bid*n+i],bid,tid,i,n);
}
*(y+bid)=dots_s[bid*n];
// printf("y[%d]=%d, bid=%d, tid=%d\n",bid,y[bid],bid,tid);
}
}
} | .text
.file "gaxpy.hip"
.globl _Z20__device_stub__gaxpyPdS_S_ii # -- Begin function _Z20__device_stub__gaxpyPdS_S_ii
.p2align 4, 0x90
.type _Z20__device_stub__gaxpyPdS_S_ii,@function
_Z20__device_stub__gaxpyPdS_S_ii: # @_Z20__device_stub__gaxpyPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5gaxpyPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__gaxpyPdS_S_ii, .Lfunc_end0-_Z20__device_stub__gaxpyPdS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5gaxpyPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5gaxpyPdS_S_ii,@object # @_Z5gaxpyPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z5gaxpyPdS_S_ii
.p2align 3, 0x0
_Z5gaxpyPdS_S_ii:
.quad _Z20__device_stub__gaxpyPdS_S_ii
.size _Z5gaxpyPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5gaxpyPdS_S_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__gaxpyPdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5gaxpyPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5gaxpyPdS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e280000002100 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e620000002500 */
/*0030*/ ISETP.GE.AND P0, PT, R8, c[0x0][0x17c], PT ; /* 0x00005f0008007a0c */
/* 0x001fc80003f06270 */
/*0040*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x002fda0000706670 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD R2, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000027a24 */
/* 0x000fe200078e02ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.IADD R10, R2, 0x1, R8 ; /* 0x00000001020a7824 */
/* 0x000fe400078e0208 */
/*00a0*/ IMAD.WIDE R6, R8, R3, c[0x0][0x170] ; /* 0x00005c0008067625 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R4, R10, R3, c[0x0][0x168] ; /* 0x00005a000a047625 */
/* 0x000fe400078e0203 */
/*00c0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1b00 */
/*00d0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*00f0*/ DMUL R8, R6, R4 ; /* 0x0000000406087228 */
/* 0x004e0e0000000000 */
/*0100*/ STS.64 [R10.X8], R8 ; /* 0x000000080a007388 */
/* 0x0011e80000008a00 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ IMAD.SHL.U32 R4, R2, 0x8, RZ ; /* 0x0000000802047824 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff067624 */
/* 0x000fc600078e00ff */
/*0150*/ LDS.64 R22, [R4] ; /* 0x0000000004167984 */
/* 0x0000640000000a00 */
/*0160*/ ISETP.GE.AND P0, PT, R6, 0x2, PT ; /* 0x000000020600780c */
/* 0x000fda0003f06270 */
/*0170*/ @!P0 BRA 0x7e0 ; /* 0x0000066000008947 */
/* 0x000fea0003800000 */
/*0180*/ IADD3 R5, R6.reuse, -0x2, RZ ; /* 0xfffffffe06057810 */
/* 0x041fe20007ffe0ff */
/*0190*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*01a0*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fe40003f06070 */
/*01c0*/ LOP3.LUT R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fd600078ec0ff */
/*01d0*/ @!P0 BRA 0x730 ; /* 0x0000055000008947 */
/* 0x000fea0003800000 */
/*01e0*/ IADD3 R7, -R6, c[0x0][0x17c], RZ ; /* 0x00005f0006077a10 */
/* 0x000fe20007ffe1ff */
/*01f0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*0200*/ IADD3 R5, R4, 0x20, RZ ; /* 0x0000002004057810 */
/* 0x000fe40007ffe0ff */
/*0210*/ ISETP.GT.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fda0003f04270 */
/*0220*/ @!P0 BRA 0x660 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0230*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x000fe40007ffe0ff */
/*0240*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0250*/ ISETP.GT.AND P1, PT, R8, 0xc, PT ; /* 0x0000000c0800780c */
/* 0x000fda0003f24270 */
/*0260*/ @!P1 BRA 0x4d0 ; /* 0x0000026000009947 */
/* 0x000fea0003800000 */
/*0270*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0280*/ LDS.64 R20, [R5+-0x18] ; /* 0xffffe80005147984 */
/* 0x001e220000000a00 */
/*0290*/ IADD3 R7, R7, -0x10, RZ ; /* 0xfffffff007077810 */
/* 0x000fe20007ffe0ff */
/*02a0*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe4000fffe03f */
/*02b0*/ LDS.64 R10, [R5+-0x10] ; /* 0xfffff000050a7984 */
/* 0x000ea20000000a00 */
/*02c0*/ ISETP.GT.AND P1, PT, R7, 0xd, PT ; /* 0x0000000d0700780c */
/* 0x000fc60003f24270 */
/*02d0*/ LDS.64 R18, [R5+-0x8] ; /* 0xfffff80005127984 */
/* 0x000ee80000000a00 */
/*02e0*/ LDS.64 R16, [R5] ; /* 0x0000000005107984 */
/* 0x000f280000000a00 */
/*02f0*/ LDS.64 R14, [R5+0x8] ; /* 0x00000800050e7984 */
/* 0x000f680000000a00 */
/*0300*/ LDS.64 R12, [R5+0x10] ; /* 0x00001000050c7984 */
/* 0x002e680000000a00 */
/*0310*/ LDS.64 R8, [R5+0x18] ; /* 0x0000180005087984 */
/* 0x000e640000000a00 */
/*0320*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0030840000000016 */
/*0330*/ LDS.64 R20, [R5+0x20] ; /* 0x0000200005147984 */
/* 0x001e280000000a00 */
/*0340*/ DADD R10, R22, R10 ; /* 0x00000000160a7229 */
/* 0x0042c8000000000a */
/*0350*/ LDS.64 R22, [R5+0x28] ; /* 0x0000280005167984 */
/* 0x002e640000000a00 */
/*0360*/ DADD R18, R10, R18 ; /* 0x000000000a127229 */
/* 0x0085080000000012 */
/*0370*/ LDS.64 R10, [R5+0x30] ; /* 0x00003000050a7984 */
/* 0x004ea40000000a00 */
/*0380*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x0107480000000010 */
/*0390*/ LDS.64 R18, [R5+0x38] ; /* 0x0000380005127984 */
/* 0x008ee40000000a00 */
/*03a0*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x020948000000000e */
/*03b0*/ LDS.64 R16, [R5+0x40] ; /* 0x0000400005107984 */
/* 0x010f240000000a00 */
/*03c0*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x020b48000000000c */
/*03d0*/ LDS.64 R14, [R5+0x48] ; /* 0x00004800050e7984 */
/* 0x020f640000000a00 */
/*03e0*/ DADD R8, R12, R8 ; /* 0x000000000c087229 */
/* 0x0000080000000008 */
/*03f0*/ LDS.64 R12, [R5+0x50] ; /* 0x00005000050c7984 */
/* 0x001e240000000a00 */
/*0400*/ DADD R20, R8, R20 ; /* 0x0000000008147229 */
/* 0x0002480000000014 */
/*0410*/ LDS.64 R8, [R5+0x58] ; /* 0x0000580005087984 */
/* 0x002e640000000a00 */
/*0420*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0004880000000016 */
/*0430*/ LDS.64 R20, [R5+0x60] ; /* 0x0000600005147984 */
/* 0x0044640000000a00 */
/*0440*/ DADD R10, R22, R10 ; /* 0x00000000160a7229 */
/* 0x000ee2000000000a */
/*0450*/ IADD3 R5, R5, 0x80, RZ ; /* 0x0000008005057810 */
/* 0x004fca0007ffe0ff */
/*0460*/ DADD R10, R10, R18 ; /* 0x000000000a0a7229 */
/* 0x008f0c0000000012 */
/*0470*/ DADD R10, R10, R16 ; /* 0x000000000a0a7229 */
/* 0x010f4c0000000010 */
/*0480*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x020e0c000000000e */
/*0490*/ DADD R10, R10, R12 ; /* 0x000000000a0a7229 */
/* 0x001e4c000000000c */
/*04a0*/ DADD R8, R10, R8 ; /* 0x000000000a087229 */
/* 0x002e0c0000000008 */
/*04b0*/ DADD R22, R8, R20 ; /* 0x0000000008167229 */
/* 0x0010620000000014 */
/*04c0*/ @P1 BRA 0x280 ; /* 0xfffffdb000001947 */
/* 0x000fea000383ffff */
/*04d0*/ IADD3 R8, R7, -0x1, RZ ; /* 0xffffffff07087810 */
/* 0x001fc80007ffe0ff */
/*04e0*/ ISETP.GT.AND P1, PT, R8, 0x4, PT ; /* 0x000000040800780c */
/* 0x000fda0003f24270 */
/*04f0*/ @!P1 BRA 0x640 ; /* 0x0000014000009947 */
/* 0x000fea0003800000 */
/*0500*/ LDS.64 R20, [R5+-0x18] ; /* 0xffffe80005147984 */
/* 0x000e220000000a00 */
/*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0520*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0530*/ IADD3 R7, R7, -0x8, RZ ; /* 0xfffffff807077810 */
/* 0x000fe20007ffe0ff */
/*0540*/ LDS.64 R8, [R5+-0x10] ; /* 0xfffff00005087984 */
/* 0x000ea80000000a00 */
/*0550*/ LDS.64 R10, [R5+-0x8] ; /* 0xfffff800050a7984 */
/* 0x000ee80000000a00 */
/*0560*/ LDS.64 R12, [R5] ; /* 0x00000000050c7984 */
/* 0x000f280000000a00 */
/*0570*/ LDS.64 R14, [R5+0x8] ; /* 0x00000800050e7984 */
/* 0x000f680000000a00 */
/*0580*/ LDS.64 R16, [R5+0x10] ; /* 0x0000100005107984 */
/* 0x000e680000000a00 */
/*0590*/ LDS.64 R18, [R5+0x18] ; /* 0x0000180005127984 */
/* 0x000e640000000a00 */
/*05a0*/ DADD R20, R22, R20 ; /* 0x0000000016147229 */
/* 0x0030840000000014 */
/*05b0*/ LDS.64 R22, [R5+0x20] ; /* 0x0000200005167984 */
/* 0x0010680000000a00 */
/*05c0*/ DADD R8, R20, R8 ; /* 0x0000000014087229 */
/* 0x004ee20000000008 */
/*05d0*/ IADD3 R5, R5, 0x40, RZ ; /* 0x0000004005057810 */
/* 0x001fca0007ffe0ff */
/*05e0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x008f0c000000000a */
/*05f0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x010f4c000000000c */
/*0600*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x020e0c000000000e */
/*0610*/ DADD R8, R8, R16 ; /* 0x0000000008087229 */
/* 0x001e0c0000000010 */
/*0620*/ DADD R8, R8, R18 ; /* 0x0000000008087229 */
/* 0x001e4c0000000012 */
/*0630*/ DADD R22, R8, R22 ; /* 0x0000000008167229 */
/* 0x0020480000000016 */
/*0640*/ ISETP.NE.OR P0, PT, R7, 0x1, P0 ; /* 0x000000010700780c */
/* 0x000fda0000705670 */
/*0650*/ @!P0 BRA 0x730 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0660*/ LDS.64 R10, [R5+-0x18] ; /* 0xffffe800050a7984 */
/* 0x000ea20000000a00 */
/*0670*/ IADD3 R7, R7, -0x4, RZ ; /* 0xfffffffc07077810 */
/* 0x000fe20007ffe0ff */
/*0680*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe4000fffe03f */
/*0690*/ LDS.64 R12, [R5+-0x10] ; /* 0xfffff000050c7984 */
/* 0x000ee20000000a00 */
/*06a0*/ ISETP.NE.AND P0, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fc60003f05270 */
/*06b0*/ LDS.64 R14, [R5+-0x8] ; /* 0xfffff800050e7984 */
/* 0x000f280000000a00 */
/*06c0*/ LDS.64 R8, [R5] ; /* 0x0000000005087984 */
/* 0x0011640000000a00 */
/*06d0*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x001fe20007ffe0ff */
/*06e0*/ DADD R10, R10, R22 ; /* 0x000000000a0a7229 */
/* 0x006ecc0000000016 */
/*06f0*/ DADD R10, R10, R12 ; /* 0x000000000a0a7229 */
/* 0x008f0c000000000c */
/*0700*/ DADD R10, R10, R14 ; /* 0x000000000a0a7229 */
/* 0x010f4c000000000e */
/*0710*/ DADD R22, R10, R8 ; /* 0x000000000a167229 */
/* 0x0200640000000008 */
/*0720*/ @P0 BRA 0x660 ; /* 0xffffff3000000947 */
/* 0x003fea000383ffff */
/*0730*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0740*/ @!P0 BRA 0x7d0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R2, R2, UR4, RZ ; /* 0x0000000402027c10 */
/* 0x000fca000fffe0ff */
/*0760*/ IMAD.SHL.U32 R2, R2, 0x8, RZ ; /* 0x0000000802027824 */
/* 0x000fca00078e00ff */
/*0770*/ LDS.64 R8, [R2] ; /* 0x0000000002087984 */
/* 0x0010a20000000a00 */
/*0780*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fc80007ffe0ff */
/*0790*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*07a0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x001fe20007ffe0ff */
/*07b0*/ DADD R22, R8, R22 ; /* 0x0000000008167229 */
/* 0x0060540000000016 */
/*07c0*/ @P0 BRA 0x770 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*07d0*/ STS.64 [R4], R22 ; /* 0x0000001604007388 */
/* 0x0023e40000000a00 */
/*07e0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fca00078e0203 */
/*07f0*/ STG.E.64 [R2.64], R22 ; /* 0x0000001602007986 */
/* 0x002fe2000c101b06 */
/*0800*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0810*/ BRA 0x810; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5gaxpyPdS_S_ii
.globl _Z5gaxpyPdS_S_ii
.p2align 8
.type _Z5gaxpyPdS_S_ii,@function
_Z5gaxpyPdS_S_ii:
s_load_b64 s[4:5], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_cmp_lt_i32 s15, s4
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, vcc_lo
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_7
s_load_b128 s[8:11], s[0:1], 0x8
s_mul_i32 s3, s15, s5
v_lshlrev_b32_e32 v4, 3, v0
v_add_nc_u32_e32 v1, s3, v0
s_mov_b32 s2, s15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_lshl_add_u32 v1, v1, 3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
global_load_b64 v[4:5], v4, s[10:11]
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f64 v[2:3], v[2:3], v[4:5]
ds_store_b64 v1, v[2:3]
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_cmp_lt_i32 s5, 2
s_cbranch_scc1 .LBB0_6
s_lshl_b32 s4, s3, 3
s_add_i32 s5, s5, -1
s_add_i32 s4, s4, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v0, s4
s_add_i32 s6, s4, 8
ds_load_b64 v[0:1], v0
.LBB0_4:
v_mov_b32_e32 v2, s6
s_add_i32 s5, s5, -1
s_add_i32 s6, s6, 8
s_cmp_eq_u32 s5, 0
ds_load_b64 v[2:3], v2
s_waitcnt lgkmcnt(0)
v_add_f64 v[0:1], v[2:3], v[0:1]
s_cbranch_scc0 .LBB0_4
v_mov_b32_e32 v2, s4
ds_store_b64 v2, v[0:1]
.LBB0_6:
s_lshl_b32 s3, s3, 3
s_load_b64 s[0:1], s[0:1], 0x0
s_add_i32 s3, s3, 0
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v0, s3
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[2:3], 3
ds_load_b64 v[0:1], v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b64 v2, v[0:1], s[0:1]
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5gaxpyPdS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5gaxpyPdS_S_ii, .Lfunc_end0-_Z5gaxpyPdS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5gaxpyPdS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5gaxpyPdS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00103964_00000000-6_gaxpy.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii
.type _Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii, @function
_Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5gaxpyPdS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii, .-_Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii
.globl _Z5gaxpyPdS_S_ii
.type _Z5gaxpyPdS_S_ii, @function
_Z5gaxpyPdS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z5gaxpyPdS_S_iiPdS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5gaxpyPdS_S_ii, .-_Z5gaxpyPdS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5gaxpyPdS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5gaxpyPdS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gaxpy.hip"
.globl _Z20__device_stub__gaxpyPdS_S_ii # -- Begin function _Z20__device_stub__gaxpyPdS_S_ii
.p2align 4, 0x90
.type _Z20__device_stub__gaxpyPdS_S_ii,@function
_Z20__device_stub__gaxpyPdS_S_ii: # @_Z20__device_stub__gaxpyPdS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5gaxpyPdS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__gaxpyPdS_S_ii, .Lfunc_end0-_Z20__device_stub__gaxpyPdS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5gaxpyPdS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5gaxpyPdS_S_ii,@object # @_Z5gaxpyPdS_S_ii
.section .rodata,"a",@progbits
.globl _Z5gaxpyPdS_S_ii
.p2align 3, 0x0
_Z5gaxpyPdS_S_ii:
.quad _Z20__device_stub__gaxpyPdS_S_ii
.size _Z5gaxpyPdS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5gaxpyPdS_S_ii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__gaxpyPdS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5gaxpyPdS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <unistd.h>
#include <string>
#include <cuda.h>
#define ThreadNum 256
#define BlockNum 16
__global__ void printOut(char *string) {
printf("%s\n", string);
}
size_t getFileSize(char *filename) {
struct stat st;
stat(filename, &st);
return st.st_size;
}
void parsing(char *aim, long int **offset_table, int *entry) {
int limit = 1024;
int i;
long int *tmp_offset = (long int*) malloc(sizeof(long int) * limit);
char *token = strtok(aim, "\n");
for (i = 0; token != NULL; i ++) {
if (i == limit) {
limit += 1024;
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * limit);
}
tmp_offset[i] = token - aim;
token = strtok(NULL, "\n");
}
printf("Count %d\n", i);
// realloc table
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * i);
// assign & return
*offset_table = tmp_offset;
*entry = i;
}
__device__ int strlen(char *s) {
int i = 0;
while (s[i] != '\0') i ++;
return i;
}
__device__ char *strstrDevice(char *a, char *b) {
int i, j;
int a_len = strlen(a);
int b_len = strlen(b);
int loop_limit = a_len - b_len + 1;
for (i = 0; i < loop_limit; i ++) {
for (j = 0; j < b_len && a[i + j] == b[j]; j ++);
if (j == b_len) return a + i;
}
return NULL;
}
__global__ void matching(char *aim, char *string, long int *offset_table, int entry, int base, int *result) {
int t_id = threadIdx.x;
int b_id = blockIdx.x;
int b_dim = blockDim.x;
int index = base + b_id * b_dim + t_id;
//int aim_len = offset_table[index + 1] - offset_table[index];
//if (index < entry && strstrDevice(string + offset_table[index], aim_len, "apple", 5) != NULL) {
if (index < entry && strstrDevice(string + offset_table[index], aim) != NULL) {
result[index] = 1;
} else {
result[index] = 0;
}
}
int myCmp(const void *a, const void *b) {
return (*(int*) a) - (*(int*) b);
}
int main(int argc, char *argv[]) {
char *filename = argv[1];
int fd = open(filename, O_RDONLY, 0644);
// get mmap data
size_t file_len = getFileSize(filename) + 1;
char *filecontent = (char*) mmap(NULL, file_len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
filecontent[file_len - 1] = '\0';
// parsing
long int *offset_table;
int entry;
parsing(filecontent, &offset_table, &entry);
// copy data to device
char *HD_filecontent;
cudaMalloc(&HD_filecontent, file_len);
cudaMemcpy(HD_filecontent, filecontent, file_len, cudaMemcpyHostToDevice);
// copy offset table to device
long int *D_offset_table;
cudaMalloc(&D_offset_table, sizeof(long int) * entry);
cudaMemcpy(D_offset_table, offset_table, sizeof(long int) * entry, cudaMemcpyHostToDevice);
// matching
int round_limit = ceil(entry / (float) (ThreadNum * BlockNum));
int i;
int *result;
cudaMallocManaged(&result, sizeof(int) * entry);
char *aim;
cudaMallocManaged(&aim, sizeof(char) * 6);
strcpy(aim, "apple");
cudaDeviceSynchronize();
for (i = 0; i < round_limit; i ++) {
matching<<<BlockNum, ThreadNum>>>(aim, HD_filecontent, D_offset_table, entry, i * ThreadNum * BlockNum, result);
}
cudaDeviceSynchronize();
qsort(result, entry, sizeof(int), myCmp);
return 0;
} | code for sm_80
Function : _Z8matchingPcS_PliiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x480 ; /* 0x0000044000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R0, c[0x0][0x17c], RZ ; /* 0x00005f0000007a10 */
/* 0x000fc80007ffe0ff */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe200078e00ff */
/*0090*/ @P0 BRA 0x470 ; /* 0x000003d000000947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f62000c1e1b00 */
/*00d0*/ BSSY B1, 0x180 ; /* 0x000000a000017945 */
/* 0x000fe20003800000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fca00078e00ff */
/*00f0*/ SHF.R.S32.HI R5, RZ, 0x1f, R7.reuse ; /* 0x0000001fff057819 */
/* 0x100fe40000011407 */
/*0100*/ IADD3 R4, P0, P1, R2, c[0x0][0x168], R7 ; /* 0x00005a0002047a10 */
/* 0x020fc8000791e007 */
/*0110*/ IADD3.X R5, R3, c[0x0][0x16c], R5, P0, P1 ; /* 0x00005b0003057a10 */
/* 0x000fca00007e2405 */
/*0120*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*0130*/ IMAD.MOV.U32 R8, RZ, RZ, R7 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0007 */
/*0140*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*0160*/ @P0 BRA 0xf0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0170*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0180*/ BSSY B1, 0x220 ; /* 0x0000009000017945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fca00078e00ff */
/*01a0*/ IADD3 R4, P0, R6, c[0x0][0x160], RZ ; /* 0x0000580006047a10 */
/* 0x000fc80007f1e0ff */
/*01b0*/ LEA.HI.X.SX32 R5, R6, c[0x0][0x164], 0x1, P0 ; /* 0x0000590006057a11 */
/* 0x000fca00000f0eff */
/*01c0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*01d0*/ IMAD.MOV.U32 R13, RZ, RZ, R6 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0006 */
/*01e0*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x004fda0003f05270 */
/*0200*/ @P0 BRA 0x1a0 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.IADD R10, R8, 0x1, -R13 ; /* 0x00000001080a7824 */
/* 0x000fe400078e0a0d */
/*0230*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fc600078e00ff */
/*0240*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f06270 */
/*0250*/ @!P0 BRA 0x470 ; /* 0x0000021000008947 */
/* 0x000fea0003800000 */
/*0260*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe400078e00ff */
/*0270*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0280*/ BSSY B1, 0x3a0 ; /* 0x0000011000017945 */
/* 0x000fe20003800000 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fd600078e00ff */
/*02a0*/ @!P0 BRA 0x390 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc800078e00ff */
/*02c0*/ IMAD.IADD R7, R8.reuse, 0x1, R9 ; /* 0x0000000108077824 */
/* 0x040fe200078e0209 */
/*02d0*/ IADD3 R4, P2, R8, c[0x0][0x160], RZ ; /* 0x0000580008047a10 */
/* 0x000fc80007f5e0ff */
/*02e0*/ SHF.R.S32.HI R11, RZ, 0x1f, R7.reuse ; /* 0x0000001fff0b7819 */
/* 0x100fe40000011407 */
/*02f0*/ IADD3 R6, P0, P1, R2, c[0x0][0x168], R7 ; /* 0x00005a0002067a10 */
/* 0x000fe4000791e007 */
/*0300*/ LEA.HI.X.SX32 R5, R8, c[0x0][0x164], 0x1, P2 ; /* 0x0000590008057a11 */
/* 0x000fe400010f0eff */
/*0310*/ IADD3.X R7, R3, c[0x0][0x16c], R11, P0, P1 ; /* 0x00005b0003077a10 */
/* 0x000fc600007e240b */
/*0320*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1100 */
/*0330*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1100 */
/*0340*/ ISETP.NE.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x004fda0003f05270 */
/*0350*/ @P0 BRA 0x390 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0360*/ IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108087810 */
/* 0x000fc80007ffe0ff */
/*0370*/ ISETP.GE.U32.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fda0003f06070 */
/*0380*/ @!P0 BRA 0x2c0 ; /* 0xffffff3000008947 */
/* 0x000fea000383ffff */
/*0390*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.NE.AND P0, PT, R8, R13, PT ; /* 0x0000000d0800720c */
/* 0x000fda0003f05270 */
/*03b0*/ @!P0 BRA 0x410 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*03c0*/ ISETP.GE.AND P0, PT, R9.reuse, R10, PT ; /* 0x0000000a0900720c */
/* 0x040fe40003f06270 */
/*03d0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fd60007ffe0ff */
/*03e0*/ @!P0 BRA 0x270 ; /* 0xfffffe8000008947 */
/* 0x000fea000383ffff */
/*03f0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0400*/ BRA 0x470 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*0410*/ SHF.R.S32.HI R5, RZ, 0x1f, R9.reuse ; /* 0x0000001fff057819 */
/* 0x100fe40000011409 */
/*0420*/ IADD3 R9, P0, P1, R2, c[0x0][0x168], R9 ; /* 0x00005a0002097a10 */
/* 0x000fc8000791e009 */
/*0430*/ IADD3.X R5, R3, c[0x0][0x16c], R5, P0, P1 ; /* 0x00005b0003057a10 */
/* 0x000fe400007e2405 */
/*0440*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05070 */
/*0450*/ ISETP.NE.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fc80003f05300 */
/*0460*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0490*/ IMAD.WIDE R2, R0, R3, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0203 */
/*04a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*04b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04c0*/ BRA 0x4c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8printOutPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R0, 0x8 ; /* 0x0000000800007802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff097624 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0060*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x0] ; /* 0x01000000ff047624 */
/* 0x000fe200078e00ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0080*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x4] ; /* 0x01000100ff057624 */
/* 0x000fe200078e00ff */
/*0090*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100a00 */
/*00a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fca00000e06ff */
/*00b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fc60000000000 */
/*00c0*/ MOV R11, 0x130 ; /* 0x00000130000b7802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R20, 0xb0 ; /* 0x000000b000147802 */
/* 0x000fc40000000f00 */
/*00e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0100*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0110*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0120*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <unistd.h>
#include <string>
#include <cuda.h>
#define ThreadNum 256
#define BlockNum 16
__global__ void printOut(char *string) {
printf("%s\n", string);
}
size_t getFileSize(char *filename) {
struct stat st;
stat(filename, &st);
return st.st_size;
}
void parsing(char *aim, long int **offset_table, int *entry) {
int limit = 1024;
int i;
long int *tmp_offset = (long int*) malloc(sizeof(long int) * limit);
char *token = strtok(aim, "\n");
for (i = 0; token != NULL; i ++) {
if (i == limit) {
limit += 1024;
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * limit);
}
tmp_offset[i] = token - aim;
token = strtok(NULL, "\n");
}
printf("Count %d\n", i);
// realloc table
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * i);
// assign & return
*offset_table = tmp_offset;
*entry = i;
}
__device__ int strlen(char *s) {
int i = 0;
while (s[i] != '\0') i ++;
return i;
}
__device__ char *strstrDevice(char *a, char *b) {
int i, j;
int a_len = strlen(a);
int b_len = strlen(b);
int loop_limit = a_len - b_len + 1;
for (i = 0; i < loop_limit; i ++) {
for (j = 0; j < b_len && a[i + j] == b[j]; j ++);
if (j == b_len) return a + i;
}
return NULL;
}
__global__ void matching(char *aim, char *string, long int *offset_table, int entry, int base, int *result) {
int t_id = threadIdx.x;
int b_id = blockIdx.x;
int b_dim = blockDim.x;
int index = base + b_id * b_dim + t_id;
//int aim_len = offset_table[index + 1] - offset_table[index];
//if (index < entry && strstrDevice(string + offset_table[index], aim_len, "apple", 5) != NULL) {
if (index < entry && strstrDevice(string + offset_table[index], aim) != NULL) {
result[index] = 1;
} else {
result[index] = 0;
}
}
int myCmp(const void *a, const void *b) {
return (*(int*) a) - (*(int*) b);
}
int main(int argc, char *argv[]) {
char *filename = argv[1];
int fd = open(filename, O_RDONLY, 0644);
// get mmap data
size_t file_len = getFileSize(filename) + 1;
char *filecontent = (char*) mmap(NULL, file_len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
filecontent[file_len - 1] = '\0';
// parsing
long int *offset_table;
int entry;
parsing(filecontent, &offset_table, &entry);
// copy data to device
char *HD_filecontent;
cudaMalloc(&HD_filecontent, file_len);
cudaMemcpy(HD_filecontent, filecontent, file_len, cudaMemcpyHostToDevice);
// copy offset table to device
long int *D_offset_table;
cudaMalloc(&D_offset_table, sizeof(long int) * entry);
cudaMemcpy(D_offset_table, offset_table, sizeof(long int) * entry, cudaMemcpyHostToDevice);
// matching
int round_limit = ceil(entry / (float) (ThreadNum * BlockNum));
int i;
int *result;
cudaMallocManaged(&result, sizeof(int) * entry);
char *aim;
cudaMallocManaged(&aim, sizeof(char) * 6);
strcpy(aim, "apple");
cudaDeviceSynchronize();
for (i = 0; i < round_limit; i ++) {
matching<<<BlockNum, ThreadNum>>>(aim, HD_filecontent, D_offset_table, entry, i * ThreadNum * BlockNum, result);
}
cudaDeviceSynchronize();
qsort(result, entry, sizeof(int), myCmp);
return 0;
} | .file "tmpxft_000b9dde_00000000-6_mmap_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z5myCmpPKvS0_
.type _Z5myCmpPKvS0_, @function
_Z5myCmpPKvS0_:
.LFB3077:
.cfi_startproc
endbr64
movl (%rdi), %eax
subl (%rsi), %eax
ret
.cfi_endproc
.LFE3077:
.size _Z5myCmpPKvS0_, .-_Z5myCmpPKvS0_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3081:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11getFileSizePc
.type _Z11getFileSizePc, @function
_Z11getFileSizePc:
.LFB3073:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
call stat@PLT
movq 48(%rsp), %rax
movq 152(%rsp), %rdx
subq %fs:40, %rdx
jne .L7
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3073:
.size _Z11getFileSizePc, .-_Z11getFileSizePc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.LC1:
.string "Count %d\n"
.text
.globl _Z7parsingPcPPlPi
.type _Z7parsingPcPPlPi, @function
_Z7parsingPcPPlPi:
.LFB3074:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movl $8192, %edi
call malloc@PLT
movq %rax, %r12
leaq .LC0(%rip), %rsi
movq %r14, %rdi
call strtok@PLT
testq %rax, %rax
je .L12
movq %rax, %rbx
movl $0, %ebp
movl $1024, %r13d
leaq .LC0(%rip), %r15
jmp .L11
.L10:
subq %r14, %rbx
movq %rbx, (%r12,%rbp,8)
movq %r15, %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %rbx
leaq 1(%rbp), %rax
testq %rbx, %rbx
je .L15
movq %rax, %rbp
.L11:
cmpl %ebp, %r13d
jne .L10
addl $1024, %r13d
movslq %r13d, %rsi
salq $3, %rsi
movq %r12, %rdi
call realloc@PLT
movq %rax, %r12
jmp .L10
.L15:
addl $1, %ebp
.L9:
movl %ebp, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebp, %rsi
salq $3, %rsi
movq %r12, %rdi
call realloc@PLT
movq (%rsp), %rcx
movq %rax, (%rcx)
movq 8(%rsp), %rax
movl %ebp, (%rax)
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl $0, %ebp
jmp .L9
.cfi_endproc
.LFE3074:
.size _Z7parsingPcPPlPi, .-_Z7parsingPcPPlPi
.globl _Z6strlenPc
.type _Z6strlenPc, @function
_Z6strlenPc:
.LFB3075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3075:
.size _Z6strlenPc, .-_Z6strlenPc
.globl _Z12strstrDevicePcS_
.type _Z12strstrDevicePcS_, @function
_Z12strstrDevicePcS_:
.LFB3076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3076:
.size _Z12strstrDevicePcS_, .-_Z12strstrDevicePcS_
.globl _Z27__device_stub__Z8printOutPcPc
.type _Z27__device_stub__Z8printOutPcPc, @function
_Z27__device_stub__Z8printOutPcPc:
.LFB3103:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8printOutPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3103:
.size _Z27__device_stub__Z8printOutPcPc, .-_Z27__device_stub__Z8printOutPcPc
.globl _Z8printOutPc
.type _Z8printOutPc, @function
_Z8printOutPc:
.LFB3104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8printOutPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3104:
.size _Z8printOutPc, .-_Z8printOutPc
.globl _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi
.type _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi, @function
_Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi:
.LFB3105:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8matchingPcS_PliiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3105:
.size _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi, .-_Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi
.globl _Z8matchingPcS_PliiPi
.type _Z8matchingPcS_PliiPi, @function
_Z8matchingPcS_PliiPi:
.LFB3106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3106:
.size _Z8matchingPcS_PliiPi, .-_Z8matchingPcS_PliiPi
.globl main
.type main, @function
main:
.LFB3078:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rbp
movl $420, %edx
movl $0, %esi
movq %rbp, %rdi
call open@PLT
movl %eax, %ebx
movq %rbp, %rdi
call _Z11getFileSizePc
movq %rax, %rbp
leaq 1(%rax), %r12
movl $0, %r9d
movl %ebx, %r8d
movl $2, %ecx
movl $3, %edx
movq %r12, %rsi
movl $0, %edi
call mmap@PLT
movq %rax, %rbx
movb $0, (%rax,%rbp)
leaq 4(%rsp), %rdx
leaq 8(%rsp), %rsi
movq %rax, %rdi
call _Z7parsingPcPPlPi
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %r12d
movslq %r12d, %r13
leaq 0(,%r13,8), %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC6(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L37
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L37:
cvttss2sil %xmm3, %ebp
leaq 0(,%r13,4), %rsi
leaq 32(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $6, %esi
call cudaMallocManaged@PLT
movq 40(%rsp), %rax
movl $1819308129, (%rax)
movw $101, 4(%rax)
call cudaDeviceSynchronize@PLT
testl %ebp, %ebp
jle .L38
movl $0, %ebx
jmp .L40
.L39:
addl $1, %ebx
cmpl %ebx, %ebp
je .L38
.L40:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L39
movq 32(%rsp), %r9
movl %ebx, %r8d
sall $12, %r8d
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi
jmp .L39
.L38:
call cudaDeviceSynchronize@PLT
leaq _Z5myCmpPKvS0_(%rip), %rcx
movl $4, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call qsort@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3078:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z8matchingPcS_PliiPi"
.LC8:
.string "_Z8printOutPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3108:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z8matchingPcS_PliiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8printOutPc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3108:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 964689920
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <unistd.h>
#include <string>
#include <cuda.h>
#define ThreadNum 256
#define BlockNum 16
__global__ void printOut(char *string) {
printf("%s\n", string);
}
size_t getFileSize(char *filename) {
struct stat st;
stat(filename, &st);
return st.st_size;
}
void parsing(char *aim, long int **offset_table, int *entry) {
int limit = 1024;
int i;
long int *tmp_offset = (long int*) malloc(sizeof(long int) * limit);
char *token = strtok(aim, "\n");
for (i = 0; token != NULL; i ++) {
if (i == limit) {
limit += 1024;
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * limit);
}
tmp_offset[i] = token - aim;
token = strtok(NULL, "\n");
}
printf("Count %d\n", i);
// realloc table
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * i);
// assign & return
*offset_table = tmp_offset;
*entry = i;
}
__device__ int strlen(char *s) {
int i = 0;
while (s[i] != '\0') i ++;
return i;
}
__device__ char *strstrDevice(char *a, char *b) {
int i, j;
int a_len = strlen(a);
int b_len = strlen(b);
int loop_limit = a_len - b_len + 1;
for (i = 0; i < loop_limit; i ++) {
for (j = 0; j < b_len && a[i + j] == b[j]; j ++);
if (j == b_len) return a + i;
}
return NULL;
}
__global__ void matching(char *aim, char *string, long int *offset_table, int entry, int base, int *result) {
int t_id = threadIdx.x;
int b_id = blockIdx.x;
int b_dim = blockDim.x;
int index = base + b_id * b_dim + t_id;
//int aim_len = offset_table[index + 1] - offset_table[index];
//if (index < entry && strstrDevice(string + offset_table[index], aim_len, "apple", 5) != NULL) {
if (index < entry && strstrDevice(string + offset_table[index], aim) != NULL) {
result[index] = 1;
} else {
result[index] = 0;
}
}
int myCmp(const void *a, const void *b) {
return (*(int*) a) - (*(int*) b);
}
int main(int argc, char *argv[]) {
char *filename = argv[1];
int fd = open(filename, O_RDONLY, 0644);
// get mmap data
size_t file_len = getFileSize(filename) + 1;
char *filecontent = (char*) mmap(NULL, file_len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
filecontent[file_len - 1] = '\0';
// parsing
long int *offset_table;
int entry;
parsing(filecontent, &offset_table, &entry);
// copy data to device
char *HD_filecontent;
cudaMalloc(&HD_filecontent, file_len);
cudaMemcpy(HD_filecontent, filecontent, file_len, cudaMemcpyHostToDevice);
// copy offset table to device
long int *D_offset_table;
cudaMalloc(&D_offset_table, sizeof(long int) * entry);
cudaMemcpy(D_offset_table, offset_table, sizeof(long int) * entry, cudaMemcpyHostToDevice);
// matching
int round_limit = ceil(entry / (float) (ThreadNum * BlockNum));
int i;
int *result;
cudaMallocManaged(&result, sizeof(int) * entry);
char *aim;
cudaMallocManaged(&aim, sizeof(char) * 6);
strcpy(aim, "apple");
cudaDeviceSynchronize();
for (i = 0; i < round_limit; i ++) {
matching<<<BlockNum, ThreadNum>>>(aim, HD_filecontent, D_offset_table, entry, i * ThreadNum * BlockNum, result);
}
cudaDeviceSynchronize();
qsort(result, entry, sizeof(int), myCmp);
return 0;
} | #include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <unistd.h>
#include <string>
#include <hip/hip_runtime.h>
#define ThreadNum 256
#define BlockNum 16
__global__ void printOut(char *string) {
printf("%s\n", string);
}
size_t getFileSize(char *filename) {
struct stat st;
stat(filename, &st);
return st.st_size;
}
void parsing(char *aim, long int **offset_table, int *entry) {
int limit = 1024;
int i;
long int *tmp_offset = (long int*) malloc(sizeof(long int) * limit);
char *token = strtok(aim, "\n");
for (i = 0; token != NULL; i ++) {
if (i == limit) {
limit += 1024;
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * limit);
}
tmp_offset[i] = token - aim;
token = strtok(NULL, "\n");
}
printf("Count %d\n", i);
// realloc table
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * i);
// assign & return
*offset_table = tmp_offset;
*entry = i;
}
__device__ int strlen(char *s) {
int i = 0;
while (s[i] != '\0') i ++;
return i;
}
__device__ char *strstrDevice(char *a, char *b) {
int i, j;
int a_len = strlen(a);
int b_len = strlen(b);
int loop_limit = a_len - b_len + 1;
for (i = 0; i < loop_limit; i ++) {
for (j = 0; j < b_len && a[i + j] == b[j]; j ++);
if (j == b_len) return a + i;
}
return NULL;
}
__global__ void matching(char *aim, char *string, long int *offset_table, int entry, int base, int *result) {
int t_id = threadIdx.x;
int b_id = blockIdx.x;
int b_dim = blockDim.x;
int index = base + b_id * b_dim + t_id;
//int aim_len = offset_table[index + 1] - offset_table[index];
//if (index < entry && strstrDevice(string + offset_table[index], aim_len, "apple", 5) != NULL) {
if (index < entry && strstrDevice(string + offset_table[index], aim) != NULL) {
result[index] = 1;
} else {
result[index] = 0;
}
}
int myCmp(const void *a, const void *b) {
return (*(int*) a) - (*(int*) b);
}
int main(int argc, char *argv[]) {
char *filename = argv[1];
int fd = open(filename, O_RDONLY, 0644);
// get mmap data
size_t file_len = getFileSize(filename) + 1;
char *filecontent = (char*) mmap(NULL, file_len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
filecontent[file_len - 1] = '\0';
// parsing
long int *offset_table;
int entry;
parsing(filecontent, &offset_table, &entry);
// copy data to device
char *HD_filecontent;
hipMalloc(&HD_filecontent, file_len);
hipMemcpy(HD_filecontent, filecontent, file_len, hipMemcpyHostToDevice);
// copy offset table to device
long int *D_offset_table;
hipMalloc(&D_offset_table, sizeof(long int) * entry);
hipMemcpy(D_offset_table, offset_table, sizeof(long int) * entry, hipMemcpyHostToDevice);
// matching
int round_limit = ceil(entry / (float) (ThreadNum * BlockNum));
int i;
int *result;
hipMallocManaged(&result, sizeof(int) * entry);
char *aim;
hipMallocManaged(&aim, sizeof(char) * 6);
strcpy(aim, "apple");
hipDeviceSynchronize();
for (i = 0; i < round_limit; i ++) {
matching<<<BlockNum, ThreadNum>>>(aim, HD_filecontent, D_offset_table, entry, i * ThreadNum * BlockNum, result);
}
hipDeviceSynchronize();
qsort(result, entry, sizeof(int), myCmp);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <sys/mman.h>
#include <unistd.h>
#include <string>
#include <hip/hip_runtime.h>
#define ThreadNum 256
#define BlockNum 16
__global__ void printOut(char *string) {
printf("%s\n", string);
}
size_t getFileSize(char *filename) {
struct stat st;
stat(filename, &st);
return st.st_size;
}
void parsing(char *aim, long int **offset_table, int *entry) {
int limit = 1024;
int i;
long int *tmp_offset = (long int*) malloc(sizeof(long int) * limit);
char *token = strtok(aim, "\n");
for (i = 0; token != NULL; i ++) {
if (i == limit) {
limit += 1024;
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * limit);
}
tmp_offset[i] = token - aim;
token = strtok(NULL, "\n");
}
printf("Count %d\n", i);
// realloc table
tmp_offset = (long int*) realloc(tmp_offset, sizeof(long int) * i);
// assign & return
*offset_table = tmp_offset;
*entry = i;
}
__device__ int strlen(char *s) {
int i = 0;
while (s[i] != '\0') i ++;
return i;
}
__device__ char *strstrDevice(char *a, char *b) {
int i, j;
int a_len = strlen(a);
int b_len = strlen(b);
int loop_limit = a_len - b_len + 1;
for (i = 0; i < loop_limit; i ++) {
for (j = 0; j < b_len && a[i + j] == b[j]; j ++);
if (j == b_len) return a + i;
}
return NULL;
}
__global__ void matching(char *aim, char *string, long int *offset_table, int entry, int base, int *result) {
int t_id = threadIdx.x;
int b_id = blockIdx.x;
int b_dim = blockDim.x;
int index = base + b_id * b_dim + t_id;
//int aim_len = offset_table[index + 1] - offset_table[index];
//if (index < entry && strstrDevice(string + offset_table[index], aim_len, "apple", 5) != NULL) {
if (index < entry && strstrDevice(string + offset_table[index], aim) != NULL) {
result[index] = 1;
} else {
result[index] = 0;
}
}
int myCmp(const void *a, const void *b) {
return (*(int*) a) - (*(int*) b);
}
int main(int argc, char *argv[]) {
char *filename = argv[1];
int fd = open(filename, O_RDONLY, 0644);
// get mmap data
size_t file_len = getFileSize(filename) + 1;
char *filecontent = (char*) mmap(NULL, file_len, PROT_READ | PROT_WRITE, MAP_PRIVATE, fd, 0);
filecontent[file_len - 1] = '\0';
// parsing
long int *offset_table;
int entry;
parsing(filecontent, &offset_table, &entry);
// copy data to device
char *HD_filecontent;
hipMalloc(&HD_filecontent, file_len);
hipMemcpy(HD_filecontent, filecontent, file_len, hipMemcpyHostToDevice);
// copy offset table to device
long int *D_offset_table;
hipMalloc(&D_offset_table, sizeof(long int) * entry);
hipMemcpy(D_offset_table, offset_table, sizeof(long int) * entry, hipMemcpyHostToDevice);
// matching
int round_limit = ceil(entry / (float) (ThreadNum * BlockNum));
int i;
int *result;
hipMallocManaged(&result, sizeof(int) * entry);
char *aim;
hipMallocManaged(&aim, sizeof(char) * 6);
strcpy(aim, "apple");
hipDeviceSynchronize();
for (i = 0; i < round_limit; i ++) {
matching<<<BlockNum, ThreadNum>>>(aim, HD_filecontent, D_offset_table, entry, i * ThreadNum * BlockNum, result);
}
hipDeviceSynchronize();
qsort(result, entry, sizeof(int), myCmp);
return 0;
} | .text
.file "mmap_gpu.hip"
.globl _Z23__device_stub__printOutPc # -- Begin function _Z23__device_stub__printOutPc
.p2align 4, 0x90
.type _Z23__device_stub__printOutPc,@function
_Z23__device_stub__printOutPc: # @_Z23__device_stub__printOutPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8printOutPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__printOutPc, .Lfunc_end0-_Z23__device_stub__printOutPc
.cfi_endproc
# -- End function
.globl _Z11getFileSizePc # -- Begin function _Z11getFileSizePc
.p2align 4, 0x90
.type _Z11getFileSizePc,@function
_Z11getFileSizePc: # @_Z11getFileSizePc
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
leaq 8(%rsp), %rsi
callq stat
movq 56(%rsp), %rax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11getFileSizePc, .Lfunc_end1-_Z11getFileSizePc
.cfi_endproc
# -- End function
.globl _Z7parsingPcPPlPi # -- Begin function _Z7parsingPcPPlPi
.p2align 4, 0x90
.type _Z7parsingPcPPlPi,@function
_Z7parsingPcPPlPi: # @_Z7parsingPcPPlPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r13
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
movl $.L.str, %esi
movq %r13, %rdi
callq strtok
testq %rax, %rax
je .LBB2_1
# %bb.2: # %.lr.ph
movq %rax, %rbp
movq %rbx, (%rsp) # 8-byte Spill
movl $1024, %ebx # imm = 0x400
xorl %r12d, %r12d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
subq %r13, %rbp
movq %rbp, (%r15,%r12,8)
movl $.L.str, %esi
xorl %edi, %edi
callq strtok
movq %rax, %rbp
incq %r12
testq %rax, %rax
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl %ebx, %eax
cmpq %rax, %r12
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movslq %ebx, %rax
addl $1024, %ebx # imm = 0x400
leaq 8192(,%rax,8), %rsi
movq %r15, %rdi
callq realloc
movq %rax, %r15
jmp .LBB2_5
.LBB2_6: # %._crit_edge.loopexit
movq (%rsp), %rbx # 8-byte Reload
jmp .LBB2_7
.LBB2_1:
xorl %r12d, %r12d
.LBB2_7: # %._crit_edge
movl $.L.str.1, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl %r12d, %esi
shlq $3, %rsi
movq %r15, %rdi
callq realloc
movq %rax, (%r14)
movl %r12d, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7parsingPcPPlPi, .Lfunc_end2-_Z7parsingPcPPlPi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__matchingPcS_PliiPi # -- Begin function _Z23__device_stub__matchingPcS_PliiPi
.p2align 4, 0x90
.type _Z23__device_stub__matchingPcS_PliiPi,@function
_Z23__device_stub__matchingPcS_PliiPi: # @_Z23__device_stub__matchingPcS_PliiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8matchingPcS_PliiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z23__device_stub__matchingPcS_PliiPi, .Lfunc_end3-_Z23__device_stub__matchingPcS_PliiPi
.cfi_endproc
# -- End function
.globl _Z5myCmpPKvS0_ # -- Begin function _Z5myCmpPKvS0_
.p2align 4, 0x90
.type _Z5myCmpPKvS0_,@function
_Z5myCmpPKvS0_: # @_Z5myCmpPKvS0_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
subl (%rsi), %eax
retq
.Lfunc_end4:
.size _Z5myCmpPKvS0_, .Lfunc_end4-_Z5myCmpPKvS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x39800000 # float 2.44140625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rbx
xorl %r13d, %r13d
movq %rbx, %rdi
xorl %esi, %esi
movl $420, %edx # imm = 0x1A4
xorl %eax, %eax
callq open
movl %eax, %ebp
leaq 144(%rsp), %rsi
movq %rbx, %rdi
callq stat
movq 192(%rsp), %r15
leaq 1(%r15), %rbx
xorl %edi, %edi
movq %rbx, %rsi
movl $3, %edx
movl $2, %ecx
movl %ebp, %r8d
xorl %r9d, %r9d
callq mmap
movq %rax, %r14
movb $0, (%rax,%r15)
leaq 56(%rsp), %rsi
leaq 4(%rsp), %rdx
movq %rax, %rdi
callq _Z7parsingPcPPlPi
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %ebp
movslq %ebp, %r14
leaq (,%r14,8), %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 56(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r14d, %xmm0
mulss .LCPI5_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movq %r14, 48(%rsp) # 8-byte Spill
leaq (,%r14,4), %rsi
leaq 24(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $6, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movl $1819308129, (%rax) # imm = 0x6C707061
movw $101, 4(%rax)
callq hipDeviceSynchronize
testl %ebx, %ebx
jle .LBB5_5
# %bb.1: # %.lr.ph
movabsq $4294967312, %r14 # imm = 0x100000010
leaq 240(%r14), %r15
leaq 144(%rsp), %r12
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
addl $4096, %r13d # imm = 0x1000
decl %ebx
je .LBB5_5
.LBB5_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movq 16(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %ebp, 12(%rsp)
movl %r13d, 8(%rsp)
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z8matchingPcS_PliiPi, %edi
movq %r12, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_4
.LBB5_5: # %._crit_edge
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
movl $4, %edx
movl $_Z5myCmpPKvS0_, %ecx
movq 48(%rsp), %rsi # 8-byte Reload
callq qsort
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8printOutPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8matchingPcS_PliiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8printOutPc,@object # @_Z8printOutPc
.section .rodata,"a",@progbits
.globl _Z8printOutPc
.p2align 3, 0x0
_Z8printOutPc:
.quad _Z23__device_stub__printOutPc
.size _Z8printOutPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Count %d\n"
.size .L.str.1, 10
.type _Z8matchingPcS_PliiPi,@object # @_Z8matchingPcS_PliiPi
.section .rodata,"a",@progbits
.globl _Z8matchingPcS_PliiPi
.p2align 3, 0x0
_Z8matchingPcS_PliiPi:
.quad _Z23__device_stub__matchingPcS_PliiPi
.size _Z8matchingPcS_PliiPi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "apple"
.size .L.str.2, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8printOutPc"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8matchingPcS_PliiPi"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__printOutPc
.addrsig_sym _Z23__device_stub__matchingPcS_PliiPi
.addrsig_sym _Z5myCmpPKvS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8printOutPc
.addrsig_sym _Z8matchingPcS_PliiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b9dde_00000000-6_mmap_gpu.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z5myCmpPKvS0_
.type _Z5myCmpPKvS0_, @function
_Z5myCmpPKvS0_:
.LFB3077:
.cfi_startproc
endbr64
movl (%rdi), %eax
subl (%rsi), %eax
ret
.cfi_endproc
.LFE3077:
.size _Z5myCmpPKvS0_, .-_Z5myCmpPKvS0_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3081:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11getFileSizePc
.type _Z11getFileSizePc, @function
_Z11getFileSizePc:
.LFB3073:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
call stat@PLT
movq 48(%rsp), %rax
movq 152(%rsp), %rdx
subq %fs:40, %rdx
jne .L7
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3073:
.size _Z11getFileSizePc, .-_Z11getFileSizePc
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.LC1:
.string "Count %d\n"
.text
.globl _Z7parsingPcPPlPi
.type _Z7parsingPcPPlPi, @function
_Z7parsingPcPPlPi:
.LFB3074:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r14
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movl $8192, %edi
call malloc@PLT
movq %rax, %r12
leaq .LC0(%rip), %rsi
movq %r14, %rdi
call strtok@PLT
testq %rax, %rax
je .L12
movq %rax, %rbx
movl $0, %ebp
movl $1024, %r13d
leaq .LC0(%rip), %r15
jmp .L11
.L10:
subq %r14, %rbx
movq %rbx, (%r12,%rbp,8)
movq %r15, %rsi
movl $0, %edi
call strtok@PLT
movq %rax, %rbx
leaq 1(%rbp), %rax
testq %rbx, %rbx
je .L15
movq %rax, %rbp
.L11:
cmpl %ebp, %r13d
jne .L10
addl $1024, %r13d
movslq %r13d, %rsi
salq $3, %rsi
movq %r12, %rdi
call realloc@PLT
movq %rax, %r12
jmp .L10
.L15:
addl $1, %ebp
.L9:
movl %ebp, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebp, %rsi
salq $3, %rsi
movq %r12, %rdi
call realloc@PLT
movq (%rsp), %rcx
movq %rax, (%rcx)
movq 8(%rsp), %rax
movl %ebp, (%rax)
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movl $0, %ebp
jmp .L9
.cfi_endproc
.LFE3074:
.size _Z7parsingPcPPlPi, .-_Z7parsingPcPPlPi
.globl _Z6strlenPc
.type _Z6strlenPc, @function
_Z6strlenPc:
.LFB3075:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3075:
.size _Z6strlenPc, .-_Z6strlenPc
.globl _Z12strstrDevicePcS_
.type _Z12strstrDevicePcS_, @function
_Z12strstrDevicePcS_:
.LFB3076:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3076:
.size _Z12strstrDevicePcS_, .-_Z12strstrDevicePcS_
.globl _Z27__device_stub__Z8printOutPcPc
.type _Z27__device_stub__Z8printOutPcPc, @function
_Z27__device_stub__Z8printOutPcPc:
.LFB3103:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8printOutPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3103:
.size _Z27__device_stub__Z8printOutPcPc, .-_Z27__device_stub__Z8printOutPcPc
.globl _Z8printOutPc
.type _Z8printOutPc, @function
_Z8printOutPc:
.LFB3104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8printOutPcPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3104:
.size _Z8printOutPc, .-_Z8printOutPc
.globl _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi
.type _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi, @function
_Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi:
.LFB3105:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z8matchingPcS_PliiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3105:
.size _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi, .-_Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi
.globl _Z8matchingPcS_PliiPi
.type _Z8matchingPcS_PliiPi, @function
_Z8matchingPcS_PliiPi:
.LFB3106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3106:
.size _Z8matchingPcS_PliiPi, .-_Z8matchingPcS_PliiPi
.globl main
.type main, @function
main:
.LFB3078:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq 8(%rsi), %rbp
movl $420, %edx
movl $0, %esi
movq %rbp, %rdi
call open@PLT
movl %eax, %ebx
movq %rbp, %rdi
call _Z11getFileSizePc
movq %rax, %rbp
leaq 1(%rax), %r12
movl $0, %r9d
movl %ebx, %r8d
movl $2, %ecx
movl $3, %edx
movq %r12, %rsi
movl $0, %edi
call mmap@PLT
movq %rax, %rbx
movb $0, (%rax,%rbp)
leaq 4(%rsp), %rdx
leaq 8(%rsp), %rsi
movq %rax, %rdi
call _Z7parsingPcPPlPi
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %r12d
movslq %r12d, %r13
leaq 0(,%r13,8), %rbx
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %r12d, %xmm0
mulss .LC2(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC6(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L37
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L37:
cvttss2sil %xmm3, %ebp
leaq 0(,%r13,4), %rsi
leaq 32(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
leaq 40(%rsp), %rdi
movl $1, %edx
movl $6, %esi
call cudaMallocManaged@PLT
movq 40(%rsp), %rax
movl $1819308129, (%rax)
movw $101, 4(%rax)
call cudaDeviceSynchronize@PLT
testl %ebp, %ebp
jle .L38
movl $0, %ebx
jmp .L40
.L39:
addl $1, %ebx
cmpl %ebx, %ebp
je .L38
.L40:
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $16, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L39
movq 32(%rsp), %r9
movl %ebx, %r8d
sall $12, %r8d
movl %r12d, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z35__device_stub__Z8matchingPcS_PliiPiPcS_PliiPi
jmp .L39
.L38:
call cudaDeviceSynchronize@PLT
leaq _Z5myCmpPKvS0_(%rip), %rcx
movl $4, %edx
movq %r13, %rsi
movq 32(%rsp), %rdi
call qsort@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L44
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3078:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z8matchingPcS_PliiPi"
.LC8:
.string "_Z8printOutPc"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3108:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z8matchingPcS_PliiPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z8printOutPc(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3108:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 964689920
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1065353216
.align 4
.LC6:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mmap_gpu.hip"
.globl _Z23__device_stub__printOutPc # -- Begin function _Z23__device_stub__printOutPc
.p2align 4, 0x90
.type _Z23__device_stub__printOutPc,@function
_Z23__device_stub__printOutPc: # @_Z23__device_stub__printOutPc
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8printOutPc, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__printOutPc, .Lfunc_end0-_Z23__device_stub__printOutPc
.cfi_endproc
# -- End function
.globl _Z11getFileSizePc # -- Begin function _Z11getFileSizePc
.p2align 4, 0x90
.type _Z11getFileSizePc,@function
_Z11getFileSizePc: # @_Z11getFileSizePc
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
leaq 8(%rsp), %rsi
callq stat
movq 56(%rsp), %rax
addq $152, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11getFileSizePc, .Lfunc_end1-_Z11getFileSizePc
.cfi_endproc
# -- End function
.globl _Z7parsingPcPPlPi # -- Begin function _Z7parsingPcPPlPi
.p2align 4, 0x90
.type _Z7parsingPcPPlPi,@function
_Z7parsingPcPPlPi: # @_Z7parsingPcPPlPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movq %rdi, %r13
movl $8192, %edi # imm = 0x2000
callq malloc
movq %rax, %r15
movl $.L.str, %esi
movq %r13, %rdi
callq strtok
testq %rax, %rax
je .LBB2_1
# %bb.2: # %.lr.ph
movq %rax, %rbp
movq %rbx, (%rsp) # 8-byte Spill
movl $1024, %ebx # imm = 0x400
xorl %r12d, %r12d
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_5: # in Loop: Header=BB2_3 Depth=1
subq %r13, %rbp
movq %rbp, (%r15,%r12,8)
movl $.L.str, %esi
xorl %edi, %edi
callq strtok
movq %rax, %rbp
incq %r12
testq %rax, %rax
je .LBB2_6
.LBB2_3: # =>This Inner Loop Header: Depth=1
movl %ebx, %eax
cmpq %rax, %r12
jne .LBB2_5
# %bb.4: # in Loop: Header=BB2_3 Depth=1
movslq %ebx, %rax
addl $1024, %ebx # imm = 0x400
leaq 8192(,%rax,8), %rsi
movq %r15, %rdi
callq realloc
movq %rax, %r15
jmp .LBB2_5
.LBB2_6: # %._crit_edge.loopexit
movq (%rsp), %rbx # 8-byte Reload
jmp .LBB2_7
.LBB2_1:
xorl %r12d, %r12d
.LBB2_7: # %._crit_edge
movl $.L.str.1, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl %r12d, %esi
shlq $3, %rsi
movq %r15, %rdi
callq realloc
movq %rax, (%r14)
movl %r12d, (%rbx)
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7parsingPcPPlPi, .Lfunc_end2-_Z7parsingPcPPlPi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__matchingPcS_PliiPi # -- Begin function _Z23__device_stub__matchingPcS_PliiPi
.p2align 4, 0x90
.type _Z23__device_stub__matchingPcS_PliiPi,@function
_Z23__device_stub__matchingPcS_PliiPi: # @_Z23__device_stub__matchingPcS_PliiPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 12(%rsp)
movl %r8d, 8(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8matchingPcS_PliiPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end3:
.size _Z23__device_stub__matchingPcS_PliiPi, .Lfunc_end3-_Z23__device_stub__matchingPcS_PliiPi
.cfi_endproc
# -- End function
.globl _Z5myCmpPKvS0_ # -- Begin function _Z5myCmpPKvS0_
.p2align 4, 0x90
.type _Z5myCmpPKvS0_,@function
_Z5myCmpPKvS0_: # @_Z5myCmpPKvS0_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
subl (%rsi), %eax
retq
.Lfunc_end4:
.size _Z5myCmpPKvS0_, .Lfunc_end4-_Z5myCmpPKvS0_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x39800000 # float 2.44140625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 352
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq 8(%rsi), %rbx
xorl %r13d, %r13d
movq %rbx, %rdi
xorl %esi, %esi
movl $420, %edx # imm = 0x1A4
xorl %eax, %eax
callq open
movl %eax, %ebp
leaq 144(%rsp), %rsi
movq %rbx, %rdi
callq stat
movq 192(%rsp), %r15
leaq 1(%r15), %rbx
xorl %edi, %edi
movq %rbx, %rsi
movl $3, %edx
movl $2, %ecx
movl %ebp, %r8d
xorl %r9d, %r9d
callq mmap
movq %rax, %r14
movb $0, (%rax,%r15)
leaq 56(%rsp), %rsi
leaq 4(%rsp), %rdx
movq %rax, %rdi
callq _Z7parsingPcPPlPi
leaq 40(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %ebp
movslq %ebp, %r14
leaq (,%r14,8), %rbx
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 56(%rsp), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
cvtsi2ss %r14d, %xmm0
mulss .LCPI5_0(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movq %r14, 48(%rsp) # 8-byte Spill
leaq (,%r14,4), %rsi
leaq 24(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $6, %esi
movl $1, %edx
callq hipMallocManaged
movq 16(%rsp), %rax
movl $1819308129, (%rax) # imm = 0x6C707061
movw $101, 4(%rax)
callq hipDeviceSynchronize
testl %ebx, %ebx
jle .LBB5_5
# %bb.1: # %.lr.ph
movabsq $4294967312, %r14 # imm = 0x100000010
leaq 240(%r14), %r15
leaq 144(%rsp), %r12
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_4: # in Loop: Header=BB5_2 Depth=1
addl $4096, %r13d # imm = 0x1000
decl %ebx
je .LBB5_5
.LBB5_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_4
# %bb.3: # in Loop: Header=BB5_2 Depth=1
movq 16(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %ebp, 12(%rsp)
movl %r13d, 8(%rsp)
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z8matchingPcS_PliiPi, %edi
movq %r12, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB5_4
.LBB5_5: # %._crit_edge
callq hipDeviceSynchronize
movq 24(%rsp), %rdi
movl $4, %edx
movl $_Z5myCmpPKvS0_, %ecx
movq 48(%rsp), %rsi # 8-byte Reload
callq qsort
xorl %eax, %eax
addq $296, %rsp # imm = 0x128
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8printOutPc, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8matchingPcS_PliiPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8printOutPc,@object # @_Z8printOutPc
.section .rodata,"a",@progbits
.globl _Z8printOutPc
.p2align 3, 0x0
_Z8printOutPc:
.quad _Z23__device_stub__printOutPc
.size _Z8printOutPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\n"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Count %d\n"
.size .L.str.1, 10
.type _Z8matchingPcS_PliiPi,@object # @_Z8matchingPcS_PliiPi
.section .rodata,"a",@progbits
.globl _Z8matchingPcS_PliiPi
.p2align 3, 0x0
_Z8matchingPcS_PliiPi:
.quad _Z23__device_stub__matchingPcS_PliiPi
.size _Z8matchingPcS_PliiPi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "apple"
.size .L.str.2, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8printOutPc"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8matchingPcS_PliiPi"
.size .L__unnamed_2, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__printOutPc
.addrsig_sym _Z23__device_stub__matchingPcS_PliiPi
.addrsig_sym _Z5myCmpPKvS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8printOutPc
.addrsig_sym _Z8matchingPcS_PliiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
// Setup for measuing time
#include <sys/time.h>
#include <time.h>
int timeval_subtract(struct timeval* result,
struct timeval* t2,
struct timeval* t1) {
unsigned int resolution=1000000;
long int diff = (t2->tv_usec + resolution * t2->tv_sec) -
(t1->tv_usec + resolution * t1->tv_sec);
result->tv_sec = diff / resolution;
result->tv_usec = diff % resolution;
return (diff<0);
}
void seqFunct(float* m_out) {
for (int i = 1; i <= 753411; i++) {
m_out[i-1] = pow(i/(i-2.3), 3);
}
}
__global__ void parFunct(float *d_in, float *d_out, int limit) {
const unsigned int lid = threadIdx.x; //local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
float x;
if (gid <= limit) {
x = d_in[gid];
d_out[gid] = pow((x/(x-2.3)),3); // Compute
}
}
int main(int argc, char** argv) {
unsigned int num_threads = 753411;
unsigned int mem_size = num_threads*sizeof(float);
// Initialize vars for measuring time
unsigned long int par_elapsed;
unsigned long int seq_elapsed;
struct timeval p_start, p_end, p_diff;
struct timeval s_start, s_end, s_diff;
// alocate host memory
float* h_in = (float*) malloc(mem_size);
float* h_out = (float*) malloc(mem_size);
float* m_out = (float*) malloc(mem_size);
// iniitalize the memory
for(unsigned int i=1; i<=num_threads; ++i) {
h_in[i-1] = (float)(i);
}
// allocate device memory
float* d_in;
float* d_out;
cudaMalloc((void**)&d_in, mem_size);
cudaMalloc((void**)&d_out, mem_size);
// copy host memory to device
cudaMemcpy(d_in, h_in, mem_size, cudaMemcpyHostToDevice);
// Start timer
gettimeofday(&p_start, NULL);
// execute the kernel
parFunct<<< ceil(num_threads/1024.0), 1024>>>(d_in, d_out, num_threads);
cudaThreadSynchronize();
// calc elapsed time
gettimeofday(&p_end, NULL);
timeval_subtract(&p_diff, &p_end, &p_start);
par_elapsed = p_diff.tv_sec*1e6+p_diff.tv_usec;
cudaMemcpy(h_out, d_out, mem_size, cudaMemcpyDeviceToHost);
gettimeofday(&s_start, NULL);
// execute the kernel
seqFunct(m_out);
// Print elapsed time
gettimeofday(&s_end, NULL);
timeval_subtract(&s_diff, &s_end, &s_start);
seq_elapsed = s_diff.tv_sec*1e6+s_diff.tv_usec;
//printf("Took %d microseconds (%.2fms)\n", elapsed, elapsed/1000.0);
bool isValid = true;
for (int i = 0; i < num_threads; i++) {
if (abs(m_out[i] - h_out[i]) > 0.000001) {
isValid = false;
break;
}
}
if (isValid) {
printf("VALID\n");
}
else {
printf("INVALID\n");
}
printf("CPU Time: %d microseconds (%.fms)\n", seq_elapsed, seq_elapsed/1000.0);
printf("GPU Time: %d microseconds (%.fms)\n", par_elapsed, par_elapsed/1000.0);
// clean-up memory
free(h_in); free(h_out);
free(m_out);
cudaFree(d_in); cudaFree(d_out);
} | code for sm_80
Function : _Z8parFunctPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0090*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x1e0 ; /* 0x0000012000007945 */
/* 0x000fe20003800000 */
/*00c0*/ F2F.F64.F32 R4, R4 ; /* 0x0000000400047310 */
/* 0x004e240000201800 */
/*00d0*/ DADD R6, R4, c[0x2][0x0] ; /* 0x0080000004067629 */
/* 0x001e220000000000 */
/*00e0*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fca0003f2e200 */
/*00f0*/ MUFU.RCP64H R9, R7 ; /* 0x0000000700097308 */
/* 0x001e240000001800 */
/*0100*/ DFMA R10, -R6, R8, 1 ; /* 0x3ff00000060a742b */
/* 0x001e0c0000000108 */
/*0110*/ DFMA R10, R10, R10, R10 ; /* 0x0000000a0a0a722b */
/* 0x001e0c000000000a */
/*0120*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x001e0c0000000008 */
/*0130*/ DFMA R8, -R6, R10, 1 ; /* 0x3ff000000608742b */
/* 0x001e0c000000010a */
/*0140*/ DFMA R8, R10, R8, R10 ; /* 0x000000080a08722b */
/* 0x001e0c000000000a */
/*0150*/ DMUL R10, R4, R8 ; /* 0x00000008040a7228 */
/* 0x001e0c0000000000 */
/*0160*/ DFMA R2, -R6, R10, R4 ; /* 0x0000000a0602722b */
/* 0x001e0c0000000104 */
/*0170*/ DFMA R2, R8, R2, R10 ; /* 0x000000020802722b */
/* 0x001e14000000000a */
/*0180*/ FFMA R8, RZ, R7, R3 ; /* 0x00000007ff087223 */
/* 0x001fca0000000003 */
/*0190*/ FSETP.GT.AND P0, PT, |R8|, 1.469367938527859385e-39, PT ; /* 0x001000000800780b */
/* 0x000fda0003f04200 */
/*01a0*/ @P0 BRA P1, 0x1d0 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*01b0*/ MOV R10, 0x1d0 ; /* 0x000001d0000a7802 */
/* 0x000fe40000000f00 */
/*01c0*/ CALL.REL.NOINC 0x430 ; /* 0x0000026000007944 */
/* 0x000fea0003c00000 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ BSSY B0, 0x220 ; /* 0x0000003000007945 */
/* 0x000fe20003800000 */
/*01f0*/ MOV R12, 0x210 ; /* 0x00000210000c7802 */
/* 0x000fe40000000f00 */
/*0200*/ CALL.REL.NOINC 0xa00 ; /* 0x000007f000007944 */
/* 0x003fea0003c00000 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ DADD R4, R2.reuse, 3 ; /* 0x4008000002047429 */
/* 0x041e220000000000 */
/*0230*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f26270 */
/*0240*/ BSSY B0, 0x3b0 ; /* 0x0000016000007945 */
/* 0x000fe40003800000 */
/*0250*/ DSETP.NEU.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200722a */
/* 0x000e8c0003f0d000 */
/*0260*/ LOP3.LUT R4, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005047812 */
/* 0x001fe200078ec0ff */
/*0270*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x002fc600078e000f */
/*0280*/ ISETP.NE.AND P2, PT, R4, 0x7ff00000, PT ; /* 0x7ff000000400780c */
/* 0x000fe20003f45270 */
/*0290*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000e */
/*02a0*/ @!P1 LOP3.LUT R7, R5, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000005079812 */
/* 0x000fe400078e3cff */
/*02b0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff048224 */
/* 0x004fc600078e00ff */
/*02c0*/ @!P1 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff059224 */
/* 0x000fe400078e0007 */
/*02d0*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff058224 */
/* 0x000fc800078e0003 */
/*02e0*/ @P2 BRA 0x3a0 ; /* 0x000000b000002947 */
/* 0x000fea0003800000 */
/*02f0*/ DSETP.GTU.AND P0, PT, |R2|, +INF , PT ; /* 0x7ff000000200742a */
/* 0x000e1c0003f0c200 */
/*0300*/ @P0 BRA 0x390 ; /* 0x0000008000000947 */
/* 0x001fea0003800000 */
/*0310*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0320*/ LOP3.LUT R6, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03067812 */
/* 0x000fc800078ec0ff */
/*0330*/ ISETP.NE.OR P0, PT, R6, 0x7ff00000, P0 ; /* 0x7ff000000600780c */
/* 0x000fda0000705670 */
/*0340*/ @P0 BRA 0x3a0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0350*/ IMAD.MOV.U32 R5, RZ, RZ, -0x100000 ; /* 0xfff00000ff057424 */
/* 0x000fe400078e00ff */
/*0360*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0370*/ SEL R5, R5, 0x7ff00000, !P1 ; /* 0x7ff0000005057807 */
/* 0x000fe20004800000 */
/*0380*/ BRA 0x3a0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0390*/ DADD R4, R2, 3 ; /* 0x4008000002047429 */
/* 0x00004c0000000000 */
/*03a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03b0*/ DSETP.NEU.AND P0, PT, R2, 1, PT ; /* 0x3ff000000200742a */
/* 0x000e8c0003f0d000 */
/*03c0*/ FSEL R3, R5, 1.875, P0 ; /* 0x3ff0000005037808 */
/* 0x007fe40000000000 */
/*03d0*/ FSEL R2, R4, RZ, P0 ; /* 0x000000ff04027208 */
/* 0x000fe40000000000 */
/*03e0*/ LEA R4, P0, R0.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x040fe400078010ff */
/*03f0*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x000e240000301000 */
/*0400*/ LEA.HI.X R5, R0, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f14ff */
/*0410*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0440*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*0450*/ LOP3.LUT R2, R7, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x000fe200078ec0ff */
/*0460*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0470*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*0480*/ BSSY B1, 0x9c0 ; /* 0x0000053000017945 */
/* 0x000fe20003800000 */
/*0490*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*04a0*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*04b0*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe400078ec0ff */
/*04c0*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc600078ec0ff */
/*04d0*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*04e0*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*04f0*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fe400078e000b */
/*0500*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0510*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0520*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0530*/ SEL R9, R12, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x000fe40004800000 */
/*0540*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0560*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fc400078ef805 */
/*0570*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fe40005800000 */
/*0580*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*0590*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe400078ef805 */
/*05a0*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fe200078efcff */
/*05c0*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e0a0000000802 */
/*05d0*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000fc80000000814 */
/*05e0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e0c0000000012 */
/*05f0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0600*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x000fc800078ec0ff */
/*0610*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fe20007ffe0ff */
/*0620*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0630*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc60003f04070 */
/*0640*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0650*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fca0000704470 */
/*0660*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0670*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*0680*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0690*/ @P0 BRA 0x860 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*06a0*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*06b0*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*06c0*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*06d0*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*06e0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*06f0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*0700*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*0710*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0720*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0730*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*0740*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0750*/ @P0 BRA 0x9b0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0760*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*0770*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0780*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*0790*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*07a0*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*07b0*/ @!P0 BRA 0x9b0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*07c0*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*07d0*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*07e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fe200078e00ff */
/*07f0*/ IADD3 R11, -R11, -0x43300000, RZ ; /* 0xbcd000000b0b7810 */
/* 0x000fca0007ffe1ff */
/*0800*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0810*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fce00078e3cff */
/*0820*/ FSETP.NEU.AND P0, PT, |R3|, R11, PT ; /* 0x0000000b0300720b */
/* 0x004fc80003f0d200 */
/*0830*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*0840*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0850*/ BRA 0x9b0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0860*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0870*/ @P0 BRA 0x990 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0880*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0890*/ @P0 BRA 0x960 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*08a0*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*08b0*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*08c0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*08d0*/ @!P0 BRA 0x9b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08e0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*08f0*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0900*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0910*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0920*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0930*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0940*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0950*/ BRA 0x9b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0960*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0970*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0980*/ BRA 0x9b0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0990*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*09a0*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fe400078e00ff */
/*09d0*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fc400078e000c */
/*09e0*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*09f0*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff6000a007950 */
/* 0x000fec0003c3ffff */
/*0a00*/ DADD R4, -RZ, |R2| ; /* 0x00000000ff047229 */
/* 0x000e220000000502 */
/*0a10*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe400078e00ff */
/*0a20*/ IMAD.MOV.U32 R10, RZ, RZ, 0x7d2cafe2 ; /* 0x7d2cafe2ff0a7424 */
/* 0x000fe400078e00ff */
/*0a30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3eb0f5ff ; /* 0x3eb0f5ffff0b7424 */
/* 0x000fca00078e00ff */
/*0a40*/ SHF.R.U32.HI R13, RZ, 0x14, R5 ; /* 0x00000014ff0d7819 */
/* 0x001fc80000011605 */
/*0a50*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fda0003f05270 */
/*0a60*/ @!P0 DMUL R20, R4, 1.80143985094819840000e+16 ; /* 0x4350000004148828 */
/* 0x000e140000000000 */
/*0a70*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R21 ; /* 0x000000ffff058224 */
/* 0x001fe200078e0015 */
/*0a80*/ @!P0 LEA.HI R13, R21, 0xffffffca, RZ, 0xc ; /* 0xffffffca150d8811 */
/* 0x000fe200078f60ff */
/*0a90*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R20 ; /* 0x000000ffff048224 */
/* 0x000fc600078e0014 */
/*0aa0*/ LOP3.LUT R5, R5, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff05057812 */
/* 0x000fc800078ec0ff */
/*0ab0*/ LOP3.LUT R5, R5, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000005057812 */
/* 0x000fc800078efcff */
/*0ac0*/ ISETP.GE.U32.AND P1, PT, R5, 0x3ff6a09f, PT ; /* 0x3ff6a09f0500780c */
/* 0x000fda0003f26070 */
/*0ad0*/ @P1 IADD3 R7, R5, -0x100000, RZ ; /* 0xfff0000005071810 */
/* 0x000fca0007ffe0ff */
/*0ae0*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff051224 */
/* 0x000fcc00078e0007 */
/*0af0*/ DADD R8, R4, 1 ; /* 0x3ff0000004087429 */
/* 0x000e080000000000 */
/*0b00*/ DADD R4, R4, -1 ; /* 0xbff0000004047429 */
/* 0x000fe40000000000 */
/*0b10*/ MUFU.RCP64H R23, R9 ; /* 0x0000000900177308 */
/* 0x001e240000001800 */
/*0b20*/ DFMA R6, -R8, R22, 1 ; /* 0x3ff000000806742b */
/* 0x001e0c0000000116 */
/*0b30*/ DFMA R6, R6, R6, R6 ; /* 0x000000060606722b */
/* 0x001e0c0000000006 */
/*0b40*/ DFMA R22, R22, R6, R22 ; /* 0x000000061616722b */
/* 0x001e0c0000000016 */
/*0b50*/ DMUL R6, R22, R4 ; /* 0x0000000416067228 */
/* 0x001e0c0000000000 */
/*0b60*/ DFMA R6, R22, R4, R6 ; /* 0x000000041606722b */
/* 0x001e0c0000000006 */
/*0b70*/ DMUL R16, R6, R6 ; /* 0x0000000606107228 */
/* 0x001e080000000000 */
/*0b80*/ DADD R8, R4, -R6 ; /* 0x0000000004087229 */
/* 0x000fc80000000806 */
/*0b90*/ DFMA R10, R16, R10, c[0x2][0x8] ; /* 0x00800200100a762b */
/* 0x001e08000000000a */
/*0ba0*/ DMUL R14, R6, R6 ; /* 0x00000006060e7228 */
/* 0x000fc80000000000 */
/*0bb0*/ DFMA R10, R16, R10, c[0x2][0x10] ; /* 0x00800400100a762b */
/* 0x001e0c000000000a */
/*0bc0*/ DFMA R10, R16, R10, c[0x2][0x18] ; /* 0x00800600100a762b */
/* 0x001e0c000000000a */
/*0bd0*/ DFMA R10, R16, R10, c[0x2][0x20] ; /* 0x00800800100a762b */
/* 0x001e0c000000000a */
/*0be0*/ DFMA R10, R16, R10, c[0x2][0x28] ; /* 0x00800a00100a762b */
/* 0x001e0c000000000a */
/*0bf0*/ DFMA R18, R16, R10, c[0x2][0x30] ; /* 0x00800c001012762b */
/* 0x001e08000000000a */
/*0c00*/ DADD R10, R8, R8 ; /* 0x00000000080a7229 */
/* 0x000e480000000008 */
/*0c10*/ DFMA R8, R16, R18, c[0x2][0x38] ; /* 0x00800e001008762b */
/* 0x001e080000000012 */
/*0c20*/ DFMA R4, R4, -R6, R10 ; /* 0x800000060404722b */
/* 0x002e48000000000a */
/*0c30*/ DADD R24, -R8, c[0x2][0x38] ; /* 0x00800e0008187629 */
/* 0x001e080000000100 */
/*0c40*/ DMUL R4, R22, R4 ; /* 0x0000000416047228 */
/* 0x002fc80000000000 */
/*0c50*/ DFMA R24, R16, R18, R24 ; /* 0x000000121018722b */
/* 0x001e080000000018 */
/*0c60*/ DMUL R18, R6, R14 ; /* 0x0000000e06127228 */
/* 0x000e480000000000 */
/*0c70*/ DADD R16, RZ, R24 ; /* 0x00000000ff107229 */
/* 0x0010a40000000018 */
/*0c80*/ IADD3 R25, R5, 0x100000, RZ ; /* 0x0010000005197810 */
/* 0x001fe20007ffe0ff */
/*0c90*/ IMAD.MOV.U32 R24, RZ, RZ, R4 ; /* 0x000000ffff187224 */
/* 0x000fe200078e0004 */
/*0ca0*/ DFMA R22, R6, R14, -R18 ; /* 0x0000000e0616722b */
/* 0x002e080000000812 */
/*0cb0*/ DADD R16, R16, c[0x2][0x40] ; /* 0x0080100010107629 */
/* 0x004e480000000000 */
/*0cc0*/ DFMA R10, R6, R6, -R14 ; /* 0x00000006060a722b */
/* 0x000e88000000080e */
/*0cd0*/ DFMA R22, R4, R14, R22 ; /* 0x0000000e0416722b */
/* 0x001fc80000000016 */
/*0ce0*/ DADD R14, R8, R16 ; /* 0x00000000080e7229 */
/* 0x002e080000000010 */
/*0cf0*/ DFMA R24, R6, R24, R10 ; /* 0x000000180618722b */
/* 0x004e48000000000a */
/*0d00*/ DMUL R10, R14, R18 ; /* 0x000000120e0a7228 */
/* 0x001e080000000000 */
/*0d10*/ DFMA R22, R6, R24, R22 ; /* 0x000000180616722b */
/* 0x002fc80000000016 */
/*0d20*/ DADD R24, R8, -R14 ; /* 0x0000000008187229 */
/* 0x000e48000000080e */
/*0d30*/ DFMA R8, R14, R18, -R10 ; /* 0x000000120e08722b */
/* 0x001e08000000080a */
/*0d40*/ DADD R24, R16, R24 ; /* 0x0000000010187229 */
/* 0x002fc80000000018 */
/*0d50*/ DFMA R8, R14, R22, R8 ; /* 0x000000160e08722b */
/* 0x001e0c0000000008 */
/*0d60*/ DFMA R24, R24, R18, R8 ; /* 0x000000121818722b */
/* 0x0010640000000008 */
/*0d70*/ IMAD.MOV.U32 R18, RZ, RZ, 0x69ce2bdf ; /* 0x69ce2bdfff127424 */
/* 0x001fe400078e00ff */
/*0d80*/ IMAD.MOV.U32 R19, RZ, RZ, 0x3e5ade15 ; /* 0x3e5ade15ff137424 */
/* 0x000fe400078e00ff */
/*0d90*/ DADD R14, R10, R24 ; /* 0x000000000a0e7229 */
/* 0x002e0c0000000018 */
/*0da0*/ DADD R8, R6, R14 ; /* 0x0000000006087229 */
/* 0x001e08000000000e */
/*0db0*/ DADD R10, R10, -R14 ; /* 0x000000000a0a7229 */
/* 0x000e48000000080e */
/*0dc0*/ DADD R6, R6, -R8 ; /* 0x0000000006067229 */
/* 0x001e080000000808 */
/*0dd0*/ DADD R10, R24, R10 ; /* 0x00000000180a7229 */
/* 0x002fc8000000000a */
/*0de0*/ DADD R6, R14, R6 ; /* 0x000000000e067229 */
/* 0x0010640000000006 */
/*0df0*/ IADD3 R14, R13.reuse, -0x3ff, RZ ; /* 0xfffffc010d0e7810 */
/* 0x041fe40007ffe0ff */
/*0e00*/ @P1 IADD3 R14, R13, -0x3fe, RZ ; /* 0xfffffc020d0e1810 */
/* 0x000fe40007ffe0ff */
/*0e10*/ DADD R6, R10, R6 ; /* 0x000000000a067229 */
/* 0x0020640000000006 */
/*0e20*/ LOP3.LUT R10, R14, 0x80000000, RZ, 0x3c, !PT ; /* 0x800000000e0a7812 */
/* 0x001fe200078e3cff */
/*0e30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x43300000 ; /* 0x43300000ff0b7424 */
/* 0x000fc600078e00ff */
/*0e40*/ DADD R6, R4, R6 ; /* 0x0000000004067229 */
/* 0x002e080000000006 */
/*0e50*/ DADD R14, R10, c[0x2][0x48] ; /* 0x008012000a0e7629 */
/* 0x000fc80000000000 */
/*0e60*/ DADD R10, R8, R6 ; /* 0x00000000080a7229 */
/* 0x001e0c0000000006 */
/*0e70*/ DFMA R4, R14, c[0x2][0x50], R10 ; /* 0x008014000e047a2b */
/* 0x001e08000000000a */
/*0e80*/ DADD R8, R8, -R10 ; /* 0x0000000008087229 */
/* 0x000e48000000080a */
/*0e90*/ DFMA R16, -R14, c[0x2][0x50], R4 ; /* 0x008014000e107a2b */
/* 0x001e080000000104 */
/*0ea0*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x002fc80000000008 */
/*0eb0*/ DADD R16, -R10, R16 ; /* 0x000000000a107229 */
/* 0x001e0c0000000110 */
/*0ec0*/ DADD R8, R8, -R16 ; /* 0x0000000008087229 */
/* 0x001e0c0000000810 */
/*0ed0*/ DFMA R8, R14, c[0x2][0x58], R8 ; /* 0x008016000e087a2b */
/* 0x001e0c0000000008 */
/*0ee0*/ DADD R6, R4, R8 ; /* 0x0000000004067229 */
/* 0x001e0c0000000008 */
/*0ef0*/ DADD R10, R4, -R6 ; /* 0x00000000040a7229 */
/* 0x001e080000000806 */
/*0f00*/ DMUL R4, R6, 3 ; /* 0x4008000006047828 */
/* 0x000e480000000000 */
/*0f10*/ DADD R10, R8, R10 ; /* 0x00000000080a7229 */
/* 0x001fc8000000000a */
/*0f20*/ DFMA R6, R6, 3, -R4 ; /* 0x400800000606782b */
/* 0x002e0c0000000804 */
/*0f30*/ DFMA R6, R10, 3, R6 ; /* 0x400800000a06782b */
/* 0x0010640000000006 */
/*0f40*/ IMAD.MOV.U32 R10, RZ, RZ, 0x652b82fe ; /* 0x652b82feff0a7424 */
/* 0x001fe400078e00ff */
/*0f50*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3ff71547 ; /* 0x3ff71547ff0b7424 */
/* 0x000fe400078e00ff */
/*0f60*/ DADD R8, R4, R6 ; /* 0x0000000004087229 */
/* 0x002e0c0000000006 */
/*0f70*/ DFMA R10, R8, R10, 6.75539944105574400000e+15 ; /* 0x43380000080a742b */
/* 0x001e08000000000a */
/*0f80*/ FSETP.GEU.AND P0, PT, |R9|, 4.1917929649353027344, PT ; /* 0x4086232b0900780b */
/* 0x000fe40003f0e200 */
/*0f90*/ DADD R14, R10, -6.75539944105574400000e+15 ; /* 0xc33800000a0e7429 */
/* 0x001e0c0000000000 */
/*0fa0*/ DFMA R16, R14, c[0x2][0x60], R8 ; /* 0x008018000e107a2b */
/* 0x001e0c0000000008 */
/*0fb0*/ DFMA R14, R14, c[0x2][0x68], R16 ; /* 0x00801a000e0e7a2b */
/* 0x001e0c0000000010 */
/*0fc0*/ DFMA R16, R14, R18, c[0x2][0x70] ; /* 0x00801c000e10762b */
/* 0x001e0c0000000012 */
/*0fd0*/ DFMA R16, R14, R16, c[0x2][0x78] ; /* 0x00801e000e10762b */
/* 0x001e0c0000000010 */
/*0fe0*/ DFMA R16, R14, R16, c[0x2][0x80] ; /* 0x008020000e10762b */
/* 0x001e0c0000000010 */
/*0ff0*/ DFMA R16, R14, R16, c[0x2][0x88] ; /* 0x008022000e10762b */
/* 0x001e0c0000000010 */
/*1000*/ DFMA R16, R14, R16, c[0x2][0x90] ; /* 0x008024000e10762b */
/* 0x001e0c0000000010 */
/*1010*/ DFMA R16, R14, R16, c[0x2][0x98] ; /* 0x008026000e10762b */
/* 0x001e0c0000000010 */
/*1020*/ DFMA R16, R14, R16, c[0x2][0xa0] ; /* 0x008028000e10762b */
/* 0x001e0c0000000010 */
/*1030*/ DFMA R16, R14, R16, c[0x2][0xa8] ; /* 0x00802a000e10762b */
/* 0x001e0c0000000010 */
/*1040*/ DFMA R16, R14, R16, c[0x2][0xb0] ; /* 0x00802c000e10762b */
/* 0x001e0c0000000010 */
/*1050*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e0c0000000010 */
/*1060*/ DFMA R16, R14, R16, 1 ; /* 0x3ff000000e10742b */
/* 0x001e140000000010 */
/*1070*/ IMAD R15, R10, 0x100000, R17 ; /* 0x001000000a0f7824 */
/* 0x001fe400078e0211 */
/*1080*/ IMAD.MOV.U32 R14, RZ, RZ, R16 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0010 */
/*1090*/ @!P0 BRA 0x1170 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*10a0*/ FSETP.GEU.AND P1, PT, |R9|, 4.2275390625, PT ; /* 0x408748000900780b */
/* 0x000fe20003f2e200 */
/*10b0*/ DADD R14, R8, +INF ; /* 0x7ff00000080e7429 */
/* 0x000fc80000000000 */
/*10c0*/ DSETP.GEU.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800722a */
/* 0x000e0c0003f0e000 */
/*10d0*/ FSEL R14, R14, RZ, P0 ; /* 0x000000ff0e0e7208 */
/* 0x001fe40000000000 */
/*10e0*/ @!P1 LEA.HI R11, R10, R10, RZ, 0x1 ; /* 0x0000000a0a0b9211 */
/* 0x000fe400078f08ff */
/*10f0*/ FSEL R15, R15, RZ, P0 ; /* 0x000000ff0f0f7208 */
/* 0x000fe40000000000 */
/*1100*/ @!P1 SHF.R.S32.HI R11, RZ, 0x1, R11 ; /* 0x00000001ff0b9819 */
/* 0x000fca000001140b */
/*1110*/ @!P1 IMAD.IADD R10, R10, 0x1, -R11 ; /* 0x000000010a0a9824 */
/* 0x000fe400078e0a0b */
/*1120*/ @!P1 IMAD R11, R11, 0x100000, R17 ; /* 0x001000000b0b9824 */
/* 0x000fc600078e0211 */
/*1130*/ @!P1 LEA R17, R10, 0x3ff00000, 0x14 ; /* 0x3ff000000a119811 */
/* 0x000fe200078ea0ff */
/*1140*/ @!P1 IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a9224 */
/* 0x000fe400078e0010 */
/*1150*/ @!P1 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff109224 */
/* 0x000fcc00078e00ff */
/*1160*/ @!P1 DMUL R14, R10, R16 ; /* 0x000000100a0e9228 */
/* 0x0000540000000000 */
/*1170*/ LOP3.LUT R10, R15, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0f0a7812 */
/* 0x003fe200078ec0ff */
/*1180*/ DADD R4, R4, -R8 ; /* 0x0000000004047229 */
/* 0x000e220000000808 */
/*1190*/ IMAD.MOV.U32 R13, RZ, RZ, 0x0 ; /* 0x00000000ff0d7424 */
/* 0x000fe400078e00ff */
/*11a0*/ ISETP.NE.AND P0, PT, R10, 0x7ff00000, PT ; /* 0x7ff000000a00780c */
/* 0x000fc60003f05270 */
/*11b0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x001e220000000004 */
/*11c0*/ ISETP.EQ.AND P0, PT, R14, RZ, !P0 ; /* 0x000000ff0e00720c */
/* 0x000fda0004702270 */
/*11d0*/ @!P0 DFMA R14, R4, R14, R14 ; /* 0x0000000e040e822b */
/* 0x001062000000000e */
/*11e0*/ RET.REL.NODEC R12 0x0 ; /* 0xffffee100c007950 */
/* 0x000ff40003c3ffff */
/*11f0*/ BRA 0x11f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
// Setup for measuing time
#include <sys/time.h>
#include <time.h>
int timeval_subtract(struct timeval* result,
struct timeval* t2,
struct timeval* t1) {
unsigned int resolution=1000000;
long int diff = (t2->tv_usec + resolution * t2->tv_sec) -
(t1->tv_usec + resolution * t1->tv_sec);
result->tv_sec = diff / resolution;
result->tv_usec = diff % resolution;
return (diff<0);
}
void seqFunct(float* m_out) {
for (int i = 1; i <= 753411; i++) {
m_out[i-1] = pow(i/(i-2.3), 3);
}
}
__global__ void parFunct(float *d_in, float *d_out, int limit) {
const unsigned int lid = threadIdx.x; //local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
float x;
if (gid <= limit) {
x = d_in[gid];
d_out[gid] = pow((x/(x-2.3)),3); // Compute
}
}
int main(int argc, char** argv) {
unsigned int num_threads = 753411;
unsigned int mem_size = num_threads*sizeof(float);
// Initialize vars for measuring time
unsigned long int par_elapsed;
unsigned long int seq_elapsed;
struct timeval p_start, p_end, p_diff;
struct timeval s_start, s_end, s_diff;
// alocate host memory
float* h_in = (float*) malloc(mem_size);
float* h_out = (float*) malloc(mem_size);
float* m_out = (float*) malloc(mem_size);
// iniitalize the memory
for(unsigned int i=1; i<=num_threads; ++i) {
h_in[i-1] = (float)(i);
}
// allocate device memory
float* d_in;
float* d_out;
cudaMalloc((void**)&d_in, mem_size);
cudaMalloc((void**)&d_out, mem_size);
// copy host memory to device
cudaMemcpy(d_in, h_in, mem_size, cudaMemcpyHostToDevice);
// Start timer
gettimeofday(&p_start, NULL);
// execute the kernel
parFunct<<< ceil(num_threads/1024.0), 1024>>>(d_in, d_out, num_threads);
cudaThreadSynchronize();
// calc elapsed time
gettimeofday(&p_end, NULL);
timeval_subtract(&p_diff, &p_end, &p_start);
par_elapsed = p_diff.tv_sec*1e6+p_diff.tv_usec;
cudaMemcpy(h_out, d_out, mem_size, cudaMemcpyDeviceToHost);
gettimeofday(&s_start, NULL);
// execute the kernel
seqFunct(m_out);
// Print elapsed time
gettimeofday(&s_end, NULL);
timeval_subtract(&s_diff, &s_end, &s_start);
seq_elapsed = s_diff.tv_sec*1e6+s_diff.tv_usec;
//printf("Took %d microseconds (%.2fms)\n", elapsed, elapsed/1000.0);
bool isValid = true;
for (int i = 0; i < num_threads; i++) {
if (abs(m_out[i] - h_out[i]) > 0.000001) {
isValid = false;
break;
}
}
if (isValid) {
printf("VALID\n");
}
else {
printf("INVALID\n");
}
printf("CPU Time: %d microseconds (%.fms)\n", seq_elapsed, seq_elapsed/1000.0);
printf("GPU Time: %d microseconds (%.fms)\n", par_elapsed, par_elapsed/1000.0);
// clean-up memory
free(h_in); free(h_out);
free(m_out);
cudaFree(d_in); cudaFree(d_out);
} | .file "tmpxft_000f07c9_00000000-6_simpleCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16timeval_subtractP7timevalS0_S0_
.type _Z16timeval_subtractP7timevalS0_S0_, @function
_Z16timeval_subtractP7timevalS0_S0_:
.LFB2057:
.cfi_startproc
endbr64
imulq $1000000, (%rsi), %rcx
addq 8(%rsi), %rcx
imulq $1000000, (%rdx), %rax
addq 8(%rdx), %rax
subq %rax, %rcx
movabsq $4835703278458516699, %rdx
movq %rcx, %rax
imulq %rdx
sarq $18, %rdx
movq %rcx, %rax
sarq $63, %rax
subq %rax, %rdx
movq %rdx, (%rdi)
imulq $1000000, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
movq %rax, 8(%rdi)
shrq $63, %rcx
movq %rcx, %rax
ret
.cfi_endproc
.LFE2057:
.size _Z16timeval_subtractP7timevalS0_S0_, .-_Z16timeval_subtractP7timevalS0_S0_
.globl _Z8seqFunctPf
.type _Z8seqFunctPf, @function
_Z8seqFunctPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl $1, %ebx
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movapd %xmm0, %xmm1
subsd .LC1(%rip), %xmm1
divsd %xmm1, %xmm0
movsd .LC0(%rip), %xmm1
call pow@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%rbp,%rbx,4)
addq $1, %rbx
cmpq $753412, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8seqFunctPf, .-_Z8seqFunctPf
.globl _Z30__device_stub__Z8parFunctPfS_iPfS_i
.type _Z30__device_stub__Z8parFunctPfS_iPfS_i, @function
_Z30__device_stub__Z8parFunctPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8parFunctPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z8parFunctPfS_iPfS_i, .-_Z30__device_stub__Z8parFunctPfS_iPfS_i
.globl _Z8parFunctPfS_i
.type _Z8parFunctPfS_i, @function
_Z8parFunctPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8parFunctPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8parFunctPfS_i, .-_Z8parFunctPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "CPU Time: %d microseconds (%.fms)\n"
.align 8
.LC8:
.string "GPU Time: %d microseconds (%.fms)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "VALID\n"
.LC10:
.string "INVALID\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $3013644, %edi
call malloc@PLT
movq %rax, %rbx
movl $3013644, %edi
call malloc@PLT
movq %rax, %rbp
movl $3013644, %edi
call malloc@PLT
movq %rax, %r12
movl $1, %eax
.L19:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $753412, %rax
jne .L19
movq %rsp, %rdi
movl $3013644, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $3013644, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $3013644, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $736, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L20:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %r13
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
leaq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
movq %r13, %rsi
call _Z16timeval_subtractP7timevalS0_S0_
pxor %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
addsd %xmm1, %xmm0
comisd .LC3(%rip), %xmm0
jnb .L21
cvttsd2siq %xmm0, %r13
.L22:
movl $2, %ecx
movl $3013644, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %r15
movl $0, %esi
movq %r15, %rdi
call gettimeofday@PLT
movq %r12, %rdi
call _Z8seqFunctPf
leaq 80(%rsp), %r14
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
leaq 96(%rsp), %rdi
movq %r15, %rdx
movq %r14, %rsi
call _Z16timeval_subtractP7timevalS0_S0_
pxor %xmm0, %xmm0
cvtsi2sdq 96(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 104(%rsp), %xmm1
addsd %xmm1, %xmm0
comisd .LC3(%rip), %xmm0
jnb .L23
cvttsd2siq %xmm0, %r14
.L24:
movl $0, %eax
movss .LC4(%rip), %xmm2
movsd .LC5(%rip), %xmm1
.L26:
movss (%r12,%rax), %xmm0
subss 0(%rbp,%rax), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L25
addq $4, %rax
cmpq $3013644, %rax
jne .L26
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L32:
testq %r14, %r14
js .L28
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
.L29:
divsd .LC6(%rip), %xmm0
movq %r14, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testq %r13, %r13
js .L30
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
.L31:
divsd .LC6(%rip), %xmm0
movq %r13, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $753411, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z8parFunctPfS_iPfS_i
jmp .L20
.L21:
subsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %r13
btcq $63, %r13
jmp .L22
.L23:
subsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %r14
btcq $63, %r14
jmp .L24
.L28:
movq %r14, %rax
shrq %rax
movq %r14, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L29
.L30:
movq %r13, %rax
shrq %rax
movq %r13, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L31
.L25:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L32
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z8parFunctPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8parFunctPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074266112
.align 8
.LC1:
.long 1717986918
.long 1073899110
.align 8
.LC2:
.long 0
.long 1093567616
.align 8
.LC3:
.long 0
.long 1138753536
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC5:
.long -1598689907
.long 1051772663
.align 8
.LC6:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <cuda_runtime.h>
// Setup for measuing time
#include <sys/time.h>
#include <time.h>
int timeval_subtract(struct timeval* result,
struct timeval* t2,
struct timeval* t1) {
unsigned int resolution=1000000;
long int diff = (t2->tv_usec + resolution * t2->tv_sec) -
(t1->tv_usec + resolution * t1->tv_sec);
result->tv_sec = diff / resolution;
result->tv_usec = diff % resolution;
return (diff<0);
}
void seqFunct(float* m_out) {
for (int i = 1; i <= 753411; i++) {
m_out[i-1] = pow(i/(i-2.3), 3);
}
}
__global__ void parFunct(float *d_in, float *d_out, int limit) {
const unsigned int lid = threadIdx.x; //local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
float x;
if (gid <= limit) {
x = d_in[gid];
d_out[gid] = pow((x/(x-2.3)),3); // Compute
}
}
int main(int argc, char** argv) {
unsigned int num_threads = 753411;
unsigned int mem_size = num_threads*sizeof(float);
// Initialize vars for measuring time
unsigned long int par_elapsed;
unsigned long int seq_elapsed;
struct timeval p_start, p_end, p_diff;
struct timeval s_start, s_end, s_diff;
// alocate host memory
float* h_in = (float*) malloc(mem_size);
float* h_out = (float*) malloc(mem_size);
float* m_out = (float*) malloc(mem_size);
// iniitalize the memory
for(unsigned int i=1; i<=num_threads; ++i) {
h_in[i-1] = (float)(i);
}
// allocate device memory
float* d_in;
float* d_out;
cudaMalloc((void**)&d_in, mem_size);
cudaMalloc((void**)&d_out, mem_size);
// copy host memory to device
cudaMemcpy(d_in, h_in, mem_size, cudaMemcpyHostToDevice);
// Start timer
gettimeofday(&p_start, NULL);
// execute the kernel
parFunct<<< ceil(num_threads/1024.0), 1024>>>(d_in, d_out, num_threads);
cudaThreadSynchronize();
// calc elapsed time
gettimeofday(&p_end, NULL);
timeval_subtract(&p_diff, &p_end, &p_start);
par_elapsed = p_diff.tv_sec*1e6+p_diff.tv_usec;
cudaMemcpy(h_out, d_out, mem_size, cudaMemcpyDeviceToHost);
gettimeofday(&s_start, NULL);
// execute the kernel
seqFunct(m_out);
// Print elapsed time
gettimeofday(&s_end, NULL);
timeval_subtract(&s_diff, &s_end, &s_start);
seq_elapsed = s_diff.tv_sec*1e6+s_diff.tv_usec;
//printf("Took %d microseconds (%.2fms)\n", elapsed, elapsed/1000.0);
bool isValid = true;
for (int i = 0; i < num_threads; i++) {
if (abs(m_out[i] - h_out[i]) > 0.000001) {
isValid = false;
break;
}
}
if (isValid) {
printf("VALID\n");
}
else {
printf("INVALID\n");
}
printf("CPU Time: %d microseconds (%.fms)\n", seq_elapsed, seq_elapsed/1000.0);
printf("GPU Time: %d microseconds (%.fms)\n", par_elapsed, par_elapsed/1000.0);
// clean-up memory
free(h_in); free(h_out);
free(m_out);
cudaFree(d_in); cudaFree(d_out);
} | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
// Setup for measuing time
#include <sys/time.h>
#include <time.h>
int timeval_subtract(struct timeval* result,
struct timeval* t2,
struct timeval* t1) {
unsigned int resolution=1000000;
long int diff = (t2->tv_usec + resolution * t2->tv_sec) -
(t1->tv_usec + resolution * t1->tv_sec);
result->tv_sec = diff / resolution;
result->tv_usec = diff % resolution;
return (diff<0);
}
void seqFunct(float* m_out) {
for (int i = 1; i <= 753411; i++) {
m_out[i-1] = pow(i/(i-2.3), 3);
}
}
__global__ void parFunct(float *d_in, float *d_out, int limit) {
const unsigned int lid = threadIdx.x; //local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
float x;
if (gid <= limit) {
x = d_in[gid];
d_out[gid] = pow((x/(x-2.3)),3); // Compute
}
}
int main(int argc, char** argv) {
unsigned int num_threads = 753411;
unsigned int mem_size = num_threads*sizeof(float);
// Initialize vars for measuring time
unsigned long int par_elapsed;
unsigned long int seq_elapsed;
struct timeval p_start, p_end, p_diff;
struct timeval s_start, s_end, s_diff;
// alocate host memory
float* h_in = (float*) malloc(mem_size);
float* h_out = (float*) malloc(mem_size);
float* m_out = (float*) malloc(mem_size);
// iniitalize the memory
for(unsigned int i=1; i<=num_threads; ++i) {
h_in[i-1] = (float)(i);
}
// allocate device memory
float* d_in;
float* d_out;
hipMalloc((void**)&d_in, mem_size);
hipMalloc((void**)&d_out, mem_size);
// copy host memory to device
hipMemcpy(d_in, h_in, mem_size, hipMemcpyHostToDevice);
// Start timer
gettimeofday(&p_start, NULL);
// execute the kernel
parFunct<<< ceil(num_threads/1024.0), 1024>>>(d_in, d_out, num_threads);
hipDeviceSynchronize();
// calc elapsed time
gettimeofday(&p_end, NULL);
timeval_subtract(&p_diff, &p_end, &p_start);
par_elapsed = p_diff.tv_sec*1e6+p_diff.tv_usec;
hipMemcpy(h_out, d_out, mem_size, hipMemcpyDeviceToHost);
gettimeofday(&s_start, NULL);
// execute the kernel
seqFunct(m_out);
// Print elapsed time
gettimeofday(&s_end, NULL);
timeval_subtract(&s_diff, &s_end, &s_start);
seq_elapsed = s_diff.tv_sec*1e6+s_diff.tv_usec;
//printf("Took %d microseconds (%.2fms)\n", elapsed, elapsed/1000.0);
bool isValid = true;
for (int i = 0; i < num_threads; i++) {
if (abs(m_out[i] - h_out[i]) > 0.000001) {
isValid = false;
break;
}
}
if (isValid) {
printf("VALID\n");
}
else {
printf("INVALID\n");
}
printf("CPU Time: %d microseconds (%.fms)\n", seq_elapsed, seq_elapsed/1000.0);
printf("GPU Time: %d microseconds (%.fms)\n", par_elapsed, par_elapsed/1000.0);
// clean-up memory
free(h_in); free(h_out);
free(m_out);
hipFree(d_in); hipFree(d_out);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
// Setup for measuing time
#include <sys/time.h>
#include <time.h>
int timeval_subtract(struct timeval* result,
struct timeval* t2,
struct timeval* t1) {
unsigned int resolution=1000000;
long int diff = (t2->tv_usec + resolution * t2->tv_sec) -
(t1->tv_usec + resolution * t1->tv_sec);
result->tv_sec = diff / resolution;
result->tv_usec = diff % resolution;
return (diff<0);
}
void seqFunct(float* m_out) {
for (int i = 1; i <= 753411; i++) {
m_out[i-1] = pow(i/(i-2.3), 3);
}
}
__global__ void parFunct(float *d_in, float *d_out, int limit) {
const unsigned int lid = threadIdx.x; //local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
float x;
if (gid <= limit) {
x = d_in[gid];
d_out[gid] = pow((x/(x-2.3)),3); // Compute
}
}
int main(int argc, char** argv) {
unsigned int num_threads = 753411;
unsigned int mem_size = num_threads*sizeof(float);
// Initialize vars for measuring time
unsigned long int par_elapsed;
unsigned long int seq_elapsed;
struct timeval p_start, p_end, p_diff;
struct timeval s_start, s_end, s_diff;
// alocate host memory
float* h_in = (float*) malloc(mem_size);
float* h_out = (float*) malloc(mem_size);
float* m_out = (float*) malloc(mem_size);
// iniitalize the memory
for(unsigned int i=1; i<=num_threads; ++i) {
h_in[i-1] = (float)(i);
}
// allocate device memory
float* d_in;
float* d_out;
hipMalloc((void**)&d_in, mem_size);
hipMalloc((void**)&d_out, mem_size);
// copy host memory to device
hipMemcpy(d_in, h_in, mem_size, hipMemcpyHostToDevice);
// Start timer
gettimeofday(&p_start, NULL);
// execute the kernel
parFunct<<< ceil(num_threads/1024.0), 1024>>>(d_in, d_out, num_threads);
hipDeviceSynchronize();
// calc elapsed time
gettimeofday(&p_end, NULL);
timeval_subtract(&p_diff, &p_end, &p_start);
par_elapsed = p_diff.tv_sec*1e6+p_diff.tv_usec;
hipMemcpy(h_out, d_out, mem_size, hipMemcpyDeviceToHost);
gettimeofday(&s_start, NULL);
// execute the kernel
seqFunct(m_out);
// Print elapsed time
gettimeofday(&s_end, NULL);
timeval_subtract(&s_diff, &s_end, &s_start);
seq_elapsed = s_diff.tv_sec*1e6+s_diff.tv_usec;
//printf("Took %d microseconds (%.2fms)\n", elapsed, elapsed/1000.0);
bool isValid = true;
for (int i = 0; i < num_threads; i++) {
if (abs(m_out[i] - h_out[i]) > 0.000001) {
isValid = false;
break;
}
}
if (isValid) {
printf("VALID\n");
}
else {
printf("INVALID\n");
}
printf("CPU Time: %d microseconds (%.fms)\n", seq_elapsed, seq_elapsed/1000.0);
printf("GPU Time: %d microseconds (%.fms)\n", par_elapsed, par_elapsed/1000.0);
// clean-up memory
free(h_in); free(h_out);
free(m_out);
hipFree(d_in); hipFree(d_out);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8parFunctPfS_i
.globl _Z8parFunctPfS_i
.p2align 8
.type _Z8parFunctPfS_i,@function
_Z8parFunctPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_ge_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_mov_b32 s5, 0x3fba6564
s_mov_b32 s4, 0x968915a9
s_mov_b32 s7, 0x3fbdee67
s_mov_b32 s6, 0x4222de17
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
s_mov_b32 s1, 0xc0026666
s_mov_b32 s0, 0x66666666
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[2:3], s[0:1]
s_mov_b32 s1, 0x3fe55555
s_mov_b32 s0, 0x55555555
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], v[2:3]
v_div_scale_f64 v[12:13], vcc_lo, v[2:3], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[10:11], v[12:13], v[8:9]
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
v_div_fixup_f64 v[2:3], v[6:7], v[4:5], v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[4:5]
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v6
v_add_f64 v[6:7], v[4:5], 1.0
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
v_add_f64 v[14:15], v[6:7], -1.0
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[6:7], v[10:11]
v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[12:13], -v[6:7]
v_add_f64 v[16:17], v[6:7], -v[16:17]
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[16:17], -v[4:5]
v_add_f64 v[6:7], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[4:5], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[6:7], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[6:7], -v[10:11]
v_mul_f64 v[10:11], v[6:7], v[6:7]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[6:7], v[6:7], -v[10:11]
v_add_f64 v[12:13], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[12:13], v[8:9]
v_add_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], s[6:7], s[4:5]
s_mov_b32 s5, 0x3fbe25e4
s_mov_b32 s4, 0x3abe935a
v_add_f64 v[10:11], v[12:13], -v[10:11]
v_mul_f64 v[20:21], v[6:7], v[12:13]
s_mov_b32 s7, 0x3ff71547
s_mov_b32 s6, 0x652b82fe
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fc110ef
s_mov_b32 s4, 0x47e6c9c2
v_add_f64 v[8:9], v[8:9], -v[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fc3b13b
s_mov_b32 s4, 0xcfa74449
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fc745d1
s_mov_b32 s4, 0x71bf3c30
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fcc71c7
s_mov_b32 s4, 0x1c7792ce
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fd24924
s_mov_b32 s4, 0x924920da
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3fd99999
s_mov_b32 s4, 0x9999999c
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[4:5]
s_mov_b32 s5, 0x3c7abc9e
s_mov_b32 s4, 0x3b39803f
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[12:13], v[14:15]
v_fma_f64 v[10:11], v[12:13], v[14:15], -v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
v_add_f64 v[14:15], v[16:17], v[10:11]
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[18:19], v[14:15], s[0:1]
v_add_f64 v[16:17], v[14:15], -v[16:17]
s_mov_b32 s1, 0xbfe55555
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_f64 v[22:23], v[18:19], s[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_fma_f64 v[16:17], v[12:13], v[6:7], -v[20:21]
s_mov_b32 s1, 0x3c8543b0
s_mov_b32 s0, 0xd5df274d
v_add_f64 v[14:15], v[14:15], -v[22:23]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], s[0:1]
v_fma_f64 v[12:13], v[12:13], v[4:5], v[16:17]
s_mov_b32 s1, 0x3fe62e42
s_mov_b32 s0, 0xfefa39ef
v_ldexp_f64 v[4:5], v[4:5], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], v[14:15]
v_fma_f64 v[8:9], v[8:9], v[6:7], v[12:13]
v_ldexp_f64 v[6:7], v[6:7], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[18:19], v[10:11]
v_add_f64 v[14:15], v[20:21], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[16:17], v[18:19], -v[12:13]
v_mul_f64 v[18:19], v[14:15], v[12:13]
v_add_f64 v[20:21], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[10:11], v[10:11], v[16:17]
v_fma_f64 v[16:17], v[14:15], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[20:21]
v_fma_f64 v[10:11], v[14:15], v[10:11], v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[8:9], v[12:13], v[10:11]
v_frexp_exp_i32_f64_e32 v12, v[2:3]
v_add_f64 v[10:11], v[18:19], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_cvt_f64_i32_e32 v[12:13], v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[6:7], v[10:11]
v_add_f64 v[16:17], v[10:11], -v[18:19]
v_mul_f64 v[18:19], v[12:13], s[0:1]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[6:7], v[14:15], -v[6:7]
v_add_f64 v[8:9], v[8:9], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[16:17], v[12:13], s[0:1], -v[18:19]
s_mov_b32 s1, 0xbfe62e42
v_add_f64 v[6:7], v[10:11], -v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[8:9]
v_fma_f64 v[8:9], v[12:13], s[4:5], v[16:17]
s_mov_b32 s5, 0xbc7abc9e
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[18:19], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[14:15], v[4:5]
v_add_f64 v[18:19], v[6:7], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[6:7], v[10:11]
v_add_f64 v[14:15], v[10:11], -v[14:15]
v_add_f64 v[8:9], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[12:13], -v[6:7]
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[12:13], -v[16:17]
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_add_f64 v[14:15], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[20:21]
v_add_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[14:15], -v[8:9]
v_add_f64 v[6:7], v[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[14:15], -v[10:11]
v_add_f64 v[4:5], v[4:5], -v[10:11]
v_add_f64 v[16:17], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[14:15]
v_add_f64 v[10:11], v[16:17], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[8:9]
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[6:7], -v[16:17]
v_mul_f64 v[10:11], v[6:7], 0x40080000
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[6:7], 0x40080000, -v[10:11]
v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
v_fma_f64 v[4:5], v[4:5], 0x40080000, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[10:11], v[4:5]
v_dual_cndmask_b32 v9, v7, v11 :: v_dual_cndmask_b32 v8, v6, v10
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]|
v_add_f64 v[4:5], v[4:5], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_mul_f64 v[12:13], v[8:9], s[6:7]
v_cndmask_b32_e32 v4, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[12:13], v[12:13]
v_fma_f64 v[14:15], v[12:13], s[0:1], v[8:9]
s_mov_b32 s1, 0x3e928af3
s_mov_b32 s0, 0xfca7ab0c
v_cvt_i32_f64_e32 v18, v[12:13]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[14:15], v[12:13], s[4:5], v[14:15]
s_mov_b32 s5, 0x3e5ade15
s_mov_b32 s4, 0x6a5dcb37
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], s[4:5], s[0:1]
s_mov_b32 s1, 0x3ec71dee
s_mov_b32 s0, 0x623fde64
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[0:1]
s_mov_b32 s1, 0x3efa0199
s_mov_b32 s0, 0x7c89e6b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[0:1]
s_mov_b32 s1, 0x3f2a01a0
s_mov_b32 s0, 0x14761f6e
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[0:1]
s_mov_b32 s1, 0x3f56c16c
s_mov_b32 s0, 0x1852b7b0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[0:1]
s_mov_b32 s1, 0x3f811111
s_mov_b32 s0, 0x11122322
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[0:1]
s_mov_b32 s1, 0x3fa55555
s_mov_b32 s0, 0x555502a1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[0:1]
s_mov_b32 s1, 0x3fc55555
s_mov_b32 s0, 0x55555511
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[0:1]
s_mov_b32 s1, 0x3fe00000
s_mov_b32 s0, 11
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[0:1]
v_cmp_nlt_f64_e64 s0, 0x40900000, v[8:9]
v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[8:9]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[16:17], v[14:15], v[16:17], 1.0
s_and_b32 vcc_lo, s1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[14:15], v[16:17], 1.0
v_ldexp_f64 v[10:11], v[12:13], v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, 0x7ff00000, v11, s0
v_cmp_eq_f64_e64 s0, 0, v[2:3]
v_cndmask_b32_e64 v7, 0, v6, s1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, 0, v10, vcc_lo
v_cmp_class_f64_e64 s1, v[2:3], 0x204
v_fma_f64 v[4:5], v[6:7], v[4:5], v[6:7]
v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v4, v6, vcc_lo
v_cndmask_b32_e32 v4, v5, v7, vcc_lo
v_cndmask_b32_e64 v5, 0x7ff00000, 0, s0
s_or_b32 vcc_lo, s0, s1
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_cndmask_b32_e64 v2, v2, 0, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_bfi_b32 v4, 0x7fffffff, v4, v3
v_bfi_b32 v3, 0x7fffffff, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v3, v4, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
v_cvt_f32_f64_e32 v2, v[2:3]
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8parFunctPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 24
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8parFunctPfS_i, .Lfunc_end0-_Z8parFunctPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8parFunctPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8parFunctPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 24
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <math.h>
#include <hip/hip_runtime.h>
// Setup for measuing time
#include <sys/time.h>
#include <time.h>
int timeval_subtract(struct timeval* result,
struct timeval* t2,
struct timeval* t1) {
unsigned int resolution=1000000;
long int diff = (t2->tv_usec + resolution * t2->tv_sec) -
(t1->tv_usec + resolution * t1->tv_sec);
result->tv_sec = diff / resolution;
result->tv_usec = diff % resolution;
return (diff<0);
}
void seqFunct(float* m_out) {
for (int i = 1; i <= 753411; i++) {
m_out[i-1] = pow(i/(i-2.3), 3);
}
}
__global__ void parFunct(float *d_in, float *d_out, int limit) {
const unsigned int lid = threadIdx.x; //local id inside a block
const unsigned int gid = blockIdx.x*blockDim.x + lid; // global id
float x;
if (gid <= limit) {
x = d_in[gid];
d_out[gid] = pow((x/(x-2.3)),3); // Compute
}
}
int main(int argc, char** argv) {
unsigned int num_threads = 753411;
unsigned int mem_size = num_threads*sizeof(float);
// Initialize vars for measuring time
unsigned long int par_elapsed;
unsigned long int seq_elapsed;
struct timeval p_start, p_end, p_diff;
struct timeval s_start, s_end, s_diff;
// alocate host memory
float* h_in = (float*) malloc(mem_size);
float* h_out = (float*) malloc(mem_size);
float* m_out = (float*) malloc(mem_size);
// iniitalize the memory
for(unsigned int i=1; i<=num_threads; ++i) {
h_in[i-1] = (float)(i);
}
// allocate device memory
float* d_in;
float* d_out;
hipMalloc((void**)&d_in, mem_size);
hipMalloc((void**)&d_out, mem_size);
// copy host memory to device
hipMemcpy(d_in, h_in, mem_size, hipMemcpyHostToDevice);
// Start timer
gettimeofday(&p_start, NULL);
// execute the kernel
parFunct<<< ceil(num_threads/1024.0), 1024>>>(d_in, d_out, num_threads);
hipDeviceSynchronize();
// calc elapsed time
gettimeofday(&p_end, NULL);
timeval_subtract(&p_diff, &p_end, &p_start);
par_elapsed = p_diff.tv_sec*1e6+p_diff.tv_usec;
hipMemcpy(h_out, d_out, mem_size, hipMemcpyDeviceToHost);
gettimeofday(&s_start, NULL);
// execute the kernel
seqFunct(m_out);
// Print elapsed time
gettimeofday(&s_end, NULL);
timeval_subtract(&s_diff, &s_end, &s_start);
seq_elapsed = s_diff.tv_sec*1e6+s_diff.tv_usec;
//printf("Took %d microseconds (%.2fms)\n", elapsed, elapsed/1000.0);
bool isValid = true;
for (int i = 0; i < num_threads; i++) {
if (abs(m_out[i] - h_out[i]) > 0.000001) {
isValid = false;
break;
}
}
if (isValid) {
printf("VALID\n");
}
else {
printf("INVALID\n");
}
printf("CPU Time: %d microseconds (%.fms)\n", seq_elapsed, seq_elapsed/1000.0);
printf("GPU Time: %d microseconds (%.fms)\n", par_elapsed, par_elapsed/1000.0);
// clean-up memory
free(h_in); free(h_out);
free(m_out);
hipFree(d_in); hipFree(d_out);
} | .text
.file "simpleCUDA.hip"
.globl _Z16timeval_subtractP7timevalS0_S0_ # -- Begin function _Z16timeval_subtractP7timevalS0_S0_
.p2align 4, 0x90
.type _Z16timeval_subtractP7timevalS0_S0_,@function
_Z16timeval_subtractP7timevalS0_S0_: # @_Z16timeval_subtractP7timevalS0_S0_
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
movq 8(%rsi), %rcx
subq (%rdx), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 8(%rdx), %rcx
addq %rax, %rcx
movabsq $4835703278458516699, %rdx # imm = 0x431BDE82D7B634DB
movq %rcx, %rax
imulq %rdx
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movq %rdx, (%rdi)
imulq $1000000, %rdx, %rax # imm = 0xF4240
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, 8(%rdi)
shrq $63, %rcx
movl %ecx, %eax
retq
.Lfunc_end0:
.size _Z16timeval_subtractP7timevalS0_S0_, .Lfunc_end0-_Z16timeval_subtractP7timevalS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8seqFunctPf
.LCPI1_0:
.quad 0xc002666666666666 # double -2.2999999999999998
.LCPI1_1:
.quad 0x4008000000000000 # double 3
.text
.globl _Z8seqFunctPf
.p2align 4, 0x90
.type _Z8seqFunctPf,@function
_Z8seqFunctPf: # @_Z8seqFunctPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r14), %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
movapd %xmm0, %xmm1
addsd .LCPI1_0(%rip), %xmm1
divsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r14,4)
movq %r15, %r14
cmpq $753411, %r15 # imm = 0xB7F03
jne .LBB1_1
# %bb.2:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8seqFunctPf, .Lfunc_end1-_Z8seqFunctPf
.cfi_endproc
# -- End function
.globl _Z23__device_stub__parFunctPfS_i # -- Begin function _Z23__device_stub__parFunctPfS_i
.p2align 4, 0x90
.type _Z23__device_stub__parFunctPfS_i,@function
_Z23__device_stub__parFunctPfS_i: # @_Z23__device_stub__parFunctPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8parFunctPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__parFunctPfS_i, .Lfunc_end2-_Z23__device_stub__parFunctPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0xc002666666666666 # double -2.2999999999999998
.LCPI3_1:
.quad 0x4008000000000000 # double 3
.LCPI3_3:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI3_4:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_5:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI3_8:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.LCPI3_6:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI3_7:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $3013644, %edi # imm = 0x2DFC0C
callq malloc
movq %rax, %rbx
movl $3013644, %edi # imm = 0x2DFC0C
callq malloc
movq %rax, %r14
movl $3013644, %edi # imm = 0x2DFC0C
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $753411, %rcx # imm = 0xB7F03
jne .LBB3_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $3013644, %esi # imm = 0x2DFC0C
callq hipMalloc
leaq 8(%rsp), %rdi
movl $3013644, %esi # imm = 0x2DFC0C
callq hipMalloc
movq 16(%rsp), %rdi
movl $3013644, %edx # imm = 0x2DFC0C
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $4294968032, %rdi # imm = 0x1000002E0
leaq 288(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl $753411, 28(%rsp) # imm = 0xB7F03
leaq 160(%rsp), %rax
movq %rax, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 72(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8parFunctPfS_i, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
xorl %ebp, %ebp
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rax
movq %rax, 120(%rsp) # 8-byte Spill
movq 72(%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 168(%rsp), %rax
movq %rax, 112(%rsp) # 8-byte Spill
movq 176(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movq 8(%rsp), %rsi
movl $3013644, %edx # imm = 0x2DFC0C
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
leaq 1(%rbp), %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
movapd %xmm0, %xmm1
addsd .LCPI3_0(%rip), %xmm1
divsd %xmm1, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbp,4)
movq %r12, %rbp
cmpq $753411, %r12 # imm = 0xB7F03
jne .LBB3_5
# %bb.6: # %_Z8seqFunctPf.exit
xorl %r13d, %r13d
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %r12
movq 40(%rsp), %rbp
movq 48(%rsp), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movaps .LCPI3_2(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_3(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r14,%r13,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB3_10
# %bb.8: # in Loop: Header=BB3_7 Depth=1
incq %r13
cmpq $753411, %r13 # imm = 0xB7F03
jne .LBB3_7
# %bb.9:
movl $.Lstr.1, %edi
jmp .LBB3_11
.LBB3_10:
movl $.Lstr, %edi
.LBB3_11: # %.critedge
callq puts@PLT
subq 88(%rsp), %rbp # 8-byte Folded Reload
subq 96(%rsp), %r12 # 8-byte Folded Reload
imulq $1000000, %r12, %rcx # imm = 0xF4240
addq %rbp, %rcx
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
movq %rcx, %rax
imulq %r8
movq %rdx, %rsi
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rsi
addq %rax, %rsi
imulq $1000000, %rsi, %rax # imm = 0xF4240
subq %rax, %rcx
movq 128(%rsp), %rax # 8-byte Reload
subq 104(%rsp), %rax # 8-byte Folded Reload
movq 120(%rsp), %rdx # 8-byte Reload
subq 112(%rsp), %rdx # 8-byte Folded Reload
imulq $1000000, %rdx, %rdi # imm = 0xF4240
addq %rax, %rdi
movq %rdi, %rax
imulq %r8
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
imulq $1000000, %rdx, %rax # imm = 0xF4240
subq %rax, %rdi
xorps %xmm0, %xmm0
cvtsi2sd %rsi, %xmm0
movsd .LCPI3_4(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
xorps %xmm2, %xmm2
cvtsi2sd %rcx, %xmm2
addsd %xmm0, %xmm2
cvttsd2si %xmm2, %rax
movq %rax, %rcx
movsd .LCPI3_5(%rip), %xmm0 # xmm0 = mem[0],zero
subsd %xmm0, %xmm2
cvttsd2si %xmm2, %rsi
sarq $63, %rcx
andq %rcx, %rsi
xorps %xmm2, %xmm2
cvtsi2sd %rdx, %xmm2
orq %rax, %rsi
mulsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sd %rdi, %xmm1
addsd %xmm2, %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd %xmm0, %xmm1
cvttsd2si %xmm1, %r12
andq %rcx, %r12
orq %rax, %r12
movq %rsi, %xmm1
punpckldq .LCPI3_6(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI3_7(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI3_8(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %r12, %xmm1
punpckldq .LCPI3_6(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI3_7(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI3_8(%rip), %xmm0
movl $.L.str.3, %edi
movq %r12, %rsi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8parFunctPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8parFunctPfS_i,@object # @_Z8parFunctPfS_i
.section .rodata,"a",@progbits
.globl _Z8parFunctPfS_i
.p2align 3, 0x0
_Z8parFunctPfS_i:
.quad _Z23__device_stub__parFunctPfS_i
.size _Z8parFunctPfS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CPU Time: %d microseconds (%.fms)\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Time: %d microseconds (%.fms)\n"
.size .L.str.3, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8parFunctPfS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "INVALID"
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "VALID"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__parFunctPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8parFunctPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f07c9_00000000-6_simpleCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16timeval_subtractP7timevalS0_S0_
.type _Z16timeval_subtractP7timevalS0_S0_, @function
_Z16timeval_subtractP7timevalS0_S0_:
.LFB2057:
.cfi_startproc
endbr64
imulq $1000000, (%rsi), %rcx
addq 8(%rsi), %rcx
imulq $1000000, (%rdx), %rax
addq 8(%rdx), %rax
subq %rax, %rcx
movabsq $4835703278458516699, %rdx
movq %rcx, %rax
imulq %rdx
sarq $18, %rdx
movq %rcx, %rax
sarq $63, %rax
subq %rax, %rdx
movq %rdx, (%rdi)
imulq $1000000, %rdx, %rdx
movq %rcx, %rax
subq %rdx, %rax
movq %rax, 8(%rdi)
shrq $63, %rcx
movq %rcx, %rax
ret
.cfi_endproc
.LFE2057:
.size _Z16timeval_subtractP7timevalS0_S0_, .-_Z16timeval_subtractP7timevalS0_S0_
.globl _Z8seqFunctPf
.type _Z8seqFunctPf, @function
_Z8seqFunctPf:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movl $1, %ebx
.L5:
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movapd %xmm0, %xmm1
subsd .LC1(%rip), %xmm1
divsd %xmm1, %xmm0
movsd .LC0(%rip), %xmm1
call pow@PLT
cvtsd2ss %xmm0, %xmm0
movss %xmm0, -4(%rbp,%rbx,4)
addq $1, %rbx
cmpq $753412, %rbx
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8seqFunctPf, .-_Z8seqFunctPf
.globl _Z30__device_stub__Z8parFunctPfS_iPfS_i
.type _Z30__device_stub__Z8parFunctPfS_iPfS_i, @function
_Z30__device_stub__Z8parFunctPfS_iPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8parFunctPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z8parFunctPfS_iPfS_i, .-_Z30__device_stub__Z8parFunctPfS_iPfS_i
.globl _Z8parFunctPfS_i
.type _Z8parFunctPfS_i, @function
_Z8parFunctPfS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z8parFunctPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z8parFunctPfS_i, .-_Z8parFunctPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC7:
.string "CPU Time: %d microseconds (%.fms)\n"
.align 8
.LC8:
.string "GPU Time: %d microseconds (%.fms)\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC9:
.string "VALID\n"
.LC10:
.string "INVALID\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl $3013644, %edi
call malloc@PLT
movq %rax, %rbx
movl $3013644, %edi
call malloc@PLT
movq %rax, %rbp
movl $3013644, %edi
call malloc@PLT
movq %rax, %r12
movl $1, %eax
.L19:
movl %eax, %edx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
movss %xmm0, -4(%rbx,%rax,4)
addq $1, %rax
cmpq $753412, %rax
jne .L19
movq %rsp, %rdi
movl $3013644, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $3013644, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $3013644, %edx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $736, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L39
.L20:
call cudaThreadSynchronize@PLT
leaq 32(%rsp), %r13
movl $0, %esi
movq %r13, %rdi
call gettimeofday@PLT
leaq 16(%rsp), %rdx
leaq 48(%rsp), %rdi
movq %r13, %rsi
call _Z16timeval_subtractP7timevalS0_S0_
pxor %xmm0, %xmm0
cvtsi2sdq 48(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 56(%rsp), %xmm1
addsd %xmm1, %xmm0
comisd .LC3(%rip), %xmm0
jnb .L21
cvttsd2siq %xmm0, %r13
.L22:
movl $2, %ecx
movl $3013644, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq 64(%rsp), %r15
movl $0, %esi
movq %r15, %rdi
call gettimeofday@PLT
movq %r12, %rdi
call _Z8seqFunctPf
leaq 80(%rsp), %r14
movl $0, %esi
movq %r14, %rdi
call gettimeofday@PLT
leaq 96(%rsp), %rdi
movq %r15, %rdx
movq %r14, %rsi
call _Z16timeval_subtractP7timevalS0_S0_
pxor %xmm0, %xmm0
cvtsi2sdq 96(%rsp), %xmm0
mulsd .LC2(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 104(%rsp), %xmm1
addsd %xmm1, %xmm0
comisd .LC3(%rip), %xmm0
jnb .L23
cvttsd2siq %xmm0, %r14
.L24:
movl $0, %eax
movss .LC4(%rip), %xmm2
movsd .LC5(%rip), %xmm1
.L26:
movss (%r12,%rax), %xmm0
subss 0(%rbp,%rax), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm1, %xmm0
ja .L25
addq $4, %rax
cmpq $3013644, %rax
jne .L26
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L32:
testq %r14, %r14
js .L28
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
.L29:
divsd .LC6(%rip), %xmm0
movq %r14, %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testq %r13, %r13
js .L30
pxor %xmm0, %xmm0
cvtsi2sdq %r13, %xmm0
.L31:
divsd .LC6(%rip), %xmm0
movq %r13, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L40
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
movl $753411, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z30__device_stub__Z8parFunctPfS_iPfS_i
jmp .L20
.L21:
subsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %r13
btcq $63, %r13
jmp .L22
.L23:
subsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %r14
btcq $63, %r14
jmp .L24
.L28:
movq %r14, %rax
shrq %rax
movq %r14, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L29
.L30:
movq %r13, %rax
shrq %rax
movq %r13, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
jmp .L31
.L25:
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L32
.L40:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z8parFunctPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8parFunctPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1074266112
.align 8
.LC1:
.long 1717986918
.long 1073899110
.align 8
.LC2:
.long 0
.long 1093567616
.align 8
.LC3:
.long 0
.long 1138753536
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC4:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC5:
.long -1598689907
.long 1051772663
.align 8
.LC6:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simpleCUDA.hip"
.globl _Z16timeval_subtractP7timevalS0_S0_ # -- Begin function _Z16timeval_subtractP7timevalS0_S0_
.p2align 4, 0x90
.type _Z16timeval_subtractP7timevalS0_S0_,@function
_Z16timeval_subtractP7timevalS0_S0_: # @_Z16timeval_subtractP7timevalS0_S0_
.cfi_startproc
# %bb.0:
movq (%rsi), %rax
movq 8(%rsi), %rcx
subq (%rdx), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 8(%rdx), %rcx
addq %rax, %rcx
movabsq $4835703278458516699, %rdx # imm = 0x431BDE82D7B634DB
movq %rcx, %rax
imulq %rdx
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
movq %rdx, (%rdi)
imulq $1000000, %rdx, %rax # imm = 0xF4240
movq %rcx, %rdx
subq %rax, %rdx
movq %rdx, 8(%rdi)
shrq $63, %rcx
movl %ecx, %eax
retq
.Lfunc_end0:
.size _Z16timeval_subtractP7timevalS0_S0_, .Lfunc_end0-_Z16timeval_subtractP7timevalS0_S0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z8seqFunctPf
.LCPI1_0:
.quad 0xc002666666666666 # double -2.2999999999999998
.LCPI1_1:
.quad 0x4008000000000000 # double 3
.text
.globl _Z8seqFunctPf
.p2align 4, 0x90
.type _Z8seqFunctPf,@function
_Z8seqFunctPf: # @_Z8seqFunctPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%r14), %r15
xorps %xmm0, %xmm0
cvtsi2sd %r15d, %xmm0
movapd %xmm0, %xmm1
addsd .LCPI1_0(%rip), %xmm1
divsd %xmm1, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r14,4)
movq %r15, %r14
cmpq $753411, %r15 # imm = 0xB7F03
jne .LBB1_1
# %bb.2:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z8seqFunctPf, .Lfunc_end1-_Z8seqFunctPf
.cfi_endproc
# -- End function
.globl _Z23__device_stub__parFunctPfS_i # -- Begin function _Z23__device_stub__parFunctPfS_i
.p2align 4, 0x90
.type _Z23__device_stub__parFunctPfS_i,@function
_Z23__device_stub__parFunctPfS_i: # @_Z23__device_stub__parFunctPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8parFunctPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z23__device_stub__parFunctPfS_i, .Lfunc_end2-_Z23__device_stub__parFunctPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI3_0:
.quad 0xc002666666666666 # double -2.2999999999999998
.LCPI3_1:
.quad 0x4008000000000000 # double 3
.LCPI3_3:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.LCPI3_4:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI3_5:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI3_8:
.quad 0x408f400000000000 # double 1000
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI3_2:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.LCPI3_6:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI3_7:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $3013644, %edi # imm = 0x2DFC0C
callq malloc
movq %rax, %rbx
movl $3013644, %edi # imm = 0x2DFC0C
callq malloc
movq %rax, %r14
movl $3013644, %edi # imm = 0x2DFC0C
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, %edx
xorps %xmm0, %xmm0
cvtsi2ss %rdx, %xmm0
movss %xmm0, (%rbx,%rax,4)
movq %rcx, %rax
cmpq $753411, %rcx # imm = 0xB7F03
jne .LBB3_1
# %bb.2:
leaq 16(%rsp), %rdi
movl $3013644, %esi # imm = 0x2DFC0C
callq hipMalloc
leaq 8(%rsp), %rdi
movl $3013644, %esi # imm = 0x2DFC0C
callq hipMalloc
movq 16(%rsp), %rdi
movl $3013644, %edx # imm = 0x2DFC0C
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 168(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movabsq $4294968032, %rdi # imm = 0x1000002E0
leaq 288(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 160(%rsp)
movq %rcx, 152(%rsp)
movl $753411, 28(%rsp) # imm = 0xB7F03
leaq 160(%rsp), %rax
movq %rax, 64(%rsp)
leaq 152(%rsp), %rax
movq %rax, 72(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z8parFunctPfS_i, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_4:
callq hipDeviceSynchronize
xorl %ebp, %ebp
leaq 64(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 64(%rsp), %rax
movq %rax, 120(%rsp) # 8-byte Spill
movq 72(%rsp), %rax
movq %rax, 128(%rsp) # 8-byte Spill
movq 168(%rsp), %rax
movq %rax, 112(%rsp) # 8-byte Spill
movq 176(%rsp), %rax
movq %rax, 104(%rsp) # 8-byte Spill
movq 8(%rsp), %rsi
movl $3013644, %edx # imm = 0x2DFC0C
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
.p2align 4, 0x90
.LBB3_5: # =>This Inner Loop Header: Depth=1
leaq 1(%rbp), %r12
xorps %xmm0, %xmm0
cvtsi2sd %r12d, %xmm0
movapd %xmm0, %xmm1
addsd .LCPI3_0(%rip), %xmm1
divsd %xmm1, %xmm0
movsd .LCPI3_1(%rip), %xmm1 # xmm1 = mem[0],zero
callq pow
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r15,%rbp,4)
movq %r12, %rbp
cmpq $753411, %r12 # imm = 0xB7F03
jne .LBB3_5
# %bb.6: # %_Z8seqFunctPf.exit
xorl %r13d, %r13d
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 32(%rsp), %r12
movq 40(%rsp), %rbp
movq 48(%rsp), %rax
movq %rax, 96(%rsp) # 8-byte Spill
movq 56(%rsp), %rax
movq %rax, 88(%rsp) # 8-byte Spill
movaps .LCPI3_2(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI3_3(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB3_7: # =>This Inner Loop Header: Depth=1
movss (%r15,%r13,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss (%r14,%r13,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm1, %xmm2
ja .LBB3_10
# %bb.8: # in Loop: Header=BB3_7 Depth=1
incq %r13
cmpq $753411, %r13 # imm = 0xB7F03
jne .LBB3_7
# %bb.9:
movl $.Lstr.1, %edi
jmp .LBB3_11
.LBB3_10:
movl $.Lstr, %edi
.LBB3_11: # %.critedge
callq puts@PLT
subq 88(%rsp), %rbp # 8-byte Folded Reload
subq 96(%rsp), %r12 # 8-byte Folded Reload
imulq $1000000, %r12, %rcx # imm = 0xF4240
addq %rbp, %rcx
movabsq $4835703278458516699, %r8 # imm = 0x431BDE82D7B634DB
movq %rcx, %rax
imulq %r8
movq %rdx, %rsi
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rsi
addq %rax, %rsi
imulq $1000000, %rsi, %rax # imm = 0xF4240
subq %rax, %rcx
movq 128(%rsp), %rax # 8-byte Reload
subq 104(%rsp), %rax # 8-byte Folded Reload
movq 120(%rsp), %rdx # 8-byte Reload
subq 112(%rsp), %rdx # 8-byte Folded Reload
imulq $1000000, %rdx, %rdi # imm = 0xF4240
addq %rax, %rdi
movq %rdi, %rax
imulq %r8
movq %rdx, %rax
shrq $63, %rax
sarq $18, %rdx
addq %rax, %rdx
imulq $1000000, %rdx, %rax # imm = 0xF4240
subq %rax, %rdi
xorps %xmm0, %xmm0
cvtsi2sd %rsi, %xmm0
movsd .LCPI3_4(%rip), %xmm1 # xmm1 = mem[0],zero
mulsd %xmm1, %xmm0
xorps %xmm2, %xmm2
cvtsi2sd %rcx, %xmm2
addsd %xmm0, %xmm2
cvttsd2si %xmm2, %rax
movq %rax, %rcx
movsd .LCPI3_5(%rip), %xmm0 # xmm0 = mem[0],zero
subsd %xmm0, %xmm2
cvttsd2si %xmm2, %rsi
sarq $63, %rcx
andq %rcx, %rsi
xorps %xmm2, %xmm2
cvtsi2sd %rdx, %xmm2
orq %rax, %rsi
mulsd %xmm1, %xmm2
xorps %xmm1, %xmm1
cvtsi2sd %rdi, %xmm1
addsd %xmm2, %xmm1
cvttsd2si %xmm1, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd %xmm0, %xmm1
cvttsd2si %xmm1, %r12
andq %rcx, %r12
orq %rax, %r12
movq %rsi, %xmm1
punpckldq .LCPI3_6(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI3_7(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI3_8(%rip), %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movq %r12, %xmm1
punpckldq .LCPI3_6(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI3_7(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
divsd .LCPI3_8(%rip), %xmm0
movl $.L.str.3, %edi
movq %r12, %rsi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8parFunctPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8parFunctPfS_i,@object # @_Z8parFunctPfS_i
.section .rodata,"a",@progbits
.globl _Z8parFunctPfS_i
.p2align 3, 0x0
_Z8parFunctPfS_i:
.quad _Z23__device_stub__parFunctPfS_i
.size _Z8parFunctPfS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "CPU Time: %d microseconds (%.fms)\n"
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU Time: %d microseconds (%.fms)\n"
.size .L.str.3, 35
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8parFunctPfS_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "INVALID"
.size .Lstr, 8
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "VALID"
.size .Lstr.1, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__parFunctPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8parFunctPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Mezclar threads y bloques
#include <stdio.h>
#define N (2048 * 2048)
#define THREADS_PER_BLOCK 512
__global__ void add(int*a, int*b, int*c, int n) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(){
int *a, *b, *c; // Copias de a b y c en el host
int *d_a, *d_b, *d_c; // Copias de a b y c en el device
int size = N * sizeof(int);
// Obtenemos espacio para las copias de a,b y c en device
cudaMalloc((void**) &d_a, size);
cudaMalloc((void**) &d_b, size);
cudaMalloc((void**) &d_c, size);
// Obtenemos espacio para las copias de a, b y c dentro del host
a = (int *)malloc(size);
b = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i;
}
c = (int *)malloc(size);
// Copiamos los imput en device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Lanzamos el kernel add dentro de la GPU
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c,N);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d, ",c[i]);
// Liberamos memoria
free(a);free(b);free(c);
cudaFree(d_a);cudaFree(d_b);cudaFree(d_c);
} | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Mezclar threads y bloques
#include <stdio.h>
#define N (2048 * 2048)
#define THREADS_PER_BLOCK 512
__global__ void add(int*a, int*b, int*c, int n) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(){
int *a, *b, *c; // Copias de a b y c en el host
int *d_a, *d_b, *d_c; // Copias de a b y c en el device
int size = N * sizeof(int);
// Obtenemos espacio para las copias de a,b y c en device
cudaMalloc((void**) &d_a, size);
cudaMalloc((void**) &d_b, size);
cudaMalloc((void**) &d_c, size);
// Obtenemos espacio para las copias de a, b y c dentro del host
a = (int *)malloc(size);
b = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i;
}
c = (int *)malloc(size);
// Copiamos los imput en device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Lanzamos el kernel add dentro de la GPU
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c,N);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d, ",c[i]);
// Liberamos memoria
free(a);free(b);free(c);
cudaFree(d_a);cudaFree(d_b);cudaFree(d_c);
} | .file "tmpxft_0010a1db_00000000-6_indexing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L12
movl $16777216, %edi
call malloc@PLT
movq %rax, %r15
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq %r15, %rbx
leaq 16777216(%r15), %r14
leaq .LC0(%rip), %r13
.L14:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $4194304, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Mezclar threads y bloques
#include <stdio.h>
#define N (2048 * 2048)
#define THREADS_PER_BLOCK 512
__global__ void add(int*a, int*b, int*c, int n) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(){
int *a, *b, *c; // Copias de a b y c en el host
int *d_a, *d_b, *d_c; // Copias de a b y c en el device
int size = N * sizeof(int);
// Obtenemos espacio para las copias de a,b y c en device
cudaMalloc((void**) &d_a, size);
cudaMalloc((void**) &d_b, size);
cudaMalloc((void**) &d_c, size);
// Obtenemos espacio para las copias de a, b y c dentro del host
a = (int *)malloc(size);
b = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i;
}
c = (int *)malloc(size);
// Copiamos los imput en device
cudaMemcpy(d_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, b, size, cudaMemcpyHostToDevice);
// Lanzamos el kernel add dentro de la GPU
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c,N);
cudaMemcpy(c, d_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d, ",c[i]);
// Liberamos memoria
free(a);free(b);free(c);
cudaFree(d_a);cudaFree(d_b);cudaFree(d_c);
} | // Mezclar threads y bloques
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N (2048 * 2048)
#define THREADS_PER_BLOCK 512
__global__ void add(int*a, int*b, int*c, int n) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(){
int *a, *b, *c; // Copias de a b y c en el host
int *d_a, *d_b, *d_c; // Copias de a b y c en el device
int size = N * sizeof(int);
// Obtenemos espacio para las copias de a,b y c en device
hipMalloc((void**) &d_a, size);
hipMalloc((void**) &d_b, size);
hipMalloc((void**) &d_c, size);
// Obtenemos espacio para las copias de a, b y c dentro del host
a = (int *)malloc(size);
b = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i;
}
c = (int *)malloc(size);
// Copiamos los imput en device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Lanzamos el kernel add dentro de la GPU
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c,N);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d, ",c[i]);
// Liberamos memoria
free(a);free(b);free(c);
hipFree(d_a);hipFree(d_b);hipFree(d_c);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Mezclar threads y bloques
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N (2048 * 2048)
#define THREADS_PER_BLOCK 512
__global__ void add(int*a, int*b, int*c, int n) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(){
int *a, *b, *c; // Copias de a b y c en el host
int *d_a, *d_b, *d_c; // Copias de a b y c en el device
int size = N * sizeof(int);
// Obtenemos espacio para las copias de a,b y c en device
hipMalloc((void**) &d_a, size);
hipMalloc((void**) &d_b, size);
hipMalloc((void**) &d_c, size);
// Obtenemos espacio para las copias de a, b y c dentro del host
a = (int *)malloc(size);
b = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i;
}
c = (int *)malloc(size);
// Copiamos los imput en device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Lanzamos el kernel add dentro de la GPU
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c,N);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d, ",c[i]);
// Liberamos memoria
free(a);free(b);free(c);
hipFree(d_a);hipFree(d_b);hipFree(d_c);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Mezclar threads y bloques
#include <hip/hip_runtime.h>
#include <stdio.h>
#define N (2048 * 2048)
#define THREADS_PER_BLOCK 512
__global__ void add(int*a, int*b, int*c, int n) {
int index = threadIdx.x + blockIdx.x * blockDim.x;
if(index < n)
c[index] = a[index] + b[index];
}
int main(){
int *a, *b, *c; // Copias de a b y c en el host
int *d_a, *d_b, *d_c; // Copias de a b y c en el device
int size = N * sizeof(int);
// Obtenemos espacio para las copias de a,b y c en device
hipMalloc((void**) &d_a, size);
hipMalloc((void**) &d_b, size);
hipMalloc((void**) &d_c, size);
// Obtenemos espacio para las copias de a, b y c dentro del host
a = (int *)malloc(size);
b = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = i;
b[i] = i;
}
c = (int *)malloc(size);
// Copiamos los imput en device
hipMemcpy(d_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(d_b, b, size, hipMemcpyHostToDevice);
// Lanzamos el kernel add dentro de la GPU
add<<<(N+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_a, d_b, d_c,N);
hipMemcpy(c, d_c, size, hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++)
printf("%d, ",c[i]);
// Liberamos memoria
free(a);free(b);free(c);
hipFree(d_a);hipFree(d_b);hipFree(d_c);
} | .text
.file "indexing.hip"
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB1_1
# %bb.2:
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4194304, 36(%rsp) # imm = 0x400000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_i
.globl _Z3addPiS_S_i
.p2align 8
.type _Z3addPiS_S_i,@function
_Z3addPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_i, .Lfunc_end0-_Z3addPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010a1db_00000000-6_indexing.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3addPiS_S_iPiS_S_i
.type _Z27__device_stub__Z3addPiS_S_iPiS_S_i, @function
_Z27__device_stub__Z3addPiS_S_iPiS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z3addPiS_S_iPiS_S_i, .-_Z27__device_stub__Z3addPiS_S_iPiS_S_i
.globl _Z3addPiS_S_i
.type _Z3addPiS_S_i, @function
_Z3addPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_i, .-_Z3addPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d, "
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $16777216, %esi
call cudaMalloc@PLT
movl $16777216, %edi
call malloc@PLT
movq %rax, %r12
movl $16777216, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $4194304, %rax
jne .L12
movl $16777216, %edi
call malloc@PLT
movq %rax, %r15
movl $1, %ecx
movl $16777216, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16777216, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $512, 44(%rsp)
movl $1, 48(%rsp)
movl $8192, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $16777216, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movq %r15, %rbx
leaq 16777216(%r15), %r14
leaq .LC0(%rip), %r13
.L14:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r14, %rbx
jne .L14
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $4194304, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z3addPiS_S_iPiS_S_i
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "indexing.hip"
.globl _Z18__device_stub__addPiS_S_i # -- Begin function _Z18__device_stub__addPiS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_i,@function
_Z18__device_stub__addPiS_S_i: # @_Z18__device_stub__addPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_i, .Lfunc_end0-_Z18__device_stub__addPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 24(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16777216, %esi # imm = 0x1000000
callq hipMalloc
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %rbx
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $4194304, %rax # imm = 0x400000
jne .LBB1_1
# %bb.2:
movl $16777216, %edi # imm = 0x1000000
callq malloc
movq %rax, %r15
movq 24(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $16777216, %edx # imm = 0x1000000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 7680(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $4194304, 36(%rsp) # imm = 0x400000
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
movl $16777216, %edx # imm = 0x1000000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $4194304, %r12 # imm = 0x400000
jne .LBB1_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_i,@object # @_Z3addPiS_S_i
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_i
.p2align 3, 0x0
_Z3addPiS_S_i:
.quad _Z18__device_stub__addPiS_S_i
.size _Z3addPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d, "
.size .L.str, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//Bibliotecas Basicas
//Biblioteca Thrust
//Biblioteca cuRAND
//PARAMETROS GLOBAIS
const int QUANT_PAIS_AVALIA = 4;
int POP_TAM = 200;
int N_CIDADES = 20;
int BLOCKSIZE = 1024;
int TOTALTHREADS = 2048;
int N_GERA = 100;
const int MUT = 10;
const int MAX = 19;
const int MIN = 0;
const int ELITE = 2;
/*
* Busca por erros nos processos da gpu
*/
__global__ void cruza(unsigned int n, unsigned int np, int *cidadesAle, int *pop, int *newPop, int *poolPais, int *mutacoes) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int paiA, paiB, copiaPai, crossover, mutar, pontoMutar;
for (int i=index; i<n; i+=stride) {
copiaPai = cidadesAle[i*4];
crossover = cidadesAle[(i+1)*4] % np;
mutar = cidadesAle[(i+2)*4];
pontoMutar = cidadesAle[(i+3)*4] % np;
paiA = poolPais[i];
paiB = poolPais[i+1];
if (copiaPai < ELITE) {
for (int j=0; j<np; j++) {
newPop[(i*np) + j] = pop[(paiA*np) + j];
continue;
}
}
for(int j=0;j<np;j++)
{
newPop[(i*np) + j] = pop[(paiA*np) + j];
}
int t=0, aux=0, crossoverSup;
crossoverSup=(crossover +mutacoes[i]>MAX)?(MAX):(crossover +mutacoes[i]);
for(int j=crossover; j<crossoverSup;j++)
{
t=0;
while(newPop[(i*np) +t]!=pop[(paiB*np) + j])
{
t++;
}
aux = newPop[i*np+j];
newPop[i*np+j] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
if (mutar < MUT) {
int mut = (mutacoes[i]>MAX)?(MAX):((mutacoes[i]<MIN)?(MIN):(mutacoes[i]));
t=0;
while(newPop[(i*np) +t]!=mut)
{
t++;
}
aux = newPop[i*np+pontoMutar];
newPop[i*np+pontoMutar] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
}
} | .file "tmpxft_0009871f_00000000-6_cruza.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_
.type _Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_, @function
_Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5cruzajjPiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_, .-_Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_
.globl _Z5cruzajjPiS_S_S_S_
.type _Z5cruzajjPiS_S_S_S_, @function
_Z5cruzajjPiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5cruzajjPiS_S_S_S_, .-_Z5cruzajjPiS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5cruzajjPiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5cruzajjPiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl N_GERA
.data
.align 4
.type N_GERA, @object
.size N_GERA, 4
N_GERA:
.long 100
.globl TOTALTHREADS
.align 4
.type TOTALTHREADS, @object
.size TOTALTHREADS, 4
TOTALTHREADS:
.long 2048
.globl BLOCKSIZE
.align 4
.type BLOCKSIZE, @object
.size BLOCKSIZE, 4
BLOCKSIZE:
.long 1024
.globl N_CIDADES
.align 4
.type N_CIDADES, @object
.size N_CIDADES, 4
N_CIDADES:
.long 20
.globl POP_TAM
.align 4
.type POP_TAM, @object
.size POP_TAM, 4
POP_TAM:
.long 200
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//Bibliotecas Basicas
//Biblioteca Thrust
//Biblioteca cuRAND
//PARAMETROS GLOBAIS
const int QUANT_PAIS_AVALIA = 4;
int POP_TAM = 200;
int N_CIDADES = 20;
int BLOCKSIZE = 1024;
int TOTALTHREADS = 2048;
int N_GERA = 100;
const int MUT = 10;
const int MAX = 19;
const int MIN = 0;
const int ELITE = 2;
/*
* Busca por erros nos processos da gpu
*/
__global__ void cruza(unsigned int n, unsigned int np, int *cidadesAle, int *pop, int *newPop, int *poolPais, int *mutacoes) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int paiA, paiB, copiaPai, crossover, mutar, pontoMutar;
for (int i=index; i<n; i+=stride) {
copiaPai = cidadesAle[i*4];
crossover = cidadesAle[(i+1)*4] % np;
mutar = cidadesAle[(i+2)*4];
pontoMutar = cidadesAle[(i+3)*4] % np;
paiA = poolPais[i];
paiB = poolPais[i+1];
if (copiaPai < ELITE) {
for (int j=0; j<np; j++) {
newPop[(i*np) + j] = pop[(paiA*np) + j];
continue;
}
}
for(int j=0;j<np;j++)
{
newPop[(i*np) + j] = pop[(paiA*np) + j];
}
int t=0, aux=0, crossoverSup;
crossoverSup=(crossover +mutacoes[i]>MAX)?(MAX):(crossover +mutacoes[i]);
for(int j=crossover; j<crossoverSup;j++)
{
t=0;
while(newPop[(i*np) +t]!=pop[(paiB*np) + j])
{
t++;
}
aux = newPop[i*np+j];
newPop[i*np+j] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
if (mutar < MUT) {
int mut = (mutacoes[i]>MAX)?(MAX):((mutacoes[i]<MIN)?(MIN):(mutacoes[i]));
t=0;
while(newPop[(i*np) +t]!=mut)
{
t++;
}
aux = newPop[i*np+pontoMutar];
newPop[i*np+pontoMutar] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
//Bibliotecas Basicas
//Biblioteca Thrust
//Biblioteca cuRAND
//PARAMETROS GLOBAIS
const int QUANT_PAIS_AVALIA = 4;
int POP_TAM = 200;
int N_CIDADES = 20;
int BLOCKSIZE = 1024;
int TOTALTHREADS = 2048;
int N_GERA = 100;
const int MUT = 10;
const int MAX = 19;
const int MIN = 0;
const int ELITE = 2;
/*
* Busca por erros nos processos da gpu
*/
__global__ void cruza(unsigned int n, unsigned int np, int *cidadesAle, int *pop, int *newPop, int *poolPais, int *mutacoes) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int paiA, paiB, copiaPai, crossover, mutar, pontoMutar;
for (int i=index; i<n; i+=stride) {
copiaPai = cidadesAle[i*4];
crossover = cidadesAle[(i+1)*4] % np;
mutar = cidadesAle[(i+2)*4];
pontoMutar = cidadesAle[(i+3)*4] % np;
paiA = poolPais[i];
paiB = poolPais[i+1];
if (copiaPai < ELITE) {
for (int j=0; j<np; j++) {
newPop[(i*np) + j] = pop[(paiA*np) + j];
continue;
}
}
for(int j=0;j<np;j++)
{
newPop[(i*np) + j] = pop[(paiA*np) + j];
}
int t=0, aux=0, crossoverSup;
crossoverSup=(crossover +mutacoes[i]>MAX)?(MAX):(crossover +mutacoes[i]);
for(int j=crossover; j<crossoverSup;j++)
{
t=0;
while(newPop[(i*np) +t]!=pop[(paiB*np) + j])
{
t++;
}
aux = newPop[i*np+j];
newPop[i*np+j] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
if (mutar < MUT) {
int mut = (mutacoes[i]>MAX)?(MAX):((mutacoes[i]<MIN)?(MIN):(mutacoes[i]));
t=0;
while(newPop[(i*np) +t]!=mut)
{
t++;
}
aux = newPop[i*np+pontoMutar];
newPop[i*np+pontoMutar] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//Bibliotecas Basicas
//Biblioteca Thrust
//Biblioteca cuRAND
//PARAMETROS GLOBAIS
const int QUANT_PAIS_AVALIA = 4;
int POP_TAM = 200;
int N_CIDADES = 20;
int BLOCKSIZE = 1024;
int TOTALTHREADS = 2048;
int N_GERA = 100;
const int MUT = 10;
const int MAX = 19;
const int MIN = 0;
const int ELITE = 2;
/*
* Busca por erros nos processos da gpu
*/
__global__ void cruza(unsigned int n, unsigned int np, int *cidadesAle, int *pop, int *newPop, int *poolPais, int *mutacoes) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int paiA, paiB, copiaPai, crossover, mutar, pontoMutar;
for (int i=index; i<n; i+=stride) {
copiaPai = cidadesAle[i*4];
crossover = cidadesAle[(i+1)*4] % np;
mutar = cidadesAle[(i+2)*4];
pontoMutar = cidadesAle[(i+3)*4] % np;
paiA = poolPais[i];
paiB = poolPais[i+1];
if (copiaPai < ELITE) {
for (int j=0; j<np; j++) {
newPop[(i*np) + j] = pop[(paiA*np) + j];
continue;
}
}
for(int j=0;j<np;j++)
{
newPop[(i*np) + j] = pop[(paiA*np) + j];
}
int t=0, aux=0, crossoverSup;
crossoverSup=(crossover +mutacoes[i]>MAX)?(MAX):(crossover +mutacoes[i]);
for(int j=crossover; j<crossoverSup;j++)
{
t=0;
while(newPop[(i*np) +t]!=pop[(paiB*np) + j])
{
t++;
}
aux = newPop[i*np+j];
newPop[i*np+j] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
if (mutar < MUT) {
int mut = (mutacoes[i]>MAX)?(MAX):((mutacoes[i]<MIN)?(MIN):(mutacoes[i]));
t=0;
while(newPop[(i*np) +t]!=mut)
{
t++;
}
aux = newPop[i*np+pontoMutar];
newPop[i*np+pontoMutar] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5cruzajjPiS_S_S_S_
.globl _Z5cruzajjPiS_S_S_S_
.p2align 8
.type _Z5cruzajjPiS_S_S_S_,@function
_Z5cruzajjPiS_S_S_S_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b32 s12, s[0:1], 0x0
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s14, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s14, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s12, v1
s_cbranch_execz .LBB0_17
s_load_b32 s13, s[0:1], 0x4
s_load_b32 s2, s[2:3], 0x0
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x28
s_mov_b32 s15, 0
s_waitcnt lgkmcnt(0)
v_cvt_f32_u32_e32 v0, s13
s_sub_i32 s3, 0, s13
s_mul_i32 s2, s2, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_mul_i32 s14, s2, s13
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v2, v0
v_mul_lo_u32 v0, s3, v2
s_max_u32 s3, s13, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v2, v0
v_mul_lo_u32 v0, s13, v1
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v10, v2, v3
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v1, s2, v1
v_add_nc_u32_e32 v0, s14, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s12, v1
s_or_b32 s15, vcc_lo, s15
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_17
.LBB0_3:
v_add_nc_u32_e32 v4, 1, v1
v_lshlrev_b32_e32 v5, 2, v1
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s16, exec_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v8, 2, v4
v_ashrrev_i32_e32 v6, 31, v5
v_add_nc_u32_e32 v11, 8, v5
v_add_nc_u32_e32 v13, 12, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[15:16], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v11
v_lshlrev_b64 v[6:7], 2, v[1:2]
v_ashrrev_i32_e32 v14, 31, v13
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[11:12], 2, v[11:12]
v_add_co_u32 v15, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_add_co_u32 v11, vcc_lo, s4, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_lshlrev_b64 v[13:14], 2, v[13:14]
v_add_co_u32 v17, vcc_lo, s10, v6
v_add_co_ci_u32_e32 v18, vcc_lo, s11, v7, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v19, vcc_lo, s4, v13
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v14, vcc_lo
global_load_b32 v14, v[17:18], off
v_add_co_u32 v4, vcc_lo, s10, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s11, v5, vcc_lo
s_clause 0x3
global_load_b32 v15, v[15:16], off
global_load_b32 v13, v[8:9], off
global_load_b32 v12, v[11:12], off
global_load_b32 v11, v[19:20], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(5)
v_mul_lo_u32 v14, v14, s13
s_waitcnt vmcnt(4)
v_cmpx_gt_i32_e32 2, v15
s_cbranch_execz .LBB0_6
s_delay_alu instid0(VALU_DEP_2)
v_mov_b32_e32 v4, v14
v_mov_b32_e32 v8, v0
s_mov_b32 s17, s3
.p2align 6
.LBB0_5:
v_mov_b32_e32 v5, 0
s_add_i32 s17, s17, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s17, 0
v_lshlrev_b64 v[15:16], 2, v[4:5]
v_dual_mov_b32 v9, v5 :: v_dual_add_nc_u32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v15, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
global_load_b32 v17, v[15:16], off
v_lshlrev_b64 v[15:16], 2, v[8:9]
v_add_nc_u32_e32 v8, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v15, vcc_lo, s8, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[15:16], v17, off
s_cbranch_scc1 .LBB0_5
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s16
s_waitcnt vmcnt(3)
v_mad_u64_u32 v[8:9], null, v13, v10, 0
s_waitcnt vmcnt(1)
v_mad_u64_u32 v[4:5], null, v11, v10, 0
s_mov_b32 s16, 0
.p2align 6
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, 0 :: v_dual_add_nc_u32 v15, s16, v14
v_lshlrev_b64 v[17:18], 2, v[15:16]
v_add_nc_u32_e32 v15, s16, v0
s_add_i32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s3, s16
v_add_co_u32 v17, vcc_lo, s6, v17
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
v_lshlrev_b64 v[15:16], 2, v[15:16]
global_load_b32 v4, v[17:18], off
v_add_co_u32 v15, vcc_lo, s8, v15
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[15:16], v4, off
s_cbranch_scc0 .LBB0_7
v_add_co_u32 v6, vcc_lo, s0, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
v_mul_lo_u32 v4, v9, s13
s_mov_b32 s16, exec_lo
global_load_b32 v8, v[6:7], off
v_sub_nc_u32_e32 v4, v13, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s13, v4
v_cmp_le_u32_e32 vcc_lo, s13, v4
v_cndmask_b32_e32 v4, v4, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v9, s13, v4
v_cmp_le_u32_e32 vcc_lo, s13, v4
v_cndmask_b32_e32 v4, v4, v9, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v8, v8, v4
v_min_i32_e32 v13, 19, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v4, v13
s_cbranch_execz .LBB0_13
v_mul_lo_u32 v14, v1, s13
v_mul_lo_u32 v15, v2, s13
s_mov_b32 s17, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, v4, v15
s_mov_b32 s18, 0
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_mov_b32_e32 v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
global_load_b32 v17, v[8:9], off
.LBB0_11:
v_lshlrev_b64 v[8:9], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s8, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b32 v16, v[8:9], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v16, v17
s_or_b32 s18, vcc_lo, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execnz .LBB0_11
s_or_b32 exec_lo, exec_lo, s18
v_add_nc_u32_e32 v2, v4, v14
v_add_nc_u32_e32 v4, 1, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[17:18], 2, v[2:3]
v_add_co_u32 v17, vcc_lo, s8, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v18, vcc_lo, s9, v18, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, v4, v13
global_load_b32 v2, v[17:18], off
global_store_b32 v[17:18], v16, off
s_waitcnt vmcnt(0)
global_store_b32 v[8:9], v2, off
s_or_b32 s17, vcc_lo, s17
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_10
.LBB0_13:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_mov_b32 s16, exec_lo
v_cmpx_gt_i32_e32 10, v12
s_cbranch_execz .LBB0_2
global_load_b32 v2, v[6:7], off
s_mov_b32 s17, 0
s_waitcnt vmcnt(0)
v_med3_i32 v8, v2, 0, 19
v_mov_b32_e32 v2, v0
.LBB0_15:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_add_nc_u32_e32 v2, 1, v2
v_add_co_u32 v6, vcc_lo, s8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
global_load_b32 v4, v[6:7], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v8
s_or_b32 s17, vcc_lo, s17
s_and_not1_b32 exec_lo, exec_lo, s17
s_cbranch_execnz .LBB0_15
s_or_b32 exec_lo, exec_lo, s17
v_mul_lo_u32 v2, v5, s13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v11, v2
v_subrev_nc_u32_e32 v5, s13, v2
v_cmp_le_u32_e32 vcc_lo, s13, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_subrev_nc_u32_e32 v5, s13, v2
v_cmp_le_u32_e32 vcc_lo, s13, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_mad_u64_u32 v[8:9], null, v1, s13, v[2:3]
v_mov_b32_e32 v9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
v_add_co_u32 v8, vcc_lo, s8, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
global_load_b32 v2, v[8:9], off
global_store_b32 v[8:9], v4, off
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v2, off
s_branch .LBB0_2
.LBB0_17:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5cruzajjPiS_S_S_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 19
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5cruzajjPiS_S_S_S_, .Lfunc_end0-_Z5cruzajjPiS_S_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5cruzajjPiS_S_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 21
.sgpr_spill_count: 0
.symbol: _Z5cruzajjPiS_S_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//Bibliotecas Basicas
//Biblioteca Thrust
//Biblioteca cuRAND
//PARAMETROS GLOBAIS
const int QUANT_PAIS_AVALIA = 4;
int POP_TAM = 200;
int N_CIDADES = 20;
int BLOCKSIZE = 1024;
int TOTALTHREADS = 2048;
int N_GERA = 100;
const int MUT = 10;
const int MAX = 19;
const int MIN = 0;
const int ELITE = 2;
/*
* Busca por erros nos processos da gpu
*/
__global__ void cruza(unsigned int n, unsigned int np, int *cidadesAle, int *pop, int *newPop, int *poolPais, int *mutacoes) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
int paiA, paiB, copiaPai, crossover, mutar, pontoMutar;
for (int i=index; i<n; i+=stride) {
copiaPai = cidadesAle[i*4];
crossover = cidadesAle[(i+1)*4] % np;
mutar = cidadesAle[(i+2)*4];
pontoMutar = cidadesAle[(i+3)*4] % np;
paiA = poolPais[i];
paiB = poolPais[i+1];
if (copiaPai < ELITE) {
for (int j=0; j<np; j++) {
newPop[(i*np) + j] = pop[(paiA*np) + j];
continue;
}
}
for(int j=0;j<np;j++)
{
newPop[(i*np) + j] = pop[(paiA*np) + j];
}
int t=0, aux=0, crossoverSup;
crossoverSup=(crossover +mutacoes[i]>MAX)?(MAX):(crossover +mutacoes[i]);
for(int j=crossover; j<crossoverSup;j++)
{
t=0;
while(newPop[(i*np) +t]!=pop[(paiB*np) + j])
{
t++;
}
aux = newPop[i*np+j];
newPop[i*np+j] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
if (mutar < MUT) {
int mut = (mutacoes[i]>MAX)?(MAX):((mutacoes[i]<MIN)?(MIN):(mutacoes[i]));
t=0;
while(newPop[(i*np) +t]!=mut)
{
t++;
}
aux = newPop[i*np+pontoMutar];
newPop[i*np+pontoMutar] = newPop[i*np+t];
newPop[i*np+t] = aux;
}
}
} | .text
.file "cruza.hip"
.globl _Z20__device_stub__cruzajjPiS_S_S_S_ # -- Begin function _Z20__device_stub__cruzajjPiS_S_S_S_
.p2align 4, 0x90
.type _Z20__device_stub__cruzajjPiS_S_S_S_,@function
_Z20__device_stub__cruzajjPiS_S_S_S_: # @_Z20__device_stub__cruzajjPiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5cruzajjPiS_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z20__device_stub__cruzajjPiS_S_S_S_, .Lfunc_end0-_Z20__device_stub__cruzajjPiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5cruzajjPiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type POP_TAM,@object # @POP_TAM
.data
.globl POP_TAM
.p2align 2, 0x0
POP_TAM:
.long 200 # 0xc8
.size POP_TAM, 4
.type N_CIDADES,@object # @N_CIDADES
.globl N_CIDADES
.p2align 2, 0x0
N_CIDADES:
.long 20 # 0x14
.size N_CIDADES, 4
.type BLOCKSIZE,@object # @BLOCKSIZE
.globl BLOCKSIZE
.p2align 2, 0x0
BLOCKSIZE:
.long 1024 # 0x400
.size BLOCKSIZE, 4
.type TOTALTHREADS,@object # @TOTALTHREADS
.globl TOTALTHREADS
.p2align 2, 0x0
TOTALTHREADS:
.long 2048 # 0x800
.size TOTALTHREADS, 4
.type N_GERA,@object # @N_GERA
.globl N_GERA
.p2align 2, 0x0
N_GERA:
.long 100 # 0x64
.size N_GERA, 4
.type _Z5cruzajjPiS_S_S_S_,@object # @_Z5cruzajjPiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z5cruzajjPiS_S_S_S_
.p2align 3, 0x0
_Z5cruzajjPiS_S_S_S_:
.quad _Z20__device_stub__cruzajjPiS_S_S_S_
.size _Z5cruzajjPiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5cruzajjPiS_S_S_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__cruzajjPiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5cruzajjPiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009871f_00000000-6_cruza.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_
.type _Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_, @function
_Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movq %rdx, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5cruzajjPiS_S_S_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_, .-_Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_
.globl _Z5cruzajjPiS_S_S_S_
.type _Z5cruzajjPiS_S_S_S_, @function
_Z5cruzajjPiS_S_S_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z34__device_stub__Z5cruzajjPiS_S_S_S_jjPiS_S_S_S_
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5cruzajjPiS_S_S_S_, .-_Z5cruzajjPiS_S_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5cruzajjPiS_S_S_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5cruzajjPiS_S_S_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl N_GERA
.data
.align 4
.type N_GERA, @object
.size N_GERA, 4
N_GERA:
.long 100
.globl TOTALTHREADS
.align 4
.type TOTALTHREADS, @object
.size TOTALTHREADS, 4
TOTALTHREADS:
.long 2048
.globl BLOCKSIZE
.align 4
.type BLOCKSIZE, @object
.size BLOCKSIZE, 4
BLOCKSIZE:
.long 1024
.globl N_CIDADES
.align 4
.type N_CIDADES, @object
.size N_CIDADES, 4
N_CIDADES:
.long 20
.globl POP_TAM
.align 4
.type POP_TAM, @object
.size POP_TAM, 4
POP_TAM:
.long 200
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cruza.hip"
.globl _Z20__device_stub__cruzajjPiS_S_S_S_ # -- Begin function _Z20__device_stub__cruzajjPiS_S_S_S_
.p2align 4, 0x90
.type _Z20__device_stub__cruzajjPiS_S_S_S_,@function
_Z20__device_stub__cruzajjPiS_S_S_S_: # @_Z20__device_stub__cruzajjPiS_S_S_S_
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 88(%rsp), %rax
movq %rax, 112(%rsp)
leaq 80(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5cruzajjPiS_S_S_S_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z20__device_stub__cruzajjPiS_S_S_S_, .Lfunc_end0-_Z20__device_stub__cruzajjPiS_S_S_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5cruzajjPiS_S_S_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type POP_TAM,@object # @POP_TAM
.data
.globl POP_TAM
.p2align 2, 0x0
POP_TAM:
.long 200 # 0xc8
.size POP_TAM, 4
.type N_CIDADES,@object # @N_CIDADES
.globl N_CIDADES
.p2align 2, 0x0
N_CIDADES:
.long 20 # 0x14
.size N_CIDADES, 4
.type BLOCKSIZE,@object # @BLOCKSIZE
.globl BLOCKSIZE
.p2align 2, 0x0
BLOCKSIZE:
.long 1024 # 0x400
.size BLOCKSIZE, 4
.type TOTALTHREADS,@object # @TOTALTHREADS
.globl TOTALTHREADS
.p2align 2, 0x0
TOTALTHREADS:
.long 2048 # 0x800
.size TOTALTHREADS, 4
.type N_GERA,@object # @N_GERA
.globl N_GERA
.p2align 2, 0x0
N_GERA:
.long 100 # 0x64
.size N_GERA, 4
.type _Z5cruzajjPiS_S_S_S_,@object # @_Z5cruzajjPiS_S_S_S_
.section .rodata,"a",@progbits
.globl _Z5cruzajjPiS_S_S_S_
.p2align 3, 0x0
_Z5cruzajjPiS_S_S_S_:
.quad _Z20__device_stub__cruzajjPiS_S_S_S_
.size _Z5cruzajjPiS_S_S_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5cruzajjPiS_S_S_S_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__cruzajjPiS_S_S_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5cruzajjPiS_S_S_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define ARRAY_SIZE 128
__global__ void avarage_list(float * value_in,float * value_out){
//Local memory
int index = threadIdx.x;
float sum = 0.0;
// Static shared var
__shared__ float sh_arr[ARRAY_SIZE];
//Shared mem | global memory
sh_arr[index] = value_in[index];
__syncthreads(); // Garante que todos os numeros foram copiados antes de começar a prox operaçao
//shared memory operation
for(int i = 0; i <= index;i++){
sum += sh_arr[i];
}
// Global memory | local memory
value_out[index] = sum / (index + 1);
}
int main(int argc,char** argv){
const int BYTE_SIZE = ARRAY_SIZE * sizeof(float);
//Host var
float h_values_in[ARRAY_SIZE];
float h_avarage_out[ARRAY_SIZE];
printf("Array Values : \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
h_values_in[i] = float(i * 2);
printf("%.2f " , h_values_in[i]);
}
printf("\n");
//Device var
float *d_values_in;
float *d_avarage_out;
cudaMalloc((void**) &d_values_in,BYTE_SIZE);
cudaMemcpy(d_values_in,h_values_in,BYTE_SIZE,cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_avarage_out,BYTE_SIZE);
avarage_list<<<1,ARRAY_SIZE>>>(d_values_in,d_avarage_out);
cudaMemcpy(h_avarage_out,d_avarage_out,BYTE_SIZE,cudaMemcpyDeviceToHost);
printf("Avarage Array: \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
printf("%.2f ",h_avarage_out[i]);
}
printf("\n");
cudaFree(d_values_in);
cudaFree(d_avarage_out);
return 0;
} | code for sm_80
Function : _Z12avarage_listPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x001fcc00078e0204 */
/*0050*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*0070*/ BSSY B2, 0x700 ; /* 0x0000068000027945 */
/* 0x000fe20003800000 */
/*0080*/ SHF.R.S32.HI R20, RZ, 0x1f, R3 ; /* 0x0000001fff147819 */
/* 0x000fe20000011403 */
/*0090*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0041e80000004800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ @!P0 BRA 0x6e0 ; /* 0x0000062000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, 0x3, PT ; /* 0x000000030300780c */
/* 0x041fe20003f06070 */
/*00d0*/ BSSY B1, 0x5c0 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*00e0*/ IADD3 R22, R3, 0x1, RZ ; /* 0x0000000103167810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc400078e00ff */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0110*/ LOP3.LUT R22, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316167812 */
/* 0x000fce00078ec0ff */
/*0120*/ @!P0 BRA 0x5b0 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.IADD R2, R3, 0x1, -R22 ; /* 0x0000000103027824 */
/* 0x000fe200078e0a16 */
/*0140*/ BSSY B0, 0x510 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0150*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fd800078e00ff */
/*0190*/ @!P0 BRA 0x500 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*01a0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ BSSY B3, 0x3a0 ; /* 0x000001e000037945 */
/* 0x000fe20003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01d0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*01e0*/ @!P1 BRA 0x390 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDS.128 R4, [R21] ; /* 0x0000000015047984 */
/* 0x000e220000000c00 */
/*0210*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*0230*/ LDS.128 R8, [R21+0x10] ; /* 0x0000100015087984 */
/* 0x000e620000000c00 */
/*0240*/ ISETP.GT.AND P1, PT, R2, 0xb, PT ; /* 0x0000000b0200780c */
/* 0x000fc60003f24270 */
/*0250*/ LDS.128 R12, [R21+0x20] ; /* 0x00002000150c7984 */
/* 0x000ea20000000c00 */
/*0260*/ FADD R4, R4, R19 ; /* 0x0000001304047221 */
/* 0x001fc60000000000 */
/*0270*/ LDS.128 R16, [R21+0x30] ; /* 0x0000300015107984 */
/* 0x0000e20000000c00 */
/*0280*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0290*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fe20000000000 */
/*02a0*/ IADD3 R21, R21, 0x40, RZ ; /* 0x0000004015157810 */
/* 0x001fc60007ffe0ff */
/*02b0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*02c0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fc80000000000 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*02e0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0300*/ FADD R12, R11, R12 ; /* 0x0000000c0b0c7221 */
/* 0x004fc80000000000 */
/*0310*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R16, R15, R16 ; /* 0x000000100f107221 */
/* 0x008fc80000000000 */
/*0350*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fe20000000000 */
/*0380*/ @P1 BRA 0x200 ; /* 0xfffffe7000001947 */
/* 0x000fea000383ffff */
/*0390*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ BSSY B3, 0x4d0 ; /* 0x0000011000037945 */
/* 0x000fe60003800000 */
/*03c0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*03d0*/ @!P1 BRA 0x4c0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*03e0*/ LDS.128 R4, [R21] ; /* 0x0000000015047984 */
/* 0x000e220000000c00 */
/*03f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0400*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe20007ffe0ff */
/*0410*/ LDS.128 R8, [R21+0x10] ; /* 0x0000100015087984 */
/* 0x0002a20000000c00 */
/*0420*/ IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802027810 */
/* 0x000fe40007ffe0ff */
/*0430*/ IADD3 R21, R21, 0x20, RZ ; /* 0x0000002015157810 */
/* 0x002fe20007ffe0ff */
/*0440*/ FADD R4, R19, R4 ; /* 0x0000000413047221 */
/* 0x001fc80000000000 */
/*0450*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0480*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fc80000000000 */
/*0490*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*04a0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*04b0*/ FADD R19, R10, R11 ; /* 0x0000000b0a137221 */
/* 0x000fe40000000000 */
/*04c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.NE.OR P0, PT, R2, -0x1, P0 ; /* 0xffffffff0200780c */
/* 0x000fda0000705670 */
/*04e0*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*04f0*/ @!P0 BRA 0x5b0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ LDS.128 R4, [R21] ; /* 0x0000000015047984 */
/* 0x0000620000000c00 */
/*0520*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe40007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R21, R21, 0x10, RZ ; /* 0x0000001015157810 */
/* 0x001fe20007ffe0ff */
/*0560*/ FADD R4, R4, R19 ; /* 0x0000001304047221 */
/* 0x002fc80000000000 */
/*0570*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0580*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0590*/ FADD R19, R6, R7 ; /* 0x0000000706137221 */
/* 0x000fe20000000000 */
/*05a0*/ @P0 BRA 0x510 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*05b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*05d0*/ BSSY B0, 0x6d0 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*05e0*/ @!P0 BRA 0x6c0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05f0*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x000e220000004800 */
/*0600*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*0620*/ FADD R19, R19, R2 ; /* 0x0000000213137221 */
/* 0x001fd80000000000 */
/*0630*/ @!P0 BRA 0x6c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fca00078e00ff */
/*0650*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fca0007ffe0ff */
/*0660*/ LDS R2, [R0] ; /* 0x0000000000027984 */
/* 0x0000620000000800 */
/*0670*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fc80007ffe0ff */
/*0680*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f05270 */
/*0690*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*06a0*/ FADD R19, R2, R19 ; /* 0x0000001302137221 */
/* 0x002fd40000000000 */
/*06b0*/ @P0 BRA 0x660 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x001fe400078e00ff */
/*06f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0700*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0710*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fe20007ffe0ff */
/*0720*/ BSSY B0, 0x800 ; /* 0x000000d000007945 */
/* 0x000fea0003800000 */
/*0730*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x000e300000201400 */
/*0740*/ MUFU.RCP R5, R2 ; /* 0x0000000200057308 */
/* 0x001e300000001000 */
/*0750*/ FCHK P0, R19, R2 ; /* 0x0000000213007302 */
/* 0x000e620000000000 */
/*0760*/ FFMA R0, -R2, R5, 1 ; /* 0x3f80000002007423 */
/* 0x001fc80000000105 */
/*0770*/ FFMA R0, R5, R0, R5 ; /* 0x0000000005007223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R5, R0, R19, RZ ; /* 0x0000001300057223 */
/* 0x000fc800000000ff */
/*0790*/ FFMA R4, -R2, R5, R19 ; /* 0x0000000502047223 */
/* 0x000fc80000000113 */
/*07a0*/ FFMA R5, R0, R4, R5 ; /* 0x0000000400057223 */
/* 0x000fe20000000005 */
/*07b0*/ @!P0 BRA 0x7f0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*07c0*/ MOV R0, 0x7e0 ; /* 0x000007e000007802 */
/* 0x000fe40000000f00 */
/*07d0*/ CALL.REL.NOINC 0x840 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*07e0*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0002 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ LEA R2, P0, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003027a11 */
/* 0x000fc800078010ff */
/*0810*/ LEA.HI.X R3, R3, c[0x0][0x16c], R20, 0x2, P0 ; /* 0x00005b0003037a11 */
/* 0x000fca00000f1414 */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ SHF.R.U32.HI R5, RZ, 0x17, R2.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011602 */
/*0850*/ BSSY B1, 0xea0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0860*/ SHF.R.U32.HI R4, RZ, 0x17, R19.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011613 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0880*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0890*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe200078ec0ff */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0013 */
/*08b0*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x000fc40007ffe0ff */
/*08d0*/ ISETP.GT.U32.AND P0, PT, R8, 0xfd, PT ; /* 0x000000fd0800780c */
/* 0x000fc80003f04070 */
/*08e0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*08f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0900*/ @!P0 BRA 0xa80 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0910*/ FSETP.GTU.FTZ.AND P0, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */
/* 0x000fe40003f1c200 */
/*0920*/ FSETP.GTU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f3c200 */
/*0930*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0940*/ @P0 BRA 0xe80 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R4, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c804 */
/*0960*/ @!P0 BRA 0xe60 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.NEU.FTZ.AND P2, PT, |R19|.reuse, +INF , PT ; /* 0x7f8000001300780b */
/* 0x040fe40003f5d200 */
/*0980*/ FSETP.NEU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f3d200 */
/*0990*/ FSETP.NEU.FTZ.AND P0, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */
/* 0x000fd60003f1d200 */
/*09a0*/ @!P1 BRA !P2, 0xe60 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*09b0*/ LOP3.LUT P2, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000784c0ff */
/*09c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*09d0*/ @P1 BRA 0xe40 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*09f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a00*/ @P0 BRA 0xe10 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0a20*/ ISETP.GE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fd60003f26270 */
/*0a30*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0a40*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0a50*/ @!P0 FFMA R4, R19, 1.84467440737095516160e+19, RZ ; /* 0x5f80000013048823 */
/* 0x000fe400000000ff */
/*0a60*/ @!P1 FFMA R7, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002079823 */
/* 0x000fe200000000ff */
/*0a70*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ LEA R2, R5, 0xc0800000, 0x17 ; /* 0xc080000005027811 */
/* 0x000fe200078eb8ff */
/*0a90*/ BSSY B2, 0xe00 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0aa0*/ IMAD.IADD R8, R7, 0x1, -R2 ; /* 0x0000000107087824 */
/* 0x000fe200078e0a02 */
/*0ab0*/ IADD3 R7, R10, -0x7f, RZ ; /* 0xffffff810a077810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ MUFU.RCP R2, R8 ; /* 0x0000000800027308 */
/* 0x000e220000001000 */
/*0ad0*/ FADD.FTZ R9, -R8, -RZ ; /* 0x800000ff08097221 */
/* 0x000fe20000010100 */
/*0ae0*/ IADD3 R5, R7.reuse, 0x7f, -R5 ; /* 0x0000007f07057810 */
/* 0x040fe20007ffe805 */
/*0af0*/ IMAD R4, R7, -0x800000, R4 ; /* 0xff80000007047824 */
/* 0x000fc800078e0204 */
/*0b00*/ IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105057824 */
/* 0x000fe400078e0206 */
/*0b10*/ FFMA R11, R2, R9, 1 ; /* 0x3f800000020b7423 */
/* 0x001fc80000000009 */
/*0b20*/ FFMA R13, R2, R11, R2 ; /* 0x0000000b020d7223 */
/* 0x000fc80000000002 */
/*0b30*/ FFMA R2, R4, R13, RZ ; /* 0x0000000d04027223 */
/* 0x000fc800000000ff */
/*0b40*/ FFMA R11, R9, R2, R4 ; /* 0x00000002090b7223 */
/* 0x000fc80000000004 */
/*0b50*/ FFMA R10, R13, R11, R2 ; /* 0x0000000b0d0a7223 */
/* 0x000fc80000000002 */
/*0b60*/ FFMA R9, R9, R10, R4 ; /* 0x0000000a09097223 */
/* 0x000fc80000000004 */
/*0b70*/ FFMA R2, R13, R9, R10 ; /* 0x000000090d027223 */
/* 0x000fca000000000a */
/*0b80*/ SHF.R.U32.HI R4, RZ, 0x17, R2 ; /* 0x00000017ff047819 */
/* 0x000fc80000011602 */
/*0b90*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0ba0*/ IMAD.IADD R8, R4, 0x1, R5 ; /* 0x0000000104087824 */
/* 0x000fca00078e0205 */
/*0bb0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0bc0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0bd0*/ @!P0 BRA 0xde0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0be0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0bf0*/ @P0 BRA 0xdb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0c10*/ @P0 BRA 0xdf0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0c20*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0c30*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fd600078ec0ff */
/*0c40*/ @!P0 BRA 0xdf0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0c50*/ FFMA.RZ R4, R13.reuse, R9.reuse, R10.reuse ; /* 0x000000090d047223 */
/* 0x1c0fe2000000c00a */
/*0c60*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x040fe20007ffe0ff */
/*0c70*/ FFMA.RM R5, R13.reuse, R9.reuse, R10.reuse ; /* 0x000000090d057223 */
/* 0x1c0fe2000000400a */
/*0c80*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0c90*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0ca0*/ FFMA.RP R4, R13, R9, R10 ; /* 0x000000090d047223 */
/* 0x000fe2000000800a */
/*0cb0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0cc0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0cd0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0ce0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0cf0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0d00*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0d10*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0d20*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0d30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0d40*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0d50*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0d60*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0d70*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0d80*/ IMAD.IADD R7, R7, 0x1, R4 ; /* 0x0000000107077824 */
/* 0x000fca00078e0204 */
/*0d90*/ LOP3.LUT R2, R7, R2, RZ, 0xfc, !PT ; /* 0x0000000207027212 */
/* 0x000fe200078efcff */
/*0da0*/ BRA 0xdf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0db0*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fc800078ec0ff */
/*0dc0*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000002027812 */
/* 0x000fe200078efcff */
/*0dd0*/ BRA 0xdf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0de0*/ IMAD R2, R5, 0x800000, R2 ; /* 0x0080000005027824 */
/* 0x000fe400078e0202 */
/*0df0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e00*/ BRA 0xe90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e10*/ LOP3.LUT R2, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007027812 */
/* 0x000fc800078e4804 */
/*0e20*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000002027812 */
/* 0x000fe200078efcff */
/*0e30*/ BRA 0xe90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0e40*/ LOP3.LUT R2, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007027812 */
/* 0x000fe200078e4804 */
/*0e50*/ BRA 0xe90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0e60*/ MUFU.RSQ R2, -QNAN ; /* 0xffc0000000027908 */
/* 0x000e220000001400 */
/*0e70*/ BRA 0xe90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e80*/ FADD.FTZ R2, R19, R2 ; /* 0x0000000213027221 */
/* 0x000fe40000010000 */
/*0e90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ea0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0eb0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0ec0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff13004007950 */
/* 0x000fea0003c3ffff */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define ARRAY_SIZE 128
__global__ void avarage_list(float * value_in,float * value_out){
//Local memory
int index = threadIdx.x;
float sum = 0.0;
// Static shared var
__shared__ float sh_arr[ARRAY_SIZE];
//Shared mem | global memory
sh_arr[index] = value_in[index];
__syncthreads(); // Garante que todos os numeros foram copiados antes de começar a prox operaçao
//shared memory operation
for(int i = 0; i <= index;i++){
sum += sh_arr[i];
}
// Global memory | local memory
value_out[index] = sum / (index + 1);
}
int main(int argc,char** argv){
const int BYTE_SIZE = ARRAY_SIZE * sizeof(float);
//Host var
float h_values_in[ARRAY_SIZE];
float h_avarage_out[ARRAY_SIZE];
printf("Array Values : \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
h_values_in[i] = float(i * 2);
printf("%.2f " , h_values_in[i]);
}
printf("\n");
//Device var
float *d_values_in;
float *d_avarage_out;
cudaMalloc((void**) &d_values_in,BYTE_SIZE);
cudaMemcpy(d_values_in,h_values_in,BYTE_SIZE,cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_avarage_out,BYTE_SIZE);
avarage_list<<<1,ARRAY_SIZE>>>(d_values_in,d_avarage_out);
cudaMemcpy(h_avarage_out,d_avarage_out,BYTE_SIZE,cudaMemcpyDeviceToHost);
printf("Avarage Array: \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
printf("%.2f ",h_avarage_out[i]);
}
printf("\n");
cudaFree(d_values_in);
cudaFree(d_avarage_out);
return 0;
} | .file "tmpxft_00196b5b_00000000-6_memory_examples.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12avarage_listPfS_PfS_
.type _Z34__device_stub__Z12avarage_listPfS_PfS_, @function
_Z34__device_stub__Z12avarage_listPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12avarage_listPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12avarage_listPfS_PfS_, .-_Z34__device_stub__Z12avarage_listPfS_PfS_
.globl _Z12avarage_listPfS_
.type _Z12avarage_listPfS_, @function
_Z12avarage_listPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12avarage_listPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12avarage_listPfS_, .-_Z12avarage_listPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Array Values : \n"
.LC1:
.string "%.2f "
.LC2:
.string "\n"
.LC3:
.string "Avarage Array: \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1096, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 560(%rsp), %r13
movl $0, %ebp
leaq .LC1(%rip), %r12
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
movss %xmm0, (%rbx)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $2, %ebp
addq $4, %rbx
cmpq %r13, %rbx
jne .L12
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 560(%rsp), %rbx
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1072(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12avarage_listPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12avarage_listPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12avarage_listPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define ARRAY_SIZE 128
__global__ void avarage_list(float * value_in,float * value_out){
//Local memory
int index = threadIdx.x;
float sum = 0.0;
// Static shared var
__shared__ float sh_arr[ARRAY_SIZE];
//Shared mem | global memory
sh_arr[index] = value_in[index];
__syncthreads(); // Garante que todos os numeros foram copiados antes de começar a prox operaçao
//shared memory operation
for(int i = 0; i <= index;i++){
sum += sh_arr[i];
}
// Global memory | local memory
value_out[index] = sum / (index + 1);
}
int main(int argc,char** argv){
const int BYTE_SIZE = ARRAY_SIZE * sizeof(float);
//Host var
float h_values_in[ARRAY_SIZE];
float h_avarage_out[ARRAY_SIZE];
printf("Array Values : \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
h_values_in[i] = float(i * 2);
printf("%.2f " , h_values_in[i]);
}
printf("\n");
//Device var
float *d_values_in;
float *d_avarage_out;
cudaMalloc((void**) &d_values_in,BYTE_SIZE);
cudaMemcpy(d_values_in,h_values_in,BYTE_SIZE,cudaMemcpyHostToDevice);
cudaMalloc((void**) &d_avarage_out,BYTE_SIZE);
avarage_list<<<1,ARRAY_SIZE>>>(d_values_in,d_avarage_out);
cudaMemcpy(h_avarage_out,d_avarage_out,BYTE_SIZE,cudaMemcpyDeviceToHost);
printf("Avarage Array: \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
printf("%.2f ",h_avarage_out[i]);
}
printf("\n");
cudaFree(d_values_in);
cudaFree(d_avarage_out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ARRAY_SIZE 128
__global__ void avarage_list(float * value_in,float * value_out){
//Local memory
int index = threadIdx.x;
float sum = 0.0;
// Static shared var
__shared__ float sh_arr[ARRAY_SIZE];
//Shared mem | global memory
sh_arr[index] = value_in[index];
__syncthreads(); // Garante que todos os numeros foram copiados antes de começar a prox operaçao
//shared memory operation
for(int i = 0; i <= index;i++){
sum += sh_arr[i];
}
// Global memory | local memory
value_out[index] = sum / (index + 1);
}
int main(int argc,char** argv){
const int BYTE_SIZE = ARRAY_SIZE * sizeof(float);
//Host var
float h_values_in[ARRAY_SIZE];
float h_avarage_out[ARRAY_SIZE];
printf("Array Values : \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
h_values_in[i] = float(i * 2);
printf("%.2f " , h_values_in[i]);
}
printf("\n");
//Device var
float *d_values_in;
float *d_avarage_out;
hipMalloc((void**) &d_values_in,BYTE_SIZE);
hipMemcpy(d_values_in,h_values_in,BYTE_SIZE,hipMemcpyHostToDevice);
hipMalloc((void**) &d_avarage_out,BYTE_SIZE);
avarage_list<<<1,ARRAY_SIZE>>>(d_values_in,d_avarage_out);
hipMemcpy(h_avarage_out,d_avarage_out,BYTE_SIZE,hipMemcpyDeviceToHost);
printf("Avarage Array: \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
printf("%.2f ",h_avarage_out[i]);
}
printf("\n");
hipFree(d_values_in);
hipFree(d_avarage_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ARRAY_SIZE 128
__global__ void avarage_list(float * value_in,float * value_out){
//Local memory
int index = threadIdx.x;
float sum = 0.0;
// Static shared var
__shared__ float sh_arr[ARRAY_SIZE];
//Shared mem | global memory
sh_arr[index] = value_in[index];
__syncthreads(); // Garante que todos os numeros foram copiados antes de começar a prox operaçao
//shared memory operation
for(int i = 0; i <= index;i++){
sum += sh_arr[i];
}
// Global memory | local memory
value_out[index] = sum / (index + 1);
}
int main(int argc,char** argv){
const int BYTE_SIZE = ARRAY_SIZE * sizeof(float);
//Host var
float h_values_in[ARRAY_SIZE];
float h_avarage_out[ARRAY_SIZE];
printf("Array Values : \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
h_values_in[i] = float(i * 2);
printf("%.2f " , h_values_in[i]);
}
printf("\n");
//Device var
float *d_values_in;
float *d_avarage_out;
hipMalloc((void**) &d_values_in,BYTE_SIZE);
hipMemcpy(d_values_in,h_values_in,BYTE_SIZE,hipMemcpyHostToDevice);
hipMalloc((void**) &d_avarage_out,BYTE_SIZE);
avarage_list<<<1,ARRAY_SIZE>>>(d_values_in,d_avarage_out);
hipMemcpy(h_avarage_out,d_avarage_out,BYTE_SIZE,hipMemcpyDeviceToHost);
printf("Avarage Array: \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
printf("%.2f ",h_avarage_out[i]);
}
printf("\n");
hipFree(d_values_in);
hipFree(d_avarage_out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12avarage_listPfS_
.globl _Z12avarage_listPfS_
.p2align 8
.type _Z12avarage_listPfS_,@function
_Z12avarage_listPfS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, 1, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
s_mov_b32 s3, 0
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_1:
v_dual_mov_b32 v3, s3 :: v_dual_add_nc_u32 v2, -1, v2
s_add_i32 s3, s3, 4
ds_load_b32 v3, v3
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_or_b32 s2, vcc_lo, s2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v3
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, 1, v0
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v2
v_div_scale_f32 v3, null, v2, v2, v1
v_div_scale_f32 v6, vcc_lo, v1, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v5
v_div_fixup_f32 v1, v3, v2, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12avarage_listPfS_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12avarage_listPfS_, .Lfunc_end0-_Z12avarage_listPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12avarage_listPfS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z12avarage_listPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define ARRAY_SIZE 128
__global__ void avarage_list(float * value_in,float * value_out){
//Local memory
int index = threadIdx.x;
float sum = 0.0;
// Static shared var
__shared__ float sh_arr[ARRAY_SIZE];
//Shared mem | global memory
sh_arr[index] = value_in[index];
__syncthreads(); // Garante que todos os numeros foram copiados antes de começar a prox operaçao
//shared memory operation
for(int i = 0; i <= index;i++){
sum += sh_arr[i];
}
// Global memory | local memory
value_out[index] = sum / (index + 1);
}
int main(int argc,char** argv){
const int BYTE_SIZE = ARRAY_SIZE * sizeof(float);
//Host var
float h_values_in[ARRAY_SIZE];
float h_avarage_out[ARRAY_SIZE];
printf("Array Values : \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
h_values_in[i] = float(i * 2);
printf("%.2f " , h_values_in[i]);
}
printf("\n");
//Device var
float *d_values_in;
float *d_avarage_out;
hipMalloc((void**) &d_values_in,BYTE_SIZE);
hipMemcpy(d_values_in,h_values_in,BYTE_SIZE,hipMemcpyHostToDevice);
hipMalloc((void**) &d_avarage_out,BYTE_SIZE);
avarage_list<<<1,ARRAY_SIZE>>>(d_values_in,d_avarage_out);
hipMemcpy(h_avarage_out,d_avarage_out,BYTE_SIZE,hipMemcpyDeviceToHost);
printf("Avarage Array: \n");
for(int i = 0 ; i < ARRAY_SIZE;i++){
printf("%.2f ",h_avarage_out[i]);
}
printf("\n");
hipFree(d_values_in);
hipFree(d_avarage_out);
return 0;
} | .text
.file "memory_examples.hip"
.globl _Z27__device_stub__avarage_listPfS_ # -- Begin function _Z27__device_stub__avarage_listPfS_
.p2align 4, 0x90
.type _Z27__device_stub__avarage_listPfS_,@function
_Z27__device_stub__avarage_listPfS_: # @_Z27__device_stub__avarage_listPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12avarage_listPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__avarage_listPfS_, .Lfunc_end0-_Z27__device_stub__avarage_listPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 1120
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 592(%rsp,%rbx,2)
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $2, %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 8(%rsp), %rdi
leaq 592(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12avarage_listPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $128, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12avarage_listPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12avarage_listPfS_,@object # @_Z12avarage_listPfS_
.section .rodata,"a",@progbits
.globl _Z12avarage_listPfS_
.p2align 3, 0x0
_Z12avarage_listPfS_:
.quad _Z27__device_stub__avarage_listPfS_
.size _Z12avarage_listPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.2f "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12avarage_listPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Array Values : "
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Avarage Array: "
.size .Lstr.1, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__avarage_listPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12avarage_listPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12avarage_listPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE R4, R3, R4, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x001fcc00078e0204 */
/*0050*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*0060*/ ISETP.GE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f06270 */
/*0070*/ BSSY B2, 0x700 ; /* 0x0000068000027945 */
/* 0x000fe20003800000 */
/*0080*/ SHF.R.S32.HI R20, RZ, 0x1f, R3 ; /* 0x0000001fff147819 */
/* 0x000fe20000011403 */
/*0090*/ STS [R3.X4], R4 ; /* 0x0000000403007388 */
/* 0x0041e80000004800 */
/*00a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00b0*/ @!P0 BRA 0x6e0 ; /* 0x0000062000008947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R3.reuse, 0x3, PT ; /* 0x000000030300780c */
/* 0x041fe20003f06070 */
/*00d0*/ BSSY B1, 0x5c0 ; /* 0x000004e000017945 */
/* 0x000fe20003800000 */
/*00e0*/ IADD3 R22, R3, 0x1, RZ ; /* 0x0000000103167810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc400078e00ff */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0110*/ LOP3.LUT R22, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316167812 */
/* 0x000fce00078ec0ff */
/*0120*/ @!P0 BRA 0x5b0 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0130*/ IMAD.IADD R2, R3, 0x1, -R22 ; /* 0x0000000103027824 */
/* 0x000fe200078e0a16 */
/*0140*/ BSSY B0, 0x510 ; /* 0x000003c000007945 */
/* 0x000fe20003800000 */
/*0150*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0170*/ ISETP.GT.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x000fe20003f04270 */
/*0180*/ IMAD.MOV.U32 R21, RZ, RZ, RZ ; /* 0x000000ffff157224 */
/* 0x000fd800078e00ff */
/*0190*/ @!P0 BRA 0x500 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*01a0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*01b0*/ BSSY B3, 0x3a0 ; /* 0x000001e000037945 */
/* 0x000fe20003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01d0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*01e0*/ @!P1 BRA 0x390 ; /* 0x000001a000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ LDS.128 R4, [R21] ; /* 0x0000000015047984 */
/* 0x000e220000000c00 */
/*0210*/ IADD3 R2, R2, -0x10, RZ ; /* 0xfffffff002027810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*0230*/ LDS.128 R8, [R21+0x10] ; /* 0x0000100015087984 */
/* 0x000e620000000c00 */
/*0240*/ ISETP.GT.AND P1, PT, R2, 0xb, PT ; /* 0x0000000b0200780c */
/* 0x000fc60003f24270 */
/*0250*/ LDS.128 R12, [R21+0x20] ; /* 0x00002000150c7984 */
/* 0x000ea20000000c00 */
/*0260*/ FADD R4, R4, R19 ; /* 0x0000001304047221 */
/* 0x001fc60000000000 */
/*0270*/ LDS.128 R16, [R21+0x30] ; /* 0x0000300015107984 */
/* 0x0000e20000000c00 */
/*0280*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0290*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fe20000000000 */
/*02a0*/ IADD3 R21, R21, 0x40, RZ ; /* 0x0000004015157810 */
/* 0x001fc60007ffe0ff */
/*02b0*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*02c0*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x002fc80000000000 */
/*02d0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*02e0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*02f0*/ FADD R11, R10, R11 ; /* 0x0000000b0a0b7221 */
/* 0x000fc80000000000 */
/*0300*/ FADD R12, R11, R12 ; /* 0x0000000c0b0c7221 */
/* 0x004fc80000000000 */
/*0310*/ FADD R13, R12, R13 ; /* 0x0000000d0c0d7221 */
/* 0x000fc80000000000 */
/*0320*/ FADD R14, R13, R14 ; /* 0x0000000e0d0e7221 */
/* 0x000fc80000000000 */
/*0330*/ FADD R15, R14, R15 ; /* 0x0000000f0e0f7221 */
/* 0x000fc80000000000 */
/*0340*/ FADD R16, R15, R16 ; /* 0x000000100f107221 */
/* 0x008fc80000000000 */
/*0350*/ FADD R17, R16, R17 ; /* 0x0000001110117221 */
/* 0x000fc80000000000 */
/*0360*/ FADD R18, R17, R18 ; /* 0x0000001211127221 */
/* 0x000fc80000000000 */
/*0370*/ FADD R19, R18, R19 ; /* 0x0000001312137221 */
/* 0x000fe20000000000 */
/*0380*/ @P1 BRA 0x200 ; /* 0xfffffe7000001947 */
/* 0x000fea000383ffff */
/*0390*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*03b0*/ BSSY B3, 0x4d0 ; /* 0x0000011000037945 */
/* 0x000fe60003800000 */
/*03c0*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*03d0*/ @!P1 BRA 0x4c0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*03e0*/ LDS.128 R4, [R21] ; /* 0x0000000015047984 */
/* 0x000e220000000c00 */
/*03f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0400*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe20007ffe0ff */
/*0410*/ LDS.128 R8, [R21+0x10] ; /* 0x0000100015087984 */
/* 0x0002a20000000c00 */
/*0420*/ IADD3 R2, R2, -0x8, RZ ; /* 0xfffffff802027810 */
/* 0x000fe40007ffe0ff */
/*0430*/ IADD3 R21, R21, 0x20, RZ ; /* 0x0000002015157810 */
/* 0x002fe20007ffe0ff */
/*0440*/ FADD R4, R19, R4 ; /* 0x0000000413047221 */
/* 0x001fc80000000000 */
/*0450*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R7, R6, R7 ; /* 0x0000000706077221 */
/* 0x000fc80000000000 */
/*0480*/ FADD R8, R7, R8 ; /* 0x0000000807087221 */
/* 0x004fc80000000000 */
/*0490*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x000fc80000000000 */
/*04a0*/ FADD R10, R9, R10 ; /* 0x0000000a090a7221 */
/* 0x000fc80000000000 */
/*04b0*/ FADD R19, R10, R11 ; /* 0x0000000b0a137221 */
/* 0x000fe40000000000 */
/*04c0*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.NE.OR P0, PT, R2, -0x1, P0 ; /* 0xffffffff0200780c */
/* 0x000fda0000705670 */
/*04e0*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*04f0*/ @!P0 BRA 0x5b0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ LDS.128 R4, [R21] ; /* 0x0000000015047984 */
/* 0x0000620000000c00 */
/*0520*/ IADD3 R2, R2, -0x4, RZ ; /* 0xfffffffc02027810 */
/* 0x000fe40007ffe0ff */
/*0530*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe40007ffe0ff */
/*0540*/ ISETP.NE.AND P0, PT, R2, -0x1, PT ; /* 0xffffffff0200780c */
/* 0x000fe40003f05270 */
/*0550*/ IADD3 R21, R21, 0x10, RZ ; /* 0x0000001015157810 */
/* 0x001fe20007ffe0ff */
/*0560*/ FADD R4, R4, R19 ; /* 0x0000001304047221 */
/* 0x002fc80000000000 */
/*0570*/ FADD R5, R4, R5 ; /* 0x0000000504057221 */
/* 0x000fc80000000000 */
/*0580*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fc80000000000 */
/*0590*/ FADD R19, R6, R7 ; /* 0x0000000706137221 */
/* 0x000fe20000000000 */
/*05a0*/ @P0 BRA 0x510 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*05b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05c0*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*05d0*/ BSSY B0, 0x6d0 ; /* 0x000000f000007945 */
/* 0x000fd80003800000 */
/*05e0*/ @!P0 BRA 0x6c0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05f0*/ LDS R2, [R0.X4] ; /* 0x0000000000027984 */
/* 0x000e220000004800 */
/*0600*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*0620*/ FADD R19, R19, R2 ; /* 0x0000000213137221 */
/* 0x001fd80000000000 */
/*0630*/ @!P0 BRA 0x6c0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0640*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x000fca00078e00ff */
/*0650*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fca0007ffe0ff */
/*0660*/ LDS R2, [R0] ; /* 0x0000000000027984 */
/* 0x0000620000000800 */
/*0670*/ IADD3 R22, R22, -0x1, RZ ; /* 0xffffffff16167810 */
/* 0x000fc80007ffe0ff */
/*0680*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe40003f05270 */
/*0690*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*06a0*/ FADD R19, R2, R19 ; /* 0x0000001302137221 */
/* 0x002fd40000000000 */
/*06b0*/ @P0 BRA 0x660 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ BRA 0x6f0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*06e0*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x001fe400078e00ff */
/*06f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0700*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0710*/ IADD3 R2, R3, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x000fe20007ffe0ff */
/*0720*/ BSSY B0, 0x800 ; /* 0x000000d000007945 */
/* 0x000fea0003800000 */
/*0730*/ I2F R2, R2 ; /* 0x0000000200027306 */
/* 0x000e300000201400 */
/*0740*/ MUFU.RCP R5, R2 ; /* 0x0000000200057308 */
/* 0x001e300000001000 */
/*0750*/ FCHK P0, R19, R2 ; /* 0x0000000213007302 */
/* 0x000e620000000000 */
/*0760*/ FFMA R0, -R2, R5, 1 ; /* 0x3f80000002007423 */
/* 0x001fc80000000105 */
/*0770*/ FFMA R0, R5, R0, R5 ; /* 0x0000000005007223 */
/* 0x000fc80000000005 */
/*0780*/ FFMA R5, R0, R19, RZ ; /* 0x0000001300057223 */
/* 0x000fc800000000ff */
/*0790*/ FFMA R4, -R2, R5, R19 ; /* 0x0000000502047223 */
/* 0x000fc80000000113 */
/*07a0*/ FFMA R5, R0, R4, R5 ; /* 0x0000000400057223 */
/* 0x000fe20000000005 */
/*07b0*/ @!P0 BRA 0x7f0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*07c0*/ MOV R0, 0x7e0 ; /* 0x000007e000007802 */
/* 0x000fe40000000f00 */
/*07d0*/ CALL.REL.NOINC 0x840 ; /* 0x0000006000007944 */
/* 0x000fea0003c00000 */
/*07e0*/ IMAD.MOV.U32 R5, RZ, RZ, R2 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0002 */
/*07f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0800*/ LEA R2, P0, R3, c[0x0][0x168], 0x2 ; /* 0x00005a0003027a11 */
/* 0x000fc800078010ff */
/*0810*/ LEA.HI.X R3, R3, c[0x0][0x16c], R20, 0x2, P0 ; /* 0x00005b0003037a11 */
/* 0x000fca00000f1414 */
/*0820*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0830*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0840*/ SHF.R.U32.HI R5, RZ, 0x17, R2.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011602 */
/*0850*/ BSSY B1, 0xea0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0860*/ SHF.R.U32.HI R4, RZ, 0x17, R19.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011613 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0880*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0890*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe200078ec0ff */
/*08a0*/ IMAD.MOV.U32 R4, RZ, RZ, R19 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0013 */
/*08b0*/ IADD3 R8, R5, -0x1, RZ ; /* 0xffffffff05087810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R9, R10, -0x1, RZ ; /* 0xffffffff0a097810 */
/* 0x000fc40007ffe0ff */
/*08d0*/ ISETP.GT.U32.AND P0, PT, R8, 0xfd, PT ; /* 0x000000fd0800780c */
/* 0x000fc80003f04070 */
/*08e0*/ ISETP.GT.U32.OR P0, PT, R9, 0xfd, P0 ; /* 0x000000fd0900780c */
/* 0x000fda0000704470 */
/*08f0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*0900*/ @!P0 BRA 0xa80 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0910*/ FSETP.GTU.FTZ.AND P0, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */
/* 0x000fe40003f1c200 */
/*0920*/ FSETP.GTU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fc80003f3c200 */
/*0930*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0940*/ @P0 BRA 0xe80 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0950*/ LOP3.LUT P0, RZ, R7, 0x7fffffff, R4, 0xc8, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fda000780c804 */
/*0960*/ @!P0 BRA 0xe60 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.NEU.FTZ.AND P2, PT, |R19|.reuse, +INF , PT ; /* 0x7f8000001300780b */
/* 0x040fe40003f5d200 */
/*0980*/ FSETP.NEU.FTZ.AND P1, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fe40003f3d200 */
/*0990*/ FSETP.NEU.FTZ.AND P0, PT, |R19|, +INF , PT ; /* 0x7f8000001300780b */
/* 0x000fd60003f1d200 */
/*09a0*/ @!P1 BRA !P2, 0xe60 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*09b0*/ LOP3.LUT P2, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fc8000784c0ff */
/*09c0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*09d0*/ @P1 BRA 0xe40 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*09e0*/ LOP3.LUT P1, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000782c0ff */
/*09f0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0a00*/ @P0 BRA 0xe10 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0a10*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f06270 */
/*0a20*/ ISETP.GE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fd60003f26270 */
/*0a30*/ @P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff060224 */
/* 0x000fe400078e00ff */
/*0a40*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, -0x40 ; /* 0xffffffc0ff068424 */
/* 0x000fe400078e00ff */
/*0a50*/ @!P0 FFMA R4, R19, 1.84467440737095516160e+19, RZ ; /* 0x5f80000013048823 */
/* 0x000fe400000000ff */
/*0a60*/ @!P1 FFMA R7, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002079823 */
/* 0x000fe200000000ff */
/*0a70*/ @!P1 IADD3 R6, R6, 0x40, RZ ; /* 0x0000004006069810 */
/* 0x000fe40007ffe0ff */
/*0a80*/ LEA R2, R5, 0xc0800000, 0x17 ; /* 0xc080000005027811 */
/* 0x000fe200078eb8ff */
/*0a90*/ BSSY B2, 0xe00 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0aa0*/ IMAD.IADD R8, R7, 0x1, -R2 ; /* 0x0000000107087824 */
/* 0x000fe200078e0a02 */
/*0ab0*/ IADD3 R7, R10, -0x7f, RZ ; /* 0xffffff810a077810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ MUFU.RCP R2, R8 ; /* 0x0000000800027308 */
/* 0x000e220000001000 */
/*0ad0*/ FADD.FTZ R9, -R8, -RZ ; /* 0x800000ff08097221 */
/* 0x000fe20000010100 */
/*0ae0*/ IADD3 R5, R7.reuse, 0x7f, -R5 ; /* 0x0000007f07057810 */
/* 0x040fe20007ffe805 */
/*0af0*/ IMAD R4, R7, -0x800000, R4 ; /* 0xff80000007047824 */
/* 0x000fc800078e0204 */
/*0b00*/ IMAD.IADD R5, R5, 0x1, R6 ; /* 0x0000000105057824 */
/* 0x000fe400078e0206 */
/*0b10*/ FFMA R11, R2, R9, 1 ; /* 0x3f800000020b7423 */
/* 0x001fc80000000009 */
/*0b20*/ FFMA R13, R2, R11, R2 ; /* 0x0000000b020d7223 */
/* 0x000fc80000000002 */
/*0b30*/ FFMA R2, R4, R13, RZ ; /* 0x0000000d04027223 */
/* 0x000fc800000000ff */
/*0b40*/ FFMA R11, R9, R2, R4 ; /* 0x00000002090b7223 */
/* 0x000fc80000000004 */
/*0b50*/ FFMA R10, R13, R11, R2 ; /* 0x0000000b0d0a7223 */
/* 0x000fc80000000002 */
/*0b60*/ FFMA R9, R9, R10, R4 ; /* 0x0000000a09097223 */
/* 0x000fc80000000004 */
/*0b70*/ FFMA R2, R13, R9, R10 ; /* 0x000000090d027223 */
/* 0x000fca000000000a */
/*0b80*/ SHF.R.U32.HI R4, RZ, 0x17, R2 ; /* 0x00000017ff047819 */
/* 0x000fc80000011602 */
/*0b90*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0ba0*/ IMAD.IADD R8, R4, 0x1, R5 ; /* 0x0000000104087824 */
/* 0x000fca00078e0205 */
/*0bb0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0bc0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0bd0*/ @!P0 BRA 0xde0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0be0*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0bf0*/ @P0 BRA 0xdb0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0c00*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0c10*/ @P0 BRA 0xdf0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0c20*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0c30*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fd600078ec0ff */
/*0c40*/ @!P0 BRA 0xdf0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0c50*/ FFMA.RZ R4, R13.reuse, R9.reuse, R10.reuse ; /* 0x000000090d047223 */
/* 0x1c0fe2000000c00a */
/*0c60*/ IADD3 R7, R8.reuse, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x040fe20007ffe0ff */
/*0c70*/ FFMA.RM R5, R13.reuse, R9.reuse, R10.reuse ; /* 0x000000090d057223 */
/* 0x1c0fe2000000400a */
/*0c80*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*0c90*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0ca0*/ FFMA.RP R4, R13, R9, R10 ; /* 0x000000090d047223 */
/* 0x000fe2000000800a */
/*0cb0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f25270 */
/*0cc0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0cd0*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0ce0*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0cf0*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0d00*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0d10*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0d20*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0d30*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0d40*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0d50*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0d60*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0d70*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0d80*/ IMAD.IADD R7, R7, 0x1, R4 ; /* 0x0000000107077824 */
/* 0x000fca00078e0204 */
/*0d90*/ LOP3.LUT R2, R7, R2, RZ, 0xfc, !PT ; /* 0x0000000207027212 */
/* 0x000fe200078efcff */
/*0da0*/ BRA 0xdf0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0db0*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000002027812 */
/* 0x000fc800078ec0ff */
/*0dc0*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000002027812 */
/* 0x000fe200078efcff */
/*0dd0*/ BRA 0xdf0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0de0*/ IMAD R2, R5, 0x800000, R2 ; /* 0x0080000005027824 */
/* 0x000fe400078e0202 */
/*0df0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0e00*/ BRA 0xe90 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0e10*/ LOP3.LUT R2, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007027812 */
/* 0x000fc800078e4804 */
/*0e20*/ LOP3.LUT R2, R2, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000002027812 */
/* 0x000fe200078efcff */
/*0e30*/ BRA 0xe90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0e40*/ LOP3.LUT R2, R7, 0x80000000, R4, 0x48, !PT ; /* 0x8000000007027812 */
/* 0x000fe200078e4804 */
/*0e50*/ BRA 0xe90 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0e60*/ MUFU.RSQ R2, -QNAN ; /* 0xffc0000000027908 */
/* 0x000e220000001400 */
/*0e70*/ BRA 0xe90 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0e80*/ FADD.FTZ R2, R19, R2 ; /* 0x0000000213027221 */
/* 0x000fe40000010000 */
/*0e90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ea0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0eb0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0ec0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff13004007950 */
/* 0x000fea0003c3ffff */
/*0ed0*/ BRA 0xed0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0f70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12avarage_listPfS_
.globl _Z12avarage_listPfS_
.p2align 8
.type _Z12avarage_listPfS_,@function
_Z12avarage_listPfS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, 1, v0
s_waitcnt lgkmcnt(0)
global_load_b32 v4, v3, s[2:3]
s_mov_b32 s3, 0
s_mov_b32 s2, 0
s_waitcnt vmcnt(0)
ds_store_b32 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_1:
v_dual_mov_b32 v3, s3 :: v_dual_add_nc_u32 v2, -1, v2
s_add_i32 s3, s3, 4
ds_load_b32 v3, v3
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_or_b32 s2, vcc_lo, s2
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v3
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_1
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, 1, v0
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v2, v2
v_div_scale_f32 v3, null, v2, v2, v1
v_div_scale_f32 v6, vcc_lo, v1, v2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v5
v_div_fixup_f32 v1, v3, v2, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12avarage_listPfS_
.amdhsa_group_segment_fixed_size 512
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12avarage_listPfS_, .Lfunc_end0-_Z12avarage_listPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 512
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12avarage_listPfS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z12avarage_listPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00196b5b_00000000-6_memory_examples.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12avarage_listPfS_PfS_
.type _Z34__device_stub__Z12avarage_listPfS_PfS_, @function
_Z34__device_stub__Z12avarage_listPfS_PfS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12avarage_listPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12avarage_listPfS_PfS_, .-_Z34__device_stub__Z12avarage_listPfS_PfS_
.globl _Z12avarage_listPfS_
.type _Z12avarage_listPfS_, @function
_Z12avarage_listPfS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12avarage_listPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12avarage_listPfS_, .-_Z12avarage_listPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Array Values : \n"
.LC1:
.string "%.2f "
.LC2:
.string "\n"
.LC3:
.string "Avarage Array: \n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1096, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %rbx
leaq 560(%rsp), %r13
movl $0, %ebp
leaq .LC1(%rip), %r12
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %ebp, %xmm0
movss %xmm0, (%rbx)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $2, %ebp
addq $4, %rbx
cmpq %r13, %rbx
jne .L12
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $512, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 16(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 560(%rsp), %rbx
movl $2, %ecx
movl $512, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 1072(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $1096, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12avarage_listPfS_PfS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12avarage_listPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12avarage_listPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memory_examples.hip"
.globl _Z27__device_stub__avarage_listPfS_ # -- Begin function _Z27__device_stub__avarage_listPfS_
.p2align 4, 0x90
.type _Z27__device_stub__avarage_listPfS_,@function
_Z27__device_stub__avarage_listPfS_: # @_Z27__device_stub__avarage_listPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12avarage_listPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__avarage_listPfS_, .Lfunc_end0-_Z27__device_stub__avarage_listPfS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 1120
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 592(%rsp,%rbx,2)
xorps %xmm0, %xmm0
cvtsi2sd %ebx, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
addq $2, %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 8(%rsp), %rdi
leaq 592(%rsp), %rsi
movl $512, %edx # imm = 0x200
movl $1, %ecx
callq hipMemcpy
movq %rsp, %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12avarage_listPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $512, %edx # imm = 0x200
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movss 80(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %rbx
cmpq $128, %rbx
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $1104, %rsp # imm = 0x450
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12avarage_listPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12avarage_listPfS_,@object # @_Z12avarage_listPfS_
.section .rodata,"a",@progbits
.globl _Z12avarage_listPfS_
.p2align 3, 0x0
_Z12avarage_listPfS_:
.quad _Z27__device_stub__avarage_listPfS_
.size _Z12avarage_listPfS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%.2f "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12avarage_listPfS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Array Values : "
.size .Lstr, 16
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Avarage Array: "
.size .Lstr.1, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__avarage_listPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12avarage_listPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #ifdef __cplusplus
extern "C" {
#endif
__global__ void mandelbrot(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y < hauteur && x < largeur)
{
int cpt = 0;
float x1 = 0.;
float y1 = 0.;
float x2 = 0.;
float y2 = 0.;
float a = 4. * x / largeur - 2.;
float b = 4. * y / hauteur - 2.;
float val = x1* x1 + y1 * y1;
while (cpt < N && val <= 4.)
{
cpt ++;
x2 = x1* x1 - y1 * y1 + a;
y2 = 2. * x1 * y1 + b;
x1 = x2;
y1 = y2;
val = x1* x1 + y1 * y1;
}
A[y*hauteur+x] = cpt;
}
}
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
}
#ifdef __cplusplus
}
#endif | code for sm_80
Function : game
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R4, RZ ; /* 0x0000000403037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R2, R7, R5, R4 ; /* 0x0000000507027224 */
/* 0x000fca00078e0204 */
/*0110*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a07 */
/*0130*/ @!P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103039810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f46270 */
/*0180*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*0190*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0003 */
/*01a0*/ @!P2 IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff08a224 */
/* 0x000fe200078e0a08 */
/*01b0*/ @!P1 LOP3.LUT R8, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff089a12 */
/* 0x000fca00078e33ff */
/*01c0*/ IMAD.MOV R3, RZ, RZ, -R8 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a08 */
/*01d0*/ IMAD R14, R3, c[0x0][0x16c], R0 ; /* 0x00005b00030e7a24 */
/* 0x000fca00078e0200 */
/*01e0*/ ISETP.GE.AND P0, PT, R14, c[0x0][0x16c], PT ; /* 0x00005b000e007a0c */
/* 0x000fc80003f06270 */
/*01f0*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x170], P0 ; /* 0x00005c0008007a0c */
/* 0x000fda0000706670 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ ULDC UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000800 */
/*0220*/ ISETP.GE.AND P2, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe20003f46270 */
/*0230*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0240*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fe200078e00ff */
/*0250*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff077624 */
/* 0x000fe200078e00ff */
/*0270*/ ISETP.GE.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f06270 */
/*0280*/ IMAD.WIDE R2, R0, R15, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fe200078e020f */
/*0290*/ ISETP.GE.AND P3, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fe2000bf66270 */
/*02a0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*02b0*/ IADD3 R11, R7, -0x1, RZ ; /* 0xffffffff070b7810 */
/* 0x000fe20007ffe0ff */
/*02c0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*02d0*/ @P2 IADD3 R4, R0, -c[0x0][0x16c], RZ ; /* 0x80005b0000042a10 */
/* 0x000fe40007ffe0ff */
/*02e0*/ ISETP.GE.AND P1, PT, R14, R11, PT ; /* 0x0000000b0e00720c */
/* 0x000fc60003f26270 */
/*02f0*/ @P2 IMAD.WIDE R4, R4, R15, c[0x0][0x160] ; /* 0x0000580004042625 */
/* 0x000fe200078e020f */
/*0300*/ ULDC UR5, c[0x0][0x16c] ; /* 0x00005b0000057ab9 */
/* 0x000fc60000000800 */
/*0310*/ @!P3 IMAD.WIDE R6, R7, 0x4, R2 ; /* 0x000000040706b825 */
/* 0x000fe200078e0202 */
/*0320*/ @P2 LDG.E R12, [R4.64] ; /* 0x00000006040c2981 */
/* 0x0000a2000c1e1900 */
/*0330*/ ISETP.GE.OR P2, PT, R8.reuse, UR4, P1 ; /* 0x0000000408007c0c */
/* 0x040fe20008f46670 */
/*0340*/ ULOP3.LUT UR5, URZ, UR5, URZ, 0x33, !UPT ; /* 0x000000053f057292 */
/* 0x000fe2000f8e333f */
/*0350*/ ISETP.LT.OR P4, PT, R8.reuse, 0x1, !P0 ; /* 0x000000010800780c */
/* 0x040fe20004781670 */
/*0360*/ @!P3 LDG.E R10, [R6.64] ; /* 0x00000006060ab981 */
/* 0x0002e2000c1e1900 */
/*0370*/ ISETP.GE.OR P3, PT, R8, UR4, !P0 ; /* 0x0000000408007c0c */
/* 0x000fe2000c766670 */
/*0380*/ IMAD.IADD R11, R0, 0x1, R11 ; /* 0x00000001000b7824 */
/* 0x000fe200078e020b */
/*0390*/ ISETP.LT.OR P5, PT, R8, 0x1, P1 ; /* 0x000000010800780c */
/* 0x000fe40000fa1670 */
/*03a0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*03b0*/ IADD3 R0, R0, UR5, RZ ; /* 0x0000000500007c10 */
/* 0x000fe2000fffe0ff */
/*03c0*/ IMAD.WIDE R4, R11, R15, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x001fc800078e020f */
/*03d0*/ @P0 LDG.E R9, [R2.64+-0x4] ; /* 0xfffffc0602090981 */
/* 0x000ea2000c1e1900 */
/*03e0*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc600078e00ff */
/*03f0*/ @!P1 LDG.E R8, [R2.64+0x4] ; /* 0x0000040602089981 */
/* 0x000ea2000c1e1900 */
/*0400*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe400078e00ff */
/*0410*/ IMAD.WIDE R6, R0, R15, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x002fe200078e020f */
/*0420*/ @!P2 LDG.E R13, [R4.64+0x8] ; /* 0x00000806040da981 */
/* 0x000ee6000c1e1900 */
/*0430*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0440*/ @!P3 LDG.E R11, [R4.64] ; /* 0x00000006040bb981 */
/* 0x000f28000c1e1900 */
/*0450*/ @!P4 LDG.E R16, [R6.64] ; /* 0x000000060610c981 */
/* 0x000f28000c1e1900 */
/*0460*/ @!P5 LDG.E R14, [R6.64+0x8] ; /* 0x00000806060ed981 */
/* 0x000f68000c1e1900 */
/*0470*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000f62000c1e1900 */
/*0480*/ IADD3 R8, R12, R8, R9 ; /* 0x000000080c087210 */
/* 0x004fc80007ffe009 */
/*0490*/ IADD3 R8, R13, R8, R10 ; /* 0x000000080d087210 */
/* 0x008fc80007ffe00a */
/*04a0*/ IADD3 R11, R16, R8, R11 ; /* 0x00000008100b7210 */
/* 0x010fca0007ffe00b */
/*04b0*/ IMAD.IADD R11, R11, 0x1, R14 ; /* 0x000000010b0b7824 */
/* 0x020fca00078e020e */
/*04c0*/ ISETP.GE.AND P0, PT, R11, 0x2, PT ; /* 0x000000020b00780c */
/* 0x000fc80003f06270 */
/*04d0*/ ISETP.EQ.AND P0, PT, R0, 0x1, !P0 ; /* 0x000000010000780c */
/* 0x000fc80004702270 */
/*04e0*/ ISETP.GT.OR P0, PT, R11, 0x3, P0 ; /* 0x000000030b00780c */
/* 0x000fda0000704670 */
/*04f0*/ @P0 BRA 0x560 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.NE.AND P0, PT, R11, 0x3, PT ; /* 0x000000030b00780c */
/* 0x000fc80003f05270 */
/*0510*/ ISETP.NE.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000705670 */
/*0520*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fca00078e00ff */
/*0540*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0550*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0560*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101906 */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ BRA 0x580; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : mandelbrot
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x170] ; /* 0x00005c0000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R4, R0 ; /* 0x0000000000047213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fc800078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R13, R3, R4, RZ ; /* 0x00000004030d7227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a0d */
/*0100*/ IMAD R2, R7, R3, R4 ; /* 0x0000000307027224 */
/* 0x000fca00078e0204 */
/*0110*/ ISETP.GT.U32.AND P1, PT, R7, R2, PT ; /* 0x000000020700720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IMAD.IADD R2, R2, 0x1, -R7 ; /* 0x0000000102029824 */
/* 0x000fe200078e0a07 */
/*0130*/ @!P1 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d9810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f25270 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R2, R7, PT ; /* 0x000000070200720c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R2, R0, c[0x0][0x170], RZ, 0x3c, !PT ; /* 0x00005c0000027a12 */
/* 0x000fc800078e3cff */
/*0170*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fce0003f46270 */
/*0180*/ @P0 IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d0810 */
/* 0x000fcc0007ffe0ff */
/*0190*/ @!P2 IMAD.MOV R13, RZ, RZ, -R13 ; /* 0x000000ffff0da224 */
/* 0x000fe200078e0a0d */
/*01a0*/ @!P1 LOP3.LUT R13, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff0d9a12 */
/* 0x000fca00078e33ff */
/*01b0*/ IMAD.MOV R3, RZ, RZ, -R13 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a0d */
/*01c0*/ IMAD R0, R3, c[0x0][0x16c], R0 ; /* 0x00005b0003007a24 */
/* 0x000fca00078e0200 */
/*01d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x16c], PT ; /* 0x00005b0000007a0c */
/* 0x000fc80003f06270 */
/*01e0*/ ISETP.GE.OR P0, PT, R13, c[0x0][0x170], P0 ; /* 0x00005c000d007a0c */
/* 0x000fda0000706670 */
/*01f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0210*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0220*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc600078e00ff */
/*0230*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0240*/ @!P0 BRA 0x6d0 ; /* 0x0000048000008947 */
/* 0x000fea0003800000 */
/*0250*/ I2F.F64 R4, c[0x0][0x170] ; /* 0x00005c0000047b12 */
/* 0x000e220000201c00 */
/*0260*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe200078e00ff */
/*0270*/ BSSY B0, 0x3d0 ; /* 0x0000015000007945 */
/* 0x000fec0003800000 */
/*0280*/ MUFU.RCP64H R7, R5 ; /* 0x0000000500077308 */
/* 0x001e240000001800 */
/*0290*/ DFMA R2, -R4, R6, 1 ; /* 0x3ff000000402742b */
/* 0x001e0c0000000106 */
/*02a0*/ DFMA R8, R2, R2, R2 ; /* 0x000000020208722b */
/* 0x0010480000000002 */
/*02b0*/ I2F.F64 R2, R13 ; /* 0x0000000d00027312 */
/* 0x001e240000201c00 */
/*02c0*/ DFMA R8, R6, R8, R6 ; /* 0x000000080608722b */
/* 0x002e4c0000000006 */
/*02d0*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x002e4c0000000108 */
/*02e0*/ DFMA R6, R8, R6, R8 ; /* 0x000000060806722b */
/* 0x002fc80000000008 */
/*02f0*/ DMUL R10, R2, 4 ; /* 0x40100000020a7828 */
/* 0x001e0c0000000000 */
/*0300*/ DMUL R2, R10, R6 ; /* 0x000000060a027228 */
/* 0x001e080000000000 */
/*0310*/ FSETP.GEU.AND P1, PT, |R11|, 6.5827683646048100446e-37, PT ; /* 0x036000000b00780b */
/* 0x000fe40003f2e200 */
/*0320*/ DFMA R8, -R4, R2, R10 ; /* 0x000000020408722b */
/* 0x001e0c000000010a */
/*0330*/ DFMA R2, R6, R8, R2 ; /* 0x000000080602722b */
/* 0x001e140000000002 */
/*0340*/ FFMA R6, RZ, R5, R3 ; /* 0x00000005ff067223 */
/* 0x001fca0000000003 */
/*0350*/ FSETP.GT.AND P0, PT, |R6|, 1.469367938527859385e-39, PT ; /* 0x001000000600780b */
/* 0x000fda0003f04200 */
/*0360*/ @P0 BRA P1, 0x3c0 ; /* 0x0000005000000947 */
/* 0x000fea0000800000 */
/*0370*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0005 */
/*0380*/ MOV R12, 0x3a0 ; /* 0x000003a0000c7802 */
/* 0x000fe40000000f00 */
/*0390*/ CALL.REL.NOINC 0x720 ; /* 0x0000038000007944 */
/* 0x000fea0003c00000 */
/*03a0*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000a */
/*03b0*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*03c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03d0*/ I2F.F64 R4, c[0x0][0x16c] ; /* 0x00005b0000047b12 */
/* 0x000e220000201c00 */
/*03e0*/ IMAD.MOV.U32 R8, RZ, RZ, 0x1 ; /* 0x00000001ff087424 */
/* 0x000fe200078e00ff */
/*03f0*/ BSSY B0, 0x580 ; /* 0x0000018000007945 */
/* 0x000fec0003800000 */
/*0400*/ MUFU.RCP64H R9, R5 ; /* 0x0000000500097308 */
/* 0x001e240000001800 */
/*0410*/ DFMA R6, -R4, R8, 1 ; /* 0x3ff000000406742b */
/* 0x001e0c0000000108 */
/*0420*/ DFMA R10, R6, R6, R6 ; /* 0x00000006060a722b */
/* 0x0010480000000006 */
/*0430*/ I2F.F64 R6, R0 ; /* 0x0000000000067312 */
/* 0x001e240000201c00 */
/*0440*/ DFMA R10, R8, R10, R8 ; /* 0x0000000a080a722b */
/* 0x002e4c0000000008 */
/*0450*/ DFMA R8, -R4, R10, 1 ; /* 0x3ff000000408742b */
/* 0x002e4c000000010a */
/*0460*/ DFMA R10, R10, R8, R10 ; /* 0x000000080a0a722b */
/* 0x002fc8000000000a */
/*0470*/ DMUL R6, R6, 4 ; /* 0x4010000006067828 */
/* 0x001e080000000000 */
/*0480*/ DADD R8, R2, -2 ; /* 0xc000000002087429 */
/* 0x000fc80000000000 */
/*0490*/ DMUL R14, R6, R10 ; /* 0x0000000a060e7228 */
/* 0x001e240000000000 */
/*04a0*/ FSETP.GEU.AND P1, PT, |R7|, 6.5827683646048100446e-37, PT ; /* 0x036000000700780b */
/* 0x000fc80003f2e200 */
/*04b0*/ DFMA R2, -R4, R14, R6 ; /* 0x0000000e0402722b */
/* 0x001e220000000106 */
/*04c0*/ F2F.F32.F64 R8, R8 ; /* 0x0000000800087310 */
/* 0x000e6a0000301000 */
/*04d0*/ DFMA R10, R10, R2, R14 ; /* 0x000000020a0a722b */
/* 0x001e14000000000e */
/*04e0*/ FFMA R12, RZ, R5, R11 ; /* 0x00000005ff0c7223 */
/* 0x001fe2000000000b */
/*04f0*/ F2F.F64.F32 R2, R8 ; /* 0x0000000800027310 */
/* 0x0020680000201800 */
/*0500*/ FSETP.GT.AND P0, PT, |R12|, 1.469367938527859385e-39, PT ; /* 0x001000000c00780b */
/* 0x000fda0003f04200 */
/*0510*/ @P0 BRA P1, 0x570 ; /* 0x0000005000000947 */
/* 0x000fea0000800000 */
/*0520*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x003fe200078e0006 */
/*0530*/ MOV R12, 0x570 ; /* 0x00000570000c7802 */
/* 0x000fe20000000f00 */
/*0540*/ IMAD.MOV.U32 R11, RZ, RZ, R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0007 */
/*0550*/ IMAD.MOV.U32 R9, RZ, RZ, R5 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0005 */
/*0560*/ CALL.REL.NOINC 0x720 ; /* 0x000001b000007944 */
/* 0x000fea0003c00000 */
/*0570*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x003fea0003800000 */
/*0580*/ DADD R10, R10, -2 ; /* 0xc00000000a0a7429 */
/* 0x000e220000000000 */
/*0590*/ BSSY B0, 0x6d0 ; /* 0x0000013000007945 */
/* 0x000fe20003800000 */
/*05a0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*05b0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fce00078e00ff */
/*05c0*/ F2F.F32.F64 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x0010640000301000 */
/*05d0*/ F2F.F64.F32 R4, R12 ; /* 0x0000000c00047310 */
/* 0x000ea20000201800 */
/*05e0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc80007ffe0ff */
/*05f0*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x168], PT ; /* 0x00005a0009007a0c */
/* 0x000fc60003f06270 */
/*0600*/ F2F.F64.F32 R6, R8 ; /* 0x0000000800067310 */
/* 0x000ee20000201800 */
/*0610*/ DADD R4, R4, R4 ; /* 0x0000000004047229 */
/* 0x004ecc0000000004 */
/*0620*/ DFMA R4, R4, R6, R2 ; /* 0x000000060404722b */
/* 0x0084e40000000002 */
/*0630*/ FMUL R7, R8, R8 ; /* 0x0000000808077220 */
/* 0x004fc80000400000 */
/*0640*/ F2F.F32.F64 R8, R4 ; /* 0x0000000400087310 */
/* 0x008ea20000301000 */
/*0650*/ FFMA R7, R12, R12, -R7 ; /* 0x0000000c0c077223 */
/* 0x000fc80000000807 */
/*0660*/ FADD R7, R10, R7 ; /* 0x000000070a077221 */
/* 0x002fc80000000000 */
/*0670*/ IMAD.MOV.U32 R12, RZ, RZ, R7 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0007 */
/*0680*/ FMUL R6, R8, R8 ; /* 0x0000000808067220 */
/* 0x004fc80000400000 */
/*0690*/ FFMA R6, R7, R7, R6 ; /* 0x0000000707067223 */
/* 0x000fca0000000006 */
/*06a0*/ FSETP.LE.AND P1, PT, R6, 4, PT ; /* 0x408000000600780b */
/* 0x000fda0003f23000 */
/*06b0*/ @!P0 BRA P1, 0x5d0 ; /* 0xffffff1000008947 */
/* 0x000fea000083ffff */
/*06c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*06e0*/ IMAD R2, R13, c[0x0][0x170], R0 ; /* 0x00005c000d027a24 */
/* 0x000fc800078e0200 */
/*06f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0700*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0710*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0720*/ FSETP.GEU.AND P0, PT, |R9|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000900780b */
/* 0x040fe20003f0e200 */
/*0730*/ IMAD.MOV.U32 R8, RZ, RZ, R4.reuse ; /* 0x000000ffff087224 */
/* 0x100fe200078e0004 */
/*0740*/ LOP3.LUT R6, R9, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff09067812 */
/* 0x000fe200078ec0ff */
/*0750*/ IMAD.MOV.U32 R15, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0f7424 */
/* 0x000fe200078e00ff */
/*0760*/ FSETP.GEU.AND P2, PT, |R11|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000b00780b */
/* 0x040fe20003f4e200 */
/*0770*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0780*/ LOP3.LUT R7, R6, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000006077812 */
/* 0x000fe200078efcff */
/*0790*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0004 */
/*07a0*/ LOP3.LUT R14, R11, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000b0e7812 */
/* 0x000fe200078ec0ff */
/*07b0*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000a */
/*07c0*/ LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009157812 */
/* 0x000fe200078ec0ff */
/*07d0*/ BSSY B1, 0xcd0 ; /* 0x000004f000017945 */
/* 0x000fe40003800000 */
/*07e0*/ @!P0 DMUL R6, R8, 8.98846567431157953865e+307 ; /* 0x7fe0000008068828 */
/* 0x000e220000000000 */
/*07f0*/ ISETP.GE.U32.AND P1, PT, R14, R21, PT ; /* 0x000000150e00720c */
/* 0x000fc60003f26070 */
/*0800*/ @!P2 LOP3.LUT R5, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000905a812 */
/* 0x000fe200078ec0ff */
/*0810*/ @!P2 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff10a224 */
/* 0x000fe200078e00ff */
/*0820*/ MUFU.RCP64H R19, R7 ; /* 0x0000000700137308 */
/* 0x001e240000001800 */
/*0830*/ @!P2 ISETP.GE.U32.AND P3, PT, R14, R5, PT ; /* 0x000000050e00a20c */
/* 0x000fe40003f66070 */
/*0840*/ SEL R5, R15.reuse, 0x63400000, !P1 ; /* 0x634000000f057807 */
/* 0x040fe40004800000 */
/*0850*/ @!P2 SEL R17, R15, 0x63400000, !P3 ; /* 0x634000000f11a807 */
/* 0x000fe40005800000 */
/*0860*/ LOP3.LUT R5, R5, 0x800fffff, R11, 0xf8, !PT ; /* 0x800fffff05057812 */
/* 0x000fc400078ef80b */
/*0870*/ @!P2 LOP3.LUT R17, R17, 0x80000000, R11, 0xf8, !PT ; /* 0x800000001111a812 */
/* 0x000fc800078ef80b */
/*0880*/ @!P2 LOP3.LUT R17, R17, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001111a812 */
/* 0x000fe200078efcff */
/*0890*/ DFMA R22, R18, -R6, 1 ; /* 0x3ff000001216742b */
/* 0x001e0a0000000806 */
/*08a0*/ @!P2 DFMA R4, R4, 2, -R16 ; /* 0x400000000404a82b */
/* 0x000fc80000000810 */
/*08b0*/ DFMA R22, R22, R22, R22 ; /* 0x000000161616722b */
/* 0x001e0c0000000016 */
/*08c0*/ DFMA R22, R18, R22, R18 ; /* 0x000000161216722b */
/* 0x0010640000000012 */
/*08d0*/ IMAD.MOV.U32 R18, RZ, RZ, R14 ; /* 0x000000ffff127224 */
/* 0x001fe200078e000e */
/*08e0*/ @!P2 LOP3.LUT R18, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000512a812 */
/* 0x000fe200078ec0ff */
/*08f0*/ IMAD.MOV.U32 R19, RZ, RZ, R21 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0015 */
/*0900*/ @!P0 LOP3.LUT R19, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007138812 */
/* 0x000fe200078ec0ff */
/*0910*/ DFMA R16, R22, -R6, 1 ; /* 0x3ff000001610742b */
/* 0x002e060000000806 */
/*0920*/ IADD3 R24, R19, -0x1, RZ ; /* 0xffffffff13187810 */
/* 0x000fc60007ffe0ff */
/*0930*/ DFMA R16, R22, R16, R22 ; /* 0x000000101610722b */
/* 0x0010640000000016 */
/*0940*/ IADD3 R22, R18, -0x1, RZ ; /* 0xffffffff12167810 */
/* 0x001fc80007ffe0ff */
/*0950*/ ISETP.GT.U32.AND P0, PT, R22, 0x7feffffe, PT ; /* 0x7feffffe1600780c */
/* 0x000fe20003f04070 */
/*0960*/ DMUL R20, R16, R4 ; /* 0x0000000410147228 */
/* 0x002e060000000000 */
/*0970*/ ISETP.GT.U32.OR P0, PT, R24, 0x7feffffe, P0 ; /* 0x7feffffe1800780c */
/* 0x000fc60000704470 */
/*0980*/ DFMA R22, R20, -R6, R4 ; /* 0x800000061416722b */
/* 0x001e0c0000000004 */
/*0990*/ DFMA R16, R16, R22, R20 ; /* 0x000000161010722b */
/* 0x0010480000000014 */
/*09a0*/ @P0 BRA 0xb70 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*09b0*/ LOP3.LUT R11, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000090b7812 */
/* 0x003fc800078ec0ff */
/*09c0*/ ISETP.GE.U32.AND P0, PT, R14.reuse, R11, PT ; /* 0x0000000b0e00720c */
/* 0x040fe20003f06070 */
/*09d0*/ IMAD.IADD R10, R14, 0x1, -R11 ; /* 0x000000010e0a7824 */
/* 0x000fc600078e0a0b */
/*09e0*/ SEL R15, R15, 0x63400000, !P0 ; /* 0x634000000f0f7807 */
/* 0x000fe40004000000 */
/*09f0*/ IMNMX R10, R10, -0x46a00000, !PT ; /* 0xb96000000a0a7817 */
/* 0x000fc80007800200 */
/*0a00*/ IMNMX R10, R10, 0x46a00000, PT ; /* 0x46a000000a0a7817 */
/* 0x000fca0003800200 */
/*0a10*/ IMAD.IADD R18, R10, 0x1, -R15 ; /* 0x000000010a127824 */
/* 0x000fe400078e0a0f */
/*0a20*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fc600078e00ff */
/*0a30*/ IADD3 R11, R18, 0x7fe00000, RZ ; /* 0x7fe00000120b7810 */
/* 0x000fcc0007ffe0ff */
/*0a40*/ DMUL R14, R16, R10 ; /* 0x0000000a100e7228 */
/* 0x000e140000000000 */
/*0a50*/ FSETP.GTU.AND P0, PT, |R15|, 1.469367938527859385e-39, PT ; /* 0x001000000f00780b */
/* 0x001fda0003f0c200 */
/*0a60*/ @P0 BRA 0xcc0 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0a70*/ DFMA R4, R16, -R6, R4 ; /* 0x800000061004722b */
/* 0x000e220000000004 */
/*0a80*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fd200078e00ff */
/*0a90*/ FSETP.NEU.AND P0, PT, R5.reuse, RZ, PT ; /* 0x000000ff0500720b */
/* 0x041fe40003f0d000 */
/*0aa0*/ LOP3.LUT R9, R5, 0x80000000, R9, 0x48, !PT ; /* 0x8000000005097812 */
/* 0x000fc800078e4809 */
/*0ab0*/ LOP3.LUT R11, R9, R11, RZ, 0xfc, !PT ; /* 0x0000000b090b7212 */
/* 0x000fce00078efcff */
/*0ac0*/ @!P0 BRA 0xcc0 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0ad0*/ IMAD.MOV R5, RZ, RZ, -R18 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0a12 */
/*0ae0*/ DMUL.RP R10, R16, R10 ; /* 0x0000000a100a7228 */
/* 0x000e220000008000 */
/*0af0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fcc00078e00ff */
/*0b00*/ DFMA R4, R14, -R4, R16 ; /* 0x800000040e04722b */
/* 0x000e460000000010 */
/*0b10*/ LOP3.LUT R9, R11, R9, RZ, 0x3c, !PT ; /* 0x000000090b097212 */
/* 0x001fc600078e3cff */
/*0b20*/ IADD3 R4, -R18, -0x43300000, RZ ; /* 0xbcd0000012047810 */
/* 0x002fc80007ffe1ff */
/*0b30*/ FSETP.NEU.AND P0, PT, |R5|, R4, PT ; /* 0x000000040500720b */
/* 0x000fc80003f0d200 */
/*0b40*/ FSEL R14, R10, R14, !P0 ; /* 0x0000000e0a0e7208 */
/* 0x000fe40004000000 */
/*0b50*/ FSEL R15, R9, R15, !P0 ; /* 0x0000000f090f7208 */
/* 0x000fe20004000000 */
/*0b60*/ BRA 0xcc0 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0b70*/ DSETP.NAN.AND P0, PT, R10, R10, PT ; /* 0x0000000a0a00722a */
/* 0x003e1c0003f08000 */
/*0b80*/ @P0 BRA 0xca0 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0b90*/ DSETP.NAN.AND P0, PT, R8, R8, PT ; /* 0x000000080800722a */
/* 0x000e1c0003f08000 */
/*0ba0*/ @P0 BRA 0xc70 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0bb0*/ ISETP.NE.AND P0, PT, R18, R19, PT ; /* 0x000000131200720c */
/* 0x000fe20003f05270 */
/*0bc0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fe400078e00ff */
/*0bd0*/ IMAD.MOV.U32 R15, RZ, RZ, -0x80000 ; /* 0xfff80000ff0f7424 */
/* 0x000fd400078e00ff */
/*0be0*/ @!P0 BRA 0xcc0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bf0*/ ISETP.NE.AND P0, PT, R18, 0x7ff00000, PT ; /* 0x7ff000001200780c */
/* 0x000fe40003f05270 */
/*0c00*/ LOP3.LUT R15, R11, 0x80000000, R9, 0x48, !PT ; /* 0x800000000b0f7812 */
/* 0x000fe400078e4809 */
/*0c10*/ ISETP.EQ.OR P0, PT, R19, RZ, !P0 ; /* 0x000000ff1300720c */
/* 0x000fda0004702670 */
/*0c20*/ @P0 LOP3.LUT R4, R15, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000f040812 */
/* 0x000fe200078efcff */
/*0c30*/ @!P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e8224 */
/* 0x000fe400078e00ff */
/*0c40*/ @P0 IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e0224 */
/* 0x000fe400078e00ff */
/*0c50*/ @P0 IMAD.MOV.U32 R15, RZ, RZ, R4 ; /* 0x000000ffff0f0224 */
/* 0x000fe200078e0004 */
/*0c60*/ BRA 0xcc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R15, R9, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000090f7812 */
/* 0x000fe200078efcff */
/*0c80*/ IMAD.MOV.U32 R14, RZ, RZ, R8 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0008 */
/*0c90*/ BRA 0xcc0 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0ca0*/ LOP3.LUT R15, R11, 0x80000, RZ, 0xfc, !PT ; /* 0x000800000b0f7812 */
/* 0x000fe200078efcff */
/*0cb0*/ IMAD.MOV.U32 R14, RZ, RZ, R10 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e000a */
/*0cc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0cd0*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*0ce0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc400078e00ff */
/*0cf0*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e000e */
/*0d00*/ IMAD.MOV.U32 R11, RZ, RZ, R15 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e000f */
/*0d10*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff2e004007950 */
/* 0x000fec0003c3ffff */
/*0d20*/ BRA 0xd20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #ifdef __cplusplus
extern "C" {
#endif
__global__ void mandelbrot(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y < hauteur && x < largeur)
{
int cpt = 0;
float x1 = 0.;
float y1 = 0.;
float x2 = 0.;
float y2 = 0.;
float a = 4. * x / largeur - 2.;
float b = 4. * y / hauteur - 2.;
float val = x1* x1 + y1 * y1;
while (cpt < N && val <= 4.)
{
cpt ++;
x2 = x1* x1 - y1 * y1 + a;
y2 = 2. * x1 * y1 + b;
x1 = x2;
y1 = y2;
val = x1* x1 + y1 * y1;
}
A[y*hauteur+x] = cpt;
}
}
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
}
#ifdef __cplusplus
}
#endif | .file "tmpxft_000fffa4_00000000-6_Game.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10mandelbrotPiiiiPiiii
.type _Z33__device_stub__Z10mandelbrotPiiiiPiiii, @function
_Z33__device_stub__Z10mandelbrotPiiiiPiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq mandelbrot(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10mandelbrotPiiiiPiiii, .-_Z33__device_stub__Z10mandelbrotPiiiiPiiii
.globl mandelbrot
.type mandelbrot, @function
mandelbrot:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10mandelbrotPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mandelbrot, .-mandelbrot
.globl _Z26__device_stub__Z4gamePiiiiPiiii
.type _Z26__device_stub__Z4gamePiiiiPiiii, @function
_Z26__device_stub__Z4gamePiiiiPiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq game(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z26__device_stub__Z4gamePiiiiPiiii, .-_Z26__device_stub__Z4gamePiiiiPiiii
.globl game
.type game, @function
game:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4gamePiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size game, .-game
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "game"
.LC1:
.string "mandelbrot"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq game(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq mandelbrot(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #ifdef __cplusplus
extern "C" {
#endif
__global__ void mandelbrot(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y < hauteur && x < largeur)
{
int cpt = 0;
float x1 = 0.;
float y1 = 0.;
float x2 = 0.;
float y2 = 0.;
float a = 4. * x / largeur - 2.;
float b = 4. * y / hauteur - 2.;
float val = x1* x1 + y1 * y1;
while (cpt < N && val <= 4.)
{
cpt ++;
x2 = x1* x1 - y1 * y1 + a;
y2 = 2. * x1 * y1 + b;
x1 = x2;
y1 = y2;
val = x1* x1 + y1 * y1;
}
A[y*hauteur+x] = cpt;
}
}
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
}
#ifdef __cplusplus
}
#endif | #include <hip/hip_runtime.h>
#ifdef __cplusplus
extern "C" {
#endif
__global__ void mandelbrot(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y < hauteur && x < largeur)
{
int cpt = 0;
float x1 = 0.;
float y1 = 0.;
float x2 = 0.;
float y2 = 0.;
float a = 4. * x / largeur - 2.;
float b = 4. * y / hauteur - 2.;
float val = x1* x1 + y1 * y1;
while (cpt < N && val <= 4.)
{
cpt ++;
x2 = x1* x1 - y1 * y1 + a;
y2 = 2. * x1 * y1 + b;
x1 = x2;
y1 = y2;
val = x1* x1 + y1 * y1;
}
A[y*hauteur+x] = cpt;
}
}
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
}
#ifdef __cplusplus
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#ifdef __cplusplus
extern "C" {
#endif
__global__ void mandelbrot(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y < hauteur && x < largeur)
{
int cpt = 0;
float x1 = 0.;
float y1 = 0.;
float x2 = 0.;
float y2 = 0.;
float a = 4. * x / largeur - 2.;
float b = 4. * y / hauteur - 2.;
float val = x1* x1 + y1 * y1;
while (cpt < N && val <= 4.)
{
cpt ++;
x2 = x1* x1 - y1 * y1 + a;
y2 = 2. * x1 * y1 + b;
x1 = x2;
y1 = y2;
val = x1* x1 + y1 * y1;
}
A[y*hauteur+x] = cpt;
}
}
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
}
#ifdef __cplusplus
}
#endif | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected mandelbrot
.globl mandelbrot
.p2align 8
.type mandelbrot,@function
mandelbrot:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0xc
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s5, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s6, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s3
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s6
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s3, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s6
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v3
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s6, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v2
v_mul_lo_u32 v0, v3, s4
v_cmp_gt_i32_e32 vcc_lo, s5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v1, v0
v_cmp_gt_i32_e64 s2, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_7
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_5
v_cvt_f64_i32_e32 v[1:2], v0
v_cvt_f64_i32_e32 v[4:5], v3
v_cvt_f64_i32_e32 v[6:7], s4
v_cvt_f64_i32_e32 v[8:9], s5
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f64 v[1:2], v[1:2], 4.0
v_mul_f64 v[4:5], v[4:5], 4.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[1:2]
v_div_scale_f64 v[12:13], null, v[8:9], v[8:9], v[4:5]
v_div_scale_f64 v[22:23], vcc_lo, v[1:2], v[6:7], v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f64_e32 v[14:15], v[10:11]
v_rcp_f64_e32 v[16:17], v[12:13]
s_waitcnt_depctr 0xfff
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
v_fma_f64 v[20:21], -v[12:13], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
v_div_scale_f64 v[18:19], s2, v[4:5], v[8:9], v[4:5]
v_fma_f64 v[16:17], v[16:17], v[20:21], v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[20:21], v[22:23], v[14:15]
v_mul_f64 v[24:25], v[18:19], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], -v[10:11], v[20:21], v[22:23]
v_fma_f64 v[12:13], -v[12:13], v[24:25], v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[20:21]
s_mov_b32 vcc_lo, s2
s_mov_b32 s2, 0
v_div_fmas_f64 v[12:13], v[12:13], v[16:17], v[24:25]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[1:2], v[10:11], v[6:7], v[1:2]
v_mov_b32_e32 v7, 0
v_div_fixup_f64 v[4:5], v[12:13], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[1:2], v[1:2], -2.0
v_add_f64 v[4:5], v[4:5], -2.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f32_f64_e32 v5, v[4:5]
v_cvt_f32_f64_e32 v4, v[1:2]
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f64_f32_e32 v[1:2], v5
v_mov_b32_e32 v5, 0
.p2align 6
.LBB0_3:
v_cvt_f64_f32_e32 v[8:9], v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cvt_f64_f32_e32 v[10:11], v5
v_mul_f32_e32 v6, v5, v5
s_add_i32 s4, s4, 1
s_cmp_ge_i32 s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v6, v7, v7, -v6
s_cselect_b32 s6, -1, 0
v_add_f64 v[8:9], v[8:9], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[1:2]
v_cvt_f32_f64_e32 v5, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v6, v4 :: v_dual_mul_f32 v6, v5, v5
v_fmac_f32_e32 v6, v7, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_nge_f32_e32 vcc_lo, 4.0, v6
v_mov_b32_e32 v6, s4
s_or_b32 s6, s6, vcc_lo
s_and_b32 s6, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, s6, s2
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s2
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v6, 0
.LBB0_6:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v3, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel mandelbrot
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size mandelbrot, .Lfunc_end0-mandelbrot
.section .AMDGPU.csdata,"",@progbits
.text
.protected game
.globl game
.p2align 8
.type game,@function
game:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0xc
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s5, 31
s_and_b32 s2, s2, 0xffff
s_add_i32 s6, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s6, s6, s3
v_cvt_f32_u32_e32 v1, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_sub_i32 s2, 0, s6
v_mul_lo_u32 v0, s2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_mul_hi_u32 v0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v2, v3
v_xor_b32_e32 v4, v4, v3
v_xor_b32_e32 v3, s3, v3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v1, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s6
v_sub_nc_u32_e32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s6, v1
v_cmp_le_u32_e32 vcc_lo, s6, v1
v_dual_cndmask_b32 v1, v1, v5 :: v_dual_add_nc_u32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s6, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v3
v_sub_nc_u32_e32 v5, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, v5, s4
v_cmp_gt_i32_e32 vcc_lo, s5, v5
v_sub_nc_u32_e32 v4, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_21
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_cmp_lt_i32_e64 s0, 0, v4
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v6, v[0:1], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_3
global_load_b32 v7, v[0:1], off offset:-4
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s1, s4, -1
v_mov_b32_e32 v8, 0
v_cmp_le_i32_e32 vcc_lo, s1, v4
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s1, v4
s_cbranch_execz .LBB1_5
global_load_b32 v8, v[0:1], off offset:4
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_i32_e64 s1, 0, v5
v_mov_b32_e32 v9, 0
v_subrev_nc_u32_e32 v3, s4, v2
s_delay_alu instid0(VALU_DEP_3)
s_and_saveexec_b32 s3, s1
s_cbranch_execz .LBB1_7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[9:10], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v9, s2, s6, v9
v_add_co_ci_u32_e64 v10, s2, s7, v10, s2
global_load_b32 v9, v[9:10], off
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s3
s_add_i32 s2, s5, -1
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, 0
v_cmp_gt_i32_e64 s2, s2, v5
v_add_nc_u32_e32 v4, s4, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB1_9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[11:12], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v11, s3, s6, v11
v_add_co_ci_u32_e64 v12, s3, s7, v12, s3
global_load_b32 v11, v[11:12], off
.LBB1_9:
s_or_b32 exec_lo, exec_lo, s5
s_xor_b32 s3, s2, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s3, vcc_lo, s3
s_xor_b32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s3
s_cbranch_execz .LBB1_11
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], 2, v[4:5]
v_add_co_u32 v12, s3, s6, v12
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v13, s3, s7, v13, s3
global_load_b32 v10, v[12:13], off offset:4
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s5
v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v5, 0
s_and_b32 s2, s2, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_13
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, s2, s6, v4
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s2, s7, v5, s2
global_load_b32 v5, v[4:5], off offset:-4
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s3
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s0
s_cbranch_execz .LBB1_15
v_xad_u32 v12, s4, -1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v13, 31, v12
v_lshlrev_b64 v[12:13], 2, v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
global_load_b32 v12, v[12:13], off
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s2
s_xor_b32 s0, s1, -1
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v4, 0
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s1, s0, -1
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB1_17
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v4, v[3:4], off offset:4
.LBB1_17:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v8, v7
v_cmp_eq_u32_e32 vcc_lo, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, v9, v11
v_add3_u32 v3, v3, v10, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, v12, v4
v_cmp_gt_i32_e64 s0, 2, v3
v_cmp_lt_i32_e64 s1, 3, v3
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s1, -1
s_and_saveexec_b32 s2, s0
v_cmp_eq_u32_e32 vcc_lo, 0, v6
v_cmp_eq_u32_e64 s0, 3, v3
v_mov_b32_e32 v2, 1
s_and_not1_b32 s1, s1, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_b32 s0, s0, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s1, s1, s0
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB1_21
global_store_b32 v[0:1], v2, off
.LBB1_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel game
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size game, .Lfunc_end1-game
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: mandelbrot
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: mandelbrot.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: game
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: game.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#ifdef __cplusplus
extern "C" {
#endif
__global__ void mandelbrot(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y < hauteur && x < largeur)
{
int cpt = 0;
float x1 = 0.;
float y1 = 0.;
float x2 = 0.;
float y2 = 0.;
float a = 4. * x / largeur - 2.;
float b = 4. * y / hauteur - 2.;
float val = x1* x1 + y1 * y1;
while (cpt < N && val <= 4.)
{
cpt ++;
x2 = x1* x1 - y1 * y1 + a;
y2 = 2. * x1 * y1 + b;
x1 = x2;
y1 = y2;
val = x1* x1 + y1 * y1;
}
A[y*hauteur+x] = cpt;
}
}
__global__ void game(int* A, const int N, const int largeur, const int hauteur){
int idx = blockDim.x * blockIdx.x + threadIdx.x;
int y = idx / hauteur;
int x = idx - (y * largeur);
if (y >= hauteur || x >= largeur)
return;
int me = A[idx];
int north = 0 ;
int northEast = 0;
int northWest = 0;
int south = 0;
int southEast = 0;
int southWest = 0;
int east = 0;
int west = 0;
if (x > 0)
west = A[idx -1];
if (x < largeur - 1)
east = A[idx + 1];
if (y > 0)
north = A[idx - largeur];
if (y < hauteur - 1)
south = A[idx + largeur];
if ((y < hauteur - 1) && (x < largeur - 1))
southEast = A[idx + largeur + 1];
if ((y < hauteur - 1) && (x > 0))
southWest = A[idx + largeur - 1];
if ((y > 0) && (x >0))
northWest = A[idx - largeur - 1];
if ((y > 0) && (x < largeur - 1))
northEast = A[idx - largeur + 1];
int res = north + south + east + west + northEast + northWest + southEast + southWest;
//__syncthreads();
if ((me == 1) && (res < 2) || (res > 3))
A[idx] = 0;
else
if ((me == 0) && (res == 3))
A[idx] = 1;
}
#ifdef __cplusplus
}
#endif | .text
.file "Game.hip"
.globl __device_stub__mandelbrot # -- Begin function __device_stub__mandelbrot
.p2align 4, 0x90
.type __device_stub__mandelbrot,@function
__device_stub__mandelbrot: # @__device_stub__mandelbrot
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mandelbrot, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__mandelbrot, .Lfunc_end0-__device_stub__mandelbrot
.cfi_endproc
# -- End function
.globl __device_stub__game # -- Begin function __device_stub__game
.p2align 4, 0x90
.type __device_stub__game,@function
__device_stub__game: # @__device_stub__game
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $game, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__game, .Lfunc_end1-__device_stub__game
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mandelbrot, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $game, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type mandelbrot,@object # @mandelbrot
.section .rodata,"a",@progbits
.globl mandelbrot
.p2align 3, 0x0
mandelbrot:
.quad __device_stub__mandelbrot
.size mandelbrot, 8
.type game,@object # @game
.globl game
.p2align 3, 0x0
game:
.quad __device_stub__game
.size game, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mandelbrot"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "game"
.size .L__unnamed_2, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mandelbrot
.addrsig_sym __device_stub__game
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mandelbrot
.addrsig_sym game
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fffa4_00000000-6_Game.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z10mandelbrotPiiiiPiiii
.type _Z33__device_stub__Z10mandelbrotPiiiiPiiii, @function
_Z33__device_stub__Z10mandelbrotPiiiiPiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq mandelbrot(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z10mandelbrotPiiiiPiiii, .-_Z33__device_stub__Z10mandelbrotPiiiiPiiii
.globl mandelbrot
.type mandelbrot, @function
mandelbrot:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z10mandelbrotPiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size mandelbrot, .-mandelbrot
.globl _Z26__device_stub__Z4gamePiiiiPiiii
.type _Z26__device_stub__Z4gamePiiiiPiiii, @function
_Z26__device_stub__Z4gamePiiiiPiiii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq game(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z26__device_stub__Z4gamePiiiiPiiii, .-_Z26__device_stub__Z4gamePiiiiPiiii
.globl game
.type game, @function
game:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4gamePiiiiPiiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size game, .-game
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "game"
.LC1:
.string "mandelbrot"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq game(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq mandelbrot(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Game.hip"
.globl __device_stub__mandelbrot # -- Begin function __device_stub__mandelbrot
.p2align 4, 0x90
.type __device_stub__mandelbrot,@function
__device_stub__mandelbrot: # @__device_stub__mandelbrot
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $mandelbrot, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__mandelbrot, .Lfunc_end0-__device_stub__mandelbrot
.cfi_endproc
# -- End function
.globl __device_stub__game # -- Begin function __device_stub__game
.p2align 4, 0x90
.type __device_stub__game,@function
__device_stub__game: # @__device_stub__game
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movl %ecx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $game, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__game, .Lfunc_end1-__device_stub__game
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $mandelbrot, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $game, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type mandelbrot,@object # @mandelbrot
.section .rodata,"a",@progbits
.globl mandelbrot
.p2align 3, 0x0
mandelbrot:
.quad __device_stub__mandelbrot
.size mandelbrot, 8
.type game,@object # @game
.globl game
.p2align 3, 0x0
game:
.quad __device_stub__game
.size game, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "mandelbrot"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "game"
.size .L__unnamed_2, 5
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__mandelbrot
.addrsig_sym __device_stub__game
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym mandelbrot
.addrsig_sym game
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <curand_kernel.h> // CURAND lib header file
#define TRIALS_PER_THREAD 1024 // Set the value for global variables
#define BLOCKS 256
#define THREADS 512
#define PI 3.1415926535 // Known value of pi, to calculate error
__global__ void pi_mc(float *estimate, curandState *states){
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
int points_in_circle = 0;
float x, y;
// Initialize CURAND
curand_init(tid, 0, 0, &states[tid]);
for(int i = 0; i < TRIALS_PER_THREAD; i++){
x = curand_uniform(&states[tid]);
y = curand_uniform(&states[tid]);
// Count if x & y is in the circle
points_in_circle += (x*x + y*y <= 1.0f);
}
estimate[tid] = 4.0f * points_in_circle / (float) TRIALS_PER_THREAD;
}
int main(int argc, char *argv[]){
float host[BLOCKS * THREADS];
float *dev;
curandState *devStates;
// Allocate memory on GPU
cudaMalloc((void **) &dev, BLOCKS * THREADS * sizeof(float));
cudaMalloc((void **) &devStates, BLOCKS * THREADS * sizeof(curandState));
// Invoke the kernel
pi_mc<<<BLOCKS, THREADS>>>(dev, devStates);
// Copy from device back to host
cudaMemcpy(host, dev, BLOCKS * THREADS * sizeof(float), cudaMemcpyDeviceToHost);
// Free the memory on GPU
cudaFree(dev);
cudaFree(devStates);
// Get the average estimate pi value among all blocks and threads, and calculate error
float pi_gpu = 0.0;
for(int i = 0; i < BLOCKS * THREADS; i++){
pi_gpu += host[i];
}
pi_gpu /= (BLOCKS * THREADS);
printf("Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n",
TRIALS_PER_THREAD, BLOCKS, THREADS);
printf("CUDA estimate of PI = %f [error of %f]\n", pi_gpu, pi_gpu - PI);
return 0;
} | code for sm_80
Function : _Z5pi_mcPfP17curandStateXORWOW
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff067424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0070*/ UMOV UR4, 0x400 ; /* 0x0000040000047882 */
/* 0x000fe20000000000 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff0b7424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff087424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x30 ; /* 0x00000030ff037424 */
/* 0x000fc600078e00ff */
/*00c0*/ LOP3.LUT R14, R0.reuse, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b49000e7812 */
/* 0x040fe200078e3cff */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0003 */
/*00e0*/ IMAD R14, R14, 0x4182bed5, RZ ; /* 0x4182bed50e0e7824 */
/* 0x000fe200078e02ff */
/*00f0*/ STG.E.64 [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x0001e6000c101b06 */
/*0100*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000e */
/*0110*/ IADD3 R5, R14.reuse, 0x75bcd15, RZ ; /* 0x075bcd150e057810 */
/* 0x040fe20007ffe0ff */
/*0120*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x0001e2000c101906 */
/*0130*/ IADD3 R4, R14.reuse, -0x260923e8, RZ ; /* 0xd9f6dc180e047810 */
/* 0x040fe40007ffe0ff */
/*0140*/ LOP3.LUT R12, R14.reuse, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e50e0c7812 */
/* 0x040fe200078e3cff */
/*0150*/ STG.E.64 [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x0001e2000c101b06 */
/*0160*/ IADD3 R7, R14, 0x583f19, RZ ; /* 0x00583f190e077810 */
/* 0x000fc40007ffe0ff */
/*0170*/ IADD3 R9, R14, -0x25dce5c0, RZ ; /* 0xda231a400e097810 */
/* 0x000fe20007ffe0ff */
/*0180*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e8000c101b06 */
/*0190*/ STG.E.64 [R2.64+0x8], R12 ; /* 0x0000080c02007986 */
/* 0x0001e8000c101b06 */
/*01a0*/ STG.E.64 [R2.64+0x10], R6 ; /* 0x0000100602007986 */
/* 0x0001e4000c101b06 */
/*01b0*/ SHF.R.U32.HI R4, RZ, 0x2, R5 ; /* 0x00000002ff047819 */
/* 0x001fe20000011605 */
/*01c0*/ IMAD.SHL.U32 R6, R7, 0x10, RZ ; /* 0x0000001007067824 */
/* 0x000fe200078e00ff */
/*01d0*/ SHF.R.U32.HI R13, RZ, 0x2, R12 ; /* 0x00000002ff0d7819 */
/* 0x000fe2000001160c */
/*01e0*/ UIADD3 UR4, UR4, -0x4, URZ ; /* 0xfffffffc04047890 */
/* 0x000fe2000fffe03f */
/*01f0*/ LOP3.LUT R4, R4, R5, RZ, 0x3c, !PT ; /* 0x0000000504047212 */
/* 0x000fc400078e3cff */
/*0200*/ LOP3.LUT R12, R13, R12, RZ, 0x3c, !PT ; /* 0x0000000c0d0c7212 */
/* 0x000fe400078e3cff */
/*0210*/ SHF.R.U32.HI R16, RZ, 0x2, R11 ; /* 0x00000002ff107819 */
/* 0x000fe2000001160b */
/*0220*/ IMAD.SHL.U32 R5, R4, 0x2, RZ ; /* 0x0000000204057824 */
/* 0x000fe200078e00ff */
/*0230*/ SHF.R.U32.HI R17, RZ, 0x2, R8 ; /* 0x00000002ff117819 */
/* 0x000fe40000011608 */
/*0240*/ LOP3.LUT R16, R16, R11, RZ, 0x3c, !PT ; /* 0x0000000b10107212 */
/* 0x000fe400078e3cff */
/*0250*/ LOP3.LUT R5, R7, R5, R4, 0x96, !PT ; /* 0x0000000507057212 */
/* 0x000fe200078e9604 */
/*0260*/ IMAD.SHL.U32 R4, R12, 0x2, RZ ; /* 0x000000020c047824 */
/* 0x000fe200078e00ff */
/*0270*/ LOP3.LUT R8, R17, R8, RZ, 0x3c, !PT ; /* 0x0000000811087212 */
/* 0x000fc400078e3cff */
/*0280*/ LOP3.LUT R13, R5, R6, RZ, 0x3c, !PT ; /* 0x00000006050d7212 */
/* 0x000fe200078e3cff */
/*0290*/ IMAD.SHL.U32 R5, R16, 0x2, RZ ; /* 0x0000000210057824 */
/* 0x000fe200078e00ff */
/*02a0*/ SHF.R.U32.HI R6, RZ, 0x2, R7 ; /* 0x00000002ff067819 */
/* 0x000fe40000011607 */
/*02b0*/ LOP3.LUT R4, R13.reuse, R4, R12, 0x96, !PT ; /* 0x000000040d047212 */
/* 0x040fe200078e960c */
/*02c0*/ IMAD.SHL.U32 R11, R13, 0x10, RZ ; /* 0x000000100d0b7824 */
/* 0x000fe200078e00ff */
/*02d0*/ LOP3.LUT R6, R6, R7, RZ, 0x3c, !PT ; /* 0x0000000706067212 */
/* 0x000fc800078e3cff */
/*02e0*/ LOP3.LUT R11, R4, R11, RZ, 0x3c, !PT ; /* 0x0000000b040b7212 */
/* 0x000fe200078e3cff */
/*02f0*/ IMAD.SHL.U32 R4, R8, 0x2, RZ ; /* 0x0000000208047824 */
/* 0x000fe400078e00ff */
/*0300*/ IMAD.SHL.U32 R7, R6, 0x2, RZ ; /* 0x0000000206077824 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R16, R11.reuse, R5, R16, 0x96, !PT ; /* 0x000000050b107212 */
/* 0x040fe200078e9610 */
/*0320*/ IMAD.SHL.U32 R17, R11, 0x10, RZ ; /* 0x000000100b117824 */
/* 0x000fe200078e00ff */
/*0330*/ IADD3 R18, R10, -0x25fe145e, R11 ; /* 0xda01eba20a127810 */
/* 0x000fc80007ffe00b */
/*0340*/ LOP3.LUT R17, R16, R17, RZ, 0x3c, !PT ; /* 0x0000001110117212 */
/* 0x000fe400078e3cff */
/*0350*/ SHF.R.U32.HI R16, RZ, 0x2, R11 ; /* 0x00000002ff107819 */
/* 0x000fe2000001160b */
/*0360*/ I2F.U32 R18, R18 ; /* 0x0000001200127306 */
/* 0x000e220000201000 */
/*0370*/ LOP3.LUT R8, R17.reuse, R4, R8, 0x96, !PT ; /* 0x0000000411087212 */
/* 0x040fe200078e9608 */
/*0380*/ IMAD.SHL.U32 R5, R17, 0x10, RZ ; /* 0x0000001011057824 */
/* 0x000fe200078e00ff */
/*0390*/ IADD3 R4, R10, -0x26039c23, R13 ; /* 0xd9fc63dd0a047810 */
/* 0x000fe40007ffe00d */
/*03a0*/ LOP3.LUT R16, R16, R11, RZ, 0x3c, !PT ; /* 0x0000000b10107212 */
/* 0x000fe400078e3cff */
/*03b0*/ LOP3.LUT R5, R8, R5, RZ, 0x3c, !PT ; /* 0x0000000508057212 */
/* 0x000fc400078e3cff */
/*03c0*/ SHF.R.U32.HI R8, RZ, 0x2, R13 ; /* 0x00000002ff087819 */
/* 0x000fe2000001160d */
/*03d0*/ I2F.U32 R4, R4 ; /* 0x0000000400047306 */
/* 0x000e620000201000 */
/*03e0*/ LOP3.LUT R7, R5.reuse, R7, R6, 0x96, !PT ; /* 0x0000000705077212 */
/* 0x040fe200078e9606 */
/*03f0*/ IMAD.SHL.U32 R12, R5, 0x10, RZ ; /* 0x00000010050c7824 */
/* 0x000fe200078e00ff */
/*0400*/ LOP3.LUT R13, R8, R13, RZ, 0x3c, !PT ; /* 0x0000000d080d7212 */
/* 0x000fe400078e3cff */
/*0410*/ SHF.R.U32.HI R22, RZ, 0x2, R17 ; /* 0x00000002ff167819 */
/* 0x000fe40000011611 */
/*0420*/ LOP3.LUT R12, R7, R12, RZ, 0x3c, !PT ; /* 0x0000000c070c7212 */
/* 0x000fe200078e3cff */
/*0430*/ IMAD.SHL.U32 R6, R13, 0x2, RZ ; /* 0x000000020d067824 */
/* 0x000fe200078e00ff */
/*0440*/ IADD3 R20, R10, -0x25f304d4, R5 ; /* 0xda0cfb2c0a147810 */
/* 0x000fc60007ffe005 */
/*0450*/ IMAD.SHL.U32 R7, R12.reuse, 0x10, RZ ; /* 0x000000100c077824 */
/* 0x040fe200078e00ff */
/*0460*/ LOP3.LUT R8, R12, R6, R13, 0x96, !PT ; /* 0x000000060c087212 */
/* 0x000fe200078e960d */
/*0470*/ IMAD.MOV.U32 R13, RZ, RZ, 0x2f800000 ; /* 0x2f800000ff0d7424 */
/* 0x000fe200078e00ff */
/*0480*/ IADD3 R6, R10, -0x25f88c99, R17 ; /* 0xda0773670a067810 */
/* 0x000fe20007ffe011 */
/*0490*/ I2F.U32 R20, R20 ; /* 0x0000001400147306 */
/* 0x000ea20000201000 */
/*04a0*/ LOP3.LUT R11, R8, R7, RZ, 0x3c, !PT ; /* 0x00000007080b7212 */
/* 0x000fe200078e3cff */
/*04b0*/ IMAD.SHL.U32 R7, R16, 0x2, RZ ; /* 0x0000000210077824 */
/* 0x000fe200078e00ff */
/*04c0*/ LOP3.LUT R17, R22, R17, RZ, 0x3c, !PT ; /* 0x0000001116117212 */
/* 0x000fe200078e3cff */
/*04d0*/ FFMA R18, R18, R13, 1.1641532182693481445e-10 ; /* 0x2f00000012127423 */
/* 0x001fe2000000000d */
/*04e0*/ IADD3 R22, R9, -0xb0f8a, R11 ; /* 0xfff4f07609167810 */
/* 0x000fe20007ffe00b */
/*04f0*/ IMAD.SHL.U32 R8, R11.reuse, 0x10, RZ ; /* 0x000000100b087824 */
/* 0x040fe200078e00ff */
/*0500*/ LOP3.LUT R7, R11, R7, R16, 0x96, !PT ; /* 0x000000070b077212 */
/* 0x000fe200078e9610 */
/*0510*/ I2F.U32 R6, R6 ; /* 0x0000000600067306 */
/* 0x000e220000201000 */
/*0520*/ IADD3 R16, R9, -0x10974f, R12 ; /* 0xffef68b109107810 */
/* 0x000fe20007ffe00c */
/*0530*/ FMUL R18, R18, R18 ; /* 0x0000001212127220 */
/* 0x000fe20000400000 */
/*0540*/ LOP3.LUT R8, R7, R8, RZ, 0x3c, !PT ; /* 0x0000000807087212 */
/* 0x000fe200078e3cff */
/*0550*/ IMAD.SHL.U32 R7, R17, 0x2, RZ ; /* 0x0000000211077824 */
/* 0x000fe200078e00ff */
/*0560*/ IADD3 R10, R10, 0x2c3e28, RZ ; /* 0x002c3e280a0a7810 */
/* 0x000fc40007ffe0ff */
/*0570*/ IADD3 R21, R9, -0x587c5, R8 ; /* 0xfffa783b09157810 */
/* 0x000fe20007ffe008 */
/*0580*/ I2F.U32 R22, R22 ; /* 0x0000001600167306 */
/* 0x000ee20000201000 */
/*0590*/ LOP3.LUT R24, R8.reuse, R7, R17, 0x96, !PT ; /* 0x0000000708187212 */
/* 0x040fe200078e9611 */
/*05a0*/ IMAD.SHL.U32 R7, R8, 0x10, RZ ; /* 0x0000001008077824 */
/* 0x000fe400078e00ff */
/*05b0*/ FFMA R17, R4, R13.reuse, 1.1641532182693481445e-10 ; /* 0x2f00000004117423 */
/* 0x082fe4000000000d */
/*05c0*/ FFMA R20, R20, R13, 1.1641532182693481445e-10 ; /* 0x2f00000014147423 */
/* 0x004fe2000000000d */
/*05d0*/ LOP3.LUT R7, R24, R7, RZ, 0x3c, !PT ; /* 0x0000000718077212 */
/* 0x000fe200078e3cff */
/*05e0*/ I2F.U32 R16, R16 ; /* 0x0000001000107306 */
/* 0x000e620000201000 */
/*05f0*/ FFMA R18, R17, R17, R18 ; /* 0x0000001111127223 */
/* 0x000fc40000000012 */
/*0600*/ FFMA R6, R6, R13.reuse, 1.1641532182693481445e-10 ; /* 0x2f00000006067423 */
/* 0x081fe4000000000d */
/*0610*/ IMAD.IADD R4, R7, 0x1, R9 ; /* 0x0000000107047824 */
/* 0x000fe200078e0209 */
/*0620*/ FSETP.GTU.AND P0, PT, R18, 1, PT ; /* 0x3f8000001200780b */
/* 0x000fe20003f0c000 */
/*0630*/ FMUL R17, R20, R20 ; /* 0x0000001414117220 */
/* 0x000fe20000400000 */
/*0640*/ I2F.U32 R24, R21 ; /* 0x0000001500187306 */
/* 0x000e220000201000 */
/*0650*/ FFMA R22, R22, R13, 1.1641532182693481445e-10 ; /* 0x2f00000016167423 */
/* 0x008fe2000000000d */
/*0660*/ IADD3 R9, R9, 0x2c3e28, RZ ; /* 0x002c3e2809097810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R17, R6, R6, R17 ; /* 0x0000000606117223 */
/* 0x000fe20000000011 */
/*0680*/ IADD3 R6, R15, 0x1, RZ ; /* 0x000000010f067810 */
/* 0x000fe20007ffe0ff */
/*0690*/ FMUL R19, R22, R22 ; /* 0x0000001616137220 */
/* 0x000fc60000400000 */
/*06a0*/ I2F.U32 R4, R4 ; /* 0x0000000400047306 */
/* 0x000ea20000201000 */
/*06b0*/ FFMA R16, R16, R13.reuse, 1.1641532182693481445e-10 ; /* 0x2f00000010107423 */
/* 0x082fe2000000000d */
/*06c0*/ FSETP.GTU.AND P1, PT, R17, 1, PT ; /* 0x3f8000001100780b */
/* 0x000fe20003f2c000 */
/*06d0*/ @P0 IMAD.MOV R6, RZ, RZ, R15 ; /* 0x000000ffff060224 */
/* 0x000fe400078e020f */
/*06e0*/ FFMA R19, R16, R16, R19 ; /* 0x0000001010137223 */
/* 0x000fe40000000013 */
/*06f0*/ FFMA R24, R24, R13, 1.1641532182693481445e-10 ; /* 0x2f00000018187423 */
/* 0x001fc6000000000d */
/*0700*/ FSETP.GTU.AND P0, PT, R19, 1, PT ; /* 0x3f8000001300780b */
/* 0x000fe20003f0c000 */
/*0710*/ FFMA R4, R4, R13, 1.1641532182693481445e-10 ; /* 0x2f00000004047423 */
/* 0x004fc8000000000d */
/*0720*/ FMUL R13, R4, R4 ; /* 0x00000004040d7220 */
/* 0x000fe20000400000 */
/*0730*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*0740*/ @P1 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff041224 */
/* 0x000fe400078e0206 */
/*0750*/ FFMA R13, R24, R24, R13 ; /* 0x00000018180d7223 */
/* 0x000fc6000000000d */
/*0760*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fe20007ffe0ff */
/*0770*/ @P0 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff060224 */
/* 0x000fe200078e0204 */
/*0780*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf05270 */
/*0790*/ FSETP.GTU.AND P1, PT, R13, 1, PT ; /* 0x3f8000000d00780b */
/* 0x000fe40003f2c000 */
/*07a0*/ IADD3 R15, R6, 0x1, RZ ; /* 0x00000001060f7810 */
/* 0x000fd60007ffe0ff */
/*07b0*/ @P1 IMAD.MOV R15, RZ, RZ, R6 ; /* 0x000000ffff0f1224 */
/* 0x000fe200078e0206 */
/*07c0*/ @P0 BRA 0x1b0 ; /* 0xfffff9e000000947 */
/* 0x000fea000383ffff */
/*07d0*/ I2F R15, R15 ; /* 0x0000000f000f7306 */
/* 0x000e220000201400 */
/*07e0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*07f0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fe200078010ff */
/*0800*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0007 */
/*0810*/ IADD3 R6, R14, 0x6350418, RZ ; /* 0x063504180e067810 */
/* 0x000fe20007ffe0ff */
/*0820*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*0830*/ LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fe200000f14ff */
/*0840*/ STG.E.64 [R2.64+0x8], R10 ; /* 0x0000080a02007986 */
/* 0x000fe8000c101b06 */
/*0850*/ STG.E.64 [R2.64+0x10], R8 ; /* 0x0000100802007986 */
/* 0x000fe8000c101b06 */
/*0860*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b06 */
/*0870*/ FMUL R12, R15, 4 ; /* 0x408000000f0c7820 */
/* 0x001fc80000400000 */
/*0880*/ FMUL R13, R12, 0.0009765625 ; /* 0x3a8000000c0d7820 */
/* 0x000fca0000400000 */
/*0890*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101906 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <curand_kernel.h> // CURAND lib header file
#define TRIALS_PER_THREAD 1024 // Set the value for global variables
#define BLOCKS 256
#define THREADS 512
#define PI 3.1415926535 // Known value of pi, to calculate error
__global__ void pi_mc(float *estimate, curandState *states){
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
int points_in_circle = 0;
float x, y;
// Initialize CURAND
curand_init(tid, 0, 0, &states[tid]);
for(int i = 0; i < TRIALS_PER_THREAD; i++){
x = curand_uniform(&states[tid]);
y = curand_uniform(&states[tid]);
// Count if x & y is in the circle
points_in_circle += (x*x + y*y <= 1.0f);
}
estimate[tid] = 4.0f * points_in_circle / (float) TRIALS_PER_THREAD;
}
int main(int argc, char *argv[]){
float host[BLOCKS * THREADS];
float *dev;
curandState *devStates;
// Allocate memory on GPU
cudaMalloc((void **) &dev, BLOCKS * THREADS * sizeof(float));
cudaMalloc((void **) &devStates, BLOCKS * THREADS * sizeof(curandState));
// Invoke the kernel
pi_mc<<<BLOCKS, THREADS>>>(dev, devStates);
// Copy from device back to host
cudaMemcpy(host, dev, BLOCKS * THREADS * sizeof(float), cudaMemcpyDeviceToHost);
// Free the memory on GPU
cudaFree(dev);
cudaFree(devStates);
// Get the average estimate pi value among all blocks and threads, and calculate error
float pi_gpu = 0.0;
for(int i = 0; i < BLOCKS * THREADS; i++){
pi_gpu += host[i];
}
pi_gpu /= (BLOCKS * THREADS);
printf("Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n",
TRIALS_PER_THREAD, BLOCKS, THREADS);
printf("CUDA estimate of PI = %f [error of %f]\n", pi_gpu, pi_gpu - PI);
return 0;
} | .file "tmpxft_000aab80_00000000-6_cuda_monte_carlo_pi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW
.type _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW, @function
_Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5pi_mcPfP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW, .-_Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW
.globl _Z5pi_mcPfP17curandStateXORWOW
.type _Z5pi_mcPfP17curandStateXORWOW, @function
_Z5pi_mcPfP17curandStateXORWOW:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z5pi_mcPfP17curandStateXORWOW, .-_Z5pi_mcPfP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n"
.align 8
.LC4:
.string "CUDA estimate of PI = %f [error of %f]\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -524288(%rsp), %r11
.cfi_def_cfa 11, 524304
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $80, %rsp
.cfi_def_cfa_offset 524384
movq %fs:40, %rax
movq %rax, 524360(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $6291456, %esi
call cudaMalloc@PLT
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $256, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rax
leaq 524352(%rsp), %rdx
pxor %xmm0, %xmm0
.L13:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L13
mulss .LC1(%rip), %xmm0
movss %xmm0, 12(%rsp)
movl $512, %r8d
movl $256, %ecx
movl $1024, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movapd %xmm0, %xmm1
subsd .LC3(%rip), %xmm1
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 524360(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $524368, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z5pi_mcPfP17curandStateXORWOW"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5pi_mcPfP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 922746880
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 1413551940
.long 1074340347
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <curand_kernel.h> // CURAND lib header file
#define TRIALS_PER_THREAD 1024 // Set the value for global variables
#define BLOCKS 256
#define THREADS 512
#define PI 3.1415926535 // Known value of pi, to calculate error
__global__ void pi_mc(float *estimate, curandState *states){
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
int points_in_circle = 0;
float x, y;
// Initialize CURAND
curand_init(tid, 0, 0, &states[tid]);
for(int i = 0; i < TRIALS_PER_THREAD; i++){
x = curand_uniform(&states[tid]);
y = curand_uniform(&states[tid]);
// Count if x & y is in the circle
points_in_circle += (x*x + y*y <= 1.0f);
}
estimate[tid] = 4.0f * points_in_circle / (float) TRIALS_PER_THREAD;
}
int main(int argc, char *argv[]){
float host[BLOCKS * THREADS];
float *dev;
curandState *devStates;
// Allocate memory on GPU
cudaMalloc((void **) &dev, BLOCKS * THREADS * sizeof(float));
cudaMalloc((void **) &devStates, BLOCKS * THREADS * sizeof(curandState));
// Invoke the kernel
pi_mc<<<BLOCKS, THREADS>>>(dev, devStates);
// Copy from device back to host
cudaMemcpy(host, dev, BLOCKS * THREADS * sizeof(float), cudaMemcpyDeviceToHost);
// Free the memory on GPU
cudaFree(dev);
cudaFree(devStates);
// Get the average estimate pi value among all blocks and threads, and calculate error
float pi_gpu = 0.0;
for(int i = 0; i < BLOCKS * THREADS; i++){
pi_gpu += host[i];
}
pi_gpu /= (BLOCKS * THREADS);
printf("Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n",
TRIALS_PER_THREAD, BLOCKS, THREADS);
printf("CUDA estimate of PI = %f [error of %f]\n", pi_gpu, pi_gpu - PI);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand_kernel.h> // CURAND lib header file
#define TRIALS_PER_THREAD 1024 // Set the value for global variables
#define BLOCKS 256
#define THREADS 512
#define PI 3.1415926535 // Known value of pi, to calculate error
__global__ void pi_mc(float *estimate, hiprandState *states){
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
int points_in_circle = 0;
float x, y;
// Initialize CURAND
hiprand_init(tid, 0, 0, &states[tid]);
for(int i = 0; i < TRIALS_PER_THREAD; i++){
x = hiprand_uniform(&states[tid]);
y = hiprand_uniform(&states[tid]);
// Count if x & y is in the circle
points_in_circle += (x*x + y*y <= 1.0f);
}
estimate[tid] = 4.0f * points_in_circle / (float) TRIALS_PER_THREAD;
}
int main(int argc, char *argv[]){
float host[BLOCKS * THREADS];
float *dev;
hiprandState *devStates;
// Allocate memory on GPU
hipMalloc((void **) &dev, BLOCKS * THREADS * sizeof(float));
hipMalloc((void **) &devStates, BLOCKS * THREADS * sizeof(hiprandState));
// Invoke the kernel
pi_mc<<<BLOCKS, THREADS>>>(dev, devStates);
// Copy from device back to host
hipMemcpy(host, dev, BLOCKS * THREADS * sizeof(float), hipMemcpyDeviceToHost);
// Free the memory on GPU
hipFree(dev);
hipFree(devStates);
// Get the average estimate pi value among all blocks and threads, and calculate error
float pi_gpu = 0.0;
for(int i = 0; i < BLOCKS * THREADS; i++){
pi_gpu += host[i];
}
pi_gpu /= (BLOCKS * THREADS);
printf("Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n",
TRIALS_PER_THREAD, BLOCKS, THREADS);
printf("CUDA estimate of PI = %f [error of %f]\n", pi_gpu, pi_gpu - PI);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand_kernel.h> // CURAND lib header file
#define TRIALS_PER_THREAD 1024 // Set the value for global variables
#define BLOCKS 256
#define THREADS 512
#define PI 3.1415926535 // Known value of pi, to calculate error
__global__ void pi_mc(float *estimate, hiprandState *states){
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
int points_in_circle = 0;
float x, y;
// Initialize CURAND
hiprand_init(tid, 0, 0, &states[tid]);
for(int i = 0; i < TRIALS_PER_THREAD; i++){
x = hiprand_uniform(&states[tid]);
y = hiprand_uniform(&states[tid]);
// Count if x & y is in the circle
points_in_circle += (x*x + y*y <= 1.0f);
}
estimate[tid] = 4.0f * points_in_circle / (float) TRIALS_PER_THREAD;
}
int main(int argc, char *argv[]){
float host[BLOCKS * THREADS];
float *dev;
hiprandState *devStates;
// Allocate memory on GPU
hipMalloc((void **) &dev, BLOCKS * THREADS * sizeof(float));
hipMalloc((void **) &devStates, BLOCKS * THREADS * sizeof(hiprandState));
// Invoke the kernel
pi_mc<<<BLOCKS, THREADS>>>(dev, devStates);
// Copy from device back to host
hipMemcpy(host, dev, BLOCKS * THREADS * sizeof(float), hipMemcpyDeviceToHost);
// Free the memory on GPU
hipFree(dev);
hipFree(devStates);
// Get the average estimate pi value among all blocks and threads, and calculate error
float pi_gpu = 0.0;
for(int i = 0; i < BLOCKS * THREADS; i++){
pi_gpu += host[i];
}
pi_gpu /= (BLOCKS * THREADS);
printf("Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n",
TRIALS_PER_THREAD, BLOCKS, THREADS);
printf("CUDA estimate of PI = %f [error of %f]\n", pi_gpu, pi_gpu - PI);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5pi_mcPfP12hiprandState
.globl _Z5pi_mcPfP12hiprandState
.p2align 8
.type _Z5pi_mcPfP12hiprandState,@function
_Z5pi_mcPfP12hiprandState:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v2, 0xa96f9d04
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0x8f14727c :: v_dual_mov_b32 v8, v7
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[9:10], null, s15, s4, v[0:1]
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, 0x2c7f967f, v9
v_mad_u64_u32 v[11:12], null, v9, 48, s[2:3]
s_mov_b32 s2, 0xd3c1d800
v_mul_lo_u32 v4, v0, 0x493c4aa1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, 0x75bcd15, v4
v_add_nc_u32_e32 v6, 0x8ac25218, v4
v_xor_b32_e32 v1, 0x159a55e5, v4
v_add_nc_u32_e32 v13, 0x583f19, v4
s_clause 0x2
global_store_b96 v[11:12], v[6:8], off
global_store_b128 v[11:12], v[0:3], off offset:24
global_store_b32 v[11:12], v13, off offset:40
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
v_lshrrev_b32_e32 v5, 2, v0
v_mov_b32_e32 v4, v2
v_mov_b32_e32 v2, v13
v_lshrrev_b32_e32 v13, 2, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v0, v5, v0
v_lshlrev_b32_e32 v5, 4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v1, v13, v1
v_lshlrev_b32_e32 v8, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v5
v_mov_b32_e32 v5, v3
v_xor3_b32 v3, v8, v0, v2
v_lshlrev_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v8, 4, v3
v_xor_b32_e32 v0, v0, v8
v_add_nc_u32_e32 v8, s2, v6
s_add_i32 s2, s2, 0xb0f8a
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 0
v_xor3_b32 v13, v0, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v1, v8, v3, 0x2c43afc5
v_add3_u32 v0, v8, v13, 0x2c49378a
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v1, v1
v_cvt_f32_u32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v1, 0x2f800000, v1, 0x2f800000 :: v_dual_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000
v_mul_f32_e32 v8, v0, v0
v_mov_b32_e32 v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v1, v1
v_mov_b32_e32 v1, v5
v_cmp_ge_f32_e32 vcc_lo, 1.0, v8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_cbranch_scc0 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v7
v_dual_mov_b32 v7, v3 :: v_dual_mul_f32 v8, 4.0, v0
v_lshlrev_b64 v[0:1], 2, v[9:10]
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v9, 0x2c3e2800, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v2, 0x3a800000, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_store_b32 v[11:12], v13, off offset:40
global_store_b128 v[11:12], v[4:7], off offset:24
global_store_b32 v[11:12], v9, off
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5pi_mcPfP12hiprandState
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5pi_mcPfP12hiprandState, .Lfunc_end0-_Z5pi_mcPfP12hiprandState
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5pi_mcPfP12hiprandState
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5pi_mcPfP12hiprandState.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <hiprand/hiprand_kernel.h> // CURAND lib header file
#define TRIALS_PER_THREAD 1024 // Set the value for global variables
#define BLOCKS 256
#define THREADS 512
#define PI 3.1415926535 // Known value of pi, to calculate error
__global__ void pi_mc(float *estimate, hiprandState *states){
unsigned int tid = threadIdx.x + blockDim.x * blockIdx.x;
int points_in_circle = 0;
float x, y;
// Initialize CURAND
hiprand_init(tid, 0, 0, &states[tid]);
for(int i = 0; i < TRIALS_PER_THREAD; i++){
x = hiprand_uniform(&states[tid]);
y = hiprand_uniform(&states[tid]);
// Count if x & y is in the circle
points_in_circle += (x*x + y*y <= 1.0f);
}
estimate[tid] = 4.0f * points_in_circle / (float) TRIALS_PER_THREAD;
}
int main(int argc, char *argv[]){
float host[BLOCKS * THREADS];
float *dev;
hiprandState *devStates;
// Allocate memory on GPU
hipMalloc((void **) &dev, BLOCKS * THREADS * sizeof(float));
hipMalloc((void **) &devStates, BLOCKS * THREADS * sizeof(hiprandState));
// Invoke the kernel
pi_mc<<<BLOCKS, THREADS>>>(dev, devStates);
// Copy from device back to host
hipMemcpy(host, dev, BLOCKS * THREADS * sizeof(float), hipMemcpyDeviceToHost);
// Free the memory on GPU
hipFree(dev);
hipFree(devStates);
// Get the average estimate pi value among all blocks and threads, and calculate error
float pi_gpu = 0.0;
for(int i = 0; i < BLOCKS * THREADS; i++){
pi_gpu += host[i];
}
pi_gpu /= (BLOCKS * THREADS);
printf("Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n",
TRIALS_PER_THREAD, BLOCKS, THREADS);
printf("CUDA estimate of PI = %f [error of %f]\n", pi_gpu, pi_gpu - PI);
return 0;
} | .text
.file "cuda_monte_carlo_pi.hip"
.globl _Z20__device_stub__pi_mcPfP12hiprandState # -- Begin function _Z20__device_stub__pi_mcPfP12hiprandState
.p2align 4, 0x90
.type _Z20__device_stub__pi_mcPfP12hiprandState,@function
_Z20__device_stub__pi_mcPfP12hiprandState: # @_Z20__device_stub__pi_mcPfP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5pi_mcPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__pi_mcPfP12hiprandState, .Lfunc_end0-_Z20__device_stub__pi_mcPfP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x37000000 # float 7.62939453E-6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0xc00921fb54411744 # double -3.1415926535000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $524392, %rsp # imm = 0x80068
.cfi_def_cfa_offset 524400
leaq 8(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $6291456, %esi # imm = 0x600000
callq hipMalloc
movabsq $4294967552, %rdi # imm = 0x100000100
leaq 256(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5pi_mcPfP12hiprandState, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addss 96(%rsp,%rax,4), %xmm0
incq %rax
cmpq $131072, %rax # imm = 0x20000
jne .LBB1_3
# %bb.4:
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, 20(%rsp) # 4-byte Spill
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
movl $256, %edx # imm = 0x100
movl $512, %ecx # imm = 0x200
xorl %eax, %eax
callq printf
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
xorl %eax, %eax
addq $524392, %rsp # imm = 0x80068
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5pi_mcPfP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5pi_mcPfP12hiprandState,@object # @_Z5pi_mcPfP12hiprandState
.section .rodata,"a",@progbits
.globl _Z5pi_mcPfP12hiprandState
.p2align 3, 0x0
_Z5pi_mcPfP12hiprandState:
.quad _Z20__device_stub__pi_mcPfP12hiprandState
.size _Z5pi_mcPfP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n"
.size .L.str, 77
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA estimate of PI = %f [error of %f]\n"
.size .L.str.1, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5pi_mcPfP12hiprandState"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__pi_mcPfP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5pi_mcPfP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5pi_mcPfP17curandStateXORWOW
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R13, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff0d7424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff067424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0070*/ UMOV UR4, 0x400 ; /* 0x0000040000047882 */
/* 0x000fe20000000000 */
/*0080*/ IMAD.MOV.U32 R11, RZ, RZ, -0x75bd8fc ; /* 0xf8a42704ff0b7424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R8, RZ, RZ, -0x23270784 ; /* 0xdcd8f87cff087424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc400078e0203 */
/*00b0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x30 ; /* 0x00000030ff037424 */
/* 0x000fc600078e00ff */
/*00c0*/ LOP3.LUT R14, R0.reuse, 0xaad26b49, RZ, 0x3c, !PT ; /* 0xaad26b49000e7812 */
/* 0x040fe200078e3cff */
/*00d0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0003 */
/*00e0*/ IMAD R14, R14, 0x4182bed5, RZ ; /* 0x4182bed50e0e7824 */
/* 0x000fe200078e02ff */
/*00f0*/ STG.E.64 [R2.64+0x18], RZ ; /* 0x000018ff02007986 */
/* 0x0001e6000c101b06 */
/*0100*/ IMAD.MOV.U32 R10, RZ, RZ, R14 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000e */
/*0110*/ IADD3 R5, R14.reuse, 0x75bcd15, RZ ; /* 0x075bcd150e057810 */
/* 0x040fe20007ffe0ff */
/*0120*/ STG.E [R2.64+0x20], RZ ; /* 0x000020ff02007986 */
/* 0x0001e2000c101906 */
/*0130*/ IADD3 R4, R14.reuse, -0x260923e8, RZ ; /* 0xd9f6dc180e047810 */
/* 0x040fe40007ffe0ff */
/*0140*/ LOP3.LUT R12, R14.reuse, 0x159a55e5, RZ, 0x3c, !PT ; /* 0x159a55e50e0c7812 */
/* 0x040fe200078e3cff */
/*0150*/ STG.E.64 [R2.64+0x28], RZ ; /* 0x000028ff02007986 */
/* 0x0001e2000c101b06 */
/*0160*/ IADD3 R7, R14, 0x583f19, RZ ; /* 0x00583f190e077810 */
/* 0x000fc40007ffe0ff */
/*0170*/ IADD3 R9, R14, -0x25dce5c0, RZ ; /* 0xda231a400e097810 */
/* 0x000fe20007ffe0ff */
/*0180*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0001e8000c101b06 */
/*0190*/ STG.E.64 [R2.64+0x8], R12 ; /* 0x0000080c02007986 */
/* 0x0001e8000c101b06 */
/*01a0*/ STG.E.64 [R2.64+0x10], R6 ; /* 0x0000100602007986 */
/* 0x0001e4000c101b06 */
/*01b0*/ SHF.R.U32.HI R4, RZ, 0x2, R5 ; /* 0x00000002ff047819 */
/* 0x001fe20000011605 */
/*01c0*/ IMAD.SHL.U32 R6, R7, 0x10, RZ ; /* 0x0000001007067824 */
/* 0x000fe200078e00ff */
/*01d0*/ SHF.R.U32.HI R13, RZ, 0x2, R12 ; /* 0x00000002ff0d7819 */
/* 0x000fe2000001160c */
/*01e0*/ UIADD3 UR4, UR4, -0x4, URZ ; /* 0xfffffffc04047890 */
/* 0x000fe2000fffe03f */
/*01f0*/ LOP3.LUT R4, R4, R5, RZ, 0x3c, !PT ; /* 0x0000000504047212 */
/* 0x000fc400078e3cff */
/*0200*/ LOP3.LUT R12, R13, R12, RZ, 0x3c, !PT ; /* 0x0000000c0d0c7212 */
/* 0x000fe400078e3cff */
/*0210*/ SHF.R.U32.HI R16, RZ, 0x2, R11 ; /* 0x00000002ff107819 */
/* 0x000fe2000001160b */
/*0220*/ IMAD.SHL.U32 R5, R4, 0x2, RZ ; /* 0x0000000204057824 */
/* 0x000fe200078e00ff */
/*0230*/ SHF.R.U32.HI R17, RZ, 0x2, R8 ; /* 0x00000002ff117819 */
/* 0x000fe40000011608 */
/*0240*/ LOP3.LUT R16, R16, R11, RZ, 0x3c, !PT ; /* 0x0000000b10107212 */
/* 0x000fe400078e3cff */
/*0250*/ LOP3.LUT R5, R7, R5, R4, 0x96, !PT ; /* 0x0000000507057212 */
/* 0x000fe200078e9604 */
/*0260*/ IMAD.SHL.U32 R4, R12, 0x2, RZ ; /* 0x000000020c047824 */
/* 0x000fe200078e00ff */
/*0270*/ LOP3.LUT R8, R17, R8, RZ, 0x3c, !PT ; /* 0x0000000811087212 */
/* 0x000fc400078e3cff */
/*0280*/ LOP3.LUT R13, R5, R6, RZ, 0x3c, !PT ; /* 0x00000006050d7212 */
/* 0x000fe200078e3cff */
/*0290*/ IMAD.SHL.U32 R5, R16, 0x2, RZ ; /* 0x0000000210057824 */
/* 0x000fe200078e00ff */
/*02a0*/ SHF.R.U32.HI R6, RZ, 0x2, R7 ; /* 0x00000002ff067819 */
/* 0x000fe40000011607 */
/*02b0*/ LOP3.LUT R4, R13.reuse, R4, R12, 0x96, !PT ; /* 0x000000040d047212 */
/* 0x040fe200078e960c */
/*02c0*/ IMAD.SHL.U32 R11, R13, 0x10, RZ ; /* 0x000000100d0b7824 */
/* 0x000fe200078e00ff */
/*02d0*/ LOP3.LUT R6, R6, R7, RZ, 0x3c, !PT ; /* 0x0000000706067212 */
/* 0x000fc800078e3cff */
/*02e0*/ LOP3.LUT R11, R4, R11, RZ, 0x3c, !PT ; /* 0x0000000b040b7212 */
/* 0x000fe200078e3cff */
/*02f0*/ IMAD.SHL.U32 R4, R8, 0x2, RZ ; /* 0x0000000208047824 */
/* 0x000fe400078e00ff */
/*0300*/ IMAD.SHL.U32 R7, R6, 0x2, RZ ; /* 0x0000000206077824 */
/* 0x000fe200078e00ff */
/*0310*/ LOP3.LUT R16, R11.reuse, R5, R16, 0x96, !PT ; /* 0x000000050b107212 */
/* 0x040fe200078e9610 */
/*0320*/ IMAD.SHL.U32 R17, R11, 0x10, RZ ; /* 0x000000100b117824 */
/* 0x000fe200078e00ff */
/*0330*/ IADD3 R18, R10, -0x25fe145e, R11 ; /* 0xda01eba20a127810 */
/* 0x000fc80007ffe00b */
/*0340*/ LOP3.LUT R17, R16, R17, RZ, 0x3c, !PT ; /* 0x0000001110117212 */
/* 0x000fe400078e3cff */
/*0350*/ SHF.R.U32.HI R16, RZ, 0x2, R11 ; /* 0x00000002ff107819 */
/* 0x000fe2000001160b */
/*0360*/ I2F.U32 R18, R18 ; /* 0x0000001200127306 */
/* 0x000e220000201000 */
/*0370*/ LOP3.LUT R8, R17.reuse, R4, R8, 0x96, !PT ; /* 0x0000000411087212 */
/* 0x040fe200078e9608 */
/*0380*/ IMAD.SHL.U32 R5, R17, 0x10, RZ ; /* 0x0000001011057824 */
/* 0x000fe200078e00ff */
/*0390*/ IADD3 R4, R10, -0x26039c23, R13 ; /* 0xd9fc63dd0a047810 */
/* 0x000fe40007ffe00d */
/*03a0*/ LOP3.LUT R16, R16, R11, RZ, 0x3c, !PT ; /* 0x0000000b10107212 */
/* 0x000fe400078e3cff */
/*03b0*/ LOP3.LUT R5, R8, R5, RZ, 0x3c, !PT ; /* 0x0000000508057212 */
/* 0x000fc400078e3cff */
/*03c0*/ SHF.R.U32.HI R8, RZ, 0x2, R13 ; /* 0x00000002ff087819 */
/* 0x000fe2000001160d */
/*03d0*/ I2F.U32 R4, R4 ; /* 0x0000000400047306 */
/* 0x000e620000201000 */
/*03e0*/ LOP3.LUT R7, R5.reuse, R7, R6, 0x96, !PT ; /* 0x0000000705077212 */
/* 0x040fe200078e9606 */
/*03f0*/ IMAD.SHL.U32 R12, R5, 0x10, RZ ; /* 0x00000010050c7824 */
/* 0x000fe200078e00ff */
/*0400*/ LOP3.LUT R13, R8, R13, RZ, 0x3c, !PT ; /* 0x0000000d080d7212 */
/* 0x000fe400078e3cff */
/*0410*/ SHF.R.U32.HI R22, RZ, 0x2, R17 ; /* 0x00000002ff167819 */
/* 0x000fe40000011611 */
/*0420*/ LOP3.LUT R12, R7, R12, RZ, 0x3c, !PT ; /* 0x0000000c070c7212 */
/* 0x000fe200078e3cff */
/*0430*/ IMAD.SHL.U32 R6, R13, 0x2, RZ ; /* 0x000000020d067824 */
/* 0x000fe200078e00ff */
/*0440*/ IADD3 R20, R10, -0x25f304d4, R5 ; /* 0xda0cfb2c0a147810 */
/* 0x000fc60007ffe005 */
/*0450*/ IMAD.SHL.U32 R7, R12.reuse, 0x10, RZ ; /* 0x000000100c077824 */
/* 0x040fe200078e00ff */
/*0460*/ LOP3.LUT R8, R12, R6, R13, 0x96, !PT ; /* 0x000000060c087212 */
/* 0x000fe200078e960d */
/*0470*/ IMAD.MOV.U32 R13, RZ, RZ, 0x2f800000 ; /* 0x2f800000ff0d7424 */
/* 0x000fe200078e00ff */
/*0480*/ IADD3 R6, R10, -0x25f88c99, R17 ; /* 0xda0773670a067810 */
/* 0x000fe20007ffe011 */
/*0490*/ I2F.U32 R20, R20 ; /* 0x0000001400147306 */
/* 0x000ea20000201000 */
/*04a0*/ LOP3.LUT R11, R8, R7, RZ, 0x3c, !PT ; /* 0x00000007080b7212 */
/* 0x000fe200078e3cff */
/*04b0*/ IMAD.SHL.U32 R7, R16, 0x2, RZ ; /* 0x0000000210077824 */
/* 0x000fe200078e00ff */
/*04c0*/ LOP3.LUT R17, R22, R17, RZ, 0x3c, !PT ; /* 0x0000001116117212 */
/* 0x000fe200078e3cff */
/*04d0*/ FFMA R18, R18, R13, 1.1641532182693481445e-10 ; /* 0x2f00000012127423 */
/* 0x001fe2000000000d */
/*04e0*/ IADD3 R22, R9, -0xb0f8a, R11 ; /* 0xfff4f07609167810 */
/* 0x000fe20007ffe00b */
/*04f0*/ IMAD.SHL.U32 R8, R11.reuse, 0x10, RZ ; /* 0x000000100b087824 */
/* 0x040fe200078e00ff */
/*0500*/ LOP3.LUT R7, R11, R7, R16, 0x96, !PT ; /* 0x000000070b077212 */
/* 0x000fe200078e9610 */
/*0510*/ I2F.U32 R6, R6 ; /* 0x0000000600067306 */
/* 0x000e220000201000 */
/*0520*/ IADD3 R16, R9, -0x10974f, R12 ; /* 0xffef68b109107810 */
/* 0x000fe20007ffe00c */
/*0530*/ FMUL R18, R18, R18 ; /* 0x0000001212127220 */
/* 0x000fe20000400000 */
/*0540*/ LOP3.LUT R8, R7, R8, RZ, 0x3c, !PT ; /* 0x0000000807087212 */
/* 0x000fe200078e3cff */
/*0550*/ IMAD.SHL.U32 R7, R17, 0x2, RZ ; /* 0x0000000211077824 */
/* 0x000fe200078e00ff */
/*0560*/ IADD3 R10, R10, 0x2c3e28, RZ ; /* 0x002c3e280a0a7810 */
/* 0x000fc40007ffe0ff */
/*0570*/ IADD3 R21, R9, -0x587c5, R8 ; /* 0xfffa783b09157810 */
/* 0x000fe20007ffe008 */
/*0580*/ I2F.U32 R22, R22 ; /* 0x0000001600167306 */
/* 0x000ee20000201000 */
/*0590*/ LOP3.LUT R24, R8.reuse, R7, R17, 0x96, !PT ; /* 0x0000000708187212 */
/* 0x040fe200078e9611 */
/*05a0*/ IMAD.SHL.U32 R7, R8, 0x10, RZ ; /* 0x0000001008077824 */
/* 0x000fe400078e00ff */
/*05b0*/ FFMA R17, R4, R13.reuse, 1.1641532182693481445e-10 ; /* 0x2f00000004117423 */
/* 0x082fe4000000000d */
/*05c0*/ FFMA R20, R20, R13, 1.1641532182693481445e-10 ; /* 0x2f00000014147423 */
/* 0x004fe2000000000d */
/*05d0*/ LOP3.LUT R7, R24, R7, RZ, 0x3c, !PT ; /* 0x0000000718077212 */
/* 0x000fe200078e3cff */
/*05e0*/ I2F.U32 R16, R16 ; /* 0x0000001000107306 */
/* 0x000e620000201000 */
/*05f0*/ FFMA R18, R17, R17, R18 ; /* 0x0000001111127223 */
/* 0x000fc40000000012 */
/*0600*/ FFMA R6, R6, R13.reuse, 1.1641532182693481445e-10 ; /* 0x2f00000006067423 */
/* 0x081fe4000000000d */
/*0610*/ IMAD.IADD R4, R7, 0x1, R9 ; /* 0x0000000107047824 */
/* 0x000fe200078e0209 */
/*0620*/ FSETP.GTU.AND P0, PT, R18, 1, PT ; /* 0x3f8000001200780b */
/* 0x000fe20003f0c000 */
/*0630*/ FMUL R17, R20, R20 ; /* 0x0000001414117220 */
/* 0x000fe20000400000 */
/*0640*/ I2F.U32 R24, R21 ; /* 0x0000001500187306 */
/* 0x000e220000201000 */
/*0650*/ FFMA R22, R22, R13, 1.1641532182693481445e-10 ; /* 0x2f00000016167423 */
/* 0x008fe2000000000d */
/*0660*/ IADD3 R9, R9, 0x2c3e28, RZ ; /* 0x002c3e2809097810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R17, R6, R6, R17 ; /* 0x0000000606117223 */
/* 0x000fe20000000011 */
/*0680*/ IADD3 R6, R15, 0x1, RZ ; /* 0x000000010f067810 */
/* 0x000fe20007ffe0ff */
/*0690*/ FMUL R19, R22, R22 ; /* 0x0000001616137220 */
/* 0x000fc60000400000 */
/*06a0*/ I2F.U32 R4, R4 ; /* 0x0000000400047306 */
/* 0x000ea20000201000 */
/*06b0*/ FFMA R16, R16, R13.reuse, 1.1641532182693481445e-10 ; /* 0x2f00000010107423 */
/* 0x082fe2000000000d */
/*06c0*/ FSETP.GTU.AND P1, PT, R17, 1, PT ; /* 0x3f8000001100780b */
/* 0x000fe20003f2c000 */
/*06d0*/ @P0 IMAD.MOV R6, RZ, RZ, R15 ; /* 0x000000ffff060224 */
/* 0x000fe400078e020f */
/*06e0*/ FFMA R19, R16, R16, R19 ; /* 0x0000001010137223 */
/* 0x000fe40000000013 */
/*06f0*/ FFMA R24, R24, R13, 1.1641532182693481445e-10 ; /* 0x2f00000018187423 */
/* 0x001fc6000000000d */
/*0700*/ FSETP.GTU.AND P0, PT, R19, 1, PT ; /* 0x3f8000001300780b */
/* 0x000fe20003f0c000 */
/*0710*/ FFMA R4, R4, R13, 1.1641532182693481445e-10 ; /* 0x2f00000004047423 */
/* 0x004fc8000000000d */
/*0720*/ FMUL R13, R4, R4 ; /* 0x00000004040d7220 */
/* 0x000fe20000400000 */
/*0730*/ IADD3 R4, R6, 0x1, RZ ; /* 0x0000000106047810 */
/* 0x000fe20007ffe0ff */
/*0740*/ @P1 IMAD.MOV R4, RZ, RZ, R6 ; /* 0x000000ffff041224 */
/* 0x000fe400078e0206 */
/*0750*/ FFMA R13, R24, R24, R13 ; /* 0x00000018180d7223 */
/* 0x000fc6000000000d */
/*0760*/ IADD3 R6, R4, 0x1, RZ ; /* 0x0000000104067810 */
/* 0x000fe20007ffe0ff */
/*0770*/ @P0 IMAD.MOV R6, RZ, RZ, R4 ; /* 0x000000ffff060224 */
/* 0x000fe200078e0204 */
/*0780*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf05270 */
/*0790*/ FSETP.GTU.AND P1, PT, R13, 1, PT ; /* 0x3f8000000d00780b */
/* 0x000fe40003f2c000 */
/*07a0*/ IADD3 R15, R6, 0x1, RZ ; /* 0x00000001060f7810 */
/* 0x000fd60007ffe0ff */
/*07b0*/ @P1 IMAD.MOV R15, RZ, RZ, R6 ; /* 0x000000ffff0f1224 */
/* 0x000fe200078e0206 */
/*07c0*/ @P0 BRA 0x1b0 ; /* 0xfffff9e000000947 */
/* 0x000fea000383ffff */
/*07d0*/ I2F R15, R15 ; /* 0x0000000f000f7306 */
/* 0x000e220000201400 */
/*07e0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*07f0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fe200078010ff */
/*0800*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0007 */
/*0810*/ IADD3 R6, R14, 0x6350418, RZ ; /* 0x063504180e067810 */
/* 0x000fe20007ffe0ff */
/*0820*/ IMAD.MOV.U32 R7, RZ, RZ, R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0005 */
/*0830*/ LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fe200000f14ff */
/*0840*/ STG.E.64 [R2.64+0x8], R10 ; /* 0x0000080a02007986 */
/* 0x000fe8000c101b06 */
/*0850*/ STG.E.64 [R2.64+0x10], R8 ; /* 0x0000100802007986 */
/* 0x000fe8000c101b06 */
/*0860*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x000fe2000c101b06 */
/*0870*/ FMUL R12, R15, 4 ; /* 0x408000000f0c7820 */
/* 0x001fc80000400000 */
/*0880*/ FMUL R13, R12, 0.0009765625 ; /* 0x3a8000000c0d7820 */
/* 0x000fca0000400000 */
/*0890*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x000fe2000c101906 */
/*08a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08b0*/ BRA 0x8b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5pi_mcPfP12hiprandState
.globl _Z5pi_mcPfP12hiprandState
.p2align 8
.type _Z5pi_mcPfP12hiprandState,@function
_Z5pi_mcPfP12hiprandState:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x8
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v2, 0xa96f9d04
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0x8f14727c :: v_dual_mov_b32 v8, v7
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[9:10], null, s15, s4, v[0:1]
v_mov_b32_e32 v10, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, 0x2c7f967f, v9
v_mad_u64_u32 v[11:12], null, v9, 48, s[2:3]
s_mov_b32 s2, 0xd3c1d800
v_mul_lo_u32 v4, v0, 0x493c4aa1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, 0x75bcd15, v4
v_add_nc_u32_e32 v6, 0x8ac25218, v4
v_xor_b32_e32 v1, 0x159a55e5, v4
v_add_nc_u32_e32 v13, 0x583f19, v4
s_clause 0x2
global_store_b96 v[11:12], v[6:8], off
global_store_b128 v[11:12], v[0:3], off offset:24
global_store_b32 v[11:12], v13, off offset:40
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
v_lshrrev_b32_e32 v5, 2, v0
v_mov_b32_e32 v4, v2
v_mov_b32_e32 v2, v13
v_lshrrev_b32_e32 v13, 2, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v0, v5, v0
v_lshlrev_b32_e32 v5, 4, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v1, v13, v1
v_lshlrev_b32_e32 v8, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v5
v_mov_b32_e32 v5, v3
v_xor3_b32 v3, v8, v0, v2
v_lshlrev_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v8, 4, v3
v_xor_b32_e32 v0, v0, v8
v_add_nc_u32_e32 v8, s2, v6
s_add_i32 s2, s2, 0xb0f8a
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s2, 0
v_xor3_b32 v13, v0, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v1, v8, v3, 0x2c43afc5
v_add3_u32 v0, v8, v13, 0x2c49378a
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_u32_e32 v1, v1
v_cvt_f32_u32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmaak_f32 v1, 0x2f800000, v1, 0x2f800000 :: v_dual_fmaak_f32 v0, 0x2f800000, v0, 0x2f800000
v_mul_f32_e32 v8, v0, v0
v_mov_b32_e32 v0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v1, v1
v_mov_b32_e32 v1, v5
v_cmp_ge_f32_e32 vcc_lo, 1.0, v8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_cbranch_scc0 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v0, v7
v_dual_mov_b32 v7, v3 :: v_dual_mul_f32 v8, 4.0, v0
v_lshlrev_b64 v[0:1], 2, v[9:10]
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v9, 0x2c3e2800, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v2, 0x3a800000, v8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_clause 0x2
global_store_b32 v[11:12], v13, off offset:40
global_store_b128 v[11:12], v[4:7], off offset:24
global_store_b32 v[11:12], v9, off
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5pi_mcPfP12hiprandState
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5pi_mcPfP12hiprandState, .Lfunc_end0-_Z5pi_mcPfP12hiprandState
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5pi_mcPfP12hiprandState
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5pi_mcPfP12hiprandState.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aab80_00000000-6_cuda_monte_carlo_pi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2274:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2274:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW
.type _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW, @function
_Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW:
.LFB2296:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5pi_mcPfP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2296:
.size _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW, .-_Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW
.globl _Z5pi_mcPfP17curandStateXORWOW
.type _Z5pi_mcPfP17curandStateXORWOW, @function
_Z5pi_mcPfP17curandStateXORWOW:
.LFB2297:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2297:
.size _Z5pi_mcPfP17curandStateXORWOW, .-_Z5pi_mcPfP17curandStateXORWOW
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n"
.align 8
.LC4:
.string "CUDA estimate of PI = %f [error of %f]\n"
.text
.globl main
.type main, @function
main:
.LFB2271:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq -524288(%rsp), %r11
.cfi_def_cfa 11, 524304
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $80, %rsp
.cfi_def_cfa_offset 524384
movq %fs:40, %rax
movq %rax, 524360(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $524288, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $6291456, %esi
call cudaMalloc@PLT
movl $512, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $256, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L12:
leaq 64(%rsp), %rbx
movl $2, %ecx
movl $524288, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rax
leaq 524352(%rsp), %rdx
pxor %xmm0, %xmm0
.L13:
addss (%rax), %xmm0
addq $4, %rax
cmpq %rdx, %rax
jne .L13
mulss .LC1(%rip), %xmm0
movss %xmm0, 12(%rsp)
movl $512, %r8d
movl $256, %ecx
movl $1024, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
movapd %xmm0, %xmm1
subsd .LC3(%rip), %xmm1
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 524360(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $524368, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z44__device_stub__Z5pi_mcPfP17curandStateXORWOWPfP17curandStateXORWOW
jmp .L12
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2271:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC5:
.string "_Z5pi_mcPfP17curandStateXORWOW"
.section .rodata.str1.1,"aMS",@progbits,1
.LC6:
.string "precalc_xorwow_matrix"
.LC7:
.string "precalc_xorwow_offset_matrix"
.LC8:
.string "mrg32k3aM1"
.LC9:
.string "mrg32k3aM2"
.LC10:
.string "mrg32k3aM1SubSeq"
.LC11:
.string "mrg32k3aM2SubSeq"
.LC12:
.string "mrg32k3aM1Seq"
.LC13:
.string "mrg32k3aM2Seq"
.LC14:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2299:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5pi_mcPfP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2299:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 922746880
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 1413551940
.long 1074340347
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_monte_carlo_pi.hip"
.globl _Z20__device_stub__pi_mcPfP12hiprandState # -- Begin function _Z20__device_stub__pi_mcPfP12hiprandState
.p2align 4, 0x90
.type _Z20__device_stub__pi_mcPfP12hiprandState,@function
_Z20__device_stub__pi_mcPfP12hiprandState: # @_Z20__device_stub__pi_mcPfP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5pi_mcPfP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__pi_mcPfP12hiprandState, .Lfunc_end0-_Z20__device_stub__pi_mcPfP12hiprandState
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x37000000 # float 7.62939453E-6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0xc00921fb54411744 # double -3.1415926535000001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $524392, %rsp # imm = 0x80068
.cfi_def_cfa_offset 524400
leaq 8(%rsp), %rdi
movl $524288, %esi # imm = 0x80000
callq hipMalloc
leaq 24(%rsp), %rdi
movl $6291456, %esi # imm = 0x600000
callq hipMalloc
movabsq $4294967552, %rdi # imm = 0x100000100
leaq 256(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5pi_mcPfP12hiprandState, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
leaq 96(%rsp), %rdi
movl $524288, %edx # imm = 0x80000
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
xorps %xmm0, %xmm0
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # =>This Inner Loop Header: Depth=1
addss 96(%rsp,%rax,4), %xmm0
incq %rax
cmpq $131072, %rax # imm = 0x20000
jne .LBB1_3
# %bb.4:
mulss .LCPI1_0(%rip), %xmm0
movss %xmm0, 20(%rsp) # 4-byte Spill
movl $.L.str, %edi
movl $1024, %esi # imm = 0x400
movl $256, %edx # imm = 0x100
movl $512, %ecx # imm = 0x200
xorl %eax, %eax
callq printf
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movl $.L.str.1, %edi
movb $2, %al
callq printf
xorl %eax, %eax
addq $524392, %rsp # imm = 0x80068
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5pi_mcPfP12hiprandState, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5pi_mcPfP12hiprandState,@object # @_Z5pi_mcPfP12hiprandState
.section .rodata,"a",@progbits
.globl _Z5pi_mcPfP12hiprandState
.p2align 3, 0x0
_Z5pi_mcPfP12hiprandState:
.quad _Z20__device_stub__pi_mcPfP12hiprandState
.size _Z5pi_mcPfP12hiprandState, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Trials per thread is: %d, number of blocks is: %d, number of threads is: %d\n"
.size .L.str, 77
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "CUDA estimate of PI = %f [error of %f]\n"
.size .L.str.1, 40
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5pi_mcPfP12hiprandState"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__pi_mcPfP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5pi_mcPfP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
unsigned int N = 1 << 12;
unsigned int N_p = N/4;
__global__
void mul(unsigned int n, unsigned int *x, unsigned int *y)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = x[i] * y[i];
}
int main(void)
{
unsigned int /**x, *y,*/ *d_x, *d_y;
int8_t *x, *y;
x = (int8_t*)malloc(N*sizeof(int8_t));
y = (int8_t*)malloc(N*sizeof(int8_t));
cudaMalloc(&d_x, N_p*sizeof(unsigned int));
cudaMalloc(&d_y, N_p*sizeof(unsigned int));
for (unsigned int i = 0; i < N; i++) {
x[i] = i%16;
y[i] = i%16;
}
cudaMemcpy(d_x, (unsigned int*) x, N_p*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, (unsigned int*) y, N_p*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
// Perform SAXPY on 1M elements
mul<<<(N_p+255)/256, 256>>>(N_p, d_x, d_y);
cudaDeviceSynchronize();
cudaMemcpy(y, d_y, N*sizeof(int8_t), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
y = (int8_t*) y;
int8_t maxError = 0;
for (unsigned int i = 0; i < N; i++) {
//maxError = max(maxError, (y[i]*y[i]-(int8_t)(((i%256*i%256)%256))));
if (y[i] != (int8_t)((i%16)*(i%16))%256)
printf("Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n", i,(int8_t)y[i], (int8_t)(x[i]*x[i]), ((i%16)*(i%16))%256);
}
printf("Max error: %d\n", maxError);
} | code for sm_80
Function : _Z3muljPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0005 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IMAD R7, R0, R3, RZ ; /* 0x0000000300077224 */
/* 0x004fca00078e02ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
unsigned int N = 1 << 12;
unsigned int N_p = N/4;
__global__
void mul(unsigned int n, unsigned int *x, unsigned int *y)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = x[i] * y[i];
}
int main(void)
{
unsigned int /**x, *y,*/ *d_x, *d_y;
int8_t *x, *y;
x = (int8_t*)malloc(N*sizeof(int8_t));
y = (int8_t*)malloc(N*sizeof(int8_t));
cudaMalloc(&d_x, N_p*sizeof(unsigned int));
cudaMalloc(&d_y, N_p*sizeof(unsigned int));
for (unsigned int i = 0; i < N; i++) {
x[i] = i%16;
y[i] = i%16;
}
cudaMemcpy(d_x, (unsigned int*) x, N_p*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, (unsigned int*) y, N_p*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
// Perform SAXPY on 1M elements
mul<<<(N_p+255)/256, 256>>>(N_p, d_x, d_y);
cudaDeviceSynchronize();
cudaMemcpy(y, d_y, N*sizeof(int8_t), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
y = (int8_t*) y;
int8_t maxError = 0;
for (unsigned int i = 0; i < N; i++) {
//maxError = max(maxError, (y[i]*y[i]-(int8_t)(((i%256*i%256)%256))));
if (y[i] != (int8_t)((i%16)*(i%16))%256)
printf("Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n", i,(int8_t)y[i], (int8_t)(x[i]*x[i]), ((i%16)*(i%16))%256);
}
printf("Max error: %d\n", maxError);
} | .file "tmpxft_00197819_00000000-6_mul_packed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3muljPjS_jPjS_
.type _Z25__device_stub__Z3muljPjS_jPjS_, @function
_Z25__device_stub__Z3muljPjS_jPjS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3muljPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z3muljPjS_jPjS_, .-_Z25__device_stub__Z3muljPjS_jPjS_
.globl _Z3muljPjS_
.type _Z3muljPjS_, @function
_Z3muljPjS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3muljPjS_jPjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3muljPjS_, .-_Z3muljPjS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Max error: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl N(%rip), %ebx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl N_p(%rip), %esi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl N_p(%rip), %esi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl N(%rip), %ecx
testl %ecx, %ecx
je .L12
movl %ecx, %ecx
movl $0, %eax
.L13:
movl %eax, %edx
andl $15, %edx
movb %dl, (%r12,%rax)
movb %dl, 0(%rbp,%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L13
.L12:
movl N_p(%rip), %edx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl N_p(%rip), %edx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl N_p(%rip), %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L14:
call cudaDeviceSynchronize@PLT
movl N(%rip), %edx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
cmpl $0, N(%rip)
je .L15
movl $0, %ebx
leaq .LC0(%rip), %r13
jmp .L17
.L22:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl N_p(%rip), %edi
call _Z25__device_stub__Z3muljPjS_jPjS_
jmp .L14
.L16:
addq $1, %rbx
cmpl N(%rip), %ebx
jnb .L15
.L17:
movsbl 0(%rbp,%rbx), %ecx
movl %ebx, %eax
andl $15, %eax
imull %eax, %eax
movsbl %al, %eax
cltd
shrl $24, %edx
addl %edx, %eax
movzbl %al, %eax
subl %edx, %eax
cmpl %eax, %ecx
je .L16
movl %ebx, %edx
movl %ebx, %r9d
andl $15, %r9d
movzbl (%r12,%rbx), %eax
imull %eax, %eax
imull %r9d, %r9d
movsbl %al, %r8d
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L15:
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3muljPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3muljPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_N, @function
_GLOBAL__sub_I_N:
.LFB2203:
.cfi_startproc
endbr64
movl N(%rip), %eax
shrl $2, %eax
movl %eax, N_p(%rip)
ret
.cfi_endproc
.LFE2203:
.size _GLOBAL__sub_I_N, .-_GLOBAL__sub_I_N
.section .init_array
.align 8
.quad _GLOBAL__sub_I_N
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl N_p
.bss
.align 4
.type N_p, @object
.size N_p, 4
N_p:
.zero 4
.globl N
.data
.align 4
.type N, @object
.size N, 4
N:
.long 4096
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
unsigned int N = 1 << 12;
unsigned int N_p = N/4;
__global__
void mul(unsigned int n, unsigned int *x, unsigned int *y)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = x[i] * y[i];
}
int main(void)
{
unsigned int /**x, *y,*/ *d_x, *d_y;
int8_t *x, *y;
x = (int8_t*)malloc(N*sizeof(int8_t));
y = (int8_t*)malloc(N*sizeof(int8_t));
cudaMalloc(&d_x, N_p*sizeof(unsigned int));
cudaMalloc(&d_y, N_p*sizeof(unsigned int));
for (unsigned int i = 0; i < N; i++) {
x[i] = i%16;
y[i] = i%16;
}
cudaMemcpy(d_x, (unsigned int*) x, N_p*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaMemcpy(d_y, (unsigned int*) y, N_p*sizeof(unsigned int), cudaMemcpyHostToDevice);
cudaDeviceSynchronize();
// Perform SAXPY on 1M elements
mul<<<(N_p+255)/256, 256>>>(N_p, d_x, d_y);
cudaDeviceSynchronize();
cudaMemcpy(y, d_y, N*sizeof(int8_t), cudaMemcpyDeviceToHost);
cudaDeviceSynchronize();
y = (int8_t*) y;
int8_t maxError = 0;
for (unsigned int i = 0; i < N; i++) {
//maxError = max(maxError, (y[i]*y[i]-(int8_t)(((i%256*i%256)%256))));
if (y[i] != (int8_t)((i%16)*(i%16))%256)
printf("Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n", i,(int8_t)y[i], (int8_t)(x[i]*x[i]), ((i%16)*(i%16))%256);
}
printf("Max error: %d\n", maxError);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
unsigned int N = 1 << 12;
unsigned int N_p = N/4;
__global__
void mul(unsigned int n, unsigned int *x, unsigned int *y)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = x[i] * y[i];
}
int main(void)
{
unsigned int /**x, *y,*/ *d_x, *d_y;
int8_t *x, *y;
x = (int8_t*)malloc(N*sizeof(int8_t));
y = (int8_t*)malloc(N*sizeof(int8_t));
hipMalloc(&d_x, N_p*sizeof(unsigned int));
hipMalloc(&d_y, N_p*sizeof(unsigned int));
for (unsigned int i = 0; i < N; i++) {
x[i] = i%16;
y[i] = i%16;
}
hipMemcpy(d_x, (unsigned int*) x, N_p*sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemcpy(d_y, (unsigned int*) y, N_p*sizeof(unsigned int), hipMemcpyHostToDevice);
hipDeviceSynchronize();
// Perform SAXPY on 1M elements
mul<<<(N_p+255)/256, 256>>>(N_p, d_x, d_y);
hipDeviceSynchronize();
hipMemcpy(y, d_y, N*sizeof(int8_t), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
y = (int8_t*) y;
int8_t maxError = 0;
for (unsigned int i = 0; i < N; i++) {
//maxError = max(maxError, (y[i]*y[i]-(int8_t)(((i%256*i%256)%256))));
if (y[i] != (int8_t)((i%16)*(i%16))%256)
printf("Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n", i,(int8_t)y[i], (int8_t)(x[i]*x[i]), ((i%16)*(i%16))%256);
}
printf("Max error: %d\n", maxError);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
unsigned int N = 1 << 12;
unsigned int N_p = N/4;
__global__
void mul(unsigned int n, unsigned int *x, unsigned int *y)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = x[i] * y[i];
}
int main(void)
{
unsigned int /**x, *y,*/ *d_x, *d_y;
int8_t *x, *y;
x = (int8_t*)malloc(N*sizeof(int8_t));
y = (int8_t*)malloc(N*sizeof(int8_t));
hipMalloc(&d_x, N_p*sizeof(unsigned int));
hipMalloc(&d_y, N_p*sizeof(unsigned int));
for (unsigned int i = 0; i < N; i++) {
x[i] = i%16;
y[i] = i%16;
}
hipMemcpy(d_x, (unsigned int*) x, N_p*sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemcpy(d_y, (unsigned int*) y, N_p*sizeof(unsigned int), hipMemcpyHostToDevice);
hipDeviceSynchronize();
// Perform SAXPY on 1M elements
mul<<<(N_p+255)/256, 256>>>(N_p, d_x, d_y);
hipDeviceSynchronize();
hipMemcpy(y, d_y, N*sizeof(int8_t), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
y = (int8_t*) y;
int8_t maxError = 0;
for (unsigned int i = 0; i < N; i++) {
//maxError = max(maxError, (y[i]*y[i]-(int8_t)(((i%256*i%256)%256))));
if (y[i] != (int8_t)((i%16)*(i%16))%256)
printf("Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n", i,(int8_t)y[i], (int8_t)(x[i]*x[i]), ((i%16)*(i%16))%256);
}
printf("Max error: %d\n", maxError);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3muljPjS_
.globl _Z3muljPjS_
.p2align 8
.type _Z3muljPjS_,@function
_Z3muljPjS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3muljPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3muljPjS_, .Lfunc_end0-_Z3muljPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3muljPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3muljPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
unsigned int N = 1 << 12;
unsigned int N_p = N/4;
__global__
void mul(unsigned int n, unsigned int *x, unsigned int *y)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
if (i < n) y[i] = x[i] * y[i];
}
int main(void)
{
unsigned int /**x, *y,*/ *d_x, *d_y;
int8_t *x, *y;
x = (int8_t*)malloc(N*sizeof(int8_t));
y = (int8_t*)malloc(N*sizeof(int8_t));
hipMalloc(&d_x, N_p*sizeof(unsigned int));
hipMalloc(&d_y, N_p*sizeof(unsigned int));
for (unsigned int i = 0; i < N; i++) {
x[i] = i%16;
y[i] = i%16;
}
hipMemcpy(d_x, (unsigned int*) x, N_p*sizeof(unsigned int), hipMemcpyHostToDevice);
hipMemcpy(d_y, (unsigned int*) y, N_p*sizeof(unsigned int), hipMemcpyHostToDevice);
hipDeviceSynchronize();
// Perform SAXPY on 1M elements
mul<<<(N_p+255)/256, 256>>>(N_p, d_x, d_y);
hipDeviceSynchronize();
hipMemcpy(y, d_y, N*sizeof(int8_t), hipMemcpyDeviceToHost);
hipDeviceSynchronize();
y = (int8_t*) y;
int8_t maxError = 0;
for (unsigned int i = 0; i < N; i++) {
//maxError = max(maxError, (y[i]*y[i]-(int8_t)(((i%256*i%256)%256))));
if (y[i] != (int8_t)((i%16)*(i%16))%256)
printf("Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n", i,(int8_t)y[i], (int8_t)(x[i]*x[i]), ((i%16)*(i%16))%256);
}
printf("Max error: %d\n", maxError);
} | .text
.file "mul_packed.hip"
.globl _Z18__device_stub__muljPjS_ # -- Begin function _Z18__device_stub__muljPjS_
.p2align 4, 0x90
.type _Z18__device_stub__muljPjS_,@function
_Z18__device_stub__muljPjS_: # @_Z18__device_stub__muljPjS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3muljPjS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__muljPjS_, .Lfunc_end0-_Z18__device_stub__muljPjS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl N(%rip), %r14d
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl N_p(%rip), %esi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl N_p(%rip), %esi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl N(%rip), %eax
testq %rax, %rax
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, %edx
andb $15, %dl
movb %dl, (%rbx,%rcx)
movb %dl, (%r14,%rcx)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq 24(%rsp), %rdi
movl N_p(%rip), %edx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl N_p(%rip), %edx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movl $255, %edi
addl N_p(%rip), %edi
shrl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movl N_p(%rip), %eax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movl %eax, 20(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3muljPjS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl N(%rip), %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
cmpl $0, N(%rip)
je .LBB1_10
# %bb.6: # %.lr.ph39.preheader
xorl %r15d, %r15d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
incq %r15
movl N(%rip), %eax
cmpq %rax, %r15
jae .LBB1_10
.LBB1_7: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movsbl (%r14,%r15), %edx
movl %r15d, %r8d
andl $15, %r8d
imull %r8d, %r8d
movsbl %r8b, %eax
cmpl %edx, %eax
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movzbl (%rbx,%r15), %eax
mulb %al
movsbl %al, %ecx
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_9
.LBB1_10: # %._crit_edge40
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3muljPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 4096 # 0x1000
.size N, 4
.type N_p,@object # @N_p
.globl N_p
.p2align 2, 0x0
N_p:
.long 1024 # 0x400
.size N_p, 4
.type _Z3muljPjS_,@object # @_Z3muljPjS_
.section .rodata,"a",@progbits
.globl _Z3muljPjS_
.p2align 3, 0x0
_Z3muljPjS_:
.quad _Z18__device_stub__muljPjS_
.size _Z3muljPjS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n"
.size .L.str, 65
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: %d\n"
.size .L.str.1, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3muljPjS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__muljPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3muljPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3muljPjS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x160], PT ; /* 0x0000580004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe400078e0005 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ IMAD R7, R0, R3, RZ ; /* 0x0000000300077224 */
/* 0x004fca00078e02ff */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3muljPjS_
.globl _Z3muljPjS_
.p2align 8
.type _Z3muljPjS_,@function
_Z3muljPjS_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x8
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3muljPjS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3muljPjS_, .Lfunc_end0-_Z3muljPjS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3muljPjS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3muljPjS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00197819_00000000-6_mul_packed.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z25__device_stub__Z3muljPjS_jPjS_
.type _Z25__device_stub__Z3muljPjS_jPjS_, @function
_Z25__device_stub__Z3muljPjS_jPjS_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3muljPjS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z25__device_stub__Z3muljPjS_jPjS_, .-_Z25__device_stub__Z3muljPjS_jPjS_
.globl _Z3muljPjS_
.type _Z3muljPjS_, @function
_Z3muljPjS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z3muljPjS_jPjS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3muljPjS_, .-_Z3muljPjS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Max error: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl N(%rip), %ebx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r12
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl N_p(%rip), %esi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
movl N_p(%rip), %esi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl N(%rip), %ecx
testl %ecx, %ecx
je .L12
movl %ecx, %ecx
movl $0, %eax
.L13:
movl %eax, %edx
andl $15, %edx
movb %dl, (%r12,%rax)
movb %dl, 0(%rbp,%rax)
addq $1, %rax
cmpq %rcx, %rax
jne .L13
.L12:
movl N_p(%rip), %edx
salq $2, %rdx
movl $1, %ecx
movq %r12, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl N_p(%rip), %edx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
movl $256, 28(%rsp)
movl $1, 32(%rsp)
movl N_p(%rip), %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L14:
call cudaDeviceSynchronize@PLT
movl N(%rip), %edx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaDeviceSynchronize@PLT
cmpl $0, N(%rip)
je .L15
movl $0, %ebx
leaq .LC0(%rip), %r13
jmp .L17
.L22:
movq 8(%rsp), %rdx
movq (%rsp), %rsi
movl N_p(%rip), %edi
call _Z25__device_stub__Z3muljPjS_jPjS_
jmp .L14
.L16:
addq $1, %rbx
cmpl N(%rip), %ebx
jnb .L15
.L17:
movsbl 0(%rbp,%rbx), %ecx
movl %ebx, %eax
andl $15, %eax
imull %eax, %eax
movsbl %al, %eax
cltd
shrl $24, %edx
addl %edx, %eax
movzbl %al, %eax
subl %edx, %eax
cmpl %eax, %ecx
je .L16
movl %ebx, %edx
movl %ebx, %r9d
andl $15, %r9d
movzbl (%r12,%rbx), %eax
imull %eax, %eax
imull %r9d, %r9d
movsbl %al, %r8d
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L15:
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3muljPjS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3muljPjS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.text
.type _GLOBAL__sub_I_N, @function
_GLOBAL__sub_I_N:
.LFB2203:
.cfi_startproc
endbr64
movl N(%rip), %eax
shrl $2, %eax
movl %eax, N_p(%rip)
ret
.cfi_endproc
.LFE2203:
.size _GLOBAL__sub_I_N, .-_GLOBAL__sub_I_N
.section .init_array
.align 8
.quad _GLOBAL__sub_I_N
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl N_p
.bss
.align 4
.type N_p, @object
.size N_p, 4
N_p:
.zero 4
.globl N
.data
.align 4
.type N, @object
.size N, 4
N:
.long 4096
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mul_packed.hip"
.globl _Z18__device_stub__muljPjS_ # -- Begin function _Z18__device_stub__muljPjS_
.p2align 4, 0x90
.type _Z18__device_stub__muljPjS_,@function
_Z18__device_stub__muljPjS_: # @_Z18__device_stub__muljPjS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3muljPjS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__muljPjS_, .Lfunc_end0-_Z18__device_stub__muljPjS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl N(%rip), %r14d
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
callq malloc
movq %rax, %r14
movl N_p(%rip), %esi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl N_p(%rip), %esi
shlq $2, %rsi
leaq 8(%rsp), %rdi
callq hipMalloc
movl N(%rip), %eax
testq %rax, %rax
je .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl %ecx, %edx
andb $15, %dl
movb %dl, (%rbx,%rcx)
movb %dl, (%r14,%rcx)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
movq 24(%rsp), %rdi
movl N_p(%rip), %edx
shlq $2, %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl N_p(%rip), %edx
shlq $2, %rdx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
movl $255, %edi
addl N_p(%rip), %edi
shrl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movl N_p(%rip), %eax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movl %eax, 20(%rsp)
movq %rcx, 88(%rsp)
movq %rdx, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3muljPjS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl N(%rip), %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipDeviceSynchronize
cmpl $0, N(%rip)
je .LBB1_10
# %bb.6: # %.lr.ph39.preheader
xorl %r15d, %r15d
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_7 Depth=1
incq %r15
movl N(%rip), %eax
cmpq %rax, %r15
jae .LBB1_10
.LBB1_7: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movsbl (%r14,%r15), %edx
movl %r15d, %r8d
andl $15, %r8d
imull %r8d, %r8d
movsbl %r8b, %eax
cmpl %edx, %eax
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_7 Depth=1
movzbl (%rbx,%r15), %eax
mulb %al
movsbl %al, %ecx
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
jmp .LBB1_9
.LBB1_10: # %._crit_edge40
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3muljPjS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.data
.globl N
.p2align 2, 0x0
N:
.long 4096 # 0x1000
.size N, 4
.type N_p,@object # @N_p
.globl N_p
.p2align 2, 0x0
N_p:
.long 1024 # 0x400
.size N_p, 4
.type _Z3muljPjS_,@object # @_Z3muljPjS_
.section .rodata,"a",@progbits
.globl _Z3muljPjS_
.p2align 3, 0x0
_Z3muljPjS_:
.quad _Z18__device_stub__muljPjS_
.size _Z3muljPjS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elements at pos %d not matching: y[i]=%x, expected = %x, i*i=%x\n"
.size .L.str, 65
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Max error: %d\n"
.size .L.str.1, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3muljPjS_"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__muljPjS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3muljPjS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/functional.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/sequence.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <chrono>
using namespace std;
using sys_clock = std::chrono::system_clock;
/// used to fill a host vector
struct rand_functor
{
int mod = 0;
rand_functor(int _mod = 0) : mod(_mod) { std::srand(std::time(0)); }
template<typename T>
void operator()(T &var)
{
if(mod > 0)
var = std::rand() % mod;
else
var = std::rand();
}
};
struct matrix_mult
{
/// Fill the structure
int * data;
matrix_mult(int* _data): data(_data){}
template <typename Tuple>
__host__ __device__
void operator()( Tuple t){
thrust::get<3>(t) = thrust::get<0>(t) * thrust::get<2>(t) + data[thrust::get<2>(t)];
}
};
void cpu_matrix_mult(float *A, float *B, float *C, int row_size, int col_size)
{
int N= row_size;
/// CPU matrix mult
for(int i=0; i<N; ++i)
for(int j=0; j<N; ++j)
for(int k=0; k<N; ++k)
C[i*N+j] += A[i*N+k] * B[k*N + j];
}
void print_matrix(float *A, int row_size, int col_size)
{
std::cout << "\n";
for(int i = 0; i < row_size; i++)
{
for(int j = 0; j <col_size; j++)
{
std::cout << A[i * col_size + j] << " ";
}
std::cout << "\n";
}
}
void thrust_matrix_mult(const int row_size, const int col_size)
{
const int matrix_size = col_size * row_size;
std::chrono::time_point<sys_clock> t1, t2;
std::chrono::duration<double, std::milli> exec_time_ms;
/// These are for the CPU matrix mult
float *A = (float*)malloc(sizeof(float) * matrix_size);
float *B = (float*)malloc(sizeof(float) * matrix_size);
float *C = (float*)malloc(sizeof(float) * matrix_size);
/// Vectors for the thrust matrix mult
thrust::host_vector<float> result(matrix_size);
thrust::host_vector<float> matrix_hA(matrix_size), matrix_hB(matrix_size);
thrust::device_vector<float> matrix_A(matrix_size), matrix_B(matrix_size), matrix_C(matrix_size, 0.0f);
thrust::device_vector<int> ids(matrix_size),data(matrix_size);
thrust::sequence(ids.begin(),ids.end(),1,1);
thrust::sequence(data.begin(),data.end(),1,1);
/// Additional variables you may need
thrust::for_each(matrix_hA.begin(), matrix_hA.end(), rand_functor(10));
thrust::for_each(matrix_hB.begin(), matrix_hB.end(), rand_functor(10));
matrix_A = matrix_hA;
matrix_B = matrix_hB;
thrust::copy(matrix_A.begin(), matrix_A.end(), A);
thrust::copy(matrix_B.begin(), matrix_B.end(), B);
t1 = sys_clock::now();
cpu_matrix_mult(A, B, C, row_size, col_size);
t2 = sys_clock::now();
exec_time_ms = t2 - t1;
std::cout << "CPU mm time: " << exec_time_ms.count() << "ms\n";
t1 = sys_clock::now();
/// Thrust code!
thrust::for_each(
thrust::make_zip_iterator(thrust::make_tuple(matrix_A.begin(),matrix_B.begin(),ids.begin(),matrix_C.begin())),
thrust::make_zip_iterator(thrust::make_tuple(matrix_A.end(),matrix_B.end(),ids.end(),matrix_C.end())),
matrix_mult(thrust::raw_pointer_cast(data.data()))
);
/*
thrust::for_each(
thrust::make_zip_iterator(thrust::make_tuple(A.begin(),B.begin(),ids.begin(),res.begin())),
thrust::make_zip_iterator(thrust::make_tuple(A.end(),B.end(),ids.end(),res.end())),
functor_add(thrust::raw_pointer_cast(data.data()))
);
*/
result = matrix_C;
t2 = sys_clock::now();
exec_time_ms = t2 - t1;
std::cout << "Thrust GPU mm time: " << exec_time_ms.count() << "ms\n";
std::cout << "\nChecking Matrices" << std::endl;
// Compare matrices (CPU & thrust) for correctness
bool tutzke =true;
for(int kuz =0; kuz < col_size; kuz++){
if(C[kuz] == result[kuz]){
tutzke = false;
break;
}
}
if(tutzke){
cout << "matrix match!" << endl;
}else{
cout << "jaja nice try" << endl;
}
}
int main(int argc, char* argv[])
{
if (argc < 2)
thrust_matrix_mult(50, 50);
else
thrust_matrix_mult(atoi(argv[1]), atoi(argv[1]));
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElNS2_12op_wrapper_tIl11matrix_multN6thrust20THRUST_200700_800_NS12zip_iteratorINS9_5tupleIJNS9_6detail15normal_iteratorINS9_10device_ptrIfEEEESG_NSD_INSE_IiEEEESG_EEEEEEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R0, P1, R2.reuse, R9, RZ ; /* 0x0000000902007210 */
/* 0x042fe40007f3e0ff */
/*0060*/ IADD3 R8, P0, -R2, c[0x0][0x160], RZ ; /* 0x0000580002087a10 */
/* 0x000fc60007f1e1ff */
/*0070*/ IMAD.X R5, RZ, RZ, R3, P1 ; /* 0x000000ffff057224 */
/* 0x000fe200008e0603 */
/*0080*/ IADD3.X R3, ~R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590003037a10 */
/* 0x000fe200007fe5ff */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x4, RZ ; /* 0x0000000400027824 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GT.U32.AND P0, PT, R8, 0x1ff, PT ; /* 0x000001ff0800780c */
/* 0x000fe40003f04070 */
/*00b0*/ SHF.L.U64.HI R0, R0, 0x2, R5 ; /* 0x0000000200007819 */
/* 0x000fe40000010205 */
/*00c0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*00d0*/ IADD3 R4, P1, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002047a10 */
/* 0x040fe40007f3e0ff */
/*00e0*/ IADD3 R6, P2, R2, c[0x0][0x178], RZ ; /* 0x00005e0002067a10 */
/* 0x000fc40007f5e0ff */
/*00f0*/ IADD3 R2, P3, R2, c[0x0][0x180], RZ ; /* 0x0000600002027a10 */
/* 0x000fe40007f7e0ff */
/*0100*/ IADD3.X R5, R0.reuse, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0000057a10 */
/* 0x040fe40000ffe4ff */
/*0110*/ IADD3.X R7, R0.reuse, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f0000077a10 */
/* 0x040fe400017fe4ff */
/*0120*/ IADD3.X R3, R0, c[0x0][0x184], RZ, P3, !PT ; /* 0x0000610000037a10 */
/* 0x000fe20001ffe4ff */
/*0130*/ @P0 BRA 0x310 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0140*/ IADD3 R0, R9, 0x100, RZ ; /* 0x0000010009007810 */
/* 0x000fe20007ffe0ff */
/*0150*/ BSSY B0, 0x260 ; /* 0x0000010000007945 */
/* 0x000fe20003800000 */
/*0160*/ ISETP.GT.U32.AND P0, PT, R8, R9, PT ; /* 0x000000090800720c */
/* 0x000fe40003f04070 */
/*0170*/ SHF.R.S32.HI R9, RZ, 0x1f, R8 ; /* 0x0000001fff097819 */
/* 0x000fc40000011408 */
/*0180*/ ISETP.GT.U32.AND P1, PT, R8, R0, PT ; /* 0x000000000800720c */
/* 0x000fe40003f24070 */
/*0190*/ ISETP.GT.AND.EX P0, PT, R9.reuse, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x040fe40003f04300 */
/*01a0*/ ISETP.GT.AND.EX P1, PT, R9, RZ, PT, P1 ; /* 0x000000ff0900720c */
/* 0x000fd60003f24310 */
/*01b0*/ @!P0 BRA 0x250 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*01c0*/ LDG.E R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ea2000c1e1900 */
/*01d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc600078e00ff */
/*01e0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee2000c1e1900 */
/*01f0*/ IMAD.WIDE R8, R10, R9, c[0x0][0x188] ; /* 0x000062000a087625 */
/* 0x004fcc00078e0209 */
/*0200*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0210*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x000ff00000201400 */
/*0220*/ I2F R12, R8 ; /* 0x00000008000c7306 */
/* 0x004ee40000201400 */
/*0230*/ FFMA R11, R0, R11, R12 ; /* 0x0000000b000b7223 */
/* 0x008fca000000000c */
/*0240*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0001e4000c101904 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0270*/ LDG.E R6, [R6.64+0x400] ; /* 0x0004000406067981 */
/* 0x000ea2000c1e1900 */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc600078e00ff */
/*0290*/ LDG.E R5, [R4.64+0x400] ; /* 0x0004000404057981 */
/* 0x000ee2000c1e1900 */
/*02a0*/ IMAD.WIDE R8, R6, R9, c[0x0][0x188] ; /* 0x0000620006087625 */
/* 0x004fcc00078e0209 */
/*02b0*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*02c0*/ I2F R0, R6 ; /* 0x0000000600007306 */
/* 0x000ff00000201400 */
/*02d0*/ I2F R10, R8 ; /* 0x00000008000a7306 */
/* 0x004ee40000201400 */
/*02e0*/ FFMA R11, R0, R5, R10 ; /* 0x00000005000b7223 */
/* 0x009fca000000000a */
/*02f0*/ STG.E [R2.64+0x400], R11 ; /* 0x0004000b02007986 */
/* 0x000fe2000c101904 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea2000c1e1900 */
/*0320*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc600078e00ff */
/*0330*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ee2000c1e1900 */
/*0340*/ IMAD.WIDE R8, R12, R15, c[0x0][0x188] ; /* 0x000062000c087625 */
/* 0x004fcc00078e020f */
/*0350*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1900 */
/*0360*/ I2F R11, R12 ; /* 0x0000000c000b7306 */
/* 0x000ff00000201400 */
/*0370*/ I2F R10, R8 ; /* 0x00000008000a7306 */
/* 0x004ee40000201400 */
/*0380*/ FFMA R13, R0, R11, R10 ; /* 0x0000000b000d7223 */
/* 0x008fca000000000a */
/*0390*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101904 */
/*03a0*/ LDG.E R0, [R6.64+0x400] ; /* 0x0004000406007981 */
/* 0x000ea4000c1e1900 */
/*03b0*/ IMAD.WIDE R10, R0, R15, c[0x0][0x188] ; /* 0x00006200000a7625 */
/* 0x004fe400078e020f */
/*03c0*/ LDG.E R15, [R4.64+0x400] ; /* 0x00040004040f7981 */
/* 0x000ea8000c1e1900 */
/*03d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ee2000c1e1900 */
/*03e0*/ I2F R0, R0 ; /* 0x0000000000007306 */
/* 0x000ff00000201400 */
/*03f0*/ I2F R9, R10 ; /* 0x0000000a00097306 */
/* 0x008ea40000201400 */
/*0400*/ FFMA R9, R0, R15, R9 ; /* 0x0000000f00097223 */
/* 0x004fca0000000009 */
/*0410*/ STG.E [R2.64+0x400], R9 ; /* 0x0004000902007986 */
/* 0x000fe2000c101904 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tElN6thrust20THRUST_200700_800_NS8cuda_cub10__tabulate7functorINS7_6detail15normal_iteratorINS7_10device_ptrIiEEEENS7_6system6detail7generic6detail22compute_sequence_valueIivEElEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R4, R4, 0x200, RZ ; /* 0x0000020004047825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R6, P1, -R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004067a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R7, P2, R4, R9, RZ ; /* 0x0000000904077210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ff, PT ; /* 0x000001ff0600780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R3, ~R5, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005037a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R0, RZ, RZ, R5, P2 ; /* 0x000000ffff007224 */
/* 0x000fe200010e0605 */
/*00a0*/ LEA R2, P1, R7, c[0x0][0x168], 0x2 ; /* 0x00005a0007027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fc40003f04300 */
/*00c0*/ LEA.HI.X R3, R7, c[0x0][0x16c], R0, 0x2, P1 ; /* 0x00005b0007037a11 */
/* 0x000fd600008f1400 */
/*00d0*/ @P0 BRA 0x1d0 ; /* 0x000000f000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R8, RZ, 0x1f, R6 ; /* 0x0000001fff087819 */
/* 0x000fe40000011406 */
/*0100*/ IADD3 R9, R9, 0x100, RZ ; /* 0x0000010009097810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04300 */
/*0120*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff000624 */
/* 0x000fc800078e00ff */
/*0130*/ @P0 IMAD R7, R7, R0, c[0x0][0x170] ; /* 0x00005c0007070624 */
/* 0x000fca00078e0200 */
/*0140*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fc80003f04070 */
/*0160*/ ISETP.GT.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f04300 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ IMAD.IADD R5, R4, 0x1, R9 ; /* 0x0000000104057824 */
/* 0x001fe400078e0209 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD R5, R5, R0, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fca00078e0200 */
/*01b0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01d0*/ IADD3 R5, R4, 0x100, R9 ; /* 0x0000010004057810 */
/* 0x000fe20007ffe009 */
/*01e0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc800078e00ff */
/*01f0*/ IMAD R7, R7, R0.reuse, c[0x0][0x170] ; /* 0x00005c0007077624 */
/* 0x080fe400078e0200 */
/*0200*/ IMAD R5, R5, R0, c[0x0][0x170] ; /* 0x00005c0005057624 */
/* 0x000fc600078e0200 */
/*0210*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101904 */
/*0220*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ BRA 0x240; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIiEEiEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/functional.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/sequence.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <chrono>
using namespace std;
using sys_clock = std::chrono::system_clock;
/// used to fill a host vector
struct rand_functor
{
int mod = 0;
rand_functor(int _mod = 0) : mod(_mod) { std::srand(std::time(0)); }
template<typename T>
void operator()(T &var)
{
if(mod > 0)
var = std::rand() % mod;
else
var = std::rand();
}
};
struct matrix_mult
{
/// Fill the structure
int * data;
matrix_mult(int* _data): data(_data){}
template <typename Tuple>
__host__ __device__
void operator()( Tuple t){
thrust::get<3>(t) = thrust::get<0>(t) * thrust::get<2>(t) + data[thrust::get<2>(t)];
}
};
void cpu_matrix_mult(float *A, float *B, float *C, int row_size, int col_size)
{
int N= row_size;
/// CPU matrix mult
for(int i=0; i<N; ++i)
for(int j=0; j<N; ++j)
for(int k=0; k<N; ++k)
C[i*N+j] += A[i*N+k] * B[k*N + j];
}
void print_matrix(float *A, int row_size, int col_size)
{
std::cout << "\n";
for(int i = 0; i < row_size; i++)
{
for(int j = 0; j <col_size; j++)
{
std::cout << A[i * col_size + j] << " ";
}
std::cout << "\n";
}
}
void thrust_matrix_mult(const int row_size, const int col_size)
{
const int matrix_size = col_size * row_size;
std::chrono::time_point<sys_clock> t1, t2;
std::chrono::duration<double, std::milli> exec_time_ms;
/// These are for the CPU matrix mult
float *A = (float*)malloc(sizeof(float) * matrix_size);
float *B = (float*)malloc(sizeof(float) * matrix_size);
float *C = (float*)malloc(sizeof(float) * matrix_size);
/// Vectors for the thrust matrix mult
thrust::host_vector<float> result(matrix_size);
thrust::host_vector<float> matrix_hA(matrix_size), matrix_hB(matrix_size);
thrust::device_vector<float> matrix_A(matrix_size), matrix_B(matrix_size), matrix_C(matrix_size, 0.0f);
thrust::device_vector<int> ids(matrix_size),data(matrix_size);
thrust::sequence(ids.begin(),ids.end(),1,1);
thrust::sequence(data.begin(),data.end(),1,1);
/// Additional variables you may need
thrust::for_each(matrix_hA.begin(), matrix_hA.end(), rand_functor(10));
thrust::for_each(matrix_hB.begin(), matrix_hB.end(), rand_functor(10));
matrix_A = matrix_hA;
matrix_B = matrix_hB;
thrust::copy(matrix_A.begin(), matrix_A.end(), A);
thrust::copy(matrix_B.begin(), matrix_B.end(), B);
t1 = sys_clock::now();
cpu_matrix_mult(A, B, C, row_size, col_size);
t2 = sys_clock::now();
exec_time_ms = t2 - t1;
std::cout << "CPU mm time: " << exec_time_ms.count() << "ms\n";
t1 = sys_clock::now();
/// Thrust code!
thrust::for_each(
thrust::make_zip_iterator(thrust::make_tuple(matrix_A.begin(),matrix_B.begin(),ids.begin(),matrix_C.begin())),
thrust::make_zip_iterator(thrust::make_tuple(matrix_A.end(),matrix_B.end(),ids.end(),matrix_C.end())),
matrix_mult(thrust::raw_pointer_cast(data.data()))
);
/*
thrust::for_each(
thrust::make_zip_iterator(thrust::make_tuple(A.begin(),B.begin(),ids.begin(),res.begin())),
thrust::make_zip_iterator(thrust::make_tuple(A.end(),B.end(),ids.end(),res.end())),
functor_add(thrust::raw_pointer_cast(data.data()))
);
*/
result = matrix_C;
t2 = sys_clock::now();
exec_time_ms = t2 - t1;
std::cout << "Thrust GPU mm time: " << exec_time_ms.count() << "ms\n";
std::cout << "\nChecking Matrices" << std::endl;
// Compare matrices (CPU & thrust) for correctness
bool tutzke =true;
for(int kuz =0; kuz < col_size; kuz++){
if(C[kuz] == result[kuz]){
tutzke = false;
break;
}
}
if(tutzke){
cout << "matrix match!" << endl;
}else{
cout << "jaja nice try" << endl;
}
}
int main(int argc, char* argv[])
{
if (argc < 2)
thrust_matrix_mult(50, 50);
else
thrust_matrix_mult(atoi(argv[1]), atoi(argv[1]));
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/functional.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/sequence.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <chrono>
using namespace std;
using sys_clock = std::chrono::system_clock;
/// used to fill a host vector
struct rand_functor
{
int mod = 0;
rand_functor(int _mod = 0) : mod(_mod) { std::srand(std::time(0)); }
template<typename T>
void operator()(T &var)
{
if(mod > 0)
var = std::rand() % mod;
else
var = std::rand();
}
};
struct matrix_mult
{
/// Fill the structure
int * data;
matrix_mult(int* _data): data(_data){}
template <typename Tuple>
__host__ __device__
void operator()( Tuple t){
thrust::get<3>(t) = thrust::get<0>(t) * thrust::get<2>(t) + data[thrust::get<2>(t)];
}
};
void cpu_matrix_mult(float *A, float *B, float *C, int row_size, int col_size)
{
int N= row_size;
/// CPU matrix mult
for(int i=0; i<N; ++i)
for(int j=0; j<N; ++j)
for(int k=0; k<N; ++k)
C[i*N+j] += A[i*N+k] * B[k*N + j];
}
void print_matrix(float *A, int row_size, int col_size)
{
std::cout << "\n";
for(int i = 0; i < row_size; i++)
{
for(int j = 0; j <col_size; j++)
{
std::cout << A[i * col_size + j] << " ";
}
std::cout << "\n";
}
}
void thrust_matrix_mult(const int row_size, const int col_size)
{
const int matrix_size = col_size * row_size;
std::chrono::time_point<sys_clock> t1, t2;
std::chrono::duration<double, std::milli> exec_time_ms;
/// These are for the CPU matrix mult
float *A = (float*)malloc(sizeof(float) * matrix_size);
float *B = (float*)malloc(sizeof(float) * matrix_size);
float *C = (float*)malloc(sizeof(float) * matrix_size);
/// Vectors for the thrust matrix mult
thrust::host_vector<float> result(matrix_size);
thrust::host_vector<float> matrix_hA(matrix_size), matrix_hB(matrix_size);
thrust::device_vector<float> matrix_A(matrix_size), matrix_B(matrix_size), matrix_C(matrix_size, 0.0f);
thrust::device_vector<int> ids(matrix_size),data(matrix_size);
thrust::sequence(ids.begin(),ids.end(),1,1);
thrust::sequence(data.begin(),data.end(),1,1);
/// Additional variables you may need
thrust::for_each(matrix_hA.begin(), matrix_hA.end(), rand_functor(10));
thrust::for_each(matrix_hB.begin(), matrix_hB.end(), rand_functor(10));
matrix_A = matrix_hA;
matrix_B = matrix_hB;
thrust::copy(matrix_A.begin(), matrix_A.end(), A);
thrust::copy(matrix_B.begin(), matrix_B.end(), B);
t1 = sys_clock::now();
cpu_matrix_mult(A, B, C, row_size, col_size);
t2 = sys_clock::now();
exec_time_ms = t2 - t1;
std::cout << "CPU mm time: " << exec_time_ms.count() << "ms\n";
t1 = sys_clock::now();
/// Thrust code!
thrust::for_each(
thrust::make_zip_iterator(thrust::make_tuple(matrix_A.begin(),matrix_B.begin(),ids.begin(),matrix_C.begin())),
thrust::make_zip_iterator(thrust::make_tuple(matrix_A.end(),matrix_B.end(),ids.end(),matrix_C.end())),
matrix_mult(thrust::raw_pointer_cast(data.data()))
);
/*
thrust::for_each(
thrust::make_zip_iterator(thrust::make_tuple(A.begin(),B.begin(),ids.begin(),res.begin())),
thrust::make_zip_iterator(thrust::make_tuple(A.end(),B.end(),ids.end(),res.end())),
functor_add(thrust::raw_pointer_cast(data.data()))
);
*/
result = matrix_C;
t2 = sys_clock::now();
exec_time_ms = t2 - t1;
std::cout << "Thrust GPU mm time: " << exec_time_ms.count() << "ms\n";
std::cout << "\nChecking Matrices" << std::endl;
// Compare matrices (CPU & thrust) for correctness
bool tutzke =true;
for(int kuz =0; kuz < col_size; kuz++){
if(C[kuz] == result[kuz]){
tutzke = false;
break;
}
}
if(tutzke){
cout << "matrix match!" << endl;
}else{
cout << "jaja nice try" << endl;
}
}
int main(int argc, char* argv[])
{
if (argc < 2)
thrust_matrix_mult(50, 50);
else
thrust_matrix_mult(atoi(argv[1]), atoi(argv[1]));
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
#include <thrust/copy.h>
#include <thrust/functional.h>
#include <thrust/iterator/zip_iterator.h>
#include <thrust/sequence.h>
#include <iostream>
#include <cstdlib>
#include <ctime>
#include <chrono>
using namespace std;
using sys_clock = std::chrono::system_clock;
/// used to fill a host vector
struct rand_functor
{
int mod = 0;
rand_functor(int _mod = 0) : mod(_mod) { std::srand(std::time(0)); }
template<typename T>
void operator()(T &var)
{
if(mod > 0)
var = std::rand() % mod;
else
var = std::rand();
}
};
struct matrix_mult
{
/// Fill the structure
int * data;
matrix_mult(int* _data): data(_data){}
template <typename Tuple>
__host__ __device__
void operator()( Tuple t){
thrust::get<3>(t) = thrust::get<0>(t) * thrust::get<2>(t) + data[thrust::get<2>(t)];
}
};
void cpu_matrix_mult(float *A, float *B, float *C, int row_size, int col_size)
{
int N= row_size;
/// CPU matrix mult
for(int i=0; i<N; ++i)
for(int j=0; j<N; ++j)
for(int k=0; k<N; ++k)
C[i*N+j] += A[i*N+k] * B[k*N + j];
}
void print_matrix(float *A, int row_size, int col_size)
{
std::cout << "\n";
for(int i = 0; i < row_size; i++)
{
for(int j = 0; j <col_size; j++)
{
std::cout << A[i * col_size + j] << " ";
}
std::cout << "\n";
}
}
void thrust_matrix_mult(const int row_size, const int col_size)
{
const int matrix_size = col_size * row_size;
std::chrono::time_point<sys_clock> t1, t2;
std::chrono::duration<double, std::milli> exec_time_ms;
/// These are for the CPU matrix mult
float *A = (float*)malloc(sizeof(float) * matrix_size);
float *B = (float*)malloc(sizeof(float) * matrix_size);
float *C = (float*)malloc(sizeof(float) * matrix_size);
/// Vectors for the thrust matrix mult
thrust::host_vector<float> result(matrix_size);
thrust::host_vector<float> matrix_hA(matrix_size), matrix_hB(matrix_size);
thrust::device_vector<float> matrix_A(matrix_size), matrix_B(matrix_size), matrix_C(matrix_size, 0.0f);
thrust::device_vector<int> ids(matrix_size),data(matrix_size);
thrust::sequence(ids.begin(),ids.end(),1,1);
thrust::sequence(data.begin(),data.end(),1,1);
/// Additional variables you may need
thrust::for_each(matrix_hA.begin(), matrix_hA.end(), rand_functor(10));
thrust::for_each(matrix_hB.begin(), matrix_hB.end(), rand_functor(10));
matrix_A = matrix_hA;
matrix_B = matrix_hB;
thrust::copy(matrix_A.begin(), matrix_A.end(), A);
thrust::copy(matrix_B.begin(), matrix_B.end(), B);
t1 = sys_clock::now();
cpu_matrix_mult(A, B, C, row_size, col_size);
t2 = sys_clock::now();
exec_time_ms = t2 - t1;
std::cout << "CPU mm time: " << exec_time_ms.count() << "ms\n";
t1 = sys_clock::now();
/// Thrust code!
thrust::for_each(
thrust::make_zip_iterator(thrust::make_tuple(matrix_A.begin(),matrix_B.begin(),ids.begin(),matrix_C.begin())),
thrust::make_zip_iterator(thrust::make_tuple(matrix_A.end(),matrix_B.end(),ids.end(),matrix_C.end())),
matrix_mult(thrust::raw_pointer_cast(data.data()))
);
/*
thrust::for_each(
thrust::make_zip_iterator(thrust::make_tuple(A.begin(),B.begin(),ids.begin(),res.begin())),
thrust::make_zip_iterator(thrust::make_tuple(A.end(),B.end(),ids.end(),res.end())),
functor_add(thrust::raw_pointer_cast(data.data()))
);
*/
result = matrix_C;
t2 = sys_clock::now();
exec_time_ms = t2 - t1;
std::cout << "Thrust GPU mm time: " << exec_time_ms.count() << "ms\n";
std::cout << "\nChecking Matrices" << std::endl;
// Compare matrices (CPU & thrust) for correctness
bool tutzke =true;
for(int kuz =0; kuz < col_size; kuz++){
if(C[kuz] == result[kuz]){
tutzke = false;
break;
}
}
if(tutzke){
cout << "matrix match!" << endl;
}else{
cout << "jaja nice try" << endl;
}
}
int main(int argc, char* argv[])
{
if (argc < 2)
thrust_matrix_mult(50, 50);
else
thrust_matrix_mult(atoi(argv[1]), atoi(argv[1]));
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB1_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB1_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end1:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_, .Lfunc_end1-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB2_2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_co_u32 v0, s0, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s0
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s7, v0, s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v2, vcc_lo
flat_store_b32 v[0:1], v3
.LBB2_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_,comdat
.Lfunc_end2:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_, .Lfunc_end2-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.section .AMDGPU.csdata,"",@progbits
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_:
s_load_b128 s[4:7], s[0:1], 0x28
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB3_2
s_load_b128 s[4:7], s[0:1], 0x10
v_add_co_u32 v0, s2, s2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s3, 0, s2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x20
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_cvt_f32_i32_e32 v2, v2
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v5, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[5:6], off
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v3, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v3, v4, v2
global_store_b32 v[0:1], v3, off
.LBB3_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 56
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_,comdat
.Lfunc_end3:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_, .Lfunc_end3-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIiEEiEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10__tabulate7functorINS_6detail15normal_iteratorINS_10device_ptrIiEEEENS_6system6detail7generic6detail22compute_sequence_valueIivEElEElLj1EEEvT0_T1_SI_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 40
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 56
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_10for_each_fINS_12zip_iteratorINS_5tupleINS_6detail15normal_iteratorINS_10device_ptrIfEEEESA_NS7_INS8_IiEEEESA_NS_9null_typeESD_SD_SD_SD_SD_EEEENS6_16wrapped_functionI11matrix_multvEEEElLj1EEEvT0_T1_SL_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <math.h>
#define N 64 // constant array lenght
#define TPB 32 // threads per block
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
// converted from serial app
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f.\n", i, ref, x, d_out[i]);
}
int main()
{
const float ref = 0.5f;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allowcate device memory to store the output array
cudaMalloc(&d_out, N * sizeof(float));
// Launch Kernel to compute and store distance values
distanceKernel<<<N / TPB, TPB>>>(d_out, ref, N);
// Free the memory
cudaFree(d_out);
return 0;
} | code for sm_80
Function : _Z14distanceKernelPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fce0007ffe0ff */
/*0070*/ I2F R4, UR4 ; /* 0x0000000400047d06 */
/* 0x000e620008201400 */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fce00078e0203 */
/*0090*/ MUFU.RCP R5, R4 ; /* 0x0000000400057308 */
/* 0x002e300000001000 */
/*00a0*/ I2F R3, R0 ; /* 0x0000000000037306 */
/* 0x000e620000201400 */
/*00b0*/ FFMA R2, -R4, R5, 1 ; /* 0x3f80000004027423 */
/* 0x001fc80000000105 */
/*00c0*/ FFMA R2, R5, R2, R5 ; /* 0x0000000205027223 */
/* 0x000fc60000000005 */
/*00d0*/ FCHK P0, R3, R4 ; /* 0x0000000403007302 */
/* 0x002e220000000000 */
/*00e0*/ FFMA R5, R3, R2, RZ ; /* 0x0000000203057223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R6, -R4, R5, R3 ; /* 0x0000000504067223 */
/* 0x000fc80000000103 */
/*0100*/ FFMA R5, R2, R6, R5 ; /* 0x0000000602057223 */
/* 0x000fe20000000005 */
/*0110*/ @!P0 BRA 0x140 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*0120*/ MOV R2, 0x140 ; /* 0x0000014000027802 */
/* 0x000fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x570 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ FADD R2, -R5, c[0x0][0x168] ; /* 0x00005a0005027621 */
/* 0x000fe20000000100 */
/*0160*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0170*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0180*/ BSSY B0, 0x2a0 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0190*/ FMUL R3, R2, R2 ; /* 0x0000000202037220 */
/* 0x000fe40000400000 */
/*01a0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe400008e06ff */
/*01b0*/ MUFU.RSQ R4, R3 ; /* 0x0000000300047308 */
/* 0x0000620000001400 */
/*01c0*/ IADD3 R2, R3, -0xd000000, RZ ; /* 0xf300000003027810 */
/* 0x000fc80007ffe0ff */
/*01d0*/ ISETP.GT.U32.AND P0, PT, R2, 0x727fffff, PT ; /* 0x727fffff0200780c */
/* 0x000fda0003f04070 */
/*01e0*/ @!P0 BRA 0x250 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*01f0*/ BSSY B1, 0x230 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0200*/ MOV R11, 0x220 ; /* 0x00000220000b7802 */
/* 0x000fe40000000f00 */
/*0210*/ CALL.REL.NOINC 0x400 ; /* 0x000001e000007944 */
/* 0x000fea0003c00000 */
/*0220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0230*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0240*/ BRA 0x290 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0250*/ FMUL.FTZ R2, R3, R4 ; /* 0x0000000403027220 */
/* 0x003fe40000410000 */
/*0260*/ FMUL.FTZ R4, R4, 0.5 ; /* 0x3f00000004047820 */
/* 0x000fe40000410000 */
/*0270*/ FFMA R3, -R2, R2, R3 ; /* 0x0000000202037223 */
/* 0x000fc80000000103 */
/*0280*/ FFMA R2, R3, R4, R2 ; /* 0x0000000403027223 */
/* 0x000fe40000000002 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ F2F.F64.F32 R8, R5 ; /* 0x0000000500087310 */
/* 0x0001e20000201800 */
/*02b0*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fe200078e00ff */
/*02c0*/ MOV R3, 0x0 ; /* 0x0000000000037802 */
/* 0x000fe20000000f00 */
/*02d0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e20000100800 */
/*02e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*02f0*/ IMAD.WIDE R12, R0, R13, c[0x0][0x160] ; /* 0x00005800000c7625 */
/* 0x000fe200078e020d */
/*0300*/ LDC.64 R16, c[0x4][R3] ; /* 0x0100000003107b82 */
/* 0x0002a20000000a00 */
/*0310*/ F2F.F64.F32 R10, R2 ; /* 0x00000002000a7310 */
/* 0x000ee40000201800 */
/*0320*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x001fe200078e00ff */
/*0330*/ STG.E [R12.64], R2 ; /* 0x000000020c007986 */
/* 0x0003ea000c101904 */
/*0340*/ F2F.F64.F32 R14, c[0x0][0x168] ; /* 0x00005a00000e7b10 */
/* 0x000e220000201800 */
/*0350*/ STL.128 [R1+0x10], R8 ; /* 0x0000100801007387 */
/* 0x0083e80000100c00 */
/*0360*/ STL.64 [R1+0x8], R14 ; /* 0x0000080e01007387 */
/* 0x0013e40000100a00 */
/*0370*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x006fe20000000000 */
/*0380*/ MOV R9, 0x3f0 ; /* 0x000003f000097802 */
/* 0x000fc40000000f00 */
/*0390*/ MOV R20, 0x370 ; /* 0x0000037000147802 */
/* 0x000fe40000000f00 */
/*03a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*03b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*03c0*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*03d0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*03e0*/ CALL.ABS.NOINC R16 ; /* 0x0000000010007343 */
/* 0x000fea0003c00000 */
/*03f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0410*/ @!P0 BRA 0x530 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe20003f1e000 */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R3 ; /* 0x000000ffff027224 */
/* 0x000fd800078e0003 */
/*0440*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff038424 */
/* 0x000fe200078e00ff */
/*0450*/ @!P0 BRA 0x530 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0460*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*0470*/ @P0 FADD.FTZ R3, R2, 1 ; /* 0x3f80000002030421 */
/* 0x000fe20000010000 */
/*0480*/ @P0 BRA 0x530 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0490*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*04a0*/ @P0 FFMA R4, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002040823 */
/* 0x000fc800000000ff */
/*04b0*/ @P0 MUFU.RSQ R3, R4 ; /* 0x0000000400030308 */
/* 0x000e240000001400 */
/*04c0*/ @P0 FMUL.FTZ R9, R4, R3 ; /* 0x0000000304090220 */
/* 0x001fe40000410000 */
/*04d0*/ @P0 FMUL.FTZ R10, R3, 0.5 ; /* 0x3f000000030a0820 */
/* 0x000fe40000410000 */
/*04e0*/ @P0 FADD.FTZ R8, -R9.reuse, -RZ ; /* 0x800000ff09080221 */
/* 0x040fe40000010100 */
/*04f0*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R2 ; /* 0x000000ffff038224 */
/* 0x000fe400078e0002 */
/*0500*/ @P0 FFMA R8, R9, R8, R4 ; /* 0x0000000809080223 */
/* 0x000fc80000000004 */
/*0510*/ @P0 FFMA R8, R8, R10, R9 ; /* 0x0000000a08080223 */
/* 0x000fc80000000009 */
/*0520*/ @P0 FMUL.FTZ R3, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008030820 */
/* 0x000fc80000410000 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, R3 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0003 */
/*0540*/ IMAD.MOV.U32 R2, RZ, RZ, R11 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000b */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0560*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffa9002007950 */
/* 0x000fea0003c3ffff */
/*0570*/ SHF.R.U32.HI R6, RZ, 0x17, R4.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011604 */
/*0580*/ BSSY B1, 0xbd0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0590*/ SHF.R.U32.HI R5, RZ, 0x17, R3.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011603 */
/*05a0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*05b0*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*05c0*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*05d0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*05e0*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0600*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0610*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0620*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0630*/ @!P0 BRA 0x7b0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0640*/ FSETP.GTU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f1c200 */
/*0650*/ FSETP.GTU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f3c200 */
/*0660*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0670*/ @P0 BRA 0xbb0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0680*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*0690*/ @!P0 BRA 0xb90 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*06a0*/ FSETP.NEU.FTZ.AND P2, PT, |R3|.reuse, +INF , PT ; /* 0x7f8000000300780b */
/* 0x040fe40003f5d200 */
/*06b0*/ FSETP.NEU.FTZ.AND P1, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f3d200 */
/*06c0*/ FSETP.NEU.FTZ.AND P0, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fd60003f1d200 */
/*06d0*/ @!P1 BRA !P2, 0xb90 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*06e0*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*06f0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0700*/ @P1 BRA 0xb70 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0710*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0720*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0730*/ @P0 BRA 0xb40 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0740*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*0750*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0760*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*0770*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*0780*/ @!P0 FFMA R7, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003078823 */
/* 0x000fe400000000ff */
/*0790*/ @!P1 FFMA R8, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004089823 */
/* 0x000fe200000000ff */
/*07a0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*07c0*/ BSSY B2, 0xb30 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*07d0*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*07e0*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*07f0*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0800*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0810*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0820*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*0830*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0840*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*0850*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*0860*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*0870*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*0880*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*0890*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*08a0*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*08b0*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*08c0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*08d0*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*08e0*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*08f0*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0900*/ @!P0 BRA 0xb10 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0910*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0920*/ @P0 BRA 0xae0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0930*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0940*/ @P0 BRA 0xb20 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0950*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*0960*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*0970*/ @!P0 BRA 0xb20 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0980*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*0990*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*09a0*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*09b0*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*09c0*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*09d0*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*09e0*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0a00*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0a10*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0a20*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0a30*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0a40*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*0a50*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*0a60*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0a70*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*0a80*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*0a90*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*0aa0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0ab0*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0ac0*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0ad0*/ BRA 0xb20 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0ae0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0af0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b00*/ BRA 0xb20 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0b10*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0b20*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0b30*/ BRA 0xbc0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0b40*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*0b50*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0b60*/ BRA 0xbc0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0b70*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*0b80*/ BRA 0xbc0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0b90*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*0ba0*/ BRA 0xbc0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0bb0*/ FADD.FTZ R3, R3, R4 ; /* 0x0000000403037221 */
/* 0x000fe40000010000 */
/*0bc0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0bd0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x001fe400078e0003 */
/*0be0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0bf0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff40002007950 */
/* 0x000fea0003c3ffff */
/*0c00*/ BRA 0xc00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <math.h>
#define N 64 // constant array lenght
#define TPB 32 // threads per block
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
// converted from serial app
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f.\n", i, ref, x, d_out[i]);
}
int main()
{
const float ref = 0.5f;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allowcate device memory to store the output array
cudaMalloc(&d_out, N * sizeof(float));
// Launch Kernel to compute and store distance values
distanceKernel<<<N / TPB, TPB>>>(d_out, ref, N);
// Free the memory
cudaFree(d_out);
return 0;
} | .file "tmpxft_0015a754_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z36__device_stub__Z14distanceKernelPffiPffi
.type _Z36__device_stub__Z14distanceKernelPffiPffi, @function
_Z36__device_stub__Z14distanceKernelPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z14distanceKernelPffiPffi, .-_Z36__device_stub__Z14distanceKernelPffiPffi
.globl _Z14distanceKernelPffi
.type _Z14distanceKernelPffi, @function
_Z14distanceKernelPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14distanceKernelPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPffi, .-_Z14distanceKernelPffi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movss .LC0(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14distanceKernelPffiPffi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <math.h>
#define N 64 // constant array lenght
#define TPB 32 // threads per block
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
// converted from serial app
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f.\n", i, ref, x, d_out[i]);
}
int main()
{
const float ref = 0.5f;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allowcate device memory to store the output array
cudaMalloc(&d_out, N * sizeof(float));
// Launch Kernel to compute and store distance values
distanceKernel<<<N / TPB, TPB>>>(d_out, ref, N);
// Free the memory
cudaFree(d_out);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <math.h>
#define N 64 // constant array lenght
#define TPB 32 // threads per block
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
// converted from serial app
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f.\n", i, ref, x, d_out[i]);
}
int main()
{
const float ref = 0.5f;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allowcate device memory to store the output array
hipMalloc(&d_out, N * sizeof(float));
// Launch Kernel to compute and store distance values
distanceKernel<<<N / TPB, TPB>>>(d_out, ref, N);
// Free the memory
hipFree(d_out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <math.h>
#define N 64 // constant array lenght
#define TPB 32 // threads per block
__device__ float scale(int i, int n)
{
return ((float)i) / (n - 1);
}
__device__ float distance(float x1, float x2)
{
return sqrt((x2 - x1) * (x2 - x1));
}
// converted from serial app
__global__ void distanceKernel(float* d_out, float ref, int len)
{
const int i = blockIdx.x * blockDim.x + threadIdx.x;
const float x = scale(i, len);
d_out[i] = distance(x, ref);
printf("i = %2d: dist from %f to %f.\n", i, ref, x, d_out[i]);
}
int main()
{
const float ref = 0.5f;
// Declare a pointer for an array of floats
float* d_out = 0;
// Allowcate device memory to store the output array
hipMalloc(&d_out, N * sizeof(float));
// Launch Kernel to compute and store distance values
distanceKernel<<<N / TPB, TPB>>>(d_out, ref, N);
// Free the memory
hipFree(d_out);
return 0;
} | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPffi # -- Begin function _Z29__device_stub__distanceKernelPffi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPffi,@function
_Z29__device_stub__distanceKernelPffi: # @_Z29__device_stub__distanceKernelPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPffi, .Lfunc_end0-_Z29__device_stub__distanceKernelPffi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1056964608, 20(%rsp) # imm = 0x3F000000
movl $64, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPffi,@object # @_Z14distanceKernelPffi
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPffi
.p2align 3, 0x0
_Z14distanceKernelPffi:
.quad _Z29__device_stub__distanceKernelPffi
.size _Z14distanceKernelPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPffi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015a754_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z36__device_stub__Z14distanceKernelPffiPffi
.type _Z36__device_stub__Z14distanceKernelPffiPffi, @function
_Z36__device_stub__Z14distanceKernelPffiPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14distanceKernelPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z14distanceKernelPffiPffi, .-_Z36__device_stub__Z14distanceKernelPffiPffi
.globl _Z14distanceKernelPffi
.type _Z14distanceKernelPffi, @function
_Z14distanceKernelPffi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14distanceKernelPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPffi, .-_Z14distanceKernelPffi
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L16:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $64, %esi
movss .LC0(%rip), %xmm0
movq 8(%rsp), %rdi
call _Z36__device_stub__Z14distanceKernelPffiPffi
jmp .L16
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z14distanceKernelPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z29__device_stub__distanceKernelPffi # -- Begin function _Z29__device_stub__distanceKernelPffi
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPffi,@function
_Z29__device_stub__distanceKernelPffi: # @_Z29__device_stub__distanceKernelPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__distanceKernelPffi, .Lfunc_end0-_Z29__device_stub__distanceKernelPffi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl $1056964608, 20(%rsp) # imm = 0x3F000000
movl $64, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPffi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPffi,@object # @_Z14distanceKernelPffi
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPffi
.p2align 3, 0x0
_Z14distanceKernelPffi:
.quad _Z29__device_stub__distanceKernelPffi
.size _Z14distanceKernelPffi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPffi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__device__ void MatrixMultiply(void *input)
{
int warp_size=32;
int thread = threadIdx.x % warp_size;
float* inputIn = (float*)input;
int matrixWidth = inputIn[0];
float *matrixA = inputIn+1;
float *matrixB = matrixA + matrixWidth*matrixWidth;
float *matrixOut = matrixA + 2*matrixWidth*matrixWidth;
// Inlcude the oommented for printing the input and output
/*
int i;
// If master thread, print details
printf("My thread id is: %d\n", thread);
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix A:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixA[i]);
}
}
// Print B
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix B:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixB[i]);
}
}
// Print C, i.e., The out Matrix
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix C:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixOut[i]);
}
}
*/
for (unsigned int i = thread; i < matrixWidth; i=i+32)
{
for (unsigned int j = 0; j < matrixWidth; j++) {
float sum = 0;
for (unsigned int k = 0; k < matrixWidth; k++) {
float a = matrixA[i * matrixWidth + k];
float b = matrixB[k * matrixWidth + j];
sum += a * b;
}
matrixOut[i * matrixWidth + j ] = sum;
}
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__device__ void MatrixMultiply(void *input)
{
int warp_size=32;
int thread = threadIdx.x % warp_size;
float* inputIn = (float*)input;
int matrixWidth = inputIn[0];
float *matrixA = inputIn+1;
float *matrixB = matrixA + matrixWidth*matrixWidth;
float *matrixOut = matrixA + 2*matrixWidth*matrixWidth;
// Inlcude the oommented for printing the input and output
/*
int i;
// If master thread, print details
printf("My thread id is: %d\n", thread);
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix A:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixA[i]);
}
}
// Print B
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix B:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixB[i]);
}
}
// Print C, i.e., The out Matrix
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix C:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixOut[i]);
}
}
*/
for (unsigned int i = thread; i < matrixWidth; i=i+32)
{
for (unsigned int j = 0; j < matrixWidth; j++) {
float sum = 0;
for (unsigned int k = 0; k < matrixWidth; k++) {
float a = matrixA[i * matrixWidth + k];
float b = matrixB[k * matrixWidth + j];
sum += a * b;
}
matrixOut[i * matrixWidth + j ] = sum;
}
}
} | .file "tmpxft_001a7564_00000000-6_MatrixMultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14MatrixMultiplyPv
.type _Z14MatrixMultiplyPv, @function
_Z14MatrixMultiplyPv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14MatrixMultiplyPv, .-_Z14MatrixMultiplyPv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__device__ void MatrixMultiply(void *input)
{
int warp_size=32;
int thread = threadIdx.x % warp_size;
float* inputIn = (float*)input;
int matrixWidth = inputIn[0];
float *matrixA = inputIn+1;
float *matrixB = matrixA + matrixWidth*matrixWidth;
float *matrixOut = matrixA + 2*matrixWidth*matrixWidth;
// Inlcude the oommented for printing the input and output
/*
int i;
// If master thread, print details
printf("My thread id is: %d\n", thread);
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix A:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixA[i]);
}
}
// Print B
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix B:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixB[i]);
}
}
// Print C, i.e., The out Matrix
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix C:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixOut[i]);
}
}
*/
for (unsigned int i = thread; i < matrixWidth; i=i+32)
{
for (unsigned int j = 0; j < matrixWidth; j++) {
float sum = 0;
for (unsigned int k = 0; k < matrixWidth; k++) {
float a = matrixA[i * matrixWidth + k];
float b = matrixB[k * matrixWidth + j];
sum += a * b;
}
matrixOut[i * matrixWidth + j ] = sum;
}
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void MatrixMultiply(void *input)
{
int warp_size=32;
int thread = threadIdx.x % warp_size;
float* inputIn = (float*)input;
int matrixWidth = inputIn[0];
float *matrixA = inputIn+1;
float *matrixB = matrixA + matrixWidth*matrixWidth;
float *matrixOut = matrixA + 2*matrixWidth*matrixWidth;
// Inlcude the oommented for printing the input and output
/*
int i;
// If master thread, print details
printf("My thread id is: %d\n", thread);
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix A:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixA[i]);
}
}
// Print B
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix B:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixB[i]);
}
}
// Print C, i.e., The out Matrix
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix C:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixOut[i]);
}
}
*/
for (unsigned int i = thread; i < matrixWidth; i=i+32)
{
for (unsigned int j = 0; j < matrixWidth; j++) {
float sum = 0;
for (unsigned int k = 0; k < matrixWidth; k++) {
float a = matrixA[i * matrixWidth + k];
float b = matrixB[k * matrixWidth + j];
sum += a * b;
}
matrixOut[i * matrixWidth + j ] = sum;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void MatrixMultiply(void *input)
{
int warp_size=32;
int thread = threadIdx.x % warp_size;
float* inputIn = (float*)input;
int matrixWidth = inputIn[0];
float *matrixA = inputIn+1;
float *matrixB = matrixA + matrixWidth*matrixWidth;
float *matrixOut = matrixA + 2*matrixWidth*matrixWidth;
// Inlcude the oommented for printing the input and output
/*
int i;
// If master thread, print details
printf("My thread id is: %d\n", thread);
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix A:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixA[i]);
}
}
// Print B
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix B:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixB[i]);
}
}
// Print C, i.e., The out Matrix
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix C:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixOut[i]);
}
}
*/
for (unsigned int i = thread; i < matrixWidth; i=i+32)
{
for (unsigned int j = 0; j < matrixWidth; j++) {
float sum = 0;
for (unsigned int k = 0; k < matrixWidth; k++) {
float a = matrixA[i * matrixWidth + k];
float b = matrixB[k * matrixWidth + j];
sum += a * b;
}
matrixOut[i * matrixWidth + j ] = sum;
}
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void MatrixMultiply(void *input)
{
int warp_size=32;
int thread = threadIdx.x % warp_size;
float* inputIn = (float*)input;
int matrixWidth = inputIn[0];
float *matrixA = inputIn+1;
float *matrixB = matrixA + matrixWidth*matrixWidth;
float *matrixOut = matrixA + 2*matrixWidth*matrixWidth;
// Inlcude the oommented for printing the input and output
/*
int i;
// If master thread, print details
printf("My thread id is: %d\n", thread);
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix A:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixA[i]);
}
}
// Print B
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix B:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixB[i]);
}
}
// Print C, i.e., The out Matrix
if(thread == 0){
printf("Matrix Width is: %d\n", matrixWidth);
printf("Printing Matrix C:\n");
for(i=0; i<(matrixWidth*matrixWidth); i++){
if (i%matrixWidth == 0 && i!=0)
printf("\n");
printf("%f ", matrixOut[i]);
}
}
*/
for (unsigned int i = thread; i < matrixWidth; i=i+32)
{
for (unsigned int j = 0; j < matrixWidth; j++) {
float sum = 0;
for (unsigned int k = 0; k < matrixWidth; k++) {
float a = matrixA[i * matrixWidth + k];
float b = matrixB[k * matrixWidth + j];
sum += a * b;
}
matrixOut[i * matrixWidth + j ] = sum;
}
}
} | .text
.file "MatrixMultiply.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a7564_00000000-6_MatrixMultiply.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14MatrixMultiplyPv
.type _Z14MatrixMultiplyPv, @function
_Z14MatrixMultiplyPv:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z14MatrixMultiplyPv, .-_Z14MatrixMultiplyPv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "MatrixMultiply.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<cuda.h>
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
#define CHECK 0
const unsigned int SINGLE_PRECISION = 1;
const unsigned int DOUBLE_PRECISION = 0;
float *SMd, *SNd, *SPd;
double *DMd, *DNd, *DPd;
const unsigned int WIDTH = 1024;
//generate matrix
template<typename T>
T *GenMatrix(const unsigned int width, const unsigned int height)
{
T *matrix;
const unsigned int M_SIZE = width*height;
unsigned int i = 0, j = 0;
matrix = (T*) malloc(M_SIZE * sizeof(double));
for(i = 0 ;i < height; i++){
for(j = 0 ;j < width; j++){
matrix[i * width + j] = (rand()*1.0)/ RAND_MAX;
}
}
return matrix;
}
//display matrix
template<typename T>
int PrintMatrix(T *P, const unsigned int width, const unsigned int height)
{
unsigned int i = 0, j = 0;
printf("\n");
for(i = 0 ;i < height; i++){
for(j = 0 ;j < width; j++){
printf("%.3f\t", P[i * width + j]);
}
printf("\n");
}
return 1;
}
//Init data
template<typename T>
void Init_Cuda(T *M, T *N, const unsigned int width, const unsigned int height, bool sp)
{
const unsigned int size = width*height*sizeof(T);
//allocate matrix
if(sp==SINGLE_PRECISION){
cudaMalloc((void**)&SMd, size);
cudaMemcpy(SMd, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&SNd, size);
cudaMemcpy(SNd, N, size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&SPd, size);
cudaMemset(SPd, 0, size);
}
else
{
cudaMalloc((void**)&DMd, size);
cudaMemcpy(DMd, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&DNd, size);
cudaMemcpy(DNd, N, size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&DPd, size);
cudaMemset(DPd, 0, size);
}
}
//Free memory
void Free_Cuda(bool sp)
{
if(sp==SINGLE_PRECISION){
cudaFree(SMd);
cudaFree(SNd);
cudaFree(SPd);
}
else
{
cudaFree(DMd);
cudaFree(DNd);
cudaFree(DPd);
}
}
//kernel function
template<typename T>
__global__ void MatrixAddKernel(T *P, const T *M, const T *N, const unsigned int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
const unsigned int length = width * width;
while (i < length) {
P[i] = M[i] + N[i];
i += gridDim.x * blockDim.x;
}
}
template<typename T>
int MatrixAdd(T *P, const T *M, const T *N, const unsigned int n)
{
int i, j ;
for(i = 0 ;i < n; i++)
for(j = 0 ;j < n; j++)
{ P [ i* n + j] = M[ i* n + j] + N[ i* n + j];
}
return 0;
}
template<typename T>
int Check(const T *KP, const T *CP, const unsigned int n)
{
int i, j;
T e = 0.001;
int correct = 1;
for(i = 0; i < n ; i++)
for(j = 0; j < n; j++)
{ if(abs(KP[i * n + j] - CP[i * n + j]) > e)
{ printf("%.10f %.10f\n", KP[i * n + j], CP[i * n + j]);
return 0;
}
}
return correct;
}
int main(int argc, char * argv[])
{
bool sp = 1;
float *SM, *SN, *SKP, *SCP;
double *DM, *DN, *DKP, *DCP;
cudaEvent_t start, stop;
float elapsedTime;
unsigned int width;
width = WIDTH;
//create number of blocks and number of threads
int Thr = 128;
dim3 block(Thr, 1, 1);
dim3 grid(((width*width)+ Thr - 1) / Thr, 1, 1);
if (argc != 5)
{
/* We print argv[0] assuming it is the program name */
printf("Wrong parameters. Please use the following format for running.\n");
printf(" Usage: %s %s %s %s %s", argv[0], "[matrix_size]", "[single|double]", "[divide_val]", "[num_threads]\n");
exit(EXIT_FAILURE);
} else {
width = atoi(argv[1]);
sp = atoi(argv[2]);
block.x = atoi(argv[4]);
grid.x = ((width*width)/atoi(argv[3]) + block.x - 1) / block.x;
if(atoi(argv[2])!=0)
sp = SINGLE_PRECISION;
else
sp = DOUBLE_PRECISION;
}
//for using MatrixMul_Kernel_Tiled_SM kernel
//block.x = TILE_WIDTH; block.y=TILE_WIDTH;
//grid.x = WIDTH/TILE_WIDTH; grid.y = WIDTH/TILE_WIDTH;
//initialize host memory
if(sp==SINGLE_PRECISION)
{
SM = GenMatrix<float>(width, width);
//PrintMatrix(M, width, width);
SN = GenMatrix<float>(width, width);
//PrintMatrix(N, width, width);
SKP = GenMatrix<float>(width, width);
SCP = GenMatrix<float>(width, width);
//initialize device memory
Init_Cuda<float>(SM, SN, width, width, SINGLE_PRECISION);
}
else
{
DM = GenMatrix<double>(width, width);
//PrintMatrix(M, width, width);
DN = GenMatrix<double>(width, width);
//PrintMatrix(N, width, width);
DKP = GenMatrix<double>(width, width);
DCP = GenMatrix<double>(width, width);
//initialize device memory
Init_Cuda<double>(DM, DN, width, width, DOUBLE_PRECISION);
}
//create cudaEvent start and stop to record elapsed time
cudaEventCreate(&start);
cudaEventCreate(&stop);
//record start time to start event
cudaEventRecord(start, 0);
//launch kernel
if(sp==SINGLE_PRECISION)
{
MatrixAddKernel<float><<<grid, block>>>(SPd, SMd, SNd, width);
}
else
{
MatrixAddKernel<double><<<grid, block>>>(DPd, DMd, DNd, width);
}
//record start time to stop event
cudaEventRecord(stop, 0);
//synchronize the stop event
cudaEventSynchronize(stop);
//calculate the elapsed time
cudaEventElapsedTime(&elapsedTime, start, stop);
//destroy the start and stop event
cudaEventDestroy(start);
cudaEventDestroy(stop);
//copy data from device memory to host memory
if(sp==SINGLE_PRECISION)
cudaMemcpy(SKP, SPd, width*width*sizeof(float), cudaMemcpyDeviceToHost);
else
cudaMemcpy(DKP, DPd, width*width*sizeof(double), cudaMemcpyDeviceToHost);
//PrintMatrix(P, width, width);
//print runtime
printf("[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n", ((sp==SINGLE_PRECISION)?"Single Precision":"Double Precision"), width, width, grid.x, block.x, elapsedTime);
#if (CHECK==1)
if(sp==SINGLE_PRECISION)
{
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SM, width, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SN, width, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SKP, width, width);
*/
MatrixAdd<float>(SCP, SM, SN, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix<float>(CP, width, width);
if(Check<float>(SKP, SCP, width))
printf("We do it.\n");
else
printf("Something is wrong.\n");
}
else
{
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DM, width, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DN, width, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DKP, width, width);
*/
MatrixAdd<double>(DCP, DM, DN, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix<double>(DCP, width, width);
if(Check<double>(DKP, DCP, width))
printf("We do it.\n");
else
printf("Something is wrong.\n");
}
#endif
//free host memory
if(sp==SINGLE_PRECISION)
{
free(SM);
free(SN);
free(SKP);
free(SCP);
//free device memory
Free_Cuda(sp);
}
else
{
free(DM);
free(DN);
free(DKP);
free(DCP);
//free device memory
Free_Cuda(sp);
}
return 0;
} | code for sm_80
Function : _Z15MatrixAddKernelIdEvPT_PKS0_S3_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0009 */
/*00b0*/ IMAD.WIDE.U32 R4, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0009 */
/*00c0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1b00 */
/*00d0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0009 */
/*00f0*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fca0000000f00 */
/*0100*/ IMAD R0, R11, c[0x0][0x0], R0 ; /* 0x000000000b007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06070 */
/*0120*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*0130*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b06 */
/*0140*/ @!P0 BRA 0x90 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15MatrixAddKernelIfEvPT_PKS0_S3_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR4, URZ ; /* 0x00000004040472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06070 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*00a0*/ IMAD.WIDE.U32 R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0007 */
/*00b0*/ IMAD.WIDE.U32 R4, R0.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0007 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE.U32 R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0007 */
/*00f0*/ MOV R11, c[0x0][0xc] ; /* 0x00000300000b7a02 */
/* 0x000fca0000000f00 */
/*0100*/ IMAD R0, R11, c[0x0][0x0], R0 ; /* 0x000000000b007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe2000bf06070 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ee000c101906 */
/*0140*/ @!P0 BRA 0x90 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<cuda.h>
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
#define CHECK 0
const unsigned int SINGLE_PRECISION = 1;
const unsigned int DOUBLE_PRECISION = 0;
float *SMd, *SNd, *SPd;
double *DMd, *DNd, *DPd;
const unsigned int WIDTH = 1024;
//generate matrix
template<typename T>
T *GenMatrix(const unsigned int width, const unsigned int height)
{
T *matrix;
const unsigned int M_SIZE = width*height;
unsigned int i = 0, j = 0;
matrix = (T*) malloc(M_SIZE * sizeof(double));
for(i = 0 ;i < height; i++){
for(j = 0 ;j < width; j++){
matrix[i * width + j] = (rand()*1.0)/ RAND_MAX;
}
}
return matrix;
}
//display matrix
template<typename T>
int PrintMatrix(T *P, const unsigned int width, const unsigned int height)
{
unsigned int i = 0, j = 0;
printf("\n");
for(i = 0 ;i < height; i++){
for(j = 0 ;j < width; j++){
printf("%.3f\t", P[i * width + j]);
}
printf("\n");
}
return 1;
}
//Init data
template<typename T>
void Init_Cuda(T *M, T *N, const unsigned int width, const unsigned int height, bool sp)
{
const unsigned int size = width*height*sizeof(T);
//allocate matrix
if(sp==SINGLE_PRECISION){
cudaMalloc((void**)&SMd, size);
cudaMemcpy(SMd, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&SNd, size);
cudaMemcpy(SNd, N, size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&SPd, size);
cudaMemset(SPd, 0, size);
}
else
{
cudaMalloc((void**)&DMd, size);
cudaMemcpy(DMd, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&DNd, size);
cudaMemcpy(DNd, N, size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&DPd, size);
cudaMemset(DPd, 0, size);
}
}
//Free memory
void Free_Cuda(bool sp)
{
if(sp==SINGLE_PRECISION){
cudaFree(SMd);
cudaFree(SNd);
cudaFree(SPd);
}
else
{
cudaFree(DMd);
cudaFree(DNd);
cudaFree(DPd);
}
}
//kernel function
template<typename T>
__global__ void MatrixAddKernel(T *P, const T *M, const T *N, const unsigned int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
const unsigned int length = width * width;
while (i < length) {
P[i] = M[i] + N[i];
i += gridDim.x * blockDim.x;
}
}
template<typename T>
int MatrixAdd(T *P, const T *M, const T *N, const unsigned int n)
{
int i, j ;
for(i = 0 ;i < n; i++)
for(j = 0 ;j < n; j++)
{ P [ i* n + j] = M[ i* n + j] + N[ i* n + j];
}
return 0;
}
template<typename T>
int Check(const T *KP, const T *CP, const unsigned int n)
{
int i, j;
T e = 0.001;
int correct = 1;
for(i = 0; i < n ; i++)
for(j = 0; j < n; j++)
{ if(abs(KP[i * n + j] - CP[i * n + j]) > e)
{ printf("%.10f %.10f\n", KP[i * n + j], CP[i * n + j]);
return 0;
}
}
return correct;
}
int main(int argc, char * argv[])
{
bool sp = 1;
float *SM, *SN, *SKP, *SCP;
double *DM, *DN, *DKP, *DCP;
cudaEvent_t start, stop;
float elapsedTime;
unsigned int width;
width = WIDTH;
//create number of blocks and number of threads
int Thr = 128;
dim3 block(Thr, 1, 1);
dim3 grid(((width*width)+ Thr - 1) / Thr, 1, 1);
if (argc != 5)
{
/* We print argv[0] assuming it is the program name */
printf("Wrong parameters. Please use the following format for running.\n");
printf(" Usage: %s %s %s %s %s", argv[0], "[matrix_size]", "[single|double]", "[divide_val]", "[num_threads]\n");
exit(EXIT_FAILURE);
} else {
width = atoi(argv[1]);
sp = atoi(argv[2]);
block.x = atoi(argv[4]);
grid.x = ((width*width)/atoi(argv[3]) + block.x - 1) / block.x;
if(atoi(argv[2])!=0)
sp = SINGLE_PRECISION;
else
sp = DOUBLE_PRECISION;
}
//for using MatrixMul_Kernel_Tiled_SM kernel
//block.x = TILE_WIDTH; block.y=TILE_WIDTH;
//grid.x = WIDTH/TILE_WIDTH; grid.y = WIDTH/TILE_WIDTH;
//initialize host memory
if(sp==SINGLE_PRECISION)
{
SM = GenMatrix<float>(width, width);
//PrintMatrix(M, width, width);
SN = GenMatrix<float>(width, width);
//PrintMatrix(N, width, width);
SKP = GenMatrix<float>(width, width);
SCP = GenMatrix<float>(width, width);
//initialize device memory
Init_Cuda<float>(SM, SN, width, width, SINGLE_PRECISION);
}
else
{
DM = GenMatrix<double>(width, width);
//PrintMatrix(M, width, width);
DN = GenMatrix<double>(width, width);
//PrintMatrix(N, width, width);
DKP = GenMatrix<double>(width, width);
DCP = GenMatrix<double>(width, width);
//initialize device memory
Init_Cuda<double>(DM, DN, width, width, DOUBLE_PRECISION);
}
//create cudaEvent start and stop to record elapsed time
cudaEventCreate(&start);
cudaEventCreate(&stop);
//record start time to start event
cudaEventRecord(start, 0);
//launch kernel
if(sp==SINGLE_PRECISION)
{
MatrixAddKernel<float><<<grid, block>>>(SPd, SMd, SNd, width);
}
else
{
MatrixAddKernel<double><<<grid, block>>>(DPd, DMd, DNd, width);
}
//record start time to stop event
cudaEventRecord(stop, 0);
//synchronize the stop event
cudaEventSynchronize(stop);
//calculate the elapsed time
cudaEventElapsedTime(&elapsedTime, start, stop);
//destroy the start and stop event
cudaEventDestroy(start);
cudaEventDestroy(stop);
//copy data from device memory to host memory
if(sp==SINGLE_PRECISION)
cudaMemcpy(SKP, SPd, width*width*sizeof(float), cudaMemcpyDeviceToHost);
else
cudaMemcpy(DKP, DPd, width*width*sizeof(double), cudaMemcpyDeviceToHost);
//PrintMatrix(P, width, width);
//print runtime
printf("[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n", ((sp==SINGLE_PRECISION)?"Single Precision":"Double Precision"), width, width, grid.x, block.x, elapsedTime);
#if (CHECK==1)
if(sp==SINGLE_PRECISION)
{
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SM, width, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SN, width, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SKP, width, width);
*/
MatrixAdd<float>(SCP, SM, SN, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix<float>(CP, width, width);
if(Check<float>(SKP, SCP, width))
printf("We do it.\n");
else
printf("Something is wrong.\n");
}
else
{
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DM, width, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DN, width, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DKP, width, width);
*/
MatrixAdd<double>(DCP, DM, DN, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix<double>(DCP, width, width);
if(Check<double>(DKP, DCP, width))
printf("We do it.\n");
else
printf("Something is wrong.\n");
}
#endif
//free host memory
if(sp==SINGLE_PRECISION)
{
free(SM);
free(SN);
free(SKP);
free(SCP);
//free device memory
Free_Cuda(sp);
}
else
{
free(DM);
free(DN);
free(DKP);
free(DCP);
//free device memory
Free_Cuda(sp);
}
return 0;
} | .file "tmpxft_0010e5b9_00000000-6_addm_s_d.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.section .text._Z15MatrixAddKernelIfEvPT_PKS0_S3_j,"axG",@progbits,_Z15MatrixAddKernelIfEvPT_PKS0_S3_j,comdat
.weak _Z15MatrixAddKernelIfEvPT_PKS0_S3_j
.type _Z15MatrixAddKernelIfEvPT_PKS0_S3_j, @function
_Z15MatrixAddKernelIfEvPT_PKS0_S3_j:
.LFB4011:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixAddKernelIfEvPT_PKS0_S3_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4011:
.size _Z15MatrixAddKernelIfEvPT_PKS0_S3_j, .-_Z15MatrixAddKernelIfEvPT_PKS0_S3_j
.section .text._Z15MatrixAddKernelIdEvPT_PKS0_S3_j,"axG",@progbits,_Z15MatrixAddKernelIdEvPT_PKS0_S3_j,comdat
.weak _Z15MatrixAddKernelIdEvPT_PKS0_S3_j
.type _Z15MatrixAddKernelIdEvPT_PKS0_S3_j, @function
_Z15MatrixAddKernelIdEvPT_PKS0_S3_j:
.LFB4012:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 8(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 4(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15MatrixAddKernelIdEvPT_PKS0_S3_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4012:
.size _Z15MatrixAddKernelIdEvPT_PKS0_S3_j, .-_Z15MatrixAddKernelIdEvPT_PKS0_S3_j
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3680:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9Free_Cudab
.type _Z9Free_Cudab, @function
_Z9Free_Cudab:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
testb %dil, %dil
je .L16
movq SMd(%rip), %rdi
call cudaFree@PLT
movq SNd(%rip), %rdi
call cudaFree@PLT
movq SPd(%rip), %rdi
call cudaFree@PLT
.L15:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq DMd(%rip), %rdi
call cudaFree@PLT
movq DNd(%rip), %rdi
call cudaFree@PLT
movq DPd(%rip), %rdi
call cudaFree@PLT
jmp .L15
.cfi_endproc
.LFE3672:
.size _Z9Free_Cudab, .-_Z9Free_Cudab
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15MatrixAddKernelIdEvPT_PKS0_S3_j"
.align 8
.LC1:
.string "_Z15MatrixAddKernelIfEvPT_PKS0_S3_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3707:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixAddKernelIdEvPT_PKS0_S3_j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z15MatrixAddKernelIfEvPT_PKS0_S3_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._Z9GenMatrixIfEPT_jj,"axG",@progbits,_Z9GenMatrixIfEPT_jj,comdat
.weak _Z9GenMatrixIfEPT_jj
.type _Z9GenMatrixIfEPT_jj, @function
_Z9GenMatrixIfEPT_jj:
.LFB4007:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r13d
movl %esi, %r15d
imull %esi, %edi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movl %r13d, %ebp
movl $0, %r14d
testl %r15d, %r15d
jne .L22
.L21:
movq %r12, %rax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
call rand@PLT
movl %eax, %edx
movl %ebx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rax,4)
addl $1, %ebx
cmpl %ebp, %ebx
jne .L24
.L26:
addl $1, %r14d
addl %r13d, %ebp
cmpl %r14d, %r15d
je .L21
.L22:
movl %ebp, %ebx
subl %r13d, %ebx
testl %r13d, %r13d
jne .L24
jmp .L26
.cfi_endproc
.LFE4007:
.size _Z9GenMatrixIfEPT_jj, .-_Z9GenMatrixIfEPT_jj
.section .text._Z9Init_CudaIfEvPT_S1_jjb,"axG",@progbits,_Z9Init_CudaIfEvPT_S1_jjb,comdat
.weak _Z9Init_CudaIfEvPT_S1_jjb
.type _Z9Init_CudaIfEvPT_S1_jjb, @function
_Z9Init_CudaIfEvPT_S1_jjb:
.LFB4008:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
imull %ecx, %edx
leal 0(,%rdx,4), %ebx
testb %r8b, %r8b
je .L33
movl %ebx, %ebx
movq %rbx, %rsi
leaq SMd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq SMd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq SNd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq SNd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq SPd(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq SPd(%rip), %rdi
call cudaMemset@PLT
.L32:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movl %ebx, %ebx
movq %rbx, %rsi
leaq DMd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq DMd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq DNd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq DNd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq DPd(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq DPd(%rip), %rdi
call cudaMemset@PLT
jmp .L32
.cfi_endproc
.LFE4008:
.size _Z9Init_CudaIfEvPT_S1_jjb, .-_Z9Init_CudaIfEvPT_S1_jjb
.section .text._Z9GenMatrixIdEPT_jj,"axG",@progbits,_Z9GenMatrixIdEPT_jj,comdat
.weak _Z9GenMatrixIdEPT_jj
.type _Z9GenMatrixIdEPT_jj, @function
_Z9GenMatrixIdEPT_jj:
.LFB4009:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %edi, %r13d
movl %esi, %r15d
imull %esi, %edi
salq $3, %rdi
call malloc@PLT
movq %rax, %r12
movl %r13d, %ebp
movl $0, %r14d
testl %r15d, %r15d
jne .L37
.L36:
movq %r12, %rax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L39:
.cfi_restore_state
call rand@PLT
movl %eax, %edx
movl %ebx, %eax
pxor %xmm0, %xmm0
cvtsi2sdl %edx, %xmm0
divsd .LC2(%rip), %xmm0
movsd %xmm0, (%r12,%rax,8)
addl $1, %ebx
cmpl %ebp, %ebx
jne .L39
.L41:
addl $1, %r14d
addl %r13d, %ebp
cmpl %r14d, %r15d
je .L36
.L37:
movl %ebp, %ebx
subl %r13d, %ebx
testl %r13d, %r13d
jne .L39
jmp .L41
.cfi_endproc
.LFE4009:
.size _Z9GenMatrixIdEPT_jj, .-_Z9GenMatrixIdEPT_jj
.section .text._Z9Init_CudaIdEvPT_S1_jjb,"axG",@progbits,_Z9Init_CudaIdEvPT_S1_jjb,comdat
.weak _Z9Init_CudaIdEvPT_S1_jjb
.type _Z9Init_CudaIdEvPT_S1_jjb, @function
_Z9Init_CudaIdEvPT_S1_jjb:
.LFB4010:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq %rsi, %rbp
imull %ecx, %edx
leal 0(,%rdx,8), %ebx
testb %r8b, %r8b
je .L48
movl %ebx, %ebx
movq %rbx, %rsi
leaq SMd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq SMd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq SNd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq SNd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq SPd(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq SPd(%rip), %rdi
call cudaMemset@PLT
.L47:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movl %ebx, %ebx
movq %rbx, %rsi
leaq DMd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r12, %rsi
movq DMd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq DNd(%rip), %rdi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq DNd(%rip), %rdi
call cudaMemcpy@PLT
movq %rbx, %rsi
leaq DPd(%rip), %rdi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq DPd(%rip), %rdi
call cudaMemset@PLT
jmp .L47
.cfi_endproc
.LFE4010:
.size _Z9Init_CudaIdEvPT_S1_jjb, .-_Z9Init_CudaIdEvPT_S1_jjb
.section .rodata.str1.8
.align 8
.LC3:
.string "Wrong parameters. Please use the following format for running.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC4:
.string "[divide_val]"
.LC5:
.string "[single|double]"
.LC6:
.string "[matrix_size]"
.LC7:
.string " Usage: %s %s %s %s %s"
.LC8:
.string "[num_threads]\n"
.LC9:
.string "Double Precision"
.section .rodata.str1.8
.align 8
.LC10:
.string "[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n"
.section .rodata.str1.1
.LC11:
.string "Single Precision"
.text
.globl main
.type main, @function
main:
.LFB3677:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
cmpl $5, %edi
jne .L64
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movl %eax, %ebx
movq 16(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq 32(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %r12d, %ebp
imull %r12d, %ebp
movq 24(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rcx
movl %ebp, %eax
movl $0, %edx
divl %ecx
leal -1(%rax,%r13), %eax
movl $0, %edx
divl %r13d
movl %eax, %r14d
movq 16(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
je .L53
movl %r12d, %esi
movl %r12d, %edi
call _Z9GenMatrixIfEPT_jj
movq %rax, %r15
movl %r12d, %esi
movl %r12d, %edi
call _Z9GenMatrixIfEPT_jj
movq %rax, 8(%rsp)
movl %r12d, %esi
movl %r12d, %edi
call _Z9GenMatrixIfEPT_jj
movq %rax, 16(%rsp)
movl %r12d, %esi
movl %r12d, %edi
call _Z9GenMatrixIfEPT_jj
movq %rax, 24(%rsp)
movl $1, %r8d
movl %r12d, %ecx
movl %r12d, %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call _Z9Init_CudaIfEvPT_S1_jjb
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %r14d, 76(%rsp)
movl %r13d, 64(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L65
.L54:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl %ebp, %edx
salq $2, %rdx
movl $2, %ecx
movq SPd(%rip), %rsi
movq 16(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %r13
.cfi_def_cfa_offset 176
movl %r14d, %r9d
movl %r12d, %r8d
movl %ebx, %ecx
leaq .LC11(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movl $1, %edi
call _Z9Free_Cudab
jmp .L58
.L64:
leaq .LC3(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 168
leaq .LC8(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 176
leaq .LC4(%rip), %r9
leaq .LC5(%rip), %r8
leaq .LC6(%rip), %rcx
movq (%r15), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
.cfi_restore_state
movl %r12d, %esi
movl %r12d, %edi
call _Z9GenMatrixIdEPT_jj
movq %rax, %r15
movl %r12d, %esi
movl %r12d, %edi
call _Z9GenMatrixIdEPT_jj
movq %rax, 8(%rsp)
movl %r12d, %esi
movl %r12d, %edi
call _Z9GenMatrixIdEPT_jj
movq %rax, 16(%rsp)
movl %r12d, %esi
movl %r12d, %edi
call _Z9GenMatrixIdEPT_jj
movq %rax, 24(%rsp)
movl $0, %r8d
movl %r12d, %ecx
movl %r12d, %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call _Z9Init_CudaIdEvPT_S1_jjb
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl %r14d, 76(%rsp)
movl %r13d, 64(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L66
.L56:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 44(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movl %ebp, %edx
salq $3, %rdx
movl $2, %ecx
movq DPd(%rip), %rsi
movq 16(%rsp), %rbp
movq %rbp, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
subq $8, %rsp
.cfi_def_cfa_offset 168
pushq %r13
.cfi_def_cfa_offset 176
movl %r14d, %r9d
movl %r12d, %r8d
movl %ebx, %ecx
leaq .LC9(%rip), %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq 24(%rsp), %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rdi
call free@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
movl $0, %edi
call _Z9Free_Cudab
.L58:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl %r12d, %ecx
movq SNd(%rip), %rdx
movq SMd(%rip), %rsi
movq SPd(%rip), %rdi
call _Z15MatrixAddKernelIfEvPT_PKS0_S3_j
jmp .L54
.L66:
movl %r12d, %ecx
movq DNd(%rip), %rdx
movq DMd(%rip), %rsi
movq DPd(%rip), %rdi
call _Z15MatrixAddKernelIdEvPT_PKS0_S3_j
jmp .L56
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3677:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl DPd
.bss
.align 8
.type DPd, @object
.size DPd, 8
DPd:
.zero 8
.globl DNd
.align 8
.type DNd, @object
.size DNd, 8
DNd:
.zero 8
.globl DMd
.align 8
.type DMd, @object
.size DMd, 8
DMd:
.zero 8
.globl SPd
.align 8
.type SPd, @object
.size SPd, 8
SPd:
.zero 8
.globl SNd
.align 8
.type SNd, @object
.size SNd, 8
SNd:
.zero 8
.globl SMd
.align 8
.type SMd, @object
.size SMd, 8
SMd:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long -4194304
.long 1105199103
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<cuda.h>
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
#define CHECK 0
const unsigned int SINGLE_PRECISION = 1;
const unsigned int DOUBLE_PRECISION = 0;
float *SMd, *SNd, *SPd;
double *DMd, *DNd, *DPd;
const unsigned int WIDTH = 1024;
//generate matrix
template<typename T>
T *GenMatrix(const unsigned int width, const unsigned int height)
{
T *matrix;
const unsigned int M_SIZE = width*height;
unsigned int i = 0, j = 0;
matrix = (T*) malloc(M_SIZE * sizeof(double));
for(i = 0 ;i < height; i++){
for(j = 0 ;j < width; j++){
matrix[i * width + j] = (rand()*1.0)/ RAND_MAX;
}
}
return matrix;
}
//display matrix
template<typename T>
int PrintMatrix(T *P, const unsigned int width, const unsigned int height)
{
unsigned int i = 0, j = 0;
printf("\n");
for(i = 0 ;i < height; i++){
for(j = 0 ;j < width; j++){
printf("%.3f\t", P[i * width + j]);
}
printf("\n");
}
return 1;
}
//Init data
template<typename T>
void Init_Cuda(T *M, T *N, const unsigned int width, const unsigned int height, bool sp)
{
const unsigned int size = width*height*sizeof(T);
//allocate matrix
if(sp==SINGLE_PRECISION){
cudaMalloc((void**)&SMd, size);
cudaMemcpy(SMd, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&SNd, size);
cudaMemcpy(SNd, N, size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&SPd, size);
cudaMemset(SPd, 0, size);
}
else
{
cudaMalloc((void**)&DMd, size);
cudaMemcpy(DMd, M, size, cudaMemcpyHostToDevice);
cudaMalloc((void**)&DNd, size);
cudaMemcpy(DNd, N, size,cudaMemcpyHostToDevice);
cudaMalloc((void**)&DPd, size);
cudaMemset(DPd, 0, size);
}
}
//Free memory
void Free_Cuda(bool sp)
{
if(sp==SINGLE_PRECISION){
cudaFree(SMd);
cudaFree(SNd);
cudaFree(SPd);
}
else
{
cudaFree(DMd);
cudaFree(DNd);
cudaFree(DPd);
}
}
//kernel function
template<typename T>
__global__ void MatrixAddKernel(T *P, const T *M, const T *N, const unsigned int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
const unsigned int length = width * width;
while (i < length) {
P[i] = M[i] + N[i];
i += gridDim.x * blockDim.x;
}
}
template<typename T>
int MatrixAdd(T *P, const T *M, const T *N, const unsigned int n)
{
int i, j ;
for(i = 0 ;i < n; i++)
for(j = 0 ;j < n; j++)
{ P [ i* n + j] = M[ i* n + j] + N[ i* n + j];
}
return 0;
}
template<typename T>
int Check(const T *KP, const T *CP, const unsigned int n)
{
int i, j;
T e = 0.001;
int correct = 1;
for(i = 0; i < n ; i++)
for(j = 0; j < n; j++)
{ if(abs(KP[i * n + j] - CP[i * n + j]) > e)
{ printf("%.10f %.10f\n", KP[i * n + j], CP[i * n + j]);
return 0;
}
}
return correct;
}
int main(int argc, char * argv[])
{
bool sp = 1;
float *SM, *SN, *SKP, *SCP;
double *DM, *DN, *DKP, *DCP;
cudaEvent_t start, stop;
float elapsedTime;
unsigned int width;
width = WIDTH;
//create number of blocks and number of threads
int Thr = 128;
dim3 block(Thr, 1, 1);
dim3 grid(((width*width)+ Thr - 1) / Thr, 1, 1);
if (argc != 5)
{
/* We print argv[0] assuming it is the program name */
printf("Wrong parameters. Please use the following format for running.\n");
printf(" Usage: %s %s %s %s %s", argv[0], "[matrix_size]", "[single|double]", "[divide_val]", "[num_threads]\n");
exit(EXIT_FAILURE);
} else {
width = atoi(argv[1]);
sp = atoi(argv[2]);
block.x = atoi(argv[4]);
grid.x = ((width*width)/atoi(argv[3]) + block.x - 1) / block.x;
if(atoi(argv[2])!=0)
sp = SINGLE_PRECISION;
else
sp = DOUBLE_PRECISION;
}
//for using MatrixMul_Kernel_Tiled_SM kernel
//block.x = TILE_WIDTH; block.y=TILE_WIDTH;
//grid.x = WIDTH/TILE_WIDTH; grid.y = WIDTH/TILE_WIDTH;
//initialize host memory
if(sp==SINGLE_PRECISION)
{
SM = GenMatrix<float>(width, width);
//PrintMatrix(M, width, width);
SN = GenMatrix<float>(width, width);
//PrintMatrix(N, width, width);
SKP = GenMatrix<float>(width, width);
SCP = GenMatrix<float>(width, width);
//initialize device memory
Init_Cuda<float>(SM, SN, width, width, SINGLE_PRECISION);
}
else
{
DM = GenMatrix<double>(width, width);
//PrintMatrix(M, width, width);
DN = GenMatrix<double>(width, width);
//PrintMatrix(N, width, width);
DKP = GenMatrix<double>(width, width);
DCP = GenMatrix<double>(width, width);
//initialize device memory
Init_Cuda<double>(DM, DN, width, width, DOUBLE_PRECISION);
}
//create cudaEvent start and stop to record elapsed time
cudaEventCreate(&start);
cudaEventCreate(&stop);
//record start time to start event
cudaEventRecord(start, 0);
//launch kernel
if(sp==SINGLE_PRECISION)
{
MatrixAddKernel<float><<<grid, block>>>(SPd, SMd, SNd, width);
}
else
{
MatrixAddKernel<double><<<grid, block>>>(DPd, DMd, DNd, width);
}
//record start time to stop event
cudaEventRecord(stop, 0);
//synchronize the stop event
cudaEventSynchronize(stop);
//calculate the elapsed time
cudaEventElapsedTime(&elapsedTime, start, stop);
//destroy the start and stop event
cudaEventDestroy(start);
cudaEventDestroy(stop);
//copy data from device memory to host memory
if(sp==SINGLE_PRECISION)
cudaMemcpy(SKP, SPd, width*width*sizeof(float), cudaMemcpyDeviceToHost);
else
cudaMemcpy(DKP, DPd, width*width*sizeof(double), cudaMemcpyDeviceToHost);
//PrintMatrix(P, width, width);
//print runtime
printf("[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n", ((sp==SINGLE_PRECISION)?"Single Precision":"Double Precision"), width, width, grid.x, block.x, elapsedTime);
#if (CHECK==1)
if(sp==SINGLE_PRECISION)
{
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SM, width, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SN, width, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SKP, width, width);
*/
MatrixAdd<float>(SCP, SM, SN, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix<float>(CP, width, width);
if(Check<float>(SKP, SCP, width))
printf("We do it.\n");
else
printf("Something is wrong.\n");
}
else
{
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DM, width, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DN, width, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DKP, width, width);
*/
MatrixAdd<double>(DCP, DM, DN, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix<double>(DCP, width, width);
if(Check<double>(DKP, DCP, width))
printf("We do it.\n");
else
printf("Something is wrong.\n");
}
#endif
//free host memory
if(sp==SINGLE_PRECISION)
{
free(SM);
free(SN);
free(SKP);
free(SCP);
//free device memory
Free_Cuda(sp);
}
else
{
free(DM);
free(DN);
free(DKP);
free(DCP);
//free device memory
Free_Cuda(sp);
}
return 0;
} | #include<hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<iostream>
#define CHECK 0
const unsigned int SINGLE_PRECISION = 1;
const unsigned int DOUBLE_PRECISION = 0;
float *SMd, *SNd, *SPd;
double *DMd, *DNd, *DPd;
const unsigned int WIDTH = 1024;
//generate matrix
template<typename T>
T *GenMatrix(const unsigned int width, const unsigned int height)
{
T *matrix;
const unsigned int M_SIZE = width*height;
unsigned int i = 0, j = 0;
matrix = (T*) malloc(M_SIZE * sizeof(double));
for(i = 0 ;i < height; i++){
for(j = 0 ;j < width; j++){
matrix[i * width + j] = (rand()*1.0)/ RAND_MAX;
}
}
return matrix;
}
//display matrix
template<typename T>
int PrintMatrix(T *P, const unsigned int width, const unsigned int height)
{
unsigned int i = 0, j = 0;
printf("\n");
for(i = 0 ;i < height; i++){
for(j = 0 ;j < width; j++){
printf("%.3f\t", P[i * width + j]);
}
printf("\n");
}
return 1;
}
//Init data
template<typename T>
void Init_Cuda(T *M, T *N, const unsigned int width, const unsigned int height, bool sp)
{
const unsigned int size = width*height*sizeof(T);
//allocate matrix
if(sp==SINGLE_PRECISION){
hipMalloc((void**)&SMd, size);
hipMemcpy(SMd, M, size, hipMemcpyHostToDevice);
hipMalloc((void**)&SNd, size);
hipMemcpy(SNd, N, size,hipMemcpyHostToDevice);
hipMalloc((void**)&SPd, size);
hipMemset(SPd, 0, size);
}
else
{
hipMalloc((void**)&DMd, size);
hipMemcpy(DMd, M, size, hipMemcpyHostToDevice);
hipMalloc((void**)&DNd, size);
hipMemcpy(DNd, N, size,hipMemcpyHostToDevice);
hipMalloc((void**)&DPd, size);
hipMemset(DPd, 0, size);
}
}
//Free memory
void Free_Cuda(bool sp)
{
if(sp==SINGLE_PRECISION){
hipFree(SMd);
hipFree(SNd);
hipFree(SPd);
}
else
{
hipFree(DMd);
hipFree(DNd);
hipFree(DPd);
}
}
//kernel function
template<typename T>
__global__ void MatrixAddKernel(T *P, const T *M, const T *N, const unsigned int width)
{
unsigned int i = blockIdx.x*blockDim.x + threadIdx.x;
const unsigned int length = width * width;
while (i < length) {
P[i] = M[i] + N[i];
i += gridDim.x * blockDim.x;
}
}
template<typename T>
int MatrixAdd(T *P, const T *M, const T *N, const unsigned int n)
{
int i, j ;
for(i = 0 ;i < n; i++)
for(j = 0 ;j < n; j++)
{ P [ i* n + j] = M[ i* n + j] + N[ i* n + j];
}
return 0;
}
template<typename T>
int Check(const T *KP, const T *CP, const unsigned int n)
{
int i, j;
T e = 0.001;
int correct = 1;
for(i = 0; i < n ; i++)
for(j = 0; j < n; j++)
{ if(abs(KP[i * n + j] - CP[i * n + j]) > e)
{ printf("%.10f %.10f\n", KP[i * n + j], CP[i * n + j]);
return 0;
}
}
return correct;
}
int main(int argc, char * argv[])
{
bool sp = 1;
float *SM, *SN, *SKP, *SCP;
double *DM, *DN, *DKP, *DCP;
hipEvent_t start, stop;
float elapsedTime;
unsigned int width;
width = WIDTH;
//create number of blocks and number of threads
int Thr = 128;
dim3 block(Thr, 1, 1);
dim3 grid(((width*width)+ Thr - 1) / Thr, 1, 1);
if (argc != 5)
{
/* We print argv[0] assuming it is the program name */
printf("Wrong parameters. Please use the following format for running.\n");
printf(" Usage: %s %s %s %s %s", argv[0], "[matrix_size]", "[single|double]", "[divide_val]", "[num_threads]\n");
exit(EXIT_FAILURE);
} else {
width = atoi(argv[1]);
sp = atoi(argv[2]);
block.x = atoi(argv[4]);
grid.x = ((width*width)/atoi(argv[3]) + block.x - 1) / block.x;
if(atoi(argv[2])!=0)
sp = SINGLE_PRECISION;
else
sp = DOUBLE_PRECISION;
}
//for using MatrixMul_Kernel_Tiled_SM kernel
//block.x = TILE_WIDTH; block.y=TILE_WIDTH;
//grid.x = WIDTH/TILE_WIDTH; grid.y = WIDTH/TILE_WIDTH;
//initialize host memory
if(sp==SINGLE_PRECISION)
{
SM = GenMatrix<float>(width, width);
//PrintMatrix(M, width, width);
SN = GenMatrix<float>(width, width);
//PrintMatrix(N, width, width);
SKP = GenMatrix<float>(width, width);
SCP = GenMatrix<float>(width, width);
//initialize device memory
Init_Cuda<float>(SM, SN, width, width, SINGLE_PRECISION);
}
else
{
DM = GenMatrix<double>(width, width);
//PrintMatrix(M, width, width);
DN = GenMatrix<double>(width, width);
//PrintMatrix(N, width, width);
DKP = GenMatrix<double>(width, width);
DCP = GenMatrix<double>(width, width);
//initialize device memory
Init_Cuda<double>(DM, DN, width, width, DOUBLE_PRECISION);
}
//create cudaEvent start and stop to record elapsed time
hipEventCreate(&start);
hipEventCreate(&stop);
//record start time to start event
hipEventRecord(start, 0);
//launch kernel
if(sp==SINGLE_PRECISION)
{
MatrixAddKernel<float><<<grid, block>>>(SPd, SMd, SNd, width);
}
else
{
MatrixAddKernel<double><<<grid, block>>>(DPd, DMd, DNd, width);
}
//record start time to stop event
hipEventRecord(stop, 0);
//synchronize the stop event
hipEventSynchronize(stop);
//calculate the elapsed time
hipEventElapsedTime(&elapsedTime, start, stop);
//destroy the start and stop event
hipEventDestroy(start);
hipEventDestroy(stop);
//copy data from device memory to host memory
if(sp==SINGLE_PRECISION)
hipMemcpy(SKP, SPd, width*width*sizeof(float), hipMemcpyDeviceToHost);
else
hipMemcpy(DKP, DPd, width*width*sizeof(double), hipMemcpyDeviceToHost);
//PrintMatrix(P, width, width);
//print runtime
printf("[ %s ][ %4dx%4d ][ %10d blocks ][ %5d threads ]\t>\t[ %7.3f (ms) ]\n", ((sp==SINGLE_PRECISION)?"Single Precision":"Double Precision"), width, width, grid.x, block.x, elapsedTime);
#if (CHECK==1)
if(sp==SINGLE_PRECISION)
{
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SM, width, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SN, width, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<float>(SKP, width, width);
*/
MatrixAdd<float>(SCP, SM, SN, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix<float>(CP, width, width);
if(Check<float>(SKP, SCP, width))
printf("We do it.\n");
else
printf("Something is wrong.\n");
}
else
{
/*printf("M >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DM, width, width);
printf("N >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DN, width, width);
printf("KP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
PrintMatrix<double>(DKP, width, width);
*/
MatrixAdd<double>(DCP, DM, DN, width);
//printf("CP >>>>>>>>>>>>>>>>>>>>>>>>>>\n");
//PrintMatrix<double>(DCP, width, width);
if(Check<double>(DKP, DCP, width))
printf("We do it.\n");
else
printf("Something is wrong.\n");
}
#endif
//free host memory
if(sp==SINGLE_PRECISION)
{
free(SM);
free(SN);
free(SKP);
free(SCP);
//free device memory
Free_Cuda(sp);
}
else
{
free(DM);
free(DN);
free(DKP);
free(DCP);
//free device memory
Free_Cuda(sp);
}
return 0;
} |
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