system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void updateStatistic ( const int nwl, const float *stt1, const float *q, const float *r, float *stt0 ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < nwl ) {
stt0[i] = ( q[i] > r[i] ) * stt1[i] + ( q[i] < r[i] ) * stt0[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15updateStatisticiPKfS0_S0_Pf
.globl _Z15updateStatisticiPKfS0_S0_Pf
.p2align 8
.type _Z15updateStatisticiPKfS0_S0_Pf,@function
_Z15updateStatisticiPKfS0_S0_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(2)
v_cmp_lt_f32_e32 vcc_lo, v6, v4
v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, v5, v1
v_cndmask_b32_e64 v4, 0, 1.0, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v0, v4
global_store_b32 v[2:3], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15updateStatisticiPKfS0_S0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15updateStatisticiPKfS0_S0_Pf, .Lfunc_end0-_Z15updateStatisticiPKfS0_S0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15updateStatisticiPKfS0_S0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15updateStatisticiPKfS0_S0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void updateStatistic ( const int nwl, const float *stt1, const float *q, const float *r, float *stt0 ) {
int i = threadIdx.x + blockDim.x * blockIdx.x;
if ( i < nwl ) {
stt0[i] = ( q[i] > r[i] ) * stt1[i] + ( q[i] < r[i] ) * stt0[i];
}
} | .text
.file "updateStatistic.hip"
.globl _Z30__device_stub__updateStatisticiPKfS0_S0_Pf # -- Begin function _Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.p2align 4, 0x90
.type _Z30__device_stub__updateStatisticiPKfS0_S0_Pf,@function
_Z30__device_stub__updateStatisticiPKfS0_S0_Pf: # @_Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15updateStatisticiPKfS0_S0_Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z30__device_stub__updateStatisticiPKfS0_S0_Pf, .Lfunc_end0-_Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15updateStatisticiPKfS0_S0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15updateStatisticiPKfS0_S0_Pf,@object # @_Z15updateStatisticiPKfS0_S0_Pf
.section .rodata,"a",@progbits
.globl _Z15updateStatisticiPKfS0_S0_Pf
.p2align 3, 0x0
_Z15updateStatisticiPKfS0_S0_Pf:
.quad _Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.size _Z15updateStatisticiPKfS0_S0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15updateStatisticiPKfS0_S0_Pf"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15updateStatisticiPKfS0_S0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15updateStatisticiPKfS0_S0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R6, R3, c[0x0][0x0], R6 ; /* 0x0000000003067a24 */
/* 0x001fca00078e0206 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x178] ; /* 0x00005e0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*00b0*/ IMAD.WIDE R8, R6.reuse, R7.reuse, c[0x0][0x180] ; /* 0x0000600006087625 */
/* 0x0c0fe400078e0207 */
/*00c0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*00d0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe400078e0207 */
/*00e0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ee8000c1e1900 */
/*00f0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000f22000c1e1900 */
/*0100*/ FSET.BF.LT.AND R10, R3, R4, PT ; /* 0x00000004030a720a */
/* 0x004fc40003801000 */
/*0110*/ FSET.BF.GT.AND R0, R3, R4, PT ; /* 0x000000040300720a */
/* 0x000fc60003804000 */
/*0120*/ FMUL R10, R10, R11 ; /* 0x0000000b0a0a7220 */
/* 0x008fc80000400000 */
/*0130*/ FFMA R11, R0, R7, R10 ; /* 0x00000007000b7223 */
/* 0x010fca000000000a */
/*0140*/ STG.E [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x000fe2000c101904 */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15updateStatisticiPKfS0_S0_Pf
.globl _Z15updateStatisticiPKfS0_S0_Pf
.p2align 8
.type _Z15updateStatisticiPKfS0_S0_Pf,@function
_Z15updateStatisticiPKfS0_S0_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b256 s[0:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
global_load_b32 v6, v[2:3], off
global_load_b32 v4, v[4:5], off
v_add_co_u32 v2, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v0, v[0:1], off
s_waitcnt vmcnt(2)
v_cmp_lt_f32_e32 vcc_lo, v6, v4
v_cndmask_b32_e64 v1, 0, 1.0, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_f32_e32 v1, v5, v1
v_cndmask_b32_e64 v4, 0, 1.0, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, v0, v4
global_store_b32 v[2:3], v1, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15updateStatisticiPKfS0_S0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15updateStatisticiPKfS0_S0_Pf, .Lfunc_end0-_Z15updateStatisticiPKfS0_S0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15updateStatisticiPKfS0_S0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15updateStatisticiPKfS0_S0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c7025_00000000-6_updateStatistic.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z15updateStatisticiPKfS0_S0_PfiPKfS0_S0_Pf
.type _Z45__device_stub__Z15updateStatisticiPKfS0_S0_PfiPKfS0_S0_Pf, @function
_Z45__device_stub__Z15updateStatisticiPKfS0_S0_PfiPKfS0_S0_Pf:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15updateStatisticiPKfS0_S0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z15updateStatisticiPKfS0_S0_PfiPKfS0_S0_Pf, .-_Z45__device_stub__Z15updateStatisticiPKfS0_S0_PfiPKfS0_S0_Pf
.globl _Z15updateStatisticiPKfS0_S0_Pf
.type _Z15updateStatisticiPKfS0_S0_Pf, @function
_Z15updateStatisticiPKfS0_S0_Pf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z15updateStatisticiPKfS0_S0_PfiPKfS0_S0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15updateStatisticiPKfS0_S0_Pf, .-_Z15updateStatisticiPKfS0_S0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z15updateStatisticiPKfS0_S0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15updateStatisticiPKfS0_S0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "updateStatistic.hip"
.globl _Z30__device_stub__updateStatisticiPKfS0_S0_Pf # -- Begin function _Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.p2align 4, 0x90
.type _Z30__device_stub__updateStatisticiPKfS0_S0_Pf,@function
_Z30__device_stub__updateStatisticiPKfS0_S0_Pf: # @_Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %edi, 12(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15updateStatisticiPKfS0_S0_Pf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z30__device_stub__updateStatisticiPKfS0_S0_Pf, .Lfunc_end0-_Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15updateStatisticiPKfS0_S0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15updateStatisticiPKfS0_S0_Pf,@object # @_Z15updateStatisticiPKfS0_S0_Pf
.section .rodata,"a",@progbits
.globl _Z15updateStatisticiPKfS0_S0_Pf
.p2align 3, 0x0
_Z15updateStatisticiPKfS0_S0_Pf:
.quad _Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.size _Z15updateStatisticiPKfS0_S0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15updateStatisticiPKfS0_S0_Pf"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__updateStatisticiPKfS0_S0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15updateStatisticiPKfS0_S0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
int reduceByHost(int * in, int n)
{
int s = in[0];
for (int i = 1; i < n; i++)
s += in[i];
return s;
}
// Kernel 1 - warp divergence
__global__ void reduceByDevice1(int * in, int * out, int n)
{
// TODO
int i = (blockIdx.x*blockDim.x + threadIdx.x)*2;
int stride;
int sum = 0;
for(stride = 0; stride < 2*threadIdx.x; stride *= 2){
if(threadIdx.x%stride == 0){
if(i+stride < n){
sum += in[i+stride];
}
}
__syncthreads();
}
out[i] = sum;
if(threadIdx.x == 0){
out[blockIdx.x*blockDim.x] = out[blockIdx.x*blockDim.x*2];
}
}
// Kernel 2 - less warp divergence
__global__ void reduceByDevice2(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = 1; stride < blockDim.x*2; stride *= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < blockDim.x/stride){
if(i + stride < n){
in[i] += in[i+stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
// Kernel 3 - less warp divergence + efficient memory access
__global__ void reduceByDevice3(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = blockDim.x; stride > 0; stride /= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < stride){
if(i + stride < n){
in[i] += in[i + stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
/*
// Kernel 4 - use shared memmory
__global__ void reduceByDevice4(int * in, int * out, int n){
// todo
// mỗi block load dữ liệu từ GMEM(ram) lên SMEM
// vì khai báo cần 1 kích thước tĩnh nên ở đây giả sử kích thước mỗi block là 256
__shared__ int blkData[2*256];
// số phần tử trước block hiện tại
int num = blockIdx.x*blockDim*2;
blkData[threadIdx.x]=in[num + threadIdx.x];
blkData[blockDim.x + threadIdx.x]=in[num + blockDim.x + threadIdx.x];
__syncthreads();
// tinh toan voi du lieu luu tai SMem
for(int stride = blockDim.x; stride > 0; stride/=2){
if(threadIdx.x < stride){
blkData[threadIdx.x]+=blkData[threadIdx.x + stride];
}
__syncthreads();
}
// chep du lieu ve lai GMem
if(threadIdx.x == 0){
out[blockIdx.x] = blkData[0];
}
}
*/
int main(int argc, char ** argv)
{
// Print out device info
cudaDeviceProp devProv;
CHECK(cudaGetDeviceProperties(&devProv, 0));
printf("**********GPU info**********\n");
printf("Name: %s\n", devProv.name); // TODO
printf("Compute capability: %d\n", devProv.major); // TODO
printf("Num SMs: %d\n", devProv.multiProcessorCount); // TODO
printf("Max num threads per SM: %d\n", devProv.maxThreadsPerMultiProcessor); // TODO
printf("Max num warps per SM: %d\n", devProv.maxThreadsPerMultiProcessor/32 ); // TODO
printf("****************************\n\n");
// Set up input size
int n = (1 << 24) + 1;
printf("Input size: %d\n", n);
// Set up execution configuration
dim3 blockSize(256); // Default
if (argc == 2) // Get block size from cmd argument
blockSize.x = atoi(argv[1]);
dim3 gridSize((n-1)/(2*blockSize.x) + 1); // TODO
printf("Grid size: %d, block size: %d\n", gridSize.x, blockSize.x);
// Allocate memories
size_t bytes = n * sizeof(int);
int * in = (int *) malloc(bytes);
int * out = (int *) malloc(gridSize.x * sizeof(int));
// Set up input data
for (int i = 0; i < n; i++)
{
// Generate a random integer in [0, 255]
in[i] = (int)(rand() & 0xFF);
}
// Reduce on host
int host_sum = reduceByHost(in, n);
printf("\n%15s%12s%16s%21s%16s\n",
"Function", "Result", "KernelTime(ms)", "Post-kernelTime(ms)", "TotalTime(ms)");
printf("%15s%12d%16s%21s%16s\n",
"reduceByHost", host_sum, "-", "-", "-");
//========================================================
// Allocate device memories
int *d_in, *d_out;
CHECK(cudaMalloc(&d_in, bytes));
CHECK(cudaMalloc(&d_out, gridSize.x * sizeof(int)));
// Copy data to device memories
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice));
// Kernel 1 - warp divergence
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice));
GpuTimer timer;
timer.Start();
reduceByDevice1<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
float kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
int device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
float postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice1", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct1 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 2 - less warp divergence
timer.Start();
reduceByDevice2<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice2", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct2 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 3 - less warp divergence + efficient memory access
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice3<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice3", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct3 = (host_sum == device_sum); // Check result
/*
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 4 - use shared memory
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice4<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice4", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct4 = (host_sum == device_sum); // Check result
*/
// Print out errors
printf("\n");
if (correct1 == false)
fprintf(stderr, "Error: reduceByDevice1 is incorrect!\n");
if (correct2 == false)
fprintf(stderr, "Error: reduceByDevice2 is incorrect!\n");
if (correct3 == false)
fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
//if (correct4 == false)
// fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
// Free device memories
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
//========================================================
// Free memories
free(in);
free(out);
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z15reduceByDevice3PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e620000002100 */
/*0050*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD R0, R10, c[0x0][0x0], RZ ; /* 0x000000000a007a24 */
/* 0x001fc800078e02ff */
/*0070*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fd000078e00ff */
/*0080*/ @!P0 BRA 0x1f0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B0, 0x1f0 ; /* 0x0000015000007945 */
/* 0x002fe20003800000 */
/*00a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.SHL.U32 R6, R12, 0x2, RZ ; /* 0x000000020c067824 */
/* 0x000fc600078e00ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x000fda0003f06070 */
/*00d0*/ @P0 BRA 0x1b0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*00e0*/ IMAD R5, R6, R7, R0 ; /* 0x0000000706057224 */
/* 0x000fca00078e0200 */
/*00f0*/ IADD3 R3, R5, R7, RZ ; /* 0x0000000705037210 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0110*/ @P0 BRA 0x190 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*0140*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0204 */
/*0150*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0170*/ IADD3 R9, R8, R3, RZ ; /* 0x0000000308097210 */
/* 0x004fca0007ffe0ff */
/*0180*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0190*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ SHF.R.U32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fc80000011607 */
/*01c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*01d0*/ @P0 BRA 0xc0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x002fda0003f05270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fc800078e00ff */
/*0220*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0230*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R4, R10, R5, c[0x0][0x168] ; /* 0x00005a000a047625 */
/* 0x000fca00078e0005 */
/*0250*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15reduceByDevice2PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0060*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0070*/ IMAD R6, R0, UR4, RZ ; /* 0x0000000400067c24 */
/* 0x001fd8000f8e02ff */
/*0080*/ @!P0 BRA 0x310 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R8, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff087435 */
/* 0x000fe200000001ff */
/*00a0*/ BSSY B0, 0x310 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.SHL.U32 R7, R10, 0x2, RZ ; /* 0x000000020a077824 */
/* 0x002fce00078e00ff */
/*00c0*/ I2F.U32.RP R4, R8 ; /* 0x0000000800047306 */
/* 0x001e220000209000 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fce0003f45070 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x001fe20000000f00 */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R5, R5, R8, RZ ; /* 0x0000000805057224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0150*/ IMAD.HI.U32 R3, R3, c[0x0][0x0], RZ ; /* 0x0000000003037a27 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0170*/ IMAD R5, R8, R5, c[0x0][0x0] ; /* 0x0000000008057624 */
/* 0x000fca00078e0205 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f06070 */
/*0190*/ @P0 IADD3 R5, R5, -R8.reuse, RZ ; /* 0x8000000805050210 */
/* 0x080fe40007ffe0ff */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*01c0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @!P2 LOP3.LUT R3, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff03a212 */
/* 0x000fc800078e33ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 BRA 0x2d0 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD R5, R7, R8, R6 ; /* 0x0000000807057224 */
/* 0x000fc800078e0206 */
/*0210*/ IMAD.IADD R3, R5, 0x1, R8 ; /* 0x0000000105037824 */
/* 0x000fca00078e0208 */
/*0220*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0230*/ @P0 BRA 0x2b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0240*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fca0000000f00 */
/*0250*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*0260*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0204 */
/*0270*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD.IADD R9, R9, 0x1, R2 ; /* 0x0000000109097824 */
/* 0x004fca00078e0202 */
/*02a0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101906 */
/*02b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108087819 */
/* 0x000fc800000006ff */
/*02e0*/ ISETP.GE.U32.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fda000bf06070 */
/*02f0*/ @!P0 BRA 0xc0 ; /* 0xfffffdc000008947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x002fda0003f05270 */
/*0320*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fc800078e00ff */
/*0340*/ IMAD.WIDE R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0205 */
/*0350*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0370*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15reduceByDevice1PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ LOP3.LUT P0, RZ, R3.reuse, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x041fe4000780c0ff */
/*0060*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f25270 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], RZ ; /* 0x0000000004047a24 */
/* 0x002fca00078e02ff */
/*0080*/ IADD3 R0, R4, R3, RZ ; /* 0x0000000304007210 */
/* 0x000fc80007ffe0ff */
/*0090*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0205 */
/*00b0*/ @!P0 BRA 0xf0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ BRA 0xc0 ; /* 0xffffffd000007947 */
/* 0x000fea000383ffff */
/*00f0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0100*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0110*/ SHF.L.U32 R2, R4, 0x1, RZ ; /* 0x0000000104027819 */
/* 0x001fca00000006ff */
/*0120*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0005 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0005 */
/*0150*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
int reduceByHost(int * in, int n)
{
int s = in[0];
for (int i = 1; i < n; i++)
s += in[i];
return s;
}
// Kernel 1 - warp divergence
__global__ void reduceByDevice1(int * in, int * out, int n)
{
// TODO
int i = (blockIdx.x*blockDim.x + threadIdx.x)*2;
int stride;
int sum = 0;
for(stride = 0; stride < 2*threadIdx.x; stride *= 2){
if(threadIdx.x%stride == 0){
if(i+stride < n){
sum += in[i+stride];
}
}
__syncthreads();
}
out[i] = sum;
if(threadIdx.x == 0){
out[blockIdx.x*blockDim.x] = out[blockIdx.x*blockDim.x*2];
}
}
// Kernel 2 - less warp divergence
__global__ void reduceByDevice2(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = 1; stride < blockDim.x*2; stride *= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < blockDim.x/stride){
if(i + stride < n){
in[i] += in[i+stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
// Kernel 3 - less warp divergence + efficient memory access
__global__ void reduceByDevice3(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = blockDim.x; stride > 0; stride /= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < stride){
if(i + stride < n){
in[i] += in[i + stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
/*
// Kernel 4 - use shared memmory
__global__ void reduceByDevice4(int * in, int * out, int n){
// todo
// mỗi block load dữ liệu từ GMEM(ram) lên SMEM
// vì khai báo cần 1 kích thước tĩnh nên ở đây giả sử kích thước mỗi block là 256
__shared__ int blkData[2*256];
// số phần tử trước block hiện tại
int num = blockIdx.x*blockDim*2;
blkData[threadIdx.x]=in[num + threadIdx.x];
blkData[blockDim.x + threadIdx.x]=in[num + blockDim.x + threadIdx.x];
__syncthreads();
// tinh toan voi du lieu luu tai SMem
for(int stride = blockDim.x; stride > 0; stride/=2){
if(threadIdx.x < stride){
blkData[threadIdx.x]+=blkData[threadIdx.x + stride];
}
__syncthreads();
}
// chep du lieu ve lai GMem
if(threadIdx.x == 0){
out[blockIdx.x] = blkData[0];
}
}
*/
int main(int argc, char ** argv)
{
// Print out device info
cudaDeviceProp devProv;
CHECK(cudaGetDeviceProperties(&devProv, 0));
printf("**********GPU info**********\n");
printf("Name: %s\n", devProv.name); // TODO
printf("Compute capability: %d\n", devProv.major); // TODO
printf("Num SMs: %d\n", devProv.multiProcessorCount); // TODO
printf("Max num threads per SM: %d\n", devProv.maxThreadsPerMultiProcessor); // TODO
printf("Max num warps per SM: %d\n", devProv.maxThreadsPerMultiProcessor/32 ); // TODO
printf("****************************\n\n");
// Set up input size
int n = (1 << 24) + 1;
printf("Input size: %d\n", n);
// Set up execution configuration
dim3 blockSize(256); // Default
if (argc == 2) // Get block size from cmd argument
blockSize.x = atoi(argv[1]);
dim3 gridSize((n-1)/(2*blockSize.x) + 1); // TODO
printf("Grid size: %d, block size: %d\n", gridSize.x, blockSize.x);
// Allocate memories
size_t bytes = n * sizeof(int);
int * in = (int *) malloc(bytes);
int * out = (int *) malloc(gridSize.x * sizeof(int));
// Set up input data
for (int i = 0; i < n; i++)
{
// Generate a random integer in [0, 255]
in[i] = (int)(rand() & 0xFF);
}
// Reduce on host
int host_sum = reduceByHost(in, n);
printf("\n%15s%12s%16s%21s%16s\n",
"Function", "Result", "KernelTime(ms)", "Post-kernelTime(ms)", "TotalTime(ms)");
printf("%15s%12d%16s%21s%16s\n",
"reduceByHost", host_sum, "-", "-", "-");
//========================================================
// Allocate device memories
int *d_in, *d_out;
CHECK(cudaMalloc(&d_in, bytes));
CHECK(cudaMalloc(&d_out, gridSize.x * sizeof(int)));
// Copy data to device memories
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice));
// Kernel 1 - warp divergence
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice));
GpuTimer timer;
timer.Start();
reduceByDevice1<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
float kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
int device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
float postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice1", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct1 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 2 - less warp divergence
timer.Start();
reduceByDevice2<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice2", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct2 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 3 - less warp divergence + efficient memory access
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice3<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice3", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct3 = (host_sum == device_sum); // Check result
/*
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 4 - use shared memory
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice4<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice4", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct4 = (host_sum == device_sum); // Check result
*/
// Print out errors
printf("\n");
if (correct1 == false)
fprintf(stderr, "Error: reduceByDevice1 is incorrect!\n");
if (correct2 == false)
fprintf(stderr, "Error: reduceByDevice2 is incorrect!\n");
if (correct3 == false)
fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
//if (correct4 == false)
// fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
// Free device memories
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
//========================================================
// Free memories
free(in);
free(out);
return EXIT_SUCCESS;
} | .file "tmpxft_001afdbf_00000000-6_bt3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2070:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .text._ZN8GpuTimer7ElapsedEv,"axG",@progbits,_ZN8GpuTimer7ElapsedEv,comdat
.align 2
.weak _ZN8GpuTimer7ElapsedEv
.type _ZN8GpuTimer7ElapsedEv, @function
_ZN8GpuTimer7ElapsedEv:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $16, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbx
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq 8(%rdi), %rdi
call cudaEventSynchronize@PLT
movq 8(%rbx), %rdx
movq (%rbx), %rsi
leaq 4(%rsp), %rdi
call cudaEventElapsedTime@PLT
movss 4(%rsp), %xmm0
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2065:
.size _ZN8GpuTimer7ElapsedEv, .-_ZN8GpuTimer7ElapsedEv
.text
.globl _Z12reduceByHostPii
.type _Z12reduceByHostPii, @function
_Z12reduceByHostPii:
.LFB2066:
.cfi_startproc
endbr64
movl (%rdi), %edx
cmpl $1, %esi
jle .L7
leaq 4(%rdi), %rax
leal -2(%rsi), %ecx
leaq 8(%rdi,%rcx,4), %rcx
.L9:
addl (%rax), %edx
addq $4, %rax
cmpq %rcx, %rax
jne .L9
.L7:
movl %edx, %eax
ret
.cfi_endproc
.LFE2066:
.size _Z12reduceByHostPii, .-_Z12reduceByHostPii
.globl _Z38__device_stub__Z15reduceByDevice1PiS_iPiS_i
.type _Z38__device_stub__Z15reduceByDevice1PiS_iPiS_i, @function
_Z38__device_stub__Z15reduceByDevice1PiS_iPiS_i:
.LFB2092:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15reduceByDevice1PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z38__device_stub__Z15reduceByDevice1PiS_iPiS_i, .-_Z38__device_stub__Z15reduceByDevice1PiS_iPiS_i
.globl _Z15reduceByDevice1PiS_i
.type _Z15reduceByDevice1PiS_i, @function
_Z15reduceByDevice1PiS_i:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15reduceByDevice1PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z15reduceByDevice1PiS_i, .-_Z15reduceByDevice1PiS_i
.globl _Z38__device_stub__Z15reduceByDevice2PiS_iPiS_i
.type _Z38__device_stub__Z15reduceByDevice2PiS_iPiS_i, @function
_Z38__device_stub__Z15reduceByDevice2PiS_iPiS_i:
.LFB2094:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15reduceByDevice2PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z38__device_stub__Z15reduceByDevice2PiS_iPiS_i, .-_Z38__device_stub__Z15reduceByDevice2PiS_iPiS_i
.globl _Z15reduceByDevice2PiS_i
.type _Z15reduceByDevice2PiS_i, @function
_Z15reduceByDevice2PiS_i:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15reduceByDevice2PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z15reduceByDevice2PiS_i, .-_Z15reduceByDevice2PiS_i
.globl _Z38__device_stub__Z15reduceByDevice3PiS_iPiS_i
.type _Z38__device_stub__Z15reduceByDevice3PiS_iPiS_i, @function
_Z38__device_stub__Z15reduceByDevice3PiS_iPiS_i:
.LFB2096:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15reduceByDevice3PiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z38__device_stub__Z15reduceByDevice3PiS_iPiS_i, .-_Z38__device_stub__Z15reduceByDevice3PiS_iPiS_i
.globl _Z15reduceByDevice3PiS_i
.type _Z15reduceByDevice3PiS_i, @function
_Z15reduceByDevice3PiS_i:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15reduceByDevice3PiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z15reduceByDevice3PiS_i, .-_Z15reduceByDevice3PiS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/TruongNgocTai/TH_03/master/bt3.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Error: %s:%d, "
.LC2:
.string "code: %d, reason: %s\n"
.LC3:
.string "**********GPU info**********\n"
.LC4:
.string "Name: %s\n"
.LC5:
.string "Compute capability: %d\n"
.LC6:
.string "Num SMs: %d\n"
.LC7:
.string "Max num threads per SM: %d\n"
.LC8:
.string "Max num warps per SM: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "****************************\n\n"
.section .rodata.str1.1
.LC10:
.string "Input size: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "Grid size: %d, block size: %d\n"
.section .rodata.str1.1
.LC12:
.string "Post-kernelTime(ms)"
.LC13:
.string "KernelTime(ms)"
.LC14:
.string "Result"
.LC15:
.string "Function"
.LC16:
.string "\n%15s%12s%16s%21s%16s\n"
.LC17:
.string "TotalTime(ms)"
.LC18:
.string "-"
.LC19:
.string "reduceByHost"
.LC20:
.string "%15s%12d%16s%21s%16s\n"
.LC21:
.string "reduceByDevice1"
.LC22:
.string "%15s%12d%16.3f%21.3f%16.3f\n"
.LC23:
.string "reduceByDevice2"
.LC24:
.string "reduceByDevice3"
.LC25:
.string "\n"
.section .rodata.str1.8
.align 8
.LC26:
.string "Error: reduceByDevice1 is incorrect!\n"
.align 8
.LC27:
.string "Error: reduceByDevice2 is incorrect!\n"
.align 8
.LC28:
.string "Error: reduceByDevice3 is incorrect!\n"
.text
.globl main
.type main, @function
main:
.LFB2067:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA2067
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movl %edi, %ebx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
leaq 96(%rsp), %rdi
movl $0, %esi
.LEHB0:
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L77
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 96(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 456(%rsp), %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 484(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 720(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 720(%rsp), %eax
leal 31(%rax), %edx
testl %eax, %eax
cmovns %eax, %edx
sarl $5, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $16777217, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $256, %ebp
cmpl $2, %ebx
je .L78
.L37:
leal (%rbp,%rbp), %ecx
movl $16777216, %eax
movl $0, %edx
divl %ecx
movl %eax, 28(%rsp)
leal 1(%rax), %r13d
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl %ebp, %ecx
movl %r13d, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $67108868, %edi
call malloc@PLT
movq %rax, %r15
movl %r13d, %r14d
salq $2, %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r15, %rbx
leaq 67108868(%r15), %r12
.L38:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L38
movl $16777217, %esi
movq %r15, %rdi
call _Z12reduceByHostPii
movl %eax, %ebx
movl %eax, 20(%rsp)
subq $8, %rsp
.cfi_def_cfa_offset 1208
leaq .LC17(%rip), %rax
pushq %rax
.cfi_def_cfa_offset 1216
leaq .LC12(%rip), %r9
leaq .LC13(%rip), %r8
leaq .LC14(%rip), %rcx
leaq .LC15(%rip), %rdx
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC18(%rip), %r8
movq %r8, (%rsp)
movq %r8, %r9
movl %ebx, %ecx
leaq .LC19(%rip), %rdx
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 1200
leaq 40(%rsp), %rdi
movl $67108868, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L79
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L80
movl $1, %ecx
movl $67108868, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L81
movl $1, %ecx
movl $67108868, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L82
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
.LEHE0:
movl $0, %esi
movq 80(%rsp), %rdi
.LEHB1:
call cudaEventRecord@PLT
.LEHE1:
jmp .L83
.L77:
movl %eax, %ebp
movl $154, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.LEHB2:
call __fprintf_chk@PLT
movl %ebp, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebp, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L78:
movq 8(%r12), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
jmp .L37
.L79:
movl $196, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L80:
movl $197, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L81:
movl $200, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L82:
movl $203, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE2:
movl $1, %edi
call exit@PLT
.L83:
movl %r13d, 68(%rsp)
movl %ebp, 56(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
.LEHB3:
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L43
movl $16777217, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z38__device_stub__Z15reduceByDevice1PiS_iPiS_i
.L43:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L84
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L85
.L84:
movl $208, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L85:
leaq 80(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
movss %xmm0, 24(%rsp)
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L86
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L87
.L86:
movl $211, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L87:
movq 8(%rsp), %rcx
movq %rcx, %rbx
movl 28(%rsp), %eax
leaq 4(%rcx,%rax,4), %rbp
movq %rcx, %rax
movl $0, %edx
.L46:
addl (%rax), %edx
movl %edx, %r13d
addq $4, %rax
cmpq %rbp, %rax
jne .L46
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
movaps %xmm0, %xmm1
movss 24(%rsp), %xmm3
movaps %xmm3, %xmm2
addss %xmm0, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm3, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
movl %r13d, %ecx
leaq .LC21(%rip), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $67108868, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L88
movq %r14, %rdx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
jmp .L89
.L88:
movl $223, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
movl %eax, %r12d
testl %eax, %eax
jne .L90
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L91
.L90:
movl $224, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L91:
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movl $16777217, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z38__device_stub__Z15reduceByDevice2PiS_iPiS_i
.L49:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L92
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L93
.L92:
movl $230, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L93:
leaq 80(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
movss %xmm0, 24(%rsp)
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L94
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L95
.L94:
movl $233, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r12d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L95:
movq 8(%rsp), %rax
movl $0, %edx
.L52:
addl (%rax), %edx
movl %edx, %r12d
addq $4, %rax
cmpq %rbp, %rax
jne .L52
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
movaps %xmm0, %xmm1
movss 24(%rsp), %xmm4
movaps %xmm4, %xmm2
addss %xmm0, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm4, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
movl %r12d, %ecx
leaq .LC23(%rip), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $1, %ecx
movl $67108868, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, 24(%rsp)
testl %eax, %eax
jne .L96
movq %r14, %rdx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
jmp .L97
.L96:
movl $245, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 24(%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L97:
movl %eax, 24(%rsp)
testl %eax, %eax
jne .L98
movl $1, %ecx
movl $67108868, %edx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
jmp .L99
.L98:
movl $246, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 24(%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L99:
movl %eax, 24(%rsp)
testl %eax, %eax
jne .L100
movq %r14, %rdx
movl $0, %esi
movq 48(%rsp), %rdi
call cudaMemset@PLT
jmp .L101
.L100:
movl $249, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 24(%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L101:
movl %eax, 24(%rsp)
testl %eax, %eax
jne .L102
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L103
.L102:
movl $250, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 24(%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L103:
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L57
movl $16777217, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z38__device_stub__Z15reduceByDevice3PiS_iPiS_i
.L57:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, 24(%rsp)
testl %eax, %eax
jne .L104
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L105
.L104:
movl $254, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl 24(%rsp), %ebx
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L105:
leaq 80(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
movss %xmm0, 24(%rsp)
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %r14d
testl %eax, %eax
jne .L106
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L107
.L106:
movl $257, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r14d, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %r14d, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L107:
movl $0, %eax
.L60:
addl (%rbx), %eax
movl %eax, %r14d
addq $4, %rbx
cmpq %rbp, %rbx
jne .L60
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
leaq 80(%rsp), %rdi
call _ZN8GpuTimer7ElapsedEv
movaps %xmm0, %xmm1
movss 24(%rsp), %xmm5
movaps %xmm5, %xmm2
addss %xmm0, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm5, %xmm0
cvtss2sd %xmm2, %xmm2
cvtss2sd %xmm1, %xmm1
movl %r14d, %ecx
leaq .LC24(%rip), %rdx
leaq .LC22(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl %r13d, 20(%rsp)
jne .L108
.L61:
cmpl %r12d, 20(%rsp)
jne .L109
.L62:
cmpl %r14d, 20(%rsp)
je .L63
leaq .LC28(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L63
.L108:
leaq .LC26(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L61
.L109:
leaq .LC27(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L62
.L63:
movq 40(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L110
movq 48(%rsp), %rdi
call cudaFree@PLT
jmp .L111
.L110:
movl $306, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE3:
movl $1, %edi
call exit@PLT
.L111:
movl %eax, %ebx
testl %eax, %eax
jne .L112
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L113
movl $0, %eax
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L112:
.cfi_restore_state
movl $307, %r8d
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
.LEHB4:
call __fprintf_chk@PLT
movl %ebx, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
.LEHE4:
movl $1, %edi
call exit@PLT
.L70:
endbr64
movq %rax, %rbx
movq 80(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rdi
call cudaEventDestroy@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
je .L67
call __stack_chk_fail@PLT
.L67:
movq %rbx, %rdi
.LEHB5:
call _Unwind_Resume@PLT
.LEHE5:
.L113:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2067:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA2067:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE2067-.LLSDACSB2067
.LLSDACSB2067:
.uleb128 .LEHB0-.LFB2067
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB2067
.uleb128 .LEHE1-.LEHB1
.uleb128 .L70-.LFB2067
.uleb128 0
.uleb128 .LEHB2-.LFB2067
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB2067
.uleb128 .LEHE3-.LEHB3
.uleb128 .L70-.LFB2067
.uleb128 0
.uleb128 .LEHB4-.LFB2067
.uleb128 .LEHE4-.LEHB4
.uleb128 .L70-.LFB2067
.uleb128 0
.uleb128 .LEHB5-.LFB2067
.uleb128 .LEHE5-.LEHB5
.uleb128 0
.uleb128 0
.LLSDACSE2067:
.text
.size main, .-main
.section .rodata.str1.1
.LC29:
.string "_Z15reduceByDevice3PiS_i"
.LC30:
.string "_Z15reduceByDevice2PiS_i"
.LC31:
.string "_Z15reduceByDevice1PiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC29(%rip), %rdx
movq %rdx, %rcx
leaq _Z15reduceByDevice3PiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC30(%rip), %rdx
movq %rdx, %rcx
leaq _Z15reduceByDevice2PiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z15reduceByDevice1PiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define CHECK(call) \
{ \
const cudaError_t error = call; \
if (error != cudaSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
cudaGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
cudaEvent_t start;
cudaEvent_t stop;
GpuTimer()
{
cudaEventCreate(&start);
cudaEventCreate(&stop);
}
~GpuTimer()
{
cudaEventDestroy(start);
cudaEventDestroy(stop);
}
void Start()
{
cudaEventRecord(start, 0);
}
void Stop()
{
cudaEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
int reduceByHost(int * in, int n)
{
int s = in[0];
for (int i = 1; i < n; i++)
s += in[i];
return s;
}
// Kernel 1 - warp divergence
__global__ void reduceByDevice1(int * in, int * out, int n)
{
// TODO
int i = (blockIdx.x*blockDim.x + threadIdx.x)*2;
int stride;
int sum = 0;
for(stride = 0; stride < 2*threadIdx.x; stride *= 2){
if(threadIdx.x%stride == 0){
if(i+stride < n){
sum += in[i+stride];
}
}
__syncthreads();
}
out[i] = sum;
if(threadIdx.x == 0){
out[blockIdx.x*blockDim.x] = out[blockIdx.x*blockDim.x*2];
}
}
// Kernel 2 - less warp divergence
__global__ void reduceByDevice2(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = 1; stride < blockDim.x*2; stride *= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < blockDim.x/stride){
if(i + stride < n){
in[i] += in[i+stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
// Kernel 3 - less warp divergence + efficient memory access
__global__ void reduceByDevice3(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = blockDim.x; stride > 0; stride /= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < stride){
if(i + stride < n){
in[i] += in[i + stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
/*
// Kernel 4 - use shared memmory
__global__ void reduceByDevice4(int * in, int * out, int n){
// todo
// mỗi block load dữ liệu từ GMEM(ram) lên SMEM
// vì khai báo cần 1 kích thước tĩnh nên ở đây giả sử kích thước mỗi block là 256
__shared__ int blkData[2*256];
// số phần tử trước block hiện tại
int num = blockIdx.x*blockDim*2;
blkData[threadIdx.x]=in[num + threadIdx.x];
blkData[blockDim.x + threadIdx.x]=in[num + blockDim.x + threadIdx.x];
__syncthreads();
// tinh toan voi du lieu luu tai SMem
for(int stride = blockDim.x; stride > 0; stride/=2){
if(threadIdx.x < stride){
blkData[threadIdx.x]+=blkData[threadIdx.x + stride];
}
__syncthreads();
}
// chep du lieu ve lai GMem
if(threadIdx.x == 0){
out[blockIdx.x] = blkData[0];
}
}
*/
int main(int argc, char ** argv)
{
// Print out device info
cudaDeviceProp devProv;
CHECK(cudaGetDeviceProperties(&devProv, 0));
printf("**********GPU info**********\n");
printf("Name: %s\n", devProv.name); // TODO
printf("Compute capability: %d\n", devProv.major); // TODO
printf("Num SMs: %d\n", devProv.multiProcessorCount); // TODO
printf("Max num threads per SM: %d\n", devProv.maxThreadsPerMultiProcessor); // TODO
printf("Max num warps per SM: %d\n", devProv.maxThreadsPerMultiProcessor/32 ); // TODO
printf("****************************\n\n");
// Set up input size
int n = (1 << 24) + 1;
printf("Input size: %d\n", n);
// Set up execution configuration
dim3 blockSize(256); // Default
if (argc == 2) // Get block size from cmd argument
blockSize.x = atoi(argv[1]);
dim3 gridSize((n-1)/(2*blockSize.x) + 1); // TODO
printf("Grid size: %d, block size: %d\n", gridSize.x, blockSize.x);
// Allocate memories
size_t bytes = n * sizeof(int);
int * in = (int *) malloc(bytes);
int * out = (int *) malloc(gridSize.x * sizeof(int));
// Set up input data
for (int i = 0; i < n; i++)
{
// Generate a random integer in [0, 255]
in[i] = (int)(rand() & 0xFF);
}
// Reduce on host
int host_sum = reduceByHost(in, n);
printf("\n%15s%12s%16s%21s%16s\n",
"Function", "Result", "KernelTime(ms)", "Post-kernelTime(ms)", "TotalTime(ms)");
printf("%15s%12d%16s%21s%16s\n",
"reduceByHost", host_sum, "-", "-", "-");
//========================================================
// Allocate device memories
int *d_in, *d_out;
CHECK(cudaMalloc(&d_in, bytes));
CHECK(cudaMalloc(&d_out, gridSize.x * sizeof(int)));
// Copy data to device memories
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice));
// Kernel 1 - warp divergence
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice));
GpuTimer timer;
timer.Start();
reduceByDevice1<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
float kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
int device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
float postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice1", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct1 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 2 - less warp divergence
timer.Start();
reduceByDevice2<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice2", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct2 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 3 - less warp divergence + efficient memory access
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice3<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice3", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct3 = (host_sum == device_sum); // Check result
/*
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 4 - use shared memory
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice4<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice4", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct4 = (host_sum == device_sum); // Check result
*/
// Print out errors
printf("\n");
if (correct1 == false)
fprintf(stderr, "Error: reduceByDevice1 is incorrect!\n");
if (correct2 == false)
fprintf(stderr, "Error: reduceByDevice2 is incorrect!\n");
if (correct3 == false)
fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
//if (correct4 == false)
// fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
// Free device memories
CHECK(cudaFree(d_in));
CHECK(cudaFree(d_out));
//========================================================
// Free memories
free(in);
free(out);
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
int reduceByHost(int * in, int n)
{
int s = in[0];
for (int i = 1; i < n; i++)
s += in[i];
return s;
}
// Kernel 1 - warp divergence
__global__ void reduceByDevice1(int * in, int * out, int n)
{
// TODO
int i = (blockIdx.x*blockDim.x + threadIdx.x)*2;
int stride;
int sum = 0;
for(stride = 0; stride < 2*threadIdx.x; stride *= 2){
if(threadIdx.x%stride == 0){
if(i+stride < n){
sum += in[i+stride];
}
}
__syncthreads();
}
out[i] = sum;
if(threadIdx.x == 0){
out[blockIdx.x*blockDim.x] = out[blockIdx.x*blockDim.x*2];
}
}
// Kernel 2 - less warp divergence
__global__ void reduceByDevice2(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = 1; stride < blockDim.x*2; stride *= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < blockDim.x/stride){
if(i + stride < n){
in[i] += in[i+stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
// Kernel 3 - less warp divergence + efficient memory access
__global__ void reduceByDevice3(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = blockDim.x; stride > 0; stride /= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < stride){
if(i + stride < n){
in[i] += in[i + stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
/*
// Kernel 4 - use shared memmory
__global__ void reduceByDevice4(int * in, int * out, int n){
// todo
// mỗi block load dữ liệu từ GMEM(ram) lên SMEM
// vì khai báo cần 1 kích thước tĩnh nên ở đây giả sử kích thước mỗi block là 256
__shared__ int blkData[2*256];
// số phần tử trước block hiện tại
int num = blockIdx.x*blockDim*2;
blkData[threadIdx.x]=in[num + threadIdx.x];
blkData[blockDim.x + threadIdx.x]=in[num + blockDim.x + threadIdx.x];
__syncthreads();
// tinh toan voi du lieu luu tai SMem
for(int stride = blockDim.x; stride > 0; stride/=2){
if(threadIdx.x < stride){
blkData[threadIdx.x]+=blkData[threadIdx.x + stride];
}
__syncthreads();
}
// chep du lieu ve lai GMem
if(threadIdx.x == 0){
out[blockIdx.x] = blkData[0];
}
}
*/
int main(int argc, char ** argv)
{
// Print out device info
hipDeviceProp_t devProv;
CHECK(hipGetDeviceProperties(&devProv, 0));
printf("**********GPU info**********\n");
printf("Name: %s\n", devProv.name); // TODO
printf("Compute capability: %d\n", devProv.major); // TODO
printf("Num SMs: %d\n", devProv.multiProcessorCount); // TODO
printf("Max num threads per SM: %d\n", devProv.maxThreadsPerMultiProcessor); // TODO
printf("Max num warps per SM: %d\n", devProv.maxThreadsPerMultiProcessor/32 ); // TODO
printf("****************************\n\n");
// Set up input size
int n = (1 << 24) + 1;
printf("Input size: %d\n", n);
// Set up execution configuration
dim3 blockSize(256); // Default
if (argc == 2) // Get block size from cmd argument
blockSize.x = atoi(argv[1]);
dim3 gridSize((n-1)/(2*blockSize.x) + 1); // TODO
printf("Grid size: %d, block size: %d\n", gridSize.x, blockSize.x);
// Allocate memories
size_t bytes = n * sizeof(int);
int * in = (int *) malloc(bytes);
int * out = (int *) malloc(gridSize.x * sizeof(int));
// Set up input data
for (int i = 0; i < n; i++)
{
// Generate a random integer in [0, 255]
in[i] = (int)(rand() & 0xFF);
}
// Reduce on host
int host_sum = reduceByHost(in, n);
printf("\n%15s%12s%16s%21s%16s\n",
"Function", "Result", "KernelTime(ms)", "Post-kernelTime(ms)", "TotalTime(ms)");
printf("%15s%12d%16s%21s%16s\n",
"reduceByHost", host_sum, "-", "-", "-");
//========================================================
// Allocate device memories
int *d_in, *d_out;
CHECK(hipMalloc(&d_in, bytes));
CHECK(hipMalloc(&d_out, gridSize.x * sizeof(int)));
// Copy data to device memories
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice));
// Kernel 1 - warp divergence
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice));
GpuTimer timer;
timer.Start();
reduceByDevice1<<<gridSize, blockSize>>>(d_in, d_out, n);
hipDeviceSynchronize();
CHECK(hipGetLastError());
timer.Stop();
float kernelTime = timer.Elapsed();
CHECK(hipMemcpy(out, d_out, gridSize.x * sizeof(int), hipMemcpyDeviceToHost));
timer.Start();
int device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
float postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice1", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct1 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(hipMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 2 - less warp divergence
timer.Start();
reduceByDevice2<<<gridSize, blockSize>>>(d_in, d_out, n);
hipDeviceSynchronize();
CHECK(hipGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(hipMemcpy(out, d_out, gridSize.x * sizeof(int), hipMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice2", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct2 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(hipMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 3 - less warp divergence + efficient memory access
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(hipMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice3<<<gridSize, blockSize>>>(d_in, d_out, n);
hipDeviceSynchronize();
CHECK(hipGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(hipMemcpy(out, d_out, gridSize.x * sizeof(int), hipMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice3", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct3 = (host_sum == device_sum); // Check result
/*
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 4 - use shared memory
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice4<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice4", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct4 = (host_sum == device_sum); // Check result
*/
// Print out errors
printf("\n");
if (correct1 == false)
fprintf(stderr, "Error: reduceByDevice1 is incorrect!\n");
if (correct2 == false)
fprintf(stderr, "Error: reduceByDevice2 is incorrect!\n");
if (correct3 == false)
fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
//if (correct4 == false)
// fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
// Free device memories
CHECK(hipFree(d_in));
CHECK(hipFree(d_out));
//========================================================
// Free memories
free(in);
free(out);
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define CHECK(call) \
{ \
const hipError_t error = call; \
if (error != hipSuccess) \
{ \
fprintf(stderr, "Error: %s:%d, ", __FILE__, __LINE__); \
fprintf(stderr, "code: %d, reason: %s\n", error, \
hipGetErrorString(error)); \
exit(EXIT_FAILURE); \
} \
}
struct GpuTimer
{
hipEvent_t start;
hipEvent_t stop;
GpuTimer()
{
hipEventCreate(&start);
hipEventCreate(&stop);
}
~GpuTimer()
{
hipEventDestroy(start);
hipEventDestroy(stop);
}
void Start()
{
hipEventRecord(start, 0);
}
void Stop()
{
hipEventRecord(stop, 0);
}
float Elapsed()
{
float elapsed;
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsed, start, stop);
return elapsed;
}
};
int reduceByHost(int * in, int n)
{
int s = in[0];
for (int i = 1; i < n; i++)
s += in[i];
return s;
}
// Kernel 1 - warp divergence
__global__ void reduceByDevice1(int * in, int * out, int n)
{
// TODO
int i = (blockIdx.x*blockDim.x + threadIdx.x)*2;
int stride;
int sum = 0;
for(stride = 0; stride < 2*threadIdx.x; stride *= 2){
if(threadIdx.x%stride == 0){
if(i+stride < n){
sum += in[i+stride];
}
}
__syncthreads();
}
out[i] = sum;
if(threadIdx.x == 0){
out[blockIdx.x*blockDim.x] = out[blockIdx.x*blockDim.x*2];
}
}
// Kernel 2 - less warp divergence
__global__ void reduceByDevice2(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = 1; stride < blockDim.x*2; stride *= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < blockDim.x/stride){
if(i + stride < n){
in[i] += in[i+stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
// Kernel 3 - less warp divergence + efficient memory access
__global__ void reduceByDevice3(int * in, int * out, int n)
{
// TODO
int num = blockIdx.x*blockDim.x*2;
for(int stride = blockDim.x; stride > 0; stride /= 2){
int i = num + threadIdx.x*2*stride;
if(threadIdx.x < stride){
if(i + stride < n){
in[i] += in[i + stride];
}
__syncthreads();
}
}
if(threadIdx.x == 0){
out[blockIdx.x] = in[num];
}
}
/*
// Kernel 4 - use shared memmory
__global__ void reduceByDevice4(int * in, int * out, int n){
// todo
// mỗi block load dữ liệu từ GMEM(ram) lên SMEM
// vì khai báo cần 1 kích thước tĩnh nên ở đây giả sử kích thước mỗi block là 256
__shared__ int blkData[2*256];
// số phần tử trước block hiện tại
int num = blockIdx.x*blockDim*2;
blkData[threadIdx.x]=in[num + threadIdx.x];
blkData[blockDim.x + threadIdx.x]=in[num + blockDim.x + threadIdx.x];
__syncthreads();
// tinh toan voi du lieu luu tai SMem
for(int stride = blockDim.x; stride > 0; stride/=2){
if(threadIdx.x < stride){
blkData[threadIdx.x]+=blkData[threadIdx.x + stride];
}
__syncthreads();
}
// chep du lieu ve lai GMem
if(threadIdx.x == 0){
out[blockIdx.x] = blkData[0];
}
}
*/
int main(int argc, char ** argv)
{
// Print out device info
hipDeviceProp_t devProv;
CHECK(hipGetDeviceProperties(&devProv, 0));
printf("**********GPU info**********\n");
printf("Name: %s\n", devProv.name); // TODO
printf("Compute capability: %d\n", devProv.major); // TODO
printf("Num SMs: %d\n", devProv.multiProcessorCount); // TODO
printf("Max num threads per SM: %d\n", devProv.maxThreadsPerMultiProcessor); // TODO
printf("Max num warps per SM: %d\n", devProv.maxThreadsPerMultiProcessor/32 ); // TODO
printf("****************************\n\n");
// Set up input size
int n = (1 << 24) + 1;
printf("Input size: %d\n", n);
// Set up execution configuration
dim3 blockSize(256); // Default
if (argc == 2) // Get block size from cmd argument
blockSize.x = atoi(argv[1]);
dim3 gridSize((n-1)/(2*blockSize.x) + 1); // TODO
printf("Grid size: %d, block size: %d\n", gridSize.x, blockSize.x);
// Allocate memories
size_t bytes = n * sizeof(int);
int * in = (int *) malloc(bytes);
int * out = (int *) malloc(gridSize.x * sizeof(int));
// Set up input data
for (int i = 0; i < n; i++)
{
// Generate a random integer in [0, 255]
in[i] = (int)(rand() & 0xFF);
}
// Reduce on host
int host_sum = reduceByHost(in, n);
printf("\n%15s%12s%16s%21s%16s\n",
"Function", "Result", "KernelTime(ms)", "Post-kernelTime(ms)", "TotalTime(ms)");
printf("%15s%12d%16s%21s%16s\n",
"reduceByHost", host_sum, "-", "-", "-");
//========================================================
// Allocate device memories
int *d_in, *d_out;
CHECK(hipMalloc(&d_in, bytes));
CHECK(hipMalloc(&d_out, gridSize.x * sizeof(int)));
// Copy data to device memories
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice));
// Kernel 1 - warp divergence
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice));
GpuTimer timer;
timer.Start();
reduceByDevice1<<<gridSize, blockSize>>>(d_in, d_out, n);
hipDeviceSynchronize();
CHECK(hipGetLastError());
timer.Stop();
float kernelTime = timer.Elapsed();
CHECK(hipMemcpy(out, d_out, gridSize.x * sizeof(int), hipMemcpyDeviceToHost));
timer.Start();
int device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
float postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice1", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct1 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(hipMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 2 - less warp divergence
timer.Start();
reduceByDevice2<<<gridSize, blockSize>>>(d_in, d_out, n);
hipDeviceSynchronize();
CHECK(hipGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(hipMemcpy(out, d_out, gridSize.x * sizeof(int), hipMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice2", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct2 = (host_sum == device_sum); // Check result
// Reset d_in and d_out
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(hipMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 3 - less warp divergence + efficient memory access
CHECK(hipMemcpy(d_in, in, bytes, hipMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(hipMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice3<<<gridSize, blockSize>>>(d_in, d_out, n);
hipDeviceSynchronize();
CHECK(hipGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(hipMemcpy(out, d_out, gridSize.x * sizeof(int), hipMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice3", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct3 = (host_sum == device_sum); // Check result
/*
// Reset d_in and d_out
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
// Kernel 4 - use shared memory
CHECK(cudaMemcpy(d_in, in, bytes, cudaMemcpyHostToDevice)); // Re-copy input data to d_in
CHECK(cudaMemset(d_out, 0, gridSize.x * sizeof(int))); // Reset d_out
timer.Start();
reduceByDevice4<<<gridSize, blockSize>>>(d_in, d_out, n);
cudaDeviceSynchronize();
CHECK(cudaGetLastError());
timer.Stop();
kernelTime = timer.Elapsed();
CHECK(cudaMemcpy(out, d_out, gridSize.x * sizeof(int), cudaMemcpyDeviceToHost));
timer.Start();
device_sum = 0;
for (int i = 0; i < gridSize.x; i++)
device_sum += out[i];
timer.Stop();
postKernelTime = timer.Elapsed();
printf("%15s%12d%16.3f%21.3f%16.3f\n",
"reduceByDevice4", device_sum, kernelTime, postKernelTime, kernelTime + postKernelTime);
bool correct4 = (host_sum == device_sum); // Check result
*/
// Print out errors
printf("\n");
if (correct1 == false)
fprintf(stderr, "Error: reduceByDevice1 is incorrect!\n");
if (correct2 == false)
fprintf(stderr, "Error: reduceByDevice2 is incorrect!\n");
if (correct3 == false)
fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
//if (correct4 == false)
// fprintf(stderr, "Error: reduceByDevice3 is incorrect!\n");
// Free device memories
CHECK(hipFree(d_in));
CHECK(hipFree(d_out));
//========================================================
// Free memories
free(in);
free(out);
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15reduceByDevice1PiS_i
.globl _Z15reduceByDevice1PiS_i
.p2align 8
.type _Z15reduceByDevice1PiS_i,@function
_Z15reduceByDevice1PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s15, s2
s_lshl_b32 s4, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s5, 0
s_add_u32 s6, s0, s6
s_addc_u32 s7, s1, s7
s_lshl_b64 s[8:9], s[4:5], 2
global_store_b32 v0, v0, s[6:7]
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_mov_b32 s3, s5
global_load_b32 v1, v0, s[8:9]
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reduceByDevice1PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15reduceByDevice1PiS_i, .Lfunc_end0-_Z15reduceByDevice1PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15reduceByDevice2PiS_i
.globl _Z15reduceByDevice2PiS_i
.p2align 8
.type _Z15reduceByDevice2PiS_i,@function
_Z15reduceByDevice2PiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s7, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s3
s_lshl_b32 s6, s6, 1
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB1_7
s_load_b32 s8, s[0:1], 0x10
v_lshlrev_b32_e32 v5, 1, v0
s_branch .LBB1_4
.LBB1_2:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s9
s_lshl_b32 s9, s7, 1
s_cmp_ge_u32 s7, s3
s_mov_b32 s7, s9
s_cbranch_scc1 .LBB1_7
.LBB1_4:
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s10, 0, s7
s_waitcnt_depctr 0xfff
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s10, s9
s_mul_hi_u32 s10, s9, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, s10
s_mul_hi_u32 s9, s3, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s9, s7
s_add_i32 s11, s9, 1
s_sub_i32 s10, s3, s10
s_sub_i32 s12, s10, s7
s_cmp_ge_u32 s10, s7
s_cselect_b32 s9, s11, s9
s_cselect_b32 s10, s12, s10
s_add_i32 s11, s9, 1
s_cmp_ge_u32 s10, s7
s_cselect_b32 s9, s11, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s9, v0
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_3
v_mad_u64_u32 v[1:2], null, v5, s7, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s7, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB1_2
.LBB1_7:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
s_ashr_i32 s7, s6, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[6:7], s[6:7], 2
s_load_b64 s[0:1], s[0:1], 0x8
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_mov_b32 s3, 0
global_load_b32 v1, v0, s[4:5]
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reduceByDevice2PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15reduceByDevice2PiS_i, .Lfunc_end1-_Z15reduceByDevice2PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15reduceByDevice3PiS_i
.globl _Z15reduceByDevice3PiS_i
.p2align 8
.type _Z15reduceByDevice3PiS_i,@function
_Z15reduceByDevice3PiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s3
s_lshl_b32 s6, s6, 1
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB2_7
s_load_b32 s7, s[0:1], 0x10
v_lshlrev_b32_e32 v5, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_4
.p2align 6
.LBB2_2:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s8
s_lshr_b32 s8, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s8
s_cbranch_scc1 .LBB2_7
.LBB2_4:
s_mov_b32 s8, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB2_3
v_mad_u32_u24 v1, v5, s3, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s3, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s7, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_2
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB2_2
.LBB2_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_9
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s6, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[6:7], s[6:7], 2
s_load_b64 s[0:1], s[0:1], 0x8
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_mov_b32 s3, 0
global_load_b32 v1, v0, s[4:5]
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reduceByDevice3PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15reduceByDevice3PiS_i, .Lfunc_end2-_Z15reduceByDevice3PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reduceByDevice1PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15reduceByDevice1PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reduceByDevice2PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15reduceByDevice2PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reduceByDevice3PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15reduceByDevice3PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15reduceByDevice3PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e620000002100 */
/*0050*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe20003f06270 */
/*0060*/ IMAD R0, R10, c[0x0][0x0], RZ ; /* 0x000000000a007a24 */
/* 0x001fc800078e02ff */
/*0070*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fd000078e00ff */
/*0080*/ @!P0 BRA 0x1f0 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*0090*/ BSSY B0, 0x1f0 ; /* 0x0000015000007945 */
/* 0x002fe20003800000 */
/*00a0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD.SHL.U32 R6, R12, 0x2, RZ ; /* 0x000000020c067824 */
/* 0x000fc600078e00ff */
/*00c0*/ ISETP.GE.U32.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x000fda0003f06070 */
/*00d0*/ @P0 BRA 0x1b0 ; /* 0x000000d000000947 */
/* 0x001fea0003800000 */
/*00e0*/ IMAD R5, R6, R7, R0 ; /* 0x0000000706057224 */
/* 0x000fca00078e0200 */
/*00f0*/ IADD3 R3, R5, R7, RZ ; /* 0x0000000705037210 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0110*/ @P0 BRA 0x190 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fc800078e00ff */
/*0130*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*0140*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0204 */
/*0150*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0160*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea4000c1e1900 */
/*0170*/ IADD3 R9, R8, R3, RZ ; /* 0x0000000308097210 */
/* 0x004fca0007ffe0ff */
/*0180*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101904 */
/*0190*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ SHF.R.U32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fc80000011607 */
/*01c0*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*01d0*/ @P0 BRA 0xc0 ; /* 0xfffffee000000947 */
/* 0x000fea000383ffff */
/*01e0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01f0*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x002fda0003f05270 */
/*0200*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fc800078e00ff */
/*0220*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*0230*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0240*/ IMAD.WIDE.U32 R4, R10, R5, c[0x0][0x168] ; /* 0x00005a000a047625 */
/* 0x000fca00078e0005 */
/*0250*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ BRA 0x270; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15reduceByDevice2PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0040*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e620000002100 */
/*0050*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*0060*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*0070*/ IMAD R6, R0, UR4, RZ ; /* 0x0000000400067c24 */
/* 0x001fd8000f8e02ff */
/*0080*/ @!P0 BRA 0x310 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R8, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff087435 */
/* 0x000fe200000001ff */
/*00a0*/ BSSY B0, 0x310 ; /* 0x0000026000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.SHL.U32 R7, R10, 0x2, RZ ; /* 0x000000020a077824 */
/* 0x002fce00078e00ff */
/*00c0*/ I2F.U32.RP R4, R8 ; /* 0x0000000800047306 */
/* 0x001e220000209000 */
/*00d0*/ ISETP.NE.U32.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fce0003f45070 */
/*00e0*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0110*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x001fe20000000f00 */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a03 */
/*0130*/ IMAD R5, R5, R8, RZ ; /* 0x0000000805057224 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*0150*/ IMAD.HI.U32 R3, R3, c[0x0][0x0], RZ ; /* 0x0000000003037a27 */
/* 0x000fc800078e00ff */
/*0160*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0170*/ IMAD R5, R8, R5, c[0x0][0x0] ; /* 0x0000000008057624 */
/* 0x000fca00078e0205 */
/*0180*/ ISETP.GE.U32.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f06070 */
/*0190*/ @P0 IADD3 R5, R5, -R8.reuse, RZ ; /* 0x8000000805050210 */
/* 0x080fe40007ffe0ff */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*01b0*/ ISETP.GE.U32.AND P1, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x000fda0003f26070 */
/*01c0*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*01d0*/ @!P2 LOP3.LUT R3, RZ, R8, RZ, 0x33, !PT ; /* 0x00000008ff03a212 */
/* 0x000fc800078e33ff */
/*01e0*/ ISETP.GE.U32.AND P0, PT, R10, R3, PT ; /* 0x000000030a00720c */
/* 0x000fda0003f06070 */
/*01f0*/ @P0 BRA 0x2d0 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD R5, R7, R8, R6 ; /* 0x0000000807057224 */
/* 0x000fc800078e0206 */
/*0210*/ IMAD.IADD R3, R5, 0x1, R8 ; /* 0x0000000105037824 */
/* 0x000fca00078e0208 */
/*0220*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fda0003f06270 */
/*0230*/ @P0 BRA 0x2b0 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0240*/ MOV R4, 0x4 ; /* 0x0000000400047802 */
/* 0x000fca0000000f00 */
/*0250*/ IMAD.WIDE R2, R3, R4, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fc800078e0204 */
/*0260*/ IMAD.WIDE R4, R5, R4, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fe400078e0204 */
/*0270*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*0280*/ LDG.E R9, [R4.64] ; /* 0x0000000604097981 */
/* 0x000ea4000c1e1900 */
/*0290*/ IMAD.IADD R9, R9, 0x1, R2 ; /* 0x0000000109097824 */
/* 0x004fca00078e0202 */
/*02a0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0001e4000c101906 */
/*02b0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*02c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02d0*/ SHF.L.U32 R8, R8, 0x1, RZ ; /* 0x0000000108087819 */
/* 0x000fc800000006ff */
/*02e0*/ ISETP.GE.U32.AND P0, PT, R8, UR4, PT ; /* 0x0000000408007c0c */
/* 0x000fda000bf06070 */
/*02f0*/ @!P0 BRA 0xc0 ; /* 0xfffffdc000008947 */
/* 0x000fea000383ffff */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x002fda0003f05270 */
/*0320*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fc800078e00ff */
/*0340*/ IMAD.WIDE R2, R6, R5, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fcc00078e0205 */
/*0350*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0360*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0005 */
/*0370*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101906 */
/*0380*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0390*/ BRA 0x390; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15reduceByDevice1PiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ LOP3.LUT P0, RZ, R3.reuse, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x041fe4000780c0ff */
/*0060*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f25270 */
/*0070*/ IMAD R4, R4, c[0x0][0x0], RZ ; /* 0x0000000004047a24 */
/* 0x002fca00078e02ff */
/*0080*/ IADD3 R0, R4, R3, RZ ; /* 0x0000000304007210 */
/* 0x000fc80007ffe0ff */
/*0090*/ SHF.L.U32 R0, R0, 0x1, RZ ; /* 0x0000000100007819 */
/* 0x000fca00000006ff */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fe200078e0205 */
/*00b0*/ @!P0 BRA 0xf0 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00c0*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*00d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00e0*/ BRA 0xc0 ; /* 0xffffffd000007947 */
/* 0x000fea000383ffff */
/*00f0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0100*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0110*/ SHF.L.U32 R2, R4, 0x1, RZ ; /* 0x0000000104027819 */
/* 0x001fca00000006ff */
/*0120*/ IMAD.WIDE.U32 R2, R2, R5, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0005 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0005 */
/*0150*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15reduceByDevice1PiS_i
.globl _Z15reduceByDevice1PiS_i
.p2align 8
.type _Z15reduceByDevice1PiS_i,@function
_Z15reduceByDevice1PiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s15, s2
s_lshl_b32 s4, s2, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s5, s4, 31
s_lshl_b64 s[6:7], s[4:5], 2
s_mov_b32 s5, 0
s_add_u32 s6, s0, s6
s_addc_u32 s7, s1, s7
s_lshl_b64 s[8:9], s[4:5], 2
global_store_b32 v0, v0, s[6:7]
s_add_u32 s8, s0, s8
s_addc_u32 s9, s1, s9
s_mov_b32 s3, s5
global_load_b32 v1, v0, s[8:9]
s_lshl_b64 s[2:3], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reduceByDevice1PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15reduceByDevice1PiS_i, .Lfunc_end0-_Z15reduceByDevice1PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15reduceByDevice2PiS_i
.globl _Z15reduceByDevice2PiS_i
.p2align 8
.type _Z15reduceByDevice2PiS_i,@function
_Z15reduceByDevice2PiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s7, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s3
s_lshl_b32 s6, s6, 1
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB1_7
s_load_b32 s8, s[0:1], 0x10
v_lshlrev_b32_e32 v5, 1, v0
s_branch .LBB1_4
.LBB1_2:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB1_3:
s_or_b32 exec_lo, exec_lo, s9
s_lshl_b32 s9, s7, 1
s_cmp_ge_u32 s7, s3
s_mov_b32 s7, s9
s_cbranch_scc1 .LBB1_7
.LBB1_4:
v_cvt_f32_u32_e32 v1, s7
s_sub_i32 s10, 0, s7
s_waitcnt_depctr 0xfff
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s9, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s10, s9
s_mul_hi_u32 s10, s9, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s9, s9, s10
s_mul_hi_u32 s9, s3, s9
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s10, s9, s7
s_add_i32 s11, s9, 1
s_sub_i32 s10, s3, s10
s_sub_i32 s12, s10, s7
s_cmp_ge_u32 s10, s7
s_cselect_b32 s9, s11, s9
s_cselect_b32 s10, s12, s10
s_add_i32 s11, s9, 1
s_cmp_ge_u32 s10, s7
s_cselect_b32 s9, s11, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s9, v0
s_and_saveexec_b32 s9, vcc_lo
s_cbranch_execz .LBB1_3
v_mad_u64_u32 v[1:2], null, v5, s7, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s7, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s8, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB1_2
.LBB1_7:
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
s_ashr_i32 s7, s6, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[6:7], s[6:7], 2
s_load_b64 s[0:1], s[0:1], 0x8
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_mov_b32 s3, 0
global_load_b32 v1, v0, s[4:5]
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reduceByDevice2PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15reduceByDevice2PiS_i, .Lfunc_end1-_Z15reduceByDevice2PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15reduceByDevice3PiS_i
.globl _Z15reduceByDevice3PiS_i
.p2align 8
.type _Z15reduceByDevice3PiS_i,@function
_Z15reduceByDevice3PiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x0
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s6, s15, s3
s_lshl_b32 s6, s6, 1
s_cmp_eq_u32 s3, 0
s_cbranch_scc1 .LBB2_7
s_load_b32 s7, s[0:1], 0x10
v_lshlrev_b32_e32 v5, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_4
.p2align 6
.LBB2_2:
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB2_3:
s_or_b32 exec_lo, exec_lo, s8
s_lshr_b32 s8, s3, 1
s_cmp_lt_u32 s3, 2
s_mov_b32 s3, s8
s_cbranch_scc1 .LBB2_7
.LBB2_4:
s_mov_b32 s8, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB2_3
v_mad_u32_u24 v1, v5, s3, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, s3, v1
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, s7, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_2
v_ashrrev_i32_e32 v4, 31, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
s_clause 0x1
global_load_b32 v3, v[3:4], off
global_load_b32 v4, v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v3, v4, v3
global_store_b32 v[1:2], v3, off
s_branch .LBB2_2
.LBB2_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB2_9
s_waitcnt lgkmcnt(0)
s_ashr_i32 s7, s6, 31
v_mov_b32_e32 v0, 0
s_lshl_b64 s[6:7], s[6:7], 2
s_load_b64 s[0:1], s[0:1], 0x8
s_add_u32 s4, s4, s6
s_addc_u32 s5, s5, s7
s_mov_b32 s3, 0
global_load_b32 v1, v0, s[4:5]
s_lshl_b64 s[2:3], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
.LBB2_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15reduceByDevice3PiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15reduceByDevice3PiS_i, .Lfunc_end2-_Z15reduceByDevice3PiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reduceByDevice1PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z15reduceByDevice1PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reduceByDevice2PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15reduceByDevice2PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15reduceByDevice3PiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15reduceByDevice3PiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define BDIMX 32
#define BDIMY 16
dim3 block (BDIMX, BDIMY);
dim3 grid (1,1);
__global__ void setRowReadRow(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.y][threadIdx.x] ;
}
__global__ void setColReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMX][BDIMY];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.x][threadIdx.y] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.x][threadIdx.y];
}
__global__ void setRowReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from 2D thread index to linear memory
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed coordinate (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[icol][irow];
}
__global__ void setRowReadColDyn(int *out)
{
// dynamic shared memory
extern __shared__ int tile[];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// convert back to smem idx to access the transposed element
unsigned int col_idx = icol * blockDim.x + irow;
// shared memory store operation
tile[idx] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[col_idx];
}
int main()
{
int *c;
c = (int*)malloc(BDIMX * BDIMY * sizeof(int));
int *d_C;
cudaMalloc(&d_C, BDIMX * BDIMY * sizeof(int));
setRowReadRow<<<grid, block, BDIMX * BDIMY * sizeof(int)>>>(d_C);
cudaDeviceSynchronize();
cudaMemcpy(c, d_C, BDIMX * BDIMY * sizeof(int), cudaMemcpyDeviceToHost);
for (int y = 0; y < BDIMY; y++)
{
printf("[ ");
for (int x = 0; x < BDIMX; x++)
printf("% 4d ", c[y * BDIMX + x]);
printf("]\n");
}
cudaFree(d_C);
free(c);
return 0;
} | code for sm_80
Function : _Z16setRowReadColDynPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x4] ; /* 0x0000010000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x4], PT ; /* 0x00000100ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e660000002100 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fe200078e0205 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fc80007ffe0ff */
/*0090*/ STS [R0.X4], R0 ; /* 0x0000000000007388 */
/* 0x000fe40000004800 */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00c0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00d0*/ IMAD R7, R7, c[0x0][0x4], RZ ; /* 0x0000010007077a24 */
/* 0x000fca00078e02ff */
/*00e0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0110*/ IMAD R2, R5, c[0x0][0x4], R0 ; /* 0x0000010005027a24 */
/* 0x000fe200078e0200 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x4], PT ; /* 0x0000010002007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R2, R2, -c[0x0][0x4], RZ ; /* 0x8000010002020a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x4], PT ; /* 0x0000010002007a0c */
/* 0x000fda0003f26070 */
/*0170*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0180*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x4], RZ, 0x33, !PT ; /* 0x00000100ff03aa12 */
/* 0x000fc800078e33ff */
/*0190*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*01a0*/ IMAD R2, R5, c[0x0][0x4], R0 ; /* 0x0000010005027a24 */
/* 0x000fc800078e0200 */
/*01b0*/ IMAD R4, R2, c[0x0][0x0], R3 ; /* 0x0000000002047a24 */
/* 0x000fe200078e0203 */
/*01c0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc80000000f00 */
/*01d0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e220000004800 */
/*01e0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13setRowReadColPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x4] ; /* 0x0000010000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x4], PT ; /* 0x00000100ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e660000002100 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R6 ; /* 0x0000000005007a24 */
/* 0x002fe200078e0206 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R7, R7, c[0x0][0x4], RZ ; /* 0x0000010007077a24 */
/* 0x000fca00078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R2, R7, c[0x0][0x4], R0 ; /* 0x0000010007027a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x4], PT ; /* 0x0000010002007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R2, R2, -c[0x0][0x4], RZ ; /* 0x8000010002020a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x4], PT ; /* 0x0000010002007a0c */
/* 0x000fda0003f26070 */
/*0150*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x4], RZ, 0x33, !PT ; /* 0x00000100ff03aa12 */
/* 0x000fc800078e33ff */
/*0170*/ IADD3 R7, -R3, RZ, RZ ; /* 0x000000ff03077210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R2, R7, c[0x0][0x4], R0 ; /* 0x0000010007027a24 */
/* 0x000fe400078e0200 */
/*0190*/ IMAD R7, R5, 0x20, R6 ; /* 0x0000002005077824 */
/* 0x000fc600078e0206 */
/*01a0*/ LEA R5, R2, R3, 0x5 ; /* 0x0000000302057211 */
/* 0x000fe400078e28ff */
/*01b0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x000fe20000004800 */
/*01c0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc60000000f00 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*01e0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*01f0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e280000004800 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13setColReadColPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x001fe200078e0203 */
/*0050*/ LEA R7, R3, R2, 0x4 ; /* 0x0000000203077211 */
/* 0x000fe200078e20ff */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc800000001ff */
/*0070*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x000fe80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*00a0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13setRowReadRowPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R2.reuse, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x041fe200078e0203 */
/*0050*/ LEA R7, R2, R3, 0x5 ; /* 0x0000000302077211 */
/* 0x000fe200078e28ff */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc800000001ff */
/*0070*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x000fe80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*00a0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define BDIMX 32
#define BDIMY 16
dim3 block (BDIMX, BDIMY);
dim3 grid (1,1);
__global__ void setRowReadRow(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.y][threadIdx.x] ;
}
__global__ void setColReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMX][BDIMY];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.x][threadIdx.y] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.x][threadIdx.y];
}
__global__ void setRowReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from 2D thread index to linear memory
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed coordinate (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[icol][irow];
}
__global__ void setRowReadColDyn(int *out)
{
// dynamic shared memory
extern __shared__ int tile[];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// convert back to smem idx to access the transposed element
unsigned int col_idx = icol * blockDim.x + irow;
// shared memory store operation
tile[idx] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[col_idx];
}
int main()
{
int *c;
c = (int*)malloc(BDIMX * BDIMY * sizeof(int));
int *d_C;
cudaMalloc(&d_C, BDIMX * BDIMY * sizeof(int));
setRowReadRow<<<grid, block, BDIMX * BDIMY * sizeof(int)>>>(d_C);
cudaDeviceSynchronize();
cudaMemcpy(c, d_C, BDIMX * BDIMY * sizeof(int), cudaMemcpyDeviceToHost);
for (int y = 0; y < BDIMY; y++)
{
printf("[ ");
for (int x = 0; x < BDIMX; x++)
printf("% 4d ", c[y * BDIMX + x]);
printf("]\n");
}
cudaFree(d_C);
free(c);
return 0;
} | .file "tmpxft_0004372e_00000000-6_sharedmem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z13setRowReadRowPiPi
.type _Z33__device_stub__Z13setRowReadRowPiPi, @function
_Z33__device_stub__Z13setRowReadRowPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13setRowReadRowPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z13setRowReadRowPiPi, .-_Z33__device_stub__Z13setRowReadRowPiPi
.globl _Z13setRowReadRowPi
.type _Z13setRowReadRowPi, @function
_Z13setRowReadRowPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13setRowReadRowPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13setRowReadRowPi, .-_Z13setRowReadRowPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[ "
.LC1:
.string "% 4d "
.LC2:
.string "]\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl 8+block(%rip), %ecx
movl $0, %r9d
movl $2048, %r8d
movq block(%rip), %rdx
movq grid(%rip), %rdi
movl 8+grid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $2048, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 128(%rbx), %rbp
leaq 2176(%rbx), %r15
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L14:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -128(%rbp), %rbx
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $-128, %rbp
cmpq %r15, %rbp
jne .L14
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z33__device_stub__Z13setRowReadRowPiPi
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z33__device_stub__Z13setColReadColPiPi
.type _Z33__device_stub__Z13setColReadColPiPi, @function
_Z33__device_stub__Z13setColReadColPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13setColReadColPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z13setColReadColPiPi, .-_Z33__device_stub__Z13setColReadColPiPi
.globl _Z13setColReadColPi
.type _Z13setColReadColPi, @function
_Z13setColReadColPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13setColReadColPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13setColReadColPi, .-_Z13setColReadColPi
.globl _Z33__device_stub__Z13setRowReadColPiPi
.type _Z33__device_stub__Z13setRowReadColPiPi, @function
_Z33__device_stub__Z13setRowReadColPiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13setRowReadColPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z13setRowReadColPiPi, .-_Z33__device_stub__Z13setRowReadColPiPi
.globl _Z13setRowReadColPi
.type _Z13setRowReadColPi, @function
_Z13setRowReadColPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13setRowReadColPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13setRowReadColPi, .-_Z13setRowReadColPi
.globl _Z36__device_stub__Z16setRowReadColDynPiPi
.type _Z36__device_stub__Z16setRowReadColDynPiPi, @function
_Z36__device_stub__Z16setRowReadColDynPiPi:
.LFB2088:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16setRowReadColDynPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z36__device_stub__Z16setRowReadColDynPiPi, .-_Z36__device_stub__Z16setRowReadColDynPiPi
.globl _Z16setRowReadColDynPi
.type _Z16setRowReadColDynPi, @function
_Z16setRowReadColDynPi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16setRowReadColDynPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z16setRowReadColDynPi, .-_Z16setRowReadColDynPi
.section .rodata.str1.1
.LC3:
.string "_Z16setRowReadColDynPi"
.LC4:
.string "_Z13setRowReadColPi"
.LC5:
.string "_Z13setColReadColPi"
.LC6:
.string "_Z13setRowReadRowPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16setRowReadColDynPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13setRowReadColPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13setColReadColPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13setRowReadRowPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl grid
.data
.align 8
.type grid, @object
.size grid, 12
grid:
.long 1
.long 1
.long 1
.globl block
.align 8
.type block, @object
.size block, 12
block:
.long 32
.long 16
.long 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define BDIMX 32
#define BDIMY 16
dim3 block (BDIMX, BDIMY);
dim3 grid (1,1);
__global__ void setRowReadRow(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.y][threadIdx.x] ;
}
__global__ void setColReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMX][BDIMY];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.x][threadIdx.y] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.x][threadIdx.y];
}
__global__ void setRowReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from 2D thread index to linear memory
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed coordinate (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[icol][irow];
}
__global__ void setRowReadColDyn(int *out)
{
// dynamic shared memory
extern __shared__ int tile[];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// convert back to smem idx to access the transposed element
unsigned int col_idx = icol * blockDim.x + irow;
// shared memory store operation
tile[idx] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[col_idx];
}
int main()
{
int *c;
c = (int*)malloc(BDIMX * BDIMY * sizeof(int));
int *d_C;
cudaMalloc(&d_C, BDIMX * BDIMY * sizeof(int));
setRowReadRow<<<grid, block, BDIMX * BDIMY * sizeof(int)>>>(d_C);
cudaDeviceSynchronize();
cudaMemcpy(c, d_C, BDIMX * BDIMY * sizeof(int), cudaMemcpyDeviceToHost);
for (int y = 0; y < BDIMY; y++)
{
printf("[ ");
for (int x = 0; x < BDIMX; x++)
printf("% 4d ", c[y * BDIMX + x]);
printf("]\n");
}
cudaFree(d_C);
free(c);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BDIMX 32
#define BDIMY 16
dim3 block (BDIMX, BDIMY);
dim3 grid (1,1);
__global__ void setRowReadRow(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.y][threadIdx.x] ;
}
__global__ void setColReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMX][BDIMY];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.x][threadIdx.y] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.x][threadIdx.y];
}
__global__ void setRowReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from 2D thread index to linear memory
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed coordinate (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[icol][irow];
}
__global__ void setRowReadColDyn(int *out)
{
// dynamic shared memory
extern __shared__ int tile[];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// convert back to smem idx to access the transposed element
unsigned int col_idx = icol * blockDim.x + irow;
// shared memory store operation
tile[idx] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[col_idx];
}
int main()
{
int *c;
c = (int*)malloc(BDIMX * BDIMY * sizeof(int));
int *d_C;
hipMalloc(&d_C, BDIMX * BDIMY * sizeof(int));
setRowReadRow<<<grid, block, BDIMX * BDIMY * sizeof(int)>>>(d_C);
hipDeviceSynchronize();
hipMemcpy(c, d_C, BDIMX * BDIMY * sizeof(int), hipMemcpyDeviceToHost);
for (int y = 0; y < BDIMY; y++)
{
printf("[ ");
for (int x = 0; x < BDIMX; x++)
printf("% 4d ", c[y * BDIMX + x]);
printf("]\n");
}
hipFree(d_C);
free(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BDIMX 32
#define BDIMY 16
dim3 block (BDIMX, BDIMY);
dim3 grid (1,1);
__global__ void setRowReadRow(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.y][threadIdx.x] ;
}
__global__ void setColReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMX][BDIMY];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.x][threadIdx.y] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.x][threadIdx.y];
}
__global__ void setRowReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from 2D thread index to linear memory
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed coordinate (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[icol][irow];
}
__global__ void setRowReadColDyn(int *out)
{
// dynamic shared memory
extern __shared__ int tile[];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// convert back to smem idx to access the transposed element
unsigned int col_idx = icol * blockDim.x + irow;
// shared memory store operation
tile[idx] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[col_idx];
}
int main()
{
int *c;
c = (int*)malloc(BDIMX * BDIMY * sizeof(int));
int *d_C;
hipMalloc(&d_C, BDIMX * BDIMY * sizeof(int));
setRowReadRow<<<grid, block, BDIMX * BDIMY * sizeof(int)>>>(d_C);
hipDeviceSynchronize();
hipMemcpy(c, d_C, BDIMX * BDIMY * sizeof(int), hipMemcpyDeviceToHost);
for (int y = 0; y < BDIMY; y++)
{
printf("[ ");
for (int x = 0; x < BDIMX; x++)
printf("% 4d ", c[y * BDIMX + x]);
printf("]\n");
}
hipFree(d_C);
free(c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13setRowReadRowPi
.globl _Z13setRowReadRowPi
.p2align 8
.type _Z13setRowReadRowPi,@function
_Z13setRowReadRowPi:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v1
v_lshl_add_u32 v2, v0, 7, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s2, v1
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13setRowReadRowPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13setRowReadRowPi, .Lfunc_end0-_Z13setRowReadRowPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13setColReadColPi
.globl _Z13setColReadColPi
.p2align 8
.type _Z13setColReadColPi,@function
_Z13setColReadColPi:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v1
v_lshl_add_u32 v2, v0, 6, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u32_u24 v0, v1, s2, v0
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13setColReadColPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13setColReadColPi, .Lfunc_end1-_Z13setColReadColPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13setRowReadColPi
.globl _Z13setRowReadColPi
.p2align 8
.type _Z13setRowReadColPi,@function
_Z13setRowReadColPi:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s4, 0, s3
v_mad_u32_u24 v4, v0, s2, v3
v_lshlrev_b32_e32 v3, 2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_lshl_add_u32 v0, v0, 7, v3
ds_store_b32 v0, v4
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_barrier
buffer_gl0_inv
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s3
v_add_nc_u32_e32 v5, 1, v1
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_add_nc_u32_e32 v5, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
v_mul_lo_u32 v2, v1, s3
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_lshl_add_u32 v1, v2, 7, v1
ds_load_b32 v0, v1
v_lshlrev_b32_e32 v1, 2, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13setRowReadColPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13setRowReadColPi, .Lfunc_end2-_Z13setRowReadColPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16setRowReadColDynPi
.globl _Z16setRowReadColDynPi
.p2align 8
.type _Z16setRowReadColDynPi,@function
_Z16setRowReadColDynPi:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s4, 0, s3
v_mad_u32_u24 v3, v0, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_lshlrev_b32_e32 v5, 2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v0, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v2, 1, v0
v_mul_lo_u32 v1, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_subrev_nc_u32_e32 v4, s3, v1
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, 1, v0
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s3
v_sub_nc_u32_e32 v4, v3, v1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s2, v[0:1]
v_add_nc_u32_e32 v0, 0, v5
ds_store_b32 v0, v3
v_lshl_add_u32 v1, v1, 2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v5, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16setRowReadColDynPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z16setRowReadColDynPi, .Lfunc_end3-_Z16setRowReadColDynPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13setRowReadRowPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z13setRowReadRowPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13setColReadColPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z13setColReadColPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13setRowReadColPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z13setRowReadColPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
- .offset: 128
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16setRowReadColDynPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z16setRowReadColDynPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define BDIMX 32
#define BDIMY 16
dim3 block (BDIMX, BDIMY);
dim3 grid (1,1);
__global__ void setRowReadRow(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.y][threadIdx.x] ;
}
__global__ void setColReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMX][BDIMY];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// shared memory store operation
tile[threadIdx.x][threadIdx.y] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[threadIdx.x][threadIdx.y];
}
__global__ void setRowReadCol(int *out)
{
// static shared memory
__shared__ int tile[BDIMY][BDIMX];
// mapping from 2D thread index to linear memory
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed coordinate (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// shared memory store operation
tile[threadIdx.y][threadIdx.x] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[icol][irow];
}
__global__ void setRowReadColDyn(int *out)
{
// dynamic shared memory
extern __shared__ int tile[];
// mapping from thread index to global memory index
unsigned int idx = threadIdx.y * blockDim.x + threadIdx.x;
// convert idx to transposed (row, col)
unsigned int irow = idx / blockDim.y;
unsigned int icol = idx % blockDim.y;
// convert back to smem idx to access the transposed element
unsigned int col_idx = icol * blockDim.x + irow;
// shared memory store operation
tile[idx] = idx;
// wait for all threads to complete
__syncthreads();
// shared memory load operation
out[idx] = tile[col_idx];
}
int main()
{
int *c;
c = (int*)malloc(BDIMX * BDIMY * sizeof(int));
int *d_C;
hipMalloc(&d_C, BDIMX * BDIMY * sizeof(int));
setRowReadRow<<<grid, block, BDIMX * BDIMY * sizeof(int)>>>(d_C);
hipDeviceSynchronize();
hipMemcpy(c, d_C, BDIMX * BDIMY * sizeof(int), hipMemcpyDeviceToHost);
for (int y = 0; y < BDIMY; y++)
{
printf("[ ");
for (int x = 0; x < BDIMX; x++)
printf("% 4d ", c[y * BDIMX + x]);
printf("]\n");
}
hipFree(d_C);
free(c);
return 0;
} | .text
.file "sharedmem.hip"
.globl _Z28__device_stub__setRowReadRowPi # -- Begin function _Z28__device_stub__setRowReadRowPi
.p2align 4, 0x90
.type _Z28__device_stub__setRowReadRowPi,@function
_Z28__device_stub__setRowReadRowPi: # @_Z28__device_stub__setRowReadRowPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13setRowReadRowPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z28__device_stub__setRowReadRowPi, .Lfunc_end0-_Z28__device_stub__setRowReadRowPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__setColReadColPi # -- Begin function _Z28__device_stub__setColReadColPi
.p2align 4, 0x90
.type _Z28__device_stub__setColReadColPi,@function
_Z28__device_stub__setColReadColPi: # @_Z28__device_stub__setColReadColPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13setColReadColPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z28__device_stub__setColReadColPi, .Lfunc_end1-_Z28__device_stub__setColReadColPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__setRowReadColPi # -- Begin function _Z28__device_stub__setRowReadColPi
.p2align 4, 0x90
.type _Z28__device_stub__setRowReadColPi,@function
_Z28__device_stub__setRowReadColPi: # @_Z28__device_stub__setRowReadColPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13setRowReadColPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z28__device_stub__setRowReadColPi, .Lfunc_end2-_Z28__device_stub__setRowReadColPi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__setRowReadColDynPi # -- Begin function _Z31__device_stub__setRowReadColDynPi
.p2align 4, 0x90
.type _Z31__device_stub__setRowReadColDynPi,@function
_Z31__device_stub__setRowReadColDynPi: # @_Z31__device_stub__setRowReadColDynPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16setRowReadColDynPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z31__device_stub__setRowReadColDynPi, .Lfunc_end3-_Z31__device_stub__setRowReadColDynPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq grid(%rip), %rdi
movl grid+8(%rip), %esi
movq block(%rip), %rdx
movl block+8(%rip), %ecx
movl $2048, %r8d # imm = 0x800
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13setRowReadRowPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $32, %r12
jne .LBB4_4
# %bb.5: # in Loop: Header=BB4_3 Depth=1
movl $.Lstr, %edi
callq puts@PLT
incq %r15
subq $-128, %r14
cmpq $16, %r15
jne .LBB4_3
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13setRowReadRowPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13setColReadColPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13setRowReadColPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16setRowReadColDynPi, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type block,@object # @block
.data
.globl block
.p2align 3, 0x0
block:
.long 32 # 0x20
.long 16 # 0x10
.long 1 # 0x1
.size block, 12
.type grid,@object # @grid
.globl grid
.p2align 3, 0x0
grid:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size grid, 12
.type _Z13setRowReadRowPi,@object # @_Z13setRowReadRowPi
.section .rodata,"a",@progbits
.globl _Z13setRowReadRowPi
.p2align 3, 0x0
_Z13setRowReadRowPi:
.quad _Z28__device_stub__setRowReadRowPi
.size _Z13setRowReadRowPi, 8
.type _Z13setColReadColPi,@object # @_Z13setColReadColPi
.globl _Z13setColReadColPi
.p2align 3, 0x0
_Z13setColReadColPi:
.quad _Z28__device_stub__setColReadColPi
.size _Z13setColReadColPi, 8
.type _Z13setRowReadColPi,@object # @_Z13setRowReadColPi
.globl _Z13setRowReadColPi
.p2align 3, 0x0
_Z13setRowReadColPi:
.quad _Z28__device_stub__setRowReadColPi
.size _Z13setRowReadColPi, 8
.type _Z16setRowReadColDynPi,@object # @_Z16setRowReadColDynPi
.globl _Z16setRowReadColDynPi
.p2align 3, 0x0
_Z16setRowReadColDynPi:
.quad _Z31__device_stub__setRowReadColDynPi
.size _Z16setRowReadColDynPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[ "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "% 4d "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13setRowReadRowPi"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13setColReadColPi"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13setRowReadColPi"
.size .L__unnamed_3, 20
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z16setRowReadColDynPi"
.size .L__unnamed_4, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "]"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__setRowReadRowPi
.addrsig_sym _Z28__device_stub__setColReadColPi
.addrsig_sym _Z28__device_stub__setRowReadColPi
.addrsig_sym _Z31__device_stub__setRowReadColDynPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13setRowReadRowPi
.addrsig_sym _Z13setColReadColPi
.addrsig_sym _Z13setRowReadColPi
.addrsig_sym _Z16setRowReadColDynPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z16setRowReadColDynPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x4] ; /* 0x0000010000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e620000002200 */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x4], PT ; /* 0x00000100ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e660000002100 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fe200078e0205 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fc80007ffe0ff */
/*0090*/ STS [R0.X4], R0 ; /* 0x0000000000007388 */
/* 0x000fe40000004800 */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00c0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00d0*/ IMAD R7, R7, c[0x0][0x4], RZ ; /* 0x0000010007077a24 */
/* 0x000fca00078e02ff */
/*00e0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV R5, RZ, RZ, -R3 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a03 */
/*0110*/ IMAD R2, R5, c[0x0][0x4], R0 ; /* 0x0000010005027a24 */
/* 0x000fe200078e0200 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe80000010000 */
/*0130*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x4], PT ; /* 0x0000010002007a0c */
/* 0x000fda0003f06070 */
/*0140*/ @P0 IADD3 R2, R2, -c[0x0][0x4], RZ ; /* 0x8000010002020a10 */
/* 0x000fe40007ffe0ff */
/*0150*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0160*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x4], PT ; /* 0x0000010002007a0c */
/* 0x000fda0003f26070 */
/*0170*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0180*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x4], RZ, 0x33, !PT ; /* 0x00000100ff03aa12 */
/* 0x000fc800078e33ff */
/*0190*/ IADD3 R5, -R3, RZ, RZ ; /* 0x000000ff03057210 */
/* 0x000fca0007ffe1ff */
/*01a0*/ IMAD R2, R5, c[0x0][0x4], R0 ; /* 0x0000010005027a24 */
/* 0x000fc800078e0200 */
/*01b0*/ IMAD R4, R2, c[0x0][0x0], R3 ; /* 0x0000000002047a24 */
/* 0x000fe200078e0203 */
/*01c0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc80000000f00 */
/*01d0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e220000004800 */
/*01e0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*01f0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13setRowReadColPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.U32.RP R4, c[0x0][0x4] ; /* 0x0000010000047b06 */
/* 0x000e220000209000 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0030*/ ISETP.NE.U32.AND P2, PT, RZ, c[0x0][0x4], PT ; /* 0x00000100ff007a0c */
/* 0x000fe20003f45070 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e660000002100 */
/*0060*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e220000001000 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R6 ; /* 0x0000000005007a24 */
/* 0x002fe200078e0206 */
/*0080*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R7, R7, c[0x0][0x4], RZ ; /* 0x0000010007077a24 */
/* 0x000fca00078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R7, R2 ; /* 0x0000000703037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fc800078e0a03 */
/*0100*/ IMAD R2, R7, c[0x0][0x4], R0 ; /* 0x0000010007027a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x4], PT ; /* 0x0000010002007a0c */
/* 0x000fda0003f06070 */
/*0120*/ @P0 IADD3 R2, R2, -c[0x0][0x4], RZ ; /* 0x8000010002020a10 */
/* 0x000fe40007ffe0ff */
/*0130*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x4], PT ; /* 0x0000010002007a0c */
/* 0x000fda0003f26070 */
/*0150*/ @P1 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103031810 */
/* 0x000fe40007ffe0ff */
/*0160*/ @!P2 LOP3.LUT R3, RZ, c[0x0][0x4], RZ, 0x33, !PT ; /* 0x00000100ff03aa12 */
/* 0x000fc800078e33ff */
/*0170*/ IADD3 R7, -R3, RZ, RZ ; /* 0x000000ff03077210 */
/* 0x000fca0007ffe1ff */
/*0180*/ IMAD R2, R7, c[0x0][0x4], R0 ; /* 0x0000010007027a24 */
/* 0x000fe400078e0200 */
/*0190*/ IMAD R7, R5, 0x20, R6 ; /* 0x0000002005077824 */
/* 0x000fc600078e0206 */
/*01a0*/ LEA R5, R2, R3, 0x5 ; /* 0x0000000302057211 */
/* 0x000fe400078e28ff */
/*01b0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x000fe20000004800 */
/*01c0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fc60000000f00 */
/*01d0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*01e0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*01f0*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e280000004800 */
/*0200*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13setColReadColPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R2, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x001fe200078e0203 */
/*0050*/ LEA R7, R3, R2, 0x4 ; /* 0x0000000203077211 */
/* 0x000fe200078e20ff */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc800000001ff */
/*0070*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x000fe80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*00a0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13setRowReadRowPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R2.reuse, c[0x0][0x0], R3 ; /* 0x0000000002007a24 */
/* 0x041fe200078e0203 */
/*0050*/ LEA R7, R2, R3, 0x5 ; /* 0x0000000302077211 */
/* 0x000fe200078e28ff */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fc800000001ff */
/*0070*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x000fe80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0090*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0003 */
/*00a0*/ LDS R5, [R7.X4] ; /* 0x0000000007057984 */
/* 0x000e280000004800 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13setRowReadRowPi
.globl _Z13setRowReadRowPi
.p2align 8
.type _Z13setRowReadRowPi,@function
_Z13setRowReadRowPi:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v1
v_lshl_add_u32 v2, v0, 7, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u32_u24 v0, v0, s2, v1
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13setRowReadRowPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13setRowReadRowPi, .Lfunc_end0-_Z13setRowReadRowPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13setColReadColPi
.globl _Z13setColReadColPi
.p2align 8
.type _Z13setColReadColPi,@function
_Z13setColReadColPi:
s_load_b32 s2, s[0:1], 0x14
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v2, 2, v1
v_lshl_add_u32 v2, v0, 6, v2
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u32_u24 v0, v1, s2, v0
ds_store_b32 v2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13setColReadColPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 3
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13setColReadColPi, .Lfunc_end1-_Z13setColReadColPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13setRowReadColPi
.globl _Z13setRowReadColPi
.p2align 8
.type _Z13setRowReadColPi,@function
_Z13setRowReadColPi:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s4, 0, s3
v_mad_u32_u24 v4, v0, s2, v3
v_lshlrev_b32_e32 v3, 2, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_lshl_add_u32 v0, v0, 7, v3
ds_store_b32 v0, v4
s_waitcnt lgkmcnt(0)
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_barrier
buffer_gl0_inv
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, s4, v1
v_mul_hi_u32 v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v1, v2
v_mul_hi_u32 v1, v4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_lo_u32 v2, v1, s3
v_add_nc_u32_e32 v5, 1, v1
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_dual_cndmask_b32 v2, v2, v6 :: v_dual_cndmask_b32 v1, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s3, v2
v_add_nc_u32_e32 v5, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v1, v1, v5, vcc_lo
v_mul_lo_u32 v2, v1, s3
v_lshlrev_b32_e32 v1, 2, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v4, v2
v_lshl_add_u32 v1, v2, 7, v1
ds_load_b32 v0, v1
v_lshlrev_b32_e32 v1, 2, v4
s_waitcnt lgkmcnt(0)
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13setRowReadColPi
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13setRowReadColPi, .Lfunc_end2-_Z13setRowReadColPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z16setRowReadColDynPi
.globl _Z16setRowReadColDynPi
.p2align 8
.type _Z16setRowReadColDynPi,@function
_Z16setRowReadColDynPi:
s_load_b32 s2, s[0:1], 0x14
v_and_b32_e32 v3, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_cvt_f32_u32_e32 v1, s3
s_sub_i32 s4, 0, s3
v_mad_u32_u24 v3, v0, s2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
v_lshlrev_b32_e32 v5, 2, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v0, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v2, 1, v0
v_mul_lo_u32 v1, v0, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v3, v1
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_subrev_nc_u32_e32 v4, s3, v1
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v2, 1, v0
v_cndmask_b32_e32 v1, v1, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s3, v1
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v1, v0, s3
v_sub_nc_u32_e32 v4, v3, v1
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, v4, s2, v[0:1]
v_add_nc_u32_e32 v0, 0, v5
ds_store_b32 v0, v3
v_lshl_add_u32 v1, v1, 2, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v0, v1
s_waitcnt lgkmcnt(0)
global_store_b32 v5, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16setRowReadColDynPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z16setRowReadColDynPi, .Lfunc_end3-_Z16setRowReadColDynPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13setRowReadRowPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z13setRowReadRowPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13setColReadColPi
.private_segment_fixed_size: 0
.sgpr_count: 3
.sgpr_spill_count: 0
.symbol: _Z13setColReadColPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13setRowReadColPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z13setRowReadColPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
- .offset: 128
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16setRowReadColDynPi
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z16setRowReadColDynPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004372e_00000000-6_sharedmem.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z13setRowReadRowPiPi
.type _Z33__device_stub__Z13setRowReadRowPiPi, @function
_Z33__device_stub__Z13setRowReadRowPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13setRowReadRowPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z13setRowReadRowPiPi, .-_Z33__device_stub__Z13setRowReadRowPiPi
.globl _Z13setRowReadRowPi
.type _Z13setRowReadRowPi, @function
_Z13setRowReadRowPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13setRowReadRowPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z13setRowReadRowPi, .-_Z13setRowReadRowPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[ "
.LC1:
.string "% 4d "
.LC2:
.string "]\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, 8(%rsp)
leaq 16(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl 8+block(%rip), %ecx
movl $0, %r9d
movl $2048, %r8d
movq block(%rip), %rdx
movq grid(%rip), %rdi
movl 8+grid(%rip), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L12:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $2048, %edx
movq 16(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq 128(%rbx), %rbp
leaq 2176(%rbx), %r15
leaq .LC0(%rip), %r14
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r13
.L14:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq -128(%rbp), %rbx
.L13:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L13
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
subq $-128, %rbp
cmpq %r15, %rbp
jne .L14
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdi
call _Z33__device_stub__Z13setRowReadRowPiPi
jmp .L12
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.globl _Z33__device_stub__Z13setColReadColPiPi
.type _Z33__device_stub__Z13setColReadColPiPi, @function
_Z33__device_stub__Z13setColReadColPiPi:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13setColReadColPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z13setColReadColPiPi, .-_Z33__device_stub__Z13setColReadColPiPi
.globl _Z13setColReadColPi
.type _Z13setColReadColPi, @function
_Z13setColReadColPi:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13setColReadColPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z13setColReadColPi, .-_Z13setColReadColPi
.globl _Z33__device_stub__Z13setRowReadColPiPi
.type _Z33__device_stub__Z13setRowReadColPiPi, @function
_Z33__device_stub__Z13setRowReadColPiPi:
.LFB2086:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L33
.L29:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13setRowReadColPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L29
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z33__device_stub__Z13setRowReadColPiPi, .-_Z33__device_stub__Z13setRowReadColPiPi
.globl _Z13setRowReadColPi
.type _Z13setRowReadColPi, @function
_Z13setRowReadColPi:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z13setRowReadColPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z13setRowReadColPi, .-_Z13setRowReadColPi
.globl _Z36__device_stub__Z16setRowReadColDynPiPi
.type _Z36__device_stub__Z16setRowReadColDynPiPi, @function
_Z36__device_stub__Z16setRowReadColDynPiPi:
.LFB2088:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z16setRowReadColDynPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z36__device_stub__Z16setRowReadColDynPiPi, .-_Z36__device_stub__Z16setRowReadColDynPiPi
.globl _Z16setRowReadColDynPi
.type _Z16setRowReadColDynPi, @function
_Z16setRowReadColDynPi:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z16setRowReadColDynPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z16setRowReadColDynPi, .-_Z16setRowReadColDynPi
.section .rodata.str1.1
.LC3:
.string "_Z16setRowReadColDynPi"
.LC4:
.string "_Z13setRowReadColPi"
.LC5:
.string "_Z13setColReadColPi"
.LC6:
.string "_Z13setRowReadRowPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z16setRowReadColDynPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z13setRowReadColPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z13setColReadColPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13setRowReadRowPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl grid
.data
.align 8
.type grid, @object
.size grid, 12
grid:
.long 1
.long 1
.long 1
.globl block
.align 8
.type block, @object
.size block, 12
block:
.long 32
.long 16
.long 1
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sharedmem.hip"
.globl _Z28__device_stub__setRowReadRowPi # -- Begin function _Z28__device_stub__setRowReadRowPi
.p2align 4, 0x90
.type _Z28__device_stub__setRowReadRowPi,@function
_Z28__device_stub__setRowReadRowPi: # @_Z28__device_stub__setRowReadRowPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13setRowReadRowPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z28__device_stub__setRowReadRowPi, .Lfunc_end0-_Z28__device_stub__setRowReadRowPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__setColReadColPi # -- Begin function _Z28__device_stub__setColReadColPi
.p2align 4, 0x90
.type _Z28__device_stub__setColReadColPi,@function
_Z28__device_stub__setColReadColPi: # @_Z28__device_stub__setColReadColPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13setColReadColPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end1:
.size _Z28__device_stub__setColReadColPi, .Lfunc_end1-_Z28__device_stub__setColReadColPi
.cfi_endproc
# -- End function
.globl _Z28__device_stub__setRowReadColPi # -- Begin function _Z28__device_stub__setRowReadColPi
.p2align 4, 0x90
.type _Z28__device_stub__setRowReadColPi,@function
_Z28__device_stub__setRowReadColPi: # @_Z28__device_stub__setRowReadColPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z13setRowReadColPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end2:
.size _Z28__device_stub__setRowReadColPi, .Lfunc_end2-_Z28__device_stub__setRowReadColPi
.cfi_endproc
# -- End function
.globl _Z31__device_stub__setRowReadColDynPi # -- Begin function _Z31__device_stub__setRowReadColDynPi
.p2align 4, 0x90
.type _Z31__device_stub__setRowReadColDynPi,@function
_Z31__device_stub__setRowReadColDynPi: # @_Z31__device_stub__setRowReadColDynPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z16setRowReadColDynPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end3:
.size _Z31__device_stub__setRowReadColDynPi, .Lfunc_end3-_Z31__device_stub__setRowReadColDynPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $88, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq grid(%rip), %rdi
movl grid+8(%rip), %esi
movq block(%rip), %rdx
movl block+8(%rip), %ecx
movl $2048, %r8d # imm = 0x800
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13setRowReadRowPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_3: # =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r14,%r12,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %r12
cmpq $32, %r12
jne .LBB4_4
# %bb.5: # in Loop: Header=BB4_3 Depth=1
movl $.Lstr, %edi
callq puts@PLT
incq %r15
subq $-128, %r14
cmpq $16, %r15
jne .LBB4_3
# %bb.6:
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13setRowReadRowPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13setColReadColPi, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13setRowReadColPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16setRowReadColDynPi, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type block,@object # @block
.data
.globl block
.p2align 3, 0x0
block:
.long 32 # 0x20
.long 16 # 0x10
.long 1 # 0x1
.size block, 12
.type grid,@object # @grid
.globl grid
.p2align 3, 0x0
grid:
.long 1 # 0x1
.long 1 # 0x1
.long 1 # 0x1
.size grid, 12
.type _Z13setRowReadRowPi,@object # @_Z13setRowReadRowPi
.section .rodata,"a",@progbits
.globl _Z13setRowReadRowPi
.p2align 3, 0x0
_Z13setRowReadRowPi:
.quad _Z28__device_stub__setRowReadRowPi
.size _Z13setRowReadRowPi, 8
.type _Z13setColReadColPi,@object # @_Z13setColReadColPi
.globl _Z13setColReadColPi
.p2align 3, 0x0
_Z13setColReadColPi:
.quad _Z28__device_stub__setColReadColPi
.size _Z13setColReadColPi, 8
.type _Z13setRowReadColPi,@object # @_Z13setRowReadColPi
.globl _Z13setRowReadColPi
.p2align 3, 0x0
_Z13setRowReadColPi:
.quad _Z28__device_stub__setRowReadColPi
.size _Z13setRowReadColPi, 8
.type _Z16setRowReadColDynPi,@object # @_Z16setRowReadColDynPi
.globl _Z16setRowReadColDynPi
.p2align 3, 0x0
_Z16setRowReadColDynPi:
.quad _Z31__device_stub__setRowReadColDynPi
.size _Z16setRowReadColDynPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "[ "
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "% 4d "
.size .L.str.1, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13setRowReadRowPi"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13setColReadColPi"
.size .L__unnamed_2, 20
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13setRowReadColPi"
.size .L__unnamed_3, 20
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z16setRowReadColDynPi"
.size .L__unnamed_4, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "]"
.size .Lstr, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__setRowReadRowPi
.addrsig_sym _Z28__device_stub__setColReadColPi
.addrsig_sym _Z28__device_stub__setRowReadColPi
.addrsig_sym _Z31__device_stub__setRowReadColDynPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13setRowReadRowPi
.addrsig_sym _Z13setColReadColPi
.addrsig_sym _Z13setRowReadColPi
.addrsig_sym _Z16setRowReadColDynPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
// DBL_INT_ADD treats two unsigned ints a and b as one 64-bit integer and adds c to it
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__device__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256_init(SHA256_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
}
__device__ void sha256_update(SHA256_CTX *ctx, uchar data[], uint len)
{
uint i;
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
}
__device__ void sha256_final(SHA256_CTX *ctx, uchar hash[])
{
uint i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
// Append to the padding the total message's length in bits and transform.
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
// Since this implementation uses little endian byte ordering and SHA uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
// DBL_INT_ADD treats two unsigned ints a and b as one 64-bit integer and adds c to it
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__device__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256_init(SHA256_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
}
__device__ void sha256_update(SHA256_CTX *ctx, uchar data[], uint len)
{
uint i;
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
}
__device__ void sha256_final(SHA256_CTX *ctx, uchar hash[])
{
uint i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
// Append to the padding the total message's length in bits and transform.
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
// Since this implementation uses little endian byte ordering and SHA uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
} | .file "tmpxft_0000ef1b_00000000-6_sha256.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16sha256_transformP10SHA256_CTXPh
.type _Z16sha256_transformP10SHA256_CTXPh, @function
_Z16sha256_transformP10SHA256_CTXPh:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z16sha256_transformP10SHA256_CTXPh, .-_Z16sha256_transformP10SHA256_CTXPh
.globl _Z11sha256_initP10SHA256_CTX
.type _Z11sha256_initP10SHA256_CTX, @function
_Z11sha256_initP10SHA256_CTX:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z11sha256_initP10SHA256_CTX, .-_Z11sha256_initP10SHA256_CTX
.globl _Z13sha256_updateP10SHA256_CTXPhj
.type _Z13sha256_updateP10SHA256_CTXPhj, @function
_Z13sha256_updateP10SHA256_CTXPhj:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z13sha256_updateP10SHA256_CTXPhj, .-_Z13sha256_updateP10SHA256_CTXPhj
.globl _Z12sha256_finalP10SHA256_CTXPh
.type _Z12sha256_finalP10SHA256_CTXPh, @function
_Z12sha256_finalP10SHA256_CTXPh:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z12sha256_finalP10SHA256_CTXPh, .-_Z12sha256_finalP10SHA256_CTXPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "k"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1k(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1k
.comm _ZL1k,256,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
// DBL_INT_ADD treats two unsigned ints a and b as one 64-bit integer and adds c to it
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__device__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256_init(SHA256_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
}
__device__ void sha256_update(SHA256_CTX *ctx, uchar data[], uint len)
{
uint i;
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
}
__device__ void sha256_final(SHA256_CTX *ctx, uchar hash[])
{
uint i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
// Append to the padding the total message's length in bits and transform.
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
// Since this implementation uses little endian byte ordering and SHA uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
} | #include <hip/hip_runtime.h>
#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
// DBL_INT_ADD treats two unsigned ints a and b as one 64-bit integer and adds c to it
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__device__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256_init(SHA256_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
}
__device__ void sha256_update(SHA256_CTX *ctx, uchar data[], uint len)
{
uint i;
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
}
__device__ void sha256_final(SHA256_CTX *ctx, uchar hash[])
{
uint i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
// Append to the padding the total message's length in bits and transform.
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
// Since this implementation uses little endian byte ordering and SHA uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
// DBL_INT_ADD treats two unsigned ints a and b as one 64-bit integer and adds c to it
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__device__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256_init(SHA256_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
}
__device__ void sha256_update(SHA256_CTX *ctx, uchar data[], uint len)
{
uint i;
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
}
__device__ void sha256_final(SHA256_CTX *ctx, uchar hash[])
{
uint i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
// Append to the padding the total message's length in bits and transform.
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
// Since this implementation uses little endian byte ordering and SHA uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected k
.type k,@object
.data
.globl k
.p2align 4, 0x0
k:
.long 1116352408
.long 1899447441
.long 3049323471
.long 3921009573
.long 961987163
.long 1508970993
.long 2453635748
.long 2870763221
.long 3624381080
.long 310598401
.long 607225278
.long 1426881987
.long 1925078388
.long 2162078206
.long 2614888103
.long 3248222580
.long 3835390401
.long 4022224774
.long 264347078
.long 604807628
.long 770255983
.long 1249150122
.long 1555081692
.long 1996064986
.long 2554220882
.long 2821834349
.long 2952996808
.long 3210313671
.long 3336571891
.long 3584528711
.long 113926993
.long 338241895
.long 666307205
.long 773529912
.long 1294757372
.long 1396182291
.long 1695183700
.long 1986661051
.long 2177026350
.long 2456956037
.long 2730485921
.long 2820302411
.long 3259730800
.long 3345764771
.long 3516065817
.long 3600352804
.long 4094571909
.long 275423344
.long 430227734
.long 506948616
.long 659060556
.long 883997877
.long 958139571
.long 1322822218
.long 1537002063
.long 1747873779
.long 1955562222
.long 2024104815
.long 2227730452
.long 2361852424
.long 2428436474
.long 2756734187
.long 3204031479
.long 3329325298
.size k, 256
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym k
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
// DBL_INT_ADD treats two unsigned ints a and b as one 64-bit integer and adds c to it
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__device__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256_init(SHA256_CTX *ctx)
{
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
}
__device__ void sha256_update(SHA256_CTX *ctx, uchar data[], uint len)
{
uint i;
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
}
__device__ void sha256_final(SHA256_CTX *ctx, uchar hash[])
{
uint i;
i = ctx->datalen;
// Pad whatever data is left in the buffer.
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
// Append to the padding the total message's length in bits and transform.
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
// Since this implementation uses little endian byte ordering and SHA uses big endian,
// reverse all the bytes when copying the final state to the output hash.
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
} | .text
.file "sha256.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $k, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $256, %r9d # imm = 0x100
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type k,@object # @k
.local k
.comm k,256,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "k"
.size .L__unnamed_1, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym k
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected k
.type k,@object
.data
.globl k
.p2align 4, 0x0
k:
.long 1116352408
.long 1899447441
.long 3049323471
.long 3921009573
.long 961987163
.long 1508970993
.long 2453635748
.long 2870763221
.long 3624381080
.long 310598401
.long 607225278
.long 1426881987
.long 1925078388
.long 2162078206
.long 2614888103
.long 3248222580
.long 3835390401
.long 4022224774
.long 264347078
.long 604807628
.long 770255983
.long 1249150122
.long 1555081692
.long 1996064986
.long 2554220882
.long 2821834349
.long 2952996808
.long 3210313671
.long 3336571891
.long 3584528711
.long 113926993
.long 338241895
.long 666307205
.long 773529912
.long 1294757372
.long 1396182291
.long 1695183700
.long 1986661051
.long 2177026350
.long 2456956037
.long 2730485921
.long 2820302411
.long 3259730800
.long 3345764771
.long 3516065817
.long 3600352804
.long 4094571909
.long 275423344
.long 430227734
.long 506948616
.long 659060556
.long 883997877
.long 958139571
.long 1322822218
.long 1537002063
.long 1747873779
.long 1955562222
.long 2024104815
.long 2227730452
.long 2361852424
.long 2428436474
.long 2756734187
.long 3204031479
.long 3329325298
.size k, 256
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym k
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000ef1b_00000000-6_sha256.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2033:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16sha256_transformP10SHA256_CTXPh
.type _Z16sha256_transformP10SHA256_CTXPh, @function
_Z16sha256_transformP10SHA256_CTXPh:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z16sha256_transformP10SHA256_CTXPh, .-_Z16sha256_transformP10SHA256_CTXPh
.globl _Z11sha256_initP10SHA256_CTX
.type _Z11sha256_initP10SHA256_CTX, @function
_Z11sha256_initP10SHA256_CTX:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z11sha256_initP10SHA256_CTX, .-_Z11sha256_initP10SHA256_CTX
.globl _Z13sha256_updateP10SHA256_CTXPhj
.type _Z13sha256_updateP10SHA256_CTXPhj, @function
_Z13sha256_updateP10SHA256_CTXPhj:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z13sha256_updateP10SHA256_CTXPhj, .-_Z13sha256_updateP10SHA256_CTXPhj
.globl _Z12sha256_finalP10SHA256_CTXPh
.type _Z12sha256_finalP10SHA256_CTXPh, @function
_Z12sha256_finalP10SHA256_CTXPh:
.LFB2030:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2030:
.size _Z12sha256_finalP10SHA256_CTXPh, .-_Z12sha256_finalP10SHA256_CTXPh
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "k"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1k(%rip), %rsi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1k
.comm _ZL1k,256,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sha256.hip"
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB0_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB0_2:
movq __hip_gpubin_handle(%rip), %rdi
movl $k, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $256, %r9d # imm = 0x100
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rax
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end0:
.size __hip_module_ctor, .Lfunc_end0-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB1_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB1_2:
retq
.Lfunc_end1:
.size __hip_module_dtor, .Lfunc_end1-__hip_module_dtor
.cfi_endproc
# -- End function
.type k,@object # @k
.local k
.comm k,256,16
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "k"
.size .L__unnamed_1, 2
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym k
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <iostream>
#include <math.h>
using namespace std;
const int max_movie = 1683;
const int max_user = 944;
#define THREAD_NUM 256
#define BLOCK_NUM 32
__global__ static void test(float* rate,float* result)
{
const int tid=threadIdx.x;
const int bid=blockIdx.x;
int i,k,j;
float sum;
for(i=bid*THREAD_NUM+tid;i<max_movie-1;i+=BLOCK_NUM*THREAD_NUM)
{
for(k=1;k<max_movie;k++)
{
if(k==i+1)
continue;
else
{
sum=0;
//count=0;
for(j=1;j<max_user;j++)
{
if((rate[j*max_movie+i+1]==-1)||(rate[j*max_movie+k]==-1))
continue;
else
{
sum=sum+(rate[j*max_movie+i+1]-rate[j*max_movie+k])*(rate[j*max_movie+i+1]-rate[j*max_movie+k]);
//count++;
}
}
result[(i+1)*max_movie+k]=sqrt(sum);
}
}
}
}
int main()
{
cout<<"start:"<<endl;
FILE *fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.base","r");
float a[max_movie*max_user];
float* res;
res=(float*)malloc(sizeof(float)*max_movie*max_movie);
int movieid,userid,stamp,i,j;
float rating;
float* gpudata;
float* result;
float min;
int minindex1,minindex2,minindex3,k;
//cout<<"yes"<<endl;
//cout<<"4";
for(i=0;i<max_user;i++)
for(j=0;j<max_movie;j++)
a[i*max_movie+j]=-1;
//cout<<"3";
cudaMalloc((void**)&gpudata,sizeof(float)*max_movie*max_user);
cudaMalloc((void**)&result,sizeof(float)*max_movie*max_movie);
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
a[userid*max_movie+movieid]=rating;
}
fclose(fp);
cudaMemcpy(gpudata,a,sizeof(float)*max_movie*max_user,cudaMemcpyHostToDevice);
//cout<<"1";
test<<<BLOCK_NUM,THREAD_NUM,0>>>(gpudata,result);
cudaMemcpy(res,result,sizeof(float)*max_movie*max_movie,cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.test","r");
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if(i==(movieid*max_movie+movieid))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex1=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex2=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1))||(i==(movieid*max_movie+minindex2)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex3=k;
min=res[i];
}
}
}
cout<<"userid:"<<userid<<" ";
cout<<"movieid:"<<movieid<<" ";
cout<<"estimate:"<<(float)(a[userid*max_movie+minindex1]+a[userid*max_movie+minindex2]+a[userid*max_movie+minindex3])/3<<" ";
cout<<"real:"<<rating<<endl;
cout<<endl;
}
fclose(fp);
//cout<<res[1687];
} | code for sm_80
Function : _Z4testPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, 0x100, R0 ; /* 0x0000010003007824 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x691, PT ; /* 0x000006910000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff037435 */
/* 0x000fe200000001ff */
/*0080*/ IADD3 R2, R0, 0x694, RZ ; /* 0x0000069400027810 */
/* 0x001fca0007ffe0ff */
/*0090*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x001fe20007ffe0ff */
/*00a0*/ BSSY B0, 0x510 ; /* 0x0000046000007945 */
/* 0x000fe60003800000 */
/*00b0*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f05270 */
/*00c0*/ @!P0 BRA 0x500 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R13, R3, 0x693, RZ ; /* 0x00000693030d7810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fca0000000f00 */
/*0120*/ IMAD.WIDE R6, R2, 0x4, R4 ; /* 0x0000000402067825 */
/* 0x000fca00078e0204 */
/*0130*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R14, [R6.64+0x1a4c] ; /* 0x001a4c04060e7981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R15, [R6.64+0x3498] ; /* 0x00349804060f7981 */
/* 0x000f22000c1e1900 */
/*0160*/ BSSY B1, 0x220 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0170*/ ISETP.NE.AND P0, PT, R16, 0x3ac, PT ; /* 0x000003ac1000780c */
/* 0x000fe20003f05270 */
/*0180*/ IMAD.WIDE R8, R13, 0x4, R4 ; /* 0x000000040d087825 */
/* 0x000fe200078e0204 */
/*0190*/ FSETP.NEU.AND P3, PT, R11, -1, PT ; /* 0xbf8000000b00780b */
/* 0x004fc40003f6d000 */
/*01a0*/ FSETP.NEU.AND P1, PT, R14, -1, PT ; /* 0xbf8000000e00780b */
/* 0x008fe40003f2d000 */
/*01b0*/ FSETP.NEU.AND P2, PT, R15, -1, PT ; /* 0xbf8000000f00780b */
/* 0x010fd20003f4d000 */
/*01c0*/ @!P3 BRA 0x210 ; /* 0x000000400000b947 */
/* 0x000fea0003800000 */
/*01d0*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FSETP.NEU.AND P3, PT, R12, -1, PT ; /* 0xbf8000000c00780b */
/* 0x004fda0003f6d000 */
/*01f0*/ @P3 FADD R11, R11, -R12 ; /* 0x8000000c0b0b3221 */
/* 0x000fc80000000000 */
/*0200*/ @P3 FFMA R10, R11, R11, R10 ; /* 0x0000000b0b0a3223 */
/* 0x000fe4000000000a */
/*0210*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0220*/ BSSY B1, 0x290 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0230*/ @!P1 BRA 0x280 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E R11, [R8.64+0x1a4c] ; /* 0x001a4c04080b7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FSETP.NEU.AND P1, PT, R11, -1, PT ; /* 0xbf8000000b00780b */
/* 0x004fda0003f2d000 */
/*0260*/ @P1 FADD R11, R14, -R11 ; /* 0x8000000b0e0b1221 */
/* 0x000fc80000000000 */
/*0270*/ @P1 FFMA R10, R11, R11, R10 ; /* 0x0000000b0b0a1223 */
/* 0x000fe4000000000a */
/*0280*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0290*/ BSSY B1, 0x300 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*02a0*/ @!P2 BRA 0x2f0 ; /* 0x000000400000a947 */
/* 0x000fea0003800000 */
/*02b0*/ LDG.E R12, [R8.64+0x3498] ; /* 0x00349804080c7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ FSETP.NEU.AND P1, PT, R12, -1, PT ; /* 0xbf8000000c00780b */
/* 0x004fda0003f2d000 */
/*02d0*/ @P1 FADD R11, R15, -R12 ; /* 0x8000000c0f0b1221 */
/* 0x000fc80000000000 */
/*02e0*/ @P1 FFMA R10, R11, R11, R10 ; /* 0x0000000b0b0a1223 */
/* 0x000fe4000000000a */
/*02f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0300*/ @!P0 BRA 0x3e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R7, [R6.64+0x4ee4] ; /* 0x004ee40406077981 */
/* 0x000ea2000c1e1900 */
/*0320*/ BSSY B1, 0x3a0 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0330*/ FSETP.NEU.AND P0, PT, R7, -1, PT ; /* 0xbf8000000700780b */
/* 0x004fda0003f0d000 */
/*0340*/ @!P0 BRA 0x390 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0350*/ LDG.E R8, [R8.64+0x4ee4] ; /* 0x004ee40408087981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FSETP.NEU.AND P0, PT, R8, -1, PT ; /* 0xbf8000000800780b */
/* 0x004fda0003f0d000 */
/*0370*/ @P0 FADD R7, R7, -R8 ; /* 0x8000000807070221 */
/* 0x000fc80000000000 */
/*0380*/ @P0 FFMA R10, R7, R7, R10 ; /* 0x00000007070a0223 */
/* 0x000fe4000000000a */
/*0390*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R4, P0, R4, 0x6930, RZ ; /* 0x0000693004047810 */
/* 0x000fe40007f1e0ff */
/*03b0*/ IADD3 R16, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fc60007ffe0ff */
/*03c0*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe200000e0605 */
/*03d0*/ BRA 0x120 ; /* 0xfffffd4000007947 */
/* 0x000fea000383ffff */
/*03e0*/ IADD3 R4, R10, -0xd000000, RZ ; /* 0xf30000000a047810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ MUFU.RSQ R5, R10 ; /* 0x0000000a00057308 */
/* 0x0000620000001400 */
/*0400*/ BSSY B1, 0x4b0 ; /* 0x000000a000017945 */
/* 0x000fe40003800000 */
/*0410*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0420*/ @!P0 BRA 0x460 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0430*/ MOV R9, 0x450 ; /* 0x0000045000097802 */
/* 0x003fe40000000f00 */
/*0440*/ CALL.REL.NOINC 0x580 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*0450*/ BRA 0x4a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0460*/ FMUL.FTZ R7, R10, R5 ; /* 0x000000050a077220 */
/* 0x003fe40000410000 */
/*0470*/ FMUL.FTZ R4, R5, 0.5 ; /* 0x3f00000005047820 */
/* 0x000fe40000410000 */
/*0480*/ FFMA R10, -R7, R7, R10 ; /* 0x00000007070a7223 */
/* 0x000fc8000000010a */
/*0490*/ FFMA R7, R10, R4, R7 ; /* 0x000000040a077223 */
/* 0x000fe40000000007 */
/*04a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD R4, R0, 0x693, R3 ; /* 0x0000069300047824 */
/* 0x000fe200078e0203 */
/*04c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc800000001ff */
/*04d0*/ IADD3 R4, R4, 0x693, RZ ; /* 0x0000069304047810 */
/* 0x000fcc0007ffe0ff */
/*04e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*04f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0520*/ ISETP.GE.U32.AND P0, PT, R3, 0x693, PT ; /* 0x000006930300780c */
/* 0x000fda0003f06070 */
/*0530*/ @!P0 BRA 0x90 ; /* 0xfffffb5000008947 */
/* 0x000fea000383ffff */
/*0540*/ ISETP.GE.AND P0, PT, R0.reuse, -0x196e, PT ; /* 0xffffe6920000780c */
/* 0x040fe40003f06270 */
/*0550*/ IADD3 R0, R0, 0x2000, RZ ; /* 0x0000200000007810 */
/* 0x000fd60007ffe0ff */
/*0560*/ @!P0 BRA 0x70 ; /* 0xfffffb0000008947 */
/* 0x000fea000383ffff */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0590*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff048224 */
/* 0x000fe200078e000a */
/*05a0*/ @!P0 BRA 0x6b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*05b0*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f1e000 */
/*05c0*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*05d0*/ @!P0 BRA 0x6b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05e0*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1c200 */
/*05f0*/ @P0 FADD.FTZ R4, R10, 1 ; /* 0x3f8000000a040421 */
/* 0x000fe20000010000 */
/*0600*/ @P0 BRA 0x6b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0610*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1d200 */
/*0620*/ @P0 FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a050823 */
/* 0x000fc800000000ff */
/*0630*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0640*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*0650*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe40000410000 */
/*0660*/ @P0 FADD.FTZ R7, -R6.reuse, -RZ ; /* 0x800000ff06070221 */
/* 0x040fe40000010100 */
/*0670*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff048224 */
/* 0x000fe400078e000a */
/*0680*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0690*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*06a0*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*06b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*06c0*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fe20000000f00 */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0009 */
/*06e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff91004007950 */
/* 0x000fea0003c3ffff */
/*06f0*/ BRA 0x6f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <iostream>
#include <math.h>
using namespace std;
const int max_movie = 1683;
const int max_user = 944;
#define THREAD_NUM 256
#define BLOCK_NUM 32
__global__ static void test(float* rate,float* result)
{
const int tid=threadIdx.x;
const int bid=blockIdx.x;
int i,k,j;
float sum;
for(i=bid*THREAD_NUM+tid;i<max_movie-1;i+=BLOCK_NUM*THREAD_NUM)
{
for(k=1;k<max_movie;k++)
{
if(k==i+1)
continue;
else
{
sum=0;
//count=0;
for(j=1;j<max_user;j++)
{
if((rate[j*max_movie+i+1]==-1)||(rate[j*max_movie+k]==-1))
continue;
else
{
sum=sum+(rate[j*max_movie+i+1]-rate[j*max_movie+k])*(rate[j*max_movie+i+1]-rate[j*max_movie+k]);
//count++;
}
}
result[(i+1)*max_movie+k]=sqrt(sum);
}
}
}
}
int main()
{
cout<<"start:"<<endl;
FILE *fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.base","r");
float a[max_movie*max_user];
float* res;
res=(float*)malloc(sizeof(float)*max_movie*max_movie);
int movieid,userid,stamp,i,j;
float rating;
float* gpudata;
float* result;
float min;
int minindex1,minindex2,minindex3,k;
//cout<<"yes"<<endl;
//cout<<"4";
for(i=0;i<max_user;i++)
for(j=0;j<max_movie;j++)
a[i*max_movie+j]=-1;
//cout<<"3";
cudaMalloc((void**)&gpudata,sizeof(float)*max_movie*max_user);
cudaMalloc((void**)&result,sizeof(float)*max_movie*max_movie);
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
a[userid*max_movie+movieid]=rating;
}
fclose(fp);
cudaMemcpy(gpudata,a,sizeof(float)*max_movie*max_user,cudaMemcpyHostToDevice);
//cout<<"1";
test<<<BLOCK_NUM,THREAD_NUM,0>>>(gpudata,result);
cudaMemcpy(res,result,sizeof(float)*max_movie*max_movie,cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.test","r");
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if(i==(movieid*max_movie+movieid))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex1=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex2=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1))||(i==(movieid*max_movie+minindex2)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex3=k;
min=res[i];
}
}
}
cout<<"userid:"<<userid<<" ";
cout<<"movieid:"<<movieid<<" ";
cout<<"estimate:"<<(float)(a[userid*max_movie+minindex1]+a[userid*max_movie+minindex2]+a[userid*max_movie+minindex3])/3<<" ";
cout<<"real:"<<rating<<endl;
cout<<endl;
}
fclose(fp);
//cout<<res[1687];
} | .file "tmpxft_000785a0_00000000-6_mymain.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL4testPfS_, @function
_ZL4testPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL4testPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _ZL4testPfS_, .-_ZL4testPfS_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "start:"
.LC2:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/3160102482/myhelloworld/ml-100k/u2.base"
.section .rodata.str1.1
.LC5:
.string "%d%d%f%d"
.section .rodata.str1.8
.align 8
.LC6:
.string "/home/3160102482/myhelloworld/ml-100k/u2.test"
.section .rodata.str1.1
.LC7:
.string "userid:"
.LC8:
.string " "
.LC9:
.string "movieid:"
.LC10:
.string "estimate:"
.LC12:
.string "real:"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -6352896(%rsp), %r11
.cfi_def_cfa 11, 6352952
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2216, %rsp
.cfi_def_cfa_offset 6355168
movq %fs:40, %rax
movq %rax, 6355096(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r14
movl $11329956, %edi
call malloc@PLT
movq %rax, %rbx
leaq 6812(%rsp), %rdx
leaq 6361820(%rsp), %rcx
movss .LC4(%rip), %xmm0
.L10:
leaq -6732(%rdx), %rax
.L11:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L11
addq $6732, %rdx
cmpq %rcx, %rdx
jne .L10
leaq 40(%rsp), %rdi
movl $6355008, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $11329956, %esi
call cudaMalloc@PLT
leaq .LC5(%rip), %r15
jmp .L13
.L14:
leaq 24(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 32(%rsp), %r9
leaq 36(%rsp), %r8
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
imull $1683, 28(%rsp), %eax
addl 24(%rsp), %eax
cltq
movss 36(%rsp), %xmm0
movss %xmm0, 80(%rsp,%rax,4)
.L13:
movq %r14, %rdi
call feof@PLT
testl %eax, %eax
je .L14
movq %r14, %rdi
call fclose@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $6355008, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $32, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L15:
movl $2, %ecx
movl $11329956, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
leaq .LC2(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
jmp .L16
.L50:
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _ZL4testPfS_
jmp .L15
.L17:
addq $1, %rdx
cmpq %rdx, %rsi
je .L51
.L20:
cmpl %edx, %edi
je .L17
movl %edx, %r11d
leal (%r8,%rdx), %ecx
movslq %ecx, %rcx
movss .LC4(%rip), %xmm4
ucomiss 80(%rsp,%rcx,4), %xmm4
jp .L39
je .L17
.L39:
movss (%rbx,%rdx,4), %xmm0
comiss %xmm0, %xmm1
jbe .L17
leal (%r10,%r11), %ebp
movaps %xmm0, %xmm1
jmp .L17
.L51:
movq %rax, %rdx
movss .LC0(%rip), %xmm3
leal (%r9,%rbp), %r11d
movss .LC4(%rip), %xmm1
movaps %xmm1, %xmm2
jmp .L24
.L21:
addq $1, %rdx
cmpq %rdx, %rsi
je .L52
.L24:
cmpl %edx, %edi
je .L21
cmpl %edx, %r11d
je .L21
movl %edx, %r14d
leal (%r8,%rdx), %ecx
movslq %ecx, %rcx
ucomiss 80(%rsp,%rcx,4), %xmm1
jp .L41
ucomiss 80(%rsp,%rcx,4), %xmm2
je .L21
.L41:
movss (%rbx,%rdx,4), %xmm0
comiss %xmm0, %xmm3
jbe .L21
leal (%r10,%r14), %r12d
movaps %xmm0, %xmm3
jmp .L21
.L52:
movss .LC0(%rip), %xmm3
leal (%r9,%rbp), %ecx
addl %r12d, %r9d
movss .LC4(%rip), %xmm2
movaps %xmm2, %xmm1
jmp .L28
.L25:
addq $1, %rax
cmpq %rsi, %rax
je .L53
.L28:
cmpl %eax, %edi
je .L25
cmpl %eax, %ecx
je .L25
cmpl %eax, %r9d
je .L25
movl %eax, %r11d
leal (%r8,%rax), %edx
movslq %edx, %rdx
ucomiss 80(%rsp,%rdx,4), %xmm2
jp .L43
ucomiss 80(%rsp,%rdx,4), %xmm1
je .L25
.L43:
movss (%rbx,%rax,4), %xmm0
comiss %xmm0, %xmm3
jbe .L25
leal (%r10,%r11), %r13d
movaps %xmm0, %xmm3
jmp .L25
.L53:
movl $7, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 28(%rsp), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC8(%rip), %r15
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $8, %edx
leaq .LC9(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 24(%rsp), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $9, %edx
leaq .LC10(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
imull $1683, 28(%rsp), %eax
leal (%rax,%rbp), %ecx
movslq %ecx, %rcx
leal (%rax,%r12), %edx
movslq %edx, %rdx
movss 80(%rsp,%rcx,4), %xmm0
addss 80(%rsp,%rdx,4), %xmm0
addl %r13d, %eax
cltq
addss 80(%rsp,%rax,4), %xmm0
divss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $5, %edx
leaq .LC12(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .L54
cmpb $0, 56(%r14)
je .L31
movzbl 67(%r14), %eax
.L32:
movsbl %al, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %r14
testq %r14, %r14
je .L55
cmpb $0, 56(%r14)
je .L35
movzbl 67(%r14), %eax
.L36:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L16:
movq 8(%rsp), %rdi
call feof@PLT
testl %eax, %eax
jne .L56
leaq 24(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 32(%rsp), %r9
leaq 36(%rsp), %r8
leaq .LC5(%rip), %rsi
movq 8(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 24(%rsp), %edx
imull $1683, %edx, %r9d
imull $1684, %edx, %edi
leal 1(%r9), %eax
cltq
movslq %edx, %rsi
addq $1, %rsi
imulq $1683, %rsi, %rsi
imull $-1683, %edx, %r10d
movl 28(%rsp), %r8d
subl %edx, %r8d
imull $1683, %r8d, %r8d
movq %rax, %rdx
movss .LC0(%rip), %xmm1
jmp .L20
.L54:
movq 6355096(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L31:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L32
.L55:
movq 6355096(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L35:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L36
.L56:
movq 8(%rsp), %rdi
call fclose@PLT
movq 6355096(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $6355112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z4testPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4testPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1120403456
.align 4
.LC4:
.long -1082130432
.align 4
.LC11:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <iostream>
#include <math.h>
using namespace std;
const int max_movie = 1683;
const int max_user = 944;
#define THREAD_NUM 256
#define BLOCK_NUM 32
__global__ static void test(float* rate,float* result)
{
const int tid=threadIdx.x;
const int bid=blockIdx.x;
int i,k,j;
float sum;
for(i=bid*THREAD_NUM+tid;i<max_movie-1;i+=BLOCK_NUM*THREAD_NUM)
{
for(k=1;k<max_movie;k++)
{
if(k==i+1)
continue;
else
{
sum=0;
//count=0;
for(j=1;j<max_user;j++)
{
if((rate[j*max_movie+i+1]==-1)||(rate[j*max_movie+k]==-1))
continue;
else
{
sum=sum+(rate[j*max_movie+i+1]-rate[j*max_movie+k])*(rate[j*max_movie+i+1]-rate[j*max_movie+k]);
//count++;
}
}
result[(i+1)*max_movie+k]=sqrt(sum);
}
}
}
}
int main()
{
cout<<"start:"<<endl;
FILE *fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.base","r");
float a[max_movie*max_user];
float* res;
res=(float*)malloc(sizeof(float)*max_movie*max_movie);
int movieid,userid,stamp,i,j;
float rating;
float* gpudata;
float* result;
float min;
int minindex1,minindex2,minindex3,k;
//cout<<"yes"<<endl;
//cout<<"4";
for(i=0;i<max_user;i++)
for(j=0;j<max_movie;j++)
a[i*max_movie+j]=-1;
//cout<<"3";
cudaMalloc((void**)&gpudata,sizeof(float)*max_movie*max_user);
cudaMalloc((void**)&result,sizeof(float)*max_movie*max_movie);
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
a[userid*max_movie+movieid]=rating;
}
fclose(fp);
cudaMemcpy(gpudata,a,sizeof(float)*max_movie*max_user,cudaMemcpyHostToDevice);
//cout<<"1";
test<<<BLOCK_NUM,THREAD_NUM,0>>>(gpudata,result);
cudaMemcpy(res,result,sizeof(float)*max_movie*max_movie,cudaMemcpyDeviceToHost);
cudaFree(gpudata);
cudaFree(result);
fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.test","r");
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if(i==(movieid*max_movie+movieid))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex1=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex2=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1))||(i==(movieid*max_movie+minindex2)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex3=k;
min=res[i];
}
}
}
cout<<"userid:"<<userid<<" ";
cout<<"movieid:"<<movieid<<" ";
cout<<"estimate:"<<(float)(a[userid*max_movie+minindex1]+a[userid*max_movie+minindex2]+a[userid*max_movie+minindex3])/3<<" ";
cout<<"real:"<<rating<<endl;
cout<<endl;
}
fclose(fp);
//cout<<res[1687];
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <math.h>
using namespace std;
const int max_movie = 1683;
const int max_user = 944;
#define THREAD_NUM 256
#define BLOCK_NUM 32
__global__ static void test(float* rate,float* result)
{
const int tid=threadIdx.x;
const int bid=blockIdx.x;
int i,k,j;
float sum;
for(i=bid*THREAD_NUM+tid;i<max_movie-1;i+=BLOCK_NUM*THREAD_NUM)
{
for(k=1;k<max_movie;k++)
{
if(k==i+1)
continue;
else
{
sum=0;
//count=0;
for(j=1;j<max_user;j++)
{
if((rate[j*max_movie+i+1]==-1)||(rate[j*max_movie+k]==-1))
continue;
else
{
sum=sum+(rate[j*max_movie+i+1]-rate[j*max_movie+k])*(rate[j*max_movie+i+1]-rate[j*max_movie+k]);
//count++;
}
}
result[(i+1)*max_movie+k]=sqrt(sum);
}
}
}
}
int main()
{
cout<<"start:"<<endl;
FILE *fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.base","r");
float a[max_movie*max_user];
float* res;
res=(float*)malloc(sizeof(float)*max_movie*max_movie);
int movieid,userid,stamp,i,j;
float rating;
float* gpudata;
float* result;
float min;
int minindex1,minindex2,minindex3,k;
//cout<<"yes"<<endl;
//cout<<"4";
for(i=0;i<max_user;i++)
for(j=0;j<max_movie;j++)
a[i*max_movie+j]=-1;
//cout<<"3";
hipMalloc((void**)&gpudata,sizeof(float)*max_movie*max_user);
hipMalloc((void**)&result,sizeof(float)*max_movie*max_movie);
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
a[userid*max_movie+movieid]=rating;
}
fclose(fp);
hipMemcpy(gpudata,a,sizeof(float)*max_movie*max_user,hipMemcpyHostToDevice);
//cout<<"1";
test<<<BLOCK_NUM,THREAD_NUM,0>>>(gpudata,result);
hipMemcpy(res,result,sizeof(float)*max_movie*max_movie,hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.test","r");
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if(i==(movieid*max_movie+movieid))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex1=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex2=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1))||(i==(movieid*max_movie+minindex2)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex3=k;
min=res[i];
}
}
}
cout<<"userid:"<<userid<<" ";
cout<<"movieid:"<<movieid<<" ";
cout<<"estimate:"<<(float)(a[userid*max_movie+minindex1]+a[userid*max_movie+minindex2]+a[userid*max_movie+minindex3])/3<<" ";
cout<<"real:"<<rating<<endl;
cout<<endl;
}
fclose(fp);
//cout<<res[1687];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <math.h>
using namespace std;
const int max_movie = 1683;
const int max_user = 944;
#define THREAD_NUM 256
#define BLOCK_NUM 32
__global__ static void test(float* rate,float* result)
{
const int tid=threadIdx.x;
const int bid=blockIdx.x;
int i,k,j;
float sum;
for(i=bid*THREAD_NUM+tid;i<max_movie-1;i+=BLOCK_NUM*THREAD_NUM)
{
for(k=1;k<max_movie;k++)
{
if(k==i+1)
continue;
else
{
sum=0;
//count=0;
for(j=1;j<max_user;j++)
{
if((rate[j*max_movie+i+1]==-1)||(rate[j*max_movie+k]==-1))
continue;
else
{
sum=sum+(rate[j*max_movie+i+1]-rate[j*max_movie+k])*(rate[j*max_movie+i+1]-rate[j*max_movie+k]);
//count++;
}
}
result[(i+1)*max_movie+k]=sqrt(sum);
}
}
}
}
int main()
{
cout<<"start:"<<endl;
FILE *fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.base","r");
float a[max_movie*max_user];
float* res;
res=(float*)malloc(sizeof(float)*max_movie*max_movie);
int movieid,userid,stamp,i,j;
float rating;
float* gpudata;
float* result;
float min;
int minindex1,minindex2,minindex3,k;
//cout<<"yes"<<endl;
//cout<<"4";
for(i=0;i<max_user;i++)
for(j=0;j<max_movie;j++)
a[i*max_movie+j]=-1;
//cout<<"3";
hipMalloc((void**)&gpudata,sizeof(float)*max_movie*max_user);
hipMalloc((void**)&result,sizeof(float)*max_movie*max_movie);
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
a[userid*max_movie+movieid]=rating;
}
fclose(fp);
hipMemcpy(gpudata,a,sizeof(float)*max_movie*max_user,hipMemcpyHostToDevice);
//cout<<"1";
test<<<BLOCK_NUM,THREAD_NUM,0>>>(gpudata,result);
hipMemcpy(res,result,sizeof(float)*max_movie*max_movie,hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.test","r");
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if(i==(movieid*max_movie+movieid))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex1=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex2=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1))||(i==(movieid*max_movie+minindex2)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex3=k;
min=res[i];
}
}
}
cout<<"userid:"<<userid<<" ";
cout<<"movieid:"<<movieid<<" ";
cout<<"estimate:"<<(float)(a[userid*max_movie+minindex1]+a[userid*max_movie+minindex2]+a[userid*max_movie+minindex3])/3<<" ";
cout<<"real:"<<rating<<endl;
cout<<endl;
}
fclose(fp);
//cout<<res[1687];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL4testPfS_,"axG",@progbits,_ZL4testPfS_,comdat
.globl _ZL4testPfS_
.p2align 8
.type _ZL4testPfS_,@function
_ZL4testPfS_:
s_lshl_b32 s4, s15, 8
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x692, v2
s_cbranch_execz .LBB0_12
s_load_b128 s[0:3], s[0:1], 0x0
v_add3_u32 v0, v0, s4, 0x693
v_mov_b32_e32 v3, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, 0x1a50
s_addc_u32 s5, s1, 0
s_add_u32 s8, s0, 4
s_addc_u32 s9, s1, 0
s_branch .LBB0_3
.LBB0_2:
v_add_nc_u32_e32 v1, 0x2000, v2
v_cmp_lt_i32_e32 vcc_lo, 0xffffe691, v2
v_add_nc_u32_e32 v0, 0x2000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v2, v1
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_12
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, 1, v2
s_mov_b64 s[6:7], s[4:5]
s_mov_b32 s11, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_mul_lo_u32 v1, v4, 0x693
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_branch .LBB0_6
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_mul_f32_e32 v8, 0x4f800000, v7
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v7, v8, vcc_lo
v_sqrt_f32_e32 v7, v9
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v10, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v8, v7, v9
v_fma_f32 v12, -v10, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v11
v_cndmask_b32_e64 v7, v7, v8, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v12
v_cndmask_b32_e64 v10, v7, v10, s0
v_add_nc_u32_e32 v7, s11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, 0x37800000, v10
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_cmp_class_f32_e64 vcc_lo, v9, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v10, v9, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_store_b32 v[7:8], v9, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s11, s11, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmpk_lg_i32 s11, 0x693
s_cbranch_scc0 .LBB0_2
.LBB0_6:
s_mov_b32 s12, exec_lo
v_cmpx_ne_u32_e64 s11, v4
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v7, 0
s_mov_b64 s[0:1], 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s13
s_add_u32 s0, s0, 0x1a4c
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 0x60ddf4
s_cbranch_scc0 .LBB0_4
.LBB0_9:
v_add_co_u32 v8, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s13, exec_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 -1.0, v8
s_cbranch_execz .LBB0_8
s_add_u32 s14, s6, s0
s_addc_u32 s15, s7, s1
global_load_b32 v9, v3, s[14:15]
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, -1.0, v9
s_cbranch_vccnz .LBB0_8
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v8
s_branch .LBB0_8
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL4testPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL4testPfS_,"axG",@progbits,_ZL4testPfS_,comdat
.Lfunc_end0:
.size _ZL4testPfS_, .Lfunc_end0-_ZL4testPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL4testPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL4testPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <math.h>
using namespace std;
const int max_movie = 1683;
const int max_user = 944;
#define THREAD_NUM 256
#define BLOCK_NUM 32
__global__ static void test(float* rate,float* result)
{
const int tid=threadIdx.x;
const int bid=blockIdx.x;
int i,k,j;
float sum;
for(i=bid*THREAD_NUM+tid;i<max_movie-1;i+=BLOCK_NUM*THREAD_NUM)
{
for(k=1;k<max_movie;k++)
{
if(k==i+1)
continue;
else
{
sum=0;
//count=0;
for(j=1;j<max_user;j++)
{
if((rate[j*max_movie+i+1]==-1)||(rate[j*max_movie+k]==-1))
continue;
else
{
sum=sum+(rate[j*max_movie+i+1]-rate[j*max_movie+k])*(rate[j*max_movie+i+1]-rate[j*max_movie+k]);
//count++;
}
}
result[(i+1)*max_movie+k]=sqrt(sum);
}
}
}
}
int main()
{
cout<<"start:"<<endl;
FILE *fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.base","r");
float a[max_movie*max_user];
float* res;
res=(float*)malloc(sizeof(float)*max_movie*max_movie);
int movieid,userid,stamp,i,j;
float rating;
float* gpudata;
float* result;
float min;
int minindex1,minindex2,minindex3,k;
//cout<<"yes"<<endl;
//cout<<"4";
for(i=0;i<max_user;i++)
for(j=0;j<max_movie;j++)
a[i*max_movie+j]=-1;
//cout<<"3";
hipMalloc((void**)&gpudata,sizeof(float)*max_movie*max_user);
hipMalloc((void**)&result,sizeof(float)*max_movie*max_movie);
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
a[userid*max_movie+movieid]=rating;
}
fclose(fp);
hipMemcpy(gpudata,a,sizeof(float)*max_movie*max_user,hipMemcpyHostToDevice);
//cout<<"1";
test<<<BLOCK_NUM,THREAD_NUM,0>>>(gpudata,result);
hipMemcpy(res,result,sizeof(float)*max_movie*max_movie,hipMemcpyDeviceToHost);
hipFree(gpudata);
hipFree(result);
fp = fopen("/home/3160102482/myhelloworld/ml-100k/u2.test","r");
while(!feof(fp)){
fscanf(fp,"%d%d%f%d",&userid, &movieid, &rating, &stamp);
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if(i==(movieid*max_movie+movieid))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex1=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex2=k;
min=res[i];
}
}
}
min=100;
for(i=movieid*max_movie+1;i<(movieid+1)*max_movie;i++)
{
if((i==(movieid*max_movie+movieid))||(i==(movieid*max_movie+minindex1))||(i==(movieid*max_movie+minindex2)))
continue;
else
{
k=i-movieid*max_movie;
if((a[userid*max_movie+k]!=-1)&&(res[i]<min))
{
minindex3=k;
min=res[i];
}
}
}
cout<<"userid:"<<userid<<" ";
cout<<"movieid:"<<movieid<<" ";
cout<<"estimate:"<<(float)(a[userid*max_movie+minindex1]+a[userid*max_movie+minindex2]+a[userid*max_movie+minindex3])/3<<" ";
cout<<"real:"<<rating<<endl;
cout<<endl;
}
fclose(fp);
//cout<<res[1687];
} | .text
.file "mymain.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x42c80000 # float 100
.LCPI0_1:
.long 0xbf800000 # float -1
.LCPI0_2:
.long 0x40400000 # float 3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $6355144, %rsp # imm = 0x60F8C8
.cfi_def_cfa_offset 6355200
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_50
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
movl $11329956, %edi # imm = 0xACE1A4
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
leaq 128(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_5: # %.preheader95
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $-1082130432, (%rax,%rdx,4) # imm = 0xBF800000
incq %rdx
cmpq $1683, %rdx # imm = 0x693
jne .LBB0_6
# %bb.7: # in Loop: Header=BB0_5 Depth=1
incq %rcx
addq $6732, %rax # imm = 0x1A4C
cmpq $944, %rcx # imm = 0x3B0
jne .LBB0_5
# %bb.8:
leaq 32(%rsp), %rdi
movl $6355008, %esi # imm = 0x60F840
callq hipMalloc
leaq 24(%rsp), %rdi
movl $11329956, %esi # imm = 0xACE1A4
callq hipMalloc
movq %r14, %rdi
callq feof
testl %eax, %eax
jne .LBB0_11
# %bb.9: # %.lr.ph.preheader
leaq 4(%rsp), %r15
leaq 8(%rsp), %r12
leaq 12(%rsp), %r13
leaq 44(%rsp), %rbp
.p2align 4, 0x90
.LBB0_10: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %r15, %rdx
movq %r12, %rcx
movq %r13, %r8
movq %rbp, %r9
xorl %eax, %eax
callq __isoc23_fscanf
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq 4(%rsp), %rax
imulq $1683, %rax, %rax # imm = 0x693
movslq 8(%rsp), %rcx
addq %rax, %rcx
movss %xmm0, 128(%rsp,%rcx,4)
movq %r14, %rdi
callq feof
testl %eax, %eax
je .LBB0_10
.LBB0_11: # %._crit_edge
movq %r14, %rdi
callq fclose
movq 32(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $6355008, %edx # imm = 0x60F840
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_ZL4testPfS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_13:
movq 24(%rsp), %rsi
movl $11329956, %edx # imm = 0xACE1A4
movq 16(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.L.str.4, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
movq %rax, %rdi
callq feof
testl %eax, %eax
je .LBB0_14
.LBB0_49: # %._crit_edge125
movq %r14, %rdi
callq fclose
xorl %eax, %eax
addq $6355144, %rsp # imm = 0x60F8C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_14: # %.lr.ph124.preheader
.cfi_def_cfa_offset 6355200
addq $4, 16(%rsp) # 8-byte Folded Spill
# implicit-def: $ebp
# implicit-def: $ebx
# implicit-def: $r13d
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_47: # in Loop: Header=BB0_15 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit90
# in Loop: Header=BB0_15 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r14, %rdi
callq feof
testl %eax, %eax
jne .LBB0_49
.LBB0_15: # %.lr.ph124
# =>This Loop Header: Depth=1
# Child Loop BB0_38 Depth 2
# Child Loop BB0_19 Depth 2
# Child Loop BB0_27 Depth 2
movl $.L.str.3, %esi
movq %r14, %rdi
leaq 4(%rsp), %rdx
leaq 8(%rsp), %rcx
leaq 12(%rsp), %r8
leaq 44(%rsp), %r9
xorl %eax, %eax
callq __isoc23_fscanf
movslq 8(%rsp), %rcx
imull $1683, %ecx, %eax # imm = 0x693
leal 1683(%rax), %edx
leal 1(%rax), %esi
cmpl %edx, %esi
jge .LBB0_16
# %bb.37: # %.lr.ph104
# in Loop: Header=BB0_15 Depth=1
imull $1683, 4(%rsp), %edi # imm = 0x693
imulq $1684, %rcx, %r10 # imm = 0x694
movslq %eax, %r8
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r9
notq %r8
addq %r10, %r8
incl %edi
xorl %r10d, %r10d
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
jmp .LBB0_38
.p2align 4, 0x90
.LBB0_42: # in Loop: Header=BB0_38 Depth=2
incq %r10
cmpl $1682, %r10d # imm = 0x692
je .LBB0_17
.LBB0_38: # Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r10, %r8
je .LBB0_42
# %bb.39: # in Loop: Header=BB0_38 Depth=2
leal (%rdi,%r10), %r11d
movslq %r11d, %r11
movss 128(%rsp,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB0_40
jnp .LBB0_42
.LBB0_40: # in Loop: Header=BB0_38 Depth=2
movss (%r9,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB0_42
# %bb.41: # in Loop: Header=BB0_38 Depth=2
leaq 1(%r10), %r13
movaps %xmm1, %xmm0
jmp .LBB0_42
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_15 Depth=1
movss .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.LBB0_17: # %.preheader94
# in Loop: Header=BB0_15 Depth=1
cmpl %edx, %esi
jge .LBB0_25
# %bb.18: # %.lr.ph110
# in Loop: Header=BB0_15 Depth=1
imulq $1684, %rcx, %rdi # imm = 0x694
leal (%rax,%r13), %r9d
imull $1683, 4(%rsp), %r10d # imm = 0x693
movslq %eax, %r8
movslq %r10d, %r10
movslq %r9d, %r11
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r9
notq %r8
addq %r8, %rdi
addq %r11, %r8
leaq 132(%rsp), %r11
leaq (%r11,%r10,4), %r10
xorl %r11d, %r11d
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB0_19
.p2align 4, 0x90
.LBB0_24: # in Loop: Header=BB0_19 Depth=2
incq %r11
cmpl $1682, %r11d # imm = 0x692
je .LBB0_25
.LBB0_19: # Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r11, %rdi
je .LBB0_24
# %bb.20: # in Loop: Header=BB0_19 Depth=2
cmpq %r11, %r8
je .LBB0_24
# %bb.21: # in Loop: Header=BB0_19 Depth=2
movss (%r10,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB0_22
jnp .LBB0_24
.LBB0_22: # in Loop: Header=BB0_19 Depth=2
movss (%r9,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB0_24
# %bb.23: # in Loop: Header=BB0_19 Depth=2
leal 1(%r11), %ebx
movaps %xmm1, %xmm0
jmp .LBB0_24
.p2align 4, 0x90
.LBB0_25: # %.preheader
# in Loop: Header=BB0_15 Depth=1
cmpl %edx, %esi
jge .LBB0_34
# %bb.26: # %.lr.ph116
# in Loop: Header=BB0_15 Depth=1
imull $1684, %ecx, %edx # imm = 0x694
leal (%rax,%r13), %ecx
leal (%rbx,%rax), %esi
imull $1683, 4(%rsp), %edi # imm = 0x693
cltq
movslq %edi, %rdi
movslq %esi, %r8
movslq %ecx, %rcx
movslq %edx, %rdx
movq 16(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %rsi
notq %rax
addq %rax, %rdx
addq %rax, %rcx
addq %r8, %rax
leaq 132(%rsp), %r8
leaq (%r8,%rdi,4), %rdi
xorl %r8d, %r8d
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB0_27
.p2align 4, 0x90
.LBB0_33: # in Loop: Header=BB0_27 Depth=2
incq %r8
cmpl $1682, %r8d # imm = 0x692
je .LBB0_34
.LBB0_27: # Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r8, %rdx
je .LBB0_33
# %bb.28: # in Loop: Header=BB0_27 Depth=2
cmpq %r8, %rcx
je .LBB0_33
# %bb.29: # in Loop: Header=BB0_27 Depth=2
cmpq %r8, %rax
je .LBB0_33
# %bb.30: # in Loop: Header=BB0_27 Depth=2
movss (%rdi,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB0_31
jnp .LBB0_33
.LBB0_31: # in Loop: Header=BB0_27 Depth=2
movss (%rsi,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB0_33
# %bb.32: # in Loop: Header=BB0_27 Depth=2
leal 1(%r8), %ebp
movaps %xmm1, %xmm0
jmp .LBB0_33
.p2align 4, 0x90
.LBB0_34: # %._crit_edge117
# in Loop: Header=BB0_15 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 4(%rsp), %rax
imulq $1683, %rax, %rax # imm = 0x693
movslq %r13d, %rcx
addq %rax, %rcx
movss 128(%rsp,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leal (%rax,%rbx), %ecx
movslq %ecx, %rcx
addss 128(%rsp,%rcx,4), %xmm0
addl %ebp, %eax
cltq
addss 128(%rsp,%rax,4), %xmm0
divss .LCPI0_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_50
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i82
# in Loop: Header=BB0_15 Depth=1
cmpb $0, 56(%r12)
je .LBB0_43
# %bb.36: # in Loop: Header=BB0_15 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_44
.p2align 4, 0x90
.LBB0_43: # in Loop: Header=BB0_15 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit85
# in Loop: Header=BB0_15 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_50
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i87
# in Loop: Header=BB0_15 Depth=1
cmpb $0, 56(%r15)
je .LBB0_47
# %bb.46: # in Loop: Header=BB0_15 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_48
.LBB0_50:
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL19__device_stub__testPfS_
.type _ZL19__device_stub__testPfS_,@function
_ZL19__device_stub__testPfS_: # @_ZL19__device_stub__testPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL4testPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _ZL19__device_stub__testPfS_, .Lfunc_end1-_ZL19__device_stub__testPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL4testPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "start:"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/3160102482/myhelloworld/ml-100k/u2.base"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d%d%f%d"
.size .L.str.3, 9
.type _ZL4testPfS_,@object # @_ZL4testPfS_
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL4testPfS_:
.quad _ZL19__device_stub__testPfS_
.size _ZL4testPfS_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "/home/3160102482/myhelloworld/ml-100k/u2.test"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "userid:"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "movieid:"
.size .L.str.7, 9
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "estimate:"
.size .L.str.8, 10
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "real:"
.size .L.str.9, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL4testPfS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL19__device_stub__testPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZL4testPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4testPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, 0x100, R0 ; /* 0x0000010003007824 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x691, PT ; /* 0x000006910000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R3, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff037435 */
/* 0x000fe200000001ff */
/*0080*/ IADD3 R2, R0, 0x694, RZ ; /* 0x0000069400027810 */
/* 0x001fca0007ffe0ff */
/*0090*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x001fe20007ffe0ff */
/*00a0*/ BSSY B0, 0x510 ; /* 0x0000046000007945 */
/* 0x000fe60003800000 */
/*00b0*/ ISETP.NE.AND P0, PT, R3, R4, PT ; /* 0x000000040300720c */
/* 0x000fda0003f05270 */
/*00c0*/ @!P0 BRA 0x500 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R13, R3, 0x693, RZ ; /* 0x00000693030d7810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e00ff */
/*00f0*/ MOV R16, RZ ; /* 0x000000ff00107202 */
/* 0x000fe20000000f00 */
/*0100*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe200078e00ff */
/*0110*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fca0000000f00 */
/*0120*/ IMAD.WIDE R6, R2, 0x4, R4 ; /* 0x0000000402067825 */
/* 0x000fca00078e0204 */
/*0130*/ LDG.E R11, [R6.64] ; /* 0x00000004060b7981 */
/* 0x000ea8000c1e1900 */
/*0140*/ LDG.E R14, [R6.64+0x1a4c] ; /* 0x001a4c04060e7981 */
/* 0x000ee8000c1e1900 */
/*0150*/ LDG.E R15, [R6.64+0x3498] ; /* 0x00349804060f7981 */
/* 0x000f22000c1e1900 */
/*0160*/ BSSY B1, 0x220 ; /* 0x000000b000017945 */
/* 0x000fe20003800000 */
/*0170*/ ISETP.NE.AND P0, PT, R16, 0x3ac, PT ; /* 0x000003ac1000780c */
/* 0x000fe20003f05270 */
/*0180*/ IMAD.WIDE R8, R13, 0x4, R4 ; /* 0x000000040d087825 */
/* 0x000fe200078e0204 */
/*0190*/ FSETP.NEU.AND P3, PT, R11, -1, PT ; /* 0xbf8000000b00780b */
/* 0x004fc40003f6d000 */
/*01a0*/ FSETP.NEU.AND P1, PT, R14, -1, PT ; /* 0xbf8000000e00780b */
/* 0x008fe40003f2d000 */
/*01b0*/ FSETP.NEU.AND P2, PT, R15, -1, PT ; /* 0xbf8000000f00780b */
/* 0x010fd20003f4d000 */
/*01c0*/ @!P3 BRA 0x210 ; /* 0x000000400000b947 */
/* 0x000fea0003800000 */
/*01d0*/ LDG.E R12, [R8.64] ; /* 0x00000004080c7981 */
/* 0x000ea4000c1e1900 */
/*01e0*/ FSETP.NEU.AND P3, PT, R12, -1, PT ; /* 0xbf8000000c00780b */
/* 0x004fda0003f6d000 */
/*01f0*/ @P3 FADD R11, R11, -R12 ; /* 0x8000000c0b0b3221 */
/* 0x000fc80000000000 */
/*0200*/ @P3 FFMA R10, R11, R11, R10 ; /* 0x0000000b0b0a3223 */
/* 0x000fe4000000000a */
/*0210*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0220*/ BSSY B1, 0x290 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*0230*/ @!P1 BRA 0x280 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E R11, [R8.64+0x1a4c] ; /* 0x001a4c04080b7981 */
/* 0x000ea4000c1e1900 */
/*0250*/ FSETP.NEU.AND P1, PT, R11, -1, PT ; /* 0xbf8000000b00780b */
/* 0x004fda0003f2d000 */
/*0260*/ @P1 FADD R11, R14, -R11 ; /* 0x8000000b0e0b1221 */
/* 0x000fc80000000000 */
/*0270*/ @P1 FFMA R10, R11, R11, R10 ; /* 0x0000000b0b0a1223 */
/* 0x000fe4000000000a */
/*0280*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0290*/ BSSY B1, 0x300 ; /* 0x0000006000017945 */
/* 0x000fe20003800000 */
/*02a0*/ @!P2 BRA 0x2f0 ; /* 0x000000400000a947 */
/* 0x000fea0003800000 */
/*02b0*/ LDG.E R12, [R8.64+0x3498] ; /* 0x00349804080c7981 */
/* 0x000ea4000c1e1900 */
/*02c0*/ FSETP.NEU.AND P1, PT, R12, -1, PT ; /* 0xbf8000000c00780b */
/* 0x004fda0003f2d000 */
/*02d0*/ @P1 FADD R11, R15, -R12 ; /* 0x8000000c0f0b1221 */
/* 0x000fc80000000000 */
/*02e0*/ @P1 FFMA R10, R11, R11, R10 ; /* 0x0000000b0b0a1223 */
/* 0x000fe4000000000a */
/*02f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0300*/ @!P0 BRA 0x3e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0310*/ LDG.E R7, [R6.64+0x4ee4] ; /* 0x004ee40406077981 */
/* 0x000ea2000c1e1900 */
/*0320*/ BSSY B1, 0x3a0 ; /* 0x0000007000017945 */
/* 0x000fe20003800000 */
/*0330*/ FSETP.NEU.AND P0, PT, R7, -1, PT ; /* 0xbf8000000700780b */
/* 0x004fda0003f0d000 */
/*0340*/ @!P0 BRA 0x390 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0350*/ LDG.E R8, [R8.64+0x4ee4] ; /* 0x004ee40408087981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FSETP.NEU.AND P0, PT, R8, -1, PT ; /* 0xbf8000000800780b */
/* 0x004fda0003f0d000 */
/*0370*/ @P0 FADD R7, R7, -R8 ; /* 0x8000000807070221 */
/* 0x000fc80000000000 */
/*0380*/ @P0 FFMA R10, R7, R7, R10 ; /* 0x00000007070a0223 */
/* 0x000fe4000000000a */
/*0390*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03a0*/ IADD3 R4, P0, R4, 0x6930, RZ ; /* 0x0000693004047810 */
/* 0x000fe40007f1e0ff */
/*03b0*/ IADD3 R16, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fc60007ffe0ff */
/*03c0*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe200000e0605 */
/*03d0*/ BRA 0x120 ; /* 0xfffffd4000007947 */
/* 0x000fea000383ffff */
/*03e0*/ IADD3 R4, R10, -0xd000000, RZ ; /* 0xf30000000a047810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ MUFU.RSQ R5, R10 ; /* 0x0000000a00057308 */
/* 0x0000620000001400 */
/*0400*/ BSSY B1, 0x4b0 ; /* 0x000000a000017945 */
/* 0x000fe40003800000 */
/*0410*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0420*/ @!P0 BRA 0x460 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0430*/ MOV R9, 0x450 ; /* 0x0000045000097802 */
/* 0x003fe40000000f00 */
/*0440*/ CALL.REL.NOINC 0x580 ; /* 0x0000013000007944 */
/* 0x000fea0003c00000 */
/*0450*/ BRA 0x4a0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0460*/ FMUL.FTZ R7, R10, R5 ; /* 0x000000050a077220 */
/* 0x003fe40000410000 */
/*0470*/ FMUL.FTZ R4, R5, 0.5 ; /* 0x3f00000005047820 */
/* 0x000fe40000410000 */
/*0480*/ FFMA R10, -R7, R7, R10 ; /* 0x00000007070a7223 */
/* 0x000fc8000000010a */
/*0490*/ FFMA R7, R10, R4, R7 ; /* 0x000000040a077223 */
/* 0x000fe40000000007 */
/*04a0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04b0*/ IMAD R4, R0, 0x693, R3 ; /* 0x0000069300047824 */
/* 0x000fe200078e0203 */
/*04c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc800000001ff */
/*04d0*/ IADD3 R4, R4, 0x693, RZ ; /* 0x0000069304047810 */
/* 0x000fcc0007ffe0ff */
/*04e0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*04f0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*0500*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0510*/ IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103037810 */
/* 0x000fc80007ffe0ff */
/*0520*/ ISETP.GE.U32.AND P0, PT, R3, 0x693, PT ; /* 0x000006930300780c */
/* 0x000fda0003f06070 */
/*0530*/ @!P0 BRA 0x90 ; /* 0xfffffb5000008947 */
/* 0x000fea000383ffff */
/*0540*/ ISETP.GE.AND P0, PT, R0.reuse, -0x196e, PT ; /* 0xffffe6920000780c */
/* 0x040fe40003f06270 */
/*0550*/ IADD3 R0, R0, 0x2000, RZ ; /* 0x0000200000007810 */
/* 0x000fd60007ffe0ff */
/*0560*/ @!P0 BRA 0x70 ; /* 0xfffffb0000008947 */
/* 0x000fea000383ffff */
/*0570*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0580*/ LOP3.LUT P0, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000780c0ff */
/*0590*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff048224 */
/* 0x000fe200078e000a */
/*05a0*/ @!P0 BRA 0x6b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*05b0*/ FSETP.GEU.FTZ.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f1e000 */
/*05c0*/ @!P0 MOV R4, 0x7fffffff ; /* 0x7fffffff00048802 */
/* 0x000fe20000000f00 */
/*05d0*/ @!P0 BRA 0x6b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*05e0*/ FSETP.GTU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1c200 */
/*05f0*/ @P0 FADD.FTZ R4, R10, 1 ; /* 0x3f8000000a040421 */
/* 0x000fe20000010000 */
/*0600*/ @P0 BRA 0x6b0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0610*/ FSETP.NEU.FTZ.AND P0, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f1d200 */
/*0620*/ @P0 FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a050823 */
/* 0x000fc800000000ff */
/*0630*/ @P0 MUFU.RSQ R4, R5 ; /* 0x0000000500040308 */
/* 0x000e240000001400 */
/*0640*/ @P0 FMUL.FTZ R6, R5, R4 ; /* 0x0000000405060220 */
/* 0x001fe40000410000 */
/*0650*/ @P0 FMUL.FTZ R8, R4, 0.5 ; /* 0x3f00000004080820 */
/* 0x000fe40000410000 */
/*0660*/ @P0 FADD.FTZ R7, -R6.reuse, -RZ ; /* 0x800000ff06070221 */
/* 0x040fe40000010100 */
/*0670*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff048224 */
/* 0x000fe400078e000a */
/*0680*/ @P0 FFMA R7, R6, R7, R5 ; /* 0x0000000706070223 */
/* 0x000fc80000000005 */
/*0690*/ @P0 FFMA R7, R7, R8, R6 ; /* 0x0000000807070223 */
/* 0x000fc80000000006 */
/*06a0*/ @P0 FMUL.FTZ R4, R7, 2.3283064365386962891e-10 ; /* 0x2f80000007040820 */
/* 0x000fc80000410000 */
/*06b0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*06c0*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fe20000000f00 */
/*06d0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0009 */
/*06e0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff91004007950 */
/* 0x000fea0003c3ffff */
/*06f0*/ BRA 0x6f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL4testPfS_,"axG",@progbits,_ZL4testPfS_,comdat
.globl _ZL4testPfS_
.p2align 8
.type _ZL4testPfS_,@function
_ZL4testPfS_:
s_lshl_b32 s4, s15, 8
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v2, s4, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x692, v2
s_cbranch_execz .LBB0_12
s_load_b128 s[0:3], s[0:1], 0x0
v_add3_u32 v0, v0, s4, 0x693
v_mov_b32_e32 v3, 0
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s0, 0x1a50
s_addc_u32 s5, s1, 0
s_add_u32 s8, s0, 4
s_addc_u32 s9, s1, 0
s_branch .LBB0_3
.LBB0_2:
v_add_nc_u32_e32 v1, 0x2000, v2
v_cmp_lt_i32_e32 vcc_lo, 0xffffe691, v2
v_add_nc_u32_e32 v0, 0x2000, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v2, v1
s_or_b32 s10, vcc_lo, s10
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_12
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
v_add_nc_u32_e32 v4, 1, v2
s_mov_b64 s[6:7], s[4:5]
s_mov_b32 s11, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[0:1]
v_mul_lo_u32 v1, v4, 0x693
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
s_branch .LBB0_6
.LBB0_4:
s_set_inst_prefetch_distance 0x2
v_mul_f32_e32 v8, 0x4f800000, v7
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v9, v7, v8, vcc_lo
v_sqrt_f32_e32 v7, v9
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v8, -1, v7
v_add_nc_u32_e32 v10, 1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v8, v7, v9
v_fma_f32 v12, -v10, v7, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v11
v_cndmask_b32_e64 v7, v7, v8, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v12
v_cndmask_b32_e64 v10, v7, v10, s0
v_add_nc_u32_e32 v7, s11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v11, 0x37800000, v10
v_ashrrev_i32_e32 v8, 31, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v10, v11, vcc_lo
v_lshlrev_b64 v[7:8], 2, v[7:8]
v_cmp_class_f32_e64 vcc_lo, v9, 0x260
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v10, v9, vcc_lo
v_add_co_u32 v7, vcc_lo, s2, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_store_b32 v[7:8], v9, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s12
s_add_i32 s11, s11, 1
s_add_u32 s6, s6, 4
s_addc_u32 s7, s7, 0
s_cmpk_lg_i32 s11, 0x693
s_cbranch_scc0 .LBB0_2
.LBB0_6:
s_mov_b32 s12, exec_lo
v_cmpx_ne_u32_e64 s11, v4
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v7, 0
s_mov_b64 s[0:1], 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_9
.p2align 6
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s13
s_add_u32 s0, s0, 0x1a4c
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 0x60ddf4
s_cbranch_scc0 .LBB0_4
.LBB0_9:
v_add_co_u32 v8, vcc_lo, v5, s0
v_add_co_ci_u32_e32 v9, vcc_lo, s1, v6, vcc_lo
s_mov_b32 s13, exec_lo
global_load_b32 v8, v[8:9], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f32_e32 -1.0, v8
s_cbranch_execz .LBB0_8
s_add_u32 s14, s6, s0
s_addc_u32 s15, s7, s1
global_load_b32 v9, v3, s[14:15]
s_waitcnt vmcnt(0)
v_cmp_eq_f32_e32 vcc_lo, -1.0, v9
s_cbranch_vccnz .LBB0_8
v_sub_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v8
s_branch .LBB0_8
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL4testPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL4testPfS_,"axG",@progbits,_ZL4testPfS_,comdat
.Lfunc_end0:
.size _ZL4testPfS_, .Lfunc_end0-_ZL4testPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL4testPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL4testPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000785a0_00000000-6_mymain.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL4testPfS_, @function
_ZL4testPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL4testPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _ZL4testPfS_, .-_ZL4testPfS_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "start:"
.LC2:
.string "r"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "/home/3160102482/myhelloworld/ml-100k/u2.base"
.section .rodata.str1.1
.LC5:
.string "%d%d%f%d"
.section .rodata.str1.8
.align 8
.LC6:
.string "/home/3160102482/myhelloworld/ml-100k/u2.test"
.section .rodata.str1.1
.LC7:
.string "userid:"
.LC8:
.string " "
.LC9:
.string "movieid:"
.LC10:
.string "estimate:"
.LC12:
.string "real:"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
leaq -6352896(%rsp), %r11
.cfi_def_cfa 11, 6352952
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2216, %rsp
.cfi_def_cfa_offset 6355168
movq %fs:40, %rax
movq %rax, 6355096(%rsp)
xorl %eax, %eax
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r14
movl $11329956, %edi
call malloc@PLT
movq %rax, %rbx
leaq 6812(%rsp), %rdx
leaq 6361820(%rsp), %rcx
movss .LC4(%rip), %xmm0
.L10:
leaq -6732(%rdx), %rax
.L11:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L11
addq $6732, %rdx
cmpq %rcx, %rdx
jne .L10
leaq 40(%rsp), %rdi
movl $6355008, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $11329956, %esi
call cudaMalloc@PLT
leaq .LC5(%rip), %r15
jmp .L13
.L14:
leaq 24(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 32(%rsp), %r9
leaq 36(%rsp), %r8
movq %r15, %rsi
movq %r14, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
imull $1683, 28(%rsp), %eax
addl 24(%rsp), %eax
cltq
movss 36(%rsp), %xmm0
movss %xmm0, 80(%rsp,%rax,4)
.L13:
movq %r14, %rdi
call feof@PLT
testl %eax, %eax
je .L14
movq %r14, %rdi
call fclose@PLT
leaq 80(%rsp), %rsi
movl $1, %ecx
movl $6355008, %edx
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $32, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L15:
movl $2, %ecx
movl $11329956, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
leaq .LC2(%rip), %rsi
leaq .LC6(%rip), %rdi
call fopen@PLT
movq %rax, 8(%rsp)
jmp .L16
.L50:
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _ZL4testPfS_
jmp .L15
.L17:
addq $1, %rdx
cmpq %rdx, %rsi
je .L51
.L20:
cmpl %edx, %edi
je .L17
movl %edx, %r11d
leal (%r8,%rdx), %ecx
movslq %ecx, %rcx
movss .LC4(%rip), %xmm4
ucomiss 80(%rsp,%rcx,4), %xmm4
jp .L39
je .L17
.L39:
movss (%rbx,%rdx,4), %xmm0
comiss %xmm0, %xmm1
jbe .L17
leal (%r10,%r11), %ebp
movaps %xmm0, %xmm1
jmp .L17
.L51:
movq %rax, %rdx
movss .LC0(%rip), %xmm3
leal (%r9,%rbp), %r11d
movss .LC4(%rip), %xmm1
movaps %xmm1, %xmm2
jmp .L24
.L21:
addq $1, %rdx
cmpq %rdx, %rsi
je .L52
.L24:
cmpl %edx, %edi
je .L21
cmpl %edx, %r11d
je .L21
movl %edx, %r14d
leal (%r8,%rdx), %ecx
movslq %ecx, %rcx
ucomiss 80(%rsp,%rcx,4), %xmm1
jp .L41
ucomiss 80(%rsp,%rcx,4), %xmm2
je .L21
.L41:
movss (%rbx,%rdx,4), %xmm0
comiss %xmm0, %xmm3
jbe .L21
leal (%r10,%r14), %r12d
movaps %xmm0, %xmm3
jmp .L21
.L52:
movss .LC0(%rip), %xmm3
leal (%r9,%rbp), %ecx
addl %r12d, %r9d
movss .LC4(%rip), %xmm2
movaps %xmm2, %xmm1
jmp .L28
.L25:
addq $1, %rax
cmpq %rsi, %rax
je .L53
.L28:
cmpl %eax, %edi
je .L25
cmpl %eax, %ecx
je .L25
cmpl %eax, %r9d
je .L25
movl %eax, %r11d
leal (%r8,%rax), %edx
movslq %edx, %rdx
ucomiss 80(%rsp,%rdx,4), %xmm2
jp .L43
ucomiss 80(%rsp,%rdx,4), %xmm1
je .L25
.L43:
movss (%rbx,%rax,4), %xmm0
comiss %xmm0, %xmm3
jbe .L25
leal (%r10,%r11), %r13d
movaps %xmm0, %xmm3
jmp .L25
.L53:
movl $7, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %r14
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 28(%rsp), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC8(%rip), %r15
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $8, %edx
leaq .LC9(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 24(%rsp), %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $9, %edx
leaq .LC10(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
imull $1683, 28(%rsp), %eax
leal (%rax,%rbp), %ecx
movslq %ecx, %rcx
leal (%rax,%r12), %edx
movslq %edx, %rdx
movss 80(%rsp,%rcx,4), %xmm0
addss 80(%rsp,%rdx,4), %xmm0
addl %r13d, %eax
cltq
addss 80(%rsp,%rax,4), %xmm0
divss .LC11(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $5, %edx
leaq .LC12(%rip), %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
movq %r14, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r14
testq %r14, %r14
je .L54
cmpb $0, 56(%r14)
je .L31
movzbl 67(%r14), %eax
.L32:
movsbl %al, %esi
movq %r15, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rip), %rdx
movq 240(%rdx,%rax), %r14
testq %r14, %r14
je .L55
cmpb $0, 56(%r14)
je .L35
movzbl 67(%r14), %eax
.L36:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
.L16:
movq 8(%rsp), %rdi
call feof@PLT
testl %eax, %eax
jne .L56
leaq 24(%rsp), %rcx
leaq 28(%rsp), %rdx
leaq 32(%rsp), %r9
leaq 36(%rsp), %r8
leaq .LC5(%rip), %rsi
movq 8(%rsp), %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 24(%rsp), %edx
imull $1683, %edx, %r9d
imull $1684, %edx, %edi
leal 1(%r9), %eax
cltq
movslq %edx, %rsi
addq $1, %rsi
imulq $1683, %rsi, %rsi
imull $-1683, %edx, %r10d
movl 28(%rsp), %r8d
subl %edx, %r8d
imull $1683, %r8d, %r8d
movq %rax, %rdx
movss .LC0(%rip), %xmm1
jmp .L20
.L54:
movq 6355096(%rsp), %rax
subq %fs:40, %rax
jne .L57
call _ZSt16__throw_bad_castv@PLT
.L57:
call __stack_chk_fail@PLT
.L31:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L32
.L55:
movq 6355096(%rsp), %rax
subq %fs:40, %rax
jne .L58
call _ZSt16__throw_bad_castv@PLT
.L58:
call __stack_chk_fail@PLT
.L35:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
jmp .L36
.L56:
movq 8(%rsp), %rdi
call fclose@PLT
movq 6355096(%rsp), %rax
subq %fs:40, %rax
jne .L59
movl $0, %eax
addq $6355112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L59:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z4testPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL4testPfS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1120403456
.align 4
.LC4:
.long -1082130432
.align 4
.LC11:
.long 1077936128
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mymain.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI0_0:
.long 0x42c80000 # float 100
.LCPI0_1:
.long 0xbf800000 # float -1
.LCPI0_2:
.long 0x40400000 # float 3
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $6355144, %rsp # imm = 0x60F8C8
.cfi_def_cfa_offset 6355200
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_50
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
movl $11329956, %edi # imm = 0xACE1A4
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
leaq 128(%rsp), %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_5: # %.preheader95
# =>This Loop Header: Depth=1
# Child Loop BB0_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $-1082130432, (%rax,%rdx,4) # imm = 0xBF800000
incq %rdx
cmpq $1683, %rdx # imm = 0x693
jne .LBB0_6
# %bb.7: # in Loop: Header=BB0_5 Depth=1
incq %rcx
addq $6732, %rax # imm = 0x1A4C
cmpq $944, %rcx # imm = 0x3B0
jne .LBB0_5
# %bb.8:
leaq 32(%rsp), %rdi
movl $6355008, %esi # imm = 0x60F840
callq hipMalloc
leaq 24(%rsp), %rdi
movl $11329956, %esi # imm = 0xACE1A4
callq hipMalloc
movq %r14, %rdi
callq feof
testl %eax, %eax
jne .LBB0_11
# %bb.9: # %.lr.ph.preheader
leaq 4(%rsp), %r15
leaq 8(%rsp), %r12
leaq 12(%rsp), %r13
leaq 44(%rsp), %rbp
.p2align 4, 0x90
.LBB0_10: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.3, %esi
movq %r14, %rdi
movq %r15, %rdx
movq %r12, %rcx
movq %r13, %r8
movq %rbp, %r9
xorl %eax, %eax
callq __isoc23_fscanf
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movslq 4(%rsp), %rax
imulq $1683, %rax, %rax # imm = 0x693
movslq 8(%rsp), %rcx
addq %rax, %rcx
movss %xmm0, 128(%rsp,%rcx,4)
movq %r14, %rdi
callq feof
testl %eax, %eax
je .LBB0_10
.LBB0_11: # %._crit_edge
movq %r14, %rdi
callq fclose
movq 32(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $6355008, %edx # imm = 0x60F840
movl $1, %ecx
callq hipMemcpy
movabsq $4294967328, %rdi # imm = 0x100000020
leaq 224(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_13
# %bb.12:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_ZL4testPfS_, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_13:
movq 24(%rsp), %rsi
movl $11329956, %edx # imm = 0xACE1A4
movq 16(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $.L.str.4, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r14
movq %rax, %rdi
callq feof
testl %eax, %eax
je .LBB0_14
.LBB0_49: # %._crit_edge125
movq %r14, %rdi
callq fclose
xorl %eax, %eax
addq $6355144, %rsp # imm = 0x60F8C8
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_14: # %.lr.ph124.preheader
.cfi_def_cfa_offset 6355200
addq $4, 16(%rsp) # 8-byte Folded Spill
# implicit-def: $ebp
# implicit-def: $ebx
# implicit-def: $r13d
jmp .LBB0_15
.p2align 4, 0x90
.LBB0_47: # in Loop: Header=BB0_15 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_48: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit90
# in Loop: Header=BB0_15 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r14, %rdi
callq feof
testl %eax, %eax
jne .LBB0_49
.LBB0_15: # %.lr.ph124
# =>This Loop Header: Depth=1
# Child Loop BB0_38 Depth 2
# Child Loop BB0_19 Depth 2
# Child Loop BB0_27 Depth 2
movl $.L.str.3, %esi
movq %r14, %rdi
leaq 4(%rsp), %rdx
leaq 8(%rsp), %rcx
leaq 12(%rsp), %r8
leaq 44(%rsp), %r9
xorl %eax, %eax
callq __isoc23_fscanf
movslq 8(%rsp), %rcx
imull $1683, %ecx, %eax # imm = 0x693
leal 1683(%rax), %edx
leal 1(%rax), %esi
cmpl %edx, %esi
jge .LBB0_16
# %bb.37: # %.lr.ph104
# in Loop: Header=BB0_15 Depth=1
imull $1683, 4(%rsp), %edi # imm = 0x693
imulq $1684, %rcx, %r10 # imm = 0x694
movslq %eax, %r8
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r9
notq %r8
addq %r10, %r8
incl %edi
xorl %r10d, %r10d
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
jmp .LBB0_38
.p2align 4, 0x90
.LBB0_42: # in Loop: Header=BB0_38 Depth=2
incq %r10
cmpl $1682, %r10d # imm = 0x692
je .LBB0_17
.LBB0_38: # Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r10, %r8
je .LBB0_42
# %bb.39: # in Loop: Header=BB0_38 Depth=2
leal (%rdi,%r10), %r11d
movslq %r11d, %r11
movss 128(%rsp,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB0_40
jnp .LBB0_42
.LBB0_40: # in Loop: Header=BB0_38 Depth=2
movss (%r9,%r10,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB0_42
# %bb.41: # in Loop: Header=BB0_38 Depth=2
leaq 1(%r10), %r13
movaps %xmm1, %xmm0
jmp .LBB0_42
.p2align 4, 0x90
.LBB0_16: # in Loop: Header=BB0_15 Depth=1
movss .LCPI0_1(%rip), %xmm2 # xmm2 = mem[0],zero,zero,zero
.LBB0_17: # %.preheader94
# in Loop: Header=BB0_15 Depth=1
cmpl %edx, %esi
jge .LBB0_25
# %bb.18: # %.lr.ph110
# in Loop: Header=BB0_15 Depth=1
imulq $1684, %rcx, %rdi # imm = 0x694
leal (%rax,%r13), %r9d
imull $1683, 4(%rsp), %r10d # imm = 0x693
movslq %eax, %r8
movslq %r10d, %r10
movslq %r9d, %r11
movq 16(%rsp), %r9 # 8-byte Reload
leaq (%r9,%r8,4), %r9
notq %r8
addq %r8, %rdi
addq %r11, %r8
leaq 132(%rsp), %r11
leaq (%r11,%r10,4), %r10
xorl %r11d, %r11d
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB0_19
.p2align 4, 0x90
.LBB0_24: # in Loop: Header=BB0_19 Depth=2
incq %r11
cmpl $1682, %r11d # imm = 0x692
je .LBB0_25
.LBB0_19: # Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r11, %rdi
je .LBB0_24
# %bb.20: # in Loop: Header=BB0_19 Depth=2
cmpq %r11, %r8
je .LBB0_24
# %bb.21: # in Loop: Header=BB0_19 Depth=2
movss (%r10,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB0_22
jnp .LBB0_24
.LBB0_22: # in Loop: Header=BB0_19 Depth=2
movss (%r9,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB0_24
# %bb.23: # in Loop: Header=BB0_19 Depth=2
leal 1(%r11), %ebx
movaps %xmm1, %xmm0
jmp .LBB0_24
.p2align 4, 0x90
.LBB0_25: # %.preheader
# in Loop: Header=BB0_15 Depth=1
cmpl %edx, %esi
jge .LBB0_34
# %bb.26: # %.lr.ph116
# in Loop: Header=BB0_15 Depth=1
imull $1684, %ecx, %edx # imm = 0x694
leal (%rax,%r13), %ecx
leal (%rbx,%rax), %esi
imull $1683, 4(%rsp), %edi # imm = 0x693
cltq
movslq %edi, %rdi
movslq %esi, %r8
movslq %ecx, %rcx
movslq %edx, %rdx
movq 16(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %rsi
notq %rax
addq %rax, %rdx
addq %rax, %rcx
addq %r8, %rax
leaq 132(%rsp), %r8
leaq (%r8,%rdi,4), %rdi
xorl %r8d, %r8d
movss .LCPI0_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB0_27
.p2align 4, 0x90
.LBB0_33: # in Loop: Header=BB0_27 Depth=2
incq %r8
cmpl $1682, %r8d # imm = 0x692
je .LBB0_34
.LBB0_27: # Parent Loop BB0_15 Depth=1
# => This Inner Loop Header: Depth=2
cmpq %r8, %rdx
je .LBB0_33
# %bb.28: # in Loop: Header=BB0_27 Depth=2
cmpq %r8, %rcx
je .LBB0_33
# %bb.29: # in Loop: Header=BB0_27 Depth=2
cmpq %r8, %rax
je .LBB0_33
# %bb.30: # in Loop: Header=BB0_27 Depth=2
movss (%rdi,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm2, %xmm1
jne .LBB0_31
jnp .LBB0_33
.LBB0_31: # in Loop: Header=BB0_27 Depth=2
movss (%rsi,%r8,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jbe .LBB0_33
# %bb.32: # in Loop: Header=BB0_27 Depth=2
leal 1(%r8), %ebp
movaps %xmm1, %xmm0
jmp .LBB0_33
.p2align 4, 0x90
.LBB0_34: # %._crit_edge117
# in Loop: Header=BB0_15 Depth=1
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 4(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl 8(%rsp), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movslq 4(%rsp), %rax
imulq $1683, %rax, %rax # imm = 0x693
movslq %r13d, %rcx
addq %rax, %rcx
movss 128(%rsp,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
leal (%rax,%rbx), %ecx
movslq %ecx, %rcx
addss 128(%rsp,%rcx,4), %xmm0
addl %ebp, %eax
cltq
addss 128(%rsp,%rax,4), %xmm0
divss .LCPI0_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.9, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 12(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB0_50
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i82
# in Loop: Header=BB0_15 Depth=1
cmpb $0, 56(%r12)
je .LBB0_43
# %bb.36: # in Loop: Header=BB0_15 Depth=1
movzbl 67(%r12), %eax
jmp .LBB0_44
.p2align 4, 0x90
.LBB0_43: # in Loop: Header=BB0_15 Depth=1
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_44: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit85
# in Loop: Header=BB0_15 Depth=1
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB0_50
# %bb.45: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i87
# in Loop: Header=BB0_15 Depth=1
cmpb $0, 56(%r15)
je .LBB0_47
# %bb.46: # in Loop: Header=BB0_15 Depth=1
movzbl 67(%r15), %eax
jmp .LBB0_48
.LBB0_50:
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL19__device_stub__testPfS_
.type _ZL19__device_stub__testPfS_,@function
_ZL19__device_stub__testPfS_: # @_ZL19__device_stub__testPfS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL4testPfS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _ZL19__device_stub__testPfS_, .Lfunc_end1-_ZL19__device_stub__testPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL4testPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "start:"
.size .L.str, 7
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/3160102482/myhelloworld/ml-100k/u2.base"
.size .L.str.1, 46
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%d%d%f%d"
.size .L.str.3, 9
.type _ZL4testPfS_,@object # @_ZL4testPfS_
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL4testPfS_:
.quad _ZL19__device_stub__testPfS_
.size _ZL4testPfS_, 8
.type .L.str.4,@object # @.str.4
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.4:
.asciz "/home/3160102482/myhelloworld/ml-100k/u2.test"
.size .L.str.4, 46
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "userid:"
.size .L.str.5, 8
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " "
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "movieid:"
.size .L.str.7, 9
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "estimate:"
.size .L.str.8, 10
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "real:"
.size .L.str.9, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL4testPfS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL19__device_stub__testPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZL4testPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Transpose checkRows matrix with rows == parity checks, to
// bitRows matrix with rows == bits
__global__ void
transposeRC (unsigned int* map, float *checkRows, float *bitRows,
unsigned int numChecks, unsigned int maxBitsForCheck) {
// index
unsigned int m,n;
unsigned int thisRowStart, thisRowLength;
unsigned int cellIndex, oneDindex;
m = blockIdx.x;
n = threadIdx.x + 1;
if (m < numChecks) {
thisRowStart = m * (maxBitsForCheck+1);
thisRowLength = map[thisRowStart];
if (n <= thisRowLength) {
cellIndex = thisRowStart + n;
oneDindex = map[cellIndex];
bitRows[oneDindex] = checkRows[cellIndex];
}
}
} | code for sm_80
Function : _Z11transposeRCPjPfS0_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*0050*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0060*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0070*/ IMAD R5, R5, UR4, RZ ; /* 0x0000000405057c24 */
/* 0x000fe2000f8e02ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R5, R6, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0006 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*00c0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x001fc80007ffe0ff */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f04070 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R2, R5, R6, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0006 */
/*0110*/ IMAD.WIDE.U32 R4, R5, R6.reuse, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x080fe400078e0006 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee2000c1e1900 */
/*0140*/ IMAD.WIDE.U32 R6, R2, R6, c[0x0][0x170] ; /* 0x00005c0002067625 */
/* 0x004fca00078e0006 */
/*0150*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x008fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Transpose checkRows matrix with rows == parity checks, to
// bitRows matrix with rows == bits
__global__ void
transposeRC (unsigned int* map, float *checkRows, float *bitRows,
unsigned int numChecks, unsigned int maxBitsForCheck) {
// index
unsigned int m,n;
unsigned int thisRowStart, thisRowLength;
unsigned int cellIndex, oneDindex;
m = blockIdx.x;
n = threadIdx.x + 1;
if (m < numChecks) {
thisRowStart = m * (maxBitsForCheck+1);
thisRowLength = map[thisRowStart];
if (n <= thisRowLength) {
cellIndex = thisRowStart + n;
oneDindex = map[cellIndex];
bitRows[oneDindex] = checkRows[cellIndex];
}
}
} | .file "tmpxft_0007067b_00000000-6_transposeRC.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj
.type _Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj, @function
_Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11transposeRCPjPfS0_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj, .-_Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj
.globl _Z11transposeRCPjPfS0_jj
.type _Z11transposeRCPjPfS0_jj, @function
_Z11transposeRCPjPfS0_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11transposeRCPjPfS0_jj, .-_Z11transposeRCPjPfS0_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11transposeRCPjPfS0_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11transposeRCPjPfS0_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Transpose checkRows matrix with rows == parity checks, to
// bitRows matrix with rows == bits
__global__ void
transposeRC (unsigned int* map, float *checkRows, float *bitRows,
unsigned int numChecks, unsigned int maxBitsForCheck) {
// index
unsigned int m,n;
unsigned int thisRowStart, thisRowLength;
unsigned int cellIndex, oneDindex;
m = blockIdx.x;
n = threadIdx.x + 1;
if (m < numChecks) {
thisRowStart = m * (maxBitsForCheck+1);
thisRowLength = map[thisRowStart];
if (n <= thisRowLength) {
cellIndex = thisRowStart + n;
oneDindex = map[cellIndex];
bitRows[oneDindex] = checkRows[cellIndex];
}
}
} | #include <hip/hip_runtime.h>
// Transpose checkRows matrix with rows == parity checks, to
// bitRows matrix with rows == bits
__global__ void
transposeRC (unsigned int* map, float *checkRows, float *bitRows,
unsigned int numChecks, unsigned int maxBitsForCheck) {
// index
unsigned int m,n;
unsigned int thisRowStart, thisRowLength;
unsigned int cellIndex, oneDindex;
m = blockIdx.x;
n = threadIdx.x + 1;
if (m < numChecks) {
thisRowStart = m * (maxBitsForCheck+1);
thisRowLength = map[thisRowStart];
if (n <= thisRowLength) {
cellIndex = thisRowStart + n;
oneDindex = map[cellIndex];
bitRows[oneDindex] = checkRows[cellIndex];
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// Transpose checkRows matrix with rows == parity checks, to
// bitRows matrix with rows == bits
__global__ void
transposeRC (unsigned int* map, float *checkRows, float *bitRows,
unsigned int numChecks, unsigned int maxBitsForCheck) {
// index
unsigned int m,n;
unsigned int thisRowStart, thisRowLength;
unsigned int cellIndex, oneDindex;
m = blockIdx.x;
n = threadIdx.x + 1;
if (m < numChecks) {
thisRowStart = m * (maxBitsForCheck+1);
thisRowLength = map[thisRowStart];
if (n <= thisRowLength) {
cellIndex = thisRowStart + n;
oneDindex = map[cellIndex];
bitRows[oneDindex] = checkRows[cellIndex];
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11transposeRCPjPfS0_jj
.globl _Z11transposeRCPjPfS0_jj
.p2align 8
.type _Z11transposeRCPjPfS0_jj,@function
_Z11transposeRCPjPfS0_jj:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s2
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s4, s15
s_lshl_b64 s[6:7], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_3
v_add3_u32 v0, v0, s4, 1
v_mov_b32_e32 v1, 0
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11transposeRCPjPfS0_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11transposeRCPjPfS0_jj, .Lfunc_end0-_Z11transposeRCPjPfS0_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11transposeRCPjPfS0_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11transposeRCPjPfS0_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// Transpose checkRows matrix with rows == parity checks, to
// bitRows matrix with rows == bits
__global__ void
transposeRC (unsigned int* map, float *checkRows, float *bitRows,
unsigned int numChecks, unsigned int maxBitsForCheck) {
// index
unsigned int m,n;
unsigned int thisRowStart, thisRowLength;
unsigned int cellIndex, oneDindex;
m = blockIdx.x;
n = threadIdx.x + 1;
if (m < numChecks) {
thisRowStart = m * (maxBitsForCheck+1);
thisRowLength = map[thisRowStart];
if (n <= thisRowLength) {
cellIndex = thisRowStart + n;
oneDindex = map[cellIndex];
bitRows[oneDindex] = checkRows[cellIndex];
}
}
} | .text
.file "transposeRC.hip"
.globl _Z26__device_stub__transposeRCPjPfS0_jj # -- Begin function _Z26__device_stub__transposeRCPjPfS0_jj
.p2align 4, 0x90
.type _Z26__device_stub__transposeRCPjPfS0_jj,@function
_Z26__device_stub__transposeRCPjPfS0_jj: # @_Z26__device_stub__transposeRCPjPfS0_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11transposeRCPjPfS0_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__transposeRCPjPfS0_jj, .Lfunc_end0-_Z26__device_stub__transposeRCPjPfS0_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11transposeRCPjPfS0_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11transposeRCPjPfS0_jj,@object # @_Z11transposeRCPjPfS0_jj
.section .rodata,"a",@progbits
.globl _Z11transposeRCPjPfS0_jj
.p2align 3, 0x0
_Z11transposeRCPjPfS0_jj:
.quad _Z26__device_stub__transposeRCPjPfS0_jj
.size _Z11transposeRCPjPfS0_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11transposeRCPjPfS0_jj"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__transposeRCPjPfS0_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11transposeRCPjPfS0_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11transposeRCPjPfS0_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e240000002500 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ ULDC UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fe20000000800 */
/*0050*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*0060*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fcc000fffe03f */
/*0070*/ IMAD R5, R5, UR4, RZ ; /* 0x0000000405057c24 */
/* 0x000fe2000f8e02ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R5, R6, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0006 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*00c0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x001fc80007ffe0ff */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x004fda0003f04070 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, R0, R5, RZ ; /* 0x0000000500057210 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD.WIDE.U32 R2, R5, R6, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fc800078e0006 */
/*0110*/ IMAD.WIDE.U32 R4, R5, R6.reuse, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x080fe400078e0006 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ee2000c1e1900 */
/*0140*/ IMAD.WIDE.U32 R6, R2, R6, c[0x0][0x170] ; /* 0x00005c0002067625 */
/* 0x004fca00078e0006 */
/*0150*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x008fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11transposeRCPjPfS0_jj
.globl _Z11transposeRCPjPfS0_jj
.p2align 8
.type _Z11transposeRCPjPfS0_jj,@function
_Z11transposeRCPjPfS0_jj:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_ge_u32 s15, s2
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s4, s15
s_lshl_b64 s[6:7], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s6, s2, s6
s_addc_u32 s7, s3, s7
s_load_b32 s5, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s5, v0
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_3
v_add3_u32 v0, v0, s4, 1
v_mov_b32_e32 v1, 0
s_load_b128 s[4:7], s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[0:1]
v_add_co_u32 v4, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[4:5], off
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11transposeRCPjPfS0_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11transposeRCPjPfS0_jj, .Lfunc_end0-_Z11transposeRCPjPfS0_jj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11transposeRCPjPfS0_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11transposeRCPjPfS0_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007067b_00000000-6_transposeRC.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj
.type _Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj, @function
_Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11transposeRCPjPfS0_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj, .-_Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj
.globl _Z11transposeRCPjPfS0_jj
.type _Z11transposeRCPjPfS0_jj, @function
_Z11transposeRCPjPfS0_jj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z11transposeRCPjPfS0_jjPjPfS0_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11transposeRCPjPfS0_jj, .-_Z11transposeRCPjPfS0_jj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11transposeRCPjPfS0_jj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11transposeRCPjPfS0_jj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transposeRC.hip"
.globl _Z26__device_stub__transposeRCPjPfS0_jj # -- Begin function _Z26__device_stub__transposeRCPjPfS0_jj
.p2align 4, 0x90
.type _Z26__device_stub__transposeRCPjPfS0_jj,@function
_Z26__device_stub__transposeRCPjPfS0_jj: # @_Z26__device_stub__transposeRCPjPfS0_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11transposeRCPjPfS0_jj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__transposeRCPjPfS0_jj, .Lfunc_end0-_Z26__device_stub__transposeRCPjPfS0_jj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11transposeRCPjPfS0_jj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11transposeRCPjPfS0_jj,@object # @_Z11transposeRCPjPfS0_jj
.section .rodata,"a",@progbits
.globl _Z11transposeRCPjPfS0_jj
.p2align 3, 0x0
_Z11transposeRCPjPfS0_jj:
.quad _Z26__device_stub__transposeRCPjPfS0_jj
.size _Z11transposeRCPjPfS0_jj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11transposeRCPjPfS0_jj"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__transposeRCPjPfS0_jj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11transposeRCPjPfS0_jj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Add 2 vectors using CUDA.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN( value ) { \
cudaError_t err = value; \
if( err != cudaSuccess ) { \
fprintf( stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(err), __LINE__, __FILE__ ); \
exit( 1 ); \
} }
#define VECT_SIZE (7841u)
#define BLOCK_SIZE (128u)
__global__ void vect_fill( int * data )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) data[ i ] = i + 1;
}
__global__ void vect_add( int * vect_1, int * vect_2, int * vect_result )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) vect_result[i] = vect_1[i] + vect_2[i];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(int argc, char **argv) {
/* Allocate data buffer in host memory for result vector */
int *h_result = (int*) malloc( VECT_SIZE * sizeof(int) );
memset( h_result, 0, VECT_SIZE * sizeof(int) );
/* Allocate data buffer in device memory for 3 vectors */
int *d_vector_1, *d_vector_2, *d_vector_result = NULL;
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_1, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_2, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_result, VECT_SIZE * sizeof(int) ) );
/* Configure kernel */
int blockSize = BLOCK_SIZE;
int gridSize = (VECT_SIZE + BLOCK_SIZE - 1) / BLOCK_SIZE;
/* Run kernels to fill 2 vectors */
vect_fill<<< gridSize, blockSize >>>( d_vector_1 );
vect_fill<<< gridSize, blockSize >>>( d_vector_2 );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( cudaDeviceSynchronize() );
/* Add 2 vectors */
vect_add<<< gridSize, blockSize >>>( d_vector_1, d_vector_2, d_vector_result );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( cudaDeviceSynchronize() );
/* Copy back to host and print */
CUDA_CHECK_RETURN( cudaMemcpy( h_result, d_vector_result, VECT_SIZE * sizeof(int), cudaMemcpyDeviceToHost) );
for( unsigned int i = 0; i < VECT_SIZE; ++i ) std::cout << h_result[i] << std::endl;
CUDA_CHECK_RETURN( cudaFree(d_vector_1) );
CUDA_CHECK_RETURN( cudaFree(d_vector_2) );
CUDA_CHECK_RETURN( cudaFree(d_vector_result) );
free( h_result );
return 0;
} | code for sm_80
Function : _Z8vect_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ea0, PT ; /* 0x00001ea00600780c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9vect_fillPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ea0, PT ; /* 0x00001ea00200780c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Add 2 vectors using CUDA.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN( value ) { \
cudaError_t err = value; \
if( err != cudaSuccess ) { \
fprintf( stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(err), __LINE__, __FILE__ ); \
exit( 1 ); \
} }
#define VECT_SIZE (7841u)
#define BLOCK_SIZE (128u)
__global__ void vect_fill( int * data )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) data[ i ] = i + 1;
}
__global__ void vect_add( int * vect_1, int * vect_2, int * vect_result )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) vect_result[i] = vect_1[i] + vect_2[i];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(int argc, char **argv) {
/* Allocate data buffer in host memory for result vector */
int *h_result = (int*) malloc( VECT_SIZE * sizeof(int) );
memset( h_result, 0, VECT_SIZE * sizeof(int) );
/* Allocate data buffer in device memory for 3 vectors */
int *d_vector_1, *d_vector_2, *d_vector_result = NULL;
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_1, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_2, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_result, VECT_SIZE * sizeof(int) ) );
/* Configure kernel */
int blockSize = BLOCK_SIZE;
int gridSize = (VECT_SIZE + BLOCK_SIZE - 1) / BLOCK_SIZE;
/* Run kernels to fill 2 vectors */
vect_fill<<< gridSize, blockSize >>>( d_vector_1 );
vect_fill<<< gridSize, blockSize >>>( d_vector_2 );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( cudaDeviceSynchronize() );
/* Add 2 vectors */
vect_add<<< gridSize, blockSize >>>( d_vector_1, d_vector_2, d_vector_result );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( cudaDeviceSynchronize() );
/* Copy back to host and print */
CUDA_CHECK_RETURN( cudaMemcpy( h_result, d_vector_result, VECT_SIZE * sizeof(int), cudaMemcpyDeviceToHost) );
for( unsigned int i = 0; i < VECT_SIZE; ++i ) std::cout << h_result[i] << std::endl;
CUDA_CHECK_RETURN( cudaFree(d_vector_1) );
CUDA_CHECK_RETURN( cudaFree(d_vector_2) );
CUDA_CHECK_RETURN( cudaFree(d_vector_result) );
free( h_result );
return 0;
} | .file "tmpxft_000aec18_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9vect_fillPiPi
.type _Z28__device_stub__Z9vect_fillPiPi, @function
_Z28__device_stub__Z9vect_fillPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9vect_fillPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z9vect_fillPiPi, .-_Z28__device_stub__Z9vect_fillPiPi
.globl _Z9vect_fillPi
.type _Z9vect_fillPi, @function
_Z9vect_fillPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9vect_fillPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9vect_fillPi, .-_Z9vect_fillPi
.globl _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
.type _Z31__device_stub__Z8vect_addPiS_S_PiS_S_, @function
_Z31__device_stub__Z8vect_addPiS_S_PiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8vect_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z31__device_stub__Z8vect_addPiS_S_PiS_S_, .-_Z31__device_stub__Z8vect_addPiS_S_PiS_S_
.globl _Z8vect_addPiS_S_
.type _Z8vect_addPiS_S_, @function
_Z8vect_addPiS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8vect_addPiS_S_, .-_Z8vect_addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jdobes/apvg/master/project1/main.cu"
.align 8
.LC1:
.string "Error %s at line %d in file %s\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $31364, %edi
call malloc@PLT
movq %rax, %r15
movl $31364, %edx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $31364, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
leaq 16(%rsp), %rdi
movl $31364, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
leaq 24(%rsp), %rdi
movl $31364, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $62, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L23:
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $62, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L24:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L45
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $62, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L26:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L47
movl $2, %ecx
movl $31364, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movq %r15, %r12
leaq 31364(%r15), %r14
leaq _ZSt4cout(%rip), %r13
jmp .L33
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $49, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $50, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $51, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movq 8(%rsp), %rdi
call _Z28__device_stub__Z9vect_fillPiPi
jmp .L23
.L44:
movq 16(%rsp), %rdi
call _Z28__device_stub__Z9vect_fillPiPi
jmp .L24
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $61, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
jmp .L26
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $66, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $69, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L31:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L32:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r14, %r12
je .L50
.L33:
movl (%r12), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L51
cmpb $0, 56(%rbp)
je .L31
movzbl 67(%rbp), %esi
jmp .L32
.L50:
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L52
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L53
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L54
movq %r15, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $72, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $73, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $74, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z8vect_addPiS_S_"
.LC3:
.string "_Z9vect_fillPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vect_addPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vect_fillPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Add 2 vectors using CUDA.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <iostream>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN( value ) { \
cudaError_t err = value; \
if( err != cudaSuccess ) { \
fprintf( stderr, "Error %s at line %d in file %s\n", \
cudaGetErrorString(err), __LINE__, __FILE__ ); \
exit( 1 ); \
} }
#define VECT_SIZE (7841u)
#define BLOCK_SIZE (128u)
__global__ void vect_fill( int * data )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) data[ i ] = i + 1;
}
__global__ void vect_add( int * vect_1, int * vect_2, int * vect_result )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) vect_result[i] = vect_1[i] + vect_2[i];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(int argc, char **argv) {
/* Allocate data buffer in host memory for result vector */
int *h_result = (int*) malloc( VECT_SIZE * sizeof(int) );
memset( h_result, 0, VECT_SIZE * sizeof(int) );
/* Allocate data buffer in device memory for 3 vectors */
int *d_vector_1, *d_vector_2, *d_vector_result = NULL;
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_1, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_2, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( cudaMalloc( &d_vector_result, VECT_SIZE * sizeof(int) ) );
/* Configure kernel */
int blockSize = BLOCK_SIZE;
int gridSize = (VECT_SIZE + BLOCK_SIZE - 1) / BLOCK_SIZE;
/* Run kernels to fill 2 vectors */
vect_fill<<< gridSize, blockSize >>>( d_vector_1 );
vect_fill<<< gridSize, blockSize >>>( d_vector_2 );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( cudaDeviceSynchronize() );
/* Add 2 vectors */
vect_add<<< gridSize, blockSize >>>( d_vector_1, d_vector_2, d_vector_result );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( cudaDeviceSynchronize() );
/* Copy back to host and print */
CUDA_CHECK_RETURN( cudaMemcpy( h_result, d_vector_result, VECT_SIZE * sizeof(int), cudaMemcpyDeviceToHost) );
for( unsigned int i = 0; i < VECT_SIZE; ++i ) std::cout << h_result[i] << std::endl;
CUDA_CHECK_RETURN( cudaFree(d_vector_1) );
CUDA_CHECK_RETURN( cudaFree(d_vector_2) );
CUDA_CHECK_RETURN( cudaFree(d_vector_result) );
free( h_result );
return 0;
} | /**
* Add 2 vectors using CUDA.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN( value ) { \
hipError_t err = value; \
if( err != hipSuccess ) { \
fprintf( stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(err), __LINE__, __FILE__ ); \
exit( 1 ); \
} }
#define VECT_SIZE (7841u)
#define BLOCK_SIZE (128u)
__global__ void vect_fill( int * data )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) data[ i ] = i + 1;
}
__global__ void vect_add( int * vect_1, int * vect_2, int * vect_result )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) vect_result[i] = vect_1[i] + vect_2[i];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(int argc, char **argv) {
/* Allocate data buffer in host memory for result vector */
int *h_result = (int*) malloc( VECT_SIZE * sizeof(int) );
memset( h_result, 0, VECT_SIZE * sizeof(int) );
/* Allocate data buffer in device memory for 3 vectors */
int *d_vector_1, *d_vector_2, *d_vector_result = NULL;
CUDA_CHECK_RETURN( hipMalloc( &d_vector_1, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( hipMalloc( &d_vector_2, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( hipMalloc( &d_vector_result, VECT_SIZE * sizeof(int) ) );
/* Configure kernel */
int blockSize = BLOCK_SIZE;
int gridSize = (VECT_SIZE + BLOCK_SIZE - 1) / BLOCK_SIZE;
/* Run kernels to fill 2 vectors */
vect_fill<<< gridSize, blockSize >>>( d_vector_1 );
vect_fill<<< gridSize, blockSize >>>( d_vector_2 );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( hipDeviceSynchronize() );
/* Add 2 vectors */
vect_add<<< gridSize, blockSize >>>( d_vector_1, d_vector_2, d_vector_result );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( hipDeviceSynchronize() );
/* Copy back to host and print */
CUDA_CHECK_RETURN( hipMemcpy( h_result, d_vector_result, VECT_SIZE * sizeof(int), hipMemcpyDeviceToHost) );
for( unsigned int i = 0; i < VECT_SIZE; ++i ) std::cout << h_result[i] << std::endl;
CUDA_CHECK_RETURN( hipFree(d_vector_1) );
CUDA_CHECK_RETURN( hipFree(d_vector_2) );
CUDA_CHECK_RETURN( hipFree(d_vector_result) );
free( h_result );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Add 2 vectors using CUDA.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN( value ) { \
hipError_t err = value; \
if( err != hipSuccess ) { \
fprintf( stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(err), __LINE__, __FILE__ ); \
exit( 1 ); \
} }
#define VECT_SIZE (7841u)
#define BLOCK_SIZE (128u)
__global__ void vect_fill( int * data )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) data[ i ] = i + 1;
}
__global__ void vect_add( int * vect_1, int * vect_2, int * vect_result )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) vect_result[i] = vect_1[i] + vect_2[i];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(int argc, char **argv) {
/* Allocate data buffer in host memory for result vector */
int *h_result = (int*) malloc( VECT_SIZE * sizeof(int) );
memset( h_result, 0, VECT_SIZE * sizeof(int) );
/* Allocate data buffer in device memory for 3 vectors */
int *d_vector_1, *d_vector_2, *d_vector_result = NULL;
CUDA_CHECK_RETURN( hipMalloc( &d_vector_1, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( hipMalloc( &d_vector_2, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( hipMalloc( &d_vector_result, VECT_SIZE * sizeof(int) ) );
/* Configure kernel */
int blockSize = BLOCK_SIZE;
int gridSize = (VECT_SIZE + BLOCK_SIZE - 1) / BLOCK_SIZE;
/* Run kernels to fill 2 vectors */
vect_fill<<< gridSize, blockSize >>>( d_vector_1 );
vect_fill<<< gridSize, blockSize >>>( d_vector_2 );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( hipDeviceSynchronize() );
/* Add 2 vectors */
vect_add<<< gridSize, blockSize >>>( d_vector_1, d_vector_2, d_vector_result );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( hipDeviceSynchronize() );
/* Copy back to host and print */
CUDA_CHECK_RETURN( hipMemcpy( h_result, d_vector_result, VECT_SIZE * sizeof(int), hipMemcpyDeviceToHost) );
for( unsigned int i = 0; i < VECT_SIZE; ++i ) std::cout << h_result[i] << std::endl;
CUDA_CHECK_RETURN( hipFree(d_vector_1) );
CUDA_CHECK_RETURN( hipFree(d_vector_2) );
CUDA_CHECK_RETURN( hipFree(d_vector_result) );
free( h_result );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vect_fillPi
.globl _Z9vect_fillPi
.p2align 8
.type _Z9vect_fillPi,@function
_Z9vect_fillPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x1ea1, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vect_fillPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vect_fillPi, .Lfunc_end0-_Z9vect_fillPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8vect_addPiS_S_
.globl _Z8vect_addPiS_S_
.p2align 8
.type _Z8vect_addPiS_S_,@function
_Z8vect_addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x1ea1, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vect_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8vect_addPiS_S_, .Lfunc_end1-_Z8vect_addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vect_fillPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vect_fillPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vect_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8vect_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Add 2 vectors using CUDA.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <iostream>
#include <string.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*/
#define CUDA_CHECK_RETURN( value ) { \
hipError_t err = value; \
if( err != hipSuccess ) { \
fprintf( stderr, "Error %s at line %d in file %s\n", \
hipGetErrorString(err), __LINE__, __FILE__ ); \
exit( 1 ); \
} }
#define VECT_SIZE (7841u)
#define BLOCK_SIZE (128u)
__global__ void vect_fill( int * data )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) data[ i ] = i + 1;
}
__global__ void vect_add( int * vect_1, int * vect_2, int * vect_result )
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if( i < VECT_SIZE ) vect_result[i] = vect_1[i] + vect_2[i];
}
/**
* Host function that prepares data array and passes it to the CUDA kernel.
*/
int main(int argc, char **argv) {
/* Allocate data buffer in host memory for result vector */
int *h_result = (int*) malloc( VECT_SIZE * sizeof(int) );
memset( h_result, 0, VECT_SIZE * sizeof(int) );
/* Allocate data buffer in device memory for 3 vectors */
int *d_vector_1, *d_vector_2, *d_vector_result = NULL;
CUDA_CHECK_RETURN( hipMalloc( &d_vector_1, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( hipMalloc( &d_vector_2, VECT_SIZE * sizeof(int) ) );
CUDA_CHECK_RETURN( hipMalloc( &d_vector_result, VECT_SIZE * sizeof(int) ) );
/* Configure kernel */
int blockSize = BLOCK_SIZE;
int gridSize = (VECT_SIZE + BLOCK_SIZE - 1) / BLOCK_SIZE;
/* Run kernels to fill 2 vectors */
vect_fill<<< gridSize, blockSize >>>( d_vector_1 );
vect_fill<<< gridSize, blockSize >>>( d_vector_2 );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( hipDeviceSynchronize() );
/* Add 2 vectors */
vect_add<<< gridSize, blockSize >>>( d_vector_1, d_vector_2, d_vector_result );
/* Wait until the kernel finishes its work */
CUDA_CHECK_RETURN( hipDeviceSynchronize() );
/* Copy back to host and print */
CUDA_CHECK_RETURN( hipMemcpy( h_result, d_vector_result, VECT_SIZE * sizeof(int), hipMemcpyDeviceToHost) );
for( unsigned int i = 0; i < VECT_SIZE; ++i ) std::cout << h_result[i] << std::endl;
CUDA_CHECK_RETURN( hipFree(d_vector_1) );
CUDA_CHECK_RETURN( hipFree(d_vector_2) );
CUDA_CHECK_RETURN( hipFree(d_vector_result) );
free( h_result );
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vect_fillPi # -- Begin function _Z24__device_stub__vect_fillPi
.p2align 4, 0x90
.type _Z24__device_stub__vect_fillPi,@function
_Z24__device_stub__vect_fillPi: # @_Z24__device_stub__vect_fillPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9vect_fillPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__vect_fillPi, .Lfunc_end0-_Z24__device_stub__vect_fillPi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__vect_addPiS_S_ # -- Begin function _Z23__device_stub__vect_addPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__vect_addPiS_S_,@function
_Z23__device_stub__vect_addPiS_S_: # @_Z23__device_stub__vect_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8vect_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__vect_addPiS_S_, .Lfunc_end1-_Z23__device_stub__vect_addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $31364, %edi # imm = 0x7A84
callq malloc
movq %rax, %rbx
movl $31364, %edx # imm = 0x7A84
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq $0, 40(%rsp)
leaq 72(%rsp), %rdi
movl $31364, %esi # imm = 0x7A84
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 64(%rsp), %rdi
movl $31364, %esi # imm = 0x7A84
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 40(%rsp), %rdi
movl $31364, %esi # imm = 0x7A84
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movabsq $4294967358, %r15 # imm = 0x10000003E
leaq 66(%r15), %r14
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 72(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z9vect_fillPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 64(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z9vect_fillPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movq %rdx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8vect_addPiS_S_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_16
# %bb.17:
movq 40(%rsp), %rsi
movl $31364, %edx # imm = 0x7A84
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_21
# %bb.18: # %.preheader.preheader
xorl %r15d, %r15d
jmp .LBB2_19
.p2align 4, 0x90
.LBB2_24: # in Loop: Header=BB2_19 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_19 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $7841, %r15 # imm = 0x1EA1
je .LBB2_26
.LBB2_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_20
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_19 Depth=1
cmpb $0, 56(%r14)
je .LBB2_24
# %bb.23: # in Loop: Header=BB2_19 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB2_25
.LBB2_26:
movq 72(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_27
# %bb.28:
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_29
# %bb.30:
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_31
# %bb.32:
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_20:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $49, %ecx
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $50, %ecx
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $51, %ecx
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $61, %ecx
jmp .LBB2_2
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $66, %ecx
jmp .LBB2_2
.LBB2_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $69, %ecx
jmp .LBB2_2
.LBB2_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %ecx
jmp .LBB2_2
.LBB2_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $73, %ecx
jmp .LBB2_2
.LBB2_31:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %ecx
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vect_fillPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8vect_addPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vect_fillPi,@object # @_Z9vect_fillPi
.section .rodata,"a",@progbits
.globl _Z9vect_fillPi
.p2align 3, 0x0
_Z9vect_fillPi:
.quad _Z24__device_stub__vect_fillPi
.size _Z9vect_fillPi, 8
.type _Z8vect_addPiS_S_,@object # @_Z8vect_addPiS_S_
.globl _Z8vect_addPiS_S_
.p2align 3, 0x0
_Z8vect_addPiS_S_:
.quad _Z23__device_stub__vect_addPiS_S_
.size _Z8vect_addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %s at line %d in file %s\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jdobes/apvg/master/project1/main.hip"
.size .L.str.1, 94
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vect_fillPi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8vect_addPiS_S_"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vect_fillPi
.addrsig_sym _Z23__device_stub__vect_addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vect_fillPi
.addrsig_sym _Z8vect_addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8vect_addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ea0, PT ; /* 0x00001ea00600780c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9vect_fillPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.U32.AND P0, PT, R2, 0x1ea0, PT ; /* 0x00001ea00200780c */
/* 0x000fda0003f04070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x000fe20007ffe0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*0090*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*00a0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9vect_fillPi
.globl _Z9vect_fillPi
.p2align 8
.type _Z9vect_fillPi,@function
_Z9vect_fillPi:
s_load_b32 s2, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x1ea1, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_add_nc_u32_e32 v4, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9vect_fillPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9vect_fillPi, .Lfunc_end0-_Z9vect_fillPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8vect_addPiS_S_
.globl _Z8vect_addPiS_S_
.p2align 8
.type _Z8vect_addPiS_S_,@function
_Z8vect_addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x1ea1, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8vect_addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8vect_addPiS_S_, .Lfunc_end1-_Z8vect_addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9vect_fillPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9vect_fillPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8vect_addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8vect_addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000aec18_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z9vect_fillPiPi
.type _Z28__device_stub__Z9vect_fillPiPi, @function
_Z28__device_stub__Z9vect_fillPiPi:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9vect_fillPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z28__device_stub__Z9vect_fillPiPi, .-_Z28__device_stub__Z9vect_fillPiPi
.globl _Z9vect_fillPi
.type _Z9vect_fillPi, @function
_Z9vect_fillPi:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z9vect_fillPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9vect_fillPi, .-_Z9vect_fillPi
.globl _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
.type _Z31__device_stub__Z8vect_addPiS_S_PiS_S_, @function
_Z31__device_stub__Z8vect_addPiS_S_PiS_S_:
.LFB3696:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8vect_addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z31__device_stub__Z8vect_addPiS_S_PiS_S_, .-_Z31__device_stub__Z8vect_addPiS_S_PiS_S_
.globl _Z8vect_addPiS_S_
.type _Z8vect_addPiS_S_, @function
_Z8vect_addPiS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z8vect_addPiS_S_, .-_Z8vect_addPiS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jdobes/apvg/master/project1/main.cu"
.align 8
.LC1:
.string "Error %s at line %d in file %s\n"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $31364, %edi
call malloc@PLT
movq %rax, %r15
movl $31364, %edx
movl $0, %esi
movq %rax, %rdi
call memset@PLT
movq $0, 24(%rsp)
leaq 8(%rsp), %rdi
movl $31364, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
leaq 16(%rsp), %rdi
movl $31364, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
leaq 24(%rsp), %rdi
movl $31364, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $62, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L43
.L23:
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $62, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L44
.L24:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L45
movl $128, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $62, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L26:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
jne .L47
movl $2, %ecx
movl $31364, %edx
movq 24(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L48
movq %r15, %r12
leaq 31364(%r15), %r14
leaq _ZSt4cout(%rip), %r13
jmp .L33
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $49, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $50, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $51, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L43:
movq 8(%rsp), %rdi
call _Z28__device_stub__Z9vect_fillPiPi
jmp .L23
.L44:
movq 16(%rsp), %rdi
call _Z28__device_stub__Z9vect_fillPiPi
jmp .L24
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $61, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8vect_addPiS_S_PiS_S_
jmp .L26
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $66, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $69, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L49
call _ZSt16__throw_bad_castv@PLT
.L49:
call __stack_chk_fail@PLT
.L31:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L32:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $4, %r12
cmpq %r14, %r12
je .L50
.L33:
movl (%r12), %esi
movq %r13, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L51
cmpb $0, 56(%rbp)
je .L31
movzbl 67(%rbp), %esi
jmp .L32
.L50:
movq 8(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L52
movq 16(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L53
movq 24(%rsp), %rdi
call cudaFree@PLT
testl %eax, %eax
jne .L54
movq %r15, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L55
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $72, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $73, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %r9
movl $74, %r8d
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L55:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z8vect_addPiS_S_"
.LC3:
.string "_Z9vect_fillPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3699:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z8vect_addPiS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z9vect_fillPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__vect_fillPi # -- Begin function _Z24__device_stub__vect_fillPi
.p2align 4, 0x90
.type _Z24__device_stub__vect_fillPi,@function
_Z24__device_stub__vect_fillPi: # @_Z24__device_stub__vect_fillPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z9vect_fillPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__vect_fillPi, .Lfunc_end0-_Z24__device_stub__vect_fillPi
.cfi_endproc
# -- End function
.globl _Z23__device_stub__vect_addPiS_S_ # -- Begin function _Z23__device_stub__vect_addPiS_S_
.p2align 4, 0x90
.type _Z23__device_stub__vect_addPiS_S_,@function
_Z23__device_stub__vect_addPiS_S_: # @_Z23__device_stub__vect_addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8vect_addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z23__device_stub__vect_addPiS_S_, .Lfunc_end1-_Z23__device_stub__vect_addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $31364, %edi # imm = 0x7A84
callq malloc
movq %rax, %rbx
movl $31364, %edx # imm = 0x7A84
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq $0, 40(%rsp)
leaq 72(%rsp), %rdi
movl $31364, %esi # imm = 0x7A84
callq hipMalloc
testl %eax, %eax
jne .LBB2_1
# %bb.3:
leaq 64(%rsp), %rdi
movl $31364, %esi # imm = 0x7A84
callq hipMalloc
testl %eax, %eax
jne .LBB2_4
# %bb.5:
leaq 40(%rsp), %rdi
movl $31364, %esi # imm = 0x7A84
callq hipMalloc
testl %eax, %eax
jne .LBB2_6
# %bb.7:
movabsq $4294967358, %r15 # imm = 0x10000003E
leaq 66(%r15), %r14
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_9
# %bb.8:
movq 72(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z9vect_fillPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_9:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 64(%rsp), %rax
movq %rax, 48(%rsp)
leaq 48(%rsp), %rax
movq %rax, (%rsp)
leaq 80(%rsp), %rdi
leaq 8(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 8(%rsp), %rcx
movl 16(%rsp), %r8d
movq %rsp, %r9
movl $_Z9vect_fillPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_12
# %bb.13:
movq %r15, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_15
# %bb.14:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 32(%rsp)
movq %rcx, 24(%rsp)
movq %rdx, (%rsp)
leaq 32(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8vect_addPiS_S_, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_15:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_16
# %bb.17:
movq 40(%rsp), %rsi
movl $31364, %edx # imm = 0x7A84
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB2_21
# %bb.18: # %.preheader.preheader
xorl %r15d, %r15d
jmp .LBB2_19
.p2align 4, 0x90
.LBB2_24: # in Loop: Header=BB2_19 Depth=1
movq %r14, %rdi
movq %rax, %r12
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r12, %rax
.LBB2_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_19 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $7841, %r15 # imm = 0x1EA1
je .LBB2_26
.LBB2_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r14
testq %r14, %r14
je .LBB2_20
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_19 Depth=1
cmpb $0, 56(%r14)
je .LBB2_24
# %bb.23: # in Loop: Header=BB2_19 Depth=1
movzbl 67(%r14), %ecx
jmp .LBB2_25
.LBB2_26:
movq 72(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_27
# %bb.28:
movq 64(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_29
# %bb.30:
movq 40(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB2_31
# %bb.32:
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_20:
.cfi_def_cfa_offset 160
callq _ZSt16__throw_bad_castv
.LBB2_1:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $49, %ecx
jmp .LBB2_2
.LBB2_4:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $50, %ecx
jmp .LBB2_2
.LBB2_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $51, %ecx
jmp .LBB2_2
.LBB2_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $61, %ecx
jmp .LBB2_2
.LBB2_16:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $66, %ecx
jmp .LBB2_2
.LBB2_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $69, %ecx
jmp .LBB2_2
.LBB2_27:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $72, %ecx
jmp .LBB2_2
.LBB2_29:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $73, %ecx
jmp .LBB2_2
.LBB2_31:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movl $.L.str.1, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl $74, %ecx
.LBB2_2:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9vect_fillPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8vect_addPiS_S_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9vect_fillPi,@object # @_Z9vect_fillPi
.section .rodata,"a",@progbits
.globl _Z9vect_fillPi
.p2align 3, 0x0
_Z9vect_fillPi:
.quad _Z24__device_stub__vect_fillPi
.size _Z9vect_fillPi, 8
.type _Z8vect_addPiS_S_,@object # @_Z8vect_addPiS_S_
.globl _Z8vect_addPiS_S_
.p2align 3, 0x0
_Z8vect_addPiS_S_:
.quad _Z23__device_stub__vect_addPiS_S_
.size _Z8vect_addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error %s at line %d in file %s\n"
.size .L.str, 32
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jdobes/apvg/master/project1/main.hip"
.size .L.str.1, 94
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9vect_fillPi"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z8vect_addPiS_S_"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__vect_fillPi
.addrsig_sym _Z23__device_stub__vect_addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9vect_fillPi
.addrsig_sym _Z8vect_addPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define TILE_DIM 1024
template<typename T>
__device__ void math_stdd(const T* vector, double* result, const int length) {
__shared__ double threadSum[TILE_DIM];
__shared__ double threadSquareSum[TILE_DIM];
int index = threadIdx.x;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
double sum = 0;
double squareSum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
double value = vector[valueIndex];
sum += value;
squareSum += value * value;
}
}
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
double value = threadSum[valueIndex];
double square = threadSquareSum[valueIndex];
sum += value;
squareSum += square;
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
}
}
}
if (index == 0) {
result[0] = sqrt((squareSum - (sum * sum) / length) / length);
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define TILE_DIM 1024
template<typename T>
__device__ void math_stdd(const T* vector, double* result, const int length) {
__shared__ double threadSum[TILE_DIM];
__shared__ double threadSquareSum[TILE_DIM];
int index = threadIdx.x;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
double sum = 0;
double squareSum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
double value = vector[valueIndex];
sum += value;
squareSum += value * value;
}
}
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
double value = threadSum[valueIndex];
double square = threadSquareSum[valueIndex];
sum += value;
squareSum += square;
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
}
}
}
if (index == 0) {
result[0] = sqrt((squareSum - (sum * sum) / length) / length);
}
} | .file "tmpxft_0016109c_00000000-6_Stdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define TILE_DIM 1024
template<typename T>
__device__ void math_stdd(const T* vector, double* result, const int length) {
__shared__ double threadSum[TILE_DIM];
__shared__ double threadSquareSum[TILE_DIM];
int index = threadIdx.x;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
double sum = 0;
double squareSum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
double value = vector[valueIndex];
sum += value;
squareSum += value * value;
}
}
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
double value = threadSum[valueIndex];
double square = threadSquareSum[valueIndex];
sum += value;
squareSum += square;
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
}
}
}
if (index == 0) {
result[0] = sqrt((squareSum - (sum * sum) / length) / length);
}
} | #include <hip/hip_runtime.h>
#define TILE_DIM 1024
template<typename T>
__device__ void math_stdd(const T* vector, double* result, const int length) {
__shared__ double threadSum[TILE_DIM];
__shared__ double threadSquareSum[TILE_DIM];
int index = threadIdx.x;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
double sum = 0;
double squareSum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
double value = vector[valueIndex];
sum += value;
squareSum += value * value;
}
}
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
double value = threadSum[valueIndex];
double square = threadSquareSum[valueIndex];
sum += value;
squareSum += square;
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
}
}
}
if (index == 0) {
result[0] = sqrt((squareSum - (sum * sum) / length) / length);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define TILE_DIM 1024
template<typename T>
__device__ void math_stdd(const T* vector, double* result, const int length) {
__shared__ double threadSum[TILE_DIM];
__shared__ double threadSquareSum[TILE_DIM];
int index = threadIdx.x;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
double sum = 0;
double squareSum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
double value = vector[valueIndex];
sum += value;
squareSum += value * value;
}
}
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
double value = threadSum[valueIndex];
double square = threadSquareSum[valueIndex];
sum += value;
squareSum += square;
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
}
}
}
if (index == 0) {
result[0] = sqrt((squareSum - (sum * sum) / length) / length);
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define TILE_DIM 1024
template<typename T>
__device__ void math_stdd(const T* vector, double* result, const int length) {
__shared__ double threadSum[TILE_DIM];
__shared__ double threadSquareSum[TILE_DIM];
int index = threadIdx.x;
int partLength = (length + TILE_DIM - 1) / TILE_DIM;
double sum = 0;
double squareSum = 0;
for (int i = 0; i < partLength; i++) {
int valueIndex = i * TILE_DIM + index;
if (valueIndex < length) {
double value = vector[valueIndex];
sum += value;
squareSum += value * value;
}
}
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
for (int d = 1; d < TILE_DIM && d < length; d <<= 1) {
__syncthreads();
if (index % (d << 1) == 0) {
int valueIndex = index + d;
if (valueIndex < TILE_DIM) {
double value = threadSum[valueIndex];
double square = threadSquareSum[valueIndex];
sum += value;
squareSum += square;
threadSum[index] = sum;
threadSquareSum[index] = squareSum;
}
}
}
if (index == 0) {
result[0] = sqrt((squareSum - (sum * sum) / length) / length);
}
} | .text
.file "Stdd.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016109c_00000000-6_Stdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Stdd.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
//Author: Adriel Kim
//6-27-2020
//Updated 7-5-2020
/*
Desc: Basic 2D matrix operations - element-wise addition, subtraction, multiplication, and division.
To do:
- Use vector instead of array?
- Be able to test for varying sizes of images. (For now we manually define with constant N)
- Add timer to compare CPU and GPU implementations
- Double check if all memory is freed
- Optimize by eliminating redundant calculations
- Test code on department servers
*/
//define imin(a,b) (a<b?a:b)//example of ternary operator in c++
//4176,2048
#define R 4176
#define C 2048
#define N (R*C)//# of elements in matrices
const int threadsPerBlock = 1024;//threads in a block. A chunk that shares the same shared memory.
const int blocksPerGrid = 8352;//imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);//this will be our output array size for sumKernel.
using namespace std;
cudaError_t matrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation, float* kernel_runtime, float* GPU_transfer_time);
void CPUMatrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
//any advantages with mapping directly to strucutre of matrix? We're just representing 2D matrix using 1D array...
//it would be difficult to do the above since we want the operations to occur over abitrarily large matrices
//this can definitely be optimzied by elminating redundant calculations
//---------------------------------------------------------------------------------
__global__ void matrixAddKernel(double *c, const double *a, const double *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N) {
c[tid] = a[tid] + b[tid];
//adds total number of running threads to tid, the current index.
tid += blockDim.x * gridDim.x;
}
} | code for sm_80
Function : _Z15matrixAddKernelPdPKdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x827fff, PT ; /* 0x00827fff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0209 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x828000, PT ; /* 0x008280000000780c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*0110*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b04 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
//Author: Adriel Kim
//6-27-2020
//Updated 7-5-2020
/*
Desc: Basic 2D matrix operations - element-wise addition, subtraction, multiplication, and division.
To do:
- Use vector instead of array?
- Be able to test for varying sizes of images. (For now we manually define with constant N)
- Add timer to compare CPU and GPU implementations
- Double check if all memory is freed
- Optimize by eliminating redundant calculations
- Test code on department servers
*/
//define imin(a,b) (a<b?a:b)//example of ternary operator in c++
//4176,2048
#define R 4176
#define C 2048
#define N (R*C)//# of elements in matrices
const int threadsPerBlock = 1024;//threads in a block. A chunk that shares the same shared memory.
const int blocksPerGrid = 8352;//imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);//this will be our output array size for sumKernel.
using namespace std;
cudaError_t matrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation, float* kernel_runtime, float* GPU_transfer_time);
void CPUMatrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
//any advantages with mapping directly to strucutre of matrix? We're just representing 2D matrix using 1D array...
//it would be difficult to do the above since we want the operations to occur over abitrarily large matrices
//this can definitely be optimzied by elminating redundant calculations
//---------------------------------------------------------------------------------
__global__ void matrixAddKernel(double *c, const double *a, const double *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N) {
c[tid] = a[tid] + b[tid];
//adds total number of running threads to tid, the current index.
tid += blockDim.x * gridDim.x;
}
} | .file "tmpxft_000d315e_00000000-6_matrixAddKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_
.type _Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_, @function
_Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddKernelPdPKdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_, .-_Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_
.globl _Z15matrixAddKernelPdPKdS1_
.type _Z15matrixAddKernelPdPKdS1_, @function
_Z15matrixAddKernelPdPKdS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15matrixAddKernelPdPKdS1_, .-_Z15matrixAddKernelPdPKdS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrixAddKernelPdPKdS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddKernelPdPKdS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
//Author: Adriel Kim
//6-27-2020
//Updated 7-5-2020
/*
Desc: Basic 2D matrix operations - element-wise addition, subtraction, multiplication, and division.
To do:
- Use vector instead of array?
- Be able to test for varying sizes of images. (For now we manually define with constant N)
- Add timer to compare CPU and GPU implementations
- Double check if all memory is freed
- Optimize by eliminating redundant calculations
- Test code on department servers
*/
//define imin(a,b) (a<b?a:b)//example of ternary operator in c++
//4176,2048
#define R 4176
#define C 2048
#define N (R*C)//# of elements in matrices
const int threadsPerBlock = 1024;//threads in a block. A chunk that shares the same shared memory.
const int blocksPerGrid = 8352;//imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);//this will be our output array size for sumKernel.
using namespace std;
cudaError_t matrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation, float* kernel_runtime, float* GPU_transfer_time);
void CPUMatrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
//any advantages with mapping directly to strucutre of matrix? We're just representing 2D matrix using 1D array...
//it would be difficult to do the above since we want the operations to occur over abitrarily large matrices
//this can definitely be optimzied by elminating redundant calculations
//---------------------------------------------------------------------------------
__global__ void matrixAddKernel(double *c, const double *a, const double *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N) {
c[tid] = a[tid] + b[tid];
//adds total number of running threads to tid, the current index.
tid += blockDim.x * gridDim.x;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
//Author: Adriel Kim
//6-27-2020
//Updated 7-5-2020
/*
Desc: Basic 2D matrix operations - element-wise addition, subtraction, multiplication, and division.
To do:
- Use vector instead of array?
- Be able to test for varying sizes of images. (For now we manually define with constant N)
- Add timer to compare CPU and GPU implementations
- Double check if all memory is freed
- Optimize by eliminating redundant calculations
- Test code on department servers
*/
//define imin(a,b) (a<b?a:b)//example of ternary operator in c++
//4176,2048
#define R 4176
#define C 2048
#define N (R*C)//# of elements in matrices
const int threadsPerBlock = 1024;//threads in a block. A chunk that shares the same shared memory.
const int blocksPerGrid = 8352;//imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);//this will be our output array size for sumKernel.
using namespace std;
hipError_t matrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation, float* kernel_runtime, float* GPU_transfer_time);
void CPUMatrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
//any advantages with mapping directly to strucutre of matrix? We're just representing 2D matrix using 1D array...
//it would be difficult to do the above since we want the operations to occur over abitrarily large matrices
//this can definitely be optimzied by elminating redundant calculations
//---------------------------------------------------------------------------------
__global__ void matrixAddKernel(double *c, const double *a, const double *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N) {
c[tid] = a[tid] + b[tid];
//adds total number of running threads to tid, the current index.
tid += blockDim.x * gridDim.x;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//Author: Adriel Kim
//6-27-2020
//Updated 7-5-2020
/*
Desc: Basic 2D matrix operations - element-wise addition, subtraction, multiplication, and division.
To do:
- Use vector instead of array?
- Be able to test for varying sizes of images. (For now we manually define with constant N)
- Add timer to compare CPU and GPU implementations
- Double check if all memory is freed
- Optimize by eliminating redundant calculations
- Test code on department servers
*/
//define imin(a,b) (a<b?a:b)//example of ternary operator in c++
//4176,2048
#define R 4176
#define C 2048
#define N (R*C)//# of elements in matrices
const int threadsPerBlock = 1024;//threads in a block. A chunk that shares the same shared memory.
const int blocksPerGrid = 8352;//imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);//this will be our output array size for sumKernel.
using namespace std;
hipError_t matrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation, float* kernel_runtime, float* GPU_transfer_time);
void CPUMatrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
//any advantages with mapping directly to strucutre of matrix? We're just representing 2D matrix using 1D array...
//it would be difficult to do the above since we want the operations to occur over abitrarily large matrices
//this can definitely be optimzied by elminating redundant calculations
//---------------------------------------------------------------------------------
__global__ void matrixAddKernel(double *c, const double *a, const double *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N) {
c[tid] = a[tid] + b[tid];
//adds total number of running threads to tid, the current index.
tid += blockDim.x * gridDim.x;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixAddKernelPdPKdS1_
.globl _Z15matrixAddKernelPdPKdS1_
.p2align 8
.type _Z15matrixAddKernelPdPKdS1_,@function
_Z15matrixAddKernelPdPKdS1_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x828000, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x827fff, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixAddKernelPdPKdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixAddKernelPdPKdS1_, .Lfunc_end0-_Z15matrixAddKernelPdPKdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixAddKernelPdPKdS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixAddKernelPdPKdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
//Author: Adriel Kim
//6-27-2020
//Updated 7-5-2020
/*
Desc: Basic 2D matrix operations - element-wise addition, subtraction, multiplication, and division.
To do:
- Use vector instead of array?
- Be able to test for varying sizes of images. (For now we manually define with constant N)
- Add timer to compare CPU and GPU implementations
- Double check if all memory is freed
- Optimize by eliminating redundant calculations
- Test code on department servers
*/
//define imin(a,b) (a<b?a:b)//example of ternary operator in c++
//4176,2048
#define R 4176
#define C 2048
#define N (R*C)//# of elements in matrices
const int threadsPerBlock = 1024;//threads in a block. A chunk that shares the same shared memory.
const int blocksPerGrid = 8352;//imin(32, (N + threadsPerBlock - 1) / threadsPerBlock);//this will be our output array size for sumKernel.
using namespace std;
hipError_t matrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation, float* kernel_runtime, float* GPU_transfer_time);
void CPUMatrixOperation(double* c, const double* a, const double* b, unsigned int arrSize, int operation);
long long start_timer();
long long stop_timer(long long start_time, const char *name);
//any advantages with mapping directly to strucutre of matrix? We're just representing 2D matrix using 1D array...
//it would be difficult to do the above since we want the operations to occur over abitrarily large matrices
//this can definitely be optimzied by elminating redundant calculations
//---------------------------------------------------------------------------------
__global__ void matrixAddKernel(double *c, const double *a, const double *b) {
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N) {
c[tid] = a[tid] + b[tid];
//adds total number of running threads to tid, the current index.
tid += blockDim.x * gridDim.x;
}
} | .text
.file "matrixAddKernel.hip"
.globl _Z30__device_stub__matrixAddKernelPdPKdS1_ # -- Begin function _Z30__device_stub__matrixAddKernelPdPKdS1_
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddKernelPdPKdS1_,@function
_Z30__device_stub__matrixAddKernelPdPKdS1_: # @_Z30__device_stub__matrixAddKernelPdPKdS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddKernelPdPKdS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixAddKernelPdPKdS1_, .Lfunc_end0-_Z30__device_stub__matrixAddKernelPdPKdS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddKernelPdPKdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixAddKernelPdPKdS1_,@object # @_Z15matrixAddKernelPdPKdS1_
.section .rodata,"a",@progbits
.globl _Z15matrixAddKernelPdPKdS1_
.p2align 3, 0x0
_Z15matrixAddKernelPdPKdS1_:
.quad _Z30__device_stub__matrixAddKernelPdPKdS1_
.size _Z15matrixAddKernelPdPKdS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrixAddKernelPdPKdS1_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixAddKernelPdPKdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixAddKernelPdPKdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15matrixAddKernelPdPKdS1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x827fff, PT ; /* 0x00827fff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R9, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff097435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R9, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0209 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R9.reuse, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x0c0fe400078e0209 */
/*00a0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1b00 */
/*00b0*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1b00 */
/*00c0*/ IMAD.WIDE R8, R0, R9, c[0x0][0x160] ; /* 0x0000580000087625 */
/* 0x000fe200078e0209 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x828000, PT ; /* 0x008280000000780c */
/* 0x000fe20003f06270 */
/*0100*/ DADD R6, R4, R2 ; /* 0x0000000004067229 */
/* 0x004e0e0000000002 */
/*0110*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x0011ea000c101b04 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15matrixAddKernelPdPKdS1_
.globl _Z15matrixAddKernelPdPKdS1_
.p2align 8
.type _Z15matrixAddKernelPdPKdS1_,@function
_Z15matrixAddKernelPdPKdS1_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x828000, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x827fff, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15matrixAddKernelPdPKdS1_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15matrixAddKernelPdPKdS1_, .Lfunc_end0-_Z15matrixAddKernelPdPKdS1_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15matrixAddKernelPdPKdS1_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15matrixAddKernelPdPKdS1_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d315e_00000000-6_matrixAddKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_
.type _Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_, @function
_Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15matrixAddKernelPdPKdS1_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_, .-_Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_
.globl _Z15matrixAddKernelPdPKdS1_
.type _Z15matrixAddKernelPdPKdS1_, @function
_Z15matrixAddKernelPdPKdS1_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z15matrixAddKernelPdPKdS1_PdPKdS1_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z15matrixAddKernelPdPKdS1_, .-_Z15matrixAddKernelPdPKdS1_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z15matrixAddKernelPdPKdS1_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z15matrixAddKernelPdPKdS1_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixAddKernel.hip"
.globl _Z30__device_stub__matrixAddKernelPdPKdS1_ # -- Begin function _Z30__device_stub__matrixAddKernelPdPKdS1_
.p2align 4, 0x90
.type _Z30__device_stub__matrixAddKernelPdPKdS1_,@function
_Z30__device_stub__matrixAddKernelPdPKdS1_: # @_Z30__device_stub__matrixAddKernelPdPKdS1_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15matrixAddKernelPdPKdS1_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z30__device_stub__matrixAddKernelPdPKdS1_, .Lfunc_end0-_Z30__device_stub__matrixAddKernelPdPKdS1_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15matrixAddKernelPdPKdS1_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z15matrixAddKernelPdPKdS1_,@object # @_Z15matrixAddKernelPdPKdS1_
.section .rodata,"a",@progbits
.globl _Z15matrixAddKernelPdPKdS1_
.p2align 3, 0x0
_Z15matrixAddKernelPdPKdS1_:
.quad _Z30__device_stub__matrixAddKernelPdPKdS1_
.size _Z15matrixAddKernelPdPKdS1_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z15matrixAddKernelPdPKdS1_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z30__device_stub__matrixAddKernelPdPKdS1_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z15matrixAddKernelPdPKdS1_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x);
}
int main()
{
int N = 10;
loop<<<1, N>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z4loopv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0060*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0070*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0002a60000000a00 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0090*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0013e80000100800 */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fc60000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x004fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x);
}
int main()
{
int N = 10;
loop<<<1, N>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_00125700_00000000-6_01-single-block-loop-solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4loopvv
.type _Z22__device_stub__Z4loopvv, @function
_Z22__device_stub__Z4loopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4loopvv, .-_Z22__device_stub__Z4loopvv
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4loopv, .-_Z4loopv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4loopvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x);
}
int main()
{
int N = 10;
loop<<<1, N>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x);
}
int main()
{
int N = 10;
loop<<<1, N>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void loop()
{
printf("This is iteration number %d\n", threadIdx.x);
}
int main()
{
int N = 10;
loop<<<1, N>>>();
hipDeviceSynchronize();
} | .text
.file "01-single-block-loop-solution.hip"
.globl _Z19__device_stub__loopv # -- Begin function _Z19__device_stub__loopv
.p2align 4, 0x90
.type _Z19__device_stub__loopv,@function
_Z19__device_stub__loopv: # @_Z19__device_stub__loopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__loopv, .Lfunc_end0-_Z19__device_stub__loopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4loopv,@object # @_Z4loopv
.section .rodata,"a",@progbits
.globl _Z4loopv
.p2align 3, 0x0
_Z4loopv:
.quad _Z19__device_stub__loopv
.size _Z4loopv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4loopv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00125700_00000000-6_01-single-block-loop-solution.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22__device_stub__Z4loopvv
.type _Z22__device_stub__Z4loopvv, @function
_Z22__device_stub__Z4loopvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z4loopv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z22__device_stub__Z4loopvv, .-_Z22__device_stub__Z4loopvv
.globl _Z4loopv
.type _Z4loopv, @function
_Z4loopv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z22__device_stub__Z4loopvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4loopv, .-_Z4loopv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $10, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z22__device_stub__Z4loopvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4loopv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4loopv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "01-single-block-loop-solution.hip"
.globl _Z19__device_stub__loopv # -- Begin function _Z19__device_stub__loopv
.p2align 4, 0x90
.type _Z19__device_stub__loopv,@function
_Z19__device_stub__loopv: # @_Z19__device_stub__loopv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z19__device_stub__loopv, .Lfunc_end0-_Z19__device_stub__loopv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 9(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z4loopv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4loopv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4loopv,@object # @_Z4loopv
.section .rodata,"a",@progbits
.globl _Z4loopv
.p2align 3, 0x0
_Z4loopv:
.quad _Z19__device_stub__loopv
.size _Z4loopv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4loopv"
.size .L__unnamed_1, 9
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__loopv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4loopv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
*
* Matrix Multiplication - CUDA for GPUs
*
* CS3210
*
**/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <assert.h>
int size;
#define BLOCK_SIZE 32
typedef struct
{
float ** element;
} matrix;
long long wall_clock_time()
{
#ifdef __linux__
struct timespec tp;
clock_gettime(CLOCK_REALTIME, &tp);
return (long long)(tp.tv_nsec + (long long)tp.tv_sec * 1000000000ll);
#else
struct timeval tv;
gettimeofday(&tv, NULL);
return (long long)(tv.tv_usec * 1000 + (long long)tv.tv_sec * 1000000000ll);
#endif
}
/**
* Allocates memory for a matrix of size SIZE
* The memory is allocated row-major order, i.e.
* elements from the same row are allocated at contiguous
* memory addresses.
**/
void allocate_matrix(matrix* m)
{
int i;
cudaError_t rc;
// allocate array for all the rows
rc = cudaMallocManaged((void**)&(m->element), sizeof(float*) * size);
if (rc != cudaSuccess)
{
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(rc));
exit(1);
}
// allocate an array for each row of the matrix
for (i = 0; i < size; i++)
{
rc = cudaMallocManaged((void**)&(m->element[i]), sizeof(float) * size);
if (rc != cudaSuccess)
{
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(rc));
exit(1);
}
}
}
/**
* Free the memory allocated for a matrix.
**/
void free_matrix(matrix* m) {
int i;
for (i = 0; i < size; i++)
cudaFree(m->element[i]);
cudaFree(m->element);
}
/**
* Initializes the elements of the matrix with
* random values between 0 and 9
**/
void init_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = rand() % 10;
}
}
/**
* Initializes the elements of the matrix with
* element 0.
**/
void init_matrix_zero(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = 0.0;
}
}
/**
* Multiplies matrix @a with matrix @b storing
* the result in matrix @result
*
* The multiplication algorithm is the O(n^3)
* algorithm
*/
void mm(matrix a, matrix b, matrix result)
{
int i, j, k;
// Do the multiplication
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
for(k = 0; k < size; k++)
result.element[i][j] += a.element[i][k] * b.element[k][j];
}
/**
* Each kernel computes the result element (i,j).
*/
__global__ void mm_kernel(matrix a, matrix b, matrix result, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int row = threadIdx.y;
int col = threadIdx.x;
int k, m;
int kmax = BLOCK_SIZE + col;
int secondRow = row + BLOCK_SIZE;
int secondCol = col + BLOCK_SIZE;
if (i >= size || j >= size)
return;
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE * 2];
__shared__ float Bs[BLOCK_SIZE * 2][BLOCK_SIZE];
float C_res = 0.0f;
for (m = 0; m < size; m += BLOCK_SIZE) {
As[row][col] = a.element[j][m + threadIdx.x];
As[row][secondCol] = As[row][col];
Bs[row][col] = b.element[m + threadIdx.y][i];
Bs[secondRow][col] = Bs[row][col];
__syncthreads();
for(k = threadIdx.x; k < kmax; k++) {
C_res += As[row][k] * Bs[k][col];
}
__syncthreads();
}
result.element[j][i] = C_res;
}
void print_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
{
printf("row %4d: ", i);
for (j = 0; j < size; j++)
printf("%6.2f ", m.element[i][j]);
printf("\n");
}
}
void work()
{
matrix a, b, result1, result2;
long long before, after;
int correct, i, j, dim;
cudaError_t rc;
// Allocate memory for matrices
allocate_matrix(&a);
allocate_matrix(&b);
allocate_matrix(&result1);
allocate_matrix(&result2);
// Initialize matrix elements
init_matrix(a);
init_matrix(b);
// Perform sequential matrix multiplication
before = wall_clock_time();
mm(a, b, result1);
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on CPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// Perform CUDA matrix multiplication
dim3 block(32, 32); // a block of 32 x 32 CUDA threads
dim = (size % 32 == 0) ? size / 32 : size / 32 + 1;
dim3 grid(dim, dim); // a grid of CUDA thread blocks
before = wall_clock_time();
mm_kernel<<<grid, block>>>(a, b, result2, size);
cudaDeviceSynchronize();
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on GPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// was there any error?
rc = cudaGetLastError();
if (rc != cudaSuccess)
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
// Compare the results
correct = 1;
for (i = 0; correct && i < size; i++)
for (j = 0; j < size; j++)
if (result1.element[i][j] != result2.element[i][j]) {
correct = 0;
break;
}
if (correct)
printf("The result matrices are identical!\n");
else
printf("Difference in result matrices at element (%d, %d)!\n", i, j);
free_matrix(&a);
free_matrix(&b);
free_matrix(&result1);
free_matrix(&result2);
}
int main(int argc, char ** argv)
{
srand(0);
printf("Usage: %s <size>\n", argv[0]);
if (argc >= 2)
size = atoi(argv[1]);
else
size = 1024;
fprintf(stderr,"Sequential matrix multiplication of size %d\n", size);
// Multiply the matrices
work();
return 0;
} | code for sm_80
Function : _Z9mm_kernel6matrixS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R5, c[0x0][0x4], R2 ; /* 0x0000010005047a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x178], P0 ; /* 0x00005e0004007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fd60000011404 */
/*00d0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*00e0*/ @!P0 BRA 0xc00 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R7, R0.reuse, 0x20, RZ ; /* 0x0000002000077810 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD.SHL.U32 R13, R0.reuse, 0x4, RZ ; /* 0x00000004000d7824 */
/* 0x040fe200078e00ff */
/*0110*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff067212 */
/* 0x000fe400078e33ff */
/*0140*/ IMNMX R15, R7, R8, !PT ; /* 0x00000008070f7217 */
/* 0x000fe40007800200 */
/*0150*/ LEA R14, R2, 0x2000, 0x7 ; /* 0x00002000020e7811 */
/* 0x000fe400078e38ff */
/*0160*/ IADD3 R6, R15.reuse, R6, RZ ; /* 0x000000060f067210 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.IADD R22, R15, 0x1, -R0 ; /* 0x000000010f167824 */
/* 0x000fe200078e0a00 */
/*0180*/ LEA R18, R0, 0x2000, 0x7 ; /* 0x0000200000127811 */
/* 0x000fe200078e38ff */
/*0190*/ IMAD.IADD R11, R13, 0x1, R14 ; /* 0x000000010d0b7824 */
/* 0x000fe200078e020e */
/*01a0*/ SHF.R.S32.HI R16, RZ, 0x1f, R3 ; /* 0x0000001fff107819 */
/* 0x000fc40000011403 */
/*01b0*/ LEA R12, P0, R4, c[0x0][0x160], 0x3 ; /* 0x00005800040c7a11 */
/* 0x000fe200078018ff */
/*01c0*/ IMAD.IADD R18, R13.reuse, 0x1, R18 ; /* 0x000000010d127824 */
/* 0x040fe200078e0212 */
/*01d0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f46070 */
/*01e0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*01f0*/ LEA R19, R2, R13, 0x8 ; /* 0x0000000d02137211 */
/* 0x000fe400078e40ff */
/*0200*/ IADD3 R20, R13, 0x2100, RZ ; /* 0x000021000d147810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R9, R0.reuse, 0x2, RZ ; /* 0x0000000200097810 */
/* 0x040fe40007ffe0ff */
/*0220*/ IADD3 R24, R0, 0x3, RZ ; /* 0x0000000300187810 */
/* 0x000fc40007ffe0ff */
/*0230*/ LEA R10, R2, 0x8, 0x8 ; /* 0x00000008020a7811 */
/* 0x000fe400078e40ff */
/*0240*/ SHF.L.U64.HI R21, R3, 0x2, R16 ; /* 0x0000000203157819 */
/* 0x000fe40000010210 */
/*0250*/ LEA.HI.X R13, R4, c[0x0][0x164], R5, 0x3, P0 ; /* 0x00005900040d7a11 */
/* 0x000fe400000f1c05 */
/*0260*/ LOP3.LUT R22, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316167812 */
/* 0x000fe400078ec0ff */
/*0270*/ MOV R27, 0x8 ; /* 0x00000008001b7802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.IADD R26, R2, 0x1, R23 ; /* 0x00000001021a7824 */
/* 0x000fe200078e0217 */
/*0290*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea6000c1e1b00 */
/*02a0*/ IMAD.WIDE.U32 R26, R26, R27, c[0x0][0x168] ; /* 0x00005a001a1a7625 */
/* 0x000fca00078e001b */
/*02b0*/ LDG.E.64 R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x000ee2000c1e1b00 */
/*02c0*/ IMAD.IADD R25, R0, 0x1, R23 ; /* 0x0000000100197824 */
/* 0x000fc800078e0217 */
/*02d0*/ IMAD.WIDE.U32 R16, R25, 0x4, R16 ; /* 0x0000000419107825 */
/* 0x004fcc00078e0010 */
/*02e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ LEA R14, P0, R3, R14, 0x2 ; /* 0x0000000e030e7211 */
/* 0x008fc800078010ff */
/*0300*/ IADD3.X R15, R15, R21, RZ, P0, !PT ; /* 0x000000150f0f7210 */
/* 0x000fca00007fe4ff */
/*0310*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0320*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*0330*/ BSSY B0, 0x4d0 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R23, R23, 0x20, RZ ; /* 0x0000002017177810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD.MOV.U32 R26, RZ, RZ, R0 ; /* 0x000000ffff1a7224 */
/* 0x000fc600078e0000 */
/*0360*/ ISETP.GE.AND P1, PT, R23, c[0x0][0x178], PT ; /* 0x00005e0017007a0c */
/* 0x000fe20003f26270 */
/*0370*/ STS [R19], R16 ; /* 0x0000001013007388 */
/* 0x0041e80000000800 */
/*0380*/ STS [R19+0x80], R16 ; /* 0x0000801013007388 */
/* 0x0001e80000000800 */
/*0390*/ STS [R11], R14 ; /* 0x0000000e0b007388 */
/* 0x0081e80000000800 */
/*03a0*/ STS [R11+0x1000], R14 ; /* 0x0010000e0b007388 */
/* 0x0001e80000000800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03c0*/ @!P0 BRA 0x4c0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*03d0*/ LDS R15, [R18] ; /* 0x00000000120f7984 */
/* 0x001fe20000000800 */
/*03e0*/ ISETP.NE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fc40003f05270 */
/*03f0*/ MOV R26, R8 ; /* 0x00000008001a7202 */
/* 0x000fe20000000f00 */
/*0400*/ LDS R14, [R19] ; /* 0x00000000130e7984 */
/* 0x000e240000000800 */
/*0410*/ FFMA R6, R15, R14, R6 ; /* 0x0000000e0f067223 */
/* 0x001fd00000000006 */
/*0420*/ @!P0 BRA 0x4c0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.NE.AND P0, PT, R22, 0x2, PT ; /* 0x000000021600780c */
/* 0x000fe20003f05270 */
/*0440*/ LDS R15, [R18+0x80] ; /* 0x00008000120f7984 */
/* 0x000fe20000000800 */
/*0450*/ IMAD.MOV.U32 R26, RZ, RZ, R9 ; /* 0x000000ffff1a7224 */
/* 0x000fc600078e0009 */
/*0460*/ LDS R14, [R19+0x4] ; /* 0x00000400130e7984 */
/* 0x000e300000000800 */
/*0470*/ @P0 LDS R17, [R18+0x100] ; /* 0x0001000012110984 */
/* 0x000fe20000000800 */
/*0480*/ @P0 MOV R26, R24 ; /* 0x00000018001a0202 */
/* 0x000fc60000000f00 */
/*0490*/ @P0 LDS R16, [R19+0x8] ; /* 0x0000080013100984 */
/* 0x000e620000000800 */
/*04a0*/ FFMA R6, R15, R14, R6 ; /* 0x0000000e0f067223 */
/* 0x001fc80000000006 */
/*04b0*/ @P0 FFMA R6, R17, R16, R6 ; /* 0x0000001011060223 */
/* 0x002fe40000000006 */
/*04c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*04d0*/ BSSY B0, 0xbe0 ; /* 0x0000070000007945 */
/* 0x000fe20003800000 */
/*04e0*/ @!P2 BRA 0xbd0 ; /* 0x000006e00000a947 */
/* 0x000fea0003800000 */
/*04f0*/ IMAD.IADD R14, R7, 0x1, -R26 ; /* 0x00000001070e7824 */
/* 0x000fe200078e0a1a */
/*0500*/ BSSY B1, 0x8e0 ; /* 0x000003d000017945 */
/* 0x000fe20003800000 */
/*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0520*/ LEA R15, R26, R20, 0x7 ; /* 0x000000141a0f7211 */
/* 0x000fe400078e38ff */
/*0530*/ ISETP.GT.AND P3, PT, R14, 0xc, PT ; /* 0x0000000c0e00780c */
/* 0x000fe20003f64270 */
/*0540*/ IMAD R14, R26, 0x4, R10 ; /* 0x000000041a0e7824 */
/* 0x000fd800078e020a */
/*0550*/ @!P3 BRA 0x8d0 ; /* 0x000003700000b947 */
/* 0x000fea0003800000 */
/*0560*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0570*/ IADD3 R17, R0, 0x14, RZ ; /* 0x0000001400117810 */
/* 0x000fe40007ffe0ff */
/*0580*/ LDS R25, [R15+-0x100] ; /* 0xffff00000f197984 */
/* 0x000fe20000000800 */
/*0590*/ IADD3 R26, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fc60007ffe0ff */
/*05a0*/ LDS R16, [R14+-0x8] ; /* 0xfffff8000e107984 */
/* 0x000e220000000800 */
/*05b0*/ ISETP.GE.AND P3, PT, R26, R17, PT ; /* 0x000000111a00720c */
/* 0x000fe20003f66270 */
/*05c0*/ FFMA R16, R25, R16, R6 ; /* 0x0000001019107223 */
/* 0x001fe40000000006 */
/*05d0*/ LDS R25, [R15+-0x80] ; /* 0xffff80000f197984 */
/* 0x000fe80000000800 */
/*05e0*/ LDS R6, [R14+-0x4] ; /* 0xfffffc000e067984 */
/* 0x000e240000000800 */
/*05f0*/ FFMA R6, R25, R6, R16 ; /* 0x0000000619067223 */
/* 0x001fc40000000010 */
/*0600*/ LDS R25, [R15] ; /* 0x000000000f197984 */
/* 0x000fe80000000800 */
/*0610*/ LDS R16, [R14] ; /* 0x000000000e107984 */
/* 0x000e240000000800 */
/*0620*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0630*/ LDS R25, [R15+0x80] ; /* 0x000080000f197984 */
/* 0x000fe80000000800 */
/*0640*/ LDS R16, [R14+0x4] ; /* 0x000004000e107984 */
/* 0x000e240000000800 */
/*0650*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*0660*/ LDS R25, [R15+0x100] ; /* 0x000100000f197984 */
/* 0x000fe80000000800 */
/*0670*/ LDS R16, [R14+0x8] ; /* 0x000008000e107984 */
/* 0x000e240000000800 */
/*0680*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0690*/ LDS R25, [R15+0x180] ; /* 0x000180000f197984 */
/* 0x000fe80000000800 */
/*06a0*/ LDS R16, [R14+0xc] ; /* 0x00000c000e107984 */
/* 0x000e240000000800 */
/*06b0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*06c0*/ LDS R25, [R15+0x200] ; /* 0x000200000f197984 */
/* 0x000fe80000000800 */
/*06d0*/ LDS R16, [R14+0x10] ; /* 0x000010000e107984 */
/* 0x000e240000000800 */
/*06e0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*06f0*/ LDS R25, [R15+0x280] ; /* 0x000280000f197984 */
/* 0x000fe80000000800 */
/*0700*/ LDS R16, [R14+0x14] ; /* 0x000014000e107984 */
/* 0x000e240000000800 */
/*0710*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*0720*/ LDS R25, [R15+0x300] ; /* 0x000300000f197984 */
/* 0x000fe80000000800 */
/*0730*/ LDS R16, [R14+0x18] ; /* 0x000018000e107984 */
/* 0x000e240000000800 */
/*0740*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0750*/ LDS R25, [R15+0x380] ; /* 0x000380000f197984 */
/* 0x000fe80000000800 */
/*0760*/ LDS R16, [R14+0x1c] ; /* 0x00001c000e107984 */
/* 0x000e240000000800 */
/*0770*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*0780*/ LDS R25, [R15+0x400] ; /* 0x000400000f197984 */
/* 0x000fe80000000800 */
/*0790*/ LDS R16, [R14+0x20] ; /* 0x000020000e107984 */
/* 0x000e240000000800 */
/*07a0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*07b0*/ LDS R25, [R15+0x480] ; /* 0x000480000f197984 */
/* 0x000fe80000000800 */
/*07c0*/ LDS R16, [R14+0x24] ; /* 0x000024000e107984 */
/* 0x000e240000000800 */
/*07d0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*07e0*/ LDS R25, [R15+0x500] ; /* 0x000500000f197984 */
/* 0x000fe80000000800 */
/*07f0*/ LDS R16, [R14+0x28] ; /* 0x000028000e107984 */
/* 0x000e240000000800 */
/*0800*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0810*/ LDS R25, [R15+0x580] ; /* 0x000580000f197984 */
/* 0x000fe80000000800 */
/*0820*/ LDS R16, [R14+0x2c] ; /* 0x00002c000e107984 */
/* 0x000e240000000800 */
/*0830*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*0840*/ LDS R25, [R15+0x600] ; /* 0x000600000f197984 */
/* 0x000fe80000000800 */
/*0850*/ LDS R16, [R14+0x30] ; /* 0x000030000e107984 */
/* 0x000e240000000800 */
/*0860*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0870*/ LDS R25, [R15+0x680] ; /* 0x000680000f197984 */
/* 0x0001e80000000800 */
/*0880*/ LDS R16, [R14+0x34] ; /* 0x000034000e107984 */
/* 0x0002a20000000800 */
/*0890*/ IADD3 R15, R15, 0x800, RZ ; /* 0x000008000f0f7810 */
/* 0x001fc40007ffe0ff */
/*08a0*/ IADD3 R14, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x002fe20007ffe0ff */
/*08b0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x004fe20000000006 */
/*08c0*/ @!P3 BRA 0x580 ; /* 0xfffffcb00000b947 */
/* 0x000fea000383ffff */
/*08d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R16, R7, -R26, RZ ; /* 0x8000001a07107210 */
/* 0x000fe20007ffe0ff */
/*08f0*/ BSSY B1, 0xaf0 ; /* 0x000001f000017945 */
/* 0x000fe60003800000 */
/*0900*/ ISETP.GT.AND P3, PT, R16, 0x4, PT ; /* 0x000000041000780c */
/* 0x000fda0003f64270 */
/*0910*/ @!P3 BRA 0xae0 ; /* 0x000001c00000b947 */
/* 0x000fea0003800000 */
/*0920*/ LDS R17, [R15+-0x100] ; /* 0xffff00000f117984 */
/* 0x000fe20000000800 */
/*0930*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0940*/ IADD3 R26, R26, 0x8, RZ ; /* 0x000000081a1a7810 */
/* 0x000fe20007ffe0ff */
/*0950*/ LDS R16, [R14+-0x8] ; /* 0xfffff8000e107984 */
/* 0x000e240000000800 */
/*0960*/ FFMA R16, R17, R16, R6 ; /* 0x0000001011107223 */
/* 0x001fe40000000006 */
/*0970*/ LDS R17, [R15+-0x80] ; /* 0xffff80000f117984 */
/* 0x000fe80000000800 */
/*0980*/ LDS R6, [R14+-0x4] ; /* 0xfffffc000e067984 */
/* 0x000e240000000800 */
/*0990*/ FFMA R6, R17, R6, R16 ; /* 0x0000000611067223 */
/* 0x001fc40000000010 */
/*09a0*/ LDS R17, [R15] ; /* 0x000000000f117984 */
/* 0x000fe80000000800 */
/*09b0*/ LDS R16, [R14] ; /* 0x000000000e107984 */
/* 0x000e240000000800 */
/*09c0*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fe40000000006 */
/*09d0*/ LDS R17, [R15+0x80] ; /* 0x000080000f117984 */
/* 0x000fe80000000800 */
/*09e0*/ LDS R16, [R14+0x4] ; /* 0x000004000e107984 */
/* 0x000e240000000800 */
/*09f0*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fc40000000006 */
/*0a00*/ LDS R17, [R15+0x100] ; /* 0x000100000f117984 */
/* 0x000fe80000000800 */
/*0a10*/ LDS R16, [R14+0x8] ; /* 0x000008000e107984 */
/* 0x000e240000000800 */
/*0a20*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fe40000000006 */
/*0a30*/ LDS R17, [R15+0x180] ; /* 0x000180000f117984 */
/* 0x000fe80000000800 */
/*0a40*/ LDS R16, [R14+0xc] ; /* 0x00000c000e107984 */
/* 0x000e240000000800 */
/*0a50*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fc40000000006 */
/*0a60*/ LDS R17, [R15+0x200] ; /* 0x000200000f117984 */
/* 0x000fe80000000800 */
/*0a70*/ LDS R16, [R14+0x10] ; /* 0x000010000e107984 */
/* 0x000e240000000800 */
/*0a80*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fe40000000006 */
/*0a90*/ LDS R17, [R15+0x280] ; /* 0x000280000f117984 */
/* 0x0001e80000000800 */
/*0aa0*/ LDS R16, [R14+0x14] ; /* 0x000014000e107984 */
/* 0x0002a20000000800 */
/*0ab0*/ IADD3 R15, R15, 0x400, RZ ; /* 0x000004000f0f7810 */
/* 0x001fc40007ffe0ff */
/*0ac0*/ IADD3 R14, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x002fe20007ffe0ff */
/*0ad0*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x004fe40000000006 */
/*0ae0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0af0*/ ISETP.LT.OR P0, PT, R26, R7, P0 ; /* 0x000000071a00720c */
/* 0x000fda0000701670 */
/*0b00*/ @!P0 BRA 0xbd0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0b10*/ LDS R17, [R15+-0x100] ; /* 0xffff00000f117984 */
/* 0x000fe80000000800 */
/*0b20*/ LDS R16, [R14+-0x8] ; /* 0xfffff8000e107984 */
/* 0x000e280000000800 */
/*0b30*/ LDS R25, [R15] ; /* 0x000000000f197984 */
/* 0x000fe80000000800 */
/*0b40*/ LDS R26, [R14] ; /* 0x000000000e1a7984 */
/* 0x000fe80000000800 */
/*0b50*/ LDS R27, [R15+0x80] ; /* 0x000080000f1b7984 */
/* 0x000fe80000000800 */
/*0b60*/ LDS R28, [R14+0x4] ; /* 0x000004000e1c7984 */
/* 0x000fe20000000800 */
/*0b70*/ FFMA R16, R17, R16, R6 ; /* 0x0000001011107223 */
/* 0x001fc60000000006 */
/*0b80*/ LDS R17, [R15+-0x80] ; /* 0xffff80000f117984 */
/* 0x000fe80000000800 */
/*0b90*/ LDS R6, [R14+-0x4] ; /* 0xfffffc000e067984 */
/* 0x000e240000000800 */
/*0ba0*/ FFMA R6, R17, R6, R16 ; /* 0x0000000611067223 */
/* 0x001fc80000000010 */
/*0bb0*/ FFMA R6, R25, R26, R6 ; /* 0x0000001a19067223 */
/* 0x000fc80000000006 */
/*0bc0*/ FFMA R6, R27, R28, R6 ; /* 0x0000001c1b067223 */
/* 0x000fe40000000006 */
/*0bd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0be0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0bf0*/ @!P1 BRA 0x270 ; /* 0xfffff67000009947 */
/* 0x000fea000383ffff */
/*0c00*/ LEA R8, P0, R4, c[0x0][0x170], 0x3 ; /* 0x00005c0004087a11 */
/* 0x000fc800078018ff */
/*0c10*/ LEA.HI.X R9, R4, c[0x0][0x174], R5, 0x3, P0 ; /* 0x00005d0004097a11 */
/* 0x000fca00000f1c05 */
/*0c20*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea4000c1e1b00 */
/*0c30*/ IMAD.WIDE R4, R3, 0x4, R4 ; /* 0x0000000403047825 */
/* 0x004fca00078e0204 */
/*0c40*/ STG.E [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
*
* Matrix Multiplication - CUDA for GPUs
*
* CS3210
*
**/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <assert.h>
int size;
#define BLOCK_SIZE 32
typedef struct
{
float ** element;
} matrix;
long long wall_clock_time()
{
#ifdef __linux__
struct timespec tp;
clock_gettime(CLOCK_REALTIME, &tp);
return (long long)(tp.tv_nsec + (long long)tp.tv_sec * 1000000000ll);
#else
struct timeval tv;
gettimeofday(&tv, NULL);
return (long long)(tv.tv_usec * 1000 + (long long)tv.tv_sec * 1000000000ll);
#endif
}
/**
* Allocates memory for a matrix of size SIZE
* The memory is allocated row-major order, i.e.
* elements from the same row are allocated at contiguous
* memory addresses.
**/
void allocate_matrix(matrix* m)
{
int i;
cudaError_t rc;
// allocate array for all the rows
rc = cudaMallocManaged((void**)&(m->element), sizeof(float*) * size);
if (rc != cudaSuccess)
{
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(rc));
exit(1);
}
// allocate an array for each row of the matrix
for (i = 0; i < size; i++)
{
rc = cudaMallocManaged((void**)&(m->element[i]), sizeof(float) * size);
if (rc != cudaSuccess)
{
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(rc));
exit(1);
}
}
}
/**
* Free the memory allocated for a matrix.
**/
void free_matrix(matrix* m) {
int i;
for (i = 0; i < size; i++)
cudaFree(m->element[i]);
cudaFree(m->element);
}
/**
* Initializes the elements of the matrix with
* random values between 0 and 9
**/
void init_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = rand() % 10;
}
}
/**
* Initializes the elements of the matrix with
* element 0.
**/
void init_matrix_zero(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = 0.0;
}
}
/**
* Multiplies matrix @a with matrix @b storing
* the result in matrix @result
*
* The multiplication algorithm is the O(n^3)
* algorithm
*/
void mm(matrix a, matrix b, matrix result)
{
int i, j, k;
// Do the multiplication
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
for(k = 0; k < size; k++)
result.element[i][j] += a.element[i][k] * b.element[k][j];
}
/**
* Each kernel computes the result element (i,j).
*/
__global__ void mm_kernel(matrix a, matrix b, matrix result, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int row = threadIdx.y;
int col = threadIdx.x;
int k, m;
int kmax = BLOCK_SIZE + col;
int secondRow = row + BLOCK_SIZE;
int secondCol = col + BLOCK_SIZE;
if (i >= size || j >= size)
return;
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE * 2];
__shared__ float Bs[BLOCK_SIZE * 2][BLOCK_SIZE];
float C_res = 0.0f;
for (m = 0; m < size; m += BLOCK_SIZE) {
As[row][col] = a.element[j][m + threadIdx.x];
As[row][secondCol] = As[row][col];
Bs[row][col] = b.element[m + threadIdx.y][i];
Bs[secondRow][col] = Bs[row][col];
__syncthreads();
for(k = threadIdx.x; k < kmax; k++) {
C_res += As[row][k] * Bs[k][col];
}
__syncthreads();
}
result.element[j][i] = C_res;
}
void print_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
{
printf("row %4d: ", i);
for (j = 0; j < size; j++)
printf("%6.2f ", m.element[i][j]);
printf("\n");
}
}
void work()
{
matrix a, b, result1, result2;
long long before, after;
int correct, i, j, dim;
cudaError_t rc;
// Allocate memory for matrices
allocate_matrix(&a);
allocate_matrix(&b);
allocate_matrix(&result1);
allocate_matrix(&result2);
// Initialize matrix elements
init_matrix(a);
init_matrix(b);
// Perform sequential matrix multiplication
before = wall_clock_time();
mm(a, b, result1);
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on CPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// Perform CUDA matrix multiplication
dim3 block(32, 32); // a block of 32 x 32 CUDA threads
dim = (size % 32 == 0) ? size / 32 : size / 32 + 1;
dim3 grid(dim, dim); // a grid of CUDA thread blocks
before = wall_clock_time();
mm_kernel<<<grid, block>>>(a, b, result2, size);
cudaDeviceSynchronize();
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on GPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// was there any error?
rc = cudaGetLastError();
if (rc != cudaSuccess)
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
// Compare the results
correct = 1;
for (i = 0; correct && i < size; i++)
for (j = 0; j < size; j++)
if (result1.element[i][j] != result2.element[i][j]) {
correct = 0;
break;
}
if (correct)
printf("The result matrices are identical!\n");
else
printf("Difference in result matrices at element (%d, %d)!\n", i, j);
free_matrix(&a);
free_matrix(&b);
free_matrix(&result1);
free_matrix(&result2);
}
int main(int argc, char ** argv)
{
srand(0);
printf("Usage: %s <size>\n", argv[0]);
if (argc >= 2)
size = atoi(argv[1]);
else
size = 1024;
fprintf(stderr,"Sequential matrix multiplication of size %d\n", size);
// Multiply the matrices
work();
return 0;
} | .file "tmpxft_00085aef_00000000-6_mm-banks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15wall_clock_timev
.type _Z15wall_clock_timev, @function
_Z15wall_clock_timev:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
imulq $1000000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z15wall_clock_timev, .-_Z15wall_clock_timev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: %s\n"
.text
.globl _Z15allocate_matrixP6matrix
.type _Z15allocate_matrixP6matrix, @function
_Z15allocate_matrixP6matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movslq size(%rip), %rsi
salq $3, %rsi
movl $1, %edx
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L8
movl size(%rip), %esi
movl $0, %ebx
testl %esi, %esi
jle .L7
.L9:
movslq %esi, %rsi
salq $2, %rsi
movq 0(%rbp), %rax
leaq (%rax,%rbx,8), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L16
movl size(%rip), %esi
addq $1, %rbx
cmpl %ebx, %esi
jg .L9
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z15allocate_matrixP6matrix, .-_Z15allocate_matrixP6matrix
.globl _Z11free_matrixP6matrix
.type _Z11free_matrixP6matrix, @function
_Z11free_matrixP6matrix:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
cmpl $0, size(%rip)
jle .L18
movl $0, %ebx
.L19:
movq 0(%rbp), %rax
movq (%rax,%rbx,8), %rdi
call cudaFree@PLT
addq $1, %rbx
cmpl %ebx, size(%rip)
jg .L19
.L18:
movq 0(%rbp), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11free_matrixP6matrix, .-_Z11free_matrixP6matrix
.globl _Z11init_matrix6matrix
.type _Z11init_matrix6matrix, @function
_Z11init_matrix6matrix:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl $0, %r13d
cmpl $0, size(%rip)
jg .L23
.L22:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call rand@PLT
movq (%r12,%rbp), %rcx
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx,%rbx,4)
addq $1, %rbx
cmpl %ebx, size(%rip)
jg .L25
.L27:
addq $1, %r13
cmpl %r13d, size(%rip)
jle .L22
.L23:
leaq 0(,%r13,8), %rbp
movl $0, %ebx
cmpl $0, size(%rip)
jg .L25
jmp .L27
.cfi_endproc
.LFE2060:
.size _Z11init_matrix6matrix, .-_Z11init_matrix6matrix
.globl _Z16init_matrix_zero6matrix
.type _Z16init_matrix_zero6matrix, @function
_Z16init_matrix_zero6matrix:
.LFB2061:
.cfi_startproc
endbr64
cmpl $0, size(%rip)
jle .L33
movl $0, %ecx
jmp .L35
.L36:
movq (%rdi), %rdx
movl $0x00000000, (%rdx,%rax,4)
addq $1, %rax
cmpl %eax, size(%rip)
jg .L36
.L37:
addl $1, %ecx
addq $8, %rdi
cmpl %ecx, size(%rip)
jle .L33
.L35:
movl $0, %eax
cmpl $0, size(%rip)
jg .L36
jmp .L37
.L33:
ret
.cfi_endproc
.LFE2061:
.size _Z16init_matrix_zero6matrix, .-_Z16init_matrix_zero6matrix
.globl _Z2mm6matrixS_S_
.type _Z2mm6matrixS_S_, @function
_Z2mm6matrixS_S_:
.LFB2062:
.cfi_startproc
endbr64
cmpl $0, size(%rip)
jle .L54
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r8
movq %rsi, %r10
movq %rdx, %r9
movl $0, %ebx
jmp .L43
.L44:
movq %rcx, %rdx
addq (%r9), %rdx
movq (%r8), %rdi
movq (%r10,%rax,8), %rsi
movss (%rdi,%rax,4), %xmm0
mulss (%rsi,%rcx), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $1, %rax
cmpl %eax, size(%rip)
jg .L44
.L47:
addq $1, %r11
cmpl %r11d, size(%rip)
jle .L45
.L48:
leaq 0(,%r11,4), %rcx
movl $0, %eax
cmpl $0, size(%rip)
jg .L44
jmp .L47
.L45:
addl $1, %ebx
addq $8, %r9
addq $8, %r8
cmpl %ebx, size(%rip)
jle .L41
.L43:
movl $0, %r11d
cmpl $0, size(%rip)
jg .L48
jmp .L45
.L41:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore 3
ret
.cfi_endproc
.LFE2062:
.size _Z2mm6matrixS_S_, .-_Z2mm6matrixS_S_
.section .rodata.str1.1
.LC2:
.string "row %4d: "
.LC3:
.string "%6.2f "
.LC4:
.string "\n"
.text
.globl _Z12print_matrix6matrix
.type _Z12print_matrix6matrix, @function
_Z12print_matrix6matrix:
.LFB2063:
.cfi_startproc
endbr64
cmpl $0, size(%rip)
jle .L65
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl $0, %r14d
leaq .LC2(%rip), %r15
leaq .LC3(%rip), %r13
.L61:
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, size(%rip)
jle .L59
leaq 0(,%r14,8), %rbp
movl $0, %ebx
.L60:
movq (%r12,%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, size(%rip)
jg .L60
.L59:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
cmpl %r14d, size(%rip)
jg .L61
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2063:
.size _Z12print_matrix6matrix, .-_Z12print_matrix6matrix
.globl _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i
.type _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i, @function
_Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L72
.L68:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9mm_kernel6matrixS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L68
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i, .-_Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i
.globl _Z9mm_kernel6matrixS_S_i
.type _Z9mm_kernel6matrixS_S_i, @function
_Z9mm_kernel6matrixS_S_i:
.LFB2091:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
leaq 8(%rsp), %rdx
leaq 16(%rsp), %rsi
leaq 24(%rsp), %rdi
call _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z9mm_kernel6matrixS_S_i, .-_Z9mm_kernel6matrixS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Matrix multiplication on CPU took %1.2f seconds\n"
.align 8
.LC7:
.string "Matrix multiplication on GPU took %1.2f seconds\n"
.section .rodata.str1.1
.LC8:
.string "Last CUDA error %s\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Difference in result matrices at element (%d, %d)!\n"
.align 8
.LC10:
.string "The result matrices are identical!\n"
.text
.globl _Z4workv
.type _Z4workv, @function
_Z4workv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call _Z15allocate_matrixP6matrix
leaq 16(%rsp), %rdi
call _Z15allocate_matrixP6matrix
leaq 24(%rsp), %rdi
call _Z15allocate_matrixP6matrix
leaq 32(%rsp), %rdi
call _Z15allocate_matrixP6matrix
movq 8(%rsp), %rdi
call _Z11init_matrix6matrix
movq 16(%rsp), %rdi
call _Z11init_matrix6matrix
call _Z15wall_clock_timev
movq %rax, %rbx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z2mm6matrixS_S_
call _Z15wall_clock_timev
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $32, 64(%rsp)
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl size(%rip), %edx
testb $31, %dl
jne .L77
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
.L78:
movl %eax, 76(%rsp)
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
call _Z15wall_clock_timev
movq %rax, %rbx
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L79:
call cudaDeviceSynchronize@PLT
call _Z15wall_clock_timev
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L95
.L80:
movl size(%rip), %r8d
movq 24(%rsp), %r10
movq 32(%rsp), %r9
movl $0, %edi
movslq %r8d, %rsi
jmp .L81
.L77:
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
addl $1, %eax
jmp .L78
.L94:
movq 8(%rsp), %rax
movq %rax, 40(%rsp)
movq 16(%rsp), %rax
movq %rax, 48(%rsp)
movq 32(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdi
movl size(%rip), %ecx
call _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i
jmp .L79
.L95:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L87:
addq $1, %rdi
.L81:
cmpl %edi, %r8d
jle .L85
testl %r8d, %r8d
jle .L87
movq (%r10,%rdi,8), %rdx
movq (%r9,%rdi,8), %rax
movl $0, %ecx
.L84:
movss (%rdx,%rcx,4), %xmm0
ucomiss (%rax,%rcx,4), %xmm0
jp .L82
jne .L82
addq $1, %rcx
cmpq %rsi, %rcx
jne .L84
jmp .L87
.L82:
leal 1(%rdi), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L88:
leaq 8(%rsp), %rdi
call _Z11free_matrixP6matrix
leaq 16(%rsp), %rdi
call _Z11free_matrixP6matrix
leaq 24(%rsp), %rdi
call _Z11free_matrixP6matrix
leaq 32(%rsp), %rdi
call _Z11free_matrixP6matrix
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L88
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z4workv, .-_Z4workv
.section .rodata.str1.1
.LC11:
.string "Usage: %s <size>\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Sequential matrix multiplication of size %d\n"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebp
movq %rsi, %rbx
movl $0, %edi
call srand@PLT
movq (%rbx), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %ecx
cmpl $1, %ebp
jg .L101
.L98:
movl %ecx, size(%rip)
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
call _Z4workv
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ecx
jmp .L98
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z9mm_kernel6matrixS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mm_kernel6matrixS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl size
.bss
.align 4
.type size, @object
.size size, 4
size:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1315859240
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
*
* Matrix Multiplication - CUDA for GPUs
*
* CS3210
*
**/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <assert.h>
int size;
#define BLOCK_SIZE 32
typedef struct
{
float ** element;
} matrix;
long long wall_clock_time()
{
#ifdef __linux__
struct timespec tp;
clock_gettime(CLOCK_REALTIME, &tp);
return (long long)(tp.tv_nsec + (long long)tp.tv_sec * 1000000000ll);
#else
struct timeval tv;
gettimeofday(&tv, NULL);
return (long long)(tv.tv_usec * 1000 + (long long)tv.tv_sec * 1000000000ll);
#endif
}
/**
* Allocates memory for a matrix of size SIZE
* The memory is allocated row-major order, i.e.
* elements from the same row are allocated at contiguous
* memory addresses.
**/
void allocate_matrix(matrix* m)
{
int i;
cudaError_t rc;
// allocate array for all the rows
rc = cudaMallocManaged((void**)&(m->element), sizeof(float*) * size);
if (rc != cudaSuccess)
{
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(rc));
exit(1);
}
// allocate an array for each row of the matrix
for (i = 0; i < size; i++)
{
rc = cudaMallocManaged((void**)&(m->element[i]), sizeof(float) * size);
if (rc != cudaSuccess)
{
fprintf(stderr, "CUDA error: %s\n", cudaGetErrorString(rc));
exit(1);
}
}
}
/**
* Free the memory allocated for a matrix.
**/
void free_matrix(matrix* m) {
int i;
for (i = 0; i < size; i++)
cudaFree(m->element[i]);
cudaFree(m->element);
}
/**
* Initializes the elements of the matrix with
* random values between 0 and 9
**/
void init_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = rand() % 10;
}
}
/**
* Initializes the elements of the matrix with
* element 0.
**/
void init_matrix_zero(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = 0.0;
}
}
/**
* Multiplies matrix @a with matrix @b storing
* the result in matrix @result
*
* The multiplication algorithm is the O(n^3)
* algorithm
*/
void mm(matrix a, matrix b, matrix result)
{
int i, j, k;
// Do the multiplication
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
for(k = 0; k < size; k++)
result.element[i][j] += a.element[i][k] * b.element[k][j];
}
/**
* Each kernel computes the result element (i,j).
*/
__global__ void mm_kernel(matrix a, matrix b, matrix result, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int row = threadIdx.y;
int col = threadIdx.x;
int k, m;
int kmax = BLOCK_SIZE + col;
int secondRow = row + BLOCK_SIZE;
int secondCol = col + BLOCK_SIZE;
if (i >= size || j >= size)
return;
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE * 2];
__shared__ float Bs[BLOCK_SIZE * 2][BLOCK_SIZE];
float C_res = 0.0f;
for (m = 0; m < size; m += BLOCK_SIZE) {
As[row][col] = a.element[j][m + threadIdx.x];
As[row][secondCol] = As[row][col];
Bs[row][col] = b.element[m + threadIdx.y][i];
Bs[secondRow][col] = Bs[row][col];
__syncthreads();
for(k = threadIdx.x; k < kmax; k++) {
C_res += As[row][k] * Bs[k][col];
}
__syncthreads();
}
result.element[j][i] = C_res;
}
void print_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
{
printf("row %4d: ", i);
for (j = 0; j < size; j++)
printf("%6.2f ", m.element[i][j]);
printf("\n");
}
}
void work()
{
matrix a, b, result1, result2;
long long before, after;
int correct, i, j, dim;
cudaError_t rc;
// Allocate memory for matrices
allocate_matrix(&a);
allocate_matrix(&b);
allocate_matrix(&result1);
allocate_matrix(&result2);
// Initialize matrix elements
init_matrix(a);
init_matrix(b);
// Perform sequential matrix multiplication
before = wall_clock_time();
mm(a, b, result1);
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on CPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// Perform CUDA matrix multiplication
dim3 block(32, 32); // a block of 32 x 32 CUDA threads
dim = (size % 32 == 0) ? size / 32 : size / 32 + 1;
dim3 grid(dim, dim); // a grid of CUDA thread blocks
before = wall_clock_time();
mm_kernel<<<grid, block>>>(a, b, result2, size);
cudaDeviceSynchronize();
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on GPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// was there any error?
rc = cudaGetLastError();
if (rc != cudaSuccess)
printf("Last CUDA error %s\n", cudaGetErrorString(rc));
// Compare the results
correct = 1;
for (i = 0; correct && i < size; i++)
for (j = 0; j < size; j++)
if (result1.element[i][j] != result2.element[i][j]) {
correct = 0;
break;
}
if (correct)
printf("The result matrices are identical!\n");
else
printf("Difference in result matrices at element (%d, %d)!\n", i, j);
free_matrix(&a);
free_matrix(&b);
free_matrix(&result1);
free_matrix(&result2);
}
int main(int argc, char ** argv)
{
srand(0);
printf("Usage: %s <size>\n", argv[0]);
if (argc >= 2)
size = atoi(argv[1]);
else
size = 1024;
fprintf(stderr,"Sequential matrix multiplication of size %d\n", size);
// Multiply the matrices
work();
return 0;
} | /**
*
* Matrix Multiplication - CUDA for GPUs
*
* CS3210
*
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <assert.h>
int size;
#define BLOCK_SIZE 32
typedef struct
{
float ** element;
} matrix;
long long wall_clock_time()
{
#ifdef __linux__
struct timespec tp;
clock_gettime(CLOCK_REALTIME, &tp);
return (long long)(tp.tv_nsec + (long long)tp.tv_sec * 1000000000ll);
#else
struct timeval tv;
gettimeofday(&tv, NULL);
return (long long)(tv.tv_usec * 1000 + (long long)tv.tv_sec * 1000000000ll);
#endif
}
/**
* Allocates memory for a matrix of size SIZE
* The memory is allocated row-major order, i.e.
* elements from the same row are allocated at contiguous
* memory addresses.
**/
void allocate_matrix(matrix* m)
{
int i;
hipError_t rc;
// allocate array for all the rows
rc = hipMallocManaged((void**)&(m->element), sizeof(float*) * size);
if (rc != hipSuccess)
{
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(rc));
exit(1);
}
// allocate an array for each row of the matrix
for (i = 0; i < size; i++)
{
rc = hipMallocManaged((void**)&(m->element[i]), sizeof(float) * size);
if (rc != hipSuccess)
{
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(rc));
exit(1);
}
}
}
/**
* Free the memory allocated for a matrix.
**/
void free_matrix(matrix* m) {
int i;
for (i = 0; i < size; i++)
hipFree(m->element[i]);
hipFree(m->element);
}
/**
* Initializes the elements of the matrix with
* random values between 0 and 9
**/
void init_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = rand() % 10;
}
}
/**
* Initializes the elements of the matrix with
* element 0.
**/
void init_matrix_zero(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = 0.0;
}
}
/**
* Multiplies matrix @a with matrix @b storing
* the result in matrix @result
*
* The multiplication algorithm is the O(n^3)
* algorithm
*/
void mm(matrix a, matrix b, matrix result)
{
int i, j, k;
// Do the multiplication
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
for(k = 0; k < size; k++)
result.element[i][j] += a.element[i][k] * b.element[k][j];
}
/**
* Each kernel computes the result element (i,j).
*/
__global__ void mm_kernel(matrix a, matrix b, matrix result, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int row = threadIdx.y;
int col = threadIdx.x;
int k, m;
int kmax = BLOCK_SIZE + col;
int secondRow = row + BLOCK_SIZE;
int secondCol = col + BLOCK_SIZE;
if (i >= size || j >= size)
return;
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE * 2];
__shared__ float Bs[BLOCK_SIZE * 2][BLOCK_SIZE];
float C_res = 0.0f;
for (m = 0; m < size; m += BLOCK_SIZE) {
As[row][col] = a.element[j][m + threadIdx.x];
As[row][secondCol] = As[row][col];
Bs[row][col] = b.element[m + threadIdx.y][i];
Bs[secondRow][col] = Bs[row][col];
__syncthreads();
for(k = threadIdx.x; k < kmax; k++) {
C_res += As[row][k] * Bs[k][col];
}
__syncthreads();
}
result.element[j][i] = C_res;
}
void print_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
{
printf("row %4d: ", i);
for (j = 0; j < size; j++)
printf("%6.2f ", m.element[i][j]);
printf("\n");
}
}
void work()
{
matrix a, b, result1, result2;
long long before, after;
int correct, i, j, dim;
hipError_t rc;
// Allocate memory for matrices
allocate_matrix(&a);
allocate_matrix(&b);
allocate_matrix(&result1);
allocate_matrix(&result2);
// Initialize matrix elements
init_matrix(a);
init_matrix(b);
// Perform sequential matrix multiplication
before = wall_clock_time();
mm(a, b, result1);
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on CPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// Perform CUDA matrix multiplication
dim3 block(32, 32); // a block of 32 x 32 CUDA threads
dim = (size % 32 == 0) ? size / 32 : size / 32 + 1;
dim3 grid(dim, dim); // a grid of CUDA thread blocks
before = wall_clock_time();
mm_kernel<<<grid, block>>>(a, b, result2, size);
hipDeviceSynchronize();
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on GPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// was there any error?
rc = hipGetLastError();
if (rc != hipSuccess)
printf("Last CUDA error %s\n", hipGetErrorString(rc));
// Compare the results
correct = 1;
for (i = 0; correct && i < size; i++)
for (j = 0; j < size; j++)
if (result1.element[i][j] != result2.element[i][j]) {
correct = 0;
break;
}
if (correct)
printf("The result matrices are identical!\n");
else
printf("Difference in result matrices at element (%d, %d)!\n", i, j);
free_matrix(&a);
free_matrix(&b);
free_matrix(&result1);
free_matrix(&result2);
}
int main(int argc, char ** argv)
{
srand(0);
printf("Usage: %s <size>\n", argv[0]);
if (argc >= 2)
size = atoi(argv[1]);
else
size = 1024;
fprintf(stderr,"Sequential matrix multiplication of size %d\n", size);
// Multiply the matrices
work();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
*
* Matrix Multiplication - CUDA for GPUs
*
* CS3210
*
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <assert.h>
int size;
#define BLOCK_SIZE 32
typedef struct
{
float ** element;
} matrix;
long long wall_clock_time()
{
#ifdef __linux__
struct timespec tp;
clock_gettime(CLOCK_REALTIME, &tp);
return (long long)(tp.tv_nsec + (long long)tp.tv_sec * 1000000000ll);
#else
struct timeval tv;
gettimeofday(&tv, NULL);
return (long long)(tv.tv_usec * 1000 + (long long)tv.tv_sec * 1000000000ll);
#endif
}
/**
* Allocates memory for a matrix of size SIZE
* The memory is allocated row-major order, i.e.
* elements from the same row are allocated at contiguous
* memory addresses.
**/
void allocate_matrix(matrix* m)
{
int i;
hipError_t rc;
// allocate array for all the rows
rc = hipMallocManaged((void**)&(m->element), sizeof(float*) * size);
if (rc != hipSuccess)
{
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(rc));
exit(1);
}
// allocate an array for each row of the matrix
for (i = 0; i < size; i++)
{
rc = hipMallocManaged((void**)&(m->element[i]), sizeof(float) * size);
if (rc != hipSuccess)
{
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(rc));
exit(1);
}
}
}
/**
* Free the memory allocated for a matrix.
**/
void free_matrix(matrix* m) {
int i;
for (i = 0; i < size; i++)
hipFree(m->element[i]);
hipFree(m->element);
}
/**
* Initializes the elements of the matrix with
* random values between 0 and 9
**/
void init_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = rand() % 10;
}
}
/**
* Initializes the elements of the matrix with
* element 0.
**/
void init_matrix_zero(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = 0.0;
}
}
/**
* Multiplies matrix @a with matrix @b storing
* the result in matrix @result
*
* The multiplication algorithm is the O(n^3)
* algorithm
*/
void mm(matrix a, matrix b, matrix result)
{
int i, j, k;
// Do the multiplication
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
for(k = 0; k < size; k++)
result.element[i][j] += a.element[i][k] * b.element[k][j];
}
/**
* Each kernel computes the result element (i,j).
*/
__global__ void mm_kernel(matrix a, matrix b, matrix result, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int row = threadIdx.y;
int col = threadIdx.x;
int k, m;
int kmax = BLOCK_SIZE + col;
int secondRow = row + BLOCK_SIZE;
int secondCol = col + BLOCK_SIZE;
if (i >= size || j >= size)
return;
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE * 2];
__shared__ float Bs[BLOCK_SIZE * 2][BLOCK_SIZE];
float C_res = 0.0f;
for (m = 0; m < size; m += BLOCK_SIZE) {
As[row][col] = a.element[j][m + threadIdx.x];
As[row][secondCol] = As[row][col];
Bs[row][col] = b.element[m + threadIdx.y][i];
Bs[secondRow][col] = Bs[row][col];
__syncthreads();
for(k = threadIdx.x; k < kmax; k++) {
C_res += As[row][k] * Bs[k][col];
}
__syncthreads();
}
result.element[j][i] = C_res;
}
void print_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
{
printf("row %4d: ", i);
for (j = 0; j < size; j++)
printf("%6.2f ", m.element[i][j]);
printf("\n");
}
}
void work()
{
matrix a, b, result1, result2;
long long before, after;
int correct, i, j, dim;
hipError_t rc;
// Allocate memory for matrices
allocate_matrix(&a);
allocate_matrix(&b);
allocate_matrix(&result1);
allocate_matrix(&result2);
// Initialize matrix elements
init_matrix(a);
init_matrix(b);
// Perform sequential matrix multiplication
before = wall_clock_time();
mm(a, b, result1);
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on CPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// Perform CUDA matrix multiplication
dim3 block(32, 32); // a block of 32 x 32 CUDA threads
dim = (size % 32 == 0) ? size / 32 : size / 32 + 1;
dim3 grid(dim, dim); // a grid of CUDA thread blocks
before = wall_clock_time();
mm_kernel<<<grid, block>>>(a, b, result2, size);
hipDeviceSynchronize();
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on GPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// was there any error?
rc = hipGetLastError();
if (rc != hipSuccess)
printf("Last CUDA error %s\n", hipGetErrorString(rc));
// Compare the results
correct = 1;
for (i = 0; correct && i < size; i++)
for (j = 0; j < size; j++)
if (result1.element[i][j] != result2.element[i][j]) {
correct = 0;
break;
}
if (correct)
printf("The result matrices are identical!\n");
else
printf("Difference in result matrices at element (%d, %d)!\n", i, j);
free_matrix(&a);
free_matrix(&b);
free_matrix(&result1);
free_matrix(&result2);
}
int main(int argc, char ** argv)
{
srand(0);
printf("Usage: %s <size>\n", argv[0]);
if (argc >= 2)
size = atoi(argv[1]);
else
size = 1024;
fprintf(stderr,"Sequential matrix multiplication of size %d\n", size);
// Multiply the matrices
work();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mm_kernel6matrixS_S_i
.globl _Z9mm_kernel6matrixS_S_i
.p2align 8
.type _Z9mm_kernel6matrixS_S_i,@function
_Z9mm_kernel6matrixS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[4:5]
v_mad_u64_u32 v[2:3], null, s15, s3, v[5:6]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v1, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v6, 2, v4
v_lshlrev_b64 v[8:9], 3, v[2:3]
s_movk_i32 s3, 0x84
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u32_u24 v12, v4, s3, 0x2000
v_lshl_add_u32 v11, v5, 8, v6
v_lshl_add_u32 v10, v5, 7, v6
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v13, 0x80, v11
v_add_nc_u32_e32 v14, 0x2000, v10
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v15, 0x3000, v10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
.LBB0_3:
global_load_b64 v[16:17], v[8:9], off
v_dual_mov_b32 v19, 0 :: v_dual_add_nc_u32 v18, s3, v4
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[20:21], 2, v[18:19]
v_add_nc_u32_e32 v18, s3, v5
v_lshlrev_b64 v[18:19], 3, v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v18, vcc_lo, s6, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
global_load_b64 v[18:19], v[18:19], off
s_waitcnt vmcnt(1)
v_add_co_u32 v16, vcc_lo, v16, v20
v_add_co_ci_u32_e32 v17, vcc_lo, v17, v21, vcc_lo
flat_load_b32 v20, v[16:17]
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_b32 v11, v20
ds_store_b32 v13, v20
v_add_co_u32 v16, vcc_lo, v18, v6
v_add_co_ci_u32_e32 v17, vcc_lo, v19, v7, vcc_lo
flat_load_b32 v17, v[16:17]
v_mov_b32_e32 v16, v12
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_b32 v14, v17
ds_store_b32 v15, v17
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_4:
v_add_nc_u32_e32 v17, s4, v11
s_add_i32 s4, s4, 4
ds_load_b32 v18, v16
ds_load_b32 v17, v17
v_add_nc_u32_e32 v16, 0x80, v16
s_cmpk_lg_i32 s4, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v10, v17, v18
s_cbranch_scc1 .LBB0_4
s_add_i32 s3, s3, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v10, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
flat_store_b32 v[0:1], v10
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mm_kernel6matrixS_S_i
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mm_kernel6matrixS_S_i, .Lfunc_end0-_Z9mm_kernel6matrixS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mm_kernel6matrixS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mm_kernel6matrixS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
*
* Matrix Multiplication - CUDA for GPUs
*
* CS3210
*
**/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <sys/time.h>
#include <assert.h>
int size;
#define BLOCK_SIZE 32
typedef struct
{
float ** element;
} matrix;
long long wall_clock_time()
{
#ifdef __linux__
struct timespec tp;
clock_gettime(CLOCK_REALTIME, &tp);
return (long long)(tp.tv_nsec + (long long)tp.tv_sec * 1000000000ll);
#else
struct timeval tv;
gettimeofday(&tv, NULL);
return (long long)(tv.tv_usec * 1000 + (long long)tv.tv_sec * 1000000000ll);
#endif
}
/**
* Allocates memory for a matrix of size SIZE
* The memory is allocated row-major order, i.e.
* elements from the same row are allocated at contiguous
* memory addresses.
**/
void allocate_matrix(matrix* m)
{
int i;
hipError_t rc;
// allocate array for all the rows
rc = hipMallocManaged((void**)&(m->element), sizeof(float*) * size);
if (rc != hipSuccess)
{
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(rc));
exit(1);
}
// allocate an array for each row of the matrix
for (i = 0; i < size; i++)
{
rc = hipMallocManaged((void**)&(m->element[i]), sizeof(float) * size);
if (rc != hipSuccess)
{
fprintf(stderr, "CUDA error: %s\n", hipGetErrorString(rc));
exit(1);
}
}
}
/**
* Free the memory allocated for a matrix.
**/
void free_matrix(matrix* m) {
int i;
for (i = 0; i < size; i++)
hipFree(m->element[i]);
hipFree(m->element);
}
/**
* Initializes the elements of the matrix with
* random values between 0 and 9
**/
void init_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = rand() % 10;
}
}
/**
* Initializes the elements of the matrix with
* element 0.
**/
void init_matrix_zero(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
{
m.element[i][j] = 0.0;
}
}
/**
* Multiplies matrix @a with matrix @b storing
* the result in matrix @result
*
* The multiplication algorithm is the O(n^3)
* algorithm
*/
void mm(matrix a, matrix b, matrix result)
{
int i, j, k;
// Do the multiplication
for (i = 0; i < size; i++)
for (j = 0; j < size; j++)
for(k = 0; k < size; k++)
result.element[i][j] += a.element[i][k] * b.element[k][j];
}
/**
* Each kernel computes the result element (i,j).
*/
__global__ void mm_kernel(matrix a, matrix b, matrix result, int size)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int j = blockIdx.y * blockDim.y + threadIdx.y;
int row = threadIdx.y;
int col = threadIdx.x;
int k, m;
int kmax = BLOCK_SIZE + col;
int secondRow = row + BLOCK_SIZE;
int secondCol = col + BLOCK_SIZE;
if (i >= size || j >= size)
return;
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE * 2];
__shared__ float Bs[BLOCK_SIZE * 2][BLOCK_SIZE];
float C_res = 0.0f;
for (m = 0; m < size; m += BLOCK_SIZE) {
As[row][col] = a.element[j][m + threadIdx.x];
As[row][secondCol] = As[row][col];
Bs[row][col] = b.element[m + threadIdx.y][i];
Bs[secondRow][col] = Bs[row][col];
__syncthreads();
for(k = threadIdx.x; k < kmax; k++) {
C_res += As[row][k] * Bs[k][col];
}
__syncthreads();
}
result.element[j][i] = C_res;
}
void print_matrix(matrix m)
{
int i, j;
for (i = 0; i < size; i++)
{
printf("row %4d: ", i);
for (j = 0; j < size; j++)
printf("%6.2f ", m.element[i][j]);
printf("\n");
}
}
void work()
{
matrix a, b, result1, result2;
long long before, after;
int correct, i, j, dim;
hipError_t rc;
// Allocate memory for matrices
allocate_matrix(&a);
allocate_matrix(&b);
allocate_matrix(&result1);
allocate_matrix(&result2);
// Initialize matrix elements
init_matrix(a);
init_matrix(b);
// Perform sequential matrix multiplication
before = wall_clock_time();
mm(a, b, result1);
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on CPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// Perform CUDA matrix multiplication
dim3 block(32, 32); // a block of 32 x 32 CUDA threads
dim = (size % 32 == 0) ? size / 32 : size / 32 + 1;
dim3 grid(dim, dim); // a grid of CUDA thread blocks
before = wall_clock_time();
mm_kernel<<<grid, block>>>(a, b, result2, size);
hipDeviceSynchronize();
after = wall_clock_time();
fprintf(stderr, "Matrix multiplication on GPU took %1.2f seconds\n", ((float)(after - before))/1000000000);
// was there any error?
rc = hipGetLastError();
if (rc != hipSuccess)
printf("Last CUDA error %s\n", hipGetErrorString(rc));
// Compare the results
correct = 1;
for (i = 0; correct && i < size; i++)
for (j = 0; j < size; j++)
if (result1.element[i][j] != result2.element[i][j]) {
correct = 0;
break;
}
if (correct)
printf("The result matrices are identical!\n");
else
printf("Difference in result matrices at element (%d, %d)!\n", i, j);
free_matrix(&a);
free_matrix(&b);
free_matrix(&result1);
free_matrix(&result2);
}
int main(int argc, char ** argv)
{
srand(0);
printf("Usage: %s <size>\n", argv[0]);
if (argc >= 2)
size = atoi(argv[1]);
else
size = 1024;
fprintf(stderr,"Sequential matrix multiplication of size %d\n", size);
// Multiply the matrices
work();
return 0;
} | .text
.file "mm-banks.hip"
.globl _Z15wall_clock_timev # -- Begin function _Z15wall_clock_timev
.p2align 4, 0x90
.type _Z15wall_clock_timev,@function
_Z15wall_clock_timev: # @_Z15wall_clock_timev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
imulq $1000000000, 8(%rsp), %rax # imm = 0x3B9ACA00
addq 16(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15wall_clock_timev, .Lfunc_end0-_Z15wall_clock_timev
.cfi_endproc
# -- End function
.globl _Z15allocate_matrixP6matrix # -- Begin function _Z15allocate_matrixP6matrix
.p2align 4, 0x90
.type _Z15allocate_matrixP6matrix,@function
_Z15allocate_matrixP6matrix: # @_Z15allocate_matrixP6matrix
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movslq size(%rip), %rsi
shlq $3, %rsi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_5
# %bb.1: # %.preheader
movl size(%rip), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.2: # %.lr.ph.preheader
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rdi
addq %r14, %rdi
movslq %eax, %rsi
shlq $2, %rsi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_5
# %bb.3: # in Loop: Header=BB1_4 Depth=1
incq %r15
movslq size(%rip), %rax
addq $8, %r14
cmpq %rax, %r15
jl .LBB1_4
.LBB1_6: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z15allocate_matrixP6matrix, .Lfunc_end1-_Z15allocate_matrixP6matrix
.cfi_endproc
# -- End function
.globl _Z11free_matrixP6matrix # -- Begin function _Z11free_matrixP6matrix
.p2align 4, 0x90
.type _Z11free_matrixP6matrix,@function
_Z11free_matrixP6matrix: # @_Z11free_matrixP6matrix
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
cmpl $0, size(%rip)
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rax
movq (%rax,%r14,8), %rdi
callq hipFree
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jl .LBB2_2
.LBB2_3: # %._crit_edge
movq (%rbx), %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end2:
.size _Z11free_matrixP6matrix, .Lfunc_end2-_Z11free_matrixP6matrix
.cfi_endproc
# -- End function
.globl _Z11init_matrix6matrix # -- Begin function _Z11init_matrix6matrix
.p2align 4, 0x90
.type _Z11init_matrix6matrix,@function
_Z11init_matrix6matrix: # @_Z11init_matrix6matrix
.cfi_startproc
# %bb.0:
cmpl $0, size(%rip)
jle .LBB3_7
# %bb.1: # %.preheader.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jge .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, size(%rip)
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%rbx,%r14,8), %rax
movss %xmm0, (%rax,%r15,4)
incq %r15
movslq size(%rip), %rax
cmpq %rax, %r15
jl .LBB3_4
jmp .LBB3_5
.LBB3_6:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_7: # %._crit_edge9
retq
.Lfunc_end3:
.size _Z11init_matrix6matrix, .Lfunc_end3-_Z11init_matrix6matrix
.cfi_endproc
# -- End function
.globl _Z16init_matrix_zero6matrix # -- Begin function _Z16init_matrix_zero6matrix
.p2align 4, 0x90
.type _Z16init_matrix_zero6matrix,@function
_Z16init_matrix_zero6matrix: # @_Z16init_matrix_zero6matrix
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl size(%rip), %r15d
testl %r15d, %r15d
jle .LBB4_3
# %bb.1: # %.preheader.lr.ph
movq %rdi, %rbx
leaq (,%r15,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rbx,%r12,8), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
incq %r12
cmpq %r12, %r15
jne .LBB4_2
.LBB4_3: # %._crit_edge9
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16init_matrix_zero6matrix, .Lfunc_end4-_Z16init_matrix_zero6matrix
.cfi_endproc
# -- End function
.globl _Z2mm6matrixS_S_ # -- Begin function _Z2mm6matrixS_S_
.p2align 4, 0x90
.type _Z2mm6matrixS_S_,@function
_Z2mm6matrixS_S_: # @_Z2mm6matrixS_S_
.cfi_startproc
# %bb.0:
movl size(%rip), %eax
testl %eax, %eax
jle .LBB5_8
# %bb.1: # %.preheader16.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.preheader16
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
# Child Loop BB5_4 Depth 3
movq (%rdi,%rcx,8), %r8
movq (%rdx,%rcx,8), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB5_3: # %.preheader
# Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_4 Depth 3
movss (%r9,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# Parent Loop BB5_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r8,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq (%rsi,%r11,8), %rbx
mulss (%rbx,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r9,%r10,4)
incq %r11
cmpq %r11, %rax
jne .LBB5_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB5_3 Depth=2
incq %r10
cmpq %rax, %r10
jne .LBB5_3
# %bb.6: # %._crit_edge19
# in Loop: Header=BB5_2 Depth=1
incq %rcx
cmpq %rax, %rcx
jne .LBB5_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB5_8: # %._crit_edge21
retq
.Lfunc_end5:
.size _Z2mm6matrixS_S_, .Lfunc_end5-_Z2mm6matrixS_S_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__mm_kernel6matrixS_S_i # -- Begin function _Z24__device_stub__mm_kernel6matrixS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__mm_kernel6matrixS_S_i,@function
_Z24__device_stub__mm_kernel6matrixS_S_i: # @_Z24__device_stub__mm_kernel6matrixS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mm_kernel6matrixS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z24__device_stub__mm_kernel6matrixS_S_i, .Lfunc_end6-_Z24__device_stub__mm_kernel6matrixS_S_i
.cfi_endproc
# -- End function
.globl _Z12print_matrix6matrix # -- Begin function _Z12print_matrix6matrix
.p2align 4, 0x90
.type _Z12print_matrix6matrix,@function
_Z12print_matrix6matrix: # @_Z12print_matrix6matrix
.cfi_startproc
# %bb.0:
cmpl $0, size(%rip)
jle .LBB7_7
# %bb.1: # %.lr.ph11.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_5: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jge .LBB7_6
.LBB7_2: # %.lr.ph11
# =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
cmpl $0, size(%rip)
jle .LBB7_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB7_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_4: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r14,8), %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
movslq size(%rip), %rax
cmpq %rax, %r15
jl .LBB7_4
jmp .LBB7_5
.LBB7_6:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB7_7: # %._crit_edge12
retq
.Lfunc_end7:
.size _Z12print_matrix6matrix, .Lfunc_end7-_Z12print_matrix6matrix
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4workv
.LCPI8_0:
.long 0x4e6e6b28 # float 1.0E+9
.text
.globl _Z4workv
.p2align 4, 0x90
.type _Z4workv,@function
_Z4workv: # @_Z4workv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
callq _Z15allocate_matrixP6matrix
movq %rsp, %rdi
callq _Z15allocate_matrixP6matrix
leaq 24(%rsp), %rdi
callq _Z15allocate_matrixP6matrix
leaq 16(%rsp), %rdi
callq _Z15allocate_matrixP6matrix
cmpl $0, size(%rip)
jle .LBB8_6
# %bb.1: # %.preheader.i.preheader
movq 8(%rsp), %rbx
xorl %r14d, %r14d
jmp .LBB8_2
.p2align 4, 0x90
.LBB8_5: # %._crit_edge.i
# in Loop: Header=BB8_2 Depth=1
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jge .LBB8_6
.LBB8_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
cmpl $0, size(%rip)
jle .LBB8_5
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB8_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_4: # Parent Loop BB8_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%rbx,%r14,8), %rax
movss %xmm0, (%rax,%r15,4)
incq %r15
movslq size(%rip), %rax
cmpq %rax, %r15
jl .LBB8_4
jmp .LBB8_5
.LBB8_6: # %_Z11init_matrix6matrix.exit
cmpl $0, size(%rip)
jle .LBB8_12
# %bb.7: # %.preheader.i39.preheader
movq (%rsp), %rbx
xorl %r14d, %r14d
jmp .LBB8_8
.p2align 4, 0x90
.LBB8_11: # %._crit_edge.i41
# in Loop: Header=BB8_8 Depth=1
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jge .LBB8_12
.LBB8_8: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB8_10 Depth 2
cmpl $0, size(%rip)
jle .LBB8_11
# %bb.9: # %.lr.ph.i43
# in Loop: Header=BB8_8 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_10: # Parent Loop BB8_8 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%rbx,%r14,8), %rax
movss %xmm0, (%rax,%r15,4)
incq %r15
movslq size(%rip), %rax
cmpq %rax, %r15
jl .LBB8_10
jmp .LBB8_11
.LBB8_12: # %_Z11init_matrix6matrix.exit46
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %r14
movq 40(%rsp), %rbx
movl size(%rip), %eax
testl %eax, %eax
jle .LBB8_19
# %bb.13: # %.preheader16.lr.ph.i
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq 24(%rsp), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB8_14: # %.preheader16.i
# =>This Loop Header: Depth=1
# Child Loop BB8_15 Depth 2
# Child Loop BB8_16 Depth 3
movq (%rcx,%rdi,8), %r8
movq (%rsi,%rdi,8), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB8_15: # %.preheader.i47
# Parent Loop BB8_14 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB8_16 Depth 3
movss (%r9,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB8_16: # Parent Loop BB8_14 Depth=1
# Parent Loop BB8_15 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r8,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq (%rdx,%r11,8), %r15
mulss (%r15,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r9,%r10,4)
incq %r11
cmpq %r11, %rax
jne .LBB8_16
# %bb.17: # %._crit_edge.i50
# in Loop: Header=BB8_15 Depth=2
incq %r10
cmpq %rax, %r10
jne .LBB8_15
# %bb.18: # %._crit_edge19.i
# in Loop: Header=BB8_14 Depth=1
incq %rdi
cmpq %rax, %rdi
jne .LBB8_14
.LBB8_19: # %_Z2mm6matrixS_S_.exit
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %rax
subq %r14, %rax
movq 40(%rsp), %rcx
subq %rbx, %rcx
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
addq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movq stderr(%rip), %rdi
divss .LCPI8_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movb $1, %al
callq fprintf
movl size(%rip), %eax
testb $31, %al
jne .LBB8_21
# %bb.20:
sarl $5, %eax
jmp .LBB8_22
.LBB8_21:
leal 31(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
incl %ecx
movl %ecx, %eax
.LBB8_22:
movl %eax, %eax
movq %rax, %rbx
shlq $32, %rbx
orq %rax, %rbx
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %r15
movq 40(%rsp), %r14
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_24
# %bb.23:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movl size(%rip), %esi
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl %esi, 76(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 76(%rsp), %rax
movq %rax, 56(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z9mm_kernel6matrixS_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_24:
callq hipDeviceSynchronize
xorl %ebx, %ebx
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %rax
subq %r15, %rax
movq 40(%rsp), %rcx
subq %r14, %rcx
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
addq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movq stderr(%rip), %rdi
divss .LCPI8_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movb $1, %bpl
movl $.L.str.5, %esi
movb $1, %al
callq fprintf
callq hipGetLastError
testl %eax, %eax
je .LBB8_26
# %bb.25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB8_26:
movl size(%rip), %eax
testl %eax, %eax
jle .LBB8_27
# %bb.28: # %.preheader.lr.ph
movq 24(%rsp), %rcx
movq 16(%rsp), %rsi
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_29: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_30 Depth 2
movq (%rcx,%rbx,8), %rdi
movq (%rsi,%rbx,8), %r8
xorl %edx, %edx
.p2align 4, 0x90
.LBB8_30: # Parent Loop BB8_29 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r8,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB8_33
jp .LBB8_33
# %bb.31: # in Loop: Header=BB8_30 Depth=2
incq %rdx
cmpq %rdx, %rax
jne .LBB8_30
# %bb.32: # %._crit_edge.loopexit
# in Loop: Header=BB8_29 Depth=1
movl %eax, %edx
.LBB8_33: # %._crit_edge
# in Loop: Header=BB8_29 Depth=1
incq %rbx
ucomiss %xmm1, %xmm0
jne .LBB8_35
jp .LBB8_35
# %bb.34: # %._crit_edge
# in Loop: Header=BB8_29 Depth=1
cmpq %rax, %rbx
jb .LBB8_29
.LBB8_35: # %._crit_edge86.loopexit
cmpeqss %xmm1, %xmm0
movd %xmm0, %ebp
andl $1, %ebp
testb %bpl, %bpl
je .LBB8_38
.LBB8_37:
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, size(%rip)
jg .LBB8_40
jmp .LBB8_42
.LBB8_27:
# implicit-def: $edx
testb %bpl, %bpl
jne .LBB8_37
.LBB8_38:
movl $.L.str.8, %edi
movl %ebx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
cmpl $0, size(%rip)
jle .LBB8_42
.LBB8_40: # %.lr.ph.i52.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_41: # %.lr.ph.i52
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
movslq size(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_41
.LBB8_42: # %_Z11free_matrixP6matrix.exit
movq 8(%rsp), %rdi
callq hipFree
cmpl $0, size(%rip)
jle .LBB8_45
# %bb.43: # %.lr.ph.i56.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_44: # %.lr.ph.i56
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
movslq size(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_44
.LBB8_45: # %_Z11free_matrixP6matrix.exit59
movq (%rsp), %rdi
callq hipFree
cmpl $0, size(%rip)
jle .LBB8_48
# %bb.46: # %.lr.ph.i61.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_47: # %.lr.ph.i61
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
movslq size(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_47
.LBB8_48: # %_Z11free_matrixP6matrix.exit64
movq 24(%rsp), %rdi
callq hipFree
cmpl $0, size(%rip)
jle .LBB8_51
# %bb.49: # %.lr.ph.i66.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_50: # %.lr.ph.i66
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
movslq size(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_50
.LBB8_51: # %_Z11free_matrixP6matrix.exit69
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z4workv, .Lfunc_end8-_Z4workv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
xorl %edi, %edi
callq srand
movq (%rbx), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $1024, %edx # imm = 0x400
cmpl $2, %ebp
jl .LBB9_2
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rdx
.LBB9_2:
movl %edx, size(%rip)
movq stderr(%rip), %rdi
movl $.L.str.10, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
callq _Z4workv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mm_kernel6matrixS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type size,@object # @size
.bss
.globl size
.p2align 2, 0x0
size:
.long 0 # 0x0
.size size, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type _Z9mm_kernel6matrixS_S_i,@object # @_Z9mm_kernel6matrixS_S_i
.section .rodata,"a",@progbits
.globl _Z9mm_kernel6matrixS_S_i
.p2align 3, 0x0
_Z9mm_kernel6matrixS_S_i:
.quad _Z24__device_stub__mm_kernel6matrixS_S_i
.size _Z9mm_kernel6matrixS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "row %4d: "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%6.2f "
.size .L.str.2, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Matrix multiplication on CPU took %1.2f seconds\n"
.size .L.str.4, 49
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Matrix multiplication on GPU took %1.2f seconds\n"
.size .L.str.5, 49
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Last CUDA error %s\n"
.size .L.str.6, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Difference in result matrices at element (%d, %d)!\n"
.size .L.str.8, 52
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Usage: %s <size>\n"
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Sequential matrix multiplication of size %d\n"
.size .L.str.10, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9mm_kernel6matrixS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The result matrices are identical!"
.size .Lstr, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mm_kernel6matrixS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mm_kernel6matrixS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9mm_kernel6matrixS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0030*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R4, R5, c[0x0][0x4], R2 ; /* 0x0000010005047a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R4, c[0x0][0x178], P0 ; /* 0x00005e0004007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fd60000011404 */
/*00d0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff068224 */
/* 0x000fe200078e00ff */
/*00e0*/ @!P0 BRA 0xc00 ; /* 0x00000b1000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R7, R0.reuse, 0x20, RZ ; /* 0x0000002000077810 */
/* 0x040fe20007ffe0ff */
/*0100*/ IMAD.SHL.U32 R13, R0.reuse, 0x4, RZ ; /* 0x00000004000d7824 */
/* 0x040fe200078e00ff */
/*0110*/ IADD3 R8, R0, 0x1, RZ ; /* 0x0000000100087810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.MOV.U32 R23, RZ, RZ, RZ ; /* 0x000000ffff177224 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff067212 */
/* 0x000fe400078e33ff */
/*0140*/ IMNMX R15, R7, R8, !PT ; /* 0x00000008070f7217 */
/* 0x000fe40007800200 */
/*0150*/ LEA R14, R2, 0x2000, 0x7 ; /* 0x00002000020e7811 */
/* 0x000fe400078e38ff */
/*0160*/ IADD3 R6, R15.reuse, R6, RZ ; /* 0x000000060f067210 */
/* 0x040fe20007ffe0ff */
/*0170*/ IMAD.IADD R22, R15, 0x1, -R0 ; /* 0x000000010f167824 */
/* 0x000fe200078e0a00 */
/*0180*/ LEA R18, R0, 0x2000, 0x7 ; /* 0x0000200000127811 */
/* 0x000fe200078e38ff */
/*0190*/ IMAD.IADD R11, R13, 0x1, R14 ; /* 0x000000010d0b7824 */
/* 0x000fe200078e020e */
/*01a0*/ SHF.R.S32.HI R16, RZ, 0x1f, R3 ; /* 0x0000001fff107819 */
/* 0x000fc40000011403 */
/*01b0*/ LEA R12, P0, R4, c[0x0][0x160], 0x3 ; /* 0x00005800040c7a11 */
/* 0x000fe200078018ff */
/*01c0*/ IMAD.IADD R18, R13.reuse, 0x1, R18 ; /* 0x000000010d127824 */
/* 0x040fe200078e0212 */
/*01d0*/ ISETP.GE.U32.AND P2, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe20003f46070 */
/*01e0*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*01f0*/ LEA R19, R2, R13, 0x8 ; /* 0x0000000d02137211 */
/* 0x000fe400078e40ff */
/*0200*/ IADD3 R20, R13, 0x2100, RZ ; /* 0x000021000d147810 */
/* 0x000fe40007ffe0ff */
/*0210*/ IADD3 R9, R0.reuse, 0x2, RZ ; /* 0x0000000200097810 */
/* 0x040fe40007ffe0ff */
/*0220*/ IADD3 R24, R0, 0x3, RZ ; /* 0x0000000300187810 */
/* 0x000fc40007ffe0ff */
/*0230*/ LEA R10, R2, 0x8, 0x8 ; /* 0x00000008020a7811 */
/* 0x000fe400078e40ff */
/*0240*/ SHF.L.U64.HI R21, R3, 0x2, R16 ; /* 0x0000000203157819 */
/* 0x000fe40000010210 */
/*0250*/ LEA.HI.X R13, R4, c[0x0][0x164], R5, 0x3, P0 ; /* 0x00005900040d7a11 */
/* 0x000fe400000f1c05 */
/*0260*/ LOP3.LUT R22, R22, 0x3, RZ, 0xc0, !PT ; /* 0x0000000316167812 */
/* 0x000fe400078ec0ff */
/*0270*/ MOV R27, 0x8 ; /* 0x00000008001b7802 */
/* 0x000fe20000000f00 */
/*0280*/ IMAD.IADD R26, R2, 0x1, R23 ; /* 0x00000001021a7824 */
/* 0x000fe200078e0217 */
/*0290*/ LDG.E.64 R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea6000c1e1b00 */
/*02a0*/ IMAD.WIDE.U32 R26, R26, R27, c[0x0][0x168] ; /* 0x00005a001a1a7625 */
/* 0x000fca00078e001b */
/*02b0*/ LDG.E.64 R14, [R26.64] ; /* 0x000000041a0e7981 */
/* 0x000ee2000c1e1b00 */
/*02c0*/ IMAD.IADD R25, R0, 0x1, R23 ; /* 0x0000000100197824 */
/* 0x000fc800078e0217 */
/*02d0*/ IMAD.WIDE.U32 R16, R25, 0x4, R16 ; /* 0x0000000419107825 */
/* 0x004fcc00078e0010 */
/*02e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ LEA R14, P0, R3, R14, 0x2 ; /* 0x0000000e030e7211 */
/* 0x008fc800078010ff */
/*0300*/ IADD3.X R15, R15, R21, RZ, P0, !PT ; /* 0x000000150f0f7210 */
/* 0x000fca00007fe4ff */
/*0310*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*0320*/ ISETP.NE.AND P0, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f05270 */
/*0330*/ BSSY B0, 0x4d0 ; /* 0x0000019000007945 */
/* 0x000fe20003800000 */
/*0340*/ IADD3 R23, R23, 0x20, RZ ; /* 0x0000002017177810 */
/* 0x000fe20007ffe0ff */
/*0350*/ IMAD.MOV.U32 R26, RZ, RZ, R0 ; /* 0x000000ffff1a7224 */
/* 0x000fc600078e0000 */
/*0360*/ ISETP.GE.AND P1, PT, R23, c[0x0][0x178], PT ; /* 0x00005e0017007a0c */
/* 0x000fe20003f26270 */
/*0370*/ STS [R19], R16 ; /* 0x0000001013007388 */
/* 0x0041e80000000800 */
/*0380*/ STS [R19+0x80], R16 ; /* 0x0000801013007388 */
/* 0x0001e80000000800 */
/*0390*/ STS [R11], R14 ; /* 0x0000000e0b007388 */
/* 0x0081e80000000800 */
/*03a0*/ STS [R11+0x1000], R14 ; /* 0x0010000e0b007388 */
/* 0x0001e80000000800 */
/*03b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03c0*/ @!P0 BRA 0x4c0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*03d0*/ LDS R15, [R18] ; /* 0x00000000120f7984 */
/* 0x001fe20000000800 */
/*03e0*/ ISETP.NE.AND P0, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fc40003f05270 */
/*03f0*/ MOV R26, R8 ; /* 0x00000008001a7202 */
/* 0x000fe20000000f00 */
/*0400*/ LDS R14, [R19] ; /* 0x00000000130e7984 */
/* 0x000e240000000800 */
/*0410*/ FFMA R6, R15, R14, R6 ; /* 0x0000000e0f067223 */
/* 0x001fd00000000006 */
/*0420*/ @!P0 BRA 0x4c0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.NE.AND P0, PT, R22, 0x2, PT ; /* 0x000000021600780c */
/* 0x000fe20003f05270 */
/*0440*/ LDS R15, [R18+0x80] ; /* 0x00008000120f7984 */
/* 0x000fe20000000800 */
/*0450*/ IMAD.MOV.U32 R26, RZ, RZ, R9 ; /* 0x000000ffff1a7224 */
/* 0x000fc600078e0009 */
/*0460*/ LDS R14, [R19+0x4] ; /* 0x00000400130e7984 */
/* 0x000e300000000800 */
/*0470*/ @P0 LDS R17, [R18+0x100] ; /* 0x0001000012110984 */
/* 0x000fe20000000800 */
/*0480*/ @P0 MOV R26, R24 ; /* 0x00000018001a0202 */
/* 0x000fc60000000f00 */
/*0490*/ @P0 LDS R16, [R19+0x8] ; /* 0x0000080013100984 */
/* 0x000e620000000800 */
/*04a0*/ FFMA R6, R15, R14, R6 ; /* 0x0000000e0f067223 */
/* 0x001fc80000000006 */
/*04b0*/ @P0 FFMA R6, R17, R16, R6 ; /* 0x0000001011060223 */
/* 0x002fe40000000006 */
/*04c0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*04d0*/ BSSY B0, 0xbe0 ; /* 0x0000070000007945 */
/* 0x000fe20003800000 */
/*04e0*/ @!P2 BRA 0xbd0 ; /* 0x000006e00000a947 */
/* 0x000fea0003800000 */
/*04f0*/ IMAD.IADD R14, R7, 0x1, -R26 ; /* 0x00000001070e7824 */
/* 0x000fe200078e0a1a */
/*0500*/ BSSY B1, 0x8e0 ; /* 0x000003d000017945 */
/* 0x000fe20003800000 */
/*0510*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*0520*/ LEA R15, R26, R20, 0x7 ; /* 0x000000141a0f7211 */
/* 0x000fe400078e38ff */
/*0530*/ ISETP.GT.AND P3, PT, R14, 0xc, PT ; /* 0x0000000c0e00780c */
/* 0x000fe20003f64270 */
/*0540*/ IMAD R14, R26, 0x4, R10 ; /* 0x000000041a0e7824 */
/* 0x000fd800078e020a */
/*0550*/ @!P3 BRA 0x8d0 ; /* 0x000003700000b947 */
/* 0x000fea0003800000 */
/*0560*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0570*/ IADD3 R17, R0, 0x14, RZ ; /* 0x0000001400117810 */
/* 0x000fe40007ffe0ff */
/*0580*/ LDS R25, [R15+-0x100] ; /* 0xffff00000f197984 */
/* 0x000fe20000000800 */
/*0590*/ IADD3 R26, R26, 0x10, RZ ; /* 0x000000101a1a7810 */
/* 0x000fc60007ffe0ff */
/*05a0*/ LDS R16, [R14+-0x8] ; /* 0xfffff8000e107984 */
/* 0x000e220000000800 */
/*05b0*/ ISETP.GE.AND P3, PT, R26, R17, PT ; /* 0x000000111a00720c */
/* 0x000fe20003f66270 */
/*05c0*/ FFMA R16, R25, R16, R6 ; /* 0x0000001019107223 */
/* 0x001fe40000000006 */
/*05d0*/ LDS R25, [R15+-0x80] ; /* 0xffff80000f197984 */
/* 0x000fe80000000800 */
/*05e0*/ LDS R6, [R14+-0x4] ; /* 0xfffffc000e067984 */
/* 0x000e240000000800 */
/*05f0*/ FFMA R6, R25, R6, R16 ; /* 0x0000000619067223 */
/* 0x001fc40000000010 */
/*0600*/ LDS R25, [R15] ; /* 0x000000000f197984 */
/* 0x000fe80000000800 */
/*0610*/ LDS R16, [R14] ; /* 0x000000000e107984 */
/* 0x000e240000000800 */
/*0620*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0630*/ LDS R25, [R15+0x80] ; /* 0x000080000f197984 */
/* 0x000fe80000000800 */
/*0640*/ LDS R16, [R14+0x4] ; /* 0x000004000e107984 */
/* 0x000e240000000800 */
/*0650*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*0660*/ LDS R25, [R15+0x100] ; /* 0x000100000f197984 */
/* 0x000fe80000000800 */
/*0670*/ LDS R16, [R14+0x8] ; /* 0x000008000e107984 */
/* 0x000e240000000800 */
/*0680*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0690*/ LDS R25, [R15+0x180] ; /* 0x000180000f197984 */
/* 0x000fe80000000800 */
/*06a0*/ LDS R16, [R14+0xc] ; /* 0x00000c000e107984 */
/* 0x000e240000000800 */
/*06b0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*06c0*/ LDS R25, [R15+0x200] ; /* 0x000200000f197984 */
/* 0x000fe80000000800 */
/*06d0*/ LDS R16, [R14+0x10] ; /* 0x000010000e107984 */
/* 0x000e240000000800 */
/*06e0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*06f0*/ LDS R25, [R15+0x280] ; /* 0x000280000f197984 */
/* 0x000fe80000000800 */
/*0700*/ LDS R16, [R14+0x14] ; /* 0x000014000e107984 */
/* 0x000e240000000800 */
/*0710*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*0720*/ LDS R25, [R15+0x300] ; /* 0x000300000f197984 */
/* 0x000fe80000000800 */
/*0730*/ LDS R16, [R14+0x18] ; /* 0x000018000e107984 */
/* 0x000e240000000800 */
/*0740*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0750*/ LDS R25, [R15+0x380] ; /* 0x000380000f197984 */
/* 0x000fe80000000800 */
/*0760*/ LDS R16, [R14+0x1c] ; /* 0x00001c000e107984 */
/* 0x000e240000000800 */
/*0770*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*0780*/ LDS R25, [R15+0x400] ; /* 0x000400000f197984 */
/* 0x000fe80000000800 */
/*0790*/ LDS R16, [R14+0x20] ; /* 0x000020000e107984 */
/* 0x000e240000000800 */
/*07a0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*07b0*/ LDS R25, [R15+0x480] ; /* 0x000480000f197984 */
/* 0x000fe80000000800 */
/*07c0*/ LDS R16, [R14+0x24] ; /* 0x000024000e107984 */
/* 0x000e240000000800 */
/*07d0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*07e0*/ LDS R25, [R15+0x500] ; /* 0x000500000f197984 */
/* 0x000fe80000000800 */
/*07f0*/ LDS R16, [R14+0x28] ; /* 0x000028000e107984 */
/* 0x000e240000000800 */
/*0800*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0810*/ LDS R25, [R15+0x580] ; /* 0x000580000f197984 */
/* 0x000fe80000000800 */
/*0820*/ LDS R16, [R14+0x2c] ; /* 0x00002c000e107984 */
/* 0x000e240000000800 */
/*0830*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fc40000000006 */
/*0840*/ LDS R25, [R15+0x600] ; /* 0x000600000f197984 */
/* 0x000fe80000000800 */
/*0850*/ LDS R16, [R14+0x30] ; /* 0x000030000e107984 */
/* 0x000e240000000800 */
/*0860*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x001fe40000000006 */
/*0870*/ LDS R25, [R15+0x680] ; /* 0x000680000f197984 */
/* 0x0001e80000000800 */
/*0880*/ LDS R16, [R14+0x34] ; /* 0x000034000e107984 */
/* 0x0002a20000000800 */
/*0890*/ IADD3 R15, R15, 0x800, RZ ; /* 0x000008000f0f7810 */
/* 0x001fc40007ffe0ff */
/*08a0*/ IADD3 R14, R14, 0x40, RZ ; /* 0x000000400e0e7810 */
/* 0x002fe20007ffe0ff */
/*08b0*/ FFMA R6, R25, R16, R6 ; /* 0x0000001019067223 */
/* 0x004fe20000000006 */
/*08c0*/ @!P3 BRA 0x580 ; /* 0xfffffcb00000b947 */
/* 0x000fea000383ffff */
/*08d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08e0*/ IADD3 R16, R7, -R26, RZ ; /* 0x8000001a07107210 */
/* 0x000fe20007ffe0ff */
/*08f0*/ BSSY B1, 0xaf0 ; /* 0x000001f000017945 */
/* 0x000fe60003800000 */
/*0900*/ ISETP.GT.AND P3, PT, R16, 0x4, PT ; /* 0x000000041000780c */
/* 0x000fda0003f64270 */
/*0910*/ @!P3 BRA 0xae0 ; /* 0x000001c00000b947 */
/* 0x000fea0003800000 */
/*0920*/ LDS R17, [R15+-0x100] ; /* 0xffff00000f117984 */
/* 0x000fe20000000800 */
/*0930*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0940*/ IADD3 R26, R26, 0x8, RZ ; /* 0x000000081a1a7810 */
/* 0x000fe20007ffe0ff */
/*0950*/ LDS R16, [R14+-0x8] ; /* 0xfffff8000e107984 */
/* 0x000e240000000800 */
/*0960*/ FFMA R16, R17, R16, R6 ; /* 0x0000001011107223 */
/* 0x001fe40000000006 */
/*0970*/ LDS R17, [R15+-0x80] ; /* 0xffff80000f117984 */
/* 0x000fe80000000800 */
/*0980*/ LDS R6, [R14+-0x4] ; /* 0xfffffc000e067984 */
/* 0x000e240000000800 */
/*0990*/ FFMA R6, R17, R6, R16 ; /* 0x0000000611067223 */
/* 0x001fc40000000010 */
/*09a0*/ LDS R17, [R15] ; /* 0x000000000f117984 */
/* 0x000fe80000000800 */
/*09b0*/ LDS R16, [R14] ; /* 0x000000000e107984 */
/* 0x000e240000000800 */
/*09c0*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fe40000000006 */
/*09d0*/ LDS R17, [R15+0x80] ; /* 0x000080000f117984 */
/* 0x000fe80000000800 */
/*09e0*/ LDS R16, [R14+0x4] ; /* 0x000004000e107984 */
/* 0x000e240000000800 */
/*09f0*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fc40000000006 */
/*0a00*/ LDS R17, [R15+0x100] ; /* 0x000100000f117984 */
/* 0x000fe80000000800 */
/*0a10*/ LDS R16, [R14+0x8] ; /* 0x000008000e107984 */
/* 0x000e240000000800 */
/*0a20*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fe40000000006 */
/*0a30*/ LDS R17, [R15+0x180] ; /* 0x000180000f117984 */
/* 0x000fe80000000800 */
/*0a40*/ LDS R16, [R14+0xc] ; /* 0x00000c000e107984 */
/* 0x000e240000000800 */
/*0a50*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fc40000000006 */
/*0a60*/ LDS R17, [R15+0x200] ; /* 0x000200000f117984 */
/* 0x000fe80000000800 */
/*0a70*/ LDS R16, [R14+0x10] ; /* 0x000010000e107984 */
/* 0x000e240000000800 */
/*0a80*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x001fe40000000006 */
/*0a90*/ LDS R17, [R15+0x280] ; /* 0x000280000f117984 */
/* 0x0001e80000000800 */
/*0aa0*/ LDS R16, [R14+0x14] ; /* 0x000014000e107984 */
/* 0x0002a20000000800 */
/*0ab0*/ IADD3 R15, R15, 0x400, RZ ; /* 0x000004000f0f7810 */
/* 0x001fc40007ffe0ff */
/*0ac0*/ IADD3 R14, R14, 0x20, RZ ; /* 0x000000200e0e7810 */
/* 0x002fe20007ffe0ff */
/*0ad0*/ FFMA R6, R17, R16, R6 ; /* 0x0000001011067223 */
/* 0x004fe40000000006 */
/*0ae0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0af0*/ ISETP.LT.OR P0, PT, R26, R7, P0 ; /* 0x000000071a00720c */
/* 0x000fda0000701670 */
/*0b00*/ @!P0 BRA 0xbd0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0b10*/ LDS R17, [R15+-0x100] ; /* 0xffff00000f117984 */
/* 0x000fe80000000800 */
/*0b20*/ LDS R16, [R14+-0x8] ; /* 0xfffff8000e107984 */
/* 0x000e280000000800 */
/*0b30*/ LDS R25, [R15] ; /* 0x000000000f197984 */
/* 0x000fe80000000800 */
/*0b40*/ LDS R26, [R14] ; /* 0x000000000e1a7984 */
/* 0x000fe80000000800 */
/*0b50*/ LDS R27, [R15+0x80] ; /* 0x000080000f1b7984 */
/* 0x000fe80000000800 */
/*0b60*/ LDS R28, [R14+0x4] ; /* 0x000004000e1c7984 */
/* 0x000fe20000000800 */
/*0b70*/ FFMA R16, R17, R16, R6 ; /* 0x0000001011107223 */
/* 0x001fc60000000006 */
/*0b80*/ LDS R17, [R15+-0x80] ; /* 0xffff80000f117984 */
/* 0x000fe80000000800 */
/*0b90*/ LDS R6, [R14+-0x4] ; /* 0xfffffc000e067984 */
/* 0x000e240000000800 */
/*0ba0*/ FFMA R6, R17, R6, R16 ; /* 0x0000000611067223 */
/* 0x001fc80000000010 */
/*0bb0*/ FFMA R6, R25, R26, R6 ; /* 0x0000001a19067223 */
/* 0x000fc80000000006 */
/*0bc0*/ FFMA R6, R27, R28, R6 ; /* 0x0000001c1b067223 */
/* 0x000fe40000000006 */
/*0bd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0be0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0bf0*/ @!P1 BRA 0x270 ; /* 0xfffff67000009947 */
/* 0x000fea000383ffff */
/*0c00*/ LEA R8, P0, R4, c[0x0][0x170], 0x3 ; /* 0x00005c0004087a11 */
/* 0x000fc800078018ff */
/*0c10*/ LEA.HI.X R9, R4, c[0x0][0x174], R5, 0x3, P0 ; /* 0x00005d0004097a11 */
/* 0x000fca00000f1c05 */
/*0c20*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea4000c1e1b00 */
/*0c30*/ IMAD.WIDE R4, R3, 0x4, R4 ; /* 0x0000000403047825 */
/* 0x004fca00078e0204 */
/*0c40*/ STG.E [R4.64], R6 ; /* 0x0000000604007986 */
/* 0x000fe2000c101904 */
/*0c50*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c60*/ BRA 0xc60; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9mm_kernel6matrixS_S_i
.globl _Z9mm_kernel6matrixS_S_i
.p2align 8
.type _Z9mm_kernel6matrixS_S_i,@function
_Z9mm_kernel6matrixS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[4:5]
v_mad_u64_u32 v[2:3], null, s15, s3, v[5:6]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v1, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_8
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_6
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v6, 2, v4
v_lshlrev_b64 v[8:9], 3, v[2:3]
s_movk_i32 s3, 0x84
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mad_u32_u24 v12, v4, s3, 0x2000
v_lshl_add_u32 v11, v5, 8, v6
v_lshl_add_u32 v10, v5, 7, v6
v_lshlrev_b64 v[6:7], 2, v[0:1]
s_mov_b32 s3, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v13, 0x80, v11
v_add_nc_u32_e32 v14, 0x2000, v10
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v15, 0x3000, v10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
.LBB0_3:
global_load_b64 v[16:17], v[8:9], off
v_dual_mov_b32 v19, 0 :: v_dual_add_nc_u32 v18, s3, v4
s_mov_b32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[20:21], 2, v[18:19]
v_add_nc_u32_e32 v18, s3, v5
v_lshlrev_b64 v[18:19], 3, v[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v18, vcc_lo, s6, v18
v_add_co_ci_u32_e32 v19, vcc_lo, s7, v19, vcc_lo
global_load_b64 v[18:19], v[18:19], off
s_waitcnt vmcnt(1)
v_add_co_u32 v16, vcc_lo, v16, v20
v_add_co_ci_u32_e32 v17, vcc_lo, v17, v21, vcc_lo
flat_load_b32 v20, v[16:17]
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_b32 v11, v20
ds_store_b32 v13, v20
v_add_co_u32 v16, vcc_lo, v18, v6
v_add_co_ci_u32_e32 v17, vcc_lo, v19, v7, vcc_lo
flat_load_b32 v17, v[16:17]
v_mov_b32_e32 v16, v12
s_waitcnt vmcnt(0) lgkmcnt(0)
ds_store_b32 v14, v17
ds_store_b32 v15, v17
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_4:
v_add_nc_u32_e32 v17, s4, v11
s_add_i32 s4, s4, 4
ds_load_b32 v18, v16
ds_load_b32 v17, v17
v_add_nc_u32_e32 v16, 0x80, v16
s_cmpk_lg_i32 s4, 0x80
s_waitcnt lgkmcnt(0)
v_fmac_f32_e32 v10, v17, v18
s_cbranch_scc1 .LBB0_4
s_add_i32 s3, s3, 32
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s3, s2
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_3
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v10, 0
.LBB0_7:
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b64 v[2:3], v[2:3], off
s_waitcnt vmcnt(0)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
flat_store_b32 v[0:1], v10
.LBB0_8:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9mm_kernel6matrixS_S_i
.amdhsa_group_segment_fixed_size 16384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9mm_kernel6matrixS_S_i, .Lfunc_end0-_Z9mm_kernel6matrixS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 16384
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9mm_kernel6matrixS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9mm_kernel6matrixS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00085aef_00000000-6_mm-banks.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z15wall_clock_timev
.type _Z15wall_clock_timev, @function
_Z15wall_clock_timev:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rsi
movl $0, %edi
call clock_gettime@PLT
imulq $1000000000, (%rsp), %rax
addq 8(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z15wall_clock_timev, .-_Z15wall_clock_timev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "CUDA error: %s\n"
.text
.globl _Z15allocate_matrixP6matrix
.type _Z15allocate_matrixP6matrix, @function
_Z15allocate_matrixP6matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
movslq size(%rip), %rsi
salq $3, %rsi
movl $1, %edx
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L8
movl size(%rip), %esi
movl $0, %ebx
testl %esi, %esi
jle .L7
.L9:
movslq %esi, %rsi
salq $2, %rsi
movq 0(%rbp), %rax
leaq (%rax,%rbx,8), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
testl %eax, %eax
jne .L16
movl size(%rip), %esi
addq $1, %rbx
cmpl %ebx, %esi
jg .L9
.L7:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L16:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z15allocate_matrixP6matrix, .-_Z15allocate_matrixP6matrix
.globl _Z11free_matrixP6matrix
.type _Z11free_matrixP6matrix, @function
_Z11free_matrixP6matrix:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rdi, %rbp
cmpl $0, size(%rip)
jle .L18
movl $0, %ebx
.L19:
movq 0(%rbp), %rax
movq (%rax,%rbx,8), %rdi
call cudaFree@PLT
addq $1, %rbx
cmpl %ebx, size(%rip)
jg .L19
.L18:
movq 0(%rbp), %rdi
call cudaFree@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z11free_matrixP6matrix, .-_Z11free_matrixP6matrix
.globl _Z11init_matrix6matrix
.type _Z11init_matrix6matrix, @function
_Z11init_matrix6matrix:
.LFB2060:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %r12
movl $0, %r13d
cmpl $0, size(%rip)
jg .L23
.L22:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call rand@PLT
movq (%r12,%rbp), %rcx
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx,%rbx,4)
addq $1, %rbx
cmpl %ebx, size(%rip)
jg .L25
.L27:
addq $1, %r13
cmpl %r13d, size(%rip)
jle .L22
.L23:
leaq 0(,%r13,8), %rbp
movl $0, %ebx
cmpl $0, size(%rip)
jg .L25
jmp .L27
.cfi_endproc
.LFE2060:
.size _Z11init_matrix6matrix, .-_Z11init_matrix6matrix
.globl _Z16init_matrix_zero6matrix
.type _Z16init_matrix_zero6matrix, @function
_Z16init_matrix_zero6matrix:
.LFB2061:
.cfi_startproc
endbr64
cmpl $0, size(%rip)
jle .L33
movl $0, %ecx
jmp .L35
.L36:
movq (%rdi), %rdx
movl $0x00000000, (%rdx,%rax,4)
addq $1, %rax
cmpl %eax, size(%rip)
jg .L36
.L37:
addl $1, %ecx
addq $8, %rdi
cmpl %ecx, size(%rip)
jle .L33
.L35:
movl $0, %eax
cmpl $0, size(%rip)
jg .L36
jmp .L37
.L33:
ret
.cfi_endproc
.LFE2061:
.size _Z16init_matrix_zero6matrix, .-_Z16init_matrix_zero6matrix
.globl _Z2mm6matrixS_S_
.type _Z2mm6matrixS_S_, @function
_Z2mm6matrixS_S_:
.LFB2062:
.cfi_startproc
endbr64
cmpl $0, size(%rip)
jle .L54
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %r8
movq %rsi, %r10
movq %rdx, %r9
movl $0, %ebx
jmp .L43
.L44:
movq %rcx, %rdx
addq (%r9), %rdx
movq (%r8), %rdi
movq (%r10,%rax,8), %rsi
movss (%rdi,%rax,4), %xmm0
mulss (%rsi,%rcx), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $1, %rax
cmpl %eax, size(%rip)
jg .L44
.L47:
addq $1, %r11
cmpl %r11d, size(%rip)
jle .L45
.L48:
leaq 0(,%r11,4), %rcx
movl $0, %eax
cmpl $0, size(%rip)
jg .L44
jmp .L47
.L45:
addl $1, %ebx
addq $8, %r9
addq $8, %r8
cmpl %ebx, size(%rip)
jle .L41
.L43:
movl $0, %r11d
cmpl $0, size(%rip)
jg .L48
jmp .L45
.L41:
popq %rbx
.cfi_def_cfa_offset 8
ret
.L54:
.cfi_restore 3
ret
.cfi_endproc
.LFE2062:
.size _Z2mm6matrixS_S_, .-_Z2mm6matrixS_S_
.section .rodata.str1.1
.LC2:
.string "row %4d: "
.LC3:
.string "%6.2f "
.LC4:
.string "\n"
.text
.globl _Z12print_matrix6matrix
.type _Z12print_matrix6matrix, @function
_Z12print_matrix6matrix:
.LFB2063:
.cfi_startproc
endbr64
cmpl $0, size(%rip)
jle .L65
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %r12
movl $0, %r14d
leaq .LC2(%rip), %r15
leaq .LC3(%rip), %r13
.L61:
movl %r14d, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, size(%rip)
jle .L59
leaq 0(,%r14,8), %rbp
movl $0, %ebx
.L60:
movq (%r12,%rbp), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, size(%rip)
jg .L60
.L59:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %r14
cmpl %r14d, size(%rip)
jg .L61
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2063:
.size _Z12print_matrix6matrix, .-_Z12print_matrix6matrix
.globl _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i
.type _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i, @function
_Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i:
.LFB2090:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %ecx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L72
.L68:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L73
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L72:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 152
pushq 24(%rsp)
.cfi_def_cfa_offset 160
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9mm_kernel6matrixS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L68
.L73:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i, .-_Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i
.globl _Z9mm_kernel6matrixS_S_i
.type _Z9mm_kernel6matrixS_S_i, @function
_Z9mm_kernel6matrixS_S_i:
.LFB2091:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
leaq 8(%rsp), %rdx
leaq 16(%rsp), %rsi
leaq 24(%rsp), %rdi
call _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z9mm_kernel6matrixS_S_i, .-_Z9mm_kernel6matrixS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC6:
.string "Matrix multiplication on CPU took %1.2f seconds\n"
.align 8
.LC7:
.string "Matrix multiplication on GPU took %1.2f seconds\n"
.section .rodata.str1.1
.LC8:
.string "Last CUDA error %s\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Difference in result matrices at element (%d, %d)!\n"
.align 8
.LC10:
.string "The result matrices are identical!\n"
.text
.globl _Z4workv
.type _Z4workv, @function
_Z4workv:
.LFB2064:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $96, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call _Z15allocate_matrixP6matrix
leaq 16(%rsp), %rdi
call _Z15allocate_matrixP6matrix
leaq 24(%rsp), %rdi
call _Z15allocate_matrixP6matrix
leaq 32(%rsp), %rdi
call _Z15allocate_matrixP6matrix
movq 8(%rsp), %rdi
call _Z11init_matrix6matrix
movq 16(%rsp), %rdi
call _Z11init_matrix6matrix
call _Z15wall_clock_timev
movq %rax, %rbx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z2mm6matrixS_S_
call _Z15wall_clock_timev
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $32, 64(%rsp)
movl $32, 68(%rsp)
movl $1, 72(%rsp)
movl size(%rip), %edx
testb $31, %dl
jne .L77
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
.L78:
movl %eax, 76(%rsp)
movl %eax, 80(%rsp)
movl $1, 84(%rsp)
call _Z15wall_clock_timev
movq %rax, %rbx
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L94
.L79:
call cudaDeviceSynchronize@PLT
call _Z15wall_clock_timev
subq %rbx, %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L95
.L80:
movl size(%rip), %r8d
movq 24(%rsp), %r10
movq 32(%rsp), %r9
movl $0, %edi
movslq %r8d, %rsi
jmp .L81
.L77:
leal 31(%rdx), %eax
testl %edx, %edx
cmovns %edx, %eax
sarl $5, %eax
addl $1, %eax
jmp .L78
.L94:
movq 8(%rsp), %rax
movq %rax, 40(%rsp)
movq 16(%rsp), %rax
movq %rax, 48(%rsp)
movq 32(%rsp), %rax
movq %rax, 56(%rsp)
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdi
movl size(%rip), %ecx
call _Z38__device_stub__Z9mm_kernel6matrixS_S_iR6matrixS0_S0_i
jmp .L79
.L95:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L80
.L87:
addq $1, %rdi
.L81:
cmpl %edi, %r8d
jle .L85
testl %r8d, %r8d
jle .L87
movq (%r10,%rdi,8), %rdx
movq (%r9,%rdi,8), %rax
movl $0, %ecx
.L84:
movss (%rdx,%rcx,4), %xmm0
ucomiss (%rax,%rcx,4), %xmm0
jp .L82
jne .L82
addq $1, %rcx
cmpq %rsi, %rcx
jne .L84
jmp .L87
.L82:
leal 1(%rdi), %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L88:
leaq 8(%rsp), %rdi
call _Z11free_matrixP6matrix
leaq 16(%rsp), %rdi
call _Z11free_matrixP6matrix
leaq 24(%rsp), %rdi
call _Z11free_matrixP6matrix
leaq 32(%rsp), %rdi
call _Z11free_matrixP6matrix
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L85:
.cfi_restore_state
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L88
.L96:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z4workv, .-_Z4workv
.section .rodata.str1.1
.LC11:
.string "Usage: %s <size>\n"
.section .rodata.str1.8
.align 8
.LC12:
.string "Sequential matrix multiplication of size %d\n"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebp
movq %rsi, %rbx
movl $0, %edi
call srand@PLT
movq (%rbx), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, %ecx
cmpl $1, %ebp
jg .L101
.L98:
movl %ecx, size(%rip)
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
call _Z4workv
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L101:
.cfi_restore_state
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ecx
jmp .L98
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC13:
.string "_Z9mm_kernel6matrixS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z9mm_kernel6matrixS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl size
.bss
.align 4
.type size, @object
.size size, 4
size:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1315859240
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mm-banks.hip"
.globl _Z15wall_clock_timev # -- Begin function _Z15wall_clock_timev
.p2align 4, 0x90
.type _Z15wall_clock_timev,@function
_Z15wall_clock_timev: # @_Z15wall_clock_timev
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
imulq $1000000000, 8(%rsp), %rax # imm = 0x3B9ACA00
addq 16(%rsp), %rax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z15wall_clock_timev, .Lfunc_end0-_Z15wall_clock_timev
.cfi_endproc
# -- End function
.globl _Z15allocate_matrixP6matrix # -- Begin function _Z15allocate_matrixP6matrix
.p2align 4, 0x90
.type _Z15allocate_matrixP6matrix,@function
_Z15allocate_matrixP6matrix: # @_Z15allocate_matrixP6matrix
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movslq size(%rip), %rsi
shlq $3, %rsi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_5
# %bb.1: # %.preheader
movl size(%rip), %eax
testl %eax, %eax
jle .LBB1_6
# %bb.2: # %.lr.ph.preheader
xorl %r14d, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rdi
addq %r14, %rdi
movslq %eax, %rsi
shlq $2, %rsi
movl $1, %edx
callq hipMallocManaged
testl %eax, %eax
jne .LBB1_5
# %bb.3: # in Loop: Header=BB1_4 Depth=1
incq %r15
movslq size(%rip), %rax
addq $8, %r14
cmpq %rax, %r15
jl .LBB1_4
.LBB1_6: # %._crit_edge
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 32
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %esi
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z15allocate_matrixP6matrix, .Lfunc_end1-_Z15allocate_matrixP6matrix
.cfi_endproc
# -- End function
.globl _Z11free_matrixP6matrix # -- Begin function _Z11free_matrixP6matrix
.p2align 4, 0x90
.type _Z11free_matrixP6matrix,@function
_Z11free_matrixP6matrix: # @_Z11free_matrixP6matrix
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rdi, %rbx
cmpl $0, size(%rip)
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%rbx), %rax
movq (%rax,%r14,8), %rdi
callq hipFree
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jl .LBB2_2
.LBB2_3: # %._crit_edge
movq (%rbx), %rdi
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
jmp hipFree # TAILCALL
.Lfunc_end2:
.size _Z11free_matrixP6matrix, .Lfunc_end2-_Z11free_matrixP6matrix
.cfi_endproc
# -- End function
.globl _Z11init_matrix6matrix # -- Begin function _Z11init_matrix6matrix
.p2align 4, 0x90
.type _Z11init_matrix6matrix,@function
_Z11init_matrix6matrix: # @_Z11init_matrix6matrix
.cfi_startproc
# %bb.0:
cmpl $0, size(%rip)
jle .LBB3_7
# %bb.1: # %.preheader.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jge .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
cmpl $0, size(%rip)
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%rbx,%r14,8), %rax
movss %xmm0, (%rax,%r15,4)
incq %r15
movslq size(%rip), %rax
cmpq %rax, %r15
jl .LBB3_4
jmp .LBB3_5
.LBB3_6:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB3_7: # %._crit_edge9
retq
.Lfunc_end3:
.size _Z11init_matrix6matrix, .Lfunc_end3-_Z11init_matrix6matrix
.cfi_endproc
# -- End function
.globl _Z16init_matrix_zero6matrix # -- Begin function _Z16init_matrix_zero6matrix
.p2align 4, 0x90
.type _Z16init_matrix_zero6matrix,@function
_Z16init_matrix_zero6matrix: # @_Z16init_matrix_zero6matrix
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl size(%rip), %r15d
testl %r15d, %r15d
jle .LBB4_3
# %bb.1: # %.preheader.lr.ph
movq %rdi, %rbx
leaq (,%r15,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movq (%rbx,%r12,8), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq memset@PLT
incq %r12
cmpq %r12, %r15
jne .LBB4_2
.LBB4_3: # %._crit_edge9
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z16init_matrix_zero6matrix, .Lfunc_end4-_Z16init_matrix_zero6matrix
.cfi_endproc
# -- End function
.globl _Z2mm6matrixS_S_ # -- Begin function _Z2mm6matrixS_S_
.p2align 4, 0x90
.type _Z2mm6matrixS_S_,@function
_Z2mm6matrixS_S_: # @_Z2mm6matrixS_S_
.cfi_startproc
# %bb.0:
movl size(%rip), %eax
testl %eax, %eax
jle .LBB5_8
# %bb.1: # %.preheader16.lr.ph
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_2: # %.preheader16
# =>This Loop Header: Depth=1
# Child Loop BB5_3 Depth 2
# Child Loop BB5_4 Depth 3
movq (%rdi,%rcx,8), %r8
movq (%rdx,%rcx,8), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB5_3: # %.preheader
# Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_4 Depth 3
movss (%r9,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# Parent Loop BB5_3 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r8,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq (%rsi,%r11,8), %rbx
mulss (%rbx,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r9,%r10,4)
incq %r11
cmpq %r11, %rax
jne .LBB5_4
# %bb.5: # %._crit_edge
# in Loop: Header=BB5_3 Depth=2
incq %r10
cmpq %rax, %r10
jne .LBB5_3
# %bb.6: # %._crit_edge19
# in Loop: Header=BB5_2 Depth=1
incq %rcx
cmpq %rax, %rcx
jne .LBB5_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.LBB5_8: # %._crit_edge21
retq
.Lfunc_end5:
.size _Z2mm6matrixS_S_, .Lfunc_end5-_Z2mm6matrixS_S_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__mm_kernel6matrixS_S_i # -- Begin function _Z24__device_stub__mm_kernel6matrixS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__mm_kernel6matrixS_S_i,@function
_Z24__device_stub__mm_kernel6matrixS_S_i: # @_Z24__device_stub__mm_kernel6matrixS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9mm_kernel6matrixS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end6:
.size _Z24__device_stub__mm_kernel6matrixS_S_i, .Lfunc_end6-_Z24__device_stub__mm_kernel6matrixS_S_i
.cfi_endproc
# -- End function
.globl _Z12print_matrix6matrix # -- Begin function _Z12print_matrix6matrix
.p2align 4, 0x90
.type _Z12print_matrix6matrix,@function
_Z12print_matrix6matrix: # @_Z12print_matrix6matrix
.cfi_startproc
# %bb.0:
cmpl $0, size(%rip)
jle .LBB7_7
# %bb.1: # %.lr.ph11.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
jmp .LBB7_2
.p2align 4, 0x90
.LBB7_5: # %._crit_edge
# in Loop: Header=BB7_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jge .LBB7_6
.LBB7_2: # %.lr.ph11
# =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
movl $.L.str.1, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
cmpl $0, size(%rip)
jle .LBB7_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB7_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB7_4: # Parent Loop BB7_2 Depth=1
# => This Inner Loop Header: Depth=2
movq (%rbx,%r14,8), %rax
movss (%rax,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
incq %r15
movslq size(%rip), %rax
cmpq %rax, %r15
jl .LBB7_4
jmp .LBB7_5
.LBB7_6:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB7_7: # %._crit_edge12
retq
.Lfunc_end7:
.size _Z12print_matrix6matrix, .Lfunc_end7-_Z12print_matrix6matrix
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z4workv
.LCPI8_0:
.long 0x4e6e6b28 # float 1.0E+9
.text
.globl _Z4workv
.p2align 4, 0x90
.type _Z4workv,@function
_Z4workv: # @_Z4workv
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 8(%rsp), %rdi
callq _Z15allocate_matrixP6matrix
movq %rsp, %rdi
callq _Z15allocate_matrixP6matrix
leaq 24(%rsp), %rdi
callq _Z15allocate_matrixP6matrix
leaq 16(%rsp), %rdi
callq _Z15allocate_matrixP6matrix
cmpl $0, size(%rip)
jle .LBB8_6
# %bb.1: # %.preheader.i.preheader
movq 8(%rsp), %rbx
xorl %r14d, %r14d
jmp .LBB8_2
.p2align 4, 0x90
.LBB8_5: # %._crit_edge.i
# in Loop: Header=BB8_2 Depth=1
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jge .LBB8_6
.LBB8_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB8_4 Depth 2
cmpl $0, size(%rip)
jle .LBB8_5
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB8_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_4: # Parent Loop BB8_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%rbx,%r14,8), %rax
movss %xmm0, (%rax,%r15,4)
incq %r15
movslq size(%rip), %rax
cmpq %rax, %r15
jl .LBB8_4
jmp .LBB8_5
.LBB8_6: # %_Z11init_matrix6matrix.exit
cmpl $0, size(%rip)
jle .LBB8_12
# %bb.7: # %.preheader.i39.preheader
movq (%rsp), %rbx
xorl %r14d, %r14d
jmp .LBB8_8
.p2align 4, 0x90
.LBB8_11: # %._crit_edge.i41
# in Loop: Header=BB8_8 Depth=1
incq %r14
movslq size(%rip), %rax
cmpq %rax, %r14
jge .LBB8_12
.LBB8_8: # %.preheader.i39
# =>This Loop Header: Depth=1
# Child Loop BB8_10 Depth 2
cmpl $0, size(%rip)
jle .LBB8_11
# %bb.9: # %.lr.ph.i43
# in Loop: Header=BB8_8 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB8_10: # Parent Loop BB8_8 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%rbx,%r14,8), %rax
movss %xmm0, (%rax,%r15,4)
incq %r15
movslq size(%rip), %rax
cmpq %rax, %r15
jl .LBB8_10
jmp .LBB8_11
.LBB8_12: # %_Z11init_matrix6matrix.exit46
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %r14
movq 40(%rsp), %rbx
movl size(%rip), %eax
testl %eax, %eax
jle .LBB8_19
# %bb.13: # %.preheader16.lr.ph.i
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq 24(%rsp), %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB8_14: # %.preheader16.i
# =>This Loop Header: Depth=1
# Child Loop BB8_15 Depth 2
# Child Loop BB8_16 Depth 3
movq (%rcx,%rdi,8), %r8
movq (%rsi,%rdi,8), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB8_15: # %.preheader.i47
# Parent Loop BB8_14 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB8_16 Depth 3
movss (%r9,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB8_16: # Parent Loop BB8_14 Depth=1
# Parent Loop BB8_15 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r8,%r11,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq (%rdx,%r11,8), %r15
mulss (%r15,%r10,4), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r9,%r10,4)
incq %r11
cmpq %r11, %rax
jne .LBB8_16
# %bb.17: # %._crit_edge.i50
# in Loop: Header=BB8_15 Depth=2
incq %r10
cmpq %rax, %r10
jne .LBB8_15
# %bb.18: # %._crit_edge19.i
# in Loop: Header=BB8_14 Depth=1
incq %rdi
cmpq %rax, %rdi
jne .LBB8_14
.LBB8_19: # %_Z2mm6matrixS_S_.exit
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %rax
subq %r14, %rax
movq 40(%rsp), %rcx
subq %rbx, %rcx
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
addq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movq stderr(%rip), %rdi
divss .LCPI8_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movb $1, %al
callq fprintf
movl size(%rip), %eax
testb $31, %al
jne .LBB8_21
# %bb.20:
sarl $5, %eax
jmp .LBB8_22
.LBB8_21:
leal 31(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
sarl $5, %ecx
incl %ecx
movl %ecx, %eax
.LBB8_22:
movl %eax, %eax
movq %rax, %rbx
shlq $32, %rbx
orq %rax, %rbx
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %r15
movq 40(%rsp), %r14
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB8_24
# %bb.23:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq 16(%rsp), %rdx
movl size(%rip), %esi
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movq %rdx, 128(%rsp)
movl %esi, 76(%rsp)
leaq 144(%rsp), %rax
movq %rax, 32(%rsp)
leaq 136(%rsp), %rax
movq %rax, 40(%rsp)
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 76(%rsp), %rax
movq %rax, 56(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 32(%rsp), %r9
movl $_Z9mm_kernel6matrixS_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB8_24:
callq hipDeviceSynchronize
xorl %ebx, %ebx
leaq 32(%rsp), %rsi
xorl %edi, %edi
callq clock_gettime
movq 32(%rsp), %rax
subq %r15, %rax
movq 40(%rsp), %rcx
subq %r14, %rcx
imulq $1000000000, %rax, %rax # imm = 0x3B9ACA00
addq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
movq stderr(%rip), %rdi
divss .LCPI8_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movb $1, %bpl
movl $.L.str.5, %esi
movb $1, %al
callq fprintf
callq hipGetLastError
testl %eax, %eax
je .LBB8_26
# %bb.25:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB8_26:
movl size(%rip), %eax
testl %eax, %eax
jle .LBB8_27
# %bb.28: # %.preheader.lr.ph
movq 24(%rsp), %rcx
movq 16(%rsp), %rsi
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_29: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB8_30 Depth 2
movq (%rcx,%rbx,8), %rdi
movq (%rsi,%rbx,8), %r8
xorl %edx, %edx
.p2align 4, 0x90
.LBB8_30: # Parent Loop BB8_29 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%rdx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss (%r8,%rdx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
ucomiss %xmm1, %xmm0
jne .LBB8_33
jp .LBB8_33
# %bb.31: # in Loop: Header=BB8_30 Depth=2
incq %rdx
cmpq %rdx, %rax
jne .LBB8_30
# %bb.32: # %._crit_edge.loopexit
# in Loop: Header=BB8_29 Depth=1
movl %eax, %edx
.LBB8_33: # %._crit_edge
# in Loop: Header=BB8_29 Depth=1
incq %rbx
ucomiss %xmm1, %xmm0
jne .LBB8_35
jp .LBB8_35
# %bb.34: # %._crit_edge
# in Loop: Header=BB8_29 Depth=1
cmpq %rax, %rbx
jb .LBB8_29
.LBB8_35: # %._crit_edge86.loopexit
cmpeqss %xmm1, %xmm0
movd %xmm0, %ebp
andl $1, %ebp
testb %bpl, %bpl
je .LBB8_38
.LBB8_37:
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, size(%rip)
jg .LBB8_40
jmp .LBB8_42
.LBB8_27:
# implicit-def: $edx
testb %bpl, %bpl
jne .LBB8_37
.LBB8_38:
movl $.L.str.8, %edi
movl %ebx, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
cmpl $0, size(%rip)
jle .LBB8_42
.LBB8_40: # %.lr.ph.i52.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_41: # %.lr.ph.i52
# =>This Inner Loop Header: Depth=1
movq 8(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
movslq size(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_41
.LBB8_42: # %_Z11free_matrixP6matrix.exit
movq 8(%rsp), %rdi
callq hipFree
cmpl $0, size(%rip)
jle .LBB8_45
# %bb.43: # %.lr.ph.i56.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_44: # %.lr.ph.i56
# =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
movslq size(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_44
.LBB8_45: # %_Z11free_matrixP6matrix.exit59
movq (%rsp), %rdi
callq hipFree
cmpl $0, size(%rip)
jle .LBB8_48
# %bb.46: # %.lr.ph.i61.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_47: # %.lr.ph.i61
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
movslq size(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_47
.LBB8_48: # %_Z11free_matrixP6matrix.exit64
movq 24(%rsp), %rdi
callq hipFree
cmpl $0, size(%rip)
jle .LBB8_51
# %bb.49: # %.lr.ph.i66.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB8_50: # %.lr.ph.i66
# =>This Inner Loop Header: Depth=1
movq 16(%rsp), %rax
movq (%rax,%rbx,8), %rdi
callq hipFree
incq %rbx
movslq size(%rip), %rax
cmpq %rax, %rbx
jl .LBB8_50
.LBB8_51: # %_Z11free_matrixP6matrix.exit69
movq 16(%rsp), %rdi
callq hipFree
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end8:
.size _Z4workv, .Lfunc_end8-_Z4workv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
xorl %edi, %edi
callq srand
movq (%rbx), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $1024, %edx # imm = 0x400
cmpl $2, %ebp
jl .LBB9_2
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rdx
.LBB9_2:
movl %edx, size(%rip)
movq stderr(%rip), %rdi
movl $.L.str.10, %esi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq fprintf
callq _Z4workv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size main, .Lfunc_end9-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9mm_kernel6matrixS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type size,@object # @size
.bss
.globl size
.p2align 2, 0x0
size:
.long 0 # 0x0
.size size, 4
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "CUDA error: %s\n"
.size .L.str, 16
.type _Z9mm_kernel6matrixS_S_i,@object # @_Z9mm_kernel6matrixS_S_i
.section .rodata,"a",@progbits
.globl _Z9mm_kernel6matrixS_S_i
.p2align 3, 0x0
_Z9mm_kernel6matrixS_S_i:
.quad _Z24__device_stub__mm_kernel6matrixS_S_i
.size _Z9mm_kernel6matrixS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "row %4d: "
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%6.2f "
.size .L.str.2, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Matrix multiplication on CPU took %1.2f seconds\n"
.size .L.str.4, 49
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Matrix multiplication on GPU took %1.2f seconds\n"
.size .L.str.5, 49
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Last CUDA error %s\n"
.size .L.str.6, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Difference in result matrices at element (%d, %d)!\n"
.size .L.str.8, 52
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Usage: %s <size>\n"
.size .L.str.9, 18
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Sequential matrix multiplication of size %d\n"
.size .L.str.10, 45
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9mm_kernel6matrixS_S_i"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "The result matrices are identical!"
.size .Lstr, 35
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__mm_kernel6matrixS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9mm_kernel6matrixS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
__global__ void vAdd(int* A, int* B, int* C, int num_elements){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < num_elements){
C[i] = A[i] + B[i];
}
}
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}
int main(){
int num_elements = 100000;
//Reservar espacio en memoria HOST
int * h_A = (int*)malloc(num_elements * sizeof(int));
int * h_B = (int*)malloc(num_elements * sizeof(int));
int * h_C = (int*)malloc(num_elements * sizeof(int));
//Inicializar elementos de los vectores
for(int i=0; i<num_elements; i++){
h_A[i] = 1;
h_B[i] = i;
}
cudaError_t err;
int size = num_elements * sizeof(int);
int * d_A = NULL;
err = cudaMalloc((void **)&d_A, size);
int * d_B = NULL;
err = cudaMalloc((void **)&d_B, size);
int * d_C = NULL;
err = cudaMalloc((void **)&d_C, size);
//Copiamos a GPU DEVICE
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
int HilosPorBloque = 512;
int BloquesPorGrid = (num_elements + HilosPorBloque -1) / HilosPorBloque;
//Lanzamos el kernel y medimos tiempos
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
vAdd<<<BloquesPorGrid, HilosPorBloque>>>(d_A, d_B, d_C, num_elements);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float tiempo_reserva_host;
cudaEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
cudaEventDestroy(start);
cudaEventDestroy(stop);
//Copiamos a CPU el vector C
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
//Realizamos la suma en la CPU
cudaEvent_t start1, stop1;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventRecord(start1, 0);
sumarVectores(h_A, h_B, h_C, num_elements);
cudaEventRecord(stop1,0);
cudaEventSynchronize(stop1);
float tiempo_reserva_host1;
cudaEventElapsedTime(&tiempo_reserva_host1, start1, stop1);
printf("Tiempo de suma vectores HOST: %f\n", tiempo_reserva_host1);
cudaEventDestroy(start1);
cudaEventDestroy(stop1);
/*for(int i=0; i<num_elements; i++){
printf("%i", h_C[i]);
printf("\n");
}*/
} | code for sm_80
Function : _Z4vAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
__global__ void vAdd(int* A, int* B, int* C, int num_elements){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < num_elements){
C[i] = A[i] + B[i];
}
}
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}
int main(){
int num_elements = 100000;
//Reservar espacio en memoria HOST
int * h_A = (int*)malloc(num_elements * sizeof(int));
int * h_B = (int*)malloc(num_elements * sizeof(int));
int * h_C = (int*)malloc(num_elements * sizeof(int));
//Inicializar elementos de los vectores
for(int i=0; i<num_elements; i++){
h_A[i] = 1;
h_B[i] = i;
}
cudaError_t err;
int size = num_elements * sizeof(int);
int * d_A = NULL;
err = cudaMalloc((void **)&d_A, size);
int * d_B = NULL;
err = cudaMalloc((void **)&d_B, size);
int * d_C = NULL;
err = cudaMalloc((void **)&d_C, size);
//Copiamos a GPU DEVICE
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
int HilosPorBloque = 512;
int BloquesPorGrid = (num_elements + HilosPorBloque -1) / HilosPorBloque;
//Lanzamos el kernel y medimos tiempos
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
vAdd<<<BloquesPorGrid, HilosPorBloque>>>(d_A, d_B, d_C, num_elements);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float tiempo_reserva_host;
cudaEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
cudaEventDestroy(start);
cudaEventDestroy(stop);
//Copiamos a CPU el vector C
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
//Realizamos la suma en la CPU
cudaEvent_t start1, stop1;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventRecord(start1, 0);
sumarVectores(h_A, h_B, h_C, num_elements);
cudaEventRecord(stop1,0);
cudaEventSynchronize(stop1);
float tiempo_reserva_host1;
cudaEventElapsedTime(&tiempo_reserva_host1, start1, stop1);
printf("Tiempo de suma vectores HOST: %f\n", tiempo_reserva_host1);
cudaEventDestroy(start1);
cudaEventDestroy(stop1);
/*for(int i=0; i<num_elements; i++){
printf("%i", h_C[i]);
printf("\n");
}*/
} | .file "tmpxft_000c6cd4_00000000-6_vAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13sumarVectoresPiS_S_i
.type _Z13sumarVectoresPiS_S_i, @function
_Z13sumarVectoresPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z13sumarVectoresPiS_S_i, .-_Z13sumarVectoresPiS_S_i
.globl _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i
.type _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i, @function
_Z28__device_stub__Z4vAddPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4vAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i, .-_Z28__device_stub__Z4vAddPiS_S_iPiS_S_i
.globl _Z4vAddPiS_S_i
.type _Z4vAddPiS_S_i, @function
_Z4vAddPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4vAddPiS_S_i, .-_Z4vAddPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Tiempo de suma vectores DEVICE: %f\n"
.align 8
.LC1:
.string "Tiempo de suma vectores HOST: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $400000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L16:
movl $1, (%rbx,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $100000, %rax
jne .L16
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $512, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $196, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $400000, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $100000, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z13sumarVectoresPiS_S_i
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 72(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $100000, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z4vAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4vAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>
__global__ void vAdd(int* A, int* B, int* C, int num_elements){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < num_elements){
C[i] = A[i] + B[i];
}
}
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}
int main(){
int num_elements = 100000;
//Reservar espacio en memoria HOST
int * h_A = (int*)malloc(num_elements * sizeof(int));
int * h_B = (int*)malloc(num_elements * sizeof(int));
int * h_C = (int*)malloc(num_elements * sizeof(int));
//Inicializar elementos de los vectores
for(int i=0; i<num_elements; i++){
h_A[i] = 1;
h_B[i] = i;
}
cudaError_t err;
int size = num_elements * sizeof(int);
int * d_A = NULL;
err = cudaMalloc((void **)&d_A, size);
int * d_B = NULL;
err = cudaMalloc((void **)&d_B, size);
int * d_C = NULL;
err = cudaMalloc((void **)&d_C, size);
//Copiamos a GPU DEVICE
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
err = cudaMemcpy(d_C, h_C, size, cudaMemcpyHostToDevice);
int HilosPorBloque = 512;
int BloquesPorGrid = (num_elements + HilosPorBloque -1) / HilosPorBloque;
//Lanzamos el kernel y medimos tiempos
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
vAdd<<<BloquesPorGrid, HilosPorBloque>>>(d_A, d_B, d_C, num_elements);
cudaEventRecord(stop,0);
cudaEventSynchronize(stop);
float tiempo_reserva_host;
cudaEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
cudaEventDestroy(start);
cudaEventDestroy(stop);
//Copiamos a CPU el vector C
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
//Realizamos la suma en la CPU
cudaEvent_t start1, stop1;
cudaEventCreate(&start1);
cudaEventCreate(&stop1);
cudaEventRecord(start1, 0);
sumarVectores(h_A, h_B, h_C, num_elements);
cudaEventRecord(stop1,0);
cudaEventSynchronize(stop1);
float tiempo_reserva_host1;
cudaEventElapsedTime(&tiempo_reserva_host1, start1, stop1);
printf("Tiempo de suma vectores HOST: %f\n", tiempo_reserva_host1);
cudaEventDestroy(start1);
cudaEventDestroy(stop1);
/*for(int i=0; i<num_elements; i++){
printf("%i", h_C[i]);
printf("\n");
}*/
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
__global__ void vAdd(int* A, int* B, int* C, int num_elements){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < num_elements){
C[i] = A[i] + B[i];
}
}
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}
int main(){
int num_elements = 100000;
//Reservar espacio en memoria HOST
int * h_A = (int*)malloc(num_elements * sizeof(int));
int * h_B = (int*)malloc(num_elements * sizeof(int));
int * h_C = (int*)malloc(num_elements * sizeof(int));
//Inicializar elementos de los vectores
for(int i=0; i<num_elements; i++){
h_A[i] = 1;
h_B[i] = i;
}
hipError_t err;
int size = num_elements * sizeof(int);
int * d_A = NULL;
err = hipMalloc((void **)&d_A, size);
int * d_B = NULL;
err = hipMalloc((void **)&d_B, size);
int * d_C = NULL;
err = hipMalloc((void **)&d_C, size);
//Copiamos a GPU DEVICE
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
err = hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
int HilosPorBloque = 512;
int BloquesPorGrid = (num_elements + HilosPorBloque -1) / HilosPorBloque;
//Lanzamos el kernel y medimos tiempos
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
vAdd<<<BloquesPorGrid, HilosPorBloque>>>(d_A, d_B, d_C, num_elements);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float tiempo_reserva_host;
hipEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
hipEventDestroy(start);
hipEventDestroy(stop);
//Copiamos a CPU el vector C
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
//Realizamos la suma en la CPU
hipEvent_t start1, stop1;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventRecord(start1, 0);
sumarVectores(h_A, h_B, h_C, num_elements);
hipEventRecord(stop1,0);
hipEventSynchronize(stop1);
float tiempo_reserva_host1;
hipEventElapsedTime(&tiempo_reserva_host1, start1, stop1);
printf("Tiempo de suma vectores HOST: %f\n", tiempo_reserva_host1);
hipEventDestroy(start1);
hipEventDestroy(stop1);
/*for(int i=0; i<num_elements; i++){
printf("%i", h_C[i]);
printf("\n");
}*/
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
__global__ void vAdd(int* A, int* B, int* C, int num_elements){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < num_elements){
C[i] = A[i] + B[i];
}
}
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}
int main(){
int num_elements = 100000;
//Reservar espacio en memoria HOST
int * h_A = (int*)malloc(num_elements * sizeof(int));
int * h_B = (int*)malloc(num_elements * sizeof(int));
int * h_C = (int*)malloc(num_elements * sizeof(int));
//Inicializar elementos de los vectores
for(int i=0; i<num_elements; i++){
h_A[i] = 1;
h_B[i] = i;
}
hipError_t err;
int size = num_elements * sizeof(int);
int * d_A = NULL;
err = hipMalloc((void **)&d_A, size);
int * d_B = NULL;
err = hipMalloc((void **)&d_B, size);
int * d_C = NULL;
err = hipMalloc((void **)&d_C, size);
//Copiamos a GPU DEVICE
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
err = hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
int HilosPorBloque = 512;
int BloquesPorGrid = (num_elements + HilosPorBloque -1) / HilosPorBloque;
//Lanzamos el kernel y medimos tiempos
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
vAdd<<<BloquesPorGrid, HilosPorBloque>>>(d_A, d_B, d_C, num_elements);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float tiempo_reserva_host;
hipEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
hipEventDestroy(start);
hipEventDestroy(stop);
//Copiamos a CPU el vector C
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
//Realizamos la suma en la CPU
hipEvent_t start1, stop1;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventRecord(start1, 0);
sumarVectores(h_A, h_B, h_C, num_elements);
hipEventRecord(stop1,0);
hipEventSynchronize(stop1);
float tiempo_reserva_host1;
hipEventElapsedTime(&tiempo_reserva_host1, start1, stop1);
printf("Tiempo de suma vectores HOST: %f\n", tiempo_reserva_host1);
hipEventDestroy(start1);
hipEventDestroy(stop1);
/*for(int i=0; i<num_elements; i++){
printf("%i", h_C[i]);
printf("\n");
}*/
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4vAddPiS_S_i
.globl _Z4vAddPiS_S_i
.p2align 8
.type _Z4vAddPiS_S_i,@function
_Z4vAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4vAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4vAddPiS_S_i, .Lfunc_end0-_Z4vAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4vAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4vAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>
__global__ void vAdd(int* A, int* B, int* C, int num_elements){
//Posicion del thread
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i < num_elements){
C[i] = A[i] + B[i];
}
}
void sumarVectores(int* A, int* B, int* C, int num_elements){
//Posicion del thread
//int i = blockIdx.x * blockDim.x + threadIdx.x;
for(int i=0; i<num_elements; i++){
C[i] = A[i] + B[i];
}
}
int main(){
int num_elements = 100000;
//Reservar espacio en memoria HOST
int * h_A = (int*)malloc(num_elements * sizeof(int));
int * h_B = (int*)malloc(num_elements * sizeof(int));
int * h_C = (int*)malloc(num_elements * sizeof(int));
//Inicializar elementos de los vectores
for(int i=0; i<num_elements; i++){
h_A[i] = 1;
h_B[i] = i;
}
hipError_t err;
int size = num_elements * sizeof(int);
int * d_A = NULL;
err = hipMalloc((void **)&d_A, size);
int * d_B = NULL;
err = hipMalloc((void **)&d_B, size);
int * d_C = NULL;
err = hipMalloc((void **)&d_C, size);
//Copiamos a GPU DEVICE
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
err = hipMemcpy(d_C, h_C, size, hipMemcpyHostToDevice);
int HilosPorBloque = 512;
int BloquesPorGrid = (num_elements + HilosPorBloque -1) / HilosPorBloque;
//Lanzamos el kernel y medimos tiempos
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
vAdd<<<BloquesPorGrid, HilosPorBloque>>>(d_A, d_B, d_C, num_elements);
hipEventRecord(stop,0);
hipEventSynchronize(stop);
float tiempo_reserva_host;
hipEventElapsedTime(&tiempo_reserva_host, start, stop);
printf("Tiempo de suma vectores DEVICE: %f\n", tiempo_reserva_host);
hipEventDestroy(start);
hipEventDestroy(stop);
//Copiamos a CPU el vector C
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
//Realizamos la suma en la CPU
hipEvent_t start1, stop1;
hipEventCreate(&start1);
hipEventCreate(&stop1);
hipEventRecord(start1, 0);
sumarVectores(h_A, h_B, h_C, num_elements);
hipEventRecord(stop1,0);
hipEventSynchronize(stop1);
float tiempo_reserva_host1;
hipEventElapsedTime(&tiempo_reserva_host1, start1, stop1);
printf("Tiempo de suma vectores HOST: %f\n", tiempo_reserva_host1);
hipEventDestroy(start1);
hipEventDestroy(stop1);
/*for(int i=0; i<num_elements; i++){
printf("%i", h_C[i]);
printf("\n");
}*/
} | .text
.file "vAdd.hip"
.globl _Z19__device_stub__vAddPiS_S_i # -- Begin function _Z19__device_stub__vAddPiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__vAddPiS_S_i,@function
_Z19__device_stub__vAddPiS_S_i: # @_Z19__device_stub__vAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4vAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__vAddPiS_S_i, .Lfunc_end0-_Z19__device_stub__vAddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13sumarVectoresPiS_S_i # -- Begin function _Z13sumarVectoresPiS_S_i
.p2align 4, 0x90
.type _Z13sumarVectoresPiS_S_i,@function
_Z13sumarVectoresPiS_S_i: # @_Z13sumarVectoresPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13sumarVectoresPiS_S_i, .Lfunc_end1-_Z13sumarVectoresPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB2_1
# %bb.2:
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq 56(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967492, %rdi # imm = 0x1000000C4
leaq 316(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 64(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl $100000, 76(%rsp) # imm = 0x186A0
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 160(%rsp), %rax
movq %rax, 104(%rsp)
leaq 152(%rsp), %rax
movq %rax, 112(%rsp)
leaq 76(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4vAddPiS_S_i, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 24(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %eax
addl (%rbx,%r12,4), %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq $100000, %r12 # imm = 0x186A0
jne .LBB2_5
# %bb.6: # %_Z13sumarVectoresPiS_S_i.exit
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 96(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4vAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4vAddPiS_S_i,@object # @_Z4vAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z4vAddPiS_S_i
.p2align 3, 0x0
_Z4vAddPiS_S_i:
.quad _Z19__device_stub__vAddPiS_S_i
.size _Z4vAddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tiempo de suma vectores DEVICE: %f\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Tiempo de suma vectores HOST: %f\n"
.size .L.str.1, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4vAddPiS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__vAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4vAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4vAddPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4vAddPiS_S_i
.globl _Z4vAddPiS_S_i
.p2align 8
.type _Z4vAddPiS_S_i,@function
_Z4vAddPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4vAddPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4vAddPiS_S_i, .Lfunc_end0-_Z4vAddPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4vAddPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4vAddPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c6cd4_00000000-6_vAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13sumarVectoresPiS_S_i
.type _Z13sumarVectoresPiS_S_i, @function
_Z13sumarVectoresPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z13sumarVectoresPiS_S_i, .-_Z13sumarVectoresPiS_S_i
.globl _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i
.type _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i, @function
_Z28__device_stub__Z4vAddPiS_S_iPiS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4vAddPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i, .-_Z28__device_stub__Z4vAddPiS_S_iPiS_S_i
.globl _Z4vAddPiS_S_i
.type _Z4vAddPiS_S_i, @function
_Z4vAddPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4vAddPiS_S_i, .-_Z4vAddPiS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Tiempo de suma vectores DEVICE: %f\n"
.align 8
.LC1:
.string "Tiempo de suma vectores HOST: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $96, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $400000, %edi
call malloc@PLT
movq %rax, %rbx
movl $400000, %edi
call malloc@PLT
movq %rax, %rbp
movl $400000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L16:
movl $1, (%rbx,%rax,4)
movl %eax, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $100000, %rax
jne .L16
movq $0, 16(%rsp)
leaq 16(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movq $0, 24(%rsp)
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400000, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
movl $512, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $196, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movq 48(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 8(%rsp), %rdi
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movl $2, %ecx
movl $400000, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $100000, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq %rbx, %rdi
call _Z13sumarVectoresPiS_S_i
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 12(%rsp), %rdi
movq 72(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 12(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 72(%rsp), %rdi
call cudaEventDestroy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $96, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $100000, %ecx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z28__device_stub__Z4vAddPiS_S_iPiS_S_i
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z4vAddPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z4vAddPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vAdd.hip"
.globl _Z19__device_stub__vAddPiS_S_i # -- Begin function _Z19__device_stub__vAddPiS_S_i
.p2align 4, 0x90
.type _Z19__device_stub__vAddPiS_S_i,@function
_Z19__device_stub__vAddPiS_S_i: # @_Z19__device_stub__vAddPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4vAddPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__vAddPiS_S_i, .Lfunc_end0-_Z19__device_stub__vAddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z13sumarVectoresPiS_S_i # -- Begin function _Z13sumarVectoresPiS_S_i
.p2align 4, 0x90
.type _Z13sumarVectoresPiS_S_i,@function
_Z13sumarVectoresPiS_S_i: # @_Z13sumarVectoresPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13sumarVectoresPiS_S_i, .Lfunc_end1-_Z13sumarVectoresPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $168, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %rbx
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r14
movl $400000, %edi # imm = 0x61A80
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%rax,4)
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $100000, %rax # imm = 0x186A0
jne .LBB2_1
# %bb.2:
movq $0, 56(%rsp)
leaq 56(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq $0, 48(%rsp)
leaq 48(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq $0, 32(%rsp)
leaq 32(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
movq 56(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movl $400000, %edx # imm = 0x61A80
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 40(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967492, %rdi # imm = 0x1000000C4
leaq 316(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 32(%rsp), %rdx
movq %rax, 64(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl $100000, 76(%rsp) # imm = 0x186A0
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 160(%rsp), %rax
movq %rax, 104(%rsp)
leaq 152(%rsp), %rax
movq %rax, 112(%rsp)
leaq 76(%rsp), %rax
movq %rax, 120(%rsp)
leaq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 144(%rsp), %rdx
leaq 136(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z4vAddPiS_S_i, %edi
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq 24(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 96(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 96(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB2_5: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%r12,4), %eax
addl (%rbx,%r12,4), %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq $100000, %r12 # imm = 0x186A0
jne .LBB2_5
# %bb.6: # %_Z13sumarVectoresPiS_S_i.exit
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 96(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
movq 96(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4vAddPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4vAddPiS_S_i,@object # @_Z4vAddPiS_S_i
.section .rodata,"a",@progbits
.globl _Z4vAddPiS_S_i
.p2align 3, 0x0
_Z4vAddPiS_S_i:
.quad _Z19__device_stub__vAddPiS_S_i
.size _Z4vAddPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Tiempo de suma vectores DEVICE: %f\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Tiempo de suma vectores HOST: %f\n"
.size .L.str.1, 34
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4vAddPiS_S_i"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__vAddPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4vAddPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <iostream>
struct soma_impares {
__device__ __host__
int operator()(const double &x, const double &y) {
return x + y;
}
};
int main() {
thrust::device_vector<double> v(100);
thrust::sequence(v.begin(), v.end());
double d = thrust::reduce(v.begin(), v.end(), 0.0, soma_impares());
std::cout << v[99] << " " << d << "\n";
return 0;
} | #include <hip/hip_runtime.h>
#include <thrust/device_vector.h>
#include <thrust/fill.h>
#include <thrust/sequence.h>
#include <iostream>
struct soma_impares {
__device__ __host__
int operator()(const double &x, const double &y) {
return x + y;
}
};
int main() {
thrust::device_vector<double> v(100);
thrust::sequence(v.begin(), v.end());
double d = thrust::reduce(v.begin(), v.end(), 0.0, soma_impares());
std::cout << v[99] << " " << d << "\n";
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define N 64
//#define N 128
//#define N 1024
//#define N 63
//#define N 65
//#define N 4096
#define TPB 32
//#define TPB 1
float scale(int i, int n){
return ((float) i)/(n - 1);
}
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
float x = 0;
//if(i>N-1)
// return;
x = d_in[i];
d_out[i] = distance(x, ref);
if(0)
{
printf("blockIdx:%2d,blockDim:%2d,threadIdx:%2d, i = %2d: dist from %f to %f.\n",
blockIdx.x,blockDim.x,threadIdx.x,i, ref, x, d_out[i]);
}
//if(i==4095) printf("find 4095\n");
}
int main(){
const float ref = 0.5f;
float *in = 0;
float *out = 0;
cudaMallocManaged(&in, N*sizeof(float));
cudaMallocManaged(&out, N*sizeof(float));
for(int i=0;i<N;++i)
in[i]=scale(i,N);
distanceKernel<<<(N+TPB-1)/TPB, TPB>>>(out, in, ref);
cudaDeviceSynchronize();
cudaFree(in);
cudaFree(out);
return 0;
} | code for sm_80
Function : _Z14distanceKernelPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x170 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0090*/ FADD R4, -R2, c[0x0][0x170] ; /* 0x00005c0002047621 */
/* 0x004fc80000000100 */
/*00a0*/ FMUL R4, R4, R4 ; /* 0x0000000404047220 */
/* 0x000fc80000400000 */
/*00b0*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*00c0*/ IADD3 R6, R4, -0xd000000, RZ ; /* 0xf300000004067810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*00e0*/ @!P0 BRA 0x120 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R8, 0x110 ; /* 0x0000011000087802 */
/* 0x003fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x1b0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BRA 0x160 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0120*/ FMUL.FTZ R3, R4, R5 ; /* 0x0000000504037220 */
/* 0x003fe40000410000 */
/*0130*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0140*/ FFMA R4, -R3, R3, R4 ; /* 0x0000000303047223 */
/* 0x000fc80000000104 */
/*0150*/ FFMA R5, R4, R5, R3 ; /* 0x0000000504057223 */
/* 0x000fe40000000003 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0180*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0190*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c0ff */
/*01c0*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*01d0*/ @!P0 BRA 0x2e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01e0*/ FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fda0003f1e000 */
/*01f0*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0200*/ @!P0 BRA 0x2e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0210*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0220*/ @P0 FADD.FTZ R2, R4, 1 ; /* 0x3f80000004020421 */
/* 0x000fe20000010000 */
/*0230*/ @P0 BRA 0x2e0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0240*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*0250*/ @P0 FFMA R3, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004030823 */
/* 0x000fc800000000ff */
/*0260*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*0270*/ @P0 FMUL.FTZ R6, R3, R2 ; /* 0x0000000203060220 */
/* 0x001fe40000410000 */
/*0280*/ @P0 FMUL.FTZ R7, R2, 0.5 ; /* 0x3f00000002070820 */
/* 0x000fe20000410000 */
/*0290*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*02a0*/ @P0 FADD.FTZ R5, -R6, -RZ ; /* 0x800000ff06050221 */
/* 0x000fc80000010100 */
/*02b0*/ @P0 FFMA R5, R6, R5, R3 ; /* 0x0000000506050223 */
/* 0x000fc80000000003 */
/*02c0*/ @P0 FFMA R5, R5, R7, R6 ; /* 0x0000000705050223 */
/* 0x000fc80000000006 */
/*02d0*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*02e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*02f0*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x000fe40000000f00 */
/*0300*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0310*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffce002007950 */
/* 0x000fea0003c3ffff */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 64
//#define N 128
//#define N 1024
//#define N 63
//#define N 65
//#define N 4096
#define TPB 32
//#define TPB 1
float scale(int i, int n){
return ((float) i)/(n - 1);
}
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
float x = 0;
//if(i>N-1)
// return;
x = d_in[i];
d_out[i] = distance(x, ref);
if(0)
{
printf("blockIdx:%2d,blockDim:%2d,threadIdx:%2d, i = %2d: dist from %f to %f.\n",
blockIdx.x,blockDim.x,threadIdx.x,i, ref, x, d_out[i]);
}
//if(i==4095) printf("find 4095\n");
}
int main(){
const float ref = 0.5f;
float *in = 0;
float *out = 0;
cudaMallocManaged(&in, N*sizeof(float));
cudaMallocManaged(&out, N*sizeof(float));
for(int i=0;i<N;++i)
in[i]=scale(i,N);
distanceKernel<<<(N+TPB-1)/TPB, TPB>>>(out, in, ref);
cudaDeviceSynchronize();
cudaFree(in);
cudaFree(out);
return 0;
} | .file "tmpxft_0002cfe3_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
subl $1, %esi
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
divss %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
.type _Z37__device_stub__Z14distanceKernelPfS_fPfS_f, @function
_Z37__device_stub__Z14distanceKernelPfS_fPfS_f:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14distanceKernelPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z14distanceKernelPfS_fPfS_f, .-_Z37__device_stub__Z14distanceKernelPfS_fPfS_f
.globl _Z14distanceKernelPfS_f
.type _Z14distanceKernelPfS_f, @function
_Z14distanceKernelPfS_f:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPfS_f, .-_Z14distanceKernelPfS_f
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $1, %edx
movl $256, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $256, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
.L15:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm1, %xmm0
movq (%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L15
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movss .LC1(%rip), %xmm0
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z14distanceKernelPfS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1115422720
.align 4
.LC1:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 64
//#define N 128
//#define N 1024
//#define N 63
//#define N 65
//#define N 4096
#define TPB 32
//#define TPB 1
float scale(int i, int n){
return ((float) i)/(n - 1);
}
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
float x = 0;
//if(i>N-1)
// return;
x = d_in[i];
d_out[i] = distance(x, ref);
if(0)
{
printf("blockIdx:%2d,blockDim:%2d,threadIdx:%2d, i = %2d: dist from %f to %f.\n",
blockIdx.x,blockDim.x,threadIdx.x,i, ref, x, d_out[i]);
}
//if(i==4095) printf("find 4095\n");
}
int main(){
const float ref = 0.5f;
float *in = 0;
float *out = 0;
cudaMallocManaged(&in, N*sizeof(float));
cudaMallocManaged(&out, N*sizeof(float));
for(int i=0;i<N;++i)
in[i]=scale(i,N);
distanceKernel<<<(N+TPB-1)/TPB, TPB>>>(out, in, ref);
cudaDeviceSynchronize();
cudaFree(in);
cudaFree(out);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 64
//#define N 128
//#define N 1024
//#define N 63
//#define N 65
//#define N 4096
#define TPB 32
//#define TPB 1
float scale(int i, int n){
return ((float) i)/(n - 1);
}
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
float x = 0;
//if(i>N-1)
// return;
x = d_in[i];
d_out[i] = distance(x, ref);
if(0)
{
printf("blockIdx:%2d,blockDim:%2d,threadIdx:%2d, i = %2d: dist from %f to %f.\n",
blockIdx.x,blockDim.x,threadIdx.x,i, ref, x, d_out[i]);
}
//if(i==4095) printf("find 4095\n");
}
int main(){
const float ref = 0.5f;
float *in = 0;
float *out = 0;
hipMallocManaged(&in, N*sizeof(float));
hipMallocManaged(&out, N*sizeof(float));
for(int i=0;i<N;++i)
in[i]=scale(i,N);
distanceKernel<<<(N+TPB-1)/TPB, TPB>>>(out, in, ref);
hipDeviceSynchronize();
hipFree(in);
hipFree(out);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 64
//#define N 128
//#define N 1024
//#define N 63
//#define N 65
//#define N 4096
#define TPB 32
//#define TPB 1
float scale(int i, int n){
return ((float) i)/(n - 1);
}
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
float x = 0;
//if(i>N-1)
// return;
x = d_in[i];
d_out[i] = distance(x, ref);
if(0)
{
printf("blockIdx:%2d,blockDim:%2d,threadIdx:%2d, i = %2d: dist from %f to %f.\n",
blockIdx.x,blockDim.x,threadIdx.x,i, ref, x, d_out[i]);
}
//if(i==4095) printf("find 4095\n");
}
int main(){
const float ref = 0.5f;
float *in = 0;
float *out = 0;
hipMallocManaged(&in, N*sizeof(float));
hipMallocManaged(&out, N*sizeof(float));
for(int i=0;i<N;++i)
in[i]=scale(i,N);
distanceKernel<<<(N+TPB-1)/TPB, TPB>>>(out, in, ref);
hipDeviceSynchronize();
hipFree(in);
hipFree(out);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfS_f
.globl _Z14distanceKernelPfS_f
.p2align 8
.type _Z14distanceKernelPfS_f,@function
_Z14distanceKernelPfS_f:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, s0, v2
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfS_f, .Lfunc_end0-_Z14distanceKernelPfS_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 64
//#define N 128
//#define N 1024
//#define N 63
//#define N 65
//#define N 4096
#define TPB 32
//#define TPB 1
float scale(int i, int n){
return ((float) i)/(n - 1);
}
__device__
float distance(float x1, float x2){
return sqrt((x2-x1)*(x2-x1));
}
__global__
void distanceKernel(float *d_out, float *d_in, float ref){
const int i = blockIdx.x*blockDim.x + threadIdx.x;
float x = 0;
//if(i>N-1)
// return;
x = d_in[i];
d_out[i] = distance(x, ref);
if(0)
{
printf("blockIdx:%2d,blockDim:%2d,threadIdx:%2d, i = %2d: dist from %f to %f.\n",
blockIdx.x,blockDim.x,threadIdx.x,i, ref, x, d_out[i]);
}
//if(i==4095) printf("find 4095\n");
}
int main(){
const float ref = 0.5f;
float *in = 0;
float *out = 0;
hipMallocManaged(&in, N*sizeof(float));
hipMallocManaged(&out, N*sizeof(float));
for(int i=0;i<N;++i)
in[i]=scale(i,N);
distanceKernel<<<(N+TPB-1)/TPB, TPB>>>(out, in, ref);
hipDeviceSynchronize();
hipFree(in);
hipFree(out);
return 0;
} | .text
.file "kernel.hip"
.globl _Z5scaleii # -- Begin function _Z5scaleii
.p2align 4, 0x90
.type _Z5scaleii,@function
_Z5scaleii: # @_Z5scaleii
.cfi_startproc
# %bb.0:
cvtsi2ss %edi, %xmm0
decl %esi
cvtsi2ss %esi, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z5scaleii, .Lfunc_end0-_Z5scaleii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__distanceKernelPfS_f # -- Begin function _Z29__device_stub__distanceKernelPfS_f
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPfS_f,@function
_Z29__device_stub__distanceKernelPfS_f: # @_Z29__device_stub__distanceKernelPfS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z29__device_stub__distanceKernelPfS_f, .Lfunc_end1-_Z29__device_stub__distanceKernelPfS_f
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x427c0000 # float 63
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rcx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1056964608, 28(%rsp) # imm = 0x3F000000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14distanceKernelPfS_f, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfS_f,@object # @_Z14distanceKernelPfS_f
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfS_f
.p2align 3, 0x0
_Z14distanceKernelPfS_f:
.quad _Z29__device_stub__distanceKernelPfS_f
.size _Z14distanceKernelPfS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPfS_f"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14distanceKernelPfS_f
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ BSSY B0, 0x170 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*0090*/ FADD R4, -R2, c[0x0][0x170] ; /* 0x00005c0002047621 */
/* 0x004fc80000000100 */
/*00a0*/ FMUL R4, R4, R4 ; /* 0x0000000404047220 */
/* 0x000fc80000400000 */
/*00b0*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*00c0*/ IADD3 R6, R4, -0xd000000, RZ ; /* 0xf300000004067810 */
/* 0x000fc80007ffe0ff */
/*00d0*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*00e0*/ @!P0 BRA 0x120 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*00f0*/ MOV R8, 0x110 ; /* 0x0000011000087802 */
/* 0x003fe40000000f00 */
/*0100*/ CALL.REL.NOINC 0x1b0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0110*/ BRA 0x160 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0120*/ FMUL.FTZ R3, R4, R5 ; /* 0x0000000504037220 */
/* 0x003fe40000410000 */
/*0130*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0140*/ FFMA R4, -R3, R3, R4 ; /* 0x0000000303047223 */
/* 0x000fc80000000104 */
/*0150*/ FFMA R5, R4, R5, R3 ; /* 0x0000000504057223 */
/* 0x000fe40000000003 */
/*0160*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0170*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0180*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0190*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c0ff */
/*01c0*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*01d0*/ @!P0 BRA 0x2e0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*01e0*/ FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fda0003f1e000 */
/*01f0*/ @!P0 MOV R2, 0x7fffffff ; /* 0x7fffffff00028802 */
/* 0x000fe20000000f00 */
/*0200*/ @!P0 BRA 0x2e0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0210*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*0220*/ @P0 FADD.FTZ R2, R4, 1 ; /* 0x3f80000004020421 */
/* 0x000fe20000010000 */
/*0230*/ @P0 BRA 0x2e0 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0240*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*0250*/ @P0 FFMA R3, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004030823 */
/* 0x000fc800000000ff */
/*0260*/ @P0 MUFU.RSQ R2, R3 ; /* 0x0000000300020308 */
/* 0x000e240000001400 */
/*0270*/ @P0 FMUL.FTZ R6, R3, R2 ; /* 0x0000000203060220 */
/* 0x001fe40000410000 */
/*0280*/ @P0 FMUL.FTZ R7, R2, 0.5 ; /* 0x3f00000002070820 */
/* 0x000fe20000410000 */
/*0290*/ @!P0 MOV R2, R4 ; /* 0x0000000400028202 */
/* 0x000fe20000000f00 */
/*02a0*/ @P0 FADD.FTZ R5, -R6, -RZ ; /* 0x800000ff06050221 */
/* 0x000fc80000010100 */
/*02b0*/ @P0 FFMA R5, R6, R5, R3 ; /* 0x0000000506050223 */
/* 0x000fc80000000003 */
/*02c0*/ @P0 FFMA R5, R5, R7, R6 ; /* 0x0000000705050223 */
/* 0x000fc80000000006 */
/*02d0*/ @P0 FMUL.FTZ R2, R5, 2.3283064365386962891e-10 ; /* 0x2f80000005020820 */
/* 0x000fc80000410000 */
/*02e0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*02f0*/ MOV R5, R2 ; /* 0x0000000200057202 */
/* 0x000fe40000000f00 */
/*0300*/ MOV R2, R8 ; /* 0x0000000800027202 */
/* 0x000fc80000000f00 */
/*0310*/ RET.REL.NODEC R2 0x0 ; /* 0xfffffce002007950 */
/* 0x000fea0003c3ffff */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14distanceKernelPfS_f
.globl _Z14distanceKernelPfS_f
.p2align 8
.type _Z14distanceKernelPfS_f,@function
_Z14distanceKernelPfS_f:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, s0, v2
v_mul_f32_e32 v2, v2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14distanceKernelPfS_f
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14distanceKernelPfS_f, .Lfunc_end0-_Z14distanceKernelPfS_f
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14distanceKernelPfS_f
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14distanceKernelPfS_f.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002cfe3_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5scaleii
.type _Z5scaleii, @function
_Z5scaleii:
.LFB2057:
.cfi_startproc
endbr64
pxor %xmm0, %xmm0
cvtsi2ssl %edi, %xmm0
subl $1, %esi
pxor %xmm1, %xmm1
cvtsi2ssl %esi, %xmm1
divss %xmm1, %xmm0
ret
.cfi_endproc
.LFE2057:
.size _Z5scaleii, .-_Z5scaleii
.globl _Z8distanceff
.type _Z8distanceff, @function
_Z8distanceff:
.LFB2058:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2058:
.size _Z8distanceff, .-_Z8distanceff
.globl _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
.type _Z37__device_stub__Z14distanceKernelPfS_fPfS_f, @function
_Z37__device_stub__Z14distanceKernelPfS_fPfS_f:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L10
.L6:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L11
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14distanceKernelPfS_f(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L6
.L11:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z14distanceKernelPfS_fPfS_f, .-_Z37__device_stub__Z14distanceKernelPfS_fPfS_f
.globl _Z14distanceKernelPfS_f
.type _Z14distanceKernelPfS_f, @function
_Z14distanceKernelPfS_f:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z14distanceKernelPfS_f, .-_Z14distanceKernelPfS_f
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
movq %rsp, %rdi
movl $1, %edx
movl $256, %esi
call cudaMallocManaged@PLT
leaq 8(%rsp), %rdi
movl $1, %edx
movl $256, %esi
call cudaMallocManaged@PLT
movl $0, %eax
movss .LC0(%rip), %xmm1
.L15:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
divss %xmm1, %xmm0
movq (%rsp), %rdx
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L15
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L16:
call cudaDeviceSynchronize@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movss .LC1(%rip), %xmm0
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z37__device_stub__Z14distanceKernelPfS_fPfS_f
jmp .L16
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z14distanceKernelPfS_f"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z14distanceKernelPfS_f(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1115422720
.align 4
.LC1:
.long 1056964608
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z5scaleii # -- Begin function _Z5scaleii
.p2align 4, 0x90
.type _Z5scaleii,@function
_Z5scaleii: # @_Z5scaleii
.cfi_startproc
# %bb.0:
cvtsi2ss %edi, %xmm0
decl %esi
cvtsi2ss %esi, %xmm1
divss %xmm1, %xmm0
retq
.Lfunc_end0:
.size _Z5scaleii, .Lfunc_end0-_Z5scaleii
.cfi_endproc
# -- End function
.globl _Z29__device_stub__distanceKernelPfS_f # -- Begin function _Z29__device_stub__distanceKernelPfS_f
.p2align 4, 0x90
.type _Z29__device_stub__distanceKernelPfS_f,@function
_Z29__device_stub__distanceKernelPfS_f: # @_Z29__device_stub__distanceKernelPfS_f
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movss %xmm0, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14distanceKernelPfS_f, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z29__device_stub__distanceKernelPfS_f, .Lfunc_end1-_Z29__device_stub__distanceKernelPfS_f
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x427c0000 # float 63
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 8(%rsp), %rdi
movl $256, %esi # imm = 0x100
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $256, %esi # imm = 0x100
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
movq 8(%rsp), %rcx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
divss %xmm0, %xmm1
movss %xmm1, (%rcx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_1
# %bb.2:
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $1056964608, 28(%rsp) # imm = 0x3F000000
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14distanceKernelPfS_f, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14distanceKernelPfS_f, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14distanceKernelPfS_f,@object # @_Z14distanceKernelPfS_f
.section .rodata,"a",@progbits
.globl _Z14distanceKernelPfS_f
.p2align 3, 0x0
_Z14distanceKernelPfS_f:
.quad _Z29__device_stub__distanceKernelPfS_f
.size _Z14distanceKernelPfS_f, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14distanceKernelPfS_f"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__distanceKernelPfS_f
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14distanceKernelPfS_f
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
static void HandleError(cudaError_t err,
const char *file,
int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main(void) {
cudaDeviceProp prop; int dev;
HANDLE_ERROR(cudaGetDevice(&dev));
printf("ID of current CUDA device: %d\n", dev);
memset(&prop, 0, sizeof(cudaDeviceProp));
prop.major = 6;
prop.minor = 1;
HANDLE_ERROR(cudaChooseDevice(&dev, &prop));
printf("ID of CUDA device closest to revision 6.1: %d\n", dev); HANDLE_ERROR(cudaSetDevice(dev));
system("pause");
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
static void HandleError(cudaError_t err,
const char *file,
int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main(void) {
cudaDeviceProp prop; int dev;
HANDLE_ERROR(cudaGetDevice(&dev));
printf("ID of current CUDA device: %d\n", dev);
memset(&prop, 0, sizeof(cudaDeviceProp));
prop.major = 6;
prop.minor = 1;
HANDLE_ERROR(cudaChooseDevice(&dev, &prop));
printf("ID of CUDA device closest to revision 6.1: %d\n", dev); HANDLE_ERROR(cudaSetDevice(dev));
system("pause");
return 0;
} | .file "tmpxft_0003daba_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/phan2410/cudaLearn/master/3_4_UsingDeviceProperties/kernel.cu"
.align 8
.LC2:
.string "ID of current CUDA device:\t%d\n"
.align 8
.LC3:
.string "ID of CUDA device closest to revision 6.1: %d\n"
.section .rodata.str1.1
.LC4:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rbp
movq %rbp, %rdi
call cudaGetDevice@PLT
movl %eax, %edi
movl $17, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rsi
movl $129, %ecx
movl $0, %eax
movq %rsi, %rdi
rep stosq
movl $6, 376(%rsp)
movl $1, 380(%rsp)
movq %rbp, %rdi
call cudaChooseDevice@PLT
movl %eax, %edi
movl $24, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 12(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $25, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq .LC4(%rip), %rdi
call system@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
static void HandleError(cudaError_t err,
const char *file,
int line) {
if (err != cudaSuccess) {
printf("%s in %s at line %d\n", cudaGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main(void) {
cudaDeviceProp prop; int dev;
HANDLE_ERROR(cudaGetDevice(&dev));
printf("ID of current CUDA device: %d\n", dev);
memset(&prop, 0, sizeof(cudaDeviceProp));
prop.major = 6;
prop.minor = 1;
HANDLE_ERROR(cudaChooseDevice(&dev, &prop));
printf("ID of CUDA device closest to revision 6.1: %d\n", dev); HANDLE_ERROR(cudaSetDevice(dev));
system("pause");
return 0;
} | #include <hip/hip_runtime.h>
#include <iostream>
static void HandleError(hipError_t err,
const char *file,
int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main(void) {
hipDeviceProp_t prop; int dev;
HANDLE_ERROR(hipGetDevice(&dev));
printf("ID of current CUDA device: %d\n", dev);
memset(&prop, 0, sizeof(hipDeviceProp_t));
prop.major = 6;
prop.minor = 1;
HANDLE_ERROR(hipChooseDevice(&dev, &prop));
printf("ID of CUDA device closest to revision 6.1: %d\n", dev); HANDLE_ERROR(hipSetDevice(dev));
system("pause");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
static void HandleError(hipError_t err,
const char *file,
int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main(void) {
hipDeviceProp_t prop; int dev;
HANDLE_ERROR(hipGetDevice(&dev));
printf("ID of current CUDA device: %d\n", dev);
memset(&prop, 0, sizeof(hipDeviceProp_t));
prop.major = 6;
prop.minor = 1;
HANDLE_ERROR(hipChooseDevice(&dev, &prop));
printf("ID of CUDA device closest to revision 6.1: %d\n", dev); HANDLE_ERROR(hipSetDevice(dev));
system("pause");
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <iostream>
static void HandleError(hipError_t err,
const char *file,
int line) {
if (err != hipSuccess) {
printf("%s in %s at line %d\n", hipGetErrorString(err),
file, line);
exit(EXIT_FAILURE);
}
}
#define HANDLE_ERROR( err ) (HandleError( err, __FILE__, __LINE__ ))
int main(void) {
hipDeviceProp_t prop; int dev;
HANDLE_ERROR(hipGetDevice(&dev));
printf("ID of current CUDA device: %d\n", dev);
memset(&prop, 0, sizeof(hipDeviceProp_t));
prop.major = 6;
prop.minor = 1;
HANDLE_ERROR(hipChooseDevice(&dev, &prop));
printf("ID of CUDA device closest to revision 6.1: %d\n", dev); HANDLE_ERROR(hipSetDevice(dev));
system("pause");
return 0;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4294967302, %rax # imm = 0x100000006
movq %rax, 376(%rsp)
leaq 12(%rsp), %rdi
movq %rbx, %rsi
callq hipChooseDeviceR0600
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit2
movl 12(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit4
movl $.L.str.3, %edi
callq system
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 1504
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $19, %ecx
jmp .LBB0_2
.LBB0_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $26, %ecx
jmp .LBB0_2
.LBB0_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $27, %ecx
.LBB0_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/phan2410/cudaLearn/master/3_4_UsingDeviceProperties/kernel.hip"
.size .L.str, 120
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ID of current CUDA device:\t%d\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ID of CUDA device closest to revision 6.1: %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "pause"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s in %s at line %d\n"
.size .L.str.4, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003daba_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%s in %s at line %d\n"
#NO_APP
.text
.type _ZL11HandleError9cudaErrorPKci, @function
_ZL11HandleError9cudaErrorPKci:
.LFB3669:
.cfi_startproc
testl %edi, %edi
jne .L6
ret
.L6:
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
movl %edx, %ebp
call cudaGetErrorString@PLT
movq %rax, %rdx
movl %ebp, %r8d
movq %rbx, %rcx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3669:
.size _ZL11HandleError9cudaErrorPKci, .-_ZL11HandleError9cudaErrorPKci
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/phan2410/cudaLearn/master/3_4_UsingDeviceProperties/kernel.cu"
.align 8
.LC2:
.string "ID of current CUDA device:\t%d\n"
.align 8
.LC3:
.string "ID of CUDA device closest to revision 6.1: %d\n"
.section .rodata.str1.1
.LC4:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rbp
movq %rbp, %rdi
call cudaGetDevice@PLT
movl %eax, %edi
movl $17, %edx
leaq .LC1(%rip), %rbx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 12(%rsp), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rsi
movl $129, %ecx
movl $0, %eax
movq %rsi, %rdi
rep stosq
movl $6, 376(%rsp)
movl $1, 380(%rsp)
movq %rbp, %rdi
call cudaChooseDevice@PLT
movl %eax, %edi
movl $24, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
movl 12(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 12(%rsp), %edi
call cudaSetDevice@PLT
movl %eax, %edi
movl $25, %edx
movq %rbx, %rsi
call _ZL11HandleError9cudaErrorPKci
leaq .LC4(%rip), %rdi
call system@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L12
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3670:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -16
leaq 12(%rsp), %rdi
callq hipGetDevice
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_ZL11HandleError10hipError_tPKci.exit
movl 12(%rsp), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rbx
movl $1472, %edx # imm = 0x5C0
movq %rbx, %rdi
xorl %esi, %esi
callq memset@PLT
movabsq $4294967302, %rax # imm = 0x100000006
movq %rax, 376(%rsp)
leaq 12(%rsp), %rdi
movq %rbx, %rsi
callq hipChooseDeviceR0600
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_ZL11HandleError10hipError_tPKci.exit2
movl 12(%rsp), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl 12(%rsp), %edi
callq hipSetDevice
testl %eax, %eax
jne .LBB0_6
# %bb.7: # %_ZL11HandleError10hipError_tPKci.exit4
movl $.L.str.3, %edi
callq system
xorl %eax, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 1504
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $19, %ecx
jmp .LBB0_2
.LBB0_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $26, %ecx
jmp .LBB0_2
.LBB0_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %edi
movl $.L.str, %edx
movq %rax, %rsi
movl $27, %ecx
.LBB0_2:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/phan2410/cudaLearn/master/3_4_UsingDeviceProperties/kernel.hip"
.size .L.str, 120
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "ID of current CUDA device:\t%d\n"
.size .L.str.1, 31
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ID of CUDA device closest to revision 6.1: %d\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "pause"
.size .L.str.3, 6
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%s in %s at line %d\n"
.size .L.str.4, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Implement your CUDA kernel in this file
*/
__global__ void mirror_boundaries(double *E_prev, const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if (col == 1) {
E_prev[row*(n+2)] = E_prev[row*(n+2) + 2];
E_prev[row*(n+2) + n + 1] = E_prev[row*(n+2) + n - 1];
}
if (row == 1) {
E_prev[col] = E_prev[2*(n+2) + col];
E_prev[(m+1)*(n+2) + col] = E_prev[(m-1)*(n+2) + col];
}
}
__global__ void solve_for_pde (double *E, const double *E_prev, const double alpha,
const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n))
E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);
}
__global__ void solve_for_ode (double *E, double *R, const double alpha,
const int n, const int m, const double kk,
const double dt, const double a, const double epsilon,
const double M1,const double M2, const double b)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n)) {
E[row*(n+2)+col] = E[row*(n+2)+col] - dt*(kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - a)*(E[row*(n+2)+col] - 1) + E[row*(n+2)+col]*R[row*(n+2)+col]);
R[row*(n+2)+col] = R[row*(n+2)+col] + dt*(epsilon + M1*R[row*(n+2)+col]/(E[row*(n+2)+col] + M2))*(-R[row*(n+2)+col] - kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - b - 1));
}
} | code for sm_80
Function : _Z13solve_for_odePdS_diiddddddd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x178], P0 ; /* 0x00005e0002007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ IADD3 R3, R0, 0x1, RZ ; /* 0x0000000100037810 */
/* 0x000fe20007ffe0ff */
/*00c0*/ UIADD3 UR4, UR4, 0x2, URZ ; /* 0x0000000204047890 */
/* 0x000fe2000fffe03f */
/*00d0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x8 ; /* 0x00000008ff0e7424 */
/* 0x000fca00078e00ff */
/*00e0*/ IMAD R3, R3, UR4, R2 ; /* 0x0000000403037c24 */
/* 0x000fe2000f8e0202 */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0100*/ IMAD.WIDE R6, R3, R14, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e020e */
/*0110*/ LDG.E.64 R12, [R6.64+0x8] ; /* 0x00000804060c7981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ IMAD.WIDE R14, R3, R14, c[0x0][0x168] ; /* 0x00005a00030e7625 */
/* 0x000fca00078e020e */
/*0130*/ LDG.E.64 R10, [R14.64+0x8] ; /* 0x000008040e0a7981 */
/* 0x000ee2000c1e1b00 */
/*0140*/ DMUL R2, R12, c[0x0][0x180] ; /* 0x000060000c027a28 */
/* 0x004fc80000000000 */
/*0150*/ DADD R4, R12, -c[0x0][0x190] ; /* 0x800064000c047629 */
/* 0x000e080000000000 */
/*0160*/ DADD R8, R12, -1 ; /* 0xbff000000c087429 */
/* 0x000fc80000000000 */
/*0170*/ DMUL R2, R2, R4 ; /* 0x0000000402027228 */
/* 0x001e0c0000000000 */
/*0180*/ DMUL R2, R2, R8 ; /* 0x0000000802027228 */
/* 0x001ecc0000000000 */
/*0190*/ DFMA R2, R12, R10, R2 ; /* 0x0000000a0c02722b */
/* 0x008e0c0000000002 */
/*01a0*/ DFMA R12, -R2, c[0x0][0x188], R12 ; /* 0x00006200020c7a2b */
/* 0x001e0e000000010c */
/*01b0*/ STG.E.64 [R6.64+0x8], R12 ; /* 0x0000080c06007986 */
/* 0x0011e8000c101b04 */
/*01c0*/ LDG.E.64 R10, [R14.64+0x8] ; /* 0x000008040e0a7981 */
/* 0x000ea2000c1e1b00 */
/*01d0*/ DADD R2, R12, c[0x0][0x1a8] ; /* 0x00006a000c027629 */
/* 0x000e620000000000 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe200078e00ff */
/*01f0*/ BSSY B0, 0x310 ; /* 0x0000011000007945 */
/* 0x000fe80003800000 */
/*0200*/ MUFU.RCP64H R5, R3 ; /* 0x0000000300057308 */
/* 0x002e640000001800 */
/*0210*/ DFMA R8, -R2, R4, 1 ; /* 0x3ff000000208742b */
/* 0x002e4c0000000104 */
/*0220*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x002e4c0000000008 */
/*0230*/ DFMA R8, R4, R8, R4 ; /* 0x000000080408722b */
/* 0x002e4c0000000004 */
/*0240*/ DFMA R16, -R2, R8, 1 ; /* 0x3ff000000210742b */
/* 0x002e4c0000000108 */
/*0250*/ DFMA R16, R8, R16, R8 ; /* 0x000000100810722b */
/* 0x002fc80000000008 */
/*0260*/ DMUL R4, R10, c[0x0][0x1a0] ; /* 0x000068000a047a28 */
/* 0x004e0c0000000000 */
/*0270*/ DMUL R6, R4, R16 ; /* 0x0000001004067228 */
/* 0x001e080000000000 */
/*0280*/ FSETP.GEU.AND P1, PT, |R5|, 6.5827683646048100446e-37, PT ; /* 0x036000000500780b */
/* 0x000fe40003f2e200 */
/*0290*/ DFMA R8, -R2, R6, R4 ; /* 0x000000060208722b */
/* 0x001e0c0000000104 */
/*02a0*/ DFMA R6, R16, R8, R6 ; /* 0x000000081006722b */
/* 0x001e140000000006 */
/*02b0*/ FFMA R0, RZ, R3, R7 ; /* 0x00000003ff007223 */
/* 0x001fca0000000007 */
/*02c0*/ FSETP.GT.AND P0, PT, |R0|, 1.469367938527859385e-39, PT ; /* 0x001000000000780b */
/* 0x000fda0003f04200 */
/*02d0*/ @P0 BRA P1, 0x300 ; /* 0x0000002000000947 */
/* 0x000fea0000800000 */
/*02e0*/ MOV R0, 0x300 ; /* 0x0000030000007802 */
/* 0x000fe40000000f00 */
/*02f0*/ CALL.REL.NOINC 0x3a0 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*0300*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0310*/ DADD R2, R12, -c[0x0][0x1b0] ; /* 0x80006c000c027629 */
/* 0x000e080000000000 */
/*0320*/ DADD R6, R6, c[0x0][0x198] ; /* 0x0000660006067629 */
/* 0x000e480000000000 */
/*0330*/ DMUL R12, R12, c[0x0][0x180] ; /* 0x000060000c0c7a28 */
/* 0x000fc80000000000 */
/*0340*/ DADD R2, R2, -1 ; /* 0xbff0000002027429 */
/* 0x001e080000000000 */
/*0350*/ DMUL R6, R6, c[0x0][0x188] ; /* 0x0000620006067a28 */
/* 0x002fc80000000000 */
/*0360*/ DFMA R2, -R12, R2, -R10 ; /* 0x000000020c02722b */
/* 0x001e0c000000090a */
/*0370*/ DFMA R2, R6, R2, R10 ; /* 0x000000020602722b */
/* 0x001e0e000000000a */
/*0380*/ STG.E.64 [R14.64+0x8], R2 ; /* 0x000008020e007986 */
/* 0x001fe2000c101b04 */
/*0390*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03a0*/ FSETP.GEU.AND P0, PT, |R3|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000300780b */
/* 0x040fe20003f0e200 */
/*03b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2.reuse ; /* 0x000000ffff067224 */
/* 0x100fe200078e0002 */
/*03c0*/ LOP3.LUT R8, R3, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03087812 */
/* 0x000fe200078ec0ff */
/*03d0*/ IMAD.MOV.U32 R7, RZ, RZ, R3 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0003 */
/*03e0*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*03f0*/ IMAD.MOV.U32 R18, RZ, RZ, 0x1 ; /* 0x00000001ff127424 */
/* 0x000fe200078e00ff */
/*0400*/ LOP3.LUT R9, R8, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000008097812 */
/* 0x000fe200078efcff */
/*0410*/ IMAD.MOV.U32 R8, RZ, RZ, R2 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0002 */
/*0420*/ LOP3.LUT R16, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000005107812 */
/* 0x000fe200078ec0ff */
/*0430*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0440*/ LOP3.LUT R23, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003177812 */
/* 0x000fe200078ec0ff */
/*0450*/ BSSY B1, 0x960 ; /* 0x0000050000017945 */
/* 0x000fe40003800000 */
/*0460*/ @!P0 DMUL R8, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006088828 */
/* 0x000e220000000000 */
/*0470*/ ISETP.GE.U32.AND P1, PT, R16, R23, PT ; /* 0x000000171000720c */
/* 0x000fc60003f26070 */
/*0480*/ @!P2 LOP3.LUT R17, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000711a812 */
/* 0x000fe200078ec0ff */
/*0490*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*04a0*/ MUFU.RCP64H R19, R9 ; /* 0x0000000900137308 */
/* 0x001e240000001800 */
/*04b0*/ @!P2 ISETP.GE.U32.AND P3, PT, R16, R17, PT ; /* 0x000000111000a20c */
/* 0x000fe20003f66070 */
/*04c0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff117424 */
/* 0x000fca00078e00ff */
/*04d0*/ @!P2 SEL R21, R17.reuse, 0x63400000, !P3 ; /* 0x634000001115a807 */
/* 0x040fe40005800000 */
/*04e0*/ SEL R3, R17, 0x63400000, !P1 ; /* 0x6340000011037807 */
/* 0x000fe40004800000 */
/*04f0*/ @!P2 LOP3.LUT R21, R21, 0x80000000, R5.reuse, 0xf8, !PT ; /* 0x800000001515a812 */
/* 0x100fe400078ef805 */
/*0500*/ LOP3.LUT R3, R3, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff03037812 */
/* 0x000fe200078ef805 */
/*0510*/ DFMA R24, R18, -R8, 1 ; /* 0x3ff000001218742b */
/* 0x001e220000000808 */
/*0520*/ @!P2 LOP3.LUT R21, R21, 0x100000, RZ, 0xfc, !PT ; /* 0x001000001515a812 */
/* 0x000fca00078efcff */
/*0530*/ DFMA R24, R24, R24, R24 ; /* 0x000000181818722b */
/* 0x001e080000000018 */
/*0540*/ @!P2 DFMA R2, R2, 2, -R20 ; /* 0x400000000202a82b */
/* 0x0003e40000000814 */
/*0550*/ IMAD.MOV.U32 R20, RZ, RZ, R16 ; /* 0x000000ffff147224 */
/* 0x002fe400078e0010 */
/*0560*/ DFMA R18, R18, R24, R18 ; /* 0x000000181212722b */
/* 0x001e220000000012 */
/*0570*/ IMAD.MOV.U32 R21, RZ, RZ, R23 ; /* 0x000000ffff157224 */
/* 0x000fe200078e0017 */
/*0580*/ @!P0 LOP3.LUT R21, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000009158812 */
/* 0x000fc800078ec0ff */
/*0590*/ DFMA R24, R18, -R8, 1 ; /* 0x3ff000001218742b */
/* 0x001e220000000808 */
/*05a0*/ @!P2 LOP3.LUT R20, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000314a812 */
/* 0x000fe400078ec0ff */
/*05b0*/ IADD3 R26, R21, -0x1, RZ ; /* 0xffffffff151a7810 */
/* 0x000fc60007ffe0ff */
/*05c0*/ DFMA R18, R18, R24, R18 ; /* 0x000000181212722b */
/* 0x0010640000000012 */
/*05d0*/ IADD3 R24, R20, -0x1, RZ ; /* 0xffffffff14187810 */
/* 0x001fc80007ffe0ff */
/*05e0*/ ISETP.GT.U32.AND P0, PT, R24, 0x7feffffe, PT ; /* 0x7feffffe1800780c */
/* 0x000fe20003f04070 */
/*05f0*/ DMUL R22, R18, R2 ; /* 0x0000000212167228 */
/* 0x002e060000000000 */
/*0600*/ ISETP.GT.U32.OR P0, PT, R26, 0x7feffffe, P0 ; /* 0x7feffffe1a00780c */
/* 0x000fc60000704470 */
/*0610*/ DFMA R24, R22, -R8, R2 ; /* 0x800000081618722b */
/* 0x001e0c0000000002 */
/*0620*/ DFMA R18, R18, R24, R22 ; /* 0x000000181212722b */
/* 0x0010480000000016 */
/*0630*/ @P0 BRA 0x800 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0640*/ LOP3.LUT R5, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007057812 */
/* 0x003fe200078ec0ff */
/*0650*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fc600078e00ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R16.reuse, R5, PT ; /* 0x000000051000720c */
/* 0x040fe20003f06070 */
/*0670*/ IMAD.IADD R4, R16, 0x1, -R5 ; /* 0x0000000110047824 */
/* 0x000fc600078e0a05 */
/*0680*/ SEL R17, R17, 0x63400000, !P0 ; /* 0x6340000011117807 */
/* 0x000fe40004000000 */
/*0690*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*06a0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*06b0*/ IMAD.IADD R4, R4, 0x1, -R17 ; /* 0x0000000104047824 */
/* 0x000fca00078e0a11 */
/*06c0*/ IADD3 R21, R4, 0x7fe00000, RZ ; /* 0x7fe0000004157810 */
/* 0x000fcc0007ffe0ff */
/*06d0*/ DMUL R16, R18, R20 ; /* 0x0000001412107228 */
/* 0x000e140000000000 */
/*06e0*/ FSETP.GTU.AND P0, PT, |R17|, 1.469367938527859385e-39, PT ; /* 0x001000001100780b */
/* 0x001fda0003f0c200 */
/*06f0*/ @P0 BRA 0x950 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0700*/ DFMA R2, R18, -R8, R2 ; /* 0x800000081202722b */
/* 0x000e220000000002 */
/*0710*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fd200078e00ff */
/*0720*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x041fe40003f0d000 */
/*0730*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0740*/ LOP3.LUT R21, R7, R21, RZ, 0xfc, !PT ; /* 0x0000001507157212 */
/* 0x000fce00078efcff */
/*0750*/ @!P0 BRA 0x950 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0a04 */
/*0770*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0780*/ DFMA R2, R16, -R2, R18 ; /* 0x800000021002722b */
/* 0x000e080000000012 */
/*0790*/ DMUL.RP R18, R18, R20 ; /* 0x0000001412127228 */
/* 0x000e640000008000 */
/*07a0*/ IADD3 R2, -R4, -0x43300000, RZ ; /* 0xbcd0000004027810 */
/* 0x001fc80007ffe1ff */
/*07b0*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*07c0*/ LOP3.LUT R7, R19, R7, RZ, 0x3c, !PT ; /* 0x0000000713077212 */
/* 0x002fe400078e3cff */
/*07d0*/ FSEL R16, R18, R16, !P0 ; /* 0x0000001012107208 */
/* 0x000fe40004000000 */
/*07e0*/ FSEL R17, R7, R17, !P0 ; /* 0x0000001107117208 */
/* 0x000fe20004000000 */
/*07f0*/ BRA 0x950 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0800*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x003e1c0003f08000 */
/*0810*/ @P0 BRA 0x930 ; /* 0x0000011000000947 */
/* 0x001fea0003800000 */
/*0820*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e1c0003f08000 */
/*0830*/ @P0 BRA 0x900 ; /* 0x000000c000000947 */
/* 0x001fea0003800000 */
/*0840*/ ISETP.NE.AND P0, PT, R20, R21, PT ; /* 0x000000151400720c */
/* 0x000fe20003f05270 */
/*0850*/ IMAD.MOV.U32 R16, RZ, RZ, 0x0 ; /* 0x00000000ff107424 */
/* 0x000fe400078e00ff */
/*0860*/ IMAD.MOV.U32 R17, RZ, RZ, -0x80000 ; /* 0xfff80000ff117424 */
/* 0x000fd400078e00ff */
/*0870*/ @!P0 BRA 0x950 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0880*/ ISETP.NE.AND P0, PT, R20, 0x7ff00000, PT ; /* 0x7ff000001400780c */
/* 0x000fe40003f05270 */
/*0890*/ LOP3.LUT R17, R5, 0x80000000, R7, 0x48, !PT ; /* 0x8000000005117812 */
/* 0x000fe400078e4807 */
/*08a0*/ ISETP.EQ.OR P0, PT, R21, RZ, !P0 ; /* 0x000000ff1500720c */
/* 0x000fda0004702670 */
/*08b0*/ @P0 LOP3.LUT R2, R17, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff0000011020812 */
/* 0x000fe200078efcff */
/*08c0*/ @!P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff108224 */
/* 0x000fe400078e00ff */
/*08d0*/ @P0 IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff100224 */
/* 0x000fe400078e00ff */
/*08e0*/ @P0 IMAD.MOV.U32 R17, RZ, RZ, R2 ; /* 0x000000ffff110224 */
/* 0x000fe200078e0002 */
/*08f0*/ BRA 0x950 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT R17, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000007117812 */
/* 0x000fe200078efcff */
/*0910*/ IMAD.MOV.U32 R16, RZ, RZ, R6 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0006 */
/*0920*/ BRA 0x950 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0930*/ LOP3.LUT R17, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x0008000005117812 */
/* 0x000fe200078efcff */
/*0940*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0004 */
/*0950*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0960*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0970*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc400078e00ff */
/*0980*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*0990*/ IMAD.MOV.U32 R7, RZ, RZ, R17 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0011 */
/*09a0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff65002007950 */
/* 0x000fec0003c3ffff */
/*09b0*/ BRA 0x9b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13solve_for_pdePdPKddii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R15, SR_CTAID.X ; /* 0x00000000000f7919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x4], R3 ; /* 0x0000010002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x17c], PT ; /* 0x00005f0002007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R15, R15, c[0x0][0x0], R0 ; /* 0x000000000f0f7a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R15, c[0x0][0x178], P0 ; /* 0x00005e000f007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000800 */
/*00b0*/ HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff007435 */
/* 0x000fe200000001ff */
/*00c0*/ UIADD3 UR4, UR4, 0x2, URZ ; /* 0x0000000204047890 */
/* 0x000fe2000fffe03f */
/*00d0*/ IADD3 R4, R2, 0x1, RZ ; /* 0x0000000102047810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc80000000a00 */
/*00f0*/ IMAD R3, R4, UR4, R15 ; /* 0x0000000404037c24 */
/* 0x000fc8000f8e020f */
/*0100*/ IMAD.WIDE R6, R3.reuse, R0, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x040fe200078e0200 */
/*0110*/ IADD3 R13, R3, c[0x0][0x178], RZ ; /* 0x00005e00030d7a10 */
/* 0x000fc80007ffe0ff */
/*0120*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea8000c1e1b00 */
/*0130*/ LDG.E.64 R10, [R6.64+0x10] ; /* 0x00001006060a7981 */
/* 0x000ea2000c1e1b00 */
/*0140*/ IMAD.WIDE R12, R13, R0, c[0x0][0x168] ; /* 0x00005a000d0c7625 */
/* 0x000fc600078e0200 */
/*0150*/ LDG.E.64 R4, [R6.64+0x8] ; /* 0x0000080606047981 */
/* 0x000ee2000c1e1b00 */
/*0160*/ IMAD R15, R2, UR4, R15 ; /* 0x00000004020f7c24 */
/* 0x000fc6000f8e020f */
/*0170*/ LDG.E.64 R12, [R12.64+0x18] ; /* 0x000018060c0c7981 */
/* 0x000f22000c1e1b00 */
/*0180*/ IMAD.WIDE R14, R15, R0, c[0x0][0x168] ; /* 0x00005a000f0e7625 */
/* 0x000fcc00078e0200 */
/*0190*/ LDG.E.64 R14, [R14.64+0x8] ; /* 0x000008060e0e7981 */
/* 0x000f62000c1e1b00 */
/*01a0*/ IMAD.WIDE R2, R3, R0, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe200078e0200 */
/*01b0*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x004ecc000000000a */
/*01c0*/ DFMA R8, R4, -4, R8 ; /* 0xc01000000408782b */
/* 0x008f0c0000000008 */
/*01d0*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x010f4c000000000c */
/*01e0*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x020e0c000000000e */
/*01f0*/ DFMA R8, R8, c[0x0][0x170], R4 ; /* 0x00005c0008087a2b */
/* 0x001e0e0000000004 */
/*0200*/ STG.E.64 [R2.64+0x8], R8 ; /* 0x0000080802007986 */
/* 0x001fe2000c101b06 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17mirror_boundariesPdii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ MOV R13, c[0x0][0x168] ; /* 0x00005a00000d7a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ BSSY B0, 0x1a0 ; /* 0x0000015000007945 */
/* 0x000fe20003800000 */
/*0050*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0060*/ IADD3 R11, R13, 0x2, RZ ; /* 0x000000020d0b7810 */
/* 0x000fc60007ffe0ff */
/*0070*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0080*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R10, R10, c[0x0][0x0], R5 ; /* 0x000000000a0a7a24 */
/* 0x001fca00078e0205 */
/*00a0*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*00b0*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*00c0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f25270 */
/*00d0*/ @P0 BRA 0x190 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*00e0*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*00f0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fca0007ffe0ff */
/*0100*/ IMAD R0, R0, R11, RZ ; /* 0x0000000b00007224 */
/* 0x000fc800078e02ff */
/*0110*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*0120*/ LDG.E.64 R4, [R2.64+0x10] ; /* 0x0000100602047981 */
/* 0x000ea2000c1e1b00 */
/*0130*/ IADD3 R0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000007a10 */
/* 0x000fc80007ffe0ff */
/*0140*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fca0007ffe0ff */
/*0150*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fe200078e0207 */
/*0160*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0041e8000c101b06 */
/*0170*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000606087981 */
/* 0x000ea8000c1e1b00 */
/*0180*/ STG.E.64 [R6.64+0x10], R8 ; /* 0x0000100806007986 */
/* 0x0041e4000c101b06 */
/*0190*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01a0*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*01b0*/ LEA R0, R13, R10, 0x1 ; /* 0x0000000a0d007211 */
/* 0x000fe400078e08ff */
/*01c0*/ MOV R9, 0x8 ; /* 0x0000000800097802 */
/* 0x001fca0000000f00 */
/*01d0*/ IMAD.WIDE R2, R0, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0209 */
/*01e0*/ LDG.E.64 R2, [R2.64+0x28] ; /* 0x0000280602027981 */
/* 0x000ea2000c1e1b00 */
/*01f0*/ ULDC UR4, c[0x0][0x16c] ; /* 0x00005b0000047ab9 */
/* 0x000fe20000000800 */
/*0200*/ IADD3 R6, R10.reuse, 0x1, RZ ; /* 0x000000010a067810 */
/* 0x040fe20007ffe0ff */
/*0210*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0220*/ IMAD.WIDE R4, R10, R9, c[0x0][0x160] ; /* 0x000058000a047625 */
/* 0x000fc800078e0209 */
/*0230*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0240*/ IMAD R11, R11, UR4, RZ ; /* 0x000000040b0b7c24 */
/* 0x000fc8000f8e02ff */
/*0250*/ IMAD.WIDE R6, R11, 0x8, R6 ; /* 0x000000080b067825 */
/* 0x000fe200078e0206 */
/*0260*/ STG.E.64 [R4.64+0x8], R2 ; /* 0x0000080204007986 */
/* 0x004fea000c101b06 */
/*0270*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea2000c1e1b00 */
/*0280*/ IADD3 R8, R0, 0x5, R11 ; /* 0x0000000500087810 */
/* 0x000fca0007ffe00b */
/*0290*/ IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fca00078e0209 */
/*02a0*/ STG.E.64 [R8.64], R6 ; /* 0x0000000608007986 */
/* 0x004fe2000c101b06 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Implement your CUDA kernel in this file
*/
__global__ void mirror_boundaries(double *E_prev, const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if (col == 1) {
E_prev[row*(n+2)] = E_prev[row*(n+2) + 2];
E_prev[row*(n+2) + n + 1] = E_prev[row*(n+2) + n - 1];
}
if (row == 1) {
E_prev[col] = E_prev[2*(n+2) + col];
E_prev[(m+1)*(n+2) + col] = E_prev[(m-1)*(n+2) + col];
}
}
__global__ void solve_for_pde (double *E, const double *E_prev, const double alpha,
const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n))
E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);
}
__global__ void solve_for_ode (double *E, double *R, const double alpha,
const int n, const int m, const double kk,
const double dt, const double a, const double epsilon,
const double M1,const double M2, const double b)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n)) {
E[row*(n+2)+col] = E[row*(n+2)+col] - dt*(kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - a)*(E[row*(n+2)+col] - 1) + E[row*(n+2)+col]*R[row*(n+2)+col]);
R[row*(n+2)+col] = R[row*(n+2)+col] + dt*(epsilon + M1*R[row*(n+2)+col]/(E[row*(n+2)+col] + M2))*(-R[row*(n+2)+col] - kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - b - 1));
}
} | .file "tmpxft_000f8f6a_00000000-6_cardiacsim_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17mirror_boundariesPdiiPdii
.type _Z39__device_stub__Z17mirror_boundariesPdiiPdii, @function
_Z39__device_stub__Z17mirror_boundariesPdiiPdii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17mirror_boundariesPdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17mirror_boundariesPdiiPdii, .-_Z39__device_stub__Z17mirror_boundariesPdiiPdii
.globl _Z17mirror_boundariesPdii
.type _Z17mirror_boundariesPdii, @function
_Z17mirror_boundariesPdii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17mirror_boundariesPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17mirror_boundariesPdii, .-_Z17mirror_boundariesPdii
.globl _Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii
.type _Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii, @function
_Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13solve_for_pdePdPKddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii, .-_Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii
.globl _Z13solve_for_pdePdPKddii
.type _Z13solve_for_pdePdPKddii, @function
_Z13solve_for_pdePdPKddii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13solve_for_pdePdPKddii, .-_Z13solve_for_pdePdPKddii
.globl _Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd
.type _Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd, @function
_Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd:
.LFB2055:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 68(%rsp)
movl %ecx, 64(%rsp)
movsd %xmm1, 56(%rsp)
movsd %xmm2, 48(%rsp)
movsd %xmm3, 40(%rsp)
movsd %xmm4, 32(%rsp)
movsd %xmm5, 24(%rsp)
movsd %xmm6, 16(%rsp)
movsd %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 68(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z13solve_for_odePdS_diiddddddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd, .-_Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd
.globl _Z13solve_for_odePdS_diiddddddd
.type _Z13solve_for_odePdS_diiddddddd, @function
_Z13solve_for_odePdS_diiddddddd:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z13solve_for_odePdS_diiddddddd, .-_Z13solve_for_odePdS_diiddddddd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13solve_for_odePdS_diiddddddd"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13solve_for_pdePdPKddii"
.LC2:
.string "_Z17mirror_boundariesPdii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13solve_for_odePdS_diiddddddd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13solve_for_pdePdPKddii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z17mirror_boundariesPdii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Implement your CUDA kernel in this file
*/
__global__ void mirror_boundaries(double *E_prev, const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if (col == 1) {
E_prev[row*(n+2)] = E_prev[row*(n+2) + 2];
E_prev[row*(n+2) + n + 1] = E_prev[row*(n+2) + n - 1];
}
if (row == 1) {
E_prev[col] = E_prev[2*(n+2) + col];
E_prev[(m+1)*(n+2) + col] = E_prev[(m-1)*(n+2) + col];
}
}
__global__ void solve_for_pde (double *E, const double *E_prev, const double alpha,
const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n))
E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);
}
__global__ void solve_for_ode (double *E, double *R, const double alpha,
const int n, const int m, const double kk,
const double dt, const double a, const double epsilon,
const double M1,const double M2, const double b)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n)) {
E[row*(n+2)+col] = E[row*(n+2)+col] - dt*(kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - a)*(E[row*(n+2)+col] - 1) + E[row*(n+2)+col]*R[row*(n+2)+col]);
R[row*(n+2)+col] = R[row*(n+2)+col] + dt*(epsilon + M1*R[row*(n+2)+col]/(E[row*(n+2)+col] + M2))*(-R[row*(n+2)+col] - kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - b - 1));
}
} | #include <hip/hip_runtime.h>
/*
Implement your CUDA kernel in this file
*/
__global__ void mirror_boundaries(double *E_prev, const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if (col == 1) {
E_prev[row*(n+2)] = E_prev[row*(n+2) + 2];
E_prev[row*(n+2) + n + 1] = E_prev[row*(n+2) + n - 1];
}
if (row == 1) {
E_prev[col] = E_prev[2*(n+2) + col];
E_prev[(m+1)*(n+2) + col] = E_prev[(m-1)*(n+2) + col];
}
}
__global__ void solve_for_pde (double *E, const double *E_prev, const double alpha,
const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n))
E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);
}
__global__ void solve_for_ode (double *E, double *R, const double alpha,
const int n, const int m, const double kk,
const double dt, const double a, const double epsilon,
const double M1,const double M2, const double b)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n)) {
E[row*(n+2)+col] = E[row*(n+2)+col] - dt*(kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - a)*(E[row*(n+2)+col] - 1) + E[row*(n+2)+col]*R[row*(n+2)+col]);
R[row*(n+2)+col] = R[row*(n+2)+col] + dt*(epsilon + M1*R[row*(n+2)+col]/(E[row*(n+2)+col] + M2))*(-R[row*(n+2)+col] - kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - b - 1));
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
Implement your CUDA kernel in this file
*/
__global__ void mirror_boundaries(double *E_prev, const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if (col == 1) {
E_prev[row*(n+2)] = E_prev[row*(n+2) + 2];
E_prev[row*(n+2) + n + 1] = E_prev[row*(n+2) + n - 1];
}
if (row == 1) {
E_prev[col] = E_prev[2*(n+2) + col];
E_prev[(m+1)*(n+2) + col] = E_prev[(m-1)*(n+2) + col];
}
}
__global__ void solve_for_pde (double *E, const double *E_prev, const double alpha,
const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n))
E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);
}
__global__ void solve_for_ode (double *E, double *R, const double alpha,
const int n, const int m, const double kk,
const double dt, const double a, const double epsilon,
const double M1,const double M2, const double b)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n)) {
E[row*(n+2)+col] = E[row*(n+2)+col] - dt*(kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - a)*(E[row*(n+2)+col] - 1) + E[row*(n+2)+col]*R[row*(n+2)+col]);
R[row*(n+2)+col] = R[row*(n+2)+col] + dt*(epsilon + M1*R[row*(n+2)+col]/(E[row*(n+2)+col] + M2))*(-R[row*(n+2)+col] - kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - b - 1));
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17mirror_boundariesPdii
.globl _Z17mirror_boundariesPdii
.p2align 8
.type _Z17mirror_boundariesPdii,@function
_Z17mirror_boundariesPdii:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s4, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s6, s5, 0xffff
s_lshr_b32 s5, s5, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s6, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s5, v[3:4]
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_2
s_add_i32 s6, s4, 2
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[2:3], null, s6, v1, s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v7, s4, v2
v_lshlrev_b64 v[3:4], 3, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
global_load_b64 v[5:6], v[3:4], off offset:16
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[3:4], v[5:6], off
global_load_b64 v[2:3], v[7:8], off offset:-8
s_waitcnt vmcnt(0)
global_store_b64 v[7:8], v[2:3], off offset:8
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_mov_b32 s5, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v0, 1, v0
s_add_i32 s4, s4, 2
s_load_b32 s0, s[0:1], 0xc
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v1, s4, 1, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_waitcnt lgkmcnt(0)
s_add_i32 s1, s0, -1
s_add_i32 s0, s0, 1
global_load_b64 v[2:3], v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s1, s4, v[0:1]
v_lshlrev_b64 v[6:7], 3, v[0:1]
v_add_co_u32 v6, vcc_lo, s2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 3, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[6:7], v[2:3], off
global_load_b64 v[1:2], v[4:5], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, s0, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17mirror_boundariesPdii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17mirror_boundariesPdii, .Lfunc_end0-_Z17mirror_boundariesPdii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13solve_for_pdePdPKddii
.globl _Z13solve_for_pdePdPKddii
.p2align 8
.type _Z13solve_for_pdePdPKddii,@function
_Z13solve_for_pdePdPKddii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_2
s_add_i32 s2, s4, 2
v_add_nc_u32_e32 v5, 1, v1
v_mul_lo_u32 v12, v0, s2
s_load_b128 s[4:7], s[0:1], 0x0
v_add_nc_u32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, s2, v12
v_add_nc_u32_e32 v12, v5, v12
v_add_nc_u32_e32 v2, v3, v5
v_add_nc_u32_e32 v6, v3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v13, 31, v12
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[12:13], 3, v[12:13]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[8:9], 3, v[2:3]
v_lshlrev_b64 v[1:2], 3, v[6:7]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s6, v8
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v6, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v2, vcc_lo
s_clause 0x1
global_load_b128 v[1:4], v[3:4], off
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[10:11], null, v0, s2, v[5:6]
v_add_f64 v[3:4], v[3:4], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v11, 31, v10
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, s6, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s7, v11, vcc_lo
v_add_co_u32 v12, vcc_lo, s6, v12
v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
s_clause 0x1
global_load_b64 v[10:11], v[10:11], off
global_load_b64 v[12:13], v[12:13], off
v_fma_f64 v[3:4], v[1:2], -4.0, v[3:4]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[10:11], v[3:4]
s_waitcnt vmcnt(0)
v_add_f64 v[3:4], v[12:13], v[3:4]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[0:1], v[3:4], s[0:1], v[1:2]
v_add_co_u32 v2, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v9, vcc_lo
global_store_b64 v[2:3], v[0:1], off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13solve_for_pdePdPKddii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13solve_for_pdePdPKddii, .Lfunc_end1-_Z13solve_for_pdePdPKddii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13solve_for_odePdS_diiddddddd
.globl _Z13solve_for_odePdS_diiddddddd
.p2align 8
.type _Z13solve_for_odePdS_diiddddddd,@function
_Z13solve_for_odePdS_diiddddddd:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x64
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB2_2
s_add_i32 s2, s4, 2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, s2, v0, s[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v0, v1, v2, 1
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b64 v[4:5], v[2:3], off
s_load_b256 s[4:11], s[0:1], 0x20
global_load_b64 v[6:7], v[0:1], off
s_waitcnt vmcnt(1) lgkmcnt(0)
v_mul_f64 v[8:9], v[4:5], s[4:5]
v_add_f64 v[10:11], v[4:5], -s[8:9]
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[8:9], v[8:9], v[10:11]
v_mul_f64 v[8:9], v[12:13], v[8:9]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[4:5], v[6:7], v[8:9]
v_fma_f64 v[4:5], -v[6:7], s[6:7], v[4:5]
global_store_b64 v[2:3], v[4:5], off
global_load_b64 v[2:3], v[0:1], off
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x40
s_load_b64 s[0:1], s[0:1], 0x50
s_waitcnt lgkmcnt(0)
v_add_f64 v[6:7], v[4:5], s[14:15]
s_waitcnt vmcnt(0)
v_mul_f64 v[8:9], v[2:3], s[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[10:11], null, v[6:7], v[6:7], v[8:9]
v_div_scale_f64 v[16:17], vcc_lo, v[8:9], v[6:7], v[8:9]
v_rcp_f64_e32 v[12:13], v[10:11]
s_waitcnt_depctr 0xfff
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
v_mul_f64 v[14:15], v[16:17], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[6:7], v[10:11], v[6:7], v[8:9]
v_add_f64 v[8:9], v[4:5], -s[0:1]
v_mul_f64 v[4:5], v[4:5], s[4:5]
v_add_f64 v[6:7], v[6:7], s[10:11]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -1.0
v_mul_f64 v[6:7], v[6:7], s[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], -v[4:5], v[8:9], -v[2:3]
v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
global_store_b64 v[0:1], v[2:3], off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13solve_for_odePdS_diiddddddd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13solve_for_odePdS_diiddddddd, .Lfunc_end2-_Z13solve_for_odePdS_diiddddddd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17mirror_boundariesPdii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17mirror_boundariesPdii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13solve_for_pdePdPKddii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13solve_for_pdePdPKddii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 8
.value_kind: by_value
- .offset: 56
.size: 8
.value_kind: by_value
- .offset: 64
.size: 8
.value_kind: by_value
- .offset: 72
.size: 8
.value_kind: by_value
- .offset: 80
.size: 8
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13solve_for_odePdS_diiddddddd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13solve_for_odePdS_diiddddddd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
Implement your CUDA kernel in this file
*/
__global__ void mirror_boundaries(double *E_prev, const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if (col == 1) {
E_prev[row*(n+2)] = E_prev[row*(n+2) + 2];
E_prev[row*(n+2) + n + 1] = E_prev[row*(n+2) + n - 1];
}
if (row == 1) {
E_prev[col] = E_prev[2*(n+2) + col];
E_prev[(m+1)*(n+2) + col] = E_prev[(m-1)*(n+2) + col];
}
}
__global__ void solve_for_pde (double *E, const double *E_prev, const double alpha,
const int n, const int m)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n))
E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);
}
__global__ void solve_for_ode (double *E, double *R, const double alpha,
const int n, const int m, const double kk,
const double dt, const double a, const double epsilon,
const double M1,const double M2, const double b)
{
int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
int col = blockIdx.x*blockDim.x + threadIdx.x + 1;
if ((row - 1 < m) && (col - 1 < n)) {
E[row*(n+2)+col] = E[row*(n+2)+col] - dt*(kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - a)*(E[row*(n+2)+col] - 1) + E[row*(n+2)+col]*R[row*(n+2)+col]);
R[row*(n+2)+col] = R[row*(n+2)+col] + dt*(epsilon + M1*R[row*(n+2)+col]/(E[row*(n+2)+col] + M2))*(-R[row*(n+2)+col] - kk*E[row*(n+2)+col]*(E[row*(n+2)+col] - b - 1));
}
} | .text
.file "cardiacsim_kernels.hip"
.globl _Z32__device_stub__mirror_boundariesPdii # -- Begin function _Z32__device_stub__mirror_boundariesPdii
.p2align 4, 0x90
.type _Z32__device_stub__mirror_boundariesPdii,@function
_Z32__device_stub__mirror_boundariesPdii: # @_Z32__device_stub__mirror_boundariesPdii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17mirror_boundariesPdii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__mirror_boundariesPdii, .Lfunc_end0-_Z32__device_stub__mirror_boundariesPdii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__solve_for_pdePdPKddii # -- Begin function _Z28__device_stub__solve_for_pdePdPKddii
.p2align 4, 0x90
.type _Z28__device_stub__solve_for_pdePdPKddii,@function
_Z28__device_stub__solve_for_pdePdPKddii: # @_Z28__device_stub__solve_for_pdePdPKddii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13solve_for_pdePdPKddii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__solve_for_pdePdPKddii, .Lfunc_end1-_Z28__device_stub__solve_for_pdePdPKddii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__solve_for_odePdS_diiddddddd # -- Begin function _Z28__device_stub__solve_for_odePdS_diiddddddd
.p2align 4, 0x90
.type _Z28__device_stub__solve_for_odePdS_diiddddddd,@function
_Z28__device_stub__solve_for_odePdS_diiddddddd: # @_Z28__device_stub__solve_for_odePdS_diiddddddd
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movsd %xmm0, 120(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm1, 112(%rsp)
movsd %xmm2, 104(%rsp)
movsd %xmm3, 96(%rsp)
movsd %xmm4, 88(%rsp)
movsd %xmm5, 80(%rsp)
movsd %xmm6, 72(%rsp)
movsd %xmm7, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13solve_for_odePdS_diiddddddd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end2:
.size _Z28__device_stub__solve_for_odePdS_diiddddddd, .Lfunc_end2-_Z28__device_stub__solve_for_odePdS_diiddddddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17mirror_boundariesPdii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13solve_for_pdePdPKddii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13solve_for_odePdS_diiddddddd, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17mirror_boundariesPdii,@object # @_Z17mirror_boundariesPdii
.section .rodata,"a",@progbits
.globl _Z17mirror_boundariesPdii
.p2align 3, 0x0
_Z17mirror_boundariesPdii:
.quad _Z32__device_stub__mirror_boundariesPdii
.size _Z17mirror_boundariesPdii, 8
.type _Z13solve_for_pdePdPKddii,@object # @_Z13solve_for_pdePdPKddii
.globl _Z13solve_for_pdePdPKddii
.p2align 3, 0x0
_Z13solve_for_pdePdPKddii:
.quad _Z28__device_stub__solve_for_pdePdPKddii
.size _Z13solve_for_pdePdPKddii, 8
.type _Z13solve_for_odePdS_diiddddddd,@object # @_Z13solve_for_odePdS_diiddddddd
.globl _Z13solve_for_odePdS_diiddddddd
.p2align 3, 0x0
_Z13solve_for_odePdS_diiddddddd:
.quad _Z28__device_stub__solve_for_odePdS_diiddddddd
.size _Z13solve_for_odePdS_diiddddddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17mirror_boundariesPdii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13solve_for_pdePdPKddii"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13solve_for_odePdS_diiddddddd"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__mirror_boundariesPdii
.addrsig_sym _Z28__device_stub__solve_for_pdePdPKddii
.addrsig_sym _Z28__device_stub__solve_for_odePdS_diiddddddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17mirror_boundariesPdii
.addrsig_sym _Z13solve_for_pdePdPKddii
.addrsig_sym _Z13solve_for_odePdS_diiddddddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f8f6a_00000000-6_cardiacsim_kernels.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z39__device_stub__Z17mirror_boundariesPdiiPdii
.type _Z39__device_stub__Z17mirror_boundariesPdiiPdii, @function
_Z39__device_stub__Z17mirror_boundariesPdiiPdii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17mirror_boundariesPdii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z39__device_stub__Z17mirror_boundariesPdiiPdii, .-_Z39__device_stub__Z17mirror_boundariesPdiiPdii
.globl _Z17mirror_boundariesPdii
.type _Z17mirror_boundariesPdii, @function
_Z17mirror_boundariesPdii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z17mirror_boundariesPdiiPdii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17mirror_boundariesPdii, .-_Z17mirror_boundariesPdii
.globl _Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii
.type _Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii, @function
_Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13solve_for_pdePdPKddii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii, .-_Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii
.globl _Z13solve_for_pdePdPKddii
.type _Z13solve_for_pdePdPKddii, @function
_Z13solve_for_pdePdPKddii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z13solve_for_pdePdPKddiiPdPKddii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13solve_for_pdePdPKddii, .-_Z13solve_for_pdePdPKddii
.globl _Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd
.type _Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd, @function
_Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd:
.LFB2055:
.cfi_startproc
endbr64
subq $280, %rsp
.cfi_def_cfa_offset 288
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movsd %xmm0, 72(%rsp)
movl %edx, 68(%rsp)
movl %ecx, 64(%rsp)
movsd %xmm1, 56(%rsp)
movsd %xmm2, 48(%rsp)
movsd %xmm3, 40(%rsp)
movsd %xmm4, 32(%rsp)
movsd %xmm5, 24(%rsp)
movsd %xmm6, 16(%rsp)
movsd %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 72(%rsp), %rax
movq %rax, 176(%rsp)
leaq 68(%rsp), %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rax
movq %rax, 192(%rsp)
leaq 56(%rsp), %rax
movq %rax, 200(%rsp)
leaq 48(%rsp), %rax
movq %rax, 208(%rsp)
leaq 40(%rsp), %rax
movq %rax, 216(%rsp)
leaq 32(%rsp), %rax
movq %rax, 224(%rsp)
leaq 24(%rsp), %rax
movq %rax, 232(%rsp)
leaq 16(%rsp), %rax
movq %rax, 240(%rsp)
leaq 8(%rsp), %rax
movq %rax, 248(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $1, 124(%rsp)
movl $1, 128(%rsp)
movl $1, 132(%rsp)
leaq 104(%rsp), %rcx
leaq 96(%rsp), %rdx
leaq 124(%rsp), %rsi
leaq 112(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 104(%rsp)
.cfi_def_cfa_offset 296
pushq 104(%rsp)
.cfi_def_cfa_offset 304
leaq 176(%rsp), %r9
movq 140(%rsp), %rcx
movl 148(%rsp), %r8d
movq 128(%rsp), %rsi
movl 136(%rsp), %edx
leaq _Z13solve_for_odePdS_diiddddddd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 288
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd, .-_Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd
.globl _Z13solve_for_odePdS_diiddddddd
.type _Z13solve_for_odePdS_diiddddddd, @function
_Z13solve_for_odePdS_diiddddddd:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z13solve_for_odePdS_diidddddddPdS_diiddddddd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z13solve_for_odePdS_diiddddddd, .-_Z13solve_for_odePdS_diiddddddd
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z13solve_for_odePdS_diiddddddd"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z13solve_for_pdePdPKddii"
.LC2:
.string "_Z17mirror_boundariesPdii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13solve_for_odePdS_diiddddddd(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z13solve_for_pdePdPKddii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z17mirror_boundariesPdii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cardiacsim_kernels.hip"
.globl _Z32__device_stub__mirror_boundariesPdii # -- Begin function _Z32__device_stub__mirror_boundariesPdii
.p2align 4, 0x90
.type _Z32__device_stub__mirror_boundariesPdii,@function
_Z32__device_stub__mirror_boundariesPdii: # @_Z32__device_stub__mirror_boundariesPdii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17mirror_boundariesPdii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z32__device_stub__mirror_boundariesPdii, .Lfunc_end0-_Z32__device_stub__mirror_boundariesPdii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__solve_for_pdePdPKddii # -- Begin function _Z28__device_stub__solve_for_pdePdPKddii
.p2align 4, 0x90
.type _Z28__device_stub__solve_for_pdePdPKddii,@function
_Z28__device_stub__solve_for_pdePdPKddii: # @_Z28__device_stub__solve_for_pdePdPKddii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movsd %xmm0, 56(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13solve_for_pdePdPKddii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z28__device_stub__solve_for_pdePdPKddii, .Lfunc_end1-_Z28__device_stub__solve_for_pdePdPKddii
.cfi_endproc
# -- End function
.globl _Z28__device_stub__solve_for_odePdS_diiddddddd # -- Begin function _Z28__device_stub__solve_for_odePdS_diiddddddd
.p2align 4, 0x90
.type _Z28__device_stub__solve_for_odePdS_diiddddddd,@function
_Z28__device_stub__solve_for_odePdS_diiddddddd: # @_Z28__device_stub__solve_for_odePdS_diiddddddd
.cfi_startproc
# %bb.0:
subq $248, %rsp
.cfi_def_cfa_offset 256
movq %rdi, 136(%rsp)
movq %rsi, 128(%rsp)
movsd %xmm0, 120(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movsd %xmm1, 112(%rsp)
movsd %xmm2, 104(%rsp)
movsd %xmm3, 96(%rsp)
movsd %xmm4, 88(%rsp)
movsd %xmm5, 80(%rsp)
movsd %xmm6, 72(%rsp)
movsd %xmm7, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 12(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rax
movq %rax, 200(%rsp)
leaq 88(%rsp), %rax
movq %rax, 208(%rsp)
leaq 80(%rsp), %rax
movq %rax, 216(%rsp)
leaq 72(%rsp), %rax
movq %rax, 224(%rsp)
leaq 64(%rsp), %rax
movq %rax, 232(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13solve_for_odePdS_diiddddddd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $264, %rsp # imm = 0x108
.cfi_adjust_cfa_offset -264
retq
.Lfunc_end2:
.size _Z28__device_stub__solve_for_odePdS_diiddddddd, .Lfunc_end2-_Z28__device_stub__solve_for_odePdS_diiddddddd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17mirror_boundariesPdii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13solve_for_pdePdPKddii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13solve_for_odePdS_diiddddddd, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17mirror_boundariesPdii,@object # @_Z17mirror_boundariesPdii
.section .rodata,"a",@progbits
.globl _Z17mirror_boundariesPdii
.p2align 3, 0x0
_Z17mirror_boundariesPdii:
.quad _Z32__device_stub__mirror_boundariesPdii
.size _Z17mirror_boundariesPdii, 8
.type _Z13solve_for_pdePdPKddii,@object # @_Z13solve_for_pdePdPKddii
.globl _Z13solve_for_pdePdPKddii
.p2align 3, 0x0
_Z13solve_for_pdePdPKddii:
.quad _Z28__device_stub__solve_for_pdePdPKddii
.size _Z13solve_for_pdePdPKddii, 8
.type _Z13solve_for_odePdS_diiddddddd,@object # @_Z13solve_for_odePdS_diiddddddd
.globl _Z13solve_for_odePdS_diiddddddd
.p2align 3, 0x0
_Z13solve_for_odePdS_diiddddddd:
.quad _Z28__device_stub__solve_for_odePdS_diiddddddd
.size _Z13solve_for_odePdS_diiddddddd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17mirror_boundariesPdii"
.size .L__unnamed_1, 26
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13solve_for_pdePdPKddii"
.size .L__unnamed_2, 26
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z13solve_for_odePdS_diiddddddd"
.size .L__unnamed_3, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__mirror_boundariesPdii
.addrsig_sym _Z28__device_stub__solve_for_pdePdPKddii
.addrsig_sym _Z28__device_stub__solve_for_odePdS_diiddddddd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17mirror_boundariesPdii
.addrsig_sym _Z13solve_for_pdePdPKddii
.addrsig_sym _Z13solve_for_odePdS_diiddddddd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#define block_size 32
__global__ void calculation( int *a,
int *b,
int *c,
int constant,
int vector_size ) {
// write your code here
// Declare shared memory
// Bring in the data from global memory into shared memory
// Synchronize
// Do calculation using the values in shared memory
// Write output
}
int main( int argc, char* argv[] ) {
// Parse Input arguments
// Check the number of arguments (we only receive command + vector size)
if (argc != 2) {
// Tell the user how to run the program
printf ("Usage: %s vector_size\n", argv[0]);
// "Usage messages" are a conventional way of telling the user
// how to run a program if they enter the command incorrectly.
return 1;
}
// Set GPU Variables based on input arguments
int vector_size = atoi(argv[1]);
int grid_size = ((vector_size-1)/block_size) + 1;
// Set device that we will use for our cuda code
// It will be either 0 or 1
cudaSetDevice(0);
// Time Variables
cudaEvent_t start_cpu, start_gpu;
cudaEvent_t stop_cpu, stop_gpu;
cudaEventCreate (&start_cpu);
cudaEventCreate (&start_gpu);
cudaEventCreate (&stop_cpu);
cudaEventCreate (&stop_gpu);
float time;
// Input Arrays and variables
int *a = new int [vector_size];
int *b = new int [vector_size];
int *c_cpu = new int [vector_size];
int *c_gpu = new int [vector_size];
int constant = 4;
// Pointers in GPU memory
int *dev_a;
int *dev_b;
int *dev_c;
// fill the arrays 'a' and 'b' on the CPU
printf("Filling up input arrays with random values between 1 and 10.\n");
for (int i = 0; i < vector_size; i++) {
a[i] = rand()%10;
b[i] = rand()%10;
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
cudaEventRecord(start_cpu,0);
// Calculate C in the CPU
for (int i = 0; i < vector_size; i++) {
// Read in inputs
int prev_a = a[i>0?i-1:(vector_size-1)];
int curr_a = a[i];
int post_a = a[i<(vector_size-1)?i+1:0];
int curr_b = b[i];
// Do computation
int output_c = (prev_a-post_a)*curr_b + curr_a*constant;
// Write result
c_cpu[i] = output_c;
}
cudaEventRecord(stop_cpu,0);
cudaEventSynchronize(stop_cpu);
cudaEventElapsedTime(&time, start_cpu, stop_cpu);
printf("\tSequential Job Time: %.2f ms\n", time);
//
// GPU Calculation
//////////////////
printf("Running parallel job.\n");
cudaEventRecord(start_gpu,0);
// allocate the memory on the GPU
cudaMalloc( (void**)&dev_a, vector_size * sizeof(int) );
cudaMalloc( (void**)&dev_b, vector_size * sizeof(int) );
cudaMalloc( (void**)&dev_c, vector_size * sizeof(int) );
// set arrays to 0
cudaMemset(dev_a, 0, vector_size * sizeof(int));
cudaMemset(dev_b, 0, vector_size * sizeof(int));
cudaMemset(dev_c, 0, vector_size * sizeof(int));
// copy the arrays 'a' and 'b' to the GPU
cudaMemcpy( dev_a, a, vector_size * sizeof(int),
cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, b, vector_size * sizeof(int),
cudaMemcpyHostToDevice );
// run kernel
calculation<<<grid_size,block_size>>>( dev_a,
dev_b,
dev_c,
constant,
vector_size );
// copy the array 'c' back from the GPU to the CPU
cudaMemcpy( c_gpu, dev_c, vector_size * sizeof(int),
cudaMemcpyDeviceToHost );
cudaEventRecord(stop_gpu,0);
cudaEventSynchronize(stop_gpu);
cudaEventElapsedTime(&time, start_gpu, stop_gpu);
printf("\tParallel Job Time: %.2f ms\n", time);
// compare the results
int error = 0;
for (int i = 0; i < vector_size; i++) {
if (c_cpu[i] != c_gpu[i]){
error = 1;
printf( "Error starting element %d, %d != %d\n", i, c_gpu[i], c_cpu[i] );
}
if (error) break;
}
if (error == 0){
printf ("Correct result. No errors were found.\n");
}
// free the memory allocated on the GPU
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
// free cuda events
cudaEventDestroy (start_cpu);
cudaEventDestroy (start_gpu);
cudaEventDestroy (stop_cpu);
cudaEventDestroy (stop_gpu);
// free CPU memory
free(a);
free(b);
free(c_cpu);
free(c_gpu);
return 0;
} | code for sm_80
Function : _Z11calculationPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#define block_size 32
__global__ void calculation( int *a,
int *b,
int *c,
int constant,
int vector_size ) {
// write your code here
// Declare shared memory
// Bring in the data from global memory into shared memory
// Synchronize
// Do calculation using the values in shared memory
// Write output
}
int main( int argc, char* argv[] ) {
// Parse Input arguments
// Check the number of arguments (we only receive command + vector size)
if (argc != 2) {
// Tell the user how to run the program
printf ("Usage: %s vector_size\n", argv[0]);
// "Usage messages" are a conventional way of telling the user
// how to run a program if they enter the command incorrectly.
return 1;
}
// Set GPU Variables based on input arguments
int vector_size = atoi(argv[1]);
int grid_size = ((vector_size-1)/block_size) + 1;
// Set device that we will use for our cuda code
// It will be either 0 or 1
cudaSetDevice(0);
// Time Variables
cudaEvent_t start_cpu, start_gpu;
cudaEvent_t stop_cpu, stop_gpu;
cudaEventCreate (&start_cpu);
cudaEventCreate (&start_gpu);
cudaEventCreate (&stop_cpu);
cudaEventCreate (&stop_gpu);
float time;
// Input Arrays and variables
int *a = new int [vector_size];
int *b = new int [vector_size];
int *c_cpu = new int [vector_size];
int *c_gpu = new int [vector_size];
int constant = 4;
// Pointers in GPU memory
int *dev_a;
int *dev_b;
int *dev_c;
// fill the arrays 'a' and 'b' on the CPU
printf("Filling up input arrays with random values between 1 and 10.\n");
for (int i = 0; i < vector_size; i++) {
a[i] = rand()%10;
b[i] = rand()%10;
}
//
// CPU Calculation
//////////////////
printf("Running sequential job.\n");
cudaEventRecord(start_cpu,0);
// Calculate C in the CPU
for (int i = 0; i < vector_size; i++) {
// Read in inputs
int prev_a = a[i>0?i-1:(vector_size-1)];
int curr_a = a[i];
int post_a = a[i<(vector_size-1)?i+1:0];
int curr_b = b[i];
// Do computation
int output_c = (prev_a-post_a)*curr_b + curr_a*constant;
// Write result
c_cpu[i] = output_c;
}
cudaEventRecord(stop_cpu,0);
cudaEventSynchronize(stop_cpu);
cudaEventElapsedTime(&time, start_cpu, stop_cpu);
printf("\tSequential Job Time: %.2f ms\n", time);
//
// GPU Calculation
//////////////////
printf("Running parallel job.\n");
cudaEventRecord(start_gpu,0);
// allocate the memory on the GPU
cudaMalloc( (void**)&dev_a, vector_size * sizeof(int) );
cudaMalloc( (void**)&dev_b, vector_size * sizeof(int) );
cudaMalloc( (void**)&dev_c, vector_size * sizeof(int) );
// set arrays to 0
cudaMemset(dev_a, 0, vector_size * sizeof(int));
cudaMemset(dev_b, 0, vector_size * sizeof(int));
cudaMemset(dev_c, 0, vector_size * sizeof(int));
// copy the arrays 'a' and 'b' to the GPU
cudaMemcpy( dev_a, a, vector_size * sizeof(int),
cudaMemcpyHostToDevice );
cudaMemcpy( dev_b, b, vector_size * sizeof(int),
cudaMemcpyHostToDevice );
// run kernel
calculation<<<grid_size,block_size>>>( dev_a,
dev_b,
dev_c,
constant,
vector_size );
// copy the array 'c' back from the GPU to the CPU
cudaMemcpy( c_gpu, dev_c, vector_size * sizeof(int),
cudaMemcpyDeviceToHost );
cudaEventRecord(stop_gpu,0);
cudaEventSynchronize(stop_gpu);
cudaEventElapsedTime(&time, start_gpu, stop_gpu);
printf("\tParallel Job Time: %.2f ms\n", time);
// compare the results
int error = 0;
for (int i = 0; i < vector_size; i++) {
if (c_cpu[i] != c_gpu[i]){
error = 1;
printf( "Error starting element %d, %d != %d\n", i, c_gpu[i], c_cpu[i] );
}
if (error) break;
}
if (error == 0){
printf ("Correct result. No errors were found.\n");
}
// free the memory allocated on the GPU
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
// free cuda events
cudaEventDestroy (start_cpu);
cudaEventDestroy (start_gpu);
cudaEventDestroy (stop_cpu);
cudaEventDestroy (stop_gpu);
// free CPU memory
free(a);
free(b);
free(c_cpu);
free(c_gpu);
return 0;
} | .file "tmpxft_000fccd3_00000000-6_Modified.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11calculationPiS_S_iiPiS_S_ii
.type _Z37__device_stub__Z11calculationPiS_S_iiPiS_S_ii, @function
_Z37__device_stub__Z11calculationPiS_S_iiPiS_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11calculationPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z37__device_stub__Z11calculationPiS_S_iiPiS_S_ii, .-_Z37__device_stub__Z11calculationPiS_S_iiPiS_S_ii
.globl _Z11calculationPiS_S_ii
.type _Z11calculationPiS_S_ii, @function
_Z11calculationPiS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11calculationPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11calculationPiS_S_ii, .-_Z11calculationPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s vector_size\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Filling up input arrays with random values between 1 and 10.\n"
.section .rodata.str1.1
.LC2:
.string "Running sequential job.\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "\tSequential Job Time: %.2f ms\n"
.section .rodata.str1.1
.LC4:
.string "Running parallel job.\n"
.LC5:
.string "\tParallel Job Time: %.2f ms\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Error starting element %d, %d != %d\n"
.align 8
.LC7:
.string "Correct result. No errors were found.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $2, %edi
je .L12
movq (%rsi), %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $1, %eax
.L11:
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L36
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movq %rax, (%rsp)
movl %eax, 20(%rsp)
subl $1, %eax
movl %eax, 16(%rsp)
movl $32, %ecx
cltd
idivl %ecx
addl $1, %eax
movl %eax, 12(%rsp)
movl $0, %edi
call cudaSetDevice@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movslq %ebx, %rax
movabsq $2305843009213693950, %rdx
cmpq %rax, %rdx
jb .L14
leaq 0(,%rax,4), %r15
movq %r15, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r15, %rdi
call _Znam@PLT
movq %rax, %r13
movq %r15, %rdi
call _Znam@PLT
movq %rax, %r12
movq %r15, %rdi
call _Znam@PLT
movq %rax, %r14
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L37
movq (%rsp), %rax
leal -1(%rax), %eax
movl $0, %ebx
movq %r15, 24(%rsp)
movq %rax, %r15
.L18:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, 0(%r13,%rbx,4)
movq %rbx, %rax
addq $1, %rbx
cmpq %r15, %rax
jne .L18
movq 24(%rsp), %r15
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq -4(%r15), %rdi
movq %rdi, %rdx
movl $0, %ecx
movl $4, %eax
movl $0, %esi
movl 16(%rsp), %r8d
movl 20(%rsp), %r9d
jmp .L19
.L14:
movq 120(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
call __cxa_throw_bad_array_new_length@PLT
.L22:
leaq -4(%rax), %rdx
testl %ecx, %ecx
cmovle %rdi, %rdx
movq %r10, %rax
.L19:
movl 0(%rbp,%rdx), %edx
movl -4(%rbp,%rax), %r10d
cmpl %ecx, %r8d
movq %rsi, %r11
cmovg %rax, %r11
subl 0(%rbp,%r11), %edx
imull -4(%r13,%rax), %edx
leal (%rdx,%r10,4), %edx
movl %edx, -4(%r12,%rax)
addl $1, %ecx
leaq 4(%rax), %r10
cmpl %r9d, %ecx
jne .L22
.L28:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 56(%rsp), %rdx
movq 40(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
leaq 72(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 80(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 88(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movq %r15, %rdx
movl $0, %esi
movq 72(%rsp), %rdi
call cudaMemset@PLT
movq %r15, %rdx
movl $0, %esi
movq 80(%rsp), %rdi
call cudaMemset@PLT
movq %r15, %rdx
movl $0, %esi
movq 88(%rsp), %rdi
call cudaMemset@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r13, %rsi
movq 80(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 108(%rsp)
movl $1, 112(%rsp)
movl 12(%rsp), %eax
movl %eax, 96(%rsp)
movl $1, 100(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 108(%rsp), %rdx
movl $1, %ecx
movq 96(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L23:
movl $2, %ecx
movq %r15, %rdx
movq 88(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 36(%rsp), %rdi
movq 64(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq (%rsp), %rax
testl %eax, %eax
jle .L24
leal -1(%rax), %esi
movl $0, %edx
jmp .L27
.L38:
movl (%rsp), %r8d
movl $4, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z37__device_stub__Z11calculationPiS_S_iiPiS_S_ii
jmp .L23
.L32:
movq %rax, %rdx
.L27:
movl (%r12,%rdx,4), %r8d
movl (%r14,%rdx,4), %ecx
cmpl %ecx, %r8d
jne .L39
leaq 1(%rdx), %rax
cmpq %rsi, %rdx
jne .L32
.L24:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L39:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L26:
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 80(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 48(%rsp), %rdi
call cudaEventDestroy@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movl $0, %eax
jmp .L11
.L37:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
jmp .L28
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z11calculationPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z11calculationPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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