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stringclasses 7
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stringlengths 10
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You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
/*
matNormInf.cu
Finds infinity-norm of a matrix
April 2013
Nicolas Sawaya
*/
//For matrix infinity-norm, sum all rows
//Remember this is in column format, so sum
//Btw with lanczos this can be made much less complicated
__global__ void matNormInf(double* mat, double* result) {
int row = threadIdx.x;
int m = blockDim.x;
double rowSum = 0.;
int i;
for(i=0;i<m;i++){
//Matrix is in column-major format
rowSum = rowSum + mat[i*m + row];
}
result[row] = rowSum;
}
|
code for sm_80
Function : _Z10matNormInfPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0060*/ @!P0 BRA 0x860 ; /* 0x000007f000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*0080*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0090*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fd800000001ff */
/*00c0*/ @!P0 BRA 0x7b0 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R5, -R4, c[0x0][0x0], RZ ; /* 0x0000000004057a10 */
/* 0x000fe20007ffe1ff */
/*00e0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*00f0*/ MOV R21, 0x8 ; /* 0x0000000800157802 */
/* 0x000fe40000000f00 */
/*0100*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.WIDE R20, R0, R21, c[0x0][0x160] ; /* 0x0000580000147625 */
/* 0x001fd400078e0215 */
/*0130*/ @!P0 BRA 0x6b0 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x4c0 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x0000a2000c1e1b00 */
/*0190*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x000fca00078e0214 */
/*01a0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x0002e2000c1e1b00 */
/*01b0*/ IMAD.WIDE R24, R2, 0x8, R22 ; /* 0x0000000802187825 */
/* 0x000fca00078e0216 */
/*01c0*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000962000c1e1b00 */
/*01d0*/ IMAD.WIDE R26, R2, 0x8, R24 ; /* 0x00000008021a7825 */
/* 0x000fca00078e0218 */
/*01e0*/ LDG.E.64 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x000162000c1e1b00 */
/*01f0*/ IMAD.WIDE R6, R2, 0x8, R26 ; /* 0x0000000802067825 */
/* 0x000fca00078e021a */
/*0200*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000162000c1e1b00 */
/*0210*/ IMAD.WIDE R28, R2, 0x8, R6 ; /* 0x00000008021c7825 */
/* 0x000fca00078e0206 */
/*0220*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x001164000c1e1b00 */
/*0230*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x001fca00078e021c */
/*0240*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000164000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x001fca00078e021c */
/*0260*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002162000c1e1b00 */
/*0270*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x010fcc00078e021c */
/*0280*/ IMAD.WIDE R26, R2, 0x8, R24 ; /* 0x00000008021a7825 */
/* 0x000fe200078e0218 */
/*0290*/ DADD R18, R8, R18 ; /* 0x0000000008127229 */
/* 0x0042e40000000012 */
/*02a0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0022a8000c1e1b00 */
/*02b0*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x0087480000000010 */
/*02c0*/ LDG.E.64 R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x008724000c1e1b00 */
/*02d0*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x020f62000000000e */
/*02e0*/ IMAD.WIDE R26, R2, 0x8, R26 ; /* 0x00000008021a7825 */
/* 0x008fca00078e021a */
/*02f0*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x020ee2000000000c */
/*0300*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b22000c1e1b00 */
/*0310*/ IMAD.WIDE R24, R2, 0x8, R26 ; /* 0x0000000802187825 */
/* 0x002fc800078e021a */
/*0320*/ DADD R10, R12, R10 ; /* 0x000000000c0a7229 */
/* 0x008e62000000000a */
/*0330*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000722000c1e1b00 */
/*0340*/ IMAD.WIDE R28, R2, 0x8, R24 ; /* 0x00000008021c7825 */
/* 0x001fc800078e0218 */
/*0350*/ DADD R6, R10, R6 ; /* 0x000000000a067229 */
/* 0x002e220000000006 */
/*0360*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x000324000c1e1b00 */
/*0370*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x002fc600078e021c */
/*0380*/ DADD R20, R6, R20 ; /* 0x0000000006147229 */
/* 0x0010640000000014 */
/*0390*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000f22000c1e1b00 */
/*03a0*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x008fca00078e021c */
/*03b0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x001ee2000c1e1b00 */
/*03c0*/ IMAD.WIDE R26, R2, 0x8, R24 ; /* 0x00000008021a7825 */
/* 0x020fe200078e0218 */
/*03d0*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0020880000000016 */
/*03e0*/ LDG.E.64 R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x001f62000c1e1b00 */
/*03f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe40007ffe0ff */
/*0400*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0410*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0420*/ DADD R8, R22, R8 ; /* 0x0000000016087229 */
/* 0x004f0c0000000008 */
/*0430*/ DADD R8, R8, R18 ; /* 0x0000000008087229 */
/* 0x010e0c0000000012 */
/*0440*/ DADD R8, R8, R16 ; /* 0x0000000008087229 */
/* 0x001e0c0000000010 */
/*0450*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x001e0c000000000e */
/*0460*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x001e0c000000000c */
/*0470*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x001ecc000000000a */
/*0480*/ DADD R6, R8, R6 ; /* 0x0000000008067229 */
/* 0x008f4c0000000006 */
/*0490*/ DADD R18, R6, R20 ; /* 0x0000000006127229 */
/* 0x0200640000000014 */
/*04a0*/ IMAD.WIDE R20, R2, 0x8, R26 ; /* 0x0000000802147825 */
/* 0x001fe200078e021a */
/*04b0*/ @P1 BRA 0x180 ; /* 0xfffffcc000001947 */
/* 0x002fea000383ffff */
/*04c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*04d0*/ @!P1 BRA 0x690 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0000a2000c1e1b00 */
/*04f0*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x000fca00078e0214 */
/*0500*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0002e2000c1e1b00 */
/*0510*/ IMAD.WIDE R26, R2, 0x8, R22 ; /* 0x00000008021a7825 */
/* 0x000fca00078e0216 */
/*0520*/ LDG.E.64 R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000f22000c1e1b00 */
/*0530*/ IMAD.WIDE R28, R2, 0x8, R26 ; /* 0x00000008021c7825 */
/* 0x000fca00078e021a */
/*0540*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000b24000c1e1b00 */
/*0550*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x020fca00078e021c */
/*0560*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x000f62000c1e1b00 */
/*0570*/ IMAD.WIDE R16, R2, 0x8, R28 ; /* 0x0000000802107825 */
/* 0x000fca00078e021c */
/*0580*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000362000c1e1b00 */
/*0590*/ IMAD.WIDE R20, R2, 0x8, R16 ; /* 0x0000000802147825 */
/* 0x001fca00078e0210 */
/*05a0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x002164000c1e1b00 */
/*05b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*05c0*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000162000c1e1b00 */
/*05d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*05e0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fe200078e0214 */
/*0610*/ DADD R24, R18, R24 ; /* 0x0000000012187229 */
/* 0x004ecc0000000018 */
/*0620*/ DADD R6, R24, R6 ; /* 0x0000000018067229 */
/* 0x008f0c0000000006 */
/*0630*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x010e0c0000000008 */
/*0640*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x001f4c000000000a */
/*0650*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x020e0c000000000c */
/*0660*/ DADD R6, R6, R14 ; /* 0x0000000006067229 */
/* 0x001e0c000000000e */
/*0670*/ DADD R6, R6, R16 ; /* 0x0000000006067229 */
/* 0x001e0c0000000010 */
/*0680*/ DADD R18, R6, R22 ; /* 0x0000000006127229 */
/* 0x0010480000000016 */
/*0690*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*06a0*/ @!P0 BRA 0x7b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*06b0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0010a2000c1e1b00 */
/*06c0*/ IMAD.WIDE R14, R2, 0x8, R20 ; /* 0x00000008020e7825 */
/* 0x000fca00078e0214 */
/*06d0*/ LDG.E.64 R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000ee2000c1e1b00 */
/*06e0*/ IMAD.WIDE R16, R2, 0x8, R14 ; /* 0x0000000802107825 */
/* 0x000fca00078e020e */
/*06f0*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000f22000c1e1b00 */
/*0700*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0710*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f62000c1e1b00 */
/*0720*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0730*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fe200078e0216 */
/*0740*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*0750*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0760*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x006ecc0000000012 */
/*0770*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x008f0c0000000008 */
/*0780*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x010f4c000000000a */
/*0790*/ DADD R18, R6, R12 ; /* 0x0000000006127229 */
/* 0x020064000000000c */
/*07a0*/ @P0 BRA 0x6b0 ; /* 0xffffff0000000947 */
/* 0x003fea000383ffff */
/*07b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*07c0*/ @!P0 BRA 0x860 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*07d0*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x001fe20000000f00 */
/*07e0*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x000fc800078e0200 */
/*07f0*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0800*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0010a2000c1e1b00 */
/*0810*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0820*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0830*/ IMAD.WIDE R6, R2, 0x8, R6 ; /* 0x0000000802067825 */
/* 0x001fe200078e0206 */
/*0840*/ DADD R18, R8, R18 ; /* 0x0000000008127229 */
/* 0x0060560000000012 */
/*0850*/ @P0 BRA 0x800 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0860*/ MOV R3, 0x8 ; /* 0x0000000800037802 */
/* 0x000fca0000000f00 */
/*0870*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0203 */
/*0880*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
/*
matNormInf.cu
Finds infinity-norm of a matrix
April 2013
Nicolas Sawaya
*/
//For matrix infinity-norm, sum all rows
//Remember this is in column format, so sum
//Btw with lanczos this can be made much less complicated
__global__ void matNormInf(double* mat, double* result) {
int row = threadIdx.x;
int m = blockDim.x;
double rowSum = 0.;
int i;
for(i=0;i<m;i++){
//Matrix is in column-major format
rowSum = rowSum + mat[i*m + row];
}
result[row] = rowSum;
}
|
.file "tmpxft_0013a689_00000000-6_matNormInf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10matNormInfPdS_PdS_
.type _Z32__device_stub__Z10matNormInfPdS_PdS_, @function
_Z32__device_stub__Z10matNormInfPdS_PdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10matNormInfPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10matNormInfPdS_PdS_, .-_Z32__device_stub__Z10matNormInfPdS_PdS_
.globl _Z10matNormInfPdS_
.type _Z10matNormInfPdS_, @function
_Z10matNormInfPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10matNormInfPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10matNormInfPdS_, .-_Z10matNormInfPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10matNormInfPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matNormInfPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
matNormInf.cu
Finds infinity-norm of a matrix
April 2013
Nicolas Sawaya
*/
//For matrix infinity-norm, sum all rows
//Remember this is in column format, so sum
//Btw with lanczos this can be made much less complicated
__global__ void matNormInf(double* mat, double* result) {
int row = threadIdx.x;
int m = blockDim.x;
double rowSum = 0.;
int i;
for(i=0;i<m;i++){
//Matrix is in column-major format
rowSum = rowSum + mat[i*m + row];
}
result[row] = rowSum;
}
|
#include <hip/hip_runtime.h>
/*
matNormInf.cu
Finds infinity-norm of a matrix
April 2013
Nicolas Sawaya
*/
//For matrix infinity-norm, sum all rows
//Remember this is in column format, so sum
//Btw with lanczos this can be made much less complicated
__global__ void matNormInf(double* mat, double* result) {
int row = threadIdx.x;
int m = blockDim.x;
double rowSum = 0.;
int i;
for(i=0;i<m;i++){
//Matrix is in column-major format
rowSum = rowSum + mat[i*m + row];
}
result[row] = rowSum;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
/*
matNormInf.cu
Finds infinity-norm of a matrix
April 2013
Nicolas Sawaya
*/
//For matrix infinity-norm, sum all rows
//Remember this is in column format, so sum
//Btw with lanczos this can be made much less complicated
__global__ void matNormInf(double* mat, double* result) {
int row = threadIdx.x;
int m = blockDim.x;
double rowSum = 0.;
int i;
for(i=0;i<m;i++){
//Matrix is in column-major format
rowSum = rowSum + mat[i*m + row];
}
result[row] = rowSum;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matNormInfPdS_
.globl _Z10matNormInfPdS_
.p2align 8
.type _Z10matNormInfPdS_,@function
_Z10matNormInfPdS_:
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s2, s3, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_mov_b32 s2, 0
s_cbranch_vccnz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 3, v0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_and_b32 s3, 0xffff, s3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s4, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s5, 0, s4
s_lshl_b32 s4, s3, 3
.LBB0_2:
global_load_b64 v[5:6], v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s2, v4, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
s_waitcnt vmcnt(0)
v_add_f64 v[1:2], v[1:2], v[5:6]
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[1:2], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matNormInfPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matNormInfPdS_, .Lfunc_end0-_Z10matNormInfPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matNormInfPdS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10matNormInfPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
/*
matNormInf.cu
Finds infinity-norm of a matrix
April 2013
Nicolas Sawaya
*/
//For matrix infinity-norm, sum all rows
//Remember this is in column format, so sum
//Btw with lanczos this can be made much less complicated
__global__ void matNormInf(double* mat, double* result) {
int row = threadIdx.x;
int m = blockDim.x;
double rowSum = 0.;
int i;
for(i=0;i<m;i++){
//Matrix is in column-major format
rowSum = rowSum + mat[i*m + row];
}
result[row] = rowSum;
}
|
.text
.file "matNormInf.hip"
.globl _Z25__device_stub__matNormInfPdS_ # -- Begin function _Z25__device_stub__matNormInfPdS_
.p2align 4, 0x90
.type _Z25__device_stub__matNormInfPdS_,@function
_Z25__device_stub__matNormInfPdS_: # @_Z25__device_stub__matNormInfPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10matNormInfPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__matNormInfPdS_, .Lfunc_end0-_Z25__device_stub__matNormInfPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matNormInfPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matNormInfPdS_,@object # @_Z10matNormInfPdS_
.section .rodata,"a",@progbits
.globl _Z10matNormInfPdS_
.p2align 3, 0x0
_Z10matNormInfPdS_:
.quad _Z25__device_stub__matNormInfPdS_
.size _Z10matNormInfPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matNormInfPdS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matNormInfPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matNormInfPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z10matNormInfPdS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ MOV R2, c[0x0][0x0] ; /* 0x0000000000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe4000001ff00 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*0060*/ @!P0 BRA 0x860 ; /* 0x000007f000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R3, R2.reuse, -0x1, RZ ; /* 0xffffffff02037810 */
/* 0x040fe20007ffe0ff */
/*0080*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*0090*/ LOP3.LUT R4, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302047812 */
/* 0x000fe400078ec0ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f06070 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fd800000001ff */
/*00c0*/ @!P0 BRA 0x7b0 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R5, -R4, c[0x0][0x0], RZ ; /* 0x0000000004057a10 */
/* 0x000fe20007ffe1ff */
/*00e0*/ CS2R R18, SRZ ; /* 0x0000000000127805 */
/* 0x000fe2000001ff00 */
/*00f0*/ MOV R21, 0x8 ; /* 0x0000000800157802 */
/* 0x000fe40000000f00 */
/*0100*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0110*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fe20000000f00 */
/*0120*/ IMAD.WIDE R20, R0, R21, c[0x0][0x160] ; /* 0x0000580000147625 */
/* 0x001fd400078e0215 */
/*0130*/ @!P0 BRA 0x6b0 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*0140*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0150*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0160*/ @!P1 BRA 0x4c0 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*0170*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0180*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x0000a2000c1e1b00 */
/*0190*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x000fca00078e0214 */
/*01a0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x0002e2000c1e1b00 */
/*01b0*/ IMAD.WIDE R24, R2, 0x8, R22 ; /* 0x0000000802187825 */
/* 0x000fca00078e0216 */
/*01c0*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000962000c1e1b00 */
/*01d0*/ IMAD.WIDE R26, R2, 0x8, R24 ; /* 0x00000008021a7825 */
/* 0x000fca00078e0218 */
/*01e0*/ LDG.E.64 R12, [R26.64] ; /* 0x000000041a0c7981 */
/* 0x000162000c1e1b00 */
/*01f0*/ IMAD.WIDE R6, R2, 0x8, R26 ; /* 0x0000000802067825 */
/* 0x000fca00078e021a */
/*0200*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000162000c1e1b00 */
/*0210*/ IMAD.WIDE R28, R2, 0x8, R6 ; /* 0x00000008021c7825 */
/* 0x000fca00078e0206 */
/*0220*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x001164000c1e1b00 */
/*0230*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x001fca00078e021c */
/*0240*/ LDG.E.64 R20, [R28.64] ; /* 0x000000041c147981 */
/* 0x000164000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x001fca00078e021c */
/*0260*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002162000c1e1b00 */
/*0270*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x010fcc00078e021c */
/*0280*/ IMAD.WIDE R26, R2, 0x8, R24 ; /* 0x00000008021a7825 */
/* 0x000fe200078e0218 */
/*0290*/ DADD R18, R8, R18 ; /* 0x0000000008127229 */
/* 0x0042e40000000012 */
/*02a0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0022a8000c1e1b00 */
/*02b0*/ DADD R16, R18, R16 ; /* 0x0000000012107229 */
/* 0x0087480000000010 */
/*02c0*/ LDG.E.64 R18, [R26.64] ; /* 0x000000041a127981 */
/* 0x008724000c1e1b00 */
/*02d0*/ DADD R14, R16, R14 ; /* 0x00000000100e7229 */
/* 0x020f62000000000e */
/*02e0*/ IMAD.WIDE R26, R2, 0x8, R26 ; /* 0x00000008021a7825 */
/* 0x008fca00078e021a */
/*02f0*/ DADD R12, R14, R12 ; /* 0x000000000e0c7229 */
/* 0x020ee2000000000c */
/*0300*/ LDG.E.64 R16, [R26.64] ; /* 0x000000041a107981 */
/* 0x000b22000c1e1b00 */
/*0310*/ IMAD.WIDE R24, R2, 0x8, R26 ; /* 0x0000000802187825 */
/* 0x002fc800078e021a */
/*0320*/ DADD R10, R12, R10 ; /* 0x000000000c0a7229 */
/* 0x008e62000000000a */
/*0330*/ LDG.E.64 R14, [R24.64] ; /* 0x00000004180e7981 */
/* 0x000722000c1e1b00 */
/*0340*/ IMAD.WIDE R28, R2, 0x8, R24 ; /* 0x00000008021c7825 */
/* 0x001fc800078e0218 */
/*0350*/ DADD R6, R10, R6 ; /* 0x000000000a067229 */
/* 0x002e220000000006 */
/*0360*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x000324000c1e1b00 */
/*0370*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x002fc600078e021c */
/*0380*/ DADD R20, R6, R20 ; /* 0x0000000006147229 */
/* 0x0010640000000014 */
/*0390*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000f22000c1e1b00 */
/*03a0*/ IMAD.WIDE R24, R2, 0x8, R28 ; /* 0x0000000802187825 */
/* 0x008fca00078e021c */
/*03b0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x001ee2000c1e1b00 */
/*03c0*/ IMAD.WIDE R26, R2, 0x8, R24 ; /* 0x00000008021a7825 */
/* 0x020fe200078e0218 */
/*03d0*/ DADD R22, R20, R22 ; /* 0x0000000014167229 */
/* 0x0020880000000016 */
/*03e0*/ LDG.E.64 R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x001f62000c1e1b00 */
/*03f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe40007ffe0ff */
/*0400*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0410*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0420*/ DADD R8, R22, R8 ; /* 0x0000000016087229 */
/* 0x004f0c0000000008 */
/*0430*/ DADD R8, R8, R18 ; /* 0x0000000008087229 */
/* 0x010e0c0000000012 */
/*0440*/ DADD R8, R8, R16 ; /* 0x0000000008087229 */
/* 0x001e0c0000000010 */
/*0450*/ DADD R8, R8, R14 ; /* 0x0000000008087229 */
/* 0x001e0c000000000e */
/*0460*/ DADD R8, R8, R12 ; /* 0x0000000008087229 */
/* 0x001e0c000000000c */
/*0470*/ DADD R8, R8, R10 ; /* 0x0000000008087229 */
/* 0x001ecc000000000a */
/*0480*/ DADD R6, R8, R6 ; /* 0x0000000008067229 */
/* 0x008f4c0000000006 */
/*0490*/ DADD R18, R6, R20 ; /* 0x0000000006127229 */
/* 0x0200640000000014 */
/*04a0*/ IMAD.WIDE R20, R2, 0x8, R26 ; /* 0x0000000802147825 */
/* 0x001fe200078e021a */
/*04b0*/ @P1 BRA 0x180 ; /* 0xfffffcc000001947 */
/* 0x002fea000383ffff */
/*04c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*04d0*/ @!P1 BRA 0x690 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*04e0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x0000a2000c1e1b00 */
/*04f0*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x000fca00078e0214 */
/*0500*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0002e2000c1e1b00 */
/*0510*/ IMAD.WIDE R26, R2, 0x8, R22 ; /* 0x00000008021a7825 */
/* 0x000fca00078e0216 */
/*0520*/ LDG.E.64 R8, [R26.64] ; /* 0x000000041a087981 */
/* 0x000f22000c1e1b00 */
/*0530*/ IMAD.WIDE R28, R2, 0x8, R26 ; /* 0x00000008021c7825 */
/* 0x000fca00078e021a */
/*0540*/ LDG.E.64 R10, [R28.64] ; /* 0x000000041c0a7981 */
/* 0x000b24000c1e1b00 */
/*0550*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x020fca00078e021c */
/*0560*/ LDG.E.64 R12, [R28.64] ; /* 0x000000041c0c7981 */
/* 0x000f62000c1e1b00 */
/*0570*/ IMAD.WIDE R16, R2, 0x8, R28 ; /* 0x0000000802107825 */
/* 0x000fca00078e021c */
/*0580*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000362000c1e1b00 */
/*0590*/ IMAD.WIDE R20, R2, 0x8, R16 ; /* 0x0000000802147825 */
/* 0x001fca00078e0210 */
/*05a0*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x002164000c1e1b00 */
/*05b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*05c0*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x000162000c1e1b00 */
/*05d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*05e0*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*05f0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0600*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fe200078e0214 */
/*0610*/ DADD R24, R18, R24 ; /* 0x0000000012187229 */
/* 0x004ecc0000000018 */
/*0620*/ DADD R6, R24, R6 ; /* 0x0000000018067229 */
/* 0x008f0c0000000006 */
/*0630*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x010e0c0000000008 */
/*0640*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x001f4c000000000a */
/*0650*/ DADD R6, R6, R12 ; /* 0x0000000006067229 */
/* 0x020e0c000000000c */
/*0660*/ DADD R6, R6, R14 ; /* 0x0000000006067229 */
/* 0x001e0c000000000e */
/*0670*/ DADD R6, R6, R16 ; /* 0x0000000006067229 */
/* 0x001e0c0000000010 */
/*0680*/ DADD R18, R6, R22 ; /* 0x0000000006127229 */
/* 0x0010480000000016 */
/*0690*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*06a0*/ @!P0 BRA 0x7b0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*06b0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0010a2000c1e1b00 */
/*06c0*/ IMAD.WIDE R14, R2, 0x8, R20 ; /* 0x00000008020e7825 */
/* 0x000fca00078e0214 */
/*06d0*/ LDG.E.64 R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000ee2000c1e1b00 */
/*06e0*/ IMAD.WIDE R16, R2, 0x8, R14 ; /* 0x0000000802107825 */
/* 0x000fca00078e020e */
/*06f0*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000f22000c1e1b00 */
/*0700*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0710*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f62000c1e1b00 */
/*0720*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0730*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fe200078e0216 */
/*0740*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fe40007ffe0ff */
/*0750*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0760*/ DADD R6, R6, R18 ; /* 0x0000000006067229 */
/* 0x006ecc0000000012 */
/*0770*/ DADD R6, R6, R8 ; /* 0x0000000006067229 */
/* 0x008f0c0000000008 */
/*0780*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x010f4c000000000a */
/*0790*/ DADD R18, R6, R12 ; /* 0x0000000006127229 */
/* 0x020064000000000c */
/*07a0*/ @P0 BRA 0x6b0 ; /* 0xffffff0000000947 */
/* 0x003fea000383ffff */
/*07b0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*07c0*/ @!P0 BRA 0x860 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*07d0*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x001fe20000000f00 */
/*07e0*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x000fc800078e0200 */
/*07f0*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0206 */
/*0800*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x0010a2000c1e1b00 */
/*0810*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fc80007ffe0ff */
/*0820*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe20003f05270 */
/*0830*/ IMAD.WIDE R6, R2, 0x8, R6 ; /* 0x0000000802067825 */
/* 0x001fe200078e0206 */
/*0840*/ DADD R18, R8, R18 ; /* 0x0000000008127229 */
/* 0x0060560000000012 */
/*0850*/ @P0 BRA 0x800 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*0860*/ MOV R3, 0x8 ; /* 0x0000000800037802 */
/* 0x000fca0000000f00 */
/*0870*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fca00078e0203 */
/*0880*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x002fe2000c101b04 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10matNormInfPdS_
.globl _Z10matNormInfPdS_
.p2align 8
.type _Z10matNormInfPdS_,@function
_Z10matNormInfPdS_:
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
v_cmp_eq_u16_e64 s2, s3, 0
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_mov_b32 s2, 0
s_cbranch_vccnz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 3, v0
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_and_b32 s3, 0xffff, s3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, s4, s4, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v4, null, s5, 0, s4
s_lshl_b32 s4, s3, 3
.LBB0_2:
global_load_b64 v[5:6], v[3:4], off
v_add_co_u32 v3, vcc_lo, v3, s4
v_add_co_ci_u32_e32 v4, vcc_lo, s2, v4, vcc_lo
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s3, 0
s_waitcnt vmcnt(0)
v_add_f64 v[1:2], v[1:2], v[5:6]
s_cbranch_scc1 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 3, v0
s_waitcnt lgkmcnt(0)
global_store_b64 v0, v[1:2], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10matNormInfPdS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10matNormInfPdS_, .Lfunc_end0-_Z10matNormInfPdS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10matNormInfPdS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z10matNormInfPdS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0013a689_00000000-6_matNormInf.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10matNormInfPdS_PdS_
.type _Z32__device_stub__Z10matNormInfPdS_PdS_, @function
_Z32__device_stub__Z10matNormInfPdS_PdS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10matNormInfPdS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10matNormInfPdS_PdS_, .-_Z32__device_stub__Z10matNormInfPdS_PdS_
.globl _Z10matNormInfPdS_
.type _Z10matNormInfPdS_, @function
_Z10matNormInfPdS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10matNormInfPdS_PdS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10matNormInfPdS_, .-_Z10matNormInfPdS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10matNormInfPdS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10matNormInfPdS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "matNormInf.hip"
.globl _Z25__device_stub__matNormInfPdS_ # -- Begin function _Z25__device_stub__matNormInfPdS_
.p2align 4, 0x90
.type _Z25__device_stub__matNormInfPdS_,@function
_Z25__device_stub__matNormInfPdS_: # @_Z25__device_stub__matNormInfPdS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10matNormInfPdS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z25__device_stub__matNormInfPdS_, .Lfunc_end0-_Z25__device_stub__matNormInfPdS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10matNormInfPdS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10matNormInfPdS_,@object # @_Z10matNormInfPdS_
.section .rodata,"a",@progbits
.globl _Z10matNormInfPdS_
.p2align 3, 0x0
_Z10matNormInfPdS_:
.quad _Z25__device_stub__matNormInfPdS_
.size _Z10matNormInfPdS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10matNormInfPdS_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__matNormInfPdS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10matNormInfPdS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void pool(unsigned char* image, unsigned char* new_image, unsigned height, unsigned width, int thread_count)
{
// process image
int offset = (blockIdx.x * blockDim.x + threadIdx.x)*4;
for (int i = offset; i < (width*height); i+=(thread_count*4) )
{
int x = i % (width * 2) * 2;
int y = i / (width * 2);
int p1 = 8 * width * y + x;
int p2 = 8 * width * y + x + 4;
int p3 = 8 * width * y + x + 4 * width;
int p4 = 8 * width * y + x + 4 * width + 4;
unsigned r[] = { image[p1], image[p2], image[p3], image[p4] };
unsigned g[] = { image[p1+1], image[p2+1], image[p3+1], image[p4+1] };
unsigned b[] = { image[p1+2], image[p2+2], image[p3+2], image[p4+2] };
unsigned a[] = { image[p1+3], image[p2+3], image[p3+3], image[p4+3] };
int rMax = r[0];
int gMax = g[0];
int bMax = b[0];
int aMax = a[0];
for (int j = 1; j < 4; j++ )
{
if (r[j] > rMax) rMax = r[j];
if (g[j] > gMax) gMax = g[j];
if (b[j] > bMax) bMax = b[j];
if (a[j] > aMax) aMax = a[j];
}
new_image[i] = rMax;
new_image[i+1] = gMax;
new_image[i+2] = bMax;
new_image[i+3] = aMax;
}
}
|
code for sm_80
Function : _Z4poolPhS_jji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R6, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R8, R2, 0x4, RZ ; /* 0x0000000402087824 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R8, R6, PT ; /* 0x000000060800720c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R7, R0.reuse, 0x2, RZ ; /* 0x0000000200077824 */
/* 0x040fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.SHL.U32 R10, R0, 0x8, RZ ; /* 0x00000008000a7824 */
/* 0x000fe400078e00ff */
/*00c0*/ I2F.U32.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e220000209000 */
/*00d0*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a07 */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05070 */
/*00f0*/ LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff097212 */
/* 0x000fc800078e33ff */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R11, R11, R3, RZ ; /* 0x000000030b0b7224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R11, R3, R11, R2 ; /* 0x0000000b030b7227 */
/* 0x000fcc00078e0002 */
/*0160*/ IMAD.HI.U32 R2, R11, R8, RZ ; /* 0x000000080b027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x001fc800078e0a02 */
/*0180*/ IMAD R4, R7, R4, R8 ; /* 0x0000000407047224 */
/* 0x000fca00078e0208 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f26070 */
/*01a0*/ @P1 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x0000000104041824 */
/* 0x000fe200078e0a07 */
/*01b0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P2, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f46070 */
/*01d0*/ @P2 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102022810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ SEL R3, R9, R2, !P0 ; /* 0x0000000209037207 */
/* 0x000fca0004000000 */
/*01f0*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a03 */
/*0200*/ IMAD R2, R7, R2, R8 ; /* 0x0000000207027224 */
/* 0x000fc800078e0208 */
/*0210*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD R3, R10, R3, R2 ; /* 0x000000030a037224 */
/* 0x000fc800078e0202 */
/*0230*/ IMAD R12, R0, 0x4, R3 ; /* 0x00000004000c7824 */
/* 0x000fe200078e0203 */
/*0240*/ IADD3 R4, P1, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fc80007f3e0ff */
/*0250*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P1 ; /* 0x0000590003057a11 */
/* 0x000fe400008f0eff */
/*0260*/ IADD3 R2, P1, R12, c[0x0][0x160], RZ ; /* 0x000058000c027a10 */
/* 0x000fc60007f3e0ff */
/*0270*/ LDG.E.U8 R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x0000a2000c1e1100 */
/*0280*/ LEA.HI.X.SX32 R3, R12, c[0x0][0x164], 0x1, P1 ; /* 0x000059000c037a11 */
/* 0x000fc600008f0eff */
/*0290*/ LDG.E.U8 R21, [R4.64+0x4] ; /* 0x0000040404157981 */
/* 0x0000a8000c1e1100 */
/*02a0*/ LDG.E.U8 R23, [R4.64+0x1] ; /* 0x0000010404177981 */
/* 0x0000e8000c1e1100 */
/*02b0*/ LDG.E.U8 R24, [R4.64+0x5] ; /* 0x0000050404187981 */
/* 0x0000e8000c1e1100 */
/*02c0*/ LDG.E.U8 R25, [R4.64+0x2] ; /* 0x0000020404197981 */
/* 0x000128000c1e1100 */
/*02d0*/ LDG.E.U8 R26, [R4.64+0x6] ; /* 0x00000604041a7981 */
/* 0x000128000c1e1100 */
/*02e0*/ LDG.E.U8 R18, [R4.64+0x3] ; /* 0x0000030404127981 */
/* 0x000168000c1e1100 */
/*02f0*/ LDG.E.U8 R27, [R4.64+0x7] ; /* 0x00000704041b7981 */
/* 0x000168000c1e1100 */
/*0300*/ LDG.E.U8 R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x000368000c1e1100 */
/*0310*/ LDG.E.U8 R12, [R2.64+0x1] ; /* 0x00000104020c7981 */
/* 0x000368000c1e1100 */
/*0320*/ LDG.E.U8 R17, [R2.64+0x2] ; /* 0x0000020402117981 */
/* 0x000368000c1e1100 */
/*0330*/ LDG.E.U8 R16, [R2.64+0x3] ; /* 0x0000030402107981 */
/* 0x000368000c1e1100 */
/*0340*/ LDG.E.U8 R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000368000c1e1100 */
/*0350*/ LDG.E.U8 R14, [R2.64+0x5] ; /* 0x00000504020e7981 */
/* 0x000368000c1e1100 */
/*0360*/ LDG.E.U8 R13, [R2.64+0x6] ; /* 0x00000604020d7981 */
/* 0x000368000c1e1100 */
/*0370*/ LDG.E.U8 R19, [R2.64+0x7] ; /* 0x0000070402137981 */
/* 0x000362000c1e1100 */
/*0380*/ IADD3 R4, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008047a10 */
/* 0x001fc80007f3e0ff */
/*0390*/ LEA.HI.X.SX32 R5, R8, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0008057a11 */
/* 0x000fe200008f0eff */
/*03a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff037624 */
/* 0x002fc800078e00ff */
/*03b0*/ IMAD R8, R3, 0x4, R8 ; /* 0x0000000403087824 */
/* 0x000fca00078e0208 */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R8, R6, PT ; /* 0x000000060800720c */
/* 0x000fe40003f26070 */
/*03d0*/ IMNMX.U32 R21, R20, R21, !PT ; /* 0x0000001514157217 */
/* 0x004fe40007800000 */
/*03e0*/ IMNMX.U32 R23, R23, R24, !PT ; /* 0x0000001817177217 */
/* 0x008fe40007800000 */
/*03f0*/ IMNMX.U32 R26, R25, R26, !PT ; /* 0x0000001a191a7217 */
/* 0x010fe40007800000 */
/*0400*/ IMNMX.U32 R27, R18, R27, !PT ; /* 0x0000001b121b7217 */
/* 0x020fe40007800000 */
/*0410*/ IMNMX.U32 R22, R22, R21, !PT ; /* 0x0000001516167217 */
/* 0x000fc40007800000 */
/*0420*/ IMNMX.U32 R23, R12, R23, !PT ; /* 0x000000170c177217 */
/* 0x000fe40007800000 */
/*0430*/ IMNMX.U32 R26, R17, R26, !PT ; /* 0x0000001a111a7217 */
/* 0x000fe40007800000 */
/*0440*/ IMNMX.U32 R16, R16, R27, !PT ; /* 0x0000001b10107217 */
/* 0x000fe40007800000 */
/*0450*/ IMNMX.U32 R15, R15, R22, !PT ; /* 0x000000160f0f7217 */
/* 0x000fe40007800000 */
/*0460*/ IMNMX.U32 R23, R14, R23, !PT ; /* 0x000000170e177217 */
/* 0x000fe40007800000 */
/*0470*/ IMNMX.U32 R13, R13, R26, !PT ; /* 0x0000001a0d0d7217 */
/* 0x000fc40007800000 */
/*0480*/ IMNMX.U32 R19, R19, R16, !PT ; /* 0x0000001013137217 */
/* 0x000fe20007800000 */
/*0490*/ STG.E.U8 [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101104 */
/*04a0*/ STG.E.U8 [R4.64+0x1], R23 ; /* 0x0000011704007986 */
/* 0x0001e8000c101104 */
/*04b0*/ STG.E.U8 [R4.64+0x2], R13 ; /* 0x0000020d04007986 */
/* 0x0001e8000c101104 */
/*04c0*/ STG.E.U8 [R4.64+0x3], R19 ; /* 0x0000031304007986 */
/* 0x0001e2000c101104 */
/*04d0*/ @!P1 BRA 0x160 ; /* 0xfffffc8000009947 */
/* 0x000fea000383ffff */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void pool(unsigned char* image, unsigned char* new_image, unsigned height, unsigned width, int thread_count)
{
// process image
int offset = (blockIdx.x * blockDim.x + threadIdx.x)*4;
for (int i = offset; i < (width*height); i+=(thread_count*4) )
{
int x = i % (width * 2) * 2;
int y = i / (width * 2);
int p1 = 8 * width * y + x;
int p2 = 8 * width * y + x + 4;
int p3 = 8 * width * y + x + 4 * width;
int p4 = 8 * width * y + x + 4 * width + 4;
unsigned r[] = { image[p1], image[p2], image[p3], image[p4] };
unsigned g[] = { image[p1+1], image[p2+1], image[p3+1], image[p4+1] };
unsigned b[] = { image[p1+2], image[p2+2], image[p3+2], image[p4+2] };
unsigned a[] = { image[p1+3], image[p2+3], image[p3+3], image[p4+3] };
int rMax = r[0];
int gMax = g[0];
int bMax = b[0];
int aMax = a[0];
for (int j = 1; j < 4; j++ )
{
if (r[j] > rMax) rMax = r[j];
if (g[j] > gMax) gMax = g[j];
if (b[j] > bMax) bMax = b[j];
if (a[j] > aMax) aMax = a[j];
}
new_image[i] = rMax;
new_image[i+1] = gMax;
new_image[i+2] = bMax;
new_image[i+3] = aMax;
}
}
|
.file "tmpxft_001bc062_00000000-6_pool.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4poolPhS_jjiPhS_jji
.type _Z28__device_stub__Z4poolPhS_jjiPhS_jji, @function
_Z28__device_stub__Z4poolPhS_jjiPhS_jji:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4poolPhS_jji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z4poolPhS_jjiPhS_jji, .-_Z28__device_stub__Z4poolPhS_jjiPhS_jji
.globl _Z4poolPhS_jji
.type _Z4poolPhS_jji, @function
_Z4poolPhS_jji:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4poolPhS_jjiPhS_jji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4poolPhS_jji, .-_Z4poolPhS_jji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4poolPhS_jji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4poolPhS_jji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void pool(unsigned char* image, unsigned char* new_image, unsigned height, unsigned width, int thread_count)
{
// process image
int offset = (blockIdx.x * blockDim.x + threadIdx.x)*4;
for (int i = offset; i < (width*height); i+=(thread_count*4) )
{
int x = i % (width * 2) * 2;
int y = i / (width * 2);
int p1 = 8 * width * y + x;
int p2 = 8 * width * y + x + 4;
int p3 = 8 * width * y + x + 4 * width;
int p4 = 8 * width * y + x + 4 * width + 4;
unsigned r[] = { image[p1], image[p2], image[p3], image[p4] };
unsigned g[] = { image[p1+1], image[p2+1], image[p3+1], image[p4+1] };
unsigned b[] = { image[p1+2], image[p2+2], image[p3+2], image[p4+2] };
unsigned a[] = { image[p1+3], image[p2+3], image[p3+3], image[p4+3] };
int rMax = r[0];
int gMax = g[0];
int bMax = b[0];
int aMax = a[0];
for (int j = 1; j < 4; j++ )
{
if (r[j] > rMax) rMax = r[j];
if (g[j] > gMax) gMax = g[j];
if (b[j] > bMax) bMax = b[j];
if (a[j] > aMax) aMax = a[j];
}
new_image[i] = rMax;
new_image[i+1] = gMax;
new_image[i+2] = bMax;
new_image[i+3] = aMax;
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pool(unsigned char* image, unsigned char* new_image, unsigned height, unsigned width, int thread_count)
{
// process image
int offset = (blockIdx.x * blockDim.x + threadIdx.x)*4;
for (int i = offset; i < (width*height); i+=(thread_count*4) )
{
int x = i % (width * 2) * 2;
int y = i / (width * 2);
int p1 = 8 * width * y + x;
int p2 = 8 * width * y + x + 4;
int p3 = 8 * width * y + x + 4 * width;
int p4 = 8 * width * y + x + 4 * width + 4;
unsigned r[] = { image[p1], image[p2], image[p3], image[p4] };
unsigned g[] = { image[p1+1], image[p2+1], image[p3+1], image[p4+1] };
unsigned b[] = { image[p1+2], image[p2+2], image[p3+2], image[p4+2] };
unsigned a[] = { image[p1+3], image[p2+3], image[p3+3], image[p4+3] };
int rMax = r[0];
int gMax = g[0];
int bMax = b[0];
int aMax = a[0];
for (int j = 1; j < 4; j++ )
{
if (r[j] > rMax) rMax = r[j];
if (g[j] > gMax) gMax = g[j];
if (b[j] > bMax) bMax = b[j];
if (a[j] > aMax) aMax = a[j];
}
new_image[i] = rMax;
new_image[i+1] = gMax;
new_image[i+2] = bMax;
new_image[i+3] = aMax;
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pool(unsigned char* image, unsigned char* new_image, unsigned height, unsigned width, int thread_count)
{
// process image
int offset = (blockIdx.x * blockDim.x + threadIdx.x)*4;
for (int i = offset; i < (width*height); i+=(thread_count*4) )
{
int x = i % (width * 2) * 2;
int y = i / (width * 2);
int p1 = 8 * width * y + x;
int p2 = 8 * width * y + x + 4;
int p3 = 8 * width * y + x + 4 * width;
int p4 = 8 * width * y + x + 4 * width + 4;
unsigned r[] = { image[p1], image[p2], image[p3], image[p4] };
unsigned g[] = { image[p1+1], image[p2+1], image[p3+1], image[p4+1] };
unsigned b[] = { image[p1+2], image[p2+2], image[p3+2], image[p4+2] };
unsigned a[] = { image[p1+3], image[p2+3], image[p3+3], image[p4+3] };
int rMax = r[0];
int gMax = g[0];
int bMax = b[0];
int aMax = a[0];
for (int j = 1; j < 4; j++ )
{
if (r[j] > rMax) rMax = r[j];
if (g[j] > gMax) gMax = g[j];
if (b[j] > bMax) bMax = b[j];
if (a[j] > aMax) aMax = a[j];
}
new_image[i] = rMax;
new_image[i+1] = gMax;
new_image[i+2] = bMax;
new_image[i+3] = aMax;
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4poolPhS_jji
.globl _Z4poolPhS_jji
.p2align 8
.type _Z4poolPhS_jji,@function
_Z4poolPhS_jji:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
s_mul_i32 s15, s15, s4
s_mov_b32 s4, exec_lo
v_add_lshl_u32 v0, s15, v0, 2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_5
s_lshl_b32 s8, s3, 1
s_load_b32 s10, s[0:1], 0x18
v_cvt_f32_u32_e32 v1, s8
s_sub_i32 s4, 0, s8
s_lshl_b32 s9, s3, 3
s_lshl_b32 s3, s3, 2
s_mov_b32 s11, 0
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s4, v1
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s10, s10, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v1
s_mov_b64 s[0:1], 1
v_mul_lo_u32 v3, v2, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v3
v_subrev_nc_u32_e32 v5, s8, v3
v_cmp_le_u32_e32 vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_nc_u32 v4, 1, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v3
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_mul_lo_u32 v3, v2, s8
v_mul_lo_u32 v2, s9, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v3
v_lshl_add_u32 v6, v3, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, 5, v6
v_add_nc_u32_e32 v2, 4, v6
v_ashrrev_i32_e32 v3, 31, v6
v_add_nc_u32_e32 v29, s3, v6
v_add_co_u32 v7, vcc_lo, s4, v6
v_or_b32_e32 v4, 1, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v14, 31, v29
v_add_co_u32 v9, vcc_lo, s4, v2
v_ashrrev_i32_e32 v16, 31, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v29
v_or_b32_e32 v11, 2, v6
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_ashrrev_i32_e32 v18, 31, v5
v_add_co_u32 v15, vcc_lo, s4, v4
v_add_nc_u32_e32 v19, 4, v29
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_ashrrev_i32_e32 v20, 31, v11
v_add_co_u32 v17, vcc_lo, s4, v5
v_or_b32_e32 v21, 1, v29
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
v_ashrrev_i32_e32 v22, 31, v19
v_add_co_u32 v2, vcc_lo, s4, v11
v_add_nc_u32_e32 v23, 5, v29
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v20, vcc_lo
v_ashrrev_i32_e32 v4, 31, v21
v_add_co_u32 v19, vcc_lo, s4, v19
v_add_nc_u32_e32 v12, 6, v6
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v22, vcc_lo
v_ashrrev_i32_e32 v5, 31, v23
v_add_co_u32 v21, vcc_lo, s4, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s5, v4, vcc_lo
v_ashrrev_i32_e32 v25, 31, v12
v_add_co_u32 v23, vcc_lo, s4, v23
v_add_co_ci_u32_e32 v24, vcc_lo, s5, v5, vcc_lo
v_or_b32_e32 v11, 2, v29
v_add_co_u32 v4, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v25, vcc_lo
v_add_nc_u32_e32 v25, 6, v29
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v11
v_or_b32_e32 v27, 3, v6
v_add_co_u32 v11, vcc_lo, s4, v11
v_ashrrev_i32_e32 v26, 31, v25
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_ashrrev_i32_e32 v28, 31, v27
v_add_co_u32 v25, vcc_lo, s4, v25
v_add_nc_u32_e32 v30, 7, v6
v_add_co_ci_u32_e32 v26, vcc_lo, s5, v26, vcc_lo
v_add_co_u32 v27, vcc_lo, s4, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
s_clause 0x4
global_load_u8 v2, v[2:3], off
global_load_u8 v3, v[4:5], off
global_load_u8 v4, v[11:12], off
global_load_u8 v5, v[25:26], off
global_load_u8 v6, v[27:28], off
v_ashrrev_i32_e32 v11, 31, v30
v_or_b32_e32 v12, 3, v29
v_add_nc_u32_e32 v29, 7, v29
v_add_co_u32 v25, vcc_lo, s4, v30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v26, vcc_lo, s5, v11, vcc_lo
v_ashrrev_i32_e32 v11, 31, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v30, 31, v29
v_add_co_u32 v27, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v28, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v29, vcc_lo, s4, v29
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
s_clause 0xa
global_load_u8 v11, v[7:8], off
global_load_u8 v12, v[9:10], off
global_load_u8 v13, v[13:14], off
global_load_u8 v14, v[19:20], off
global_load_u8 v15, v[15:16], off
global_load_u8 v16, v[17:18], off
global_load_u8 v17, v[21:22], off
global_load_u8 v18, v[23:24], off
global_load_u8 v19, v[25:26], off
global_load_u8 v20, v[27:28], off
global_load_u8 v21, v[29:30], off
s_waitcnt vmcnt(15)
v_mov_b32_e32 v8, v2
s_waitcnt vmcnt(10)
v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v10, v11
s_waitcnt vmcnt(6)
v_mov_b32_e32 v9, v15
.p2align 6
.LBB0_3:
s_cmp_eq_u32 s0, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 2
s_waitcnt vmcnt(2)
v_dual_cndmask_b32 v22, v11, v12 :: v_dual_cndmask_b32 v25, v6, v19
v_dual_cndmask_b32 v23, v15, v16 :: v_dual_cndmask_b32 v24, v2, v3
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 3
s_waitcnt vmcnt(1)
v_dual_cndmask_b32 v22, v22, v13 :: v_dual_cndmask_b32 v25, v25, v20
v_dual_cndmask_b32 v23, v23, v17 :: v_dual_cndmask_b32 v24, v24, v4
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s0, s0, 1
s_waitcnt vmcnt(0)
v_dual_cndmask_b32 v22, v22, v14 :: v_dual_cndmask_b32 v25, v25, v21
v_dual_cndmask_b32 v23, v23, v18 :: v_dual_cndmask_b32 v24, v24, v5
s_addc_u32 s1, s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_max_u32_e32 v10, v22, v10
v_max_u32_e32 v7, v25, v7
s_delay_alu instid0(VALU_DEP_3)
v_max_u32_e32 v9, v23, v9
v_max_u32_e32 v8, v24, v8
s_cmp_eq_u32 s0, 4
s_cbranch_scc0 .LBB0_3
v_or_b32_e32 v4, 1, v0
v_ashrrev_i32_e32 v3, 31, v0
v_or_b32_e32 v6, 2, v0
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_ashrrev_i32_e32 v12, 31, v6
v_or_b32_e32 v13, 3, v0
v_add_nc_u32_e32 v0, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
v_ashrrev_i32_e32 v6, 31, v13
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_add_co_u32 v13, s0, s6, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, s7, v6, s0
s_or_b32 s11, vcc_lo, s11
s_clause 0x3
global_store_b8 v[2:3], v10, off
global_store_b8 v[4:5], v9, off
global_store_b8 v[11:12], v8, off
global_store_b8 v[13:14], v7, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4poolPhS_jji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4poolPhS_jji, .Lfunc_end0-_Z4poolPhS_jji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4poolPhS_jji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4poolPhS_jji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void pool(unsigned char* image, unsigned char* new_image, unsigned height, unsigned width, int thread_count)
{
// process image
int offset = (blockIdx.x * blockDim.x + threadIdx.x)*4;
for (int i = offset; i < (width*height); i+=(thread_count*4) )
{
int x = i % (width * 2) * 2;
int y = i / (width * 2);
int p1 = 8 * width * y + x;
int p2 = 8 * width * y + x + 4;
int p3 = 8 * width * y + x + 4 * width;
int p4 = 8 * width * y + x + 4 * width + 4;
unsigned r[] = { image[p1], image[p2], image[p3], image[p4] };
unsigned g[] = { image[p1+1], image[p2+1], image[p3+1], image[p4+1] };
unsigned b[] = { image[p1+2], image[p2+2], image[p3+2], image[p4+2] };
unsigned a[] = { image[p1+3], image[p2+3], image[p3+3], image[p4+3] };
int rMax = r[0];
int gMax = g[0];
int bMax = b[0];
int aMax = a[0];
for (int j = 1; j < 4; j++ )
{
if (r[j] > rMax) rMax = r[j];
if (g[j] > gMax) gMax = g[j];
if (b[j] > bMax) bMax = b[j];
if (a[j] > aMax) aMax = a[j];
}
new_image[i] = rMax;
new_image[i+1] = gMax;
new_image[i+2] = bMax;
new_image[i+3] = aMax;
}
}
|
.text
.file "pool.hip"
.globl _Z19__device_stub__poolPhS_jji # -- Begin function _Z19__device_stub__poolPhS_jji
.p2align 4, 0x90
.type _Z19__device_stub__poolPhS_jji,@function
_Z19__device_stub__poolPhS_jji: # @_Z19__device_stub__poolPhS_jji
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4poolPhS_jji, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__poolPhS_jji, .Lfunc_end0-_Z19__device_stub__poolPhS_jji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4poolPhS_jji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4poolPhS_jji,@object # @_Z4poolPhS_jji
.section .rodata,"a",@progbits
.globl _Z4poolPhS_jji
.p2align 3, 0x0
_Z4poolPhS_jji:
.quad _Z19__device_stub__poolPhS_jji
.size _Z4poolPhS_jji, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4poolPhS_jji"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__poolPhS_jji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4poolPhS_jji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4poolPhS_jji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff007624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R6, R0, c[0x0][0x170], RZ ; /* 0x00005c0000067a24 */
/* 0x000fe400078e02ff */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.SHL.U32 R8, R2, 0x4, RZ ; /* 0x0000000402087824 */
/* 0x000fca00078e00ff */
/*0070*/ ISETP.GE.U32.AND P0, PT, R8, R6, PT ; /* 0x000000060800720c */
/* 0x000fda0003f06070 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R7, R0.reuse, 0x2, RZ ; /* 0x0000000200077824 */
/* 0x040fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ IMAD.SHL.U32 R10, R0, 0x8, RZ ; /* 0x00000008000a7824 */
/* 0x000fe400078e00ff */
/*00c0*/ I2F.U32.RP R4, R7 ; /* 0x0000000700047306 */
/* 0x000e220000209000 */
/*00d0*/ IMAD.MOV R11, RZ, RZ, -R7 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0a07 */
/*00e0*/ ISETP.NE.U32.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f05070 */
/*00f0*/ LOP3.LUT R9, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff097212 */
/* 0x000fc800078e33ff */
/*0100*/ MUFU.RCP R4, R4 ; /* 0x0000000400047308 */
/* 0x001e240000001000 */
/*0110*/ IADD3 R2, R4, 0xffffffe, RZ ; /* 0x0ffffffe04027810 */
/* 0x001fcc0007ffe0ff */
/*0120*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*0130*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD R11, R11, R3, RZ ; /* 0x000000030b0b7224 */
/* 0x002fc800078e02ff */
/*0150*/ IMAD.HI.U32 R11, R3, R11, R2 ; /* 0x0000000b030b7227 */
/* 0x000fcc00078e0002 */
/*0160*/ IMAD.HI.U32 R2, R11, R8, RZ ; /* 0x000000080b027227 */
/* 0x000fc800078e00ff */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R2 ; /* 0x000000ffff047224 */
/* 0x001fc800078e0a02 */
/*0180*/ IMAD R4, R7, R4, R8 ; /* 0x0000000407047224 */
/* 0x000fca00078e0208 */
/*0190*/ ISETP.GE.U32.AND P1, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f26070 */
/*01a0*/ @P1 IMAD.IADD R4, R4, 0x1, -R7 ; /* 0x0000000104041824 */
/* 0x000fe200078e0a07 */
/*01b0*/ @P1 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102021810 */
/* 0x000fc80007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P2, PT, R4, R7, PT ; /* 0x000000070400720c */
/* 0x000fda0003f46070 */
/*01d0*/ @P2 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102022810 */
/* 0x000fc80007ffe0ff */
/*01e0*/ SEL R3, R9, R2, !P0 ; /* 0x0000000209037207 */
/* 0x000fca0004000000 */
/*01f0*/ IMAD.MOV R2, RZ, RZ, -R3 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a03 */
/*0200*/ IMAD R2, R7, R2, R8 ; /* 0x0000000207027224 */
/* 0x000fc800078e0208 */
/*0210*/ IMAD.SHL.U32 R2, R2, 0x2, RZ ; /* 0x0000000202027824 */
/* 0x000fc800078e00ff */
/*0220*/ IMAD R3, R10, R3, R2 ; /* 0x000000030a037224 */
/* 0x000fc800078e0202 */
/*0230*/ IMAD R12, R0, 0x4, R3 ; /* 0x00000004000c7824 */
/* 0x000fe200078e0203 */
/*0240*/ IADD3 R4, P1, R3, c[0x0][0x160], RZ ; /* 0x0000580003047a10 */
/* 0x000fc80007f3e0ff */
/*0250*/ LEA.HI.X.SX32 R5, R3, c[0x0][0x164], 0x1, P1 ; /* 0x0000590003057a11 */
/* 0x000fe400008f0eff */
/*0260*/ IADD3 R2, P1, R12, c[0x0][0x160], RZ ; /* 0x000058000c027a10 */
/* 0x000fc60007f3e0ff */
/*0270*/ LDG.E.U8 R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x0000a2000c1e1100 */
/*0280*/ LEA.HI.X.SX32 R3, R12, c[0x0][0x164], 0x1, P1 ; /* 0x000059000c037a11 */
/* 0x000fc600008f0eff */
/*0290*/ LDG.E.U8 R21, [R4.64+0x4] ; /* 0x0000040404157981 */
/* 0x0000a8000c1e1100 */
/*02a0*/ LDG.E.U8 R23, [R4.64+0x1] ; /* 0x0000010404177981 */
/* 0x0000e8000c1e1100 */
/*02b0*/ LDG.E.U8 R24, [R4.64+0x5] ; /* 0x0000050404187981 */
/* 0x0000e8000c1e1100 */
/*02c0*/ LDG.E.U8 R25, [R4.64+0x2] ; /* 0x0000020404197981 */
/* 0x000128000c1e1100 */
/*02d0*/ LDG.E.U8 R26, [R4.64+0x6] ; /* 0x00000604041a7981 */
/* 0x000128000c1e1100 */
/*02e0*/ LDG.E.U8 R18, [R4.64+0x3] ; /* 0x0000030404127981 */
/* 0x000168000c1e1100 */
/*02f0*/ LDG.E.U8 R27, [R4.64+0x7] ; /* 0x00000704041b7981 */
/* 0x000168000c1e1100 */
/*0300*/ LDG.E.U8 R22, [R2.64] ; /* 0x0000000402167981 */
/* 0x000368000c1e1100 */
/*0310*/ LDG.E.U8 R12, [R2.64+0x1] ; /* 0x00000104020c7981 */
/* 0x000368000c1e1100 */
/*0320*/ LDG.E.U8 R17, [R2.64+0x2] ; /* 0x0000020402117981 */
/* 0x000368000c1e1100 */
/*0330*/ LDG.E.U8 R16, [R2.64+0x3] ; /* 0x0000030402107981 */
/* 0x000368000c1e1100 */
/*0340*/ LDG.E.U8 R15, [R2.64+0x4] ; /* 0x00000404020f7981 */
/* 0x000368000c1e1100 */
/*0350*/ LDG.E.U8 R14, [R2.64+0x5] ; /* 0x00000504020e7981 */
/* 0x000368000c1e1100 */
/*0360*/ LDG.E.U8 R13, [R2.64+0x6] ; /* 0x00000604020d7981 */
/* 0x000368000c1e1100 */
/*0370*/ LDG.E.U8 R19, [R2.64+0x7] ; /* 0x0000070402137981 */
/* 0x000362000c1e1100 */
/*0380*/ IADD3 R4, P1, R8, c[0x0][0x168], RZ ; /* 0x00005a0008047a10 */
/* 0x001fc80007f3e0ff */
/*0390*/ LEA.HI.X.SX32 R5, R8, c[0x0][0x16c], 0x1, P1 ; /* 0x00005b0008057a11 */
/* 0x000fe200008f0eff */
/*03a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff037624 */
/* 0x002fc800078e00ff */
/*03b0*/ IMAD R8, R3, 0x4, R8 ; /* 0x0000000403087824 */
/* 0x000fca00078e0208 */
/*03c0*/ ISETP.GE.U32.AND P1, PT, R8, R6, PT ; /* 0x000000060800720c */
/* 0x000fe40003f26070 */
/*03d0*/ IMNMX.U32 R21, R20, R21, !PT ; /* 0x0000001514157217 */
/* 0x004fe40007800000 */
/*03e0*/ IMNMX.U32 R23, R23, R24, !PT ; /* 0x0000001817177217 */
/* 0x008fe40007800000 */
/*03f0*/ IMNMX.U32 R26, R25, R26, !PT ; /* 0x0000001a191a7217 */
/* 0x010fe40007800000 */
/*0400*/ IMNMX.U32 R27, R18, R27, !PT ; /* 0x0000001b121b7217 */
/* 0x020fe40007800000 */
/*0410*/ IMNMX.U32 R22, R22, R21, !PT ; /* 0x0000001516167217 */
/* 0x000fc40007800000 */
/*0420*/ IMNMX.U32 R23, R12, R23, !PT ; /* 0x000000170c177217 */
/* 0x000fe40007800000 */
/*0430*/ IMNMX.U32 R26, R17, R26, !PT ; /* 0x0000001a111a7217 */
/* 0x000fe40007800000 */
/*0440*/ IMNMX.U32 R16, R16, R27, !PT ; /* 0x0000001b10107217 */
/* 0x000fe40007800000 */
/*0450*/ IMNMX.U32 R15, R15, R22, !PT ; /* 0x000000160f0f7217 */
/* 0x000fe40007800000 */
/*0460*/ IMNMX.U32 R23, R14, R23, !PT ; /* 0x000000170e177217 */
/* 0x000fe40007800000 */
/*0470*/ IMNMX.U32 R13, R13, R26, !PT ; /* 0x0000001a0d0d7217 */
/* 0x000fc40007800000 */
/*0480*/ IMNMX.U32 R19, R19, R16, !PT ; /* 0x0000001013137217 */
/* 0x000fe20007800000 */
/*0490*/ STG.E.U8 [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0001e8000c101104 */
/*04a0*/ STG.E.U8 [R4.64+0x1], R23 ; /* 0x0000011704007986 */
/* 0x0001e8000c101104 */
/*04b0*/ STG.E.U8 [R4.64+0x2], R13 ; /* 0x0000020d04007986 */
/* 0x0001e8000c101104 */
/*04c0*/ STG.E.U8 [R4.64+0x3], R19 ; /* 0x0000031304007986 */
/* 0x0001e2000c101104 */
/*04d0*/ @!P1 BRA 0x160 ; /* 0xfffffc8000009947 */
/* 0x000fea000383ffff */
/*04e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*04f0*/ BRA 0x4f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4poolPhS_jji
.globl _Z4poolPhS_jji
.p2align 8
.type _Z4poolPhS_jji,@function
_Z4poolPhS_jji:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
s_mul_i32 s15, s15, s4
s_mov_b32 s4, exec_lo
v_add_lshl_u32 v0, s15, v0, 2
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_5
s_lshl_b32 s8, s3, 1
s_load_b32 s10, s[0:1], 0x18
v_cvt_f32_u32_e32 v1, s8
s_sub_i32 s4, 0, s8
s_lshl_b32 s9, s3, 3
s_lshl_b32 s3, s3, 2
s_mov_b32 s11, 0
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s4, v1
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s10, s10, 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v0, v1
s_mov_b64 s[0:1], 1
v_mul_lo_u32 v3, v2, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v3
v_subrev_nc_u32_e32 v5, s8, v3
v_cmp_le_u32_e32 vcc_lo, s8, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_add_nc_u32 v4, 1, v2
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s8, v3
v_add_nc_u32_e32 v4, 1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v4, vcc_lo
v_mul_lo_u32 v3, v2, s8
v_mul_lo_u32 v2, s9, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v0, v3
v_lshl_add_u32 v6, v3, 1, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v5, 5, v6
v_add_nc_u32_e32 v2, 4, v6
v_ashrrev_i32_e32 v3, 31, v6
v_add_nc_u32_e32 v29, s3, v6
v_add_co_u32 v7, vcc_lo, s4, v6
v_or_b32_e32 v4, 1, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v3, vcc_lo
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v14, 31, v29
v_add_co_u32 v9, vcc_lo, s4, v2
v_ashrrev_i32_e32 v16, 31, v4
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v13, vcc_lo, s4, v29
v_or_b32_e32 v11, 2, v6
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
v_ashrrev_i32_e32 v18, 31, v5
v_add_co_u32 v15, vcc_lo, s4, v4
v_add_nc_u32_e32 v19, 4, v29
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v16, vcc_lo
v_ashrrev_i32_e32 v20, 31, v11
v_add_co_u32 v17, vcc_lo, s4, v5
v_or_b32_e32 v21, 1, v29
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v18, vcc_lo
v_ashrrev_i32_e32 v22, 31, v19
v_add_co_u32 v2, vcc_lo, s4, v11
v_add_nc_u32_e32 v23, 5, v29
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v20, vcc_lo
v_ashrrev_i32_e32 v4, 31, v21
v_add_co_u32 v19, vcc_lo, s4, v19
v_add_nc_u32_e32 v12, 6, v6
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v22, vcc_lo
v_ashrrev_i32_e32 v5, 31, v23
v_add_co_u32 v21, vcc_lo, s4, v21
v_add_co_ci_u32_e32 v22, vcc_lo, s5, v4, vcc_lo
v_ashrrev_i32_e32 v25, 31, v12
v_add_co_u32 v23, vcc_lo, s4, v23
v_add_co_ci_u32_e32 v24, vcc_lo, s5, v5, vcc_lo
v_or_b32_e32 v11, 2, v29
v_add_co_u32 v4, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v25, vcc_lo
v_add_nc_u32_e32 v25, 6, v29
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v12, 31, v11
v_or_b32_e32 v27, 3, v6
v_add_co_u32 v11, vcc_lo, s4, v11
v_ashrrev_i32_e32 v26, 31, v25
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v12, vcc_lo
v_ashrrev_i32_e32 v28, 31, v27
v_add_co_u32 v25, vcc_lo, s4, v25
v_add_nc_u32_e32 v30, 7, v6
v_add_co_ci_u32_e32 v26, vcc_lo, s5, v26, vcc_lo
v_add_co_u32 v27, vcc_lo, s4, v27
v_add_co_ci_u32_e32 v28, vcc_lo, s5, v28, vcc_lo
s_clause 0x4
global_load_u8 v2, v[2:3], off
global_load_u8 v3, v[4:5], off
global_load_u8 v4, v[11:12], off
global_load_u8 v5, v[25:26], off
global_load_u8 v6, v[27:28], off
v_ashrrev_i32_e32 v11, 31, v30
v_or_b32_e32 v12, 3, v29
v_add_nc_u32_e32 v29, 7, v29
v_add_co_u32 v25, vcc_lo, s4, v30
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v26, vcc_lo, s5, v11, vcc_lo
v_ashrrev_i32_e32 v11, 31, v12
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v30, 31, v29
v_add_co_u32 v27, vcc_lo, s4, v12
v_add_co_ci_u32_e32 v28, vcc_lo, s5, v11, vcc_lo
v_add_co_u32 v29, vcc_lo, s4, v29
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v30, vcc_lo, s5, v30, vcc_lo
s_clause 0xa
global_load_u8 v11, v[7:8], off
global_load_u8 v12, v[9:10], off
global_load_u8 v13, v[13:14], off
global_load_u8 v14, v[19:20], off
global_load_u8 v15, v[15:16], off
global_load_u8 v16, v[17:18], off
global_load_u8 v17, v[21:22], off
global_load_u8 v18, v[23:24], off
global_load_u8 v19, v[25:26], off
global_load_u8 v20, v[27:28], off
global_load_u8 v21, v[29:30], off
s_waitcnt vmcnt(15)
v_mov_b32_e32 v8, v2
s_waitcnt vmcnt(10)
v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v10, v11
s_waitcnt vmcnt(6)
v_mov_b32_e32 v9, v15
.p2align 6
.LBB0_3:
s_cmp_eq_u32 s0, 1
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 2
s_waitcnt vmcnt(2)
v_dual_cndmask_b32 v22, v11, v12 :: v_dual_cndmask_b32 v25, v6, v19
v_dual_cndmask_b32 v23, v15, v16 :: v_dual_cndmask_b32 v24, v2, v3
s_cselect_b32 vcc_lo, -1, 0
s_cmp_eq_u32 s0, 3
s_waitcnt vmcnt(1)
v_dual_cndmask_b32 v22, v22, v13 :: v_dual_cndmask_b32 v25, v25, v20
v_dual_cndmask_b32 v23, v23, v17 :: v_dual_cndmask_b32 v24, v24, v4
s_cselect_b32 vcc_lo, -1, 0
s_add_u32 s0, s0, 1
s_waitcnt vmcnt(0)
v_dual_cndmask_b32 v22, v22, v14 :: v_dual_cndmask_b32 v25, v25, v21
v_dual_cndmask_b32 v23, v23, v18 :: v_dual_cndmask_b32 v24, v24, v5
s_addc_u32 s1, s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_max_u32_e32 v10, v22, v10
v_max_u32_e32 v7, v25, v7
s_delay_alu instid0(VALU_DEP_3)
v_max_u32_e32 v9, v23, v9
v_max_u32_e32 v8, v24, v8
s_cmp_eq_u32 s0, 4
s_cbranch_scc0 .LBB0_3
v_or_b32_e32 v4, 1, v0
v_ashrrev_i32_e32 v3, 31, v0
v_or_b32_e32 v6, 2, v0
v_add_co_u32 v2, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v5, 31, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v4
v_ashrrev_i32_e32 v12, 31, v6
v_or_b32_e32 v13, 3, v0
v_add_nc_u32_e32 v0, s10, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
v_ashrrev_i32_e32 v6, 31, v13
v_cmp_le_u32_e32 vcc_lo, s2, v0
v_add_co_u32 v13, s0, s6, v13
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v14, s0, s7, v6, s0
s_or_b32 s11, vcc_lo, s11
s_clause 0x3
global_store_b8 v[2:3], v10, off
global_store_b8 v[4:5], v9, off
global_store_b8 v[11:12], v8, off
global_store_b8 v[13:14], v7, off
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4poolPhS_jji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 31
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4poolPhS_jji, .Lfunc_end0-_Z4poolPhS_jji
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4poolPhS_jji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4poolPhS_jji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 31
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001bc062_00000000-6_pool.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z4poolPhS_jjiPhS_jji
.type _Z28__device_stub__Z4poolPhS_jjiPhS_jji, @function
_Z28__device_stub__Z4poolPhS_jjiPhS_jji:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4poolPhS_jji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z4poolPhS_jjiPhS_jji, .-_Z28__device_stub__Z4poolPhS_jjiPhS_jji
.globl _Z4poolPhS_jji
.type _Z4poolPhS_jji, @function
_Z4poolPhS_jji:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4poolPhS_jjiPhS_jji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z4poolPhS_jji, .-_Z4poolPhS_jji
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4poolPhS_jji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4poolPhS_jji(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "pool.hip"
.globl _Z19__device_stub__poolPhS_jji # -- Begin function _Z19__device_stub__poolPhS_jji
.p2align 4, 0x90
.type _Z19__device_stub__poolPhS_jji,@function
_Z19__device_stub__poolPhS_jji: # @_Z19__device_stub__poolPhS_jji
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4poolPhS_jji, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z19__device_stub__poolPhS_jji, .Lfunc_end0-_Z19__device_stub__poolPhS_jji
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4poolPhS_jji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4poolPhS_jji,@object # @_Z4poolPhS_jji
.section .rodata,"a",@progbits
.globl _Z4poolPhS_jji
.p2align 3, 0x0
_Z4poolPhS_jji:
.quad _Z19__device_stub__poolPhS_jji
.size _Z4poolPhS_jji, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z4poolPhS_jji"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__poolPhS_jji
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4poolPhS_jji
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <iostream>
#include <cuda.h>
#include <stdio.h>
using std::cout;
using std::endl;
__global__ void my_kernel(float mypi)
{
printf("Printf hello from the kernel!!\n");
printf("I'm in thread %i \n", threadIdx.x);
printf("Someone sent me %f \n", mypi);
}
int main(int argc, char *argv[])
{
cout << "Hello world!! I will call a CUDA kernel now!!" << endl;
my_kernel<<<1,1,0>>>(3.1415f);
cudaDeviceSynchronize();
return 0;
}
|
code for sm_80
Function : _Z9my_kernelf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ MOV R17, 0x0 ; /* 0x0000000000117802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R8, c[0x4][R17] ; /* 0x0100000011087b82 */
/* 0x0000620000000a00 */
/*0060*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0070*/ IADD3 R16, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001107a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R2, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff027624 */
/* 0x000fe400000e06ff */
/*0090*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fcc0000000000 */
/*00a0*/ MOV R3, 0x110 ; /* 0x0000011000037802 */
/* 0x000fe40000000f00 */
/*00b0*/ MOV R20, 0x90 ; /* 0x0000009000147802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00e0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*00f0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0100*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x003fea0003c00000 */
/*0110*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0120*/ LDC.64 R8, c[0x4][R17] ; /* 0x0100000011087b82 */
/* 0x0002a20000000a00 */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*0160*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0170*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0013e80000100800 */
/*0180*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x000fe40000000000 */
/*0190*/ MOV R3, 0x200 ; /* 0x0000020000037802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R20, 0x180 ; /* 0x0000018000147802 */
/* 0x000fc40000000f00 */
/*01b0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*01d0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*01e0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*01f0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*0200*/ F2F.F64.F32 R10, c[0x0][0x160] ; /* 0x00005800000a7b10 */
/* 0x000e220000201800 */
/*0210*/ LDC.64 R8, c[0x4][R17] ; /* 0x0100000011087b82 */
/* 0x0002a20000000a00 */
/*0220*/ IMAD.MOV.U32 R6, RZ, RZ, R16 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0010 */
/*0230*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0002 */
/*0240*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe400078e00ff */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fe200078e00ff */
/*0260*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0013e80000100a00 */
/*0270*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x000fe40000000000 */
/*0280*/ MOV R11, 0x2f0 ; /* 0x000002f0000b7802 */
/* 0x002fe40000000f00 */
/*0290*/ MOV R20, 0x270 ; /* 0x0000027000147802 */
/* 0x000fc40000000f00 */
/*02a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*02b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*02c0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*02d0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*02e0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x004fea0003c00000 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <iostream>
#include <cuda.h>
#include <stdio.h>
using std::cout;
using std::endl;
__global__ void my_kernel(float mypi)
{
printf("Printf hello from the kernel!!\n");
printf("I'm in thread %i \n", threadIdx.x);
printf("Someone sent me %f \n", mypi);
}
int main(int argc, char *argv[])
{
cout << "Hello world!! I will call a CUDA kernel now!!" << endl;
my_kernel<<<1,1,0>>>(3.1415f);
cudaDeviceSynchronize();
return 0;
}
|
.file "tmpxft_0011cafb_00000000-6_hello3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9my_kernelff
.type _Z27__device_stub__Z9my_kernelff, @function
_Z27__device_stub__Z9my_kernelff:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9my_kernelf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z9my_kernelff, .-_Z27__device_stub__Z9my_kernelff
.globl _Z9my_kernelf
.type _Z9my_kernelf, @function
_Z9my_kernelf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9my_kernelff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9my_kernelf, .-_Z9my_kernelf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Hello world!! I will call a CUDA kernel now!!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss .LC1(%rip), %xmm0
call _Z27__device_stub__Z9my_kernelff
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z9my_kernelf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9my_kernelf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1078529622
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <iostream>
#include <cuda.h>
#include <stdio.h>
using std::cout;
using std::endl;
__global__ void my_kernel(float mypi)
{
printf("Printf hello from the kernel!!\n");
printf("I'm in thread %i \n", threadIdx.x);
printf("Someone sent me %f \n", mypi);
}
int main(int argc, char *argv[])
{
cout << "Hello world!! I will call a CUDA kernel now!!" << endl;
my_kernel<<<1,1,0>>>(3.1415f);
cudaDeviceSynchronize();
return 0;
}
|
#include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
using std::cout;
using std::endl;
__global__ void my_kernel(float mypi)
{
printf("Printf hello from the kernel!!\n");
printf("I'm in thread %i \n", threadIdx.x);
printf("Someone sent me %f \n", mypi);
}
int main(int argc, char *argv[])
{
cout << "Hello world!! I will call a CUDA kernel now!!" << endl;
my_kernel<<<1,1,0>>>(3.1415f);
hipDeviceSynchronize();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <iostream>
#include <hip/hip_runtime.h>
#include <stdio.h>
using std::cout;
using std::endl;
__global__ void my_kernel(float mypi)
{
printf("Printf hello from the kernel!!\n");
printf("I'm in thread %i \n", threadIdx.x);
printf("Someone sent me %f \n", mypi);
}
int main(int argc, char *argv[])
{
cout << "Hello world!! I will call a CUDA kernel now!!" << endl;
my_kernel<<<1,1,0>>>(3.1415f);
hipDeviceSynchronize();
return 0;
}
|
.text
.file "hello3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__my_kernelf # -- Begin function _Z24__device_stub__my_kernelf
.p2align 4, 0x90
.type _Z24__device_stub__my_kernelf,@function
_Z24__device_stub__my_kernelf: # @_Z24__device_stub__my_kernelf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9my_kernelf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__my_kernelf, .Lfunc_end0-_Z24__device_stub__my_kernelf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movl $1078529622, 12(%rsp) # imm = 0x40490E56
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9my_kernelf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9my_kernelf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9my_kernelf,@object # @_Z9my_kernelf
.section .rodata,"a",@progbits
.globl _Z9my_kernelf
.p2align 3, 0x0
_Z9my_kernelf:
.quad _Z24__device_stub__my_kernelf
.size _Z9my_kernelf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello world!! I will call a CUDA kernel now!!"
.size .L.str, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9my_kernelf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__my_kernelf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9my_kernelf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0011cafb_00000000-6_hello3.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9my_kernelff
.type _Z27__device_stub__Z9my_kernelff, @function
_Z27__device_stub__Z9my_kernelff:
.LFB3694:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movss %xmm0, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9my_kernelf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z27__device_stub__Z9my_kernelff, .-_Z27__device_stub__Z9my_kernelff
.globl _Z9my_kernelf
.type _Z9my_kernelf, @function
_Z9my_kernelf:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9my_kernelff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z9my_kernelf, .-_Z9my_kernelf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Hello world!! I will call a CUDA kernel now!!"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movss .LC1(%rip), %xmm0
call _Z27__device_stub__Z9my_kernelff
jmp .L12
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "_Z9my_kernelf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z9my_kernelf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 1078529622
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "hello3.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__my_kernelf # -- Begin function _Z24__device_stub__my_kernelf
.p2align 4, 0x90
.type _Z24__device_stub__my_kernelf,@function
_Z24__device_stub__my_kernelf: # @_Z24__device_stub__my_kernelf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movss %xmm0, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9my_kernelf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__my_kernelf, .Lfunc_end0-_Z24__device_stub__my_kernelf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_7
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_3
# %bb.2:
movzbl 67(%rbx), %eax
jmp .LBB1_4
.LBB1_3:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movl $1078529622, 12(%rsp) # imm = 0x40490E56
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9my_kernelf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB1_7:
.cfi_def_cfa_offset 96
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9my_kernelf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9my_kernelf,@object # @_Z9my_kernelf
.section .rodata,"a",@progbits
.globl _Z9my_kernelf
.p2align 3, 0x0
_Z9my_kernelf:
.quad _Z24__device_stub__my_kernelf
.size _Z9my_kernelf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Hello world!! I will call a CUDA kernel now!!"
.size .L.str, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9my_kernelf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__my_kernelf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9my_kernelf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <math.h>
#include <stdio.h>
#include <cuda_runtime.h>
// Array access macros
#define f(i,j) A[(i) + (j)*(m)]
#define B(i,j) B[(i) + (j)*(m)]
#define Z(x,y) Z[(x) + (y)*(m)]
#define f_(x,y) f_[(x) + (y)*(m)]
__global__ void Zcalc(float const * const A, float *Z,float const * const H,int patchSize,float patchSigma,float fltSigma, int m, int n) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
float FNij=0.0;
float temp=0.0;
patchSize=(patchSize-1)/2;
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
Z(x+patchSize,y+patchSize)=Z(x+patchSize,y+patchSize)+expf(-(FNij/(fltSigma)));
FNij=0.0;
counter=0;
}
}
}
}
__global__ void fCalc(float const * const A,float const * const Z,float const * const H, float *f_,int patchSize,float patchSigma,float fltSigma, int m, int n){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
patchSize=(patchSize-1)/2;
float FNij=0.0;
float temp=0.0;
float Z_local=Z(x+patchSize,y+patchSize);
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
f_(x+patchSize,y+patchSize)=f_(x+patchSize,y+patchSize)+((1/Z_local)*expf(-(FNij/(fltSigma))))*f(i,j);
FNij=0.0;
counter=0;
}
}
}
}
|
.file "tmpxft_00139923_00000000-6_nlmGlobal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii
.type _Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii, @function
_Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii:
.LFB2081:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5ZcalcPKfPfS0_iffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii, .-_Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii
.globl _Z5ZcalcPKfPfS0_iffii
.type _Z5ZcalcPKfPfS0_iffii, @function
_Z5ZcalcPKfPfS0_iffii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z5ZcalcPKfPfS0_iffii, .-_Z5ZcalcPKfPfS0_iffii
.globl _Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii
.type _Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii, @function
_Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5fCalcPKfS0_S0_Pfiffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii, .-_Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii
.globl _Z5fCalcPKfS0_S0_Pfiffii
.type _Z5fCalcPKfS0_S0_Pfiffii, @function
_Z5fCalcPKfS0_S0_Pfiffii:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5fCalcPKfS0_S0_Pfiffii, .-_Z5fCalcPKfS0_S0_Pfiffii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5fCalcPKfS0_S0_Pfiffii"
.LC1:
.string "_Z5ZcalcPKfPfS0_iffii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5fCalcPKfS0_S0_Pfiffii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5ZcalcPKfPfS0_iffii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <math.h>
#include <stdio.h>
#include <cuda_runtime.h>
// Array access macros
#define f(i,j) A[(i) + (j)*(m)]
#define B(i,j) B[(i) + (j)*(m)]
#define Z(x,y) Z[(x) + (y)*(m)]
#define f_(x,y) f_[(x) + (y)*(m)]
__global__ void Zcalc(float const * const A, float *Z,float const * const H,int patchSize,float patchSigma,float fltSigma, int m, int n) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
float FNij=0.0;
float temp=0.0;
patchSize=(patchSize-1)/2;
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
Z(x+patchSize,y+patchSize)=Z(x+patchSize,y+patchSize)+expf(-(FNij/(fltSigma)));
FNij=0.0;
counter=0;
}
}
}
}
__global__ void fCalc(float const * const A,float const * const Z,float const * const H, float *f_,int patchSize,float patchSigma,float fltSigma, int m, int n){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
patchSize=(patchSize-1)/2;
float FNij=0.0;
float temp=0.0;
float Z_local=Z(x+patchSize,y+patchSize);
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
f_(x+patchSize,y+patchSize)=f_(x+patchSize,y+patchSize)+((1/Z_local)*expf(-(FNij/(fltSigma))))*f(i,j);
FNij=0.0;
counter=0;
}
}
}
}
|
#include <math.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
// Array access macros
#define f(i,j) A[(i) + (j)*(m)]
#define B(i,j) B[(i) + (j)*(m)]
#define Z(x,y) Z[(x) + (y)*(m)]
#define f_(x,y) f_[(x) + (y)*(m)]
__global__ void Zcalc(float const * const A, float *Z,float const * const H,int patchSize,float patchSigma,float fltSigma, int m, int n) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
float FNij=0.0;
float temp=0.0;
patchSize=(patchSize-1)/2;
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
Z(x+patchSize,y+patchSize)=Z(x+patchSize,y+patchSize)+expf(-(FNij/(fltSigma)));
FNij=0.0;
counter=0;
}
}
}
}
__global__ void fCalc(float const * const A,float const * const Z,float const * const H, float *f_,int patchSize,float patchSigma,float fltSigma, int m, int n){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
patchSize=(patchSize-1)/2;
float FNij=0.0;
float temp=0.0;
float Z_local=Z(x+patchSize,y+patchSize);
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
f_(x+patchSize,y+patchSize)=f_(x+patchSize,y+patchSize)+((1/Z_local)*expf(-(FNij/(fltSigma))))*f(i,j);
FNij=0.0;
counter=0;
}
}
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <math.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
// Array access macros
#define f(i,j) A[(i) + (j)*(m)]
#define B(i,j) B[(i) + (j)*(m)]
#define Z(x,y) Z[(x) + (y)*(m)]
#define f_(x,y) f_[(x) + (y)*(m)]
__global__ void Zcalc(float const * const A, float *Z,float const * const H,int patchSize,float patchSigma,float fltSigma, int m, int n) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
float FNij=0.0;
float temp=0.0;
patchSize=(patchSize-1)/2;
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
Z(x+patchSize,y+patchSize)=Z(x+patchSize,y+patchSize)+expf(-(FNij/(fltSigma)));
FNij=0.0;
counter=0;
}
}
}
}
__global__ void fCalc(float const * const A,float const * const Z,float const * const H, float *f_,int patchSize,float patchSigma,float fltSigma, int m, int n){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
patchSize=(patchSize-1)/2;
float FNij=0.0;
float temp=0.0;
float Z_local=Z(x+patchSize,y+patchSize);
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
f_(x+patchSize,y+patchSize)=f_(x+patchSize,y+patchSize)+((1/Z_local)*expf(-(FNij/(fltSigma))))*f(i,j);
FNij=0.0;
counter=0;
}
}
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5ZcalcPKfPfS0_iffii
.globl _Z5ZcalcPKfPfS0_iffii
.p2align 8
.type _Z5ZcalcPKfPfS0_iffii,@function
_Z5ZcalcPKfPfS0_iffii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s16, s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x24
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshl_b32 s4, s16, 1
s_lshr_b32 s2, s2, 16
s_add_i32 s4, s4, -1
s_mul_i32 s17, s14, s3
s_lshr_b32 s3, s4, 31
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
s_add_i32 s4, s4, s3
v_add_nc_u32_e32 v1, s17, v2
s_ashr_i32 s2, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_sub_i32 s3, s8, s2
s_sub_i32 s2, s9, s2
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_13
s_add_i32 s2, s16, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s3, s2, 31
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s10, s2, 1
s_sub_i32 s11, s8, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s10, s11
s_cbranch_scc1 .LBB0_13
v_add_nc_u32_e32 v3, s10, v0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s12, s[0:1], 0x20
s_sub_i32 s9, s9, s10
v_mul_lo_u32 v5, s8, v0
v_mul_lo_u32 v3, v3, s8
s_cmp_lt_i32 s10, s9
s_cselect_b32 s13, -1, 0
s_sub_i32 s14, 0, s10
s_cmp_gt_i32 s16, -1
s_cselect_b32 s15, -1, 0
s_delay_alu instid0(VALU_DEP_1)
v_add3_u32 v3, v1, s10, v3
s_abs_i32 s16, s10
v_add3_u32 v2, v2, v5, s17
s_add_i32 s0, s10, s16
s_mov_b32 s17, s10
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[3:4]
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_mov_b32 s6, 0
s_add_i32 s7, s0, 1
s_branch .LBB0_4
.LBB0_3:
s_add_i32 s17, s17, 1
s_add_i32 s6, s6, 1
s_cmp_lt_i32 s17, s11
s_cbranch_scc0 .LBB0_13
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB0_3
global_load_b32 v4, v[0:1], off
s_mov_b32 s18, s6
s_mov_b32 s19, s10
s_branch .LBB0_7
.LBB0_6:
s_set_inst_prefetch_distance 0x2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_div_scale_f32 v6, null, s12, s12, -v5
v_div_scale_f32 v9, vcc_lo, -v5, s12, -v5
s_add_i32 s19, s19, 1
v_rcp_f32_e32 v7, v6
s_add_i32 s18, s18, s8
s_cmp_lt_i32 s19, s9
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v6, v7, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v7
v_mul_f32_e32 v8, v9, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, -v6, v8, v9
v_fmac_f32_e32 v8, v10, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v6, -v6, v8, v9
v_div_fmas_f32 v6, v6, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v5, v6, s12, -v5
v_mul_f32_e32 v6, 0x3fb8aa3b, v5
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v7, v5, 0x3fb8aa3b, -v6
v_rndne_f32_e32 v8, v6
v_dual_fmac_f32 v7, 0x32a5705f, v5 :: v_dual_sub_f32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v6, v7
v_cvt_i32_f32_e32 v7, v8
v_exp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
v_cndmask_b32_e32 v5, 0x7f800000, v6, vcc_lo
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v4, v5, v4
global_store_b32 v[0:1], v4, off
s_cbranch_scc0 .LBB0_3
.LBB0_7:
v_mov_b32_e32 v5, 0
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_6
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v6, v2
s_mov_b32 s0, 0
s_mov_b32 s20, s18
s_mov_b32 s21, s14
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_9:
s_mov_b32 s22, 0
s_mov_b32 s23, s7
.p2align 6
.LBB0_10:
v_add_nc_u32_e32 v7, s22, v6
s_add_i32 s24, s20, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s25, s24, 31
s_lshl_b64 s[24:25], s[24:25], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
s_add_u32 s24, s4, s24
s_addc_u32 s25, s5, s25
s_ashr_i32 s1, s0, 31
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_lshl_b64 s[26:27], s[0:1], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
s_clause 0x1
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v3, s[24:25]
s_add_u32 s24, s2, s26
s_addc_u32 s25, s3, s27
s_add_i32 s23, s23, -1
global_load_b32 v9, v3, s[24:25]
s_add_i32 s0, s0, 1
s_add_i32 s22, s22, s8
s_cmp_lg_u32 s23, 0
s_waitcnt vmcnt(1)
v_sub_f32_e32 v7, v7, v8
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v7, v9
v_fmac_f32_e32 v5, v7, v7
s_cbranch_scc1 .LBB0_10
v_add_nc_u32_e32 v6, 1, v6
s_add_i32 s1, s21, 1
s_add_i32 s20, s20, 1
s_cmp_lg_u32 s21, s16
s_cbranch_scc0 .LBB0_6
s_mov_b32 s21, s1
s_branch .LBB0_9
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5ZcalcPKfPfS0_iffii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5ZcalcPKfPfS0_iffii, .Lfunc_end0-_Z5ZcalcPKfPfS0_iffii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5fCalcPKfS0_S0_Pfiffii
.globl _Z5fCalcPKfS0_S0_Pfiffii
.p2align 8
.type _Z5fCalcPKfS0_S0_Pfiffii,@function
_Z5fCalcPKfS0_S0_Pfiffii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s16, s[0:1], 0x20
s_load_b64 s[12:13], s[0:1], 0x2c
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshl_b32 s4, s16, 1
s_lshr_b32 s2, s2, 16
s_add_i32 s4, s4, -1
s_mul_i32 s17, s14, s3
s_lshr_b32 s3, s4, 31
v_mad_u64_u32 v[0:1], null, s15, s2, v[3:4]
s_add_i32 s4, s4, s3
v_add_nc_u32_e32 v1, s17, v2
s_ashr_i32 s2, s4, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_sub_i32 s3, s12, s2
s_sub_i32 s2, s13, s2
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s2, v0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_13
s_add_i32 s2, s16, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshr_b32 s3, s2, 31
s_add_i32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 1
s_sub_i32 s3, s12, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s2, s3
s_cbranch_scc1 .LBB1_13
v_add_nc_u32_e32 v3, s2, v0
s_load_b256 s[4:11], s[0:1], 0x0
v_mul_lo_u32 v0, s12, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s12
v_add3_u32 v2, v2, v0, s17
s_mov_b32 s17, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v3, v1, s2, v3
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
s_load_b32 s7, s[0:1], 0x28
s_sub_i32 s6, s13, s2
s_cmp_lt_i32 s2, s6
global_load_b32 v5, v[5:6], off
s_cselect_b32 s13, -1, 0
s_sub_i32 s14, 0, s2
s_cmp_gt_i32 s16, -1
s_cselect_b32 s15, -1, 0
s_abs_i32 s16, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
s_add_i32 s0, s2, s16
s_waitcnt vmcnt(0)
v_div_scale_f32 v1, null, v5, v5, 1.0
v_div_scale_f32 v8, vcc_lo, 1.0, v5, 1.0
v_rcp_f32_e32 v6, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v7, -v1, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v6
v_mul_f32_e32 v7, v8, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v1, v7, v8
v_fmac_f32_e32 v7, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v1, -v1, v7, v8
v_div_fmas_f32 v6, v1, v6, v7
v_add_co_u32 v0, vcc_lo, s10, v3
v_add_co_ci_u32_e32 v1, vcc_lo, s11, v4, vcc_lo
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_4)
v_div_fixup_f32 v3, v6, v5, 1.0
s_mov_b32 s10, 0
s_add_i32 s11, s0, 1
s_branch .LBB1_4
.LBB1_3:
s_add_i32 s17, s17, 1
s_add_i32 s10, s10, 1
s_cmp_lt_i32 s17, s3
s_cbranch_scc0 .LBB1_13
.LBB1_4:
s_and_not1_b32 vcc_lo, exec_lo, s13
s_cbranch_vccnz .LBB1_3
global_load_b32 v5, v[0:1], off
s_mov_b32 s18, s10
s_mov_b32 s19, s2
s_branch .LBB1_7
.LBB1_6:
s_set_inst_prefetch_distance 0x2
s_mul_i32 s0, s19, s12
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v8, null, s7, s7, -v6
s_add_i32 s0, s0, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s1, s0, 31
v_rcp_f32_e32 v9, v8
s_lshl_b64 s[0:1], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
s_add_i32 s19, s19, 1
global_load_b32 v7, v4, s[0:1]
s_add_i32 s18, s18, s12
s_cmp_lt_i32 s19, s6
v_fma_f32 v10, -v8, v9, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v9, v10, v9
v_div_scale_f32 v10, vcc_lo, -v6, s7, -v6
v_mul_f32_e32 v11, v10, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, -v8, v11, v10
v_fmac_f32_e32 v11, v12, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v8, v11, v10
v_div_fmas_f32 v8, v8, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v6, v8, s7, -v6
v_mul_f32_e32 v8, 0x3fb8aa3b, v6
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v9, v6, 0x3fb8aa3b, -v8
v_rndne_f32_e32 v10, v8
v_fmac_f32_e32 v9, 0x32a5705f, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v10
v_add_f32_e32 v8, v8, v9
v_cvt_i32_f32_e32 v9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_exp_f32_e32 v8, v8
s_waitcnt_depctr 0xfff
v_ldexp_f32 v8, v8, v9
v_cndmask_b32_e32 v8, 0, v8, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v6, 0x7f800000, v8, vcc_lo
v_mul_f32_e32 v6, v3, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v5, v6, v7
global_store_b32 v[0:1], v5, off
s_cbranch_scc0 .LBB1_3
.LBB1_7:
v_mov_b32_e32 v6, 0
s_and_not1_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB1_6
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, v2
s_mov_b32 s0, 0
s_mov_b32 s20, s18
s_mov_b32 s21, s14
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB1_9:
s_mov_b32 s22, 0
s_mov_b32 s23, s11
.p2align 6
.LBB1_10:
v_add_nc_u32_e32 v8, s22, v7
s_add_i32 s24, s20, s22
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s25, s24, 31
s_lshl_b64 s[24:25], s[24:25], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
s_add_u32 s24, s4, s24
s_addc_u32 s25, s5, s25
s_ashr_i32 s1, s0, 31
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_lshl_b64 s[26:27], s[0:1], 2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
s_clause 0x1
global_load_b32 v8, v[8:9], off
global_load_b32 v9, v4, s[24:25]
s_add_u32 s24, s8, s26
s_addc_u32 s25, s9, s27
s_add_i32 s23, s23, -1
global_load_b32 v10, v4, s[24:25]
s_add_i32 s0, s0, 1
s_add_i32 s22, s22, s12
s_cmp_lg_u32 s23, 0
s_waitcnt vmcnt(1)
v_sub_f32_e32 v8, v8, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v8, v10
v_fmac_f32_e32 v6, v8, v8
s_cbranch_scc1 .LBB1_10
v_add_nc_u32_e32 v7, 1, v7
s_add_i32 s1, s21, 1
s_add_i32 s20, s20, 1
s_cmp_lg_u32 s21, s16
s_cbranch_scc0 .LBB1_6
s_mov_b32 s21, s1
s_branch .LBB1_9
.LBB1_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5fCalcPKfS0_S0_Pfiffii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5fCalcPKfS0_S0_Pfiffii, .Lfunc_end1-_Z5fCalcPKfS0_S0_Pfiffii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5ZcalcPKfPfS0_iffii
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z5ZcalcPKfPfS0_iffii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5fCalcPKfS0_S0_Pfiffii
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z5fCalcPKfS0_S0_Pfiffii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <math.h>
#include <stdio.h>
#include <hip/hip_runtime.h>
// Array access macros
#define f(i,j) A[(i) + (j)*(m)]
#define B(i,j) B[(i) + (j)*(m)]
#define Z(x,y) Z[(x) + (y)*(m)]
#define f_(x,y) f_[(x) + (y)*(m)]
__global__ void Zcalc(float const * const A, float *Z,float const * const H,int patchSize,float patchSigma,float fltSigma, int m, int n) {
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
float FNij=0.0;
float temp=0.0;
patchSize=(patchSize-1)/2;
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
Z(x+patchSize,y+patchSize)=Z(x+patchSize,y+patchSize)+expf(-(FNij/(fltSigma)));
FNij=0.0;
counter=0;
}
}
}
}
__global__ void fCalc(float const * const A,float const * const Z,float const * const H, float *f_,int patchSize,float patchSigma,float fltSigma, int m, int n){
int x = blockIdx.x * blockDim.x + threadIdx.x;
int y = blockIdx.y * blockDim.y + threadIdx.y;
if(x<m-(2*patchSize-1)/2 && y<n-(2*patchSize-1)/2){
int i,j,k,l,counter=0;
patchSize=(patchSize-1)/2;
float FNij=0.0;
float temp=0.0;
float Z_local=Z(x+patchSize,y+patchSize);
for(i=patchSize;i<m-patchSize;i++){
for(j=patchSize;j<n-patchSize;j++){
for(k=-patchSize;k<=patchSize;k++){
for(l=-patchSize;l<=patchSize;l++){
temp=(f(x+patchSize+k,y+patchSize+l)-f(i+k,j+l))*H[counter];
temp=temp*temp;
FNij=FNij+(temp);
counter++;
}
}
f_(x+patchSize,y+patchSize)=f_(x+patchSize,y+patchSize)+((1/Z_local)*expf(-(FNij/(fltSigma))))*f(i,j);
FNij=0.0;
counter=0;
}
}
}
}
|
.text
.file "nlmGlobal.hip"
.globl _Z20__device_stub__ZcalcPKfPfS0_iffii # -- Begin function _Z20__device_stub__ZcalcPKfPfS0_iffii
.p2align 4, 0x90
.type _Z20__device_stub__ZcalcPKfPfS0_iffii,@function
_Z20__device_stub__ZcalcPKfPfS0_iffii: # @_Z20__device_stub__ZcalcPKfPfS0_iffii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5ZcalcPKfPfS0_iffii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z20__device_stub__ZcalcPKfPfS0_iffii, .Lfunc_end0-_Z20__device_stub__ZcalcPKfPfS0_iffii
.cfi_endproc
# -- End function
.globl _Z20__device_stub__fCalcPKfS0_S0_Pfiffii # -- Begin function _Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.p2align 4, 0x90
.type _Z20__device_stub__fCalcPKfS0_S0_Pfiffii,@function
_Z20__device_stub__fCalcPKfS0_S0_Pfiffii: # @_Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movl %r9d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5fCalcPKfS0_S0_Pfiffii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z20__device_stub__fCalcPKfS0_S0_Pfiffii, .Lfunc_end1-_Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5ZcalcPKfPfS0_iffii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5fCalcPKfS0_S0_Pfiffii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5ZcalcPKfPfS0_iffii,@object # @_Z5ZcalcPKfPfS0_iffii
.section .rodata,"a",@progbits
.globl _Z5ZcalcPKfPfS0_iffii
.p2align 3, 0x0
_Z5ZcalcPKfPfS0_iffii:
.quad _Z20__device_stub__ZcalcPKfPfS0_iffii
.size _Z5ZcalcPKfPfS0_iffii, 8
.type _Z5fCalcPKfS0_S0_Pfiffii,@object # @_Z5fCalcPKfS0_S0_Pfiffii
.globl _Z5fCalcPKfS0_S0_Pfiffii
.p2align 3, 0x0
_Z5fCalcPKfS0_S0_Pfiffii:
.quad _Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.size _Z5fCalcPKfS0_S0_Pfiffii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5ZcalcPKfPfS0_iffii"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5fCalcPKfS0_S0_Pfiffii"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__ZcalcPKfPfS0_iffii
.addrsig_sym _Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5ZcalcPKfPfS0_iffii
.addrsig_sym _Z5fCalcPKfS0_S0_Pfiffii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00139923_00000000-6_nlmGlobal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii
.type _Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii, @function
_Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii:
.LFB2081:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
leaq 4(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5ZcalcPKfPfS0_iffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii, .-_Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii
.globl _Z5ZcalcPKfPfS0_iffii
.type _Z5ZcalcPKfPfS0_iffii, @function
_Z5ZcalcPKfPfS0_iffii:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z5ZcalcPKfPfS0_iffiiPKfPfS0_iffii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z5ZcalcPKfPfS0_iffii, .-_Z5ZcalcPKfPfS0_iffii
.globl _Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii
.type _Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii, @function
_Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii:
.LFB2083:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
leaq 208(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5fCalcPKfS0_S0_Pfiffii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii, .-_Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii
.globl _Z5fCalcPKfS0_S0_Pfiffii
.type _Z5fCalcPKfS0_S0_Pfiffii, @function
_Z5fCalcPKfS0_S0_Pfiffii:
.LFB2084:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z38__device_stub__Z5fCalcPKfS0_S0_PfiffiiPKfS0_S0_Pfiffii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z5fCalcPKfS0_S0_Pfiffii, .-_Z5fCalcPKfS0_S0_Pfiffii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5fCalcPKfS0_S0_Pfiffii"
.LC1:
.string "_Z5ZcalcPKfPfS0_iffii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5fCalcPKfS0_S0_Pfiffii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5ZcalcPKfPfS0_iffii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "nlmGlobal.hip"
.globl _Z20__device_stub__ZcalcPKfPfS0_iffii # -- Begin function _Z20__device_stub__ZcalcPKfPfS0_iffii
.p2align 4, 0x90
.type _Z20__device_stub__ZcalcPKfPfS0_iffii,@function
_Z20__device_stub__ZcalcPKfPfS0_iffii: # @_Z20__device_stub__ZcalcPKfPfS0_iffii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movss %xmm0, 16(%rsp)
movss %xmm1, 12(%rsp)
movl %r8d, 8(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5ZcalcPKfPfS0_iffii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z20__device_stub__ZcalcPKfPfS0_iffii, .Lfunc_end0-_Z20__device_stub__ZcalcPKfPfS0_iffii
.cfi_endproc
# -- End function
.globl _Z20__device_stub__fCalcPKfS0_S0_Pfiffii # -- Begin function _Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.p2align 4, 0x90
.type _Z20__device_stub__fCalcPKfS0_S0_Pfiffii,@function
_Z20__device_stub__fCalcPKfS0_S0_Pfiffii: # @_Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movl %r9d, (%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5fCalcPKfS0_S0_Pfiffii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z20__device_stub__fCalcPKfS0_S0_Pfiffii, .Lfunc_end1-_Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5ZcalcPKfPfS0_iffii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5fCalcPKfS0_S0_Pfiffii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5ZcalcPKfPfS0_iffii,@object # @_Z5ZcalcPKfPfS0_iffii
.section .rodata,"a",@progbits
.globl _Z5ZcalcPKfPfS0_iffii
.p2align 3, 0x0
_Z5ZcalcPKfPfS0_iffii:
.quad _Z20__device_stub__ZcalcPKfPfS0_iffii
.size _Z5ZcalcPKfPfS0_iffii, 8
.type _Z5fCalcPKfS0_S0_Pfiffii,@object # @_Z5fCalcPKfS0_S0_Pfiffii
.globl _Z5fCalcPKfS0_S0_Pfiffii
.p2align 3, 0x0
_Z5fCalcPKfS0_S0_Pfiffii:
.quad _Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.size _Z5fCalcPKfS0_S0_Pfiffii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5ZcalcPKfPfS0_iffii"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5fCalcPKfS0_S0_Pfiffii"
.size .L__unnamed_2, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__ZcalcPKfPfS0_iffii
.addrsig_sym _Z20__device_stub__fCalcPKfS0_S0_Pfiffii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5ZcalcPKfPfS0_iffii
.addrsig_sym _Z5fCalcPKfS0_S0_Pfiffii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main()
{
int deviceCount;
cudaDeviceProp devProp;
cudaGetDeviceCount(&deviceCount);
printf("Found %d devices\n", deviceCount);
for (int device=0; device < deviceCount; device++)
{
cudaGetDeviceProperties(&devProp, device);
printf("Device %d\n", device);
printf("Compute capability: %d.%d\n", devProp.major, devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total Global Memory: %d\n", devProp.totalGlobalMem);
printf("Shared memory per block: %d\n", devProp.sharedMemPerBlock);
printf("Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Max threads per block: %d\n", devProp.maxThreadsPerBlock);
printf("Total constant memory: %d\n", devProp.totalConstMem);
printf("Clock Rate: %d\n", devProp.clockRate);
printf("Texture Alignment: %u\n", devProp.textureAlignment);
printf("Device overlap: %d\n", devProp.deviceOverlap);
printf("Multiprocessot Count: %d\n", devProp.multiProcessorCount);
printf("Max Threads Dim: %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("Max Grid Size: %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
}
getchar();
return 0;
}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main()
{
int deviceCount;
cudaDeviceProp devProp;
cudaGetDeviceCount(&deviceCount);
printf("Found %d devices\n", deviceCount);
for (int device=0; device < deviceCount; device++)
{
cudaGetDeviceProperties(&devProp, device);
printf("Device %d\n", device);
printf("Compute capability: %d.%d\n", devProp.major, devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total Global Memory: %d\n", devProp.totalGlobalMem);
printf("Shared memory per block: %d\n", devProp.sharedMemPerBlock);
printf("Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Max threads per block: %d\n", devProp.maxThreadsPerBlock);
printf("Total constant memory: %d\n", devProp.totalConstMem);
printf("Clock Rate: %d\n", devProp.clockRate);
printf("Texture Alignment: %u\n", devProp.textureAlignment);
printf("Device overlap: %d\n", devProp.deviceOverlap);
printf("Multiprocessot Count: %d\n", devProp.multiProcessorCount);
printf("Max Threads Dim: %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("Max Grid Size: %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
}
getchar();
return 0;
}
|
.file "tmpxft_000d13af_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Found %d devices\n"
.LC1:
.string "Device %d\n"
.LC2:
.string "Compute capability: %d.%d\n"
.LC3:
.string "Name: %s\n"
.LC4:
.string "Total Global Memory: %d\n"
.LC5:
.string "Shared memory per block: %d\n"
.LC6:
.string "Registers per block: %d\n"
.LC7:
.string "Warp size: %d\n"
.LC8:
.string "Max threads per block: %d\n"
.LC9:
.string "Total constant memory: %d\n"
.LC10:
.string "Clock Rate: %d\n"
.LC11:
.string "Texture Alignment: %u\n"
.LC12:
.string "Device overlap: %d\n"
.LC13:
.string "Multiprocessot Count: %d\n"
.LC14:
.string "Max Threads Dim: %d %d %d\n"
.LC15:
.string "Max Grid Size: %d %d %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq stdin(%rip), %rdi
call getc@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
int main()
{
int deviceCount;
cudaDeviceProp devProp;
cudaGetDeviceCount(&deviceCount);
printf("Found %d devices\n", deviceCount);
for (int device=0; device < deviceCount; device++)
{
cudaGetDeviceProperties(&devProp, device);
printf("Device %d\n", device);
printf("Compute capability: %d.%d\n", devProp.major, devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total Global Memory: %d\n", devProp.totalGlobalMem);
printf("Shared memory per block: %d\n", devProp.sharedMemPerBlock);
printf("Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Max threads per block: %d\n", devProp.maxThreadsPerBlock);
printf("Total constant memory: %d\n", devProp.totalConstMem);
printf("Clock Rate: %d\n", devProp.clockRate);
printf("Texture Alignment: %u\n", devProp.textureAlignment);
printf("Device overlap: %d\n", devProp.deviceOverlap);
printf("Multiprocessot Count: %d\n", devProp.multiProcessorCount);
printf("Max Threads Dim: %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("Max Grid Size: %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
}
getchar();
return 0;
}
|
#include "hip/hip_runtime.h"
#include <stdio.h>
int main()
{
int deviceCount;
hipDeviceProp_t devProp;
hipGetDeviceCount(&deviceCount);
printf("Found %d devices\n", deviceCount);
for (int device=0; device < deviceCount; device++)
{
hipGetDeviceProperties(&devProp, device);
printf("Device %d\n", device);
printf("Compute capability: %d.%d\n", devProp.major, devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total Global Memory: %d\n", devProp.totalGlobalMem);
printf("Shared memory per block: %d\n", devProp.sharedMemPerBlock);
printf("Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Max threads per block: %d\n", devProp.maxThreadsPerBlock);
printf("Total constant memory: %d\n", devProp.totalConstMem);
printf("Clock Rate: %d\n", devProp.clockRate);
printf("Texture Alignment: %u\n", devProp.textureAlignment);
printf("Device overlap: %d\n", devProp.deviceOverlap);
printf("Multiprocessot Count: %d\n", devProp.multiProcessorCount);
printf("Max Threads Dim: %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("Max Grid Size: %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
}
getchar();
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
int main()
{
int deviceCount;
hipDeviceProp_t devProp;
hipGetDeviceCount(&deviceCount);
printf("Found %d devices\n", deviceCount);
for (int device=0; device < deviceCount; device++)
{
hipGetDeviceProperties(&devProp, device);
printf("Device %d\n", device);
printf("Compute capability: %d.%d\n", devProp.major, devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total Global Memory: %d\n", devProp.totalGlobalMem);
printf("Shared memory per block: %d\n", devProp.sharedMemPerBlock);
printf("Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Max threads per block: %d\n", devProp.maxThreadsPerBlock);
printf("Total constant memory: %d\n", devProp.totalConstMem);
printf("Clock Rate: %d\n", devProp.clockRate);
printf("Texture Alignment: %u\n", devProp.textureAlignment);
printf("Device overlap: %d\n", devProp.deviceOverlap);
printf("Multiprocessot Count: %d\n", devProp.multiProcessorCount);
printf("Max Threads Dim: %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("Max Grid Size: %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
}
getchar();
return 0;
}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include "hip/hip_runtime.h"
#include <stdio.h>
int main()
{
int deviceCount;
hipDeviceProp_t devProp;
hipGetDeviceCount(&deviceCount);
printf("Found %d devices\n", deviceCount);
for (int device=0; device < deviceCount; device++)
{
hipGetDeviceProperties(&devProp, device);
printf("Device %d\n", device);
printf("Compute capability: %d.%d\n", devProp.major, devProp.minor);
printf("Name: %s\n", devProp.name);
printf("Total Global Memory: %d\n", devProp.totalGlobalMem);
printf("Shared memory per block: %d\n", devProp.sharedMemPerBlock);
printf("Registers per block: %d\n", devProp.regsPerBlock);
printf("Warp size: %d\n", devProp.warpSize);
printf("Max threads per block: %d\n", devProp.maxThreadsPerBlock);
printf("Total constant memory: %d\n", devProp.totalConstMem);
printf("Clock Rate: %d\n", devProp.clockRate);
printf("Texture Alignment: %u\n", devProp.textureAlignment);
printf("Device overlap: %d\n", devProp.deviceOverlap);
printf("Multiprocessot Count: %d\n", devProp.multiProcessorCount);
printf("Max Threads Dim: %d %d %d\n", devProp.maxThreadsDim[0], devProp.maxThreadsDim[1], devProp.maxThreadsDim[2]);
printf("Max Grid Size: %d %d %d\n", devProp.maxGridSize[0], devProp.maxGridSize[1], devProp.maxGridSize[2]);
}
getchar();
return 0;
}
|
.text
.file "kernel.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 392(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Found %d devices\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Device %d\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute capability: %d.%d\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Name: %s\n"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total Global Memory: %d\n"
.size .L.str.4, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Shared memory per block: %d\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Registers per block: %d\n"
.size .L.str.6, 25
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Warp size: %d\n"
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Max threads per block: %d\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Total constant memory: %d\n"
.size .L.str.9, 27
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Clock Rate: %d\n"
.size .L.str.10, 16
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Texture Alignment: %u\n"
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Device overlap: %d\n"
.size .L.str.12, 20
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Multiprocessot Count: %d\n"
.size .L.str.13, 26
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Max Threads Dim: %d %d %d\n"
.size .L.str.14, 27
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Max Grid Size: %d %d %d\n"
.size .L.str.15, 25
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d13af_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Found %d devices\n"
.LC1:
.string "Device %d\n"
.LC2:
.string "Compute capability: %d.%d\n"
.LC3:
.string "Name: %s\n"
.LC4:
.string "Total Global Memory: %d\n"
.LC5:
.string "Shared memory per block: %d\n"
.LC6:
.string "Registers per block: %d\n"
.LC7:
.string "Warp size: %d\n"
.LC8:
.string "Max threads per block: %d\n"
.LC9:
.string "Total constant memory: %d\n"
.LC10:
.string "Clock Rate: %d\n"
.LC11:
.string "Texture Alignment: %u\n"
.LC12:
.string "Device overlap: %d\n"
.LC13:
.string "Multiprocessot Count: %d\n"
.LC14:
.string "Max Threads Dim: %d %d %d\n"
.LC15:
.string "Max Grid Size: %d %d %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1064, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L4
movl $0, %ebx
leaq .LC1(%rip), %r15
leaq .LC2(%rip), %r14
leaq .LC3(%rip), %r13
leaq .LC4(%rip), %r12
.L5:
leaq 16(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl %ebx, %edx
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 380(%rsp), %ecx
movl 376(%rsp), %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 320(%rsp), %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 324(%rsp), %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 364(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 384(%rsp), %rdx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 400(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L5
.L4:
movq stdin(%rip), %rdi
call getc@PLT
movq 1048(%rsp), %rax
subq %fs:40, %rax
jne .L9
movl $0, %eax
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernel.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 1504
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq 8(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 368(%rsp), %esi
movl 372(%rsp), %edx
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 296(%rsp), %rsi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl 312(%rsp), %esi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movl 316(%rsp), %esi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 328(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 360(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 356(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movq 376(%rsp), %rsi
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 392(%rsp), %esi
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl 396(%rsp), %esi
movl $.L.str.13, %edi
xorl %eax, %eax
callq printf
movl 332(%rsp), %esi
movl 336(%rsp), %edx
movl 340(%rsp), %ecx
movl $.L.str.14, %edi
xorl %eax, %eax
callq printf
movl 344(%rsp), %esi
movl 348(%rsp), %edx
movl 352(%rsp), %ecx
movl $.L.str.15, %edi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB0_2
.LBB0_3: # %._crit_edge
movq stdin(%rip), %rdi
callq getc
xorl %eax, %eax
addq $1480, %rsp # imm = 0x5C8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Found %d devices\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Device %d\n"
.size .L.str.1, 11
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Compute capability: %d.%d\n"
.size .L.str.2, 27
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Name: %s\n"
.size .L.str.3, 10
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Total Global Memory: %d\n"
.size .L.str.4, 25
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Shared memory per block: %d\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Registers per block: %d\n"
.size .L.str.6, 25
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Warp size: %d\n"
.size .L.str.7, 15
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Max threads per block: %d\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Total constant memory: %d\n"
.size .L.str.9, 27
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Clock Rate: %d\n"
.size .L.str.10, 16
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Texture Alignment: %u\n"
.size .L.str.11, 23
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Device overlap: %d\n"
.size .L.str.12, 20
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "Multiprocessot Count: %d\n"
.size .L.str.13, 26
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Max Threads Dim: %d %d %d\n"
.size .L.str.14, 27
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "Max Grid Size: %d %d %d\n"
.size .L.str.15, 25
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
#define cudaErrChk(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
struct config {
int AH;
int AW;
int BH;
int BW;
int CH;
int CW;
float alpha;
float beta;
bool do_test;
};
/***************************************
* Device code "matmul"
**************************************/
template <int BLOCK_SIZE>
__global__ void sgemm (const float* A, const float* B, float* C, const int CH, const int CW, const int AW, const int BW, const float alpha, const float beta) {
int y = blockIdx.y*blockDim.y + threadIdx.y;
int x = blockIdx.x*blockDim.x + threadIdx.x;
int sy = threadIdx.y;
int sx = threadIdx.x;
__shared__ float sA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float sB[BLOCK_SIZE][BLOCK_SIZE];
int num_tiles = (AW+(BLOCK_SIZE-1))/BLOCK_SIZE;
float sum=0.0f;
for (int t=0; t<num_tiles; t++) {
if (y<CH && (sx+t*BLOCK_SIZE)<AW) {
sA[sy][sx] = A[y*AW+(sx+t*BLOCK_SIZE)];
} else {
sA[sy][sx] = 0.0f;
}
if (x<CW && (sy+t*BLOCK_SIZE)<AW) {
sB[sy][sx] = B[(sy+t*BLOCK_SIZE)*BW+x];
} else {
sB[sy][sx] = 0.0f;
}
__syncthreads();
#pragma unroll
for (int k=0; k<BLOCK_SIZE; k++) {
sum += sA[sy][k]*sB[k][sx];
}
__syncthreads();
}
if (x<CW && y<CH) {
C[y*CW+x] = alpha*sum + beta*C[y*CW+x];
}
}
/***************************************
* Host code "matmul"
**************************************/
float* host_mat_mul(const float* A, const float* B, const float* C, const struct config conf) {
printf("[Kernel] Run kernal\n");
/*** Initialize device memory ***/
const int num_executions = 1;
const int block_size = 16;
size_t size_A = sizeof(float)*conf.AH*conf.AW;
size_t size_B = sizeof(float)*conf.BH*conf.BW;
size_t size_C = sizeof(float)*conf.CH*conf.CW;
float *d_A, *d_B, *d_C;
float *result = (float *) malloc (conf.CH*conf.CW*sizeof(float));
cudaErrChk (cudaMalloc ((void**)(&d_A), size_A));
cudaErrChk (cudaMalloc ((void**)(&d_B), size_B));
cudaErrChk (cudaMalloc ((void**)(&d_C), size_C));
cudaErrChk (cudaMemcpy (d_A, A, size_A, cudaMemcpyHostToDevice));
cudaErrChk (cudaMemcpy (d_B, B, size_B, cudaMemcpyHostToDevice));
cudaErrChk (cudaMemcpy (d_C, C, size_C, cudaMemcpyHostToDevice));
cudaErrChk (cudaDeviceSynchronize ())
/*** Setup execution config ***/
dim3 threads(block_size, block_size);
dim3 blocks((conf.CW+threads.x-1)/threads.x, (conf.CH+threads.y-1)/threads.y);
/*** Run CUDA kernel ***/
cudaEvent_t start, stop;
cudaErrChk(cudaEventCreate(&start));
cudaErrChk(cudaEventCreate(&stop));
cudaErrChk(cudaEventRecord(start, NULL));
// Main body
for (int i=0; i<num_executions; i++) {
sgemm<block_size><<<blocks, threads>>>(d_A, d_B, d_C, conf.CH, conf.CW, conf.AW, conf.BW, conf.alpha, conf.beta);
cudaErrChk (cudaDeviceSynchronize ())
cudaErrChk( cudaGetLastError() );
}
// End of main body
cudaErrChk(cudaEventRecord(stop, NULL));
cudaErrChk(cudaEventSynchronize(stop));
float msec_total = 0.0f;
float gflo = num_executions*conf.CH*conf.CW*(2.0*conf.AW+2)*1e-9;
cudaErrChk(cudaEventElapsedTime(&msec_total, start, stop));
printf(" Elaped time: %.4f msec\n", msec_total);
printf(" gFlops : %.4f gflops\n", gflo/(msec_total*1e-3));
cudaErrChk (cudaMemcpy(result, d_C, size_C, cudaMemcpyDeviceToHost));
cudaErrChk (cudaDeviceSynchronize ())
cudaErrChk (cudaFree (d_A));
cudaErrChk (cudaFree (d_B));
cudaErrChk (cudaFree (d_C));
return result;
}
/****************************************
* Helper functions for host
****************************************/
const struct config host_get_cmd_args(int argc, char** argv) {
int a=100, b=100, c=100;
float alpha=1.0f, beta=0.0f;
bool do_test = false;
if (argc >= 2)
do_test = (bool)atoi(argv[1]);
if (argc >= 7) {
a = atoi(argv[2]);
b = atoi(argv[3]);
c = atoi(argv[4]);
alpha = atof(argv[5]);
beta = atof(argv[6]);
}
struct config conf = {
a,
b,
b,
c,
a,
c,
alpha,
beta,
do_test
};
printf("\n================================================\n");
printf("CUDA implementaion of SGEMM\n");
printf(" args: ./matmul [test] [a, b, c, alpha, beta]\n");
printf(" C[a, c] = alpha * A[a, b] @ B[b, c] + beta * C[a, c]\n");
printf(" C[%d, %d] = %f * A[%d, %d] @ B[%d, %d] + %f * C[%d, %d]\n", a,c,alpha,a,b,b,c,beta,a,c);
printf("================================================\n\n");
return conf;
}
void host_initialize(float *mem, const int H, const int W) {
for (int i=0; i<H; i++) {
for (int j=0; j<W; j++) {
mem[i*W+j] = (float)(rand()%100);
}
}
}
void host_test(const float *A, const float *B, const float *C, const float * result, const struct config conf) {
if (conf.do_test == false) {
printf("[TEST] Test skipped..\n");
return;
}
printf("[TEST] Test start..\n");
float alpha=conf.alpha, beta=conf.beta;
int len_k = conf.AW;
for (int i=0; i<conf.CH; i++) {
for (int j=0; j<conf.CW; j++) {
float sum = 0;
for (int k=0; k<len_k; k++) {
sum += A[i*conf.AW+k]*B[k*conf.BW+j];
}
sum = alpha*sum+beta*C[i*conf.CW+j];
if (sum != result[i*conf.CW+j]){
printf(" [ERROR] C[%d][%d] = %.f != %f\n", i, j, result[i*conf.CW+j], sum);
printf(" Test failed...!\n");
return;
}
}
}
printf(" Test passed!!\n");
return;
}
/***************************************
* Main function
**************************************/
int main(int argc, char** argv) {
/*** Program configuration ***/
const struct config conf = host_get_cmd_args(argc, argv);
srand(0);
/*** Initialize Data ***/
float *A = (float *) malloc (conf.AH*conf.AW*sizeof(float));
float *B = (float *) malloc (conf.BH*conf.BW*sizeof(float));
float *C = (float *) calloc (conf.CH*conf.CW,sizeof(float));
host_initialize(A, conf.AH, conf.AW);
host_initialize(B, conf.BH, conf.BW);
host_initialize(C, conf.CH, conf.CW);
size_t total_size = (size_t)(conf.AH*conf.AW*sizeof(float) + conf.BH*conf.BW*sizeof(float) + 2.0*conf.CH*conf.CW*sizeof(float));
printf("[Mem] Total size of matrices : %.3fGB\n", total_size*1e-9);
/*** Run matmul ***/
float* result = host_mat_mul (A, B, C, conf);
/*** Test result ***/
host_test(A, B, C, result, conf);
/*** Finalize ***/
free (A);
free (B);
free (C);
free (result);
return 0;
}
|
code for sm_80
Function : _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x4], R13 ; /* 0x0000010003037a24 */
/* 0x002fca00078e020d */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x590 ; /* 0x000004b000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R4, R4, 0xf, RZ ; /* 0x0000000f04047810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R14, R3, c[0x0][0x180], R2 ; /* 0x00006000030e7a24 */
/* 0x000fe200078e0202 */
/*0100*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R12, R13.reuse, c[0x0][0x184], R0 ; /* 0x000061000d0c7a24 */
/* 0x040fe200078e0200 */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0130*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0140*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020f */
/*0160*/ LEA.HI R5, R5, R4, RZ, 0x4 ; /* 0x0000000405057211 */
/* 0x000fe400078f20ff */
/*0170*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R19, R2, 0x4, R17 ; /* 0x0000000402137824 */
/* 0x000fe200078e0211 */
/*0190*/ MOV R18, R14 ; /* 0x0000000e00127202 */
/* 0x000fc40000000f00 */
/*01a0*/ LEA R16, R2, 0x400, 0x2 ; /* 0x0000040002107811 */
/* 0x000fe400078e10ff */
/*01b0*/ SHF.R.S32.HI R14, RZ, 0x4, R5 ; /* 0x00000004ff0e7819 */
/* 0x000fe40000011405 */
/*01c0*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fe20003f26270 */
/*01d0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f46270 */
/*01f0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x17c], P1 ; /* 0x00005f0000007a0c */
/* 0x000fe40000f26670 */
/*0200*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fe40001746670 */
/*0210*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0220*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0230*/ @!P2 IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0012 */
/*0240*/ @!P2 MOV R5, R15 ; /* 0x0000000f0005a202 */
/* 0x000fe40000000f00 */
/*0250*/ @!P1 IMAD.WIDE R24, R12, R25, c[0x0][0x168] ; /* 0x00005a000c189625 */
/* 0x000fc600078e0219 */
/*0260*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0270*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0290*/ IADD3 R18, P2, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ ISETP.LE.AND P1, PT, R14, UR4, PT ; /* 0x000000040e007c0c */
/* 0x000fe4000bf23270 */
/*02d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*02e0*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R29, [R16] ; /* 0x00000000101d7984 */
/* 0x000fe80000000800 */
/*0320*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0330*/ LDS R24, [R16+0x40] ; /* 0x0000400010187984 */
/* 0x000e680000000800 */
/*0340*/ LDS R27, [R16+0x80] ; /* 0x00008000101b7984 */
/* 0x000ea80000000800 */
/*0350*/ LDS R26, [R16+0xc0] ; /* 0x0000c000101a7984 */
/* 0x000ee80000000800 */
/*0360*/ LDS R23, [R16+0x100] ; /* 0x0001000010177984 */
/* 0x000fe80000000800 */
/*0370*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0380*/ LDS R20, [R16+0x140] ; /* 0x0001400010147984 */
/* 0x000f680000000800 */
/*0390*/ LDS R25, [R16+0x180] ; /* 0x0001800010197984 */
/* 0x000f680000000800 */
/*03a0*/ LDS R22, [R16+0x1c0] ; /* 0x0001c00010167984 */
/* 0x000f620000000800 */
/*03b0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03c0*/ LDS R21, [R16+0x200] ; /* 0x0002000010157984 */
/* 0x000fe20000000800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*03e0*/ LDS R24, [R16+0x240] ; /* 0x0002400010187984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0400*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0410*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0420*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0430*/ LDS R23, [R16+0x280] ; /* 0x0002800010177984 */
/* 0x000e640000000800 */
/*0440*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0450*/ LDS R20, [R16+0x2c0] ; /* 0x0002c00010147984 */
/* 0x000ea40000000800 */
/*0460*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0470*/ LDS R25, [R16+0x300] ; /* 0x0003000010197984 */
/* 0x000fe40000000800 */
/*0480*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*0490*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000ee80000000c00 */
/*04a0*/ LDS R22, [R16+0x340] ; /* 0x0003400010167984 */
/* 0x000f220000000800 */
/*04b0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R21, [R16+0x380] ; /* 0x0003800010157984 */
/* 0x000e220000000800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*04e0*/ LDS R8, [R16+0x3c0] ; /* 0x0003c00010087984 */
/* 0x000f620000000800 */
/*04f0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0500*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0510*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0520*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe20000000004 */
/*0530*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*0540*/ IMAD R12, R5, c[0x0][0x184], R12 ; /* 0x00006100050c7a24 */
/* 0x000fe400078e020c */
/*0550*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0560*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0570*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0580*/ @!P1 BRA 0x1c0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0590*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0200 */
/*05c0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05d0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FMUL R0, R0, c[0x0][0x18c] ; /* 0x0000630000007a20 */
/* 0x004fc80000400000 */
/*05f0*/ FFMA R21, R21, c[0x0][0x188], R0 ; /* 0x0000620015157a23 */
/* 0x000fca0000000000 */
/*0600*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
#define cudaErrChk(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
struct config {
int AH;
int AW;
int BH;
int BW;
int CH;
int CW;
float alpha;
float beta;
bool do_test;
};
/***************************************
* Device code "matmul"
**************************************/
template <int BLOCK_SIZE>
__global__ void sgemm (const float* A, const float* B, float* C, const int CH, const int CW, const int AW, const int BW, const float alpha, const float beta) {
int y = blockIdx.y*blockDim.y + threadIdx.y;
int x = blockIdx.x*blockDim.x + threadIdx.x;
int sy = threadIdx.y;
int sx = threadIdx.x;
__shared__ float sA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float sB[BLOCK_SIZE][BLOCK_SIZE];
int num_tiles = (AW+(BLOCK_SIZE-1))/BLOCK_SIZE;
float sum=0.0f;
for (int t=0; t<num_tiles; t++) {
if (y<CH && (sx+t*BLOCK_SIZE)<AW) {
sA[sy][sx] = A[y*AW+(sx+t*BLOCK_SIZE)];
} else {
sA[sy][sx] = 0.0f;
}
if (x<CW && (sy+t*BLOCK_SIZE)<AW) {
sB[sy][sx] = B[(sy+t*BLOCK_SIZE)*BW+x];
} else {
sB[sy][sx] = 0.0f;
}
__syncthreads();
#pragma unroll
for (int k=0; k<BLOCK_SIZE; k++) {
sum += sA[sy][k]*sB[k][sx];
}
__syncthreads();
}
if (x<CW && y<CH) {
C[y*CW+x] = alpha*sum + beta*C[y*CW+x];
}
}
/***************************************
* Host code "matmul"
**************************************/
float* host_mat_mul(const float* A, const float* B, const float* C, const struct config conf) {
printf("[Kernel] Run kernal\n");
/*** Initialize device memory ***/
const int num_executions = 1;
const int block_size = 16;
size_t size_A = sizeof(float)*conf.AH*conf.AW;
size_t size_B = sizeof(float)*conf.BH*conf.BW;
size_t size_C = sizeof(float)*conf.CH*conf.CW;
float *d_A, *d_B, *d_C;
float *result = (float *) malloc (conf.CH*conf.CW*sizeof(float));
cudaErrChk (cudaMalloc ((void**)(&d_A), size_A));
cudaErrChk (cudaMalloc ((void**)(&d_B), size_B));
cudaErrChk (cudaMalloc ((void**)(&d_C), size_C));
cudaErrChk (cudaMemcpy (d_A, A, size_A, cudaMemcpyHostToDevice));
cudaErrChk (cudaMemcpy (d_B, B, size_B, cudaMemcpyHostToDevice));
cudaErrChk (cudaMemcpy (d_C, C, size_C, cudaMemcpyHostToDevice));
cudaErrChk (cudaDeviceSynchronize ())
/*** Setup execution config ***/
dim3 threads(block_size, block_size);
dim3 blocks((conf.CW+threads.x-1)/threads.x, (conf.CH+threads.y-1)/threads.y);
/*** Run CUDA kernel ***/
cudaEvent_t start, stop;
cudaErrChk(cudaEventCreate(&start));
cudaErrChk(cudaEventCreate(&stop));
cudaErrChk(cudaEventRecord(start, NULL));
// Main body
for (int i=0; i<num_executions; i++) {
sgemm<block_size><<<blocks, threads>>>(d_A, d_B, d_C, conf.CH, conf.CW, conf.AW, conf.BW, conf.alpha, conf.beta);
cudaErrChk (cudaDeviceSynchronize ())
cudaErrChk( cudaGetLastError() );
}
// End of main body
cudaErrChk(cudaEventRecord(stop, NULL));
cudaErrChk(cudaEventSynchronize(stop));
float msec_total = 0.0f;
float gflo = num_executions*conf.CH*conf.CW*(2.0*conf.AW+2)*1e-9;
cudaErrChk(cudaEventElapsedTime(&msec_total, start, stop));
printf(" Elaped time: %.4f msec\n", msec_total);
printf(" gFlops : %.4f gflops\n", gflo/(msec_total*1e-3));
cudaErrChk (cudaMemcpy(result, d_C, size_C, cudaMemcpyDeviceToHost));
cudaErrChk (cudaDeviceSynchronize ())
cudaErrChk (cudaFree (d_A));
cudaErrChk (cudaFree (d_B));
cudaErrChk (cudaFree (d_C));
return result;
}
/****************************************
* Helper functions for host
****************************************/
const struct config host_get_cmd_args(int argc, char** argv) {
int a=100, b=100, c=100;
float alpha=1.0f, beta=0.0f;
bool do_test = false;
if (argc >= 2)
do_test = (bool)atoi(argv[1]);
if (argc >= 7) {
a = atoi(argv[2]);
b = atoi(argv[3]);
c = atoi(argv[4]);
alpha = atof(argv[5]);
beta = atof(argv[6]);
}
struct config conf = {
a,
b,
b,
c,
a,
c,
alpha,
beta,
do_test
};
printf("\n================================================\n");
printf("CUDA implementaion of SGEMM\n");
printf(" args: ./matmul [test] [a, b, c, alpha, beta]\n");
printf(" C[a, c] = alpha * A[a, b] @ B[b, c] + beta * C[a, c]\n");
printf(" C[%d, %d] = %f * A[%d, %d] @ B[%d, %d] + %f * C[%d, %d]\n", a,c,alpha,a,b,b,c,beta,a,c);
printf("================================================\n\n");
return conf;
}
void host_initialize(float *mem, const int H, const int W) {
for (int i=0; i<H; i++) {
for (int j=0; j<W; j++) {
mem[i*W+j] = (float)(rand()%100);
}
}
}
void host_test(const float *A, const float *B, const float *C, const float * result, const struct config conf) {
if (conf.do_test == false) {
printf("[TEST] Test skipped..\n");
return;
}
printf("[TEST] Test start..\n");
float alpha=conf.alpha, beta=conf.beta;
int len_k = conf.AW;
for (int i=0; i<conf.CH; i++) {
for (int j=0; j<conf.CW; j++) {
float sum = 0;
for (int k=0; k<len_k; k++) {
sum += A[i*conf.AW+k]*B[k*conf.BW+j];
}
sum = alpha*sum+beta*C[i*conf.CW+j];
if (sum != result[i*conf.CW+j]){
printf(" [ERROR] C[%d][%d] = %.f != %f\n", i, j, result[i*conf.CW+j], sum);
printf(" Test failed...!\n");
return;
}
}
}
printf(" Test passed!!\n");
return;
}
/***************************************
* Main function
**************************************/
int main(int argc, char** argv) {
/*** Program configuration ***/
const struct config conf = host_get_cmd_args(argc, argv);
srand(0);
/*** Initialize Data ***/
float *A = (float *) malloc (conf.AH*conf.AW*sizeof(float));
float *B = (float *) malloc (conf.BH*conf.BW*sizeof(float));
float *C = (float *) calloc (conf.CH*conf.CW,sizeof(float));
host_initialize(A, conf.AH, conf.AW);
host_initialize(B, conf.BH, conf.BW);
host_initialize(C, conf.CH, conf.CW);
size_t total_size = (size_t)(conf.AH*conf.AW*sizeof(float) + conf.BH*conf.BW*sizeof(float) + 2.0*conf.CH*conf.CW*sizeof(float));
printf("[Mem] Total size of matrices : %.3fGB\n", total_size*1e-9);
/*** Run matmul ***/
float* result = host_mat_mul (A, B, C, conf);
/*** Test result ***/
host_test(A, B, C, result, conf);
/*** Finalize ***/
free (A);
free (B);
free (C);
free (result);
return 0;
}
|
.file "tmpxft_0003f15e_00000000-6_sgemm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL44__device_stub__Z5sgemmILi16EEvPKfS1_PfiiiiffPKfS0_Pfiiiiff, @function
_ZL44__device_stub__Z5sgemmILi16EEvPKfS1_PfiiiiffPKfS0_Pfiiiiff:
.LFB4173:
.cfi_startproc
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z5sgemmILi16EEvPKfS1_Pfiiiiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4173:
.size _ZL44__device_stub__Z5sgemmILi16EEvPKfS1_PfiiiiffPKfS0_Pfiiiiff, .-_ZL44__device_stub__Z5sgemmILi16EEvPKfS1_PfiiiiffPKfS0_Pfiiiiff
.section .text._Z5sgemmILi16EEvPKfS1_Pfiiiiff,"axG",@progbits,_Z5sgemmILi16EEvPKfS1_Pfiiiiff,comdat
.weak _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.type _Z5sgemmILi16EEvPKfS1_Pfiiiiff, @function
_Z5sgemmILi16EEvPKfS1_Pfiiiiff:
.LFB4487:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _ZL44__device_stub__Z5sgemmILi16EEvPKfS1_PfiiiiffPKfS0_Pfiiiiff
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4487:
.size _Z5sgemmILi16EEvPKfS1_Pfiiiiff, .-_Z5sgemmILi16EEvPKfS1_Pfiiiiff
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4151:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4151:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "[Kernel] Run kernal\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/jhson989/cuda_study/main/jhBLAS/gemm/sgemm.cu"
.section .rodata.str1.1
.LC2:
.string "CUDA assert: %s %s %d\n"
.LC4:
.string " Elaped time: %.4f msec\n"
.LC8:
.string " gFlops : %.4f gflops\n"
.text
.globl _Z12host_mat_mulPKfS0_S0_6config
.type _Z12host_mat_mulPKfS0_S0_6config, @function
_Z12host_mat_mulPKfS0_S0_6config:
.LFB4144:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 32(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl 196(%rsp), %r15d
movl 204(%rsp), %eax
movl %eax, 8(%rsp)
movl 208(%rsp), %r14d
movl 212(%rsp), %r13d
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq 192(%rsp), %rbp
movslq %r15d, %rax
imulq %rax, %rbp
salq $2, %rbp
movl 200(%rsp), %eax
movl %eax, 12(%rsp)
movslq %r14d, %rbx
movslq %r13d, %rax
imulq %rax, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, 40(%rsp)
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L35
movslq 12(%rsp), %rax
movslq 8(%rsp), %rdx
imulq %rdx, %rax
leaq 0(,%rax,4), %r12
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L36
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L37
movl $1, %ecx
movq %rbp, %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L38
movl $1, %ecx
movq %r12, %rdx
movq 24(%rsp), %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L39
movl $1, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L40
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L41
movl $1, 104(%rsp)
leal 15(%r13), %eax
shrl $4, %eax
movl %eax, 108(%rsp)
leal 15(%r14), %eax
shrl $4, %eax
movl %eax, 112(%rsp)
movl $1, 116(%rsp)
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L42
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L43
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L44
movl $16, 96(%rsp)
movl $16, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L22:
call cudaDeviceSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L46
call cudaGetLastError@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L47
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L48
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L49
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L50
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
addsd %xmm0, %xmm0
addsd .LC5(%rip), %xmm0
imull %r14d, %r13d
pxor %xmm1, %xmm1
cvtsi2sdl %r13d, %xmm1
mulsd %xmm1, %xmm0
mulsd .LC6(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtss2sd 52(%rsp), %xmm1
mulsd .LC7(%rip), %xmm1
divsd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 72(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L51
call cudaDeviceSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L52
movq 56(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L53
movq 64(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L54
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L55
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L56
movq 40(%rsp), %rax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %eax, %r12d
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $89, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L36:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $90, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L37:
movl %eax, %ebx
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $91, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L38:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $92, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $93, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $94, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $95, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $103, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $104, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $105, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L45:
subq $8, %rsp
.cfi_def_cfa_offset 200
movl 16(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 208
movss 236(%rsp), %xmm1
movss 232(%rsp), %xmm0
movl %r15d, %r9d
movl %r13d, %r8d
movl %r14d, %ecx
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _ZL44__device_stub__Z5sgemmILi16EEvPKfS1_PfiiiiffPKfS0_Pfiiiiff
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L22
.L46:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $109, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L47:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $110, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L48:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $113, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L49:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $114, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $117, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L51:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $121, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L52:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $122, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $123, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L54:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $124, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
movl $125, %r9d
leaq .LC1(%rip), %r8
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4144:
.size _Z12host_mat_mulPKfS0_S0_6config, .-_Z12host_mat_mulPKfS0_S0_6config
.section .rodata.str1.8
.align 8
.LC10:
.string "\n================================================\n"
.section .rodata.str1.1
.LC11:
.string "CUDA implementaion of SGEMM\n"
.section .rodata.str1.8
.align 8
.LC12:
.string " args: ./matmul [test] [a, b, c, alpha, beta]\n"
.align 8
.LC13:
.string " C[a, c] = alpha * A[a, b] @ B[b, c] + beta * C[a, c]\n"
.align 8
.LC14:
.string " C[%d, %d] = %f * A[%d, %d] @ B[%d, %d] + %f * C[%d, %d]\n"
.align 8
.LC15:
.string "================================================\n\n"
.text
.globl _Z17host_get_cmd_argsiPPc
.type _Z17host_get_cmd_argsiPPc, @function
_Z17host_get_cmd_argsiPPc:
.LFB4145:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
cmpl $1, %esi
jg .L62
movl $0, %r13d
movl $0x00000000, 12(%rsp)
movss .LC9(%rip), %xmm4
movss %xmm4, 8(%rsp)
movl $100, %r12d
movl $100, %r14d
movl $100, %ebp
.L58:
movl %ebp, (%rbx)
movl %r14d, 4(%rbx)
movl %r14d, 8(%rbx)
movl %r12d, 12(%rbx)
movl %ebp, 16(%rbx)
movl %r12d, 20(%rbx)
movss 8(%rsp), %xmm2
movss %xmm2, 24(%rbx)
movss 12(%rsp), %xmm3
movss %xmm3, 28(%rbx)
movb %r13b, 32(%rbx)
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtss2sd 8(%rsp), %xmm0
pushq %r12
.cfi_def_cfa_offset 88
pushq %rbp
.cfi_def_cfa_offset 96
pushq %r12
.cfi_def_cfa_offset 104
pushq %r14
.cfi_def_cfa_offset 112
pxor %xmm1, %xmm1
cvtss2sd 44(%rsp), %xmm1
movl %r14d, %r9d
movl %ebp, %r8d
movl %r12d, %ecx
movl %ebp, %edx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $32, %rsp
.cfi_def_cfa_offset 80
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L62:
.cfi_restore_state
movl %esi, %ebp
movq %rdx, %r15
movq 8(%rdx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
testl %eax, %eax
setne %r13b
cmpl $6, %ebp
jg .L63
movl $0x00000000, 12(%rsp)
movss .LC9(%rip), %xmm5
movss %xmm5, 8(%rsp)
movl $100, %r12d
movl $100, %r14d
movl $100, %ebp
jmp .L58
.L63:
movq 16(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebp
movq 24(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r14d
movq 32(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %r12d
movq 40(%r15), %rdi
movl $0, %esi
call strtod@PLT
pxor %xmm6, %xmm6
cvtsd2ss %xmm0, %xmm6
movss %xmm6, 8(%rsp)
movq 48(%r15), %rdi
movl $0, %esi
call strtod@PLT
pxor %xmm7, %xmm7
cvtsd2ss %xmm0, %xmm7
movss %xmm7, 12(%rsp)
jmp .L58
.cfi_endproc
.LFE4145:
.size _Z17host_get_cmd_argsiPPc, .-_Z17host_get_cmd_argsiPPc
.globl _Z15host_initializePfii
.type _Z15host_initializePfii, @function
_Z15host_initializePfii:
.LFB4146:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %esi, 4(%rsp)
testl %esi, %esi
jle .L64
movq %rdi, %r15
movl %edx, %r14d
movl $0, %r13d
movl $0, %r12d
movslq %edx, %rax
movq %rax, 8(%rsp)
jmp .L66
.L68:
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rsi
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L67:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L67
.L69:
addl $1, %r12d
addl %r14d, %r13d
cmpl %r12d, 4(%rsp)
je .L64
.L66:
testl %r14d, %r14d
jg .L68
jmp .L69
.L64:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4146:
.size _Z15host_initializePfii, .-_Z15host_initializePfii
.section .rodata.str1.1
.LC16:
.string "[TEST] Test skipped..\n"
.LC17:
.string "[TEST] Test start..\n"
.section .rodata.str1.8
.align 8
.LC18:
.string " [ERROR] C[%d][%d] = %.f != %f\n"
.section .rodata.str1.1
.LC19:
.string " Test failed...!\n"
.LC20:
.string " Test passed!!\n"
.text
.globl _Z9host_testPKfS0_S0_S0_6config
.type _Z9host_testPKfS0_S0_S0_6config, @function
_Z9host_testPKfS0_S0_S0_6config:
.LFB4147:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdx, (%rsp)
movq %rcx, 8(%rsp)
movl 112(%rsp), %r14d
movl 100(%rsp), %ebx
movl 116(%rsp), %r13d
cmpb $0, 128(%rsp)
je .L88
movq %rdi, %r12
movq %rsi, %rbp
leaq .LC17(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movss 120(%rsp), %xmm2
movss 124(%rsp), %xmm3
testl %r14d, %r14d
jle .L75
movslq 108(%rsp), %rsi
salq $2, %rsi
movl $0, %r15d
movl $0, %eax
movl $0, %edx
movslq %r13d, %r10
movslq %ebx, %rcx
movq %rcx, 16(%rsp)
movl %r14d, 28(%rsp)
movl %r13d, %r8d
.L76:
testl %r8d, %r8d
jle .L80
movslq %r15d, %rcx
leaq (%r12,%rcx,4), %r14
movq 16(%rsp), %rdi
addq %rdi, %rcx
leaq (%r12,%rcx,4), %r9
movslq %eax, %r11
salq $2, %r11
movq (%rsp), %rcx
leaq (%rcx,%r11), %r13
movq 8(%rsp), %rcx
addq %rcx, %r11
movl $0, %ecx
movl %r8d, 24(%rsp)
jmp .L83
.L88:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L72
.L89:
leaq 0(%rbp,%rcx,4), %r8
movq %r14, %rdi
pxor %xmm1, %xmm1
.L77:
movss (%rdi), %xmm0
mulss (%r8), %xmm0
addss %xmm0, %xmm1
addq $4, %rdi
addq %rsi, %r8
cmpq %r9, %rdi
jne .L77
.L82:
mulss %xmm2, %xmm1
movaps %xmm3, %xmm0
mulss 0(%r13,%rcx,4), %xmm0
addss %xmm0, %xmm1
movss (%r11,%rcx,4), %xmm0
ucomiss %xmm1, %xmm0
jp .L84
jne .L84
addq $1, %rcx
cmpq %r10, %rcx
je .L86
.L83:
pxor %xmm1, %xmm1
testl %ebx, %ebx
jg .L89
jmp .L82
.L84:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
leaq .LC19(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L72:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L86:
.cfi_restore_state
movl 24(%rsp), %r8d
.L80:
addl $1, %edx
addl %r8d, %eax
addl %ebx, %r15d
cmpl %edx, 28(%rsp)
jne .L76
.L75:
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L72
.cfi_endproc
.LFE4147:
.size _Z9host_testPKfS0_S0_S0_6config, .-_Z9host_testPKfS0_S0_S0_6config
.section .rodata.str1.8
.align 8
.LC23:
.string "[Mem] Total size of matrices : %.3fGB\n"
.text
.globl main
.type main, @function
main:
.LFB4148:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rsi, %rdx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rax
movl %edi, %esi
movq %rax, %rdi
call _Z17host_get_cmd_argsiPPc
movl $0, %edi
call srand@PLT
movl 32(%rsp), %ebx
movl 36(%rsp), %eax
movl %ebx, 16(%rsp)
movl %eax, 20(%rsp)
imull %eax, %ebx
movslq %ebx, %rbx
leaq 0(,%rbx,4), %rdi
call malloc@PLT
movq %rax, %r12
movl 40(%rsp), %r13d
movl 44(%rsp), %ecx
movl %r13d, 24(%rsp)
movl %ecx, 28(%rsp)
imull %ecx, %r13d
movslq %r13d, %r13
leaq 0(,%r13,4), %rdi
call malloc@PLT
movq %rax, %rbp
movl 48(%rsp), %r15d
movl 52(%rsp), %r14d
movl %r15d, %edi
imull %r14d, %edi
movslq %edi, %rdi
movl $4, %esi
call calloc@PLT
movq %rax, 8(%rsp)
movl 20(%rsp), %edx
movl 16(%rsp), %esi
movq %r12, %rdi
call _Z15host_initializePfii
movl 28(%rsp), %edx
movl 24(%rsp), %esi
movq %rbp, %rdi
call _Z15host_initializePfii
movl %r14d, %edx
movl %r15d, %esi
movq 8(%rsp), %rdi
call _Z15host_initializePfii
pxor %xmm0, %xmm0
cvtsi2sdl %r15d, %xmm0
addsd %xmm0, %xmm0
pxor %xmm1, %xmm1
cvtsi2sdl %r14d, %xmm1
mulsd %xmm1, %xmm0
mulsd .LC21(%rip), %xmm0
addq %r13, %rbx
salq $2, %rbx
js .L91
pxor %xmm1, %xmm1
cvtsi2sdq %rbx, %xmm1
.L92:
addsd %xmm1, %xmm0
comisd .LC22(%rip), %xmm0
jnb .L93
cvttsd2siq %xmm0, %rax
.L94:
testq %rax, %rax
js .L95
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
.L96:
mulsd .LC6(%rip), %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
subq $48, %rsp
.cfi_def_cfa_offset 192
movdqa 80(%rsp), %xmm2
movups %xmm2, (%rsp)
movdqa 96(%rsp), %xmm3
movups %xmm3, 16(%rsp)
movl 112(%rsp), %eax
movl %eax, 32(%rsp)
movq 56(%rsp), %r15
movq %r15, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z12host_mat_mulPKfS0_S0_6config
movq %rax, %rbx
movdqa 80(%rsp), %xmm4
movups %xmm4, (%rsp)
movdqa 96(%rsp), %xmm5
movups %xmm5, 16(%rsp)
movl 112(%rsp), %eax
movl %eax, 32(%rsp)
movq %rbx, %rcx
movq %r15, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z9host_testPKfS0_S0_S0_6config
addq $48, %rsp
.cfi_def_cfa_offset 144
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L99
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L91:
.cfi_restore_state
shrq %rbx
pxor %xmm1, %xmm1
cvtsi2sdq %rbx, %xmm1
addsd %xmm1, %xmm1
jmp .L92
.L93:
subsd .LC22(%rip), %xmm0
cvttsd2siq %xmm0, %rax
btcq $63, %rax
jmp .L94
.L95:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
jmp .L96
.L99:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4148:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC24:
.string "_Z5sgemmILi16EEvPKfS1_Pfiiiiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4176:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC24(%rip), %rdx
movq %rdx, %rcx
leaq _Z5sgemmILi16EEvPKfS1_Pfiiiiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4176:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long 0
.long 1073741824
.align 8
.LC6:
.long -400107883
.long 1041313291
.align 8
.LC7:
.long -755914244
.long 1062232653
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC9:
.long 1065353216
.section .rodata.cst8
.align 8
.LC21:
.long 0
.long 1074790400
.align 8
.LC22:
.long 0
.long 1138753536
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
#define cudaErrChk(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
if (code != cudaSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", cudaGetErrorString(code), file, line);
if (abort) exit(code);
}
}
struct config {
int AH;
int AW;
int BH;
int BW;
int CH;
int CW;
float alpha;
float beta;
bool do_test;
};
/***************************************
* Device code "matmul"
**************************************/
template <int BLOCK_SIZE>
__global__ void sgemm (const float* A, const float* B, float* C, const int CH, const int CW, const int AW, const int BW, const float alpha, const float beta) {
int y = blockIdx.y*blockDim.y + threadIdx.y;
int x = blockIdx.x*blockDim.x + threadIdx.x;
int sy = threadIdx.y;
int sx = threadIdx.x;
__shared__ float sA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float sB[BLOCK_SIZE][BLOCK_SIZE];
int num_tiles = (AW+(BLOCK_SIZE-1))/BLOCK_SIZE;
float sum=0.0f;
for (int t=0; t<num_tiles; t++) {
if (y<CH && (sx+t*BLOCK_SIZE)<AW) {
sA[sy][sx] = A[y*AW+(sx+t*BLOCK_SIZE)];
} else {
sA[sy][sx] = 0.0f;
}
if (x<CW && (sy+t*BLOCK_SIZE)<AW) {
sB[sy][sx] = B[(sy+t*BLOCK_SIZE)*BW+x];
} else {
sB[sy][sx] = 0.0f;
}
__syncthreads();
#pragma unroll
for (int k=0; k<BLOCK_SIZE; k++) {
sum += sA[sy][k]*sB[k][sx];
}
__syncthreads();
}
if (x<CW && y<CH) {
C[y*CW+x] = alpha*sum + beta*C[y*CW+x];
}
}
/***************************************
* Host code "matmul"
**************************************/
float* host_mat_mul(const float* A, const float* B, const float* C, const struct config conf) {
printf("[Kernel] Run kernal\n");
/*** Initialize device memory ***/
const int num_executions = 1;
const int block_size = 16;
size_t size_A = sizeof(float)*conf.AH*conf.AW;
size_t size_B = sizeof(float)*conf.BH*conf.BW;
size_t size_C = sizeof(float)*conf.CH*conf.CW;
float *d_A, *d_B, *d_C;
float *result = (float *) malloc (conf.CH*conf.CW*sizeof(float));
cudaErrChk (cudaMalloc ((void**)(&d_A), size_A));
cudaErrChk (cudaMalloc ((void**)(&d_B), size_B));
cudaErrChk (cudaMalloc ((void**)(&d_C), size_C));
cudaErrChk (cudaMemcpy (d_A, A, size_A, cudaMemcpyHostToDevice));
cudaErrChk (cudaMemcpy (d_B, B, size_B, cudaMemcpyHostToDevice));
cudaErrChk (cudaMemcpy (d_C, C, size_C, cudaMemcpyHostToDevice));
cudaErrChk (cudaDeviceSynchronize ())
/*** Setup execution config ***/
dim3 threads(block_size, block_size);
dim3 blocks((conf.CW+threads.x-1)/threads.x, (conf.CH+threads.y-1)/threads.y);
/*** Run CUDA kernel ***/
cudaEvent_t start, stop;
cudaErrChk(cudaEventCreate(&start));
cudaErrChk(cudaEventCreate(&stop));
cudaErrChk(cudaEventRecord(start, NULL));
// Main body
for (int i=0; i<num_executions; i++) {
sgemm<block_size><<<blocks, threads>>>(d_A, d_B, d_C, conf.CH, conf.CW, conf.AW, conf.BW, conf.alpha, conf.beta);
cudaErrChk (cudaDeviceSynchronize ())
cudaErrChk( cudaGetLastError() );
}
// End of main body
cudaErrChk(cudaEventRecord(stop, NULL));
cudaErrChk(cudaEventSynchronize(stop));
float msec_total = 0.0f;
float gflo = num_executions*conf.CH*conf.CW*(2.0*conf.AW+2)*1e-9;
cudaErrChk(cudaEventElapsedTime(&msec_total, start, stop));
printf(" Elaped time: %.4f msec\n", msec_total);
printf(" gFlops : %.4f gflops\n", gflo/(msec_total*1e-3));
cudaErrChk (cudaMemcpy(result, d_C, size_C, cudaMemcpyDeviceToHost));
cudaErrChk (cudaDeviceSynchronize ())
cudaErrChk (cudaFree (d_A));
cudaErrChk (cudaFree (d_B));
cudaErrChk (cudaFree (d_C));
return result;
}
/****************************************
* Helper functions for host
****************************************/
const struct config host_get_cmd_args(int argc, char** argv) {
int a=100, b=100, c=100;
float alpha=1.0f, beta=0.0f;
bool do_test = false;
if (argc >= 2)
do_test = (bool)atoi(argv[1]);
if (argc >= 7) {
a = atoi(argv[2]);
b = atoi(argv[3]);
c = atoi(argv[4]);
alpha = atof(argv[5]);
beta = atof(argv[6]);
}
struct config conf = {
a,
b,
b,
c,
a,
c,
alpha,
beta,
do_test
};
printf("\n================================================\n");
printf("CUDA implementaion of SGEMM\n");
printf(" args: ./matmul [test] [a, b, c, alpha, beta]\n");
printf(" C[a, c] = alpha * A[a, b] @ B[b, c] + beta * C[a, c]\n");
printf(" C[%d, %d] = %f * A[%d, %d] @ B[%d, %d] + %f * C[%d, %d]\n", a,c,alpha,a,b,b,c,beta,a,c);
printf("================================================\n\n");
return conf;
}
void host_initialize(float *mem, const int H, const int W) {
for (int i=0; i<H; i++) {
for (int j=0; j<W; j++) {
mem[i*W+j] = (float)(rand()%100);
}
}
}
void host_test(const float *A, const float *B, const float *C, const float * result, const struct config conf) {
if (conf.do_test == false) {
printf("[TEST] Test skipped..\n");
return;
}
printf("[TEST] Test start..\n");
float alpha=conf.alpha, beta=conf.beta;
int len_k = conf.AW;
for (int i=0; i<conf.CH; i++) {
for (int j=0; j<conf.CW; j++) {
float sum = 0;
for (int k=0; k<len_k; k++) {
sum += A[i*conf.AW+k]*B[k*conf.BW+j];
}
sum = alpha*sum+beta*C[i*conf.CW+j];
if (sum != result[i*conf.CW+j]){
printf(" [ERROR] C[%d][%d] = %.f != %f\n", i, j, result[i*conf.CW+j], sum);
printf(" Test failed...!\n");
return;
}
}
}
printf(" Test passed!!\n");
return;
}
/***************************************
* Main function
**************************************/
int main(int argc, char** argv) {
/*** Program configuration ***/
const struct config conf = host_get_cmd_args(argc, argv);
srand(0);
/*** Initialize Data ***/
float *A = (float *) malloc (conf.AH*conf.AW*sizeof(float));
float *B = (float *) malloc (conf.BH*conf.BW*sizeof(float));
float *C = (float *) calloc (conf.CH*conf.CW,sizeof(float));
host_initialize(A, conf.AH, conf.AW);
host_initialize(B, conf.BH, conf.BW);
host_initialize(C, conf.CH, conf.CW);
size_t total_size = (size_t)(conf.AH*conf.AW*sizeof(float) + conf.BH*conf.BW*sizeof(float) + 2.0*conf.CH*conf.CW*sizeof(float));
printf("[Mem] Total size of matrices : %.3fGB\n", total_size*1e-9);
/*** Run matmul ***/
float* result = host_mat_mul (A, B, C, conf);
/*** Test result ***/
host_test(A, B, C, result, conf);
/*** Finalize ***/
free (A);
free (B);
free (C);
free (result);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
#define cudaErrChk(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
struct config {
int AH;
int AW;
int BH;
int BW;
int CH;
int CW;
float alpha;
float beta;
bool do_test;
};
/***************************************
* Device code "matmul"
**************************************/
template <int BLOCK_SIZE>
__global__ void sgemm (const float* A, const float* B, float* C, const int CH, const int CW, const int AW, const int BW, const float alpha, const float beta) {
int y = blockIdx.y*blockDim.y + threadIdx.y;
int x = blockIdx.x*blockDim.x + threadIdx.x;
int sy = threadIdx.y;
int sx = threadIdx.x;
__shared__ float sA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float sB[BLOCK_SIZE][BLOCK_SIZE];
int num_tiles = (AW+(BLOCK_SIZE-1))/BLOCK_SIZE;
float sum=0.0f;
for (int t=0; t<num_tiles; t++) {
if (y<CH && (sx+t*BLOCK_SIZE)<AW) {
sA[sy][sx] = A[y*AW+(sx+t*BLOCK_SIZE)];
} else {
sA[sy][sx] = 0.0f;
}
if (x<CW && (sy+t*BLOCK_SIZE)<AW) {
sB[sy][sx] = B[(sy+t*BLOCK_SIZE)*BW+x];
} else {
sB[sy][sx] = 0.0f;
}
__syncthreads();
#pragma unroll
for (int k=0; k<BLOCK_SIZE; k++) {
sum += sA[sy][k]*sB[k][sx];
}
__syncthreads();
}
if (x<CW && y<CH) {
C[y*CW+x] = alpha*sum + beta*C[y*CW+x];
}
}
/***************************************
* Host code "matmul"
**************************************/
float* host_mat_mul(const float* A, const float* B, const float* C, const struct config conf) {
printf("[Kernel] Run kernal\n");
/*** Initialize device memory ***/
const int num_executions = 1;
const int block_size = 16;
size_t size_A = sizeof(float)*conf.AH*conf.AW;
size_t size_B = sizeof(float)*conf.BH*conf.BW;
size_t size_C = sizeof(float)*conf.CH*conf.CW;
float *d_A, *d_B, *d_C;
float *result = (float *) malloc (conf.CH*conf.CW*sizeof(float));
cudaErrChk (hipMalloc ((void**)(&d_A), size_A));
cudaErrChk (hipMalloc ((void**)(&d_B), size_B));
cudaErrChk (hipMalloc ((void**)(&d_C), size_C));
cudaErrChk (hipMemcpy (d_A, A, size_A, hipMemcpyHostToDevice));
cudaErrChk (hipMemcpy (d_B, B, size_B, hipMemcpyHostToDevice));
cudaErrChk (hipMemcpy (d_C, C, size_C, hipMemcpyHostToDevice));
cudaErrChk (hipDeviceSynchronize ())
/*** Setup execution config ***/
dim3 threads(block_size, block_size);
dim3 blocks((conf.CW+threads.x-1)/threads.x, (conf.CH+threads.y-1)/threads.y);
/*** Run CUDA kernel ***/
hipEvent_t start, stop;
cudaErrChk(hipEventCreate(&start));
cudaErrChk(hipEventCreate(&stop));
cudaErrChk(hipEventRecord(start, NULL));
// Main body
for (int i=0; i<num_executions; i++) {
sgemm<block_size><<<blocks, threads>>>(d_A, d_B, d_C, conf.CH, conf.CW, conf.AW, conf.BW, conf.alpha, conf.beta);
cudaErrChk (hipDeviceSynchronize ())
cudaErrChk( hipGetLastError() );
}
// End of main body
cudaErrChk(hipEventRecord(stop, NULL));
cudaErrChk(hipEventSynchronize(stop));
float msec_total = 0.0f;
float gflo = num_executions*conf.CH*conf.CW*(2.0*conf.AW+2)*1e-9;
cudaErrChk(hipEventElapsedTime(&msec_total, start, stop));
printf(" Elaped time: %.4f msec\n", msec_total);
printf(" gFlops : %.4f gflops\n", gflo/(msec_total*1e-3));
cudaErrChk (hipMemcpy(result, d_C, size_C, hipMemcpyDeviceToHost));
cudaErrChk (hipDeviceSynchronize ())
cudaErrChk (hipFree (d_A));
cudaErrChk (hipFree (d_B));
cudaErrChk (hipFree (d_C));
return result;
}
/****************************************
* Helper functions for host
****************************************/
const struct config host_get_cmd_args(int argc, char** argv) {
int a=100, b=100, c=100;
float alpha=1.0f, beta=0.0f;
bool do_test = false;
if (argc >= 2)
do_test = (bool)atoi(argv[1]);
if (argc >= 7) {
a = atoi(argv[2]);
b = atoi(argv[3]);
c = atoi(argv[4]);
alpha = atof(argv[5]);
beta = atof(argv[6]);
}
struct config conf = {
a,
b,
b,
c,
a,
c,
alpha,
beta,
do_test
};
printf("\n================================================\n");
printf("CUDA implementaion of SGEMM\n");
printf(" args: ./matmul [test] [a, b, c, alpha, beta]\n");
printf(" C[a, c] = alpha * A[a, b] @ B[b, c] + beta * C[a, c]\n");
printf(" C[%d, %d] = %f * A[%d, %d] @ B[%d, %d] + %f * C[%d, %d]\n", a,c,alpha,a,b,b,c,beta,a,c);
printf("================================================\n\n");
return conf;
}
void host_initialize(float *mem, const int H, const int W) {
for (int i=0; i<H; i++) {
for (int j=0; j<W; j++) {
mem[i*W+j] = (float)(rand()%100);
}
}
}
void host_test(const float *A, const float *B, const float *C, const float * result, const struct config conf) {
if (conf.do_test == false) {
printf("[TEST] Test skipped..\n");
return;
}
printf("[TEST] Test start..\n");
float alpha=conf.alpha, beta=conf.beta;
int len_k = conf.AW;
for (int i=0; i<conf.CH; i++) {
for (int j=0; j<conf.CW; j++) {
float sum = 0;
for (int k=0; k<len_k; k++) {
sum += A[i*conf.AW+k]*B[k*conf.BW+j];
}
sum = alpha*sum+beta*C[i*conf.CW+j];
if (sum != result[i*conf.CW+j]){
printf(" [ERROR] C[%d][%d] = %.f != %f\n", i, j, result[i*conf.CW+j], sum);
printf(" Test failed...!\n");
return;
}
}
}
printf(" Test passed!!\n");
return;
}
/***************************************
* Main function
**************************************/
int main(int argc, char** argv) {
/*** Program configuration ***/
const struct config conf = host_get_cmd_args(argc, argv);
srand(0);
/*** Initialize Data ***/
float *A = (float *) malloc (conf.AH*conf.AW*sizeof(float));
float *B = (float *) malloc (conf.BH*conf.BW*sizeof(float));
float *C = (float *) calloc (conf.CH*conf.CW,sizeof(float));
host_initialize(A, conf.AH, conf.AW);
host_initialize(B, conf.BH, conf.BW);
host_initialize(C, conf.CH, conf.CW);
size_t total_size = (size_t)(conf.AH*conf.AW*sizeof(float) + conf.BH*conf.BW*sizeof(float) + 2.0*conf.CH*conf.CW*sizeof(float));
printf("[Mem] Total size of matrices : %.3fGB\n", total_size*1e-9);
/*** Run matmul ***/
float* result = host_mat_mul (A, B, C, conf);
/*** Test result ***/
host_test(A, B, C, result, conf);
/*** Finalize ***/
free (A);
free (B);
free (C);
free (result);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
#define cudaErrChk(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
struct config {
int AH;
int AW;
int BH;
int BW;
int CH;
int CW;
float alpha;
float beta;
bool do_test;
};
/***************************************
* Device code "matmul"
**************************************/
template <int BLOCK_SIZE>
__global__ void sgemm (const float* A, const float* B, float* C, const int CH, const int CW, const int AW, const int BW, const float alpha, const float beta) {
int y = blockIdx.y*blockDim.y + threadIdx.y;
int x = blockIdx.x*blockDim.x + threadIdx.x;
int sy = threadIdx.y;
int sx = threadIdx.x;
__shared__ float sA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float sB[BLOCK_SIZE][BLOCK_SIZE];
int num_tiles = (AW+(BLOCK_SIZE-1))/BLOCK_SIZE;
float sum=0.0f;
for (int t=0; t<num_tiles; t++) {
if (y<CH && (sx+t*BLOCK_SIZE)<AW) {
sA[sy][sx] = A[y*AW+(sx+t*BLOCK_SIZE)];
} else {
sA[sy][sx] = 0.0f;
}
if (x<CW && (sy+t*BLOCK_SIZE)<AW) {
sB[sy][sx] = B[(sy+t*BLOCK_SIZE)*BW+x];
} else {
sB[sy][sx] = 0.0f;
}
__syncthreads();
#pragma unroll
for (int k=0; k<BLOCK_SIZE; k++) {
sum += sA[sy][k]*sB[k][sx];
}
__syncthreads();
}
if (x<CW && y<CH) {
C[y*CW+x] = alpha*sum + beta*C[y*CW+x];
}
}
/***************************************
* Host code "matmul"
**************************************/
float* host_mat_mul(const float* A, const float* B, const float* C, const struct config conf) {
printf("[Kernel] Run kernal\n");
/*** Initialize device memory ***/
const int num_executions = 1;
const int block_size = 16;
size_t size_A = sizeof(float)*conf.AH*conf.AW;
size_t size_B = sizeof(float)*conf.BH*conf.BW;
size_t size_C = sizeof(float)*conf.CH*conf.CW;
float *d_A, *d_B, *d_C;
float *result = (float *) malloc (conf.CH*conf.CW*sizeof(float));
cudaErrChk (hipMalloc ((void**)(&d_A), size_A));
cudaErrChk (hipMalloc ((void**)(&d_B), size_B));
cudaErrChk (hipMalloc ((void**)(&d_C), size_C));
cudaErrChk (hipMemcpy (d_A, A, size_A, hipMemcpyHostToDevice));
cudaErrChk (hipMemcpy (d_B, B, size_B, hipMemcpyHostToDevice));
cudaErrChk (hipMemcpy (d_C, C, size_C, hipMemcpyHostToDevice));
cudaErrChk (hipDeviceSynchronize ())
/*** Setup execution config ***/
dim3 threads(block_size, block_size);
dim3 blocks((conf.CW+threads.x-1)/threads.x, (conf.CH+threads.y-1)/threads.y);
/*** Run CUDA kernel ***/
hipEvent_t start, stop;
cudaErrChk(hipEventCreate(&start));
cudaErrChk(hipEventCreate(&stop));
cudaErrChk(hipEventRecord(start, NULL));
// Main body
for (int i=0; i<num_executions; i++) {
sgemm<block_size><<<blocks, threads>>>(d_A, d_B, d_C, conf.CH, conf.CW, conf.AW, conf.BW, conf.alpha, conf.beta);
cudaErrChk (hipDeviceSynchronize ())
cudaErrChk( hipGetLastError() );
}
// End of main body
cudaErrChk(hipEventRecord(stop, NULL));
cudaErrChk(hipEventSynchronize(stop));
float msec_total = 0.0f;
float gflo = num_executions*conf.CH*conf.CW*(2.0*conf.AW+2)*1e-9;
cudaErrChk(hipEventElapsedTime(&msec_total, start, stop));
printf(" Elaped time: %.4f msec\n", msec_total);
printf(" gFlops : %.4f gflops\n", gflo/(msec_total*1e-3));
cudaErrChk (hipMemcpy(result, d_C, size_C, hipMemcpyDeviceToHost));
cudaErrChk (hipDeviceSynchronize ())
cudaErrChk (hipFree (d_A));
cudaErrChk (hipFree (d_B));
cudaErrChk (hipFree (d_C));
return result;
}
/****************************************
* Helper functions for host
****************************************/
const struct config host_get_cmd_args(int argc, char** argv) {
int a=100, b=100, c=100;
float alpha=1.0f, beta=0.0f;
bool do_test = false;
if (argc >= 2)
do_test = (bool)atoi(argv[1]);
if (argc >= 7) {
a = atoi(argv[2]);
b = atoi(argv[3]);
c = atoi(argv[4]);
alpha = atof(argv[5]);
beta = atof(argv[6]);
}
struct config conf = {
a,
b,
b,
c,
a,
c,
alpha,
beta,
do_test
};
printf("\n================================================\n");
printf("CUDA implementaion of SGEMM\n");
printf(" args: ./matmul [test] [a, b, c, alpha, beta]\n");
printf(" C[a, c] = alpha * A[a, b] @ B[b, c] + beta * C[a, c]\n");
printf(" C[%d, %d] = %f * A[%d, %d] @ B[%d, %d] + %f * C[%d, %d]\n", a,c,alpha,a,b,b,c,beta,a,c);
printf("================================================\n\n");
return conf;
}
void host_initialize(float *mem, const int H, const int W) {
for (int i=0; i<H; i++) {
for (int j=0; j<W; j++) {
mem[i*W+j] = (float)(rand()%100);
}
}
}
void host_test(const float *A, const float *B, const float *C, const float * result, const struct config conf) {
if (conf.do_test == false) {
printf("[TEST] Test skipped..\n");
return;
}
printf("[TEST] Test start..\n");
float alpha=conf.alpha, beta=conf.beta;
int len_k = conf.AW;
for (int i=0; i<conf.CH; i++) {
for (int j=0; j<conf.CW; j++) {
float sum = 0;
for (int k=0; k<len_k; k++) {
sum += A[i*conf.AW+k]*B[k*conf.BW+j];
}
sum = alpha*sum+beta*C[i*conf.CW+j];
if (sum != result[i*conf.CW+j]){
printf(" [ERROR] C[%d][%d] = %.f != %f\n", i, j, result[i*conf.CW+j], sum);
printf(" Test failed...!\n");
return;
}
}
}
printf(" Test passed!!\n");
return;
}
/***************************************
* Main function
**************************************/
int main(int argc, char** argv) {
/*** Program configuration ***/
const struct config conf = host_get_cmd_args(argc, argv);
srand(0);
/*** Initialize Data ***/
float *A = (float *) malloc (conf.AH*conf.AW*sizeof(float));
float *B = (float *) malloc (conf.BH*conf.BW*sizeof(float));
float *C = (float *) calloc (conf.CH*conf.CW,sizeof(float));
host_initialize(A, conf.AH, conf.AW);
host_initialize(B, conf.BH, conf.BW);
host_initialize(C, conf.CH, conf.CW);
size_t total_size = (size_t)(conf.AH*conf.AW*sizeof(float) + conf.BH*conf.BW*sizeof(float) + 2.0*conf.CH*conf.CW*sizeof(float));
printf("[Mem] Total size of matrices : %.3fGB\n", total_size*1e-9);
/*** Run matmul ***/
float* result = host_mat_mul (A, B, C, conf);
/*** Test result ***/
host_test(A, B, C, result, conf);
/*** Finalize ***/
free (A);
free (B);
free (C);
free (result);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z5sgemmILi16EEvPKfS1_Pfiiiiff,"axG",@progbits,_Z5sgemmILi16EEvPKfS1_Pfiiiiff,comdat
.protected _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.globl _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.p2align 8
.type _Z5sgemmILi16EEvPKfS1_Pfiiiiff,@function
_Z5sgemmILi16EEvPKfS1_Pfiiiiff:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v5, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
s_mul_i32 s14, s14, s2
s_cmp_lt_i32 s10, 1
v_add_nc_u32_e32 v1, s14, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_cbranch_scc1 .LBB0_15
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s15, s[0:1], 0x24
v_dual_mov_b32 v42, 0 :: v_dual_lshlrev_b32 v3, 2, v5
v_dual_mov_b32 v21, 0 :: v_dual_lshlrev_b32 v6, 6, v2
v_mul_lo_u32 v9, v0, s10
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v7, 0x400, v3
s_add_i32 s3, s10, 15
v_cmp_le_i32_e64 s11, s8, v0
v_add_nc_u32_e32 v8, v6, v3
v_cmp_le_i32_e64 s12, s9, v1
v_add_nc_u32_e32 v10, v7, v6
v_or_b32_e32 v11, 4, v6
v_add_nc_u32_e32 v12, 0x440, v3
v_or_b32_e32 v13, 8, v6
v_add_nc_u32_e32 v14, 0x480, v3
v_or_b32_e32 v15, 12, v6
v_add_nc_u32_e32 v16, 0x4c0, v3
v_or_b32_e32 v17, 16, v6
v_add_nc_u32_e32 v18, 0x500, v3
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v2, s15
v_or_b32_e32 v19, 20, v6
v_add_nc_u32_e32 v20, 0x540, v3
v_or_b32_e32 v22, 24, v6
v_add_nc_u32_e32 v23, 0x580, v3
v_or_b32_e32 v24, 28, v6
v_add_nc_u32_e32 v25, 0x5c0, v3
v_or_b32_e32 v26, 32, v6
v_add_nc_u32_e32 v27, 0x600, v3
v_or_b32_e32 v28, 36, v6
v_add_nc_u32_e32 v29, 0x640, v3
v_or_b32_e32 v30, 40, v6
v_add_nc_u32_e32 v31, 0x680, v3
v_or_b32_e32 v32, 44, v6
v_add_nc_u32_e32 v33, 0x6c0, v3
v_or_b32_e32 v34, 48, v6
v_add_nc_u32_e32 v35, 0x700, v3
v_or_b32_e32 v36, 52, v6
v_add_nc_u32_e32 v37, 0x740, v3
v_or_b32_e32 v38, 56, v6
v_add_nc_u32_e32 v39, 0x780, v3
v_or_b32_e32 v40, 60, v6
v_add_nc_u32_e32 v41, 0x7c0, v3
v_add3_u32 v3, v5, v4, s14
s_lshr_b32 s3, s3, 4
s_lshl_b32 s14, s15, 4
s_max_i32 s13, s3, 1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v6
ds_load_b32 v43, v7
ds_load_b32 v44, v11
ds_load_b32 v45, v12
ds_load_b32 v46, v13
ds_load_b32 v47, v14
ds_load_b32 v48, v15
ds_load_b32 v49, v16
v_add_nc_u32_e32 v5, 16, v5
v_add_nc_u32_e32 v3, s14, v3
s_add_i32 s13, s13, -1
v_add_nc_u32_e32 v2, 16, v2
s_cmp_eq_u32 s13, 0
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v4, v43
ds_load_b32 v4, v17
ds_load_b32 v43, v18
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v44, v45
ds_load_b32 v44, v19
ds_load_b32 v45, v20
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v46, v47
ds_load_b32 v46, v22
ds_load_b32 v47, v23
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v48, v49
ds_load_b32 v48, v24
ds_load_b32 v49, v25
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v4, v43
ds_load_b32 v4, v26
ds_load_b32 v43, v27
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v44, v45
ds_load_b32 v44, v28
ds_load_b32 v45, v29
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v46, v47
ds_load_b32 v46, v30
ds_load_b32 v47, v31
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v48, v49
ds_load_b32 v48, v32
ds_load_b32 v49, v33
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v4, v43
ds_load_b32 v4, v34
ds_load_b32 v43, v35
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v44, v45
ds_load_b32 v44, v36
ds_load_b32 v45, v37
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v46, v47
ds_load_b32 v46, v38
ds_load_b32 v47, v39
ds_load_b32 v50, v40
ds_load_b32 v51, v41
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v21, v48, v49
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v21, v4, v43
v_fmac_f32_e32 v21, v44, v45
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v21, v46, v47
v_fmac_f32_e32 v21, v50, v51
s_cbranch_scc1 .LBB0_16
.LBB0_3:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
v_cmp_le_i32_e64 s3, s10, v5
s_and_not1_b32 s17, s11, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, exec_lo
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_7
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v8, v42
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v43, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v44, 31, v43
v_lshlrev_b64 v[43:44], 2, v[43:44]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v43, s3, s4, v43
v_add_co_ci_u32_e64 v44, s3, s5, v44, s3
global_load_b32 v4, v[43:44], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_cmp_le_i32_e64 s3, s10, v2
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, exec_lo
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_13
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v10, v42
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[43:44], 2, v[3:4]
v_add_co_u32 v43, s3, s6, v43
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v44, s3, s7, v44, s3
global_load_b32 v4, v[43:44], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v4
s_branch .LBB0_2
.LBB0_15:
v_mov_b32_e32 v21, 0
.LBB0_16:
v_cmp_gt_i32_e32 vcc_lo, s9, v1
v_cmp_gt_i32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s9, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v21
global_store_b32 v[0:1], v2, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 52
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z5sgemmILi16EEvPKfS1_Pfiiiiff,"axG",@progbits,_Z5sgemmILi16EEvPKfS1_Pfiiiiff,comdat
.Lfunc_end0:
.size _Z5sgemmILi16EEvPKfS1_Pfiiiiff, .Lfunc_end0-_Z5sgemmILi16EEvPKfS1_Pfiiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z5sgemmILi16EEvPKfS1_Pfiiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 52
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <cstdio>
#include <cstdlib>
#include <random>
#include <sys/time.h>
#define cudaErrChk(ans) { cudaAssert((ans), __FILE__, __LINE__); }
inline void cudaAssert(hipError_t code, const char *file, int line, bool abort=true)
{
if (code != hipSuccess)
{
fprintf(stderr,"CUDA assert: %s %s %d\n", hipGetErrorString(code), file, line);
if (abort) exit(code);
}
}
struct config {
int AH;
int AW;
int BH;
int BW;
int CH;
int CW;
float alpha;
float beta;
bool do_test;
};
/***************************************
* Device code "matmul"
**************************************/
template <int BLOCK_SIZE>
__global__ void sgemm (const float* A, const float* B, float* C, const int CH, const int CW, const int AW, const int BW, const float alpha, const float beta) {
int y = blockIdx.y*blockDim.y + threadIdx.y;
int x = blockIdx.x*blockDim.x + threadIdx.x;
int sy = threadIdx.y;
int sx = threadIdx.x;
__shared__ float sA[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float sB[BLOCK_SIZE][BLOCK_SIZE];
int num_tiles = (AW+(BLOCK_SIZE-1))/BLOCK_SIZE;
float sum=0.0f;
for (int t=0; t<num_tiles; t++) {
if (y<CH && (sx+t*BLOCK_SIZE)<AW) {
sA[sy][sx] = A[y*AW+(sx+t*BLOCK_SIZE)];
} else {
sA[sy][sx] = 0.0f;
}
if (x<CW && (sy+t*BLOCK_SIZE)<AW) {
sB[sy][sx] = B[(sy+t*BLOCK_SIZE)*BW+x];
} else {
sB[sy][sx] = 0.0f;
}
__syncthreads();
#pragma unroll
for (int k=0; k<BLOCK_SIZE; k++) {
sum += sA[sy][k]*sB[k][sx];
}
__syncthreads();
}
if (x<CW && y<CH) {
C[y*CW+x] = alpha*sum + beta*C[y*CW+x];
}
}
/***************************************
* Host code "matmul"
**************************************/
float* host_mat_mul(const float* A, const float* B, const float* C, const struct config conf) {
printf("[Kernel] Run kernal\n");
/*** Initialize device memory ***/
const int num_executions = 1;
const int block_size = 16;
size_t size_A = sizeof(float)*conf.AH*conf.AW;
size_t size_B = sizeof(float)*conf.BH*conf.BW;
size_t size_C = sizeof(float)*conf.CH*conf.CW;
float *d_A, *d_B, *d_C;
float *result = (float *) malloc (conf.CH*conf.CW*sizeof(float));
cudaErrChk (hipMalloc ((void**)(&d_A), size_A));
cudaErrChk (hipMalloc ((void**)(&d_B), size_B));
cudaErrChk (hipMalloc ((void**)(&d_C), size_C));
cudaErrChk (hipMemcpy (d_A, A, size_A, hipMemcpyHostToDevice));
cudaErrChk (hipMemcpy (d_B, B, size_B, hipMemcpyHostToDevice));
cudaErrChk (hipMemcpy (d_C, C, size_C, hipMemcpyHostToDevice));
cudaErrChk (hipDeviceSynchronize ())
/*** Setup execution config ***/
dim3 threads(block_size, block_size);
dim3 blocks((conf.CW+threads.x-1)/threads.x, (conf.CH+threads.y-1)/threads.y);
/*** Run CUDA kernel ***/
hipEvent_t start, stop;
cudaErrChk(hipEventCreate(&start));
cudaErrChk(hipEventCreate(&stop));
cudaErrChk(hipEventRecord(start, NULL));
// Main body
for (int i=0; i<num_executions; i++) {
sgemm<block_size><<<blocks, threads>>>(d_A, d_B, d_C, conf.CH, conf.CW, conf.AW, conf.BW, conf.alpha, conf.beta);
cudaErrChk (hipDeviceSynchronize ())
cudaErrChk( hipGetLastError() );
}
// End of main body
cudaErrChk(hipEventRecord(stop, NULL));
cudaErrChk(hipEventSynchronize(stop));
float msec_total = 0.0f;
float gflo = num_executions*conf.CH*conf.CW*(2.0*conf.AW+2)*1e-9;
cudaErrChk(hipEventElapsedTime(&msec_total, start, stop));
printf(" Elaped time: %.4f msec\n", msec_total);
printf(" gFlops : %.4f gflops\n", gflo/(msec_total*1e-3));
cudaErrChk (hipMemcpy(result, d_C, size_C, hipMemcpyDeviceToHost));
cudaErrChk (hipDeviceSynchronize ())
cudaErrChk (hipFree (d_A));
cudaErrChk (hipFree (d_B));
cudaErrChk (hipFree (d_C));
return result;
}
/****************************************
* Helper functions for host
****************************************/
const struct config host_get_cmd_args(int argc, char** argv) {
int a=100, b=100, c=100;
float alpha=1.0f, beta=0.0f;
bool do_test = false;
if (argc >= 2)
do_test = (bool)atoi(argv[1]);
if (argc >= 7) {
a = atoi(argv[2]);
b = atoi(argv[3]);
c = atoi(argv[4]);
alpha = atof(argv[5]);
beta = atof(argv[6]);
}
struct config conf = {
a,
b,
b,
c,
a,
c,
alpha,
beta,
do_test
};
printf("\n================================================\n");
printf("CUDA implementaion of SGEMM\n");
printf(" args: ./matmul [test] [a, b, c, alpha, beta]\n");
printf(" C[a, c] = alpha * A[a, b] @ B[b, c] + beta * C[a, c]\n");
printf(" C[%d, %d] = %f * A[%d, %d] @ B[%d, %d] + %f * C[%d, %d]\n", a,c,alpha,a,b,b,c,beta,a,c);
printf("================================================\n\n");
return conf;
}
void host_initialize(float *mem, const int H, const int W) {
for (int i=0; i<H; i++) {
for (int j=0; j<W; j++) {
mem[i*W+j] = (float)(rand()%100);
}
}
}
void host_test(const float *A, const float *B, const float *C, const float * result, const struct config conf) {
if (conf.do_test == false) {
printf("[TEST] Test skipped..\n");
return;
}
printf("[TEST] Test start..\n");
float alpha=conf.alpha, beta=conf.beta;
int len_k = conf.AW;
for (int i=0; i<conf.CH; i++) {
for (int j=0; j<conf.CW; j++) {
float sum = 0;
for (int k=0; k<len_k; k++) {
sum += A[i*conf.AW+k]*B[k*conf.BW+j];
}
sum = alpha*sum+beta*C[i*conf.CW+j];
if (sum != result[i*conf.CW+j]){
printf(" [ERROR] C[%d][%d] = %.f != %f\n", i, j, result[i*conf.CW+j], sum);
printf(" Test failed...!\n");
return;
}
}
}
printf(" Test passed!!\n");
return;
}
/***************************************
* Main function
**************************************/
int main(int argc, char** argv) {
/*** Program configuration ***/
const struct config conf = host_get_cmd_args(argc, argv);
srand(0);
/*** Initialize Data ***/
float *A = (float *) malloc (conf.AH*conf.AW*sizeof(float));
float *B = (float *) malloc (conf.BH*conf.BW*sizeof(float));
float *C = (float *) calloc (conf.CH*conf.CW,sizeof(float));
host_initialize(A, conf.AH, conf.AW);
host_initialize(B, conf.BH, conf.BW);
host_initialize(C, conf.CH, conf.CW);
size_t total_size = (size_t)(conf.AH*conf.AW*sizeof(float) + conf.BH*conf.BW*sizeof(float) + 2.0*conf.CH*conf.CW*sizeof(float));
printf("[Mem] Total size of matrices : %.3fGB\n", total_size*1e-9);
/*** Run matmul ***/
float* result = host_mat_mul (A, B, C, conf);
/*** Test result ***/
host_test(A, B, C, result, conf);
/*** Finalize ***/
free (A);
free (B);
free (C);
free (result);
return 0;
}
|
.text
.file "sgemm.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z12host_mat_mulPKfS0_S0_6config
.LCPI0_0:
.quad 0x4000000000000000 # double 2
.LCPI0_1:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.LCPI0_2:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl _Z12host_mat_mulPKfS0_S0_6config
.p2align 4, 0x90
.type _Z12host_mat_mulPKfS0_S0_6config,@function
_Z12host_mat_mulPKfS0_S0_6config: # @_Z12host_mat_mulPKfS0_S0_6config
.cfi_startproc
# %bb.0: # %.critedge
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 320
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, 96(%rsp) # 8-byte Spill
movq %rsi, 104(%rsp) # 8-byte Spill
movq %rdi, 112(%rsp) # 8-byte Spill
movl $.Lstr, %edi
callq puts@PLT
movslq 320(%rsp), %rbx
movslq 324(%rsp), %rbp
imulq %rbp, %rbx
shlq $2, %rbx
movslq 328(%rsp), %r13
movslq 332(%rsp), %r15
movslq 336(%rsp), %rcx
movslq 340(%rsp), %rax
movq %rax, (%rsp) # 8-byte Spill
movl %eax, %r14d
movq %rcx, %r12
imull %ecx, %r14d
movslq %r14d, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 88(%rsp) # 8-byte Spill
leaq 32(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_1
# %bb.3: # %_Z10cudaAssert10hipError_tPKcib.exit
movl %r14d, 44(%rsp) # 4-byte Spill
movq %r15, 80(%rsp) # 8-byte Spill
imulq %r15, %r13
shlq $2, %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_4
# %bb.5: # %_Z10cudaAssert10hipError_tPKcib.exit21
movq %r12, %r14
imulq (%rsp), %r14 # 8-byte Folded Reload
shlq $2, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_43
# %bb.6: # %_Z10cudaAssert10hipError_tPKcib.exit23
movq 32(%rsp), %rdi
movq 112(%rsp), %rsi # 8-byte Reload
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_7
# %bb.8: # %_Z10cudaAssert10hipError_tPKcib.exit25
movq 24(%rsp), %rdi
movq 104(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_9
# %bb.10: # %_Z10cudaAssert10hipError_tPKcib.exit27
movq 8(%rsp), %rdi
movq 96(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
movq (%rsp), %rbx # 8-byte Reload
jne .LBB0_11
# %bb.12: # %_Z10cudaAssert10hipError_tPKcib.exit29
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_13
# %bb.14: # %_Z10cudaAssert10hipError_tPKcib.exit31
leaq 72(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_15
# %bb.16: # %_Z10cudaAssert10hipError_tPKcib.exit33
leaq 16(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB0_17
# %bb.18: # %_Z10cudaAssert10hipError_tPKcib.exit35
movq 72(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_19
# %bb.20: # %_Z10cudaAssert10hipError_tPKcib.exit37
leal 15(%rbx), %eax
shrl $4, %eax
leal 15(%r12), %edi
shrl $4, %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_22
# %bb.21:
leaq 320(%rsp), %rax
movq 32(%rsp), %rcx
movq 24(%rsp), %rdx
movq 8(%rsp), %rsi
movss 24(%rax), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 28(%rax), %xmm1 # xmm1 = mem[0],zero,zero,zero
movq %rcx, 184(%rsp)
movq %rdx, 176(%rsp)
movq %rsi, 168(%rsp)
movl %r12d, 68(%rsp)
movl %ebx, 64(%rsp)
movl %ebp, 60(%rsp)
movq 80(%rsp), %rax # 8-byte Reload
movl %eax, 56(%rsp)
movss %xmm0, 52(%rsp)
movss %xmm1, 48(%rsp)
leaq 184(%rsp), %rax
movq %rax, 192(%rsp)
leaq 176(%rsp), %rax
movq %rax, 200(%rsp)
leaq 168(%rsp), %rax
movq %rax, 208(%rsp)
leaq 68(%rsp), %rax
movq %rax, 216(%rsp)
leaq 64(%rsp), %rax
movq %rax, 224(%rsp)
leaq 60(%rsp), %rax
movq %rax, 232(%rsp)
leaq 56(%rsp), %rax
movq %rax, 240(%rsp)
leaq 52(%rsp), %rax
movq %rax, 248(%rsp)
leaq 48(%rsp), %rax
movq %rax, 256(%rsp)
leaq 152(%rsp), %rdi
leaq 136(%rsp), %rsi
leaq 128(%rsp), %rdx
leaq 120(%rsp), %rcx
callq __hipPopCallConfiguration
movq 152(%rsp), %rsi
movl 160(%rsp), %edx
movq 136(%rsp), %rcx
movl 144(%rsp), %r8d
leaq 192(%rsp), %r9
movl $_Z5sgemmILi16EEvPKfS1_Pfiiiiff, %edi
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
pushq 136(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_22:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_23
# %bb.24: # %_Z10cudaAssert10hipError_tPKcib.exit39
callq hipGetLastError
testl %eax, %eax
movq 88(%rsp), %rbx # 8-byte Reload
jne .LBB0_25
# %bb.26: # %_Z10cudaAssert10hipError_tPKcib.exit41
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB0_27
# %bb.28: # %_Z10cudaAssert10hipError_tPKcib.exit43
movq 16(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB0_29
# %bb.30: # %_Z10cudaAssert10hipError_tPKcib.exit45
movl $0, 192(%rsp)
movq 72(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 192(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB0_31
# %bb.32: # %_Z10cudaAssert10hipError_tPKcib.exit47
cvtsi2sd %ebp, %xmm0
addsd %xmm0, %xmm0
addsd .LCPI0_0(%rip), %xmm0
cvtsi2sdl 44(%rsp), %xmm1 # 4-byte Folded Reload
mulsd %xmm0, %xmm1
mulsd .LCPI0_1(%rip), %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movss 192(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 192(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
mulsd .LCPI0_2(%rip), %xmm1
divsd %xmm1, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_33
# %bb.34: # %_Z10cudaAssert10hipError_tPKcib.exit49
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_35
# %bb.36: # %_Z10cudaAssert10hipError_tPKcib.exit51
movq 32(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_37
# %bb.38: # %_Z10cudaAssert10hipError_tPKcib.exit53
movq 24(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_39
# %bb.40: # %_Z10cudaAssert10hipError_tPKcib.exit55
movq 8(%rsp), %rdi
callq hipFree
testl %eax, %eax
jne .LBB0_41
# %bb.42: # %_Z10cudaAssert10hipError_tPKcib.exit57
movq %rbx, %rax
addq $264, %rsp # imm = 0x108
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_1:
.cfi_def_cfa_offset 320
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $91, %r8d
jmp .LBB0_2
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $92, %r8d
jmp .LBB0_2
.LBB0_43:
movl %eax, %r15d
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $93, %r8d
xorl %eax, %eax
callq fprintf
movl %r15d, %edi
callq exit
.LBB0_7:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $94, %r8d
jmp .LBB0_2
.LBB0_9:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $95, %r8d
jmp .LBB0_2
.LBB0_11:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $96, %r8d
jmp .LBB0_2
.LBB0_13:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $97, %r8d
jmp .LBB0_2
.LBB0_15:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $105, %r8d
jmp .LBB0_2
.LBB0_17:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $106, %r8d
jmp .LBB0_2
.LBB0_19:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $107, %r8d
jmp .LBB0_2
.LBB0_23:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $111, %r8d
jmp .LBB0_2
.LBB0_25:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $112, %r8d
jmp .LBB0_2
.LBB0_27:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $115, %r8d
jmp .LBB0_2
.LBB0_29:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $116, %r8d
jmp .LBB0_2
.LBB0_31:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $119, %r8d
jmp .LBB0_2
.LBB0_33:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $123, %r8d
jmp .LBB0_2
.LBB0_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $124, %r8d
jmp .LBB0_2
.LBB0_37:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $125, %r8d
jmp .LBB0_2
.LBB0_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $126, %r8d
jmp .LBB0_2
.LBB0_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.16, %esi
movl $.L.str.1, %ecx
movq %rbx, %rdi
movq %rax, %rdx
movl $127, %r8d
.LBB0_2:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size _Z12host_mat_mulPKfS0_S0_6config, .Lfunc_end0-_Z12host_mat_mulPKfS0_S0_6config
.cfi_endproc
# -- End function
.section .text._Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff,"axG",@progbits,_Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff,comdat
.weak _Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff # -- Begin function _Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff
.p2align 4, 0x90
.type _Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff,@function
_Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff: # @_Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movss %xmm0, 8(%rsp)
movss %xmm1, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5sgemmILi16EEvPKfS1_Pfiiiiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end1:
.size _Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff, .Lfunc_end1-_Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17host_get_cmd_argsiPPc
.LCPI2_0:
.long 0x3f800000 # float 1
.text
.globl _Z17host_get_cmd_argsiPPc
.p2align 4, 0x90
.type _Z17host_get_cmd_argsiPPc,@function
_Z17host_get_cmd_argsiPPc: # @_Z17host_get_cmd_argsiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r13
movl %esi, %ebp
movq %rdi, %rbx
cmpl $2, %esi
jl .LBB2_1
# %bb.2:
movq 8(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
setne %al
cmpl $7, %ebp
jge .LBB2_5
.LBB2_4:
xorps %xmm1, %xmm1
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsp) # 4-byte Spill
movl $100, %r14d
movl $100, %r15d
movl $100, %r12d
jmp .LBB2_6
.LBB2_1:
xorl %eax, %eax
cmpl $7, %ebp
jl .LBB2_4
.LBB2_5:
movq 16(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
movl %eax, %ebp
callq __isoc23_strtol
movq %rax, %r14
movq 24(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 32(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 40(%r13), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rsp) # 4-byte Spill
movq 48(%r13), %rdi
xorl %esi, %esi
callq strtod
movl %ebp, %eax
cvtsd2ss %xmm0, %xmm1
.LBB2_6:
movss %xmm1, 4(%rsp) # 4-byte Spill
movl %r14d, (%rbx)
movl %r15d, 4(%rbx)
movl %r15d, 8(%rbx)
movl %r12d, 12(%rbx)
movl %r14d, 16(%rbx)
movl %r12d, 20(%rbx)
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 24(%rbx)
movss %xmm1, 28(%rbx)
movb %al, 32(%rbx)
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
movl $.Lstr.3, %edi
callq puts@PLT
movl $.Lstr.4, %edi
callq puts@PLT
movss (%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss 4(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.8, %edi
movl %r14d, %esi
movl %r12d, %edx
movl %r14d, %ecx
movl %r15d, %r8d
movl %r15d, %r9d
movb $2, %al
pushq %r12
.cfi_adjust_cfa_offset 8
pushq %r14
.cfi_adjust_cfa_offset 8
pushq %r12
.cfi_adjust_cfa_offset 8
callq printf
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $.Lstr.5, %edi
callq puts@PLT
movq %rbx, %rax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17host_get_cmd_argsiPPc, .Lfunc_end2-_Z17host_get_cmd_argsiPPc
.cfi_endproc
# -- End function
.globl _Z15host_initializePfii # -- Begin function _Z15host_initializePfii
.p2align 4, 0x90
.type _Z15host_initializePfii,@function
_Z15host_initializePfii: # @_Z15host_initializePfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z15host_initializePfii, .Lfunc_end3-_Z15host_initializePfii
.cfi_endproc
# -- End function
.globl _Z9host_testPKfS0_S0_S0_6config # -- Begin function _Z9host_testPKfS0_S0_S0_6config
.p2align 4, 0x90
.type _Z9host_testPKfS0_S0_S0_6config,@function
_Z9host_testPKfS0_S0_S0_6config: # @_Z9host_testPKfS0_S0_S0_6config
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $72, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 48(%rsp) # 8-byte Spill
cmpb $0, 160(%rsp)
je .LBB4_1
# %bb.2:
movq %rdi, %r13
movq %rdx, 24(%rsp) # 8-byte Spill
movq %rcx, 32(%rsp) # 8-byte Spill
leaq 128(%rsp), %r14
movl $.Lstr.6, %edi
callq puts@PLT
movl 16(%r14), %r10d
movl $.Lstr.8, %edi
testl %r10d, %r10d
setg %r11b
jle .LBB4_16
# %bb.3: # %.preheader48.lr.ph
movss 24(%r14), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss 28(%r14), %xmm3 # xmm3 = mem[0],zero,zero,zero
movslq 4(%r14), %rax
movl %eax, %r15d
movslq 20(%r14), %rbx
testq %rbx, %rbx
setg 7(%rsp) # 1-byte Folded Spill
movslq 12(%r14), %r14
movl %ebx, %ecx
movq %rcx, 64(%rsp) # 8-byte Spill
movq %rax, %rbp
leaq (,%rax,4), %rax
movq %rax, 56(%rsp) # 8-byte Spill
shlq $2, %r14
xorl %eax, %eax
movq %rax, 8(%rsp) # 8-byte Spill
movq 32(%rsp), %r8 # 8-byte Reload
movq 24(%rsp), %r9 # 8-byte Reload
movq %r10, 40(%rsp) # 8-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
movss %xmm3, 16(%rsp) # 4-byte Spill
jmp .LBB4_4
.p2align 4, 0x90
.LBB4_8: # in Loop: Header=BB4_4 Depth=1
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.12, %edi
movq 8(%rsp), %rsi # 8-byte Reload
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
movb $2, %al
movb %r11b, 6(%rsp) # 1-byte Spill
callq printf
movl $.Lstr.7, %edi
callq puts@PLT
movss 16(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movzbl 6(%rsp), %eax # 1-byte Folded Reload
movss 20(%rsp), %xmm2 # 4-byte Reload
# xmm2 = mem[0],zero,zero,zero
movq 40(%rsp), %r10 # 8-byte Reload
movq 24(%rsp), %r9 # 8-byte Reload
movq 32(%rsp), %r8 # 8-byte Reload
testb $1, %r12b
jne .LBB4_9
.LBB4_14: # %.critedge45
# in Loop: Header=BB4_4 Depth=1
movq 8(%rsp), %rcx # 8-byte Reload
incq %rcx
cmpq %r10, %rcx
setb %r11b
addq 56(%rsp), %r13 # 8-byte Folded Reload
movq %rcx, %rax
movq %rcx, 8(%rsp) # 8-byte Spill
cmpq %r10, %rcx
je .LBB4_15
.LBB4_4: # %.preheader48
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
# Child Loop BB4_12 Depth 3
testl %ebx, %ebx
jle .LBB4_14
# %bb.5: # %.preheader.lr.ph
# in Loop: Header=BB4_4 Depth=1
movq 8(%rsp), %rax # 8-byte Reload
imulq %rbx, %rax
movq 48(%rsp), %rcx # 8-byte Reload
xorl %edx, %edx
movzbl 7(%rsp), %r12d # 1-byte Folded Reload
.p2align 4, 0x90
.LBB4_6: # %.preheader
# Parent Loop BB4_4 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB4_12 Depth 3
xorps %xmm0, %xmm0
testl %ebp, %ebp
jle .LBB4_7
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB4_6 Depth=2
movq %rcx, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB4_12: # %.lr.ph
# Parent Loop BB4_4 Depth=1
# Parent Loop BB4_6 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r13,%rdi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rsi), %xmm1
addss %xmm1, %xmm0
incq %rdi
addq %r14, %rsi
cmpq %rdi, %r15
jne .LBB4_12
.LBB4_7: # %._crit_edge
# in Loop: Header=BB4_6 Depth=2
mulss %xmm2, %xmm0
leaq (%rax,%rdx), %rsi
movss (%r9,%rsi,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm3, %xmm1
addss %xmm0, %xmm1
movss (%r8,%rsi,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss %xmm0, %xmm1
jne .LBB4_8
jp .LBB4_8
# %bb.13: # %.critedge
# in Loop: Header=BB4_6 Depth=2
incq %rdx
cmpq %rbx, %rdx
setl %r12b
addq $4, %rcx
cmpq 64(%rsp), %rdx # 8-byte Folded Reload
jne .LBB4_6
jmp .LBB4_14
.LBB4_1:
movl $.Lstr.9, %edi
jmp .LBB4_16
.LBB4_15:
movl $.Lstr.8, %edi
.LBB4_16: # %.sink.split
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.LBB4_9:
.cfi_def_cfa_offset 128
testb $1, %al
movl $.Lstr.8, %edi
je .LBB4_16
# %bb.10:
addq $72, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9host_testPKfS0_S0_S0_6config, .Lfunc_end4-_Z9host_testPKfS0_S0_S0_6config
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI5_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI5_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_2:
.quad 0x4010000000000000 # double 4
.LCPI5_3:
.quad 0x43e0000000000000 # double 9.2233720368547758E+18
.LCPI5_4:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rdx
movl %edi, %esi
leaq 80(%rsp), %rdi
callq _Z17host_get_cmd_argsiPPc
xorl %eax, %eax
movq %rax, 48(%rsp) # 8-byte Spill
xorl %edi, %edi
callq srand
movl 80(%rsp), %r14d
movl 84(%rsp), %ebp
movl %ebp, %eax
imull %r14d, %eax
cltq
movq %rax, 128(%rsp) # 8-byte Spill
leaq (,%rax,4), %rdi
callq malloc
movq %rax, 64(%rsp) # 8-byte Spill
movl 88(%rsp), %ecx
movl 92(%rsp), %ebx
movl %ebx, %eax
movq %rcx, 72(%rsp) # 8-byte Spill
imull %ecx, %eax
cltq
movq %rax, 120(%rsp) # 8-byte Spill
leaq (,%rax,4), %rdi
callq malloc
movq %rax, 56(%rsp) # 8-byte Spill
movl 96(%rsp), %ecx
movl 100(%rsp), %r13d
movl %r13d, %eax
movq %rcx, 40(%rsp) # 8-byte Spill
imull %ecx, %eax
movslq %eax, %rdi
movl $4, %esi
callq calloc
movq %rax, 136(%rsp) # 8-byte Spill
movq %r14, 144(%rsp) # 8-byte Spill
testl %r14d, %r14d
jle .LBB5_6
# %bb.1: # %.preheader.lr.ph.i
xorl %r12d, %r12d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_5: # %._crit_edge.i
# in Loop: Header=BB5_2 Depth=1
incq %r12
movq 48(%rsp), %rax # 8-byte Reload
addl %ebp, %eax
movq %rax, 48(%rsp) # 8-byte Spill
cmpq 144(%rsp), %r12 # 8-byte Folded Reload
je .LBB5_6
.LBB5_2: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
testl %ebp, %ebp
jle .LBB5_5
# %bb.3: # %.lr.ph.i
# in Loop: Header=BB5_2 Depth=1
movl 48(%rsp), %eax # 4-byte Reload
movq 64(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r14,4)
incq %r14
cmpq %r14, %rbp
jne .LBB5_4
jmp .LBB5_5
.LBB5_6: # %_Z15host_initializePfii.exit
cmpl $0, 72(%rsp) # 4-byte Folded Reload
jle .LBB5_12
# %bb.7: # %.preheader.lr.ph.i16
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB5_8
.p2align 4, 0x90
.LBB5_11: # %._crit_edge.i20
# in Loop: Header=BB5_8 Depth=1
incq %r15
addl %ebx, %r14d
cmpq 72(%rsp), %r15 # 8-byte Folded Reload
je .LBB5_12
.LBB5_8: # %.preheader.i18
# =>This Loop Header: Depth=1
# Child Loop BB5_10 Depth 2
testl %ebx, %ebx
jle .LBB5_11
# %bb.9: # %.lr.ph.i23
# in Loop: Header=BB5_8 Depth=1
movl %r14d, %eax
movq 56(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r12
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB5_10: # Parent Loop BB5_8 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r12,%rbp,4)
incq %rbp
cmpq %rbp, %rbx
jne .LBB5_10
jmp .LBB5_11
.LBB5_12: # %_Z15host_initializePfii.exit28
cmpl $0, 40(%rsp) # 4-byte Folded Reload
movq 136(%rsp), %rbp # 8-byte Reload
jle .LBB5_18
# %bb.13: # %.preheader.lr.ph.i29
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB5_14
.p2align 4, 0x90
.LBB5_17: # %._crit_edge.i33
# in Loop: Header=BB5_14 Depth=1
incq %r14
addl %r13d, %ebx
cmpq 40(%rsp), %r14 # 8-byte Folded Reload
je .LBB5_18
.LBB5_14: # %.preheader.i31
# =>This Loop Header: Depth=1
# Child Loop BB5_16 Depth 2
testl %r13d, %r13d
jle .LBB5_17
# %bb.15: # %.lr.ph.i36
# in Loop: Header=BB5_14 Depth=1
movl %ebx, %eax
leaq (,%rax,4), %r15
addq %rbp, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB5_16: # Parent Loop BB5_14 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB5_16
jmp .LBB5_17
.LBB5_18: # %_Z15host_initializePfii.exit41
movq 120(%rsp), %rax # 8-byte Reload
addq 128(%rsp), %rax # 8-byte Folded Reload
shlq $2, %rax
movq %rax, %xmm2
movdqa .LCPI5_0(%rip), %xmm0 # xmm0 = [1127219200,1160773632,0,0]
punpckldq %xmm0, %xmm2 # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
movapd .LCPI5_1(%rip), %xmm1 # xmm1 = [4.503599627370496E+15,1.9342813113834067E+25]
subpd %xmm1, %xmm2
cvtsi2sdl 40(%rsp), %xmm3 # 4-byte Folded Reload
addsd %xmm3, %xmm3
cvtsi2sd %r13d, %xmm4
mulsd %xmm3, %xmm4
movapd %xmm2, %xmm3
unpckhpd %xmm2, %xmm3 # xmm3 = xmm3[1],xmm2[1]
mulsd .LCPI5_2(%rip), %xmm4
addsd %xmm2, %xmm3
addsd %xmm3, %xmm4
cvttsd2si %xmm4, %rax
movq %rax, %rcx
sarq $63, %rcx
subsd .LCPI5_3(%rip), %xmm4
cvttsd2si %xmm4, %rdx
andq %rcx, %rdx
orq %rax, %rdx
movq %rdx, %xmm2
punpckldq %xmm0, %xmm2 # xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
subpd %xmm1, %xmm2
movapd %xmm2, %xmm0
unpckhpd %xmm2, %xmm0 # xmm0 = xmm0[1],xmm2[1]
addsd %xmm2, %xmm0
mulsd .LCPI5_4(%rip), %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
movl 112(%rsp), %eax
movl %eax, 32(%rsp)
movups 80(%rsp), %xmm0
movups 96(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movups %xmm0, (%rsp)
movq 64(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq 56(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
movq %rbp, %rdx
callq _Z12host_mat_mulPKfS0_S0_6config
movq %rax, %r12
movl 112(%rsp), %eax
movl %eax, 32(%rsp)
movups 80(%rsp), %xmm0
movups 96(%rsp), %xmm1
movups %xmm1, 16(%rsp)
movups %xmm0, (%rsp)
movq %rbx, %rdi
movq %r14, %rsi
movq %rbp, %rdx
movq %r12, %rcx
callq _Z9host_testPKfS0_S0_S0_6config
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %rbp, %rdi
callq free
movq %r12, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5sgemmILi16EEvPKfS1_Pfiiiiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/jhson989/cuda_study/main/jhBLAS/gemm/sgemm.hip"
.size .L.str.1, 104
.type _Z5sgemmILi16EEvPKfS1_Pfiiiiff,@object # @_Z5sgemmILi16EEvPKfS1_Pfiiiiff
.section .rodata._Z5sgemmILi16EEvPKfS1_Pfiiiiff,"aG",@progbits,_Z5sgemmILi16EEvPKfS1_Pfiiiiff,comdat
.weak _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.p2align 3, 0x0
_Z5sgemmILi16EEvPKfS1_Pfiiiiff:
.quad _Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff
.size _Z5sgemmILi16EEvPKfS1_Pfiiiiff, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " Elaped time: %.4f msec\n"
.size .L.str.2, 28
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " gFlops : %.4f gflops\n"
.size .L.str.3, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz " C[%d, %d] = %f * A[%d, %d] @ B[%d, %d] + %f * C[%d, %d]\n"
.size .L.str.8, 61
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz " [ERROR] C[%d][%d] = %.f != %f\n"
.size .L.str.12, 35
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "[Mem] Total size of matrices : %.3fGB\n"
.size .L.str.15, 39
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "CUDA assert: %s %s %d\n"
.size .L.str.16, 23
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5sgemmILi16EEvPKfS1_Pfiiiiff"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "[Kernel] Run kernal"
.size .Lstr, 20
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n================================================"
.size .Lstr.1, 50
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "CUDA implementaion of SGEMM"
.size .Lstr.2, 28
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " args: ./matmul [test] [a, b, c, alpha, beta]"
.size .Lstr.3, 49
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz " C[a, c] = alpha * A[a, b] @ B[b, c] + beta * C[a, c]"
.size .Lstr.4, 57
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "================================================\n"
.size .Lstr.5, 50
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "[TEST] Test start.."
.size .Lstr.6, 20
.type .Lstr.7,@object # @str.7
.Lstr.7:
.asciz " Test failed...!"
.size .Lstr.7, 20
.type .Lstr.8,@object # @str.8
.Lstr.8:
.asciz " Test passed!!"
.size .Lstr.8, 18
.type .Lstr.9,@object # @str.9
.Lstr.9:
.asciz "[TEST] Test skipped.."
.size .Lstr.9, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__sgemmILi16EEvPKfS1_Pfiiiiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0060*/ ISETP.GE.AND P1, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc60003f26270 */
/*0070*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0080*/ S2R R13, SR_TID.Y ; /* 0x00000000000d7919 */
/* 0x000e620000002200 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R2 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R3, R3, c[0x0][0x4], R13 ; /* 0x0000010003037a24 */
/* 0x002fca00078e020d */
/*00c0*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fe20000706670 */
/*00d0*/ @!P1 BRA 0x590 ; /* 0x000004b000009947 */
/* 0x000fd80003800000 */
/*00e0*/ IADD3 R4, R4, 0xf, RZ ; /* 0x0000000f04047810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD R14, R3, c[0x0][0x180], R2 ; /* 0x00006000030e7a24 */
/* 0x000fe200078e0202 */
/*0100*/ MOV R15, 0x4 ; /* 0x00000004000f7802 */
/* 0x000fe20000000f00 */
/*0110*/ IMAD R12, R13.reuse, c[0x0][0x184], R0 ; /* 0x000061000d0c7a24 */
/* 0x040fe200078e0200 */
/*0120*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe20000011404 */
/*0130*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0140*/ SHF.L.U32 R17, R13, 0x6, RZ ; /* 0x000000060d117819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD.WIDE R14, R14, R15, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e020f */
/*0160*/ LEA.HI R5, R5, R4, RZ, 0x4 ; /* 0x0000000405057211 */
/* 0x000fe400078f20ff */
/*0170*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD R19, R2, 0x4, R17 ; /* 0x0000000402137824 */
/* 0x000fe200078e0211 */
/*0190*/ MOV R18, R14 ; /* 0x0000000e00127202 */
/* 0x000fc40000000f00 */
/*01a0*/ LEA R16, R2, 0x400, 0x2 ; /* 0x0000040002107811 */
/* 0x000fe400078e10ff */
/*01b0*/ SHF.R.S32.HI R14, RZ, 0x4, R5 ; /* 0x00000004ff0e7819 */
/* 0x000fe40000011405 */
/*01c0*/ ISETP.GE.AND P1, PT, R13, c[0x0][0x180], PT ; /* 0x000060000d007a0c */
/* 0x000fe20003f26270 */
/*01d0*/ HFMA2.MMA R22, -RZ, RZ, 0, 0 ; /* 0x00000000ff167435 */
/* 0x000fe200000001ff */
/*01e0*/ ISETP.GE.AND P2, PT, R2, c[0x0][0x180], PT ; /* 0x0000600002007a0c */
/* 0x000fe40003f46270 */
/*01f0*/ ISETP.GE.OR P1, PT, R0, c[0x0][0x17c], P1 ; /* 0x00005f0000007a0c */
/* 0x000fe40000f26670 */
/*0200*/ ISETP.GE.OR P2, PT, R3, c[0x0][0x178], P2 ; /* 0x00005e0003007a0c */
/* 0x000fe40001746670 */
/*0210*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0220*/ @!P1 MOV R25, 0x4 ; /* 0x0000000400199802 */
/* 0x000fe40000000f00 */
/*0230*/ @!P2 IMAD.MOV.U32 R4, RZ, RZ, R18 ; /* 0x000000ffff04a224 */
/* 0x000fe200078e0012 */
/*0240*/ @!P2 MOV R5, R15 ; /* 0x0000000f0005a202 */
/* 0x000fe40000000f00 */
/*0250*/ @!P1 IMAD.WIDE R24, R12, R25, c[0x0][0x168] ; /* 0x00005a000c189625 */
/* 0x000fc600078e0219 */
/*0260*/ @!P2 LDG.E R22, [R4.64] ; /* 0x000000060416a981 */
/* 0x000ea8000c1e1900 */
/*0270*/ @!P1 LDG.E R28, [R24.64] ; /* 0x00000006181c9981 */
/* 0x000ee2000c1e1900 */
/*0280*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0290*/ IADD3 R18, P2, R18, 0x40, RZ ; /* 0x0000004012127810 */
/* 0x000fe40007f5e0ff */
/*02a0*/ IADD3 R13, R13, 0x10, RZ ; /* 0x000000100d0d7810 */
/* 0x000fe40007ffe0ff */
/*02b0*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc40007ffe0ff */
/*02c0*/ ISETP.LE.AND P1, PT, R14, UR4, PT ; /* 0x000000040e007c0c */
/* 0x000fe4000bf23270 */
/*02d0*/ IADD3.X R15, RZ, R15, RZ, P2, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe200017fe4ff */
/*02e0*/ STS [R19], R22 ; /* 0x0000001613007388 */
/* 0x004fe80000000800 */
/*02f0*/ STS [R19+0x400], R28 ; /* 0x0004001c13007388 */
/* 0x008fe80000000800 */
/*0300*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0310*/ LDS R29, [R16] ; /* 0x00000000101d7984 */
/* 0x000fe80000000800 */
/*0320*/ LDS.128 R8, [R17] ; /* 0x0000000011087984 */
/* 0x000e280000000c00 */
/*0330*/ LDS R24, [R16+0x40] ; /* 0x0000400010187984 */
/* 0x000e680000000800 */
/*0340*/ LDS R27, [R16+0x80] ; /* 0x00008000101b7984 */
/* 0x000ea80000000800 */
/*0350*/ LDS R26, [R16+0xc0] ; /* 0x0000c000101a7984 */
/* 0x000ee80000000800 */
/*0360*/ LDS R23, [R16+0x100] ; /* 0x0001000010177984 */
/* 0x000fe80000000800 */
/*0370*/ LDS.128 R4, [R17+0x10] ; /* 0x0000100011047984 */
/* 0x000f280000000c00 */
/*0380*/ LDS R20, [R16+0x140] ; /* 0x0001400010147984 */
/* 0x000f680000000800 */
/*0390*/ LDS R25, [R16+0x180] ; /* 0x0001800010197984 */
/* 0x000f680000000800 */
/*03a0*/ LDS R22, [R16+0x1c0] ; /* 0x0001c00010167984 */
/* 0x000f620000000800 */
/*03b0*/ FFMA R8, R29, R8, R21 ; /* 0x000000081d087223 */
/* 0x001fc60000000015 */
/*03c0*/ LDS R21, [R16+0x200] ; /* 0x0002000010157984 */
/* 0x000fe20000000800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x002fc60000000008 */
/*03e0*/ LDS R24, [R16+0x240] ; /* 0x0002400010187984 */
/* 0x000fe20000000800 */
/*03f0*/ FFMA R8, R27, R10, R8 ; /* 0x0000000a1b087223 */
/* 0x004fc80000000008 */
/*0400*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x008fe40000000008 */
/*0410*/ LDS.128 R8, [R17+0x20] ; /* 0x0000200011087984 */
/* 0x000e240000000c00 */
/*0420*/ FFMA R4, R23, R4, R26 ; /* 0x0000000417047223 */
/* 0x010fe4000000001a */
/*0430*/ LDS R23, [R16+0x280] ; /* 0x0002800010177984 */
/* 0x000e640000000800 */
/*0440*/ FFMA R4, R20, R5, R4 ; /* 0x0000000514047223 */
/* 0x020fe40000000004 */
/*0450*/ LDS R20, [R16+0x2c0] ; /* 0x0002c00010147984 */
/* 0x000ea40000000800 */
/*0460*/ FFMA R4, R25, R6, R4 ; /* 0x0000000619047223 */
/* 0x000fc40000000004 */
/*0470*/ LDS R25, [R16+0x300] ; /* 0x0003000010197984 */
/* 0x000fe40000000800 */
/*0480*/ FFMA R26, R22, R7, R4 ; /* 0x00000007161a7223 */
/* 0x000fe40000000004 */
/*0490*/ LDS.128 R4, [R17+0x30] ; /* 0x0000300011047984 */
/* 0x000ee80000000c00 */
/*04a0*/ LDS R22, [R16+0x340] ; /* 0x0003400010167984 */
/* 0x000f220000000800 */
/*04b0*/ FFMA R26, R21, R8, R26 ; /* 0x00000008151a7223 */
/* 0x001fc6000000001a */
/*04c0*/ LDS R21, [R16+0x380] ; /* 0x0003800010157984 */
/* 0x000e220000000800 */
/*04d0*/ FFMA R9, R24, R9, R26 ; /* 0x0000000918097223 */
/* 0x000fc6000000001a */
/*04e0*/ LDS R8, [R16+0x3c0] ; /* 0x0003c00010087984 */
/* 0x000f620000000800 */
/*04f0*/ FFMA R9, R23, R10, R9 ; /* 0x0000000a17097223 */
/* 0x002fc80000000009 */
/*0500*/ FFMA R9, R20, R11, R9 ; /* 0x0000000b14097223 */
/* 0x004fc80000000009 */
/*0510*/ FFMA R4, R25, R4, R9 ; /* 0x0000000419047223 */
/* 0x008fc80000000009 */
/*0520*/ FFMA R4, R22, R5, R4 ; /* 0x0000000516047223 */
/* 0x010fe20000000004 */
/*0530*/ HFMA2.MMA R5, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff057435 */
/* 0x000fd400000001ff */
/*0540*/ IMAD R12, R5, c[0x0][0x184], R12 ; /* 0x00006100050c7a24 */
/* 0x000fe400078e020c */
/*0550*/ FFMA R21, R21, R6, R4 ; /* 0x0000000615157223 */
/* 0x001fc80000000004 */
/*0560*/ FFMA R21, R8, R7, R21 ; /* 0x0000000708157223 */
/* 0x020fe20000000015 */
/*0570*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0580*/ @!P1 BRA 0x1c0 ; /* 0xfffffc3000009947 */
/* 0x000fea000383ffff */
/*0590*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*05a0*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*05b0*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x000fc800078e0200 */
/*05c0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*05d0*/ LDG.E R0, [R2.64] ; /* 0x0000000602007981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ FMUL R0, R0, c[0x0][0x18c] ; /* 0x0000630000007a20 */
/* 0x004fc80000400000 */
/*05f0*/ FFMA R21, R21, c[0x0][0x188], R0 ; /* 0x0000620015157a23 */
/* 0x000fca0000000000 */
/*0600*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101906 */
/*0610*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0620*/ BRA 0x620; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0680*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0690*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z5sgemmILi16EEvPKfS1_Pfiiiiff,"axG",@progbits,_Z5sgemmILi16EEvPKfS1_Pfiiiiff,comdat
.protected _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.globl _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.p2align 8
.type _Z5sgemmILi16EEvPKfS1_Pfiiiiff,@function
_Z5sgemmILi16EEvPKfS1_Pfiiiiff:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[8:9], s[0:1], 0x18
s_load_b32 s10, s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v5, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
s_mul_i32 s14, s14, s2
s_cmp_lt_i32 s10, 1
v_add_nc_u32_e32 v1, s14, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s8, v0
v_cmp_gt_i32_e64 s2, s9, v1
s_cbranch_scc1 .LBB0_15
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s15, s[0:1], 0x24
v_dual_mov_b32 v42, 0 :: v_dual_lshlrev_b32 v3, 2, v5
v_dual_mov_b32 v21, 0 :: v_dual_lshlrev_b32 v6, 6, v2
v_mul_lo_u32 v9, v0, s10
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v7, 0x400, v3
s_add_i32 s3, s10, 15
v_cmp_le_i32_e64 s11, s8, v0
v_add_nc_u32_e32 v8, v6, v3
v_cmp_le_i32_e64 s12, s9, v1
v_add_nc_u32_e32 v10, v7, v6
v_or_b32_e32 v11, 4, v6
v_add_nc_u32_e32 v12, 0x440, v3
v_or_b32_e32 v13, 8, v6
v_add_nc_u32_e32 v14, 0x480, v3
v_or_b32_e32 v15, 12, v6
v_add_nc_u32_e32 v16, 0x4c0, v3
v_or_b32_e32 v17, 16, v6
v_add_nc_u32_e32 v18, 0x500, v3
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v2, s15
v_or_b32_e32 v19, 20, v6
v_add_nc_u32_e32 v20, 0x540, v3
v_or_b32_e32 v22, 24, v6
v_add_nc_u32_e32 v23, 0x580, v3
v_or_b32_e32 v24, 28, v6
v_add_nc_u32_e32 v25, 0x5c0, v3
v_or_b32_e32 v26, 32, v6
v_add_nc_u32_e32 v27, 0x600, v3
v_or_b32_e32 v28, 36, v6
v_add_nc_u32_e32 v29, 0x640, v3
v_or_b32_e32 v30, 40, v6
v_add_nc_u32_e32 v31, 0x680, v3
v_or_b32_e32 v32, 44, v6
v_add_nc_u32_e32 v33, 0x6c0, v3
v_or_b32_e32 v34, 48, v6
v_add_nc_u32_e32 v35, 0x700, v3
v_or_b32_e32 v36, 52, v6
v_add_nc_u32_e32 v37, 0x740, v3
v_or_b32_e32 v38, 56, v6
v_add_nc_u32_e32 v39, 0x780, v3
v_or_b32_e32 v40, 60, v6
v_add_nc_u32_e32 v41, 0x7c0, v3
v_add3_u32 v3, v5, v4, s14
s_lshr_b32 s3, s3, 4
s_lshl_b32 s14, s15, 4
s_max_i32 s13, s3, 1
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v4, v6
ds_load_b32 v43, v7
ds_load_b32 v44, v11
ds_load_b32 v45, v12
ds_load_b32 v46, v13
ds_load_b32 v47, v14
ds_load_b32 v48, v15
ds_load_b32 v49, v16
v_add_nc_u32_e32 v5, 16, v5
v_add_nc_u32_e32 v3, s14, v3
s_add_i32 s13, s13, -1
v_add_nc_u32_e32 v2, 16, v2
s_cmp_eq_u32 s13, 0
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v4, v43
ds_load_b32 v4, v17
ds_load_b32 v43, v18
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v44, v45
ds_load_b32 v44, v19
ds_load_b32 v45, v20
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v46, v47
ds_load_b32 v46, v22
ds_load_b32 v47, v23
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v48, v49
ds_load_b32 v48, v24
ds_load_b32 v49, v25
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v4, v43
ds_load_b32 v4, v26
ds_load_b32 v43, v27
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v44, v45
ds_load_b32 v44, v28
ds_load_b32 v45, v29
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v46, v47
ds_load_b32 v46, v30
ds_load_b32 v47, v31
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v48, v49
ds_load_b32 v48, v32
ds_load_b32 v49, v33
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v4, v43
ds_load_b32 v4, v34
ds_load_b32 v43, v35
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v44, v45
ds_load_b32 v44, v36
ds_load_b32 v45, v37
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v21, v46, v47
ds_load_b32 v46, v38
ds_load_b32 v47, v39
ds_load_b32 v50, v40
ds_load_b32 v51, v41
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v21, v48, v49
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v21, v4, v43
v_fmac_f32_e32 v21, v44, v45
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v21, v46, v47
v_fmac_f32_e32 v21, v50, v51
s_cbranch_scc1 .LBB0_16
.LBB0_3:
s_mov_b32 s3, s11
s_mov_b32 s15, 0
s_and_saveexec_b32 s16, vcc_lo
v_cmp_le_i32_e64 s3, s10, v5
s_and_not1_b32 s17, s11, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, exec_lo
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_7
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v8, v42
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_9
v_add_nc_u32_e32 v43, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v44, 31, v43
v_lshlrev_b64 v[43:44], 2, v[43:44]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v43, s3, s4, v43
v_add_co_ci_u32_e64 v44, s3, s5, v44, s3
global_load_b32 v4, v[43:44], off
s_waitcnt vmcnt(0)
ds_store_b32 v8, v4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s16
s_mov_b32 s15, 0
s_mov_b32 s3, s12
s_and_saveexec_b32 s16, s2
v_cmp_le_i32_e64 s3, s10, v2
s_and_not1_b32 s17, s12, exec_lo
s_mov_b32 s15, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, exec_lo
s_or_b32 s3, s17, s3
s_or_b32 exec_lo, exec_lo, s16
s_and_saveexec_b32 s16, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s3, exec_lo, s16
s_cbranch_execz .LBB0_13
s_and_not1_b32 s15, s15, exec_lo
ds_store_b32 v10, v42
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s3
s_and_saveexec_b32 s16, s15
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[43:44], 2, v[3:4]
v_add_co_u32 v43, s3, s6, v43
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v44, s3, s7, v44, s3
global_load_b32 v4, v[43:44], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v4
s_branch .LBB0_2
.LBB0_15:
v_mov_b32_e32 v21, 0
.LBB0_16:
v_cmp_gt_i32_e32 vcc_lo, s9, v1
v_cmp_gt_i32_e64 s2, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, vcc_lo
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_18
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, s9, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x28
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, s1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v2, s0, v21
global_store_b32 v[0:1], v2, off
.LBB0_18:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 52
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z5sgemmILi16EEvPKfS1_Pfiiiiff,"axG",@progbits,_Z5sgemmILi16EEvPKfS1_Pfiiiiff,comdat
.Lfunc_end0:
.size _Z5sgemmILi16EEvPKfS1_Pfiiiiff, .Lfunc_end0-_Z5sgemmILi16EEvPKfS1_Pfiiiiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5sgemmILi16EEvPKfS1_Pfiiiiff
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z5sgemmILi16EEvPKfS1_Pfiiiiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 52
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void kernelUpdateNablaW(float *nabla_w,float *delta_nabla_w,int tws) {
if ((blockIdx.x*blockDim.x+threadIdx.x)<tws) {
nabla_w[blockIdx.x*blockDim.x+threadIdx.x]+=delta_nabla_w[blockIdx.x*blockDim.x+threadIdx.x];
}
}
|
code for sm_80
Function : _Z18kernelUpdateNablaWPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0005 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void kernelUpdateNablaW(float *nabla_w,float *delta_nabla_w,int tws) {
if ((blockIdx.x*blockDim.x+threadIdx.x)<tws) {
nabla_w[blockIdx.x*blockDim.x+threadIdx.x]+=delta_nabla_w[blockIdx.x*blockDim.x+threadIdx.x];
}
}
|
.file "tmpxft_00041faf_00000000-6_kernelUpdateNablaW.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i
.type _Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i, @function
_Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernelUpdateNablaWPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i, .-_Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i
.globl _Z18kernelUpdateNablaWPfS_i
.type _Z18kernelUpdateNablaWPfS_i, @function
_Z18kernelUpdateNablaWPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernelUpdateNablaWPfS_i, .-_Z18kernelUpdateNablaWPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernelUpdateNablaWPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernelUpdateNablaWPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void kernelUpdateNablaW(float *nabla_w,float *delta_nabla_w,int tws) {
if ((blockIdx.x*blockDim.x+threadIdx.x)<tws) {
nabla_w[blockIdx.x*blockDim.x+threadIdx.x]+=delta_nabla_w[blockIdx.x*blockDim.x+threadIdx.x];
}
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelUpdateNablaW(float *nabla_w,float *delta_nabla_w,int tws) {
if ((blockIdx.x*blockDim.x+threadIdx.x)<tws) {
nabla_w[blockIdx.x*blockDim.x+threadIdx.x]+=delta_nabla_w[blockIdx.x*blockDim.x+threadIdx.x];
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelUpdateNablaW(float *nabla_w,float *delta_nabla_w,int tws) {
if ((blockIdx.x*blockDim.x+threadIdx.x)<tws) {
nabla_w[blockIdx.x*blockDim.x+threadIdx.x]+=delta_nabla_w[blockIdx.x*blockDim.x+threadIdx.x];
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernelUpdateNablaWPfS_i
.globl _Z18kernelUpdateNablaWPfS_i
.p2align 8
.type _Z18kernelUpdateNablaWPfS_i,@function
_Z18kernelUpdateNablaWPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernelUpdateNablaWPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernelUpdateNablaWPfS_i, .Lfunc_end0-_Z18kernelUpdateNablaWPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernelUpdateNablaWPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernelUpdateNablaWPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernelUpdateNablaW(float *nabla_w,float *delta_nabla_w,int tws) {
if ((blockIdx.x*blockDim.x+threadIdx.x)<tws) {
nabla_w[blockIdx.x*blockDim.x+threadIdx.x]+=delta_nabla_w[blockIdx.x*blockDim.x+threadIdx.x];
}
}
|
.text
.file "kernelUpdateNablaW.hip"
.globl _Z33__device_stub__kernelUpdateNablaWPfS_i # -- Begin function _Z33__device_stub__kernelUpdateNablaWPfS_i
.p2align 4, 0x90
.type _Z33__device_stub__kernelUpdateNablaWPfS_i,@function
_Z33__device_stub__kernelUpdateNablaWPfS_i: # @_Z33__device_stub__kernelUpdateNablaWPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernelUpdateNablaWPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__kernelUpdateNablaWPfS_i, .Lfunc_end0-_Z33__device_stub__kernelUpdateNablaWPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernelUpdateNablaWPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernelUpdateNablaWPfS_i,@object # @_Z18kernelUpdateNablaWPfS_i
.section .rodata,"a",@progbits
.globl _Z18kernelUpdateNablaWPfS_i
.p2align 3, 0x0
_Z18kernelUpdateNablaWPfS_i:
.quad _Z33__device_stub__kernelUpdateNablaWPfS_i
.size _Z18kernelUpdateNablaWPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernelUpdateNablaWPfS_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernelUpdateNablaWPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernelUpdateNablaWPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z18kernelUpdateNablaWPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R4, c[0x0][0x0], R3 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fc800078e0005 */
/*0090*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0005 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*00c0*/ FADD R7, R0, R3 ; /* 0x0000000300077221 */
/* 0x004fca0000000000 */
/*00d0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernelUpdateNablaWPfS_i
.globl _Z18kernelUpdateNablaWPfS_i
.p2align 8
.type _Z18kernelUpdateNablaWPfS_i,@function
_Z18kernelUpdateNablaWPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernelUpdateNablaWPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernelUpdateNablaWPfS_i, .Lfunc_end0-_Z18kernelUpdateNablaWPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernelUpdateNablaWPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernelUpdateNablaWPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00041faf_00000000-6_kernelUpdateNablaW.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i
.type _Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i, @function
_Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernelUpdateNablaWPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i, .-_Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i
.globl _Z18kernelUpdateNablaWPfS_i
.type _Z18kernelUpdateNablaWPfS_i, @function
_Z18kernelUpdateNablaWPfS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18kernelUpdateNablaWPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernelUpdateNablaWPfS_i, .-_Z18kernelUpdateNablaWPfS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernelUpdateNablaWPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernelUpdateNablaWPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernelUpdateNablaW.hip"
.globl _Z33__device_stub__kernelUpdateNablaWPfS_i # -- Begin function _Z33__device_stub__kernelUpdateNablaWPfS_i
.p2align 4, 0x90
.type _Z33__device_stub__kernelUpdateNablaWPfS_i,@function
_Z33__device_stub__kernelUpdateNablaWPfS_i: # @_Z33__device_stub__kernelUpdateNablaWPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernelUpdateNablaWPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__kernelUpdateNablaWPfS_i, .Lfunc_end0-_Z33__device_stub__kernelUpdateNablaWPfS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernelUpdateNablaWPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernelUpdateNablaWPfS_i,@object # @_Z18kernelUpdateNablaWPfS_i
.section .rodata,"a",@progbits
.globl _Z18kernelUpdateNablaWPfS_i
.p2align 3, 0x0
_Z18kernelUpdateNablaWPfS_i:
.quad _Z33__device_stub__kernelUpdateNablaWPfS_i
.size _Z18kernelUpdateNablaWPfS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernelUpdateNablaWPfS_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernelUpdateNablaWPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernelUpdateNablaWPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#define SIZE (1024*1024)
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
__host__ int main()
{
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
}
float* devVec1;
float* devVec2;
float* devVec3;
cudaEvent_t start, stop;
cudaMalloc((void**)&devVec1, sizeof(float) * SIZE);
cudaMalloc((void**)&devVec2, sizeof(float) * SIZE);
cudaMalloc((void**)&devVec3, sizeof(float) * SIZE);
cudaMemcpy(devVec1, vec1, sizeof(float) * SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(devVec2, vec2, sizeof(float) * SIZE, cudaMemcpyHostToDevice);
int block = 512;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
addVector<<<SIZE/512, block>>>(devVec1, devVec2, devVec3);
cudaEventRecord(stop);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(vec3, devVec3, sizeof(float) * SIZE, cudaMemcpyDeviceToHost);
float time = 0;
// for (int i = 0; i < SIZE; i++)
// printf("Element #%i: %.1f\n", i , vec3[i]);
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time: %f\n", time);
FILE *f = fopen("time.txt", "a+");
if (f == NULL) {
fprintf(stderr, "FILE ERROR!\n");
} else {
fprintf(f, "%f 512\n", time);
}
fclose(f);
cudaEventDestroy(syncEvent);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(devVec1);
cudaFree(devVec2);
cudaFree(devVec3);
return EXIT_SUCCESS;
}
|
code for sm_80
Function : _Z9addVectorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#define SIZE (1024*1024)
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
__host__ int main()
{
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
}
float* devVec1;
float* devVec2;
float* devVec3;
cudaEvent_t start, stop;
cudaMalloc((void**)&devVec1, sizeof(float) * SIZE);
cudaMalloc((void**)&devVec2, sizeof(float) * SIZE);
cudaMalloc((void**)&devVec3, sizeof(float) * SIZE);
cudaMemcpy(devVec1, vec1, sizeof(float) * SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(devVec2, vec2, sizeof(float) * SIZE, cudaMemcpyHostToDevice);
int block = 512;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
addVector<<<SIZE/512, block>>>(devVec1, devVec2, devVec3);
cudaEventRecord(stop);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(vec3, devVec3, sizeof(float) * SIZE, cudaMemcpyDeviceToHost);
float time = 0;
// for (int i = 0; i < SIZE; i++)
// printf("Element #%i: %.1f\n", i , vec3[i]);
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time: %f\n", time);
FILE *f = fopen("time.txt", "a+");
if (f == NULL) {
fprintf(stderr, "FILE ERROR!\n");
} else {
fprintf(f, "%f 512\n", time);
}
fclose(f);
cudaEventDestroy(syncEvent);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(devVec1);
cudaFree(devVec2);
cudaFree(devVec3);
return EXIT_SUCCESS;
}
|
.file "tmpxft_000d3fda_00000000-6_cudaVectorAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.type _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, @function
_Z32__device_stub__Z9addVectorPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, .-_Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.globl _Z9addVectorPfS_S_
.type _Z9addVectorPfS_S_, @function
_Z9addVectorPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addVectorPfS_S_, .-_Z9addVectorPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Elapsed time: %f\n"
.LC2:
.string "a+"
.LC3:
.string "time.txt"
.LC4:
.string "FILE ERROR!\n"
.LC5:
.string "%f 512\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L12
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $512, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $2048, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L20
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L15:
movq %rbx, %rdi
call fclose@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
jmp .L13
.L20:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9addVectorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#define SIZE (1024*1024)
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
__host__ int main()
{
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
}
float* devVec1;
float* devVec2;
float* devVec3;
cudaEvent_t start, stop;
cudaMalloc((void**)&devVec1, sizeof(float) * SIZE);
cudaMalloc((void**)&devVec2, sizeof(float) * SIZE);
cudaMalloc((void**)&devVec3, sizeof(float) * SIZE);
cudaMemcpy(devVec1, vec1, sizeof(float) * SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(devVec2, vec2, sizeof(float) * SIZE, cudaMemcpyHostToDevice);
int block = 512;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start);
addVector<<<SIZE/512, block>>>(devVec1, devVec2, devVec3);
cudaEventRecord(stop);
cudaEvent_t syncEvent;
cudaEventCreate(&syncEvent);
cudaEventRecord(syncEvent, 0);
cudaEventSynchronize(syncEvent);
cudaMemcpy(vec3, devVec3, sizeof(float) * SIZE, cudaMemcpyDeviceToHost);
float time = 0;
// for (int i = 0; i < SIZE; i++)
// printf("Element #%i: %.1f\n", i , vec3[i]);
cudaEventElapsedTime(&time, start, stop);
printf("Elapsed time: %f\n", time);
FILE *f = fopen("time.txt", "a+");
if (f == NULL) {
fprintf(stderr, "FILE ERROR!\n");
} else {
fprintf(f, "%f 512\n", time);
}
fclose(f);
cudaEventDestroy(syncEvent);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaFree(devVec1);
cudaFree(devVec2);
cudaFree(devVec3);
return EXIT_SUCCESS;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE (1024*1024)
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
__host__ int main()
{
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
}
float* devVec1;
float* devVec2;
float* devVec3;
hipEvent_t start, stop;
hipMalloc((void**)&devVec1, sizeof(float) * SIZE);
hipMalloc((void**)&devVec2, sizeof(float) * SIZE);
hipMalloc((void**)&devVec3, sizeof(float) * SIZE);
hipMemcpy(devVec1, vec1, sizeof(float) * SIZE, hipMemcpyHostToDevice);
hipMemcpy(devVec2, vec2, sizeof(float) * SIZE, hipMemcpyHostToDevice);
int block = 512;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
addVector<<<SIZE/512, block>>>(devVec1, devVec2, devVec3);
hipEventRecord(stop);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(vec3, devVec3, sizeof(float) * SIZE, hipMemcpyDeviceToHost);
float time = 0;
// for (int i = 0; i < SIZE; i++)
// printf("Element #%i: %.1f\n", i , vec3[i]);
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time: %f\n", time);
FILE *f = fopen("time.txt", "a+");
if (f == NULL) {
fprintf(stderr, "FILE ERROR!\n");
} else {
fprintf(f, "%f 512\n", time);
}
fclose(f);
hipEventDestroy(syncEvent);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(devVec1);
hipFree(devVec2);
hipFree(devVec3);
return EXIT_SUCCESS;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE (1024*1024)
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
__host__ int main()
{
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
}
float* devVec1;
float* devVec2;
float* devVec3;
hipEvent_t start, stop;
hipMalloc((void**)&devVec1, sizeof(float) * SIZE);
hipMalloc((void**)&devVec2, sizeof(float) * SIZE);
hipMalloc((void**)&devVec3, sizeof(float) * SIZE);
hipMemcpy(devVec1, vec1, sizeof(float) * SIZE, hipMemcpyHostToDevice);
hipMemcpy(devVec2, vec2, sizeof(float) * SIZE, hipMemcpyHostToDevice);
int block = 512;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
addVector<<<SIZE/512, block>>>(devVec1, devVec2, devVec3);
hipEventRecord(stop);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(vec3, devVec3, sizeof(float) * SIZE, hipMemcpyDeviceToHost);
float time = 0;
// for (int i = 0; i < SIZE; i++)
// printf("Element #%i: %.1f\n", i , vec3[i]);
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time: %f\n", time);
FILE *f = fopen("time.txt", "a+");
if (f == NULL) {
fprintf(stderr, "FILE ERROR!\n");
} else {
fprintf(f, "%f 512\n", time);
}
fclose(f);
hipEventDestroy(syncEvent);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(devVec1);
hipFree(devVec2);
hipFree(devVec3);
return EXIT_SUCCESS;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPfS_S_
.globl _Z9addVectorPfS_S_
.p2align 8
.type _Z9addVectorPfS_S_,@function
_Z9addVectorPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPfS_S_, .Lfunc_end0-_Z9addVectorPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addVectorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#define SIZE (1024*1024)
__global__ void addVector(float* left, float* right, float* result)
{
int idx = threadIdx.x;
result[idx] = left[idx] + right[idx];
}
__host__ int main()
{
float* vec1 = new float[SIZE];
float* vec2 = new float[SIZE];
float* vec3 = new float[SIZE];
for (int i = 0; i < SIZE; i++)
{
vec1[i] = i;
vec2[i] = i;
}
float* devVec1;
float* devVec2;
float* devVec3;
hipEvent_t start, stop;
hipMalloc((void**)&devVec1, sizeof(float) * SIZE);
hipMalloc((void**)&devVec2, sizeof(float) * SIZE);
hipMalloc((void**)&devVec3, sizeof(float) * SIZE);
hipMemcpy(devVec1, vec1, sizeof(float) * SIZE, hipMemcpyHostToDevice);
hipMemcpy(devVec2, vec2, sizeof(float) * SIZE, hipMemcpyHostToDevice);
int block = 512;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start);
addVector<<<SIZE/512, block>>>(devVec1, devVec2, devVec3);
hipEventRecord(stop);
hipEvent_t syncEvent;
hipEventCreate(&syncEvent);
hipEventRecord(syncEvent, 0);
hipEventSynchronize(syncEvent);
hipMemcpy(vec3, devVec3, sizeof(float) * SIZE, hipMemcpyDeviceToHost);
float time = 0;
// for (int i = 0; i < SIZE; i++)
// printf("Element #%i: %.1f\n", i , vec3[i]);
hipEventElapsedTime(&time, start, stop);
printf("Elapsed time: %f\n", time);
FILE *f = fopen("time.txt", "a+");
if (f == NULL) {
fprintf(stderr, "FILE ERROR!\n");
} else {
fprintf(f, "%f 512\n", time);
}
fclose(f);
hipEventDestroy(syncEvent);
hipEventDestroy(start);
hipEventDestroy(stop);
hipFree(devVec1);
hipFree(devVec2);
hipFree(devVec3);
return EXIT_SUCCESS;
}
|
.text
.file "cudaVectorAddition.hip"
.globl _Z24__device_stub__addVectorPfS_S_ # -- Begin function _Z24__device_stub__addVectorPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPfS_S_,@function
_Z24__device_stub__addVectorPfS_S_: # @_Z24__device_stub__addVectorPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addVectorPfS_S_, .Lfunc_end0-_Z24__device_stub__addVectorPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 56(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 56(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 1536(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addVectorPfS_S_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 64(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
je .LBB1_5
# %bb.6:
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
.LBB1_7:
movq %rbx, %rdi
callq fclose
movq 64(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $12, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB1_7
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPfS_S_,@object # @_Z9addVectorPfS_S_
.section .rodata,"a",@progbits
.globl _Z9addVectorPfS_S_
.p2align 3, 0x0
_Z9addVectorPfS_S_:
.quad _Z24__device_stub__addVectorPfS_S_
.size _Z9addVectorPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %f\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "time.txt"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "a+"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FILE ERROR!\n"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f 512\n"
.size .L.str.4, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addVectorPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9addVectorPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addVectorPfS_S_
.globl _Z9addVectorPfS_S_
.p2align 8
.type _Z9addVectorPfS_S_,@function
_Z9addVectorPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addVectorPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addVectorPfS_S_, .Lfunc_end0-_Z9addVectorPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addVectorPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9addVectorPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_000d3fda_00000000-6_cudaVectorAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.type _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, @function
_Z32__device_stub__Z9addVectorPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addVectorPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z9addVectorPfS_S_PfS_S_, .-_Z32__device_stub__Z9addVectorPfS_S_PfS_S_
.globl _Z9addVectorPfS_S_
.type _Z9addVectorPfS_S_, @function
_Z9addVectorPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9addVectorPfS_S_, .-_Z9addVectorPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Elapsed time: %f\n"
.LC2:
.string "a+"
.LC3:
.string "time.txt"
.LC4:
.string "FILE ERROR!\n"
.LC5:
.string "%f 512\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbp
movl $4194304, %edi
call _Znam@PLT
movq %rax, %rbx
movl $4194304, %edi
call _Znam@PLT
movq %rax, %r12
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $1048576, %rax
jne .L12
movq %rsp, %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $512, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $2048, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $2, %ecx
movl $4194304, %edx
movq 16(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbx
testq %rax, %rax
je .L20
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rax, %rdi
movl $1, %eax
call __fprintf_chk@PLT
.L15:
movq %rbx, %rdi
call fclose@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z32__device_stub__Z9addVectorPfS_S_PfS_S_
jmp .L13
.L20:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L15
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9addVectorPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addVectorPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "cudaVectorAddition.hip"
.globl _Z24__device_stub__addVectorPfS_S_ # -- Begin function _Z24__device_stub__addVectorPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__addVectorPfS_S_,@function
_Z24__device_stub__addVectorPfS_S_: # @_Z24__device_stub__addVectorPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addVectorPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__addVectorPfS_S_, .Lfunc_end0-_Z24__device_stub__addVectorPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r15
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq _Znam
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
leaq 56(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 48(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq 56(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 32(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movq 32(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967808, %rdx # imm = 0x100000200
leaq 1536(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 120(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addVectorPfS_S_, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 64(%rsp), %rdi
callq hipEventCreate
movq 64(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 64(%rsp), %rdi
callq hipEventSynchronize
movq 40(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $0, 8(%rsp)
movq 32(%rsp), %rsi
movq 24(%rsp), %rdx
leaq 8(%rsp), %rdi
callq hipEventElapsedTime
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movl $.L.str.1, %edi
movl $.L.str.2, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
je .LBB1_5
# %bb.6:
movss 8(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %esi
movq %rbx, %rdi
movb $1, %al
callq fprintf
.LBB1_7:
movq %rbx, %rdi
callq fclose
movq 64(%rsp), %rdi
callq hipEventDestroy
movq 32(%rsp), %rdi
callq hipEventDestroy
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 56(%rsp), %rdi
callq hipFree
movq 48(%rsp), %rdi
callq hipFree
movq 40(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_5:
.cfi_def_cfa_offset 176
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $12, %esi
movl $1, %edx
callq fwrite@PLT
jmp .LBB1_7
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addVectorPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addVectorPfS_S_,@object # @_Z9addVectorPfS_S_
.section .rodata,"a",@progbits
.globl _Z9addVectorPfS_S_
.p2align 3, 0x0
_Z9addVectorPfS_S_:
.quad _Z24__device_stub__addVectorPfS_S_
.size _Z9addVectorPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Elapsed time: %f\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "time.txt"
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "a+"
.size .L.str.2, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FILE ERROR!\n"
.size .L.str.3, 13
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%f 512\n"
.size .L.str.4, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addVectorPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addVectorPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addVectorPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define XSIZE 1024
#define YSIZE 1024
#define ITERATION 100
#define NUMBER(n,i,j) (((n)&0x1? XSIZE*YSIZE :0) + (i)*YSIZE + (j))
void debug_print( float* u ){
int i,j;
for( i=0 ; i<XSIZE ; ++i ){
for( j=0 ; j<YSIZE ; ++j ){
printf("%.1e ",u[NUMBER(0,i,j)]);
}
printf("\n");
}
return ;
}
__global__ void iter(float *u,float r,int n){
int i = blockIdx.x+1;
int j = threadIdx.x+1;
u[NUMBER(n+1,i,j)]
= (1.0-4.0*r)*u[NUMBER(n,i,j)]
+ r*(u[NUMBER(n,i+1,j)]+u[NUMBER(n,i-1,j)]+u[NUMBER(n,i,j+1)]+u[NUMBER(n,i,j-1)]);
return ;
}
int main(){
int array_size = 2 * XSIZE * YSIZE * sizeof(float) ;
float r = 0.05;
float* u = (float*)malloc(array_size);
int i,j,n;
// initialize
for( i = 0 ; i < XSIZE ; ++i ){
for( j = 0 ; j < YSIZE ; ++j ){
u[NUMBER(0,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
u[NUMBER(1,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
}
}
// malloc in device
float *device_u;
cudaMalloc((void**)&device_u,array_size);
// copy to device
cudaMemcpy(device_u,u,array_size,cudaMemcpyHostToDevice);
// get time
struct timeval t_begin,t_end;
gettimeofday(&t_begin,NULL);
for( n = 0 ; n < ITERATION ; ++n )
iter<<<XSIZE-2,YSIZE-2>>>(device_u,r,n);
// print time
cudaThreadSynchronize();
gettimeofday(&t_end,NULL);
double elapsed = (double)(t_end.tv_sec-t_begin.tv_sec) + (double)(t_end.tv_usec-t_begin.tv_usec) / (1000.0*1000.0);
printf("Elapsed time = %lf(sec)\n", elapsed );
printf("FLOPS = %g\n" , 6.0*ITERATION*(XSIZE-2)*(YSIZE-2)/elapsed );
// copy from device
cudaMemcpy(u,device_u,array_size,cudaMemcpyDeviceToHost);
// debug_print(u);
return 0;
}
|
code for sm_80
Function : _Z4iterPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e640000002100 */
/*0060*/ IMAD.SHL.U32 R5, R5, 0x100000, RZ ; /* 0x0010000005057824 */
/* 0x000fca00078e00ff */
/*0070*/ LOP3.LUT R5, R5, 0x100000, RZ, 0xc0, !PT ; /* 0x0010000005057812 */
/* 0x000fc800078ec0ff */
/*0080*/ LEA R3, R6, R5, 0xa ; /* 0x0000000506037211 */
/* 0x001fc800078e50ff */
/*0090*/ IADD3 R3, R3, R4, RZ ; /* 0x0000000403037210 */
/* 0x002fca0007ffe0ff */
/*00a0*/ IMAD.WIDE R8, R3, R0, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fca00078e0200 */
/*00b0*/ LDG.E R7, [R8.64+0x2004] ; /* 0x0020040408077981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R12, [R8.64+0x4] ; /* 0x00000404080c7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R14, [R8.64+0x1008] ; /* 0x00100804080e7981 */
/* 0x000ee8000c1e1900 */
/*00e0*/ LDG.E R16, [R8.64+0x1000] ; /* 0x0010000408107981 */
/* 0x000f28000c1e1900 */
/*00f0*/ LDG.E R10, [R8.64+0x1004] ; /* 0x00100404080a7981 */
/* 0x000f62000c1e1900 */
/*0100*/ F2F.F64.F32 R2, c[0x0][0x168] ; /* 0x00005a0000027b10 */
/* 0x000e220000201800 */
/*0110*/ HFMA2.MMA R15, -RZ, RZ, 2.03125, 0 ; /* 0x40100000ff0f7435 */
/* 0x000fe200000001ff */
/*0120*/ LEA R4, R6, R4, 0xa ; /* 0x0000000406047211 */
/* 0x000fc400078e50ff */
/*0130*/ LOP3.LUT R5, R5, 0x100000, RZ, 0x3c, !PT ; /* 0x0010000005057812 */
/* 0x000fc800078e3cff */
/*0140*/ IADD3 R5, R4, 0x401, R5 ; /* 0x0000040104057810 */
/* 0x000fca0007ffe005 */
/*0150*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0200 */
/*0160*/ FADD R7, R7, R12 ; /* 0x0000000c07077221 */
/* 0x004fc80000000000 */
/*0170*/ FADD R7, R7, R14 ; /* 0x0000000e07077221 */
/* 0x008fc80000000000 */
/*0180*/ FADD R7, R7, R16 ; /* 0x0000001007077221 */
/* 0x010fc80000000000 */
/*0190*/ FMUL R7, R7, c[0x0][0x168] ; /* 0x00005a0007077a20 */
/* 0x000fe20000400000 */
/*01a0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x020fe20000201800 */
/*01b0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fce00078e00ff */
/*01c0*/ F2F.F64.F32 R12, R7 ; /* 0x00000007000c7310 */
/* 0x000e620000201800 */
/*01d0*/ DFMA R2, R2, -R14, 1 ; /* 0x3ff000000202742b */
/* 0x001e4c000000080e */
/*01e0*/ DFMA R2, R2, R10, R12 ; /* 0x0000000a0202722b */
/* 0x002e14000000000c */
/*01f0*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*0200*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define XSIZE 1024
#define YSIZE 1024
#define ITERATION 100
#define NUMBER(n,i,j) (((n)&0x1? XSIZE*YSIZE :0) + (i)*YSIZE + (j))
void debug_print( float* u ){
int i,j;
for( i=0 ; i<XSIZE ; ++i ){
for( j=0 ; j<YSIZE ; ++j ){
printf("%.1e ",u[NUMBER(0,i,j)]);
}
printf("\n");
}
return ;
}
__global__ void iter(float *u,float r,int n){
int i = blockIdx.x+1;
int j = threadIdx.x+1;
u[NUMBER(n+1,i,j)]
= (1.0-4.0*r)*u[NUMBER(n,i,j)]
+ r*(u[NUMBER(n,i+1,j)]+u[NUMBER(n,i-1,j)]+u[NUMBER(n,i,j+1)]+u[NUMBER(n,i,j-1)]);
return ;
}
int main(){
int array_size = 2 * XSIZE * YSIZE * sizeof(float) ;
float r = 0.05;
float* u = (float*)malloc(array_size);
int i,j,n;
// initialize
for( i = 0 ; i < XSIZE ; ++i ){
for( j = 0 ; j < YSIZE ; ++j ){
u[NUMBER(0,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
u[NUMBER(1,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
}
}
// malloc in device
float *device_u;
cudaMalloc((void**)&device_u,array_size);
// copy to device
cudaMemcpy(device_u,u,array_size,cudaMemcpyHostToDevice);
// get time
struct timeval t_begin,t_end;
gettimeofday(&t_begin,NULL);
for( n = 0 ; n < ITERATION ; ++n )
iter<<<XSIZE-2,YSIZE-2>>>(device_u,r,n);
// print time
cudaThreadSynchronize();
gettimeofday(&t_end,NULL);
double elapsed = (double)(t_end.tv_sec-t_begin.tv_sec) + (double)(t_end.tv_usec-t_begin.tv_usec) / (1000.0*1000.0);
printf("Elapsed time = %lf(sec)\n", elapsed );
printf("FLOPS = %g\n" , 6.0*ITERATION*(XSIZE-2)*(YSIZE-2)/elapsed );
// copy from device
cudaMemcpy(u,device_u,array_size,cudaMemcpyDeviceToHost);
// debug_print(u);
return 0;
}
|
.file "tmpxft_00045538_00000000-6_gpgpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.1e "
.LC1:
.string "\n"
.text
.globl _Z11debug_printPf
.type _Z11debug_printPf, @function
_Z11debug_printPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
leaq 4096(%rdi), %rbp
addq $4198400, %r13
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L4:
leaq -4096(%rbp), %rbx
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4096, %rbp
cmpq %r13, %rbp
jne .L4
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11debug_printPf, .-_Z11debug_printPf
.globl _Z25__device_stub__Z4iterPffiPffi
.type _Z25__device_stub__Z4iterPffiPffi, @function
_Z25__device_stub__Z4iterPffiPffi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4iterPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z25__device_stub__Z4iterPffiPffi, .-_Z25__device_stub__Z4iterPffiPffi
.globl _Z4iterPffi
.type _Z4iterPffi, @function
_Z4iterPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4iterPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4iterPffi, .-_Z4iterPffi
.section .rodata.str1.1
.LC5:
.string "Elapsed time = %lf(sec)\n"
.LC7:
.string "FLOPS = %g\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, %rsi
leaq 4194304(%rax), %r8
movl $0, %ecx
movss .LC8(%rip), %xmm0
jmp .L18
.L35:
addl $1, %ecx
addq $4096, %rsi
cmpq %r8, %rsi
je .L23
.L18:
movl %ecx, %edx
sall $10, %edx
movl $0, %eax
jmp .L24
.L23:
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %ebp
jmp .L26
.L25:
addl $1, %ebp
cmpl $100, %ebp
je .L33
.L26:
movl $1022, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1022, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movl %ebp, %esi
movss .LC3(%rip), %xmm0
movq 24(%rsp), %rdi
call _Z25__device_stub__Z4iterPffiPffi
jmp .L25
.L33:
call cudaThreadSynchronize@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC6(%rip), %xmm0
divsd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $8388608, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movslq %edx, %rdi
movl $0x00000000, (%rbx,%rdi,4)
.L27:
movl $0x00000000, 4194304(%rsi,%rax,4)
addq $1, %rax
addl $1, %edx
cmpq $1024, %rax
je .L35
.L24:
testl %ecx, %ecx
je .L19
cmpl $1023, %ecx
je .L19
testl %eax, %eax
je .L20
cmpl $1023, %eax
je .L20
movslq %edx, %rdi
movss %xmm0, (%rbx,%rdi,4)
movss %xmm0, 4194304(%rsi,%rax,4)
addq $1, %rax
addl $1, %edx
jmp .L24
.L20:
movslq %edx, %rdi
movl $0x00000000, (%rbx,%rdi,4)
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z4iterPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z4iterPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1028443341
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC6:
.long -1342177280
.long 1103277380
.section .rodata.cst4
.align 4
.LC8:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define XSIZE 1024
#define YSIZE 1024
#define ITERATION 100
#define NUMBER(n,i,j) (((n)&0x1? XSIZE*YSIZE :0) + (i)*YSIZE + (j))
void debug_print( float* u ){
int i,j;
for( i=0 ; i<XSIZE ; ++i ){
for( j=0 ; j<YSIZE ; ++j ){
printf("%.1e ",u[NUMBER(0,i,j)]);
}
printf("\n");
}
return ;
}
__global__ void iter(float *u,float r,int n){
int i = blockIdx.x+1;
int j = threadIdx.x+1;
u[NUMBER(n+1,i,j)]
= (1.0-4.0*r)*u[NUMBER(n,i,j)]
+ r*(u[NUMBER(n,i+1,j)]+u[NUMBER(n,i-1,j)]+u[NUMBER(n,i,j+1)]+u[NUMBER(n,i,j-1)]);
return ;
}
int main(){
int array_size = 2 * XSIZE * YSIZE * sizeof(float) ;
float r = 0.05;
float* u = (float*)malloc(array_size);
int i,j,n;
// initialize
for( i = 0 ; i < XSIZE ; ++i ){
for( j = 0 ; j < YSIZE ; ++j ){
u[NUMBER(0,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
u[NUMBER(1,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
}
}
// malloc in device
float *device_u;
cudaMalloc((void**)&device_u,array_size);
// copy to device
cudaMemcpy(device_u,u,array_size,cudaMemcpyHostToDevice);
// get time
struct timeval t_begin,t_end;
gettimeofday(&t_begin,NULL);
for( n = 0 ; n < ITERATION ; ++n )
iter<<<XSIZE-2,YSIZE-2>>>(device_u,r,n);
// print time
cudaThreadSynchronize();
gettimeofday(&t_end,NULL);
double elapsed = (double)(t_end.tv_sec-t_begin.tv_sec) + (double)(t_end.tv_usec-t_begin.tv_usec) / (1000.0*1000.0);
printf("Elapsed time = %lf(sec)\n", elapsed );
printf("FLOPS = %g\n" , 6.0*ITERATION*(XSIZE-2)*(YSIZE-2)/elapsed );
// copy from device
cudaMemcpy(u,device_u,array_size,cudaMemcpyDeviceToHost);
// debug_print(u);
return 0;
}
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define XSIZE 1024
#define YSIZE 1024
#define ITERATION 100
#define NUMBER(n,i,j) (((n)&0x1? XSIZE*YSIZE :0) + (i)*YSIZE + (j))
void debug_print( float* u ){
int i,j;
for( i=0 ; i<XSIZE ; ++i ){
for( j=0 ; j<YSIZE ; ++j ){
printf("%.1e ",u[NUMBER(0,i,j)]);
}
printf("\n");
}
return ;
}
__global__ void iter(float *u,float r,int n){
int i = blockIdx.x+1;
int j = threadIdx.x+1;
u[NUMBER(n+1,i,j)]
= (1.0-4.0*r)*u[NUMBER(n,i,j)]
+ r*(u[NUMBER(n,i+1,j)]+u[NUMBER(n,i-1,j)]+u[NUMBER(n,i,j+1)]+u[NUMBER(n,i,j-1)]);
return ;
}
int main(){
int array_size = 2 * XSIZE * YSIZE * sizeof(float) ;
float r = 0.05;
float* u = (float*)malloc(array_size);
int i,j,n;
// initialize
for( i = 0 ; i < XSIZE ; ++i ){
for( j = 0 ; j < YSIZE ; ++j ){
u[NUMBER(0,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
u[NUMBER(1,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
}
}
// malloc in device
float *device_u;
hipMalloc((void**)&device_u,array_size);
// copy to device
hipMemcpy(device_u,u,array_size,hipMemcpyHostToDevice);
// get time
struct timeval t_begin,t_end;
gettimeofday(&t_begin,NULL);
for( n = 0 ; n < ITERATION ; ++n )
iter<<<XSIZE-2,YSIZE-2>>>(device_u,r,n);
// print time
hipDeviceSynchronize();
gettimeofday(&t_end,NULL);
double elapsed = (double)(t_end.tv_sec-t_begin.tv_sec) + (double)(t_end.tv_usec-t_begin.tv_usec) / (1000.0*1000.0);
printf("Elapsed time = %lf(sec)\n", elapsed );
printf("FLOPS = %g\n" , 6.0*ITERATION*(XSIZE-2)*(YSIZE-2)/elapsed );
// copy from device
hipMemcpy(u,device_u,array_size,hipMemcpyDeviceToHost);
// debug_print(u);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define XSIZE 1024
#define YSIZE 1024
#define ITERATION 100
#define NUMBER(n,i,j) (((n)&0x1? XSIZE*YSIZE :0) + (i)*YSIZE + (j))
void debug_print( float* u ){
int i,j;
for( i=0 ; i<XSIZE ; ++i ){
for( j=0 ; j<YSIZE ; ++j ){
printf("%.1e ",u[NUMBER(0,i,j)]);
}
printf("\n");
}
return ;
}
__global__ void iter(float *u,float r,int n){
int i = blockIdx.x+1;
int j = threadIdx.x+1;
u[NUMBER(n+1,i,j)]
= (1.0-4.0*r)*u[NUMBER(n,i,j)]
+ r*(u[NUMBER(n,i+1,j)]+u[NUMBER(n,i-1,j)]+u[NUMBER(n,i,j+1)]+u[NUMBER(n,i,j-1)]);
return ;
}
int main(){
int array_size = 2 * XSIZE * YSIZE * sizeof(float) ;
float r = 0.05;
float* u = (float*)malloc(array_size);
int i,j,n;
// initialize
for( i = 0 ; i < XSIZE ; ++i ){
for( j = 0 ; j < YSIZE ; ++j ){
u[NUMBER(0,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
u[NUMBER(1,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
}
}
// malloc in device
float *device_u;
hipMalloc((void**)&device_u,array_size);
// copy to device
hipMemcpy(device_u,u,array_size,hipMemcpyHostToDevice);
// get time
struct timeval t_begin,t_end;
gettimeofday(&t_begin,NULL);
for( n = 0 ; n < ITERATION ; ++n )
iter<<<XSIZE-2,YSIZE-2>>>(device_u,r,n);
// print time
hipDeviceSynchronize();
gettimeofday(&t_end,NULL);
double elapsed = (double)(t_end.tv_sec-t_begin.tv_sec) + (double)(t_end.tv_usec-t_begin.tv_usec) / (1000.0*1000.0);
printf("Elapsed time = %lf(sec)\n", elapsed );
printf("FLOPS = %g\n" , 6.0*ITERATION*(XSIZE-2)*(YSIZE-2)/elapsed );
// copy from device
hipMemcpy(u,device_u,array_size,hipMemcpyDeviceToHost);
// debug_print(u);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4iterPffi
.globl _Z4iterPffi
.p2align 8
.type _Z4iterPffi,@function
_Z4iterPffi:
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v12, 1, v0
s_lshl_b32 s4, s15, 10
s_waitcnt lgkmcnt(0)
s_lshl_b32 s3, s3, 20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, 0x100000
v_add3_u32 v1, s3, s4, v12
s_addk_i32 s4, 0x400
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s3, s4
v_or_b32_e32 v5, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, 0x800, v1
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, 2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v9, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_add_co_u32 v0, vcc_lo, s0, v0
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v9, v[10:11], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v5, v6, v9
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v5, v4
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v4, v2 :: v_dual_add_nc_u32 v7, s5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_mul_f32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[7:8]
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v3, v[0:1], off
v_cvt_f64_f32_e32 v[0:1], s2
s_xor_b32 s2, s3, 0x100000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], -4.0, 1.0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v3
v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[0:1]
v_add3_u32 v0, s2, s4, v12
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4iterPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4iterPffi, .Lfunc_end0-_Z4iterPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4iterPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4iterPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#define XSIZE 1024
#define YSIZE 1024
#define ITERATION 100
#define NUMBER(n,i,j) (((n)&0x1? XSIZE*YSIZE :0) + (i)*YSIZE + (j))
void debug_print( float* u ){
int i,j;
for( i=0 ; i<XSIZE ; ++i ){
for( j=0 ; j<YSIZE ; ++j ){
printf("%.1e ",u[NUMBER(0,i,j)]);
}
printf("\n");
}
return ;
}
__global__ void iter(float *u,float r,int n){
int i = blockIdx.x+1;
int j = threadIdx.x+1;
u[NUMBER(n+1,i,j)]
= (1.0-4.0*r)*u[NUMBER(n,i,j)]
+ r*(u[NUMBER(n,i+1,j)]+u[NUMBER(n,i-1,j)]+u[NUMBER(n,i,j+1)]+u[NUMBER(n,i,j-1)]);
return ;
}
int main(){
int array_size = 2 * XSIZE * YSIZE * sizeof(float) ;
float r = 0.05;
float* u = (float*)malloc(array_size);
int i,j,n;
// initialize
for( i = 0 ; i < XSIZE ; ++i ){
for( j = 0 ; j < YSIZE ; ++j ){
u[NUMBER(0,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
u[NUMBER(1,i,j)] = ( i==0 || i==XSIZE-1 || j==0 || j==YSIZE-1 ? 0.0 : 1.0 );
}
}
// malloc in device
float *device_u;
hipMalloc((void**)&device_u,array_size);
// copy to device
hipMemcpy(device_u,u,array_size,hipMemcpyHostToDevice);
// get time
struct timeval t_begin,t_end;
gettimeofday(&t_begin,NULL);
for( n = 0 ; n < ITERATION ; ++n )
iter<<<XSIZE-2,YSIZE-2>>>(device_u,r,n);
// print time
hipDeviceSynchronize();
gettimeofday(&t_end,NULL);
double elapsed = (double)(t_end.tv_sec-t_begin.tv_sec) + (double)(t_end.tv_usec-t_begin.tv_usec) / (1000.0*1000.0);
printf("Elapsed time = %lf(sec)\n", elapsed );
printf("FLOPS = %g\n" , 6.0*ITERATION*(XSIZE-2)*(YSIZE-2)/elapsed );
// copy from device
hipMemcpy(u,device_u,array_size,hipMemcpyDeviceToHost);
// debug_print(u);
return 0;
}
|
.text
.file "gpgpu.hip"
.globl _Z11debug_printPf # -- Begin function _Z11debug_printPf
.p2align 4, 0x90
.type _Z11debug_printPf,@function
_Z11debug_printPf: # @_Z11debug_printPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB0_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11debug_printPf, .Lfunc_end0-_Z11debug_printPf
.cfi_endproc
# -- End function
.globl _Z19__device_stub__iterPffi # -- Begin function _Z19__device_stub__iterPffi
.p2align 4, 0x90
.type _Z19__device_stub__iterPffi,@function
_Z19__device_stub__iterPffi: # @_Z19__device_stub__iterPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4iterPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__iterPffi, .Lfunc_end1-_Z19__device_stub__iterPffi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_2:
.quad 0x41c2ad44b0000000 # double 626690400
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
addq $4194304, %rax # imm = 0x400000
xorl %ecx, %ecx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_1 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rcx # imm = 0x400
je .LBB2_16
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq $-1024, %rdx # imm = 0xFC00
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_2 Depth=2
movss %xmm1, 4096(%rax,%rdx,4)
incq %rdx
je .LBB2_15
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movb $1, %sil
cmpq $-1024, %rdx # imm = 0xFC00
je .LBB2_6
# %bb.3: # %switch.early.test
# in Loop: Header=BB2_2 Depth=2
testl %ecx, %ecx
je .LBB2_6
# %bb.4: # %switch.early.test
# in Loop: Header=BB2_2 Depth=2
cmpl $1023, %ecx # imm = 0x3FF
je .LBB2_6
# %bb.5: # in Loop: Header=BB2_2 Depth=2
cmpq $-1, %rdx
sete %sil
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=2
xorps %xmm1, %xmm1
testb %sil, %sil
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_2 Depth=2
movaps %xmm0, %xmm1
.LBB2_8: # in Loop: Header=BB2_2 Depth=2
movss %xmm1, -4190208(%rax,%rdx,4)
movb $1, %sil
cmpq $-1024, %rdx # imm = 0xFC00
je .LBB2_12
# %bb.9: # %switch.early.test40
# in Loop: Header=BB2_2 Depth=2
testl %ecx, %ecx
je .LBB2_12
# %bb.10: # %switch.early.test40
# in Loop: Header=BB2_2 Depth=2
cmpl $1023, %ecx # imm = 0x3FF
je .LBB2_12
# %bb.11: # in Loop: Header=BB2_2 Depth=2
cmpq $-1, %rdx
sete %sil
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_2 Depth=2
xorps %xmm1, %xmm1
testb %sil, %sil
jne .LBB2_14
# %bb.13: # in Loop: Header=BB2_2 Depth=2
movaps %xmm0, %xmm1
jmp .LBB2_14
.LBB2_16:
movabsq $4294968318, %r14 # imm = 0x1000003FE
movq %rsp, %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq (%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r15d, %r15d
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 80(%rsp), %r12
leaq 72(%rsp), %r13
leaq 64(%rsp), %rbp
leaq 16(%rsp), %rbx
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
incl %r15d
cmpl $100, %r15d
je .LBB2_20
.LBB2_17: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movq (%rsp), %rax
movq %rax, 112(%rsp)
movl $1028443341, 12(%rsp) # imm = 0x3D4CCCCD
movl %r15d, 8(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z4iterPffi, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_19
.LBB2_20:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 120(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 128(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI2_1(%rip), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movb $1, %al
callq printf
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4iterPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.1e "
.size .L.str, 6
.type _Z4iterPffi,@object # @_Z4iterPffi
.section .rodata,"a",@progbits
.globl _Z4iterPffi
.p2align 3, 0x0
_Z4iterPffi:
.quad _Z19__device_stub__iterPffi
.size _Z4iterPffi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Elapsed time = %lf(sec)\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FLOPS = %g\n"
.size .L.str.3, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4iterPffi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__iterPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4iterPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z4iterPffi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ MOV R5, c[0x0][0x16c] ; /* 0x00005b0000057a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e640000002100 */
/*0060*/ IMAD.SHL.U32 R5, R5, 0x100000, RZ ; /* 0x0010000005057824 */
/* 0x000fca00078e00ff */
/*0070*/ LOP3.LUT R5, R5, 0x100000, RZ, 0xc0, !PT ; /* 0x0010000005057812 */
/* 0x000fc800078ec0ff */
/*0080*/ LEA R3, R6, R5, 0xa ; /* 0x0000000506037211 */
/* 0x001fc800078e50ff */
/*0090*/ IADD3 R3, R3, R4, RZ ; /* 0x0000000403037210 */
/* 0x002fca0007ffe0ff */
/*00a0*/ IMAD.WIDE R8, R3, R0, c[0x0][0x160] ; /* 0x0000580003087625 */
/* 0x000fca00078e0200 */
/*00b0*/ LDG.E R7, [R8.64+0x2004] ; /* 0x0020040408077981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R12, [R8.64+0x4] ; /* 0x00000404080c7981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R14, [R8.64+0x1008] ; /* 0x00100804080e7981 */
/* 0x000ee8000c1e1900 */
/*00e0*/ LDG.E R16, [R8.64+0x1000] ; /* 0x0010000408107981 */
/* 0x000f28000c1e1900 */
/*00f0*/ LDG.E R10, [R8.64+0x1004] ; /* 0x00100404080a7981 */
/* 0x000f62000c1e1900 */
/*0100*/ F2F.F64.F32 R2, c[0x0][0x168] ; /* 0x00005a0000027b10 */
/* 0x000e220000201800 */
/*0110*/ HFMA2.MMA R15, -RZ, RZ, 2.03125, 0 ; /* 0x40100000ff0f7435 */
/* 0x000fe200000001ff */
/*0120*/ LEA R4, R6, R4, 0xa ; /* 0x0000000406047211 */
/* 0x000fc400078e50ff */
/*0130*/ LOP3.LUT R5, R5, 0x100000, RZ, 0x3c, !PT ; /* 0x0010000005057812 */
/* 0x000fc800078e3cff */
/*0140*/ IADD3 R5, R4, 0x401, R5 ; /* 0x0000040104057810 */
/* 0x000fca0007ffe005 */
/*0150*/ IMAD.WIDE R4, R5, R0, c[0x0][0x160] ; /* 0x0000580005047625 */
/* 0x000fc800078e0200 */
/*0160*/ FADD R7, R7, R12 ; /* 0x0000000c07077221 */
/* 0x004fc80000000000 */
/*0170*/ FADD R7, R7, R14 ; /* 0x0000000e07077221 */
/* 0x008fc80000000000 */
/*0180*/ FADD R7, R7, R16 ; /* 0x0000001007077221 */
/* 0x010fc80000000000 */
/*0190*/ FMUL R7, R7, c[0x0][0x168] ; /* 0x00005a0007077a20 */
/* 0x000fe20000400000 */
/*01a0*/ F2F.F64.F32 R10, R10 ; /* 0x0000000a000a7310 */
/* 0x020fe20000201800 */
/*01b0*/ IMAD.MOV.U32 R14, RZ, RZ, 0x0 ; /* 0x00000000ff0e7424 */
/* 0x000fce00078e00ff */
/*01c0*/ F2F.F64.F32 R12, R7 ; /* 0x00000007000c7310 */
/* 0x000e620000201800 */
/*01d0*/ DFMA R2, R2, -R14, 1 ; /* 0x3ff000000202742b */
/* 0x001e4c000000080e */
/*01e0*/ DFMA R2, R2, R10, R12 ; /* 0x0000000a0202722b */
/* 0x002e14000000000c */
/*01f0*/ F2F.F32.F64 R3, R2 ; /* 0x0000000200037310 */
/* 0x001e240000301000 */
/*0200*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x001fe2000c101904 */
/*0210*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0220*/ BRA 0x220; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4iterPffi
.globl _Z4iterPffi
.p2align 8
.type _Z4iterPffi,@function
_Z4iterPffi:
s_load_b128 s[0:3], s[0:1], 0x0
v_add_nc_u32_e32 v12, 1, v0
s_lshl_b32 s4, s15, 10
s_waitcnt lgkmcnt(0)
s_lshl_b32 s3, s3, 20
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, 0x100000
v_add3_u32 v1, s3, s4, v12
s_addk_i32 s4, 0x400
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s5, s3, s4
v_or_b32_e32 v5, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_nc_u32_e32 v3, 0x800, v1
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v0, 2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[8:9], 2, v[1:2]
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v2, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v4, vcc_lo
v_add_co_u32 v10, vcc_lo, s0, v8
v_add_co_ci_u32_e32 v11, vcc_lo, s1, v9, vcc_lo
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_add_co_u32 v0, vcc_lo, s0, v0
s_clause 0x1
global_load_b32 v6, v[2:3], off
global_load_b32 v9, v[10:11], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v5, vcc_lo
s_clause 0x1
global_load_b32 v4, v[0:1], off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(2)
v_add_f32_e32 v5, v6, v9
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v5, v4
s_waitcnt vmcnt(0)
v_dual_add_f32 v2, v4, v2 :: v_dual_add_nc_u32 v7, s5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_mul_f32_e32 v4, s2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[7:8]
v_cvt_f64_f32_e32 v[4:5], v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v3, v[0:1], off
v_cvt_f64_f32_e32 v[0:1], s2
s_xor_b32 s2, s3, 0x100000
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_fma_f64 v[0:1], v[0:1], -4.0, 1.0
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[2:3], v3
v_fma_f64 v[0:1], v[0:1], v[2:3], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_f64_e32 v2, v[0:1]
v_add3_u32 v0, s2, s4, v12
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4iterPffi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4iterPffi, .Lfunc_end0-_Z4iterPffi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4iterPffi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4iterPffi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_00045538_00000000-6_gpgpu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.1e "
.LC1:
.string "\n"
.text
.globl _Z11debug_printPf
.type _Z11debug_printPf, @function
_Z11debug_printPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r13
leaq 4096(%rdi), %rbp
addq $4198400, %r13
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r14
.L4:
leaq -4096(%rbp), %rbx
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L5
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4096, %rbp
cmpq %r13, %rbp
jne .L4
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11debug_printPf, .-_Z11debug_printPf
.globl _Z25__device_stub__Z4iterPffiPffi
.type _Z25__device_stub__Z4iterPffiPffi, @function
_Z25__device_stub__Z4iterPffiPffi:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L13
.L9:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z4iterPffi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L9
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z25__device_stub__Z4iterPffiPffi, .-_Z25__device_stub__Z4iterPffiPffi
.globl _Z4iterPffi
.type _Z4iterPffi, @function
_Z4iterPffi:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z25__device_stub__Z4iterPffiPffi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z4iterPffi, .-_Z4iterPffi
.section .rodata.str1.1
.LC5:
.string "Elapsed time = %lf(sec)\n"
.LC7:
.string "FLOPS = %g\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $104, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $8388608, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, %rsi
leaq 4194304(%rax), %r8
movl $0, %ecx
movss .LC8(%rip), %xmm0
jmp .L18
.L35:
addl $1, %ecx
addq $4096, %rsi
cmpq %r8, %rsi
je .L23
.L18:
movl %ecx, %edx
sall $10, %edx
movl $0, %eax
jmp .L24
.L23:
leaq 24(%rsp), %rdi
movl $8388608, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $8388608, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $0, %ebp
jmp .L26
.L25:
addl $1, %ebp
cmpl $100, %ebp
je .L33
.L26:
movl $1022, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1022, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movl $1, %ecx
movq 36(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L25
movl %ebp, %esi
movss .LC3(%rip), %xmm0
movq 24(%rsp), %rdi
call _Z25__device_stub__Z4iterPffiPffi
jmp .L25
.L33:
call cudaThreadSynchronize@PLT
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 72(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC4(%rip), %xmm0
movq 64(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC6(%rip), %xmm0
divsd 8(%rsp), %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movl $8388608, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L34
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movslq %edx, %rdi
movl $0x00000000, (%rbx,%rdi,4)
.L27:
movl $0x00000000, 4194304(%rsi,%rax,4)
addq $1, %rax
addl $1, %edx
cmpq $1024, %rax
je .L35
.L24:
testl %ecx, %ecx
je .L19
cmpl $1023, %ecx
je .L19
testl %eax, %eax
je .L20
cmpl $1023, %eax
je .L20
movslq %edx, %rdi
movss %xmm0, (%rbx,%rdi,4)
movss %xmm0, 4194304(%rsi,%rax,4)
addq $1, %rax
addl $1, %edx
jmp .L24
.L20:
movslq %edx, %rdi
movl $0x00000000, (%rbx,%rdi,4)
jmp .L27
.L34:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z4iterPffi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z4iterPffi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1028443341
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1093567616
.align 8
.LC6:
.long -1342177280
.long 1103277380
.section .rodata.cst4
.align 4
.LC8:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "gpgpu.hip"
.globl _Z11debug_printPf # -- Begin function _Z11debug_printPf
.p2align 4, 0x90
.type _Z11debug_printPf,@function
_Z11debug_printPf: # @_Z11debug_printPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $1024, %r15 # imm = 0x400
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $4096, %rbx # imm = 0x1000
cmpq $1024, %r14 # imm = 0x400
jne .LBB0_1
# %bb.4:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11debug_printPf, .Lfunc_end0-_Z11debug_printPf
.cfi_endproc
# -- End function
.globl _Z19__device_stub__iterPffi # -- Begin function _Z19__device_stub__iterPffi
.p2align 4, 0x90
.type _Z19__device_stub__iterPffi,@function
_Z19__device_stub__iterPffi: # @_Z19__device_stub__iterPffi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movss %xmm0, 4(%rsp)
movl %esi, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z4iterPffi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z19__device_stub__iterPffi, .Lfunc_end1-_Z19__device_stub__iterPffi
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f800000 # float 1
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_1:
.quad 0x412e848000000000 # double 1.0E+6
.LCPI2_2:
.quad 0x41c2ad44b0000000 # double 626690400
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $8388608, %edi # imm = 0x800000
callq malloc
movq %rax, %rbx
addq $4194304, %rax # imm = 0x400000
xorl %ecx, %ecx
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_15: # in Loop: Header=BB2_1 Depth=1
incq %rcx
addq $4096, %rax # imm = 0x1000
cmpq $1024, %rcx # imm = 0x400
je .LBB2_16
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
movq $-1024, %rdx # imm = 0xFC00
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_14: # in Loop: Header=BB2_2 Depth=2
movss %xmm1, 4096(%rax,%rdx,4)
incq %rdx
je .LBB2_15
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movb $1, %sil
cmpq $-1024, %rdx # imm = 0xFC00
je .LBB2_6
# %bb.3: # %switch.early.test
# in Loop: Header=BB2_2 Depth=2
testl %ecx, %ecx
je .LBB2_6
# %bb.4: # %switch.early.test
# in Loop: Header=BB2_2 Depth=2
cmpl $1023, %ecx # imm = 0x3FF
je .LBB2_6
# %bb.5: # in Loop: Header=BB2_2 Depth=2
cmpq $-1, %rdx
sete %sil
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_2 Depth=2
xorps %xmm1, %xmm1
testb %sil, %sil
jne .LBB2_8
# %bb.7: # in Loop: Header=BB2_2 Depth=2
movaps %xmm0, %xmm1
.LBB2_8: # in Loop: Header=BB2_2 Depth=2
movss %xmm1, -4190208(%rax,%rdx,4)
movb $1, %sil
cmpq $-1024, %rdx # imm = 0xFC00
je .LBB2_12
# %bb.9: # %switch.early.test40
# in Loop: Header=BB2_2 Depth=2
testl %ecx, %ecx
je .LBB2_12
# %bb.10: # %switch.early.test40
# in Loop: Header=BB2_2 Depth=2
cmpl $1023, %ecx # imm = 0x3FF
je .LBB2_12
# %bb.11: # in Loop: Header=BB2_2 Depth=2
cmpq $-1, %rdx
sete %sil
.p2align 4, 0x90
.LBB2_12: # in Loop: Header=BB2_2 Depth=2
xorps %xmm1, %xmm1
testb %sil, %sil
jne .LBB2_14
# %bb.13: # in Loop: Header=BB2_2 Depth=2
movaps %xmm0, %xmm1
jmp .LBB2_14
.LBB2_16:
movabsq $4294968318, %r14 # imm = 0x1000003FE
movq %rsp, %rdi
movl $8388608, %esi # imm = 0x800000
callq hipMalloc
movq (%rsp), %rdi
movl $8388608, %edx # imm = 0x800000
movq %rbx, 56(%rsp) # 8-byte Spill
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
xorl %r15d, %r15d
leaq 120(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 80(%rsp), %r12
leaq 72(%rsp), %r13
leaq 64(%rsp), %rbp
leaq 16(%rsp), %rbx
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_19: # in Loop: Header=BB2_17 Depth=1
incl %r15d
cmpl $100, %r15d
je .LBB2_20
.LBB2_17: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_19
# %bb.18: # in Loop: Header=BB2_17 Depth=1
movq (%rsp), %rax
movq %rax, 112(%rsp)
movl $1028443341, 12(%rsp) # imm = 0x3D4CCCCD
movl %r15d, 8(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 12(%rsp), %rax
movq %rax, 24(%rsp)
leaq 8(%rsp), %rax
movq %rax, 32(%rsp)
leaq 96(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movq %rbp, %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
movl $_Z4iterPffi, %edi
movq %rbx, %r9
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB2_19
.LBB2_20:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 120(%rsp), %rax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
subq 128(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI2_1(%rip), %xmm0
addsd %xmm1, %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
movl $.L.str.2, %edi
movb $1, %al
callq printf
movsd .LCPI2_2(%rip), %xmm0 # xmm0 = mem[0],zero
divsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.3, %edi
movb $1, %al
callq printf
movq (%rsp), %rsi
movl $8388608, %edx # imm = 0x800000
movq 56(%rsp), %rdi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4iterPffi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.1e "
.size .L.str, 6
.type _Z4iterPffi,@object # @_Z4iterPffi
.section .rodata,"a",@progbits
.globl _Z4iterPffi
.p2align 3, 0x0
_Z4iterPffi:
.quad _Z19__device_stub__iterPffi
.size _Z4iterPffi, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Elapsed time = %lf(sec)\n"
.size .L.str.2, 25
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "FLOPS = %g\n"
.size .L.str.3, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4iterPffi"
.size .L__unnamed_1, 12
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__iterPffi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4iterPffi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include "includes.h"
__global__ void VectorAdd(float *VecA, float *VecB, float *VecC, int size)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size)
VecC[i] = VecA[i] + VecB[i];
}
|
code for sm_80
Function : _Z9VectorAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include "includes.h"
__global__ void VectorAdd(float *VecA, float *VecB, float *VecC, int size)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size)
VecC[i] = VecA[i] + VecB[i];
}
|
.file "tmpxft_001040d0_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
.globl _Z9VectorAddPfS_S_i
.type _Z9VectorAddPfS_S_i, @function
_Z9VectorAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9VectorAddPfS_S_i, .-_Z9VectorAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9VectorAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include "includes.h"
__global__ void VectorAdd(float *VecA, float *VecB, float *VecC, int size)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size)
VecC[i] = VecA[i] + VecB[i];
}
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorAdd(float *VecA, float *VecB, float *VecC, int size)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size)
VecC[i] = VecA[i] + VecB[i];
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorAdd(float *VecA, float *VecB, float *VecC, int size)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size)
VecC[i] = VecA[i] + VecB[i];
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPfS_S_i
.globl _Z9VectorAddPfS_S_i
.p2align 8
.type _Z9VectorAddPfS_S_i,@function
_Z9VectorAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPfS_S_i, .Lfunc_end0-_Z9VectorAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void VectorAdd(float *VecA, float *VecB, float *VecC, int size)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if (i < size)
VecC[i] = VecA[i] + VecB[i];
}
|
.text
.file "VectorAdd.hip"
.globl _Z24__device_stub__VectorAddPfS_S_i # -- Begin function _Z24__device_stub__VectorAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPfS_S_i,@function
_Z24__device_stub__VectorAddPfS_S_i: # @_Z24__device_stub__VectorAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPfS_S_i,@object # @_Z9VectorAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9VectorAddPfS_S_i
.p2align 3, 0x0
_Z9VectorAddPfS_S_i:
.quad _Z24__device_stub__VectorAddPfS_S_i
.size _Z9VectorAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9VectorAddPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z9VectorAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPfS_S_i
.globl _Z9VectorAddPfS_S_i
.p2align 8
.type _Z9VectorAddPfS_S_i,@function
_Z9VectorAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPfS_S_i, .Lfunc_end0-_Z9VectorAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001040d0_00000000-6_VectorAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
.globl _Z9VectorAddPfS_S_i
.type _Z9VectorAddPfS_S_i, @function
_Z9VectorAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9VectorAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9VectorAddPfS_S_i, .-_Z9VectorAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9VectorAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "VectorAdd.hip"
.globl _Z24__device_stub__VectorAddPfS_S_i # -- Begin function _Z24__device_stub__VectorAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPfS_S_i,@function
_Z24__device_stub__VectorAddPfS_S_i: # @_Z24__device_stub__VectorAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__VectorAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPfS_S_i,@object # @_Z9VectorAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9VectorAddPfS_S_i
.p2align 3, 0x0
_Z9VectorAddPfS_S_i:
.quad _Z24__device_stub__VectorAddPfS_S_i
.size _Z9VectorAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9VectorAddPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <cuda.h>
__global__ void square_cuda(float *a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
extern "C" {
void square(float *a, int N) {
float* a_d;
size_t size = N * sizeof(float);
cudaMalloc((void **) &a_d, size);
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_cuda <<< n_blocks, block_size >>> (a_d, N);
cudaMemcpy(a, a_d, size, cudaMemcpyDeviceToHost);
cudaFree(a_d);
}
}
|
code for sm_80
Function : _Z11square_cudaPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <cuda.h>
__global__ void square_cuda(float *a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
extern "C" {
void square(float *a, int N) {
float* a_d;
size_t size = N * sizeof(float);
cudaMalloc((void **) &a_d, size);
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_cuda <<< n_blocks, block_size >>> (a_d, N);
cudaMemcpy(a, a_d, size, cudaMemcpyDeviceToHost);
cudaFree(a_d);
}
}
|
.file "tmpxft_0016e1bf_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11square_cudaPfiPfi
.type _Z32__device_stub__Z11square_cudaPfiPfi, @function
_Z32__device_stub__Z11square_cudaPfiPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11square_cudaPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z11square_cudaPfiPfi, .-_Z32__device_stub__Z11square_cudaPfiPfi
.globl _Z11square_cudaPfi
.type _Z11square_cudaPfi, @function
_Z11square_cudaPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11square_cudaPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11square_cudaPfi, .-_Z11square_cudaPfi
.globl square
.type square, @function
square:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %esi, %rbp
salq $2, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
testb $3, %bl
setne %dl
movzbl %dl, %edx
leal 3(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $2, %eax
addl %edx, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z11square_cudaPfiPfi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size square, .-square
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11square_cudaPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11square_cudaPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <cuda.h>
__global__ void square_cuda(float *a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
extern "C" {
void square(float *a, int N) {
float* a_d;
size_t size = N * sizeof(float);
cudaMalloc((void **) &a_d, size);
cudaMemcpy(a_d, a, size, cudaMemcpyHostToDevice);
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_cuda <<< n_blocks, block_size >>> (a_d, N);
cudaMemcpy(a, a_d, size, cudaMemcpyDeviceToHost);
cudaFree(a_d);
}
}
|
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void square_cuda(float *a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
extern "C" {
void square(float *a, int N) {
float* a_d;
size_t size = N * sizeof(float);
hipMalloc((void **) &a_d, size);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_cuda <<< n_blocks, block_size >>> (a_d, N);
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
hipFree(a_d);
}
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void square_cuda(float *a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
extern "C" {
void square(float *a, int N) {
float* a_d;
size_t size = N * sizeof(float);
hipMalloc((void **) &a_d, size);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_cuda <<< n_blocks, block_size >>> (a_d, N);
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
hipFree(a_d);
}
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11square_cudaPfi
.globl _Z11square_cudaPfi
.p2align 8
.type _Z11square_cudaPfi,@function
_Z11square_cudaPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11square_cudaPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11square_cudaPfi, .Lfunc_end0-_Z11square_cudaPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11square_cudaPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11square_cudaPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void square_cuda(float *a, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx<N) a[idx] = a[idx] * a[idx];
}
extern "C" {
void square(float *a, int N) {
float* a_d;
size_t size = N * sizeof(float);
hipMalloc((void **) &a_d, size);
hipMemcpy(a_d, a, size, hipMemcpyHostToDevice);
int block_size = 4;
int n_blocks = N/block_size + (N%block_size == 0 ? 0:1);
square_cuda <<< n_blocks, block_size >>> (a_d, N);
hipMemcpy(a, a_d, size, hipMemcpyDeviceToHost);
hipFree(a_d);
}
}
|
.text
.file "square.hip"
.globl _Z26__device_stub__square_cudaPfi # -- Begin function _Z26__device_stub__square_cudaPfi
.p2align 4, 0x90
.type _Z26__device_stub__square_cudaPfi,@function
_Z26__device_stub__square_cudaPfi: # @_Z26__device_stub__square_cudaPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11square_cudaPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__square_cudaPfi, .Lfunc_end0-_Z26__device_stub__square_cudaPfi
.cfi_endproc
# -- End function
.globl square # -- Begin function square
.p2align 4, 0x90
.type square,@function
square: # @square
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r15
leaq (,%r15,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal 3(%r15), %edi
testl %r15d, %r15d
cmovnsl %ebp, %edi
sarl $2, %edi
andl $3, %r15d
cmpl $1, %r15d
sbbl $-1, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $4, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11square_cudaPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size square, .Lfunc_end1-square
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11square_cudaPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11square_cudaPfi,@object # @_Z11square_cudaPfi
.section .rodata,"a",@progbits
.globl _Z11square_cudaPfi
.p2align 3, 0x0
_Z11square_cudaPfi:
.quad _Z26__device_stub__square_cudaPfi
.size _Z11square_cudaPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11square_cudaPfi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__square_cudaPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11square_cudaPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z11square_cudaPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ FMUL R5, R0, R0 ; /* 0x0000000000057220 */
/* 0x004fca0000400000 */
/*00b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11square_cudaPfi
.globl _Z11square_cudaPfi
.p2align 8
.type _Z11square_cudaPfi,@function
_Z11square_cudaPfi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11square_cudaPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11square_cudaPfi, .Lfunc_end0-_Z11square_cudaPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11square_cudaPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11square_cudaPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0016e1bf_00000000-6_square.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11square_cudaPfiPfi
.type _Z32__device_stub__Z11square_cudaPfiPfi, @function
_Z32__device_stub__Z11square_cudaPfiPfi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11square_cudaPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z11square_cudaPfiPfi, .-_Z32__device_stub__Z11square_cudaPfiPfi
.globl _Z11square_cudaPfi
.type _Z11square_cudaPfi, @function
_Z11square_cudaPfi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11square_cudaPfiPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11square_cudaPfi, .-_Z11square_cudaPfi
.globl square
.type square, @function
square:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r12
movl %esi, %ebx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movslq %esi, %rbp
salq $2, %rbp
leaq 8(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbp, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
testb $3, %bl
setne %dl
movzbl %dl, %edx
leal 3(%rbx), %eax
testl %ebx, %ebx
cmovns %ebx, %eax
sarl $2, %eax
addl %edx, %eax
movl %eax, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbp, %rdx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z11square_cudaPfiPfi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size square, .-square
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11square_cudaPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11square_cudaPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "square.hip"
.globl _Z26__device_stub__square_cudaPfi # -- Begin function _Z26__device_stub__square_cudaPfi
.p2align 4, 0x90
.type _Z26__device_stub__square_cudaPfi,@function
_Z26__device_stub__square_cudaPfi: # @_Z26__device_stub__square_cudaPfi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11square_cudaPfi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__square_cudaPfi, .Lfunc_end0-_Z26__device_stub__square_cudaPfi
.cfi_endproc
# -- End function
.globl square # -- Begin function square
.p2align 4, 0x90
.type square,@function
square: # @square
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movslq %esi, %r15
leaq (,%r15,4), %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %r14, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
leal 3(%r15), %edi
testl %r15d, %r15d
cmovnsl %ebp, %edi
sarl $2, %edi
andl $3, %r15d
cmpl $1, %r15d
sbbl $-1, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $4, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11square_cudaPfi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size square, .Lfunc_end1-square
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11square_cudaPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11square_cudaPfi,@object # @_Z11square_cudaPfi
.section .rodata,"a",@progbits
.globl _Z11square_cudaPfi
.p2align 3, 0x0
_Z11square_cudaPfi:
.quad _Z26__device_stub__square_cudaPfi
.size _Z11square_cudaPfi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11square_cudaPfi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__square_cudaPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11square_cudaPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//errorcheck_wcheck.cu: The program is designed to produce output
//'data = 7'. However, errors have been intentionally placed into
//the program as an exercise in error checking.
#include <stdio.h>
#include <stdlib.h>
__global__ void setData(int *ptr)
{
*ptr = 7;
}
int main(void)
{
int *data_d = 0;
int *data_h = 0;
cudaError_t error;
error = cudaMalloc((void**)&data_d, UINT_MAX*sizeof(int));
if( error != cudaSuccess)
{
printf("cudaMalloc error: %s\n", cudaGetErrorString(error));
}
data_h = (int *)malloc(sizeof(int));
setData<<<1,1>>>(0);
cudaThreadSynchronize();
error = cudaGetLastError();
if(error != cudaSuccess)
{
printf("setData error: %s\n", cudaGetErrorString(error));
}
error = cudaMemcpy(data_h, data_d, sizeof(int), cudaMemcpyDeviceToHost);
if(error != cudaSuccess)
{
printf("cudaMemcpy error: %s\n", cudaGetErrorString(error));
}
printf("data = %d\n", *data_h);
free(data_h);
cudaFree(data_d);
return 0;
}
|
code for sm_80
Function : _Z7setDataPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x7 ; /* 0x00000007ff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//errorcheck_wcheck.cu: The program is designed to produce output
//'data = 7'. However, errors have been intentionally placed into
//the program as an exercise in error checking.
#include <stdio.h>
#include <stdlib.h>
__global__ void setData(int *ptr)
{
*ptr = 7;
}
int main(void)
{
int *data_d = 0;
int *data_h = 0;
cudaError_t error;
error = cudaMalloc((void**)&data_d, UINT_MAX*sizeof(int));
if( error != cudaSuccess)
{
printf("cudaMalloc error: %s\n", cudaGetErrorString(error));
}
data_h = (int *)malloc(sizeof(int));
setData<<<1,1>>>(0);
cudaThreadSynchronize();
error = cudaGetLastError();
if(error != cudaSuccess)
{
printf("setData error: %s\n", cudaGetErrorString(error));
}
error = cudaMemcpy(data_h, data_d, sizeof(int), cudaMemcpyDeviceToHost);
if(error != cudaSuccess)
{
printf("cudaMemcpy error: %s\n", cudaGetErrorString(error));
}
printf("data = %d\n", *data_h);
free(data_h);
cudaFree(data_d);
return 0;
}
|
.file "tmpxft_001bd90b_00000000-6_errorcheck_wcheck.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7setDataPiPi
.type _Z26__device_stub__Z7setDataPiPi, @function
_Z26__device_stub__Z7setDataPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7setDataPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z7setDataPiPi, .-_Z26__device_stub__Z7setDataPiPi
.globl _Z7setDataPi
.type _Z7setDataPi, @function
_Z7setDataPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7setDataPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7setDataPi, .-_Z7setDataPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc error: %s\n"
.LC1:
.string "setData error: %s\n"
.LC2:
.string "cudaMemcpy error: %s\n"
.LC3:
.string "data = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movabsq $17179869180, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L18
.L12:
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L14:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L21
.L15:
movl (%rbx), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L19:
movl $0, %edi
call _Z26__device_stub__Z7setDataPiPi
jmp .L13
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7setDataPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7setDataPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//errorcheck_wcheck.cu: The program is designed to produce output
//'data = 7'. However, errors have been intentionally placed into
//the program as an exercise in error checking.
#include <stdio.h>
#include <stdlib.h>
__global__ void setData(int *ptr)
{
*ptr = 7;
}
int main(void)
{
int *data_d = 0;
int *data_h = 0;
cudaError_t error;
error = cudaMalloc((void**)&data_d, UINT_MAX*sizeof(int));
if( error != cudaSuccess)
{
printf("cudaMalloc error: %s\n", cudaGetErrorString(error));
}
data_h = (int *)malloc(sizeof(int));
setData<<<1,1>>>(0);
cudaThreadSynchronize();
error = cudaGetLastError();
if(error != cudaSuccess)
{
printf("setData error: %s\n", cudaGetErrorString(error));
}
error = cudaMemcpy(data_h, data_d, sizeof(int), cudaMemcpyDeviceToHost);
if(error != cudaSuccess)
{
printf("cudaMemcpy error: %s\n", cudaGetErrorString(error));
}
printf("data = %d\n", *data_h);
free(data_h);
cudaFree(data_d);
return 0;
}
|
//errorcheck_wcheck.cu: The program is designed to produce output
//'data = 7'. However, errors have been intentionally placed into
//the program as an exercise in error checking.
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void setData(int *ptr)
{
*ptr = 7;
}
int main(void)
{
int *data_d = 0;
int *data_h = 0;
hipError_t error;
error = hipMalloc((void**)&data_d, UINT_MAX*sizeof(int));
if( error != hipSuccess)
{
printf("hipMalloc error: %s\n", hipGetErrorString(error));
}
data_h = (int *)malloc(sizeof(int));
setData<<<1,1>>>(0);
hipDeviceSynchronize();
error = hipGetLastError();
if(error != hipSuccess)
{
printf("setData error: %s\n", hipGetErrorString(error));
}
error = hipMemcpy(data_h, data_d, sizeof(int), hipMemcpyDeviceToHost);
if(error != hipSuccess)
{
printf("hipMemcpy error: %s\n", hipGetErrorString(error));
}
printf("data = %d\n", *data_h);
free(data_h);
hipFree(data_d);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
//errorcheck_wcheck.cu: The program is designed to produce output
//'data = 7'. However, errors have been intentionally placed into
//the program as an exercise in error checking.
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void setData(int *ptr)
{
*ptr = 7;
}
int main(void)
{
int *data_d = 0;
int *data_h = 0;
hipError_t error;
error = hipMalloc((void**)&data_d, UINT_MAX*sizeof(int));
if( error != hipSuccess)
{
printf("hipMalloc error: %s\n", hipGetErrorString(error));
}
data_h = (int *)malloc(sizeof(int));
setData<<<1,1>>>(0);
hipDeviceSynchronize();
error = hipGetLastError();
if(error != hipSuccess)
{
printf("setData error: %s\n", hipGetErrorString(error));
}
error = hipMemcpy(data_h, data_d, sizeof(int), hipMemcpyDeviceToHost);
if(error != hipSuccess)
{
printf("hipMemcpy error: %s\n", hipGetErrorString(error));
}
printf("data = %d\n", *data_h);
free(data_h);
hipFree(data_d);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7setDataPi
.globl _Z7setDataPi
.p2align 8
.type _Z7setDataPi,@function
_Z7setDataPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 7
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7setDataPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7setDataPi, .Lfunc_end0-_Z7setDataPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7setDataPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z7setDataPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
//errorcheck_wcheck.cu: The program is designed to produce output
//'data = 7'. However, errors have been intentionally placed into
//the program as an exercise in error checking.
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void setData(int *ptr)
{
*ptr = 7;
}
int main(void)
{
int *data_d = 0;
int *data_h = 0;
hipError_t error;
error = hipMalloc((void**)&data_d, UINT_MAX*sizeof(int));
if( error != hipSuccess)
{
printf("hipMalloc error: %s\n", hipGetErrorString(error));
}
data_h = (int *)malloc(sizeof(int));
setData<<<1,1>>>(0);
hipDeviceSynchronize();
error = hipGetLastError();
if(error != hipSuccess)
{
printf("setData error: %s\n", hipGetErrorString(error));
}
error = hipMemcpy(data_h, data_d, sizeof(int), hipMemcpyDeviceToHost);
if(error != hipSuccess)
{
printf("hipMemcpy error: %s\n", hipGetErrorString(error));
}
printf("data = %d\n", *data_h);
free(data_h);
hipFree(data_d);
return 0;
}
|
.text
.file "errorcheck_wcheck.hip"
.globl _Z22__device_stub__setDataPi # -- Begin function _Z22__device_stub__setDataPi
.p2align 4, 0x90
.type _Z22__device_stub__setDataPi,@function
_Z22__device_stub__setDataPi: # @_Z22__device_stub__setDataPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7setDataPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__setDataPi, .Lfunc_end0-_Z22__device_stub__setDataPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movabsq $17179869180, %rsi # imm = 0x3FFFFFFFC
callq hipMalloc
testl %eax, %eax
je .LBB1_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_2:
movl $4, %edi
callq malloc
movq %rax, %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq $0, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7setDataPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_6:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_8:
movl (%rbx), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7setDataPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7setDataPi,@object # @_Z7setDataPi
.section .rodata,"a",@progbits
.globl _Z7setDataPi
.p2align 3, 0x0
_Z7setDataPi:
.quad _Z22__device_stub__setDataPi
.size _Z7setDataPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc error: %s\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "setData error: %s\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy error: %s\n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "data = %d\n"
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7setDataPi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__setDataPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7setDataPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
Function : _Z7setDataPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, 0x7 ; /* 0x00000007ff057424 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fca0000000f00 */
/*0050*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0060*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0070*/ BRA 0x70; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7setDataPi
.globl _Z7setDataPi
.p2align 8
.type _Z7setDataPi,@function
_Z7setDataPi:
s_load_b64 s[0:1], s[0:1], 0x0
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 7
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7setDataPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7setDataPi, .Lfunc_end0-_Z7setDataPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7setDataPi
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z7setDataPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001bd90b_00000000-6_errorcheck_wcheck.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7setDataPiPi
.type _Z26__device_stub__Z7setDataPiPi, @function
_Z26__device_stub__Z7setDataPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7setDataPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z7setDataPiPi, .-_Z26__device_stub__Z7setDataPiPi
.globl _Z7setDataPi
.type _Z7setDataPi, @function
_Z7setDataPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7setDataPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z7setDataPi, .-_Z7setDataPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc error: %s\n"
.LC1:
.string "setData error: %s\n"
.LC2:
.string "cudaMemcpy error: %s\n"
.LC3:
.string "data = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $48, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movabsq $17179869180, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L18
.L12:
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L20
.L14:
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L21
.L15:
movl (%rbx), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L12
.L19:
movl $0, %edi
call _Z26__device_stub__Z7setDataPiPi
jmp .L13
.L20:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L14
.L21:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z7setDataPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7setDataPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "errorcheck_wcheck.hip"
.globl _Z22__device_stub__setDataPi # -- Begin function _Z22__device_stub__setDataPi
.p2align 4, 0x90
.type _Z22__device_stub__setDataPi,@function
_Z22__device_stub__setDataPi: # @_Z22__device_stub__setDataPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7setDataPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__setDataPi, .Lfunc_end0-_Z22__device_stub__setDataPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $80, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -16
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movabsq $17179869180, %rsi # imm = 0x3FFFFFFFC
callq hipMalloc
testl %eax, %eax
je .LBB1_2
# %bb.1:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_2:
movl $4, %edi
callq malloc
movq %rax, %rbx
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq $0, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7setDataPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB1_6
# %bb.5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.1, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_6:
movq 8(%rsp), %rsi
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
je .LBB1_8
# %bb.7:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_8:
movl (%rbx), %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7setDataPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7setDataPi,@object # @_Z7setDataPi
.section .rodata,"a",@progbits
.globl _Z7setDataPi
.p2align 3, 0x0
_Z7setDataPi:
.quad _Z22__device_stub__setDataPi
.size _Z7setDataPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "hipMalloc error: %s\n"
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "setData error: %s\n"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy error: %s\n"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "data = %d\n"
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7setDataPi"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__setDataPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7setDataPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
//
// kernal_add.cu
// XCodeCudaTest
//
// Created by on 2011/11/9.
// Copyright (c) 2011年 takmatsumoto All rights reserved.
//
//__global__ void VecAdd(float* A, float* float* B, float* C)
//{
// int idx = threadIdx.x;
//}
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
//
// kernal_add.cu
// XCodeCudaTest
//
// Created by on 2011/11/9.
// Copyright (c) 2011年 takmatsumoto All rights reserved.
//
//__global__ void VecAdd(float* A, float* float* B, float* C)
//{
// int idx = threadIdx.x;
//}
|
.file "tmpxft_0007265c_00000000-6_kernal_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
//
// kernal_add.cu
// XCodeCudaTest
//
// Created by on 2011/11/9.
// Copyright (c) 2011年 takmatsumoto All rights reserved.
//
//__global__ void VecAdd(float* A, float* float* B, float* C)
//{
// int idx = threadIdx.x;
//}
|
#include <hip/hip_runtime.h>
//
// kernal_add.cu
// XCodeCudaTest
//
// Created by on 2011/11/9.
// Copyright (c) 2011年 takmatsumoto All rights reserved.
//
//__global__ void VecAdd(float* A, float* float* B, float* C)
//{
// int idx = threadIdx.x;
//}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
//
// kernal_add.cu
// XCodeCudaTest
//
// Created by on 2011/11/9.
// Copyright (c) 2011年 takmatsumoto All rights reserved.
//
//__global__ void VecAdd(float* A, float* float* B, float* C)
//{
// int idx = threadIdx.x;
//}
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
//
// kernal_add.cu
// XCodeCudaTest
//
// Created by on 2011/11/9.
// Copyright (c) 2011年 takmatsumoto All rights reserved.
//
//__global__ void VecAdd(float* A, float* float* B, float* C)
//{
// int idx = threadIdx.x;
//}
|
.text
.file "kernal_add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0007265c_00000000-6_kernal_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "kernal_add.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include<stdio.h>
#include<iostream>
extern "C" {
__global__ void GPU_add(
int n,
int* d_a,
int* d_b
);
void calling_routine_c (
int n,
int* d_a,
int* d_b
)
{
//printf("cuda c stream = %lld\n",streamid);
// Call the cuda kernel:
GPU_add<<<1,1024>>>(
n,
d_a,
d_b
);
printf("Completed an add kernel\n");
} // end calling routine
} // extern "C"
|
code for sm_80
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include<stdio.h>
#include<iostream>
extern "C" {
__global__ void GPU_add(
int n,
int* d_a,
int* d_b
);
void calling_routine_c (
int n,
int* d_a,
int* d_b
)
{
//printf("cuda c stream = %lld\n",streamid);
// Call the cuda kernel:
GPU_add<<<1,1024>>>(
n,
d_a,
d_b
);
printf("Completed an add kernel\n");
} // end calling routine
} // extern "C"
|
.file "tmpxft_0013fb77_00000000-6_c_code.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Completed an add kernel\n"
.text
.globl calling_routine_c
.type calling_routine_c, @function
calling_routine_c:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L6
.L4:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call GPU_add@PLT
jmp .L4
.cfi_endproc
.LFE3669:
.size calling_routine_c, .-calling_routine_c
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include<stdio.h>
#include<iostream>
extern "C" {
__global__ void GPU_add(
int n,
int* d_a,
int* d_b
);
void calling_routine_c (
int n,
int* d_a,
int* d_b
)
{
//printf("cuda c stream = %lld\n",streamid);
// Call the cuda kernel:
GPU_add<<<1,1024>>>(
n,
d_a,
d_b
);
printf("Completed an add kernel\n");
} // end calling routine
} // extern "C"
|
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
extern "C" {
__global__ void GPU_add(
int n,
int* d_a,
int* d_b
);
void calling_routine_c (
int n,
int* d_a,
int* d_b
)
{
//printf("cuda c stream = %lld\n",streamid);
// Call the cuda kernel:
GPU_add<<<1,1024>>>(
n,
d_a,
d_b
);
printf("Completed an add kernel\n");
} // end calling routine
} // extern "C"
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
extern "C" {
__global__ void GPU_add(
int n,
int* d_a,
int* d_b
);
void calling_routine_c (
int n,
int* d_a,
int* d_b
)
{
//printf("cuda c stream = %lld\n",streamid);
// Call the cuda kernel:
GPU_add<<<1,1024>>>(
n,
d_a,
d_b
);
printf("Completed an add kernel\n");
} // end calling routine
} // extern "C"
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <hip/hip_runtime.h>
#include<stdio.h>
#include<iostream>
extern "C" {
__global__ void GPU_add(
int n,
int* d_a,
int* d_b
);
void calling_routine_c (
int n,
int* d_a,
int* d_b
)
{
//printf("cuda c stream = %lld\n",streamid);
// Call the cuda kernel:
GPU_add<<<1,1024>>>(
n,
d_a,
d_b
);
printf("Completed an add kernel\n");
} // end calling routine
} // extern "C"
|
.text
.file "c_code.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl calling_routine_c # -- Begin function calling_routine_c
.p2align 4, 0x90
.type calling_routine_c,@function
calling_routine_c: # @calling_routine_c
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, %ebp
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movl %ebp, %edi
movq %r14, %rsi
movq %rbx, %rdx
callq __device_stub__GPU_add
.LBB0_2:
movl $.Lstr, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size calling_routine_c, .Lfunc_end0-calling_routine_c
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Completed an add kernel"
.size .Lstr, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly.
|
code for sm_80
|
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_0013fb77_00000000-6_c_code.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Completed an add kernel\n"
.text
.globl calling_routine_c
.type calling_routine_c, @function
calling_routine_c:
.LFB3669:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %rsi, %rbp
movq %rdx, %r12
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L6
.L4:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
movq %r12, %rdx
movq %rbp, %rsi
movl %ebx, %edi
call GPU_add@PLT
jmp .L4
.cfi_endproc
.LFE3669:
.size calling_routine_c, .-calling_routine_c
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "c_code.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl calling_routine_c # -- Begin function calling_routine_c
.p2align 4, 0x90
.type calling_routine_c,@function
calling_routine_c: # @calling_routine_c
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rdx, %rbx
movq %rsi, %r14
movl %edi, %ebp
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 1023(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_2
# %bb.1:
movl %ebp, %edi
movq %r14, %rsi
movq %rbx, %rdx
callq __device_stub__GPU_add
.LBB0_2:
movl $.Lstr, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end0:
.size calling_routine_c, .Lfunc_end0-calling_routine_c
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Completed an add kernel"
.size .Lstr, 24
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <cuda_runtime.h>
#define PI 3.14159265358979323846
#define N 100000
#define BLOCK_SIZE 1024
__device__ void BoxMuller(float u1, float u2, float *n1, float *n2)
{
float r = sqrtf(-2*logf(u1));
float theta = 2*PI*(u2);
*n1 = r*sinf(theta);
*n2 = r*cosf(theta);
}
__global__ void norm_transform(float *dev_u1, float *dev_u2,
float *dev_n1, float *dev_n2, int size)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < size)
{
float res1;
float res2;
BoxMuller(dev_u1[tid], dev_u2[tid], &res1, &res2);
dev_n1[tid] = res1;
dev_n2[tid] = res2;
}
}
int main()
{
int dev_count;
cudaGetDeviceCount(&dev_count);
printf("Number of CUDA-capable devices: %d.\n", dev_count);
cudaDeviceProp dev_prop;
for (int j=0; j<dev_count; j++)
{
cudaGetDeviceProperties(&dev_prop, j);
printf("Device number %d has max %d threads per block.\n", j, dev_prop.maxThreadsPerBlock);
printf("Device number %d has %d multiprocessors.\n", j, dev_prop.multiProcessorCount);
}
int i;
curandGenerator_t gen1, gen2;
float *dev_u1, *dev_u2, *host_u1, *host_u2;
float *dev_n1, *dev_n2, *host_n1, *host_n2;
// allocate memory on the host
//host_u1 = (float*)calloc(N, sizeof(float));
//host_u2 = (float*)calloc(N, sizeof(float));
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
host_n1 = (float*)calloc(N, sizeof(float));
host_n2 = (float*)calloc(N, sizeof(float));
// allocate memory on the device
cudaMalloc((void**)&dev_u1, N * sizeof(float));
cudaMalloc((void**)&dev_u2, N * sizeof(float));
cudaMalloc((void**)&dev_n1, N * sizeof(float));
cudaMalloc((void**)&dev_n2, N * sizeof(float));
// create a mersenne twister
curandCreateGenerator(&gen1, CURAND_RNG_PSEUDO_MTGP32);
curandCreateGenerator(&gen2, CURAND_RNG_PSEUDO_MTGP32);
// set seed
curandGenerateUniform(gen1, dev_u1, N);
curandGenerateUniform(gen2, dev_u2, N);
int numBlocks = ceil(float(N) / BLOCK_SIZE);
// box muller transform
norm_transform<<<numBlocks, BLOCK_SIZE>>>(dev_u1, dev_u2, dev_n1, dev_n2, N);
// copy device memory to host
cudaMemcpy(host_n1, dev_n1, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(host_n2, dev_n2, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("Time elapsed to generate 2 x %d normal variables: %f seconds.\n", N, elapsedTime/1000.0);
printf("Random normal draws: \n");
for (i = 0; i < 10; i++)
{
printf(" %1.4f %1.4f\n", host_n1[i], host_n2[i]);
}
printf("\n");
curandDestroyGenerator(gen1);
curandDestroyGenerator(gen2);
cudaDeviceReset();
free(host_n1);
free(host_n2);
return 0;
}
|
code for sm_80
Function : _Z14norm_transformPfS_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x20, RZ ; /* 0xffffffe001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R11, R11, c[0x0][0x0], R0 ; /* 0x000000000b0b7a24 */
/* 0x001fca00078e0200 */
/*0050*/ ISETP.GE.AND P0, PT, R11, c[0x0][0x180], PT ; /* 0x000060000b007a0c */
/* 0x000fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0090*/ IMAD.WIDE R6, R11, R4, c[0x0][0x168] ; /* 0x00005a000b067625 */
/* 0x000fc800078e0204 */
/*00a0*/ IMAD.WIDE R4, R11, R4, c[0x0][0x160] ; /* 0x000058000b047625 */
/* 0x000fe400078e0204 */
/*00b0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000ea8000c1e1900 */
/*00c0*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ IMAD.MOV.U32 R10, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff0a7424 */
/* 0x000fe200078e00ff */
/*00e0*/ BSSY B0, 0x750 ; /* 0x0000066000007945 */
/* 0x000fe20003800000 */
/*00f0*/ F2F.F64.F32 R8, R6 ; /* 0x0000000600087310 */
/* 0x004e220000201800 */
/*0100*/ FSETP.GEU.AND P0, PT, R2, 1.175494350822287508e-38, PT ; /* 0x008000000200780b */
/* 0x008fc80003f0e000 */
/*0110*/ FSEL R3, RZ, -23, P0 ; /* 0xc1b80000ff037808 */
/* 0x000fe20000000000 */
/*0120*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x001e100000000000 */
/*0130*/ @!P0 FMUL R2, R2, 8388608 ; /* 0x4b00000002028820 */
/* 0x000fca0000400000 */
/*0140*/ IADD3 R0, R2.reuse, -0x3f2aaaab, RZ ; /* 0xc0d5555502007810 */
/* 0x040fe40007ffe0ff */
/*0150*/ ISETP.GE.U32.AND P1, PT, R2, 0x7f800000, PT ; /* 0x7f8000000200780c */
/* 0x000fe20003f26070 */
/*0160*/ F2F.F32.F64 R9, R8 ; /* 0x0000000800097310 */
/* 0x0010620000301000 */
/*0170*/ LOP3.LUT R13, R0, 0xff800000, RZ, 0xc0, !PT ; /* 0xff800000000d7812 */
/* 0x000fca00078ec0ff */
/*0180*/ IMAD.IADD R0, R2, 0x1, -R13 ; /* 0x0000000102007824 */
/* 0x000fc800078e0a0d */
/*0190*/ FADD R7, R0, -1 ; /* 0xbf80000000077421 */
/* 0x000fe20000000000 */
/*01a0*/ SHF.R.S32.HI R8, RZ, 0x1f, R11 ; /* 0x0000001fff087819 */
/* 0x001fc6000001140b */
/*01b0*/ FFMA R0, R7, -R10, 0.14084610342979431152 ; /* 0x3e1039f607007423 */
/* 0x000fe4000000080a */
/*01c0*/ FMUL R5, R9.reuse, 0.63661974668502807617 ; /* 0x3f22f98309057820 */
/* 0x042fe20000400000 */
/*01d0*/ FSETP.GE.AND P0, PT, |R9|, 105615, PT ; /* 0x47ce47800900780b */
/* 0x000fe20003f06200 */
/*01e0*/ FFMA R4, R7.reuse, R0, -0.12148627638816833496 ; /* 0xbdf8cdcc07047423 */
/* 0x040fe40000000000 */
/*01f0*/ F2I.NTZ R0, R5 ; /* 0x0000000500007305 */
/* 0x000e240000203100 */
/*0200*/ FFMA R4, R7, R4, 0.13980610668659210205 ; /* 0x3e0f295507047423 */
/* 0x000fc80000000004 */
/*0210*/ FFMA R6, R7.reuse, R4, -0.16684235632419586182 ; /* 0xbe2ad8b907067423 */
/* 0x040fe40000000004 */
/*0220*/ I2F R4, R13 ; /* 0x0000000d00047306 */
/* 0x000e640000201400 */
/*0230*/ FFMA R6, R7, R6, 0.20012299716472625732 ; /* 0x3e4ced0b07067423 */
/* 0x000fc80000000006 */
/*0240*/ FFMA R6, R7.reuse, R6, -0.24999669194221496582 ; /* 0xbe7fff2207067423 */
/* 0x040fe40000000006 */
/*0250*/ I2F R14, R0 ; /* 0x00000000000e7306 */
/* 0x001e220000201400 */
/*0260*/ IMAD.MOV.U32 R15, RZ, RZ, R0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0000 */
/*0270*/ FFMA R6, R7, R6, 0.33333182334899902344 ; /* 0x3eaaaa7807067423 */
/* 0x000fc80000000006 */
/*0280*/ FFMA R6, R7.reuse, R6, -0.5 ; /* 0xbf00000007067423 */
/* 0x040fe40000000006 */
/*0290*/ FFMA R3, R4, 1.1920928955078125e-07, R3 ; /* 0x3400000004037823 */
/* 0x002fe40000000003 */
/*02a0*/ FMUL R6, R7, R6 ; /* 0x0000000607067220 */
/* 0x000fc80000400000 */
/*02b0*/ FFMA R6, R7, R6, R7 ; /* 0x0000000607067223 */
/* 0x000fe40000000007 */
/*02c0*/ @P1 IMAD.MOV.U32 R7, RZ, RZ, 0x7f800000 ; /* 0x7f800000ff071424 */
/* 0x000fe400078e00ff */
/*02d0*/ FFMA R5, R14, -1.5707962512969970703, R9 ; /* 0xbfc90fda0e057823 */
/* 0x001fe40000000009 */
/*02e0*/ FFMA R3, R3, 0.69314718246459960938, R6 ; /* 0x3f31721803037823 */
/* 0x000fe40000000006 */
/*02f0*/ @P1 FFMA R3, R2.reuse, R7, +INF ; /* 0x7f80000002031423 */
/* 0x040fe20000000007 */
/*0300*/ FSETP.NEU.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x000fe20003f2d000 */
/*0310*/ FFMA R5, R14, -7.5497894158615963534e-08, R5 ; /* 0xb3a221680e057823 */
/* 0x000fc40000000005 */
/*0320*/ FMUL R3, R3, -2 ; /* 0xc000000003037820 */
/* 0x000fe40000400000 */
/*0330*/ FFMA R14, R14, -5.3903029534742383927e-15, R5 ; /* 0xa7c234c50e0e7823 */
/* 0x000fc60000000005 */
/*0340*/ FSEL R10, R3, +INF , P1 ; /* 0x7f800000030a7808 */
/* 0x000fe20000800000 */
/*0350*/ IMAD.MOV.U32 R2, RZ, RZ, R14 ; /* 0x000000ffff027224 */
/* 0x000fe200078e000e */
/*0360*/ @!P0 BRA 0x740 ; /* 0x000003d000008947 */
/* 0x000fea0003800000 */
/*0370*/ FSETP.NEU.AND P1, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f2d200 */
/*0380*/ @!P1 BRA 0x720 ; /* 0x0000039000009947 */
/* 0x000fea0003800000 */
/*0390*/ SHF.R.U32.HI R0, RZ, 0x17, R9 ; /* 0x00000017ff007819 */
/* 0x000fe20000011609 */
/*03a0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*03b0*/ SHF.L.U32 R2, R9, 0x8, RZ ; /* 0x0000000809027819 */
/* 0x000fe200000006ff */
/*03c0*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x000fe200078e00ff */
/*03d0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe200078ec0ff */
/*03e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*03f0*/ LOP3.LUT R12, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x80000000020c7812 */
/* 0x000fe200078efcff */
/*0400*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*0410*/ IADD3 R7, R0, -0x80, RZ ; /* 0xffffff8000077810 */
/* 0x000fe20007ffe0ff */
/*0420*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0001 */
/*0430*/ SHF.R.U32.HI R13, RZ, 0x5, R7 ; /* 0x00000005ff0d7819 */
/* 0x000fe40000011607 */
/*0440*/ IMAD.U32 R4, RZ, RZ, UR8 ; /* 0x00000008ff047e24 */
/* 0x000fe4000f8e00ff */
/*0450*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*0460*/ LDG.E.CONSTANT R3, [R4.64] ; /* 0x0000000604037981 */
/* 0x000ea2000c1e9900 */
/*0470*/ IADD3 R16, R16, 0x1, RZ ; /* 0x0000000110107810 */
/* 0x000fe20007ffe0ff */
/*0480*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0490*/ ISETP.NE.AND P1, PT, R16, 0x6, PT ; /* 0x000000061000780c */
/* 0x000fe20003f25270 */
/*04a0*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*04b0*/ IMAD.WIDE.U32 R2, R3, R12, RZ ; /* 0x0000000c03027225 */
/* 0x004fca00078e00ff */
/*04c0*/ IADD3 R17, P2, R2, R6, RZ ; /* 0x0000000602117210 */
/* 0x000fc80007f5e0ff */
/*04d0*/ IADD3.X R6, R3, UR4, RZ, P2, !PT ; /* 0x0000000403067c10 */
/* 0x000fe200097fe4ff */
/*04e0*/ STL [R0], R17 ; /* 0x0000001100007387 */
/* 0x0001e40000100800 */
/*04f0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0500*/ @P1 BRA 0x440 ; /* 0xffffff3000001947 */
/* 0x000fea000383ffff */
/*0510*/ LOP3.LUT P1, R7, R7, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f07077812 */
/* 0x000fe2000782c0ff */
/*0520*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e20000100800 */
/*0530*/ IADD3 R0, -R13.reuse, 0x4, RZ ; /* 0x000000040d007810 */
/* 0x040fe40007ffe1ff */
/*0540*/ IADD3 R2, -R13, 0x6, RZ ; /* 0x000000060d027810 */
/* 0x000fc80007ffe1ff */
/*0550*/ LEA R12, R2, R1, 0x2 ; /* 0x00000001020c7211 */
/* 0x000fca00078e10ff */
/*0560*/ @P1 IMAD R13, R0, 0x4, R1 ; /* 0x00000004000d1824 */
/* 0x000fe200078e0201 */
/*0570*/ LDL R3, [R12+-0x4] ; /* 0xfffffc000c037983 */
/* 0x000ea80000100800 */
/*0580*/ @P1 LDL R5, [R13] ; /* 0x000000000d051983 */
/* 0x000ee80000100800 */
/*0590*/ LDL R0, [R12] ; /* 0x000000000c007983 */
/* 0x000f220000100800 */
/*05a0*/ @P1 IADD3 R2, -R7, 0x20, RZ ; /* 0x0000002007021810 */
/* 0x000fc80007ffe1ff */
/*05b0*/ @P1 SHF.R.U32.HI R4, RZ, R2.reuse, R5 ; /* 0x00000002ff041219 */
/* 0x088fe40000011605 */
/*05c0*/ @P1 SHF.R.U32.HI R2, RZ, R2, R3 ; /* 0x00000002ff021219 */
/* 0x004fe40000011603 */
/*05d0*/ @P1 SHF.L.U32 R5, R0, R7.reuse, RZ ; /* 0x0000000700051219 */
/* 0x090fe400000006ff */
/*05e0*/ @P1 SHF.L.U32 R7, R3, R7, RZ ; /* 0x0000000703071219 */
/* 0x000fc600000006ff */
/*05f0*/ @P1 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102001824 */
/* 0x000fe400078e0205 */
/*0600*/ @P1 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104031824 */
/* 0x000fca00078e0207 */
/*0610*/ SHF.L.U32.HI R7, R3, 0x2, R0 ; /* 0x0000000203077819 */
/* 0x000fc80000010600 */
/*0620*/ SHF.R.U32.HI R13, RZ, 0x1f, R7 ; /* 0x0000001fff0d7819 */
/* 0x000fc80000011607 */
/*0630*/ ISETP.NE.AND P2, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f45270 */
/*0640*/ IMAD.SHL.U32 R6, R3, 0x4, RZ ; /* 0x0000000403067824 */
/* 0x001fd800078e00ff */
/*0650*/ @P2 LOP3.LUT R7, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff072212 */
/* 0x000fe400078e33ff */
/*0660*/ @P2 LOP3.LUT R6, RZ, R6, RZ, 0x33, !PT ; /* 0x00000006ff062212 */
/* 0x000fc800078e33ff */
/*0670*/ I2F.F64.S64 R2, R6 ; /* 0x0000000600027312 */
/* 0x000e240000301c00 */
/*0680*/ DMUL R4, R2, c[0x2][0x8] ; /* 0x0080020002047a28 */
/* 0x0010640000000000 */
/*0690*/ LOP3.LUT P1, R2, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009027812 */
/* 0x001fe4000782c0ff */
/*06a0*/ LEA.HI R0, R0, R13, RZ, 0x2 ; /* 0x0000000d00007211 */
/* 0x000fcc00078f10ff */
/*06b0*/ F2F.F32.F64 R4, R4 ; /* 0x0000000400047310 */
/* 0x002e220000301000 */
/*06c0*/ @P2 LOP3.LUT R2, R2, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000002022812 */
/* 0x000fc800078e3cff */
/*06d0*/ ISETP.NE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f45270 */
/*06e0*/ IMAD.MOV R2, RZ, RZ, -R0 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a00 */
/*06f0*/ @P1 IMAD.MOV.U32 R0, RZ, RZ, R2 ; /* 0x000000ffff001224 */
/* 0x000fe200078e0002 */
/*0700*/ FSEL R2, R4, -R4, !P2 ; /* 0x8000000404027208 */
/* 0x001fe20005000000 */
/*0710*/ BRA 0x740 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0720*/ FMUL R2, RZ, R9 ; /* 0x00000009ff027220 */
/* 0x000fe40000400000 */
/*0730*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe400078e00ff */
/*0740*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R3, R10, -0xd000000, RZ ; /* 0xf30000000a037810 */
/* 0x000fe20007ffe0ff */
/*0760*/ MUFU.RSQ R5, R10 ; /* 0x0000000a00057308 */
/* 0x0000620000001400 */
/*0770*/ BSSY B0, 0x830 ; /* 0x000000b000007945 */
/* 0x000fe40003800000 */
/*0780*/ ISETP.GT.U32.AND P1, PT, R3, 0x727fffff, PT ; /* 0x727fffff0300780c */
/* 0x000fda0003f24070 */
/*0790*/ @!P1 BRA 0x7e0 ; /* 0x0000004000009947 */
/* 0x000fea0003800000 */
/*07a0*/ MOV R12, 0x7c0 ; /* 0x000007c0000c7802 */
/* 0x003fe40000000f00 */
/*07b0*/ CALL.REL.NOINC 0xec0 ; /* 0x0000070000007944 */
/* 0x000fea0003c00000 */
/*07c0*/ MOV R10, R3 ; /* 0x00000003000a7202 */
/* 0x000fe20000000f00 */
/*07d0*/ BRA 0x820 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07e0*/ FMUL.FTZ R3, R10, R5 ; /* 0x000000050a037220 */
/* 0x003fe40000410000 */
/*07f0*/ FMUL.FTZ R4, R5, 0.5 ; /* 0x3f00000005047820 */
/* 0x000fe40000410000 */
/*0800*/ FFMA R10, -R3, R3, R10 ; /* 0x00000003030a7223 */
/* 0x000fc8000000010a */
/*0810*/ FFMA R10, R10, R4, R3 ; /* 0x000000040a0a7223 */
/* 0x000fe40000000003 */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT P2, RZ, R0.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100ff7812 */
/* 0x040fe2000784c0ff */
/*0840*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3c0885e4 ; /* 0x3c0885e4ff0c7424 */
/* 0x000fe200078e00ff */
/*0850*/ LOP3.LUT P1, RZ, R0, 0x2, RZ, 0xc0, !PT ; /* 0x0000000200ff7812 */
/* 0x000fe2000782c0ff */
/*0860*/ FMUL R6, R2.reuse, R2 ; /* 0x0000000202067220 */
/* 0x040fe20000400000 */
/*0870*/ FSEL R2, R2, 1, !P2 ; /* 0x3f80000002027808 */
/* 0x000fe20005000000 */
/*0880*/ IMAD.MOV.U32 R13, RZ, RZ, 0x3e2aaaa8 ; /* 0x3e2aaaa8ff0d7424 */
/* 0x000fe200078e00ff */
/*0890*/ FSEL R4, R12, 0.041666727513074874878, !P2 ; /* 0x3d2aaabb0c047808 */
/* 0x000fe20005000000 */
/*08a0*/ IMAD.MOV.U32 R3, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff037424 */
/* 0x000fe200078e00ff */
/*08b0*/ BSSY B0, 0xd20 ; /* 0x0000046000007945 */
/* 0x000fe20003800000 */
/*08c0*/ FFMA R17, R2, R6, RZ ; /* 0x0000000602117223 */
/* 0x000fe200000000ff */
/*08d0*/ FSEL R0, -R13, -0.4999999701976776123, !P2 ; /* 0xbeffffff0d007808 */
/* 0x000fc60005000100 */
/*08e0*/ @P2 IMAD.MOV.U32 R5, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff052424 */
/* 0x000fc800078e00ff */
/*08f0*/ @P2 FFMA R3, R6, R5, -0.0013887860113754868507 ; /* 0xbab607ed06032423 */
/* 0x000fc80000000005 */
/*0900*/ FFMA R3, R6, R3, R4 ; /* 0x0000000306037223 */
/* 0x000fc80000000004 */
/*0910*/ FFMA R0, R6, R3, R0 ; /* 0x0000000306007223 */
/* 0x000fc80000000000 */
/*0920*/ FFMA R17, R0, R17, R2 ; /* 0x0000001100117223 */
/* 0x000fc80000000002 */
/*0930*/ @P1 FFMA R17, R17, -1, RZ ; /* 0xbf80000011111823 */
/* 0x000fe200000000ff */
/*0940*/ @!P0 BRA 0xd10 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*0950*/ FSETP.NEU.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fda0003f0d200 */
/*0960*/ @!P0 BRA 0xcf0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0970*/ SHF.R.U32.HI R0, RZ, 0x17, R9 ; /* 0x00000017ff007819 */
/* 0x000fe20000011609 */
/*0980*/ IMAD.SHL.U32 R2, R9, 0x100, RZ ; /* 0x0000010009027824 */
/* 0x000fe200078e00ff */
/*0990*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*09a0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*09b0*/ LOP3.LUT R0, R0, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff00007812 */
/* 0x000fe200078ec0ff */
/*09c0*/ ULDC.64 UR8, c[0x4][0x0] ; /* 0x0100000000087ab9 */
/* 0x000fe20000000a00 */
/*09d0*/ LOP3.LUT R19, R2, 0x80000000, RZ, 0xfc, !PT ; /* 0x8000000002137812 */
/* 0x000fe400078efcff */
/*09e0*/ IADD3 R14, R0, -0x80, RZ ; /* 0xffffff80000e7810 */
/* 0x000fe20007ffe0ff */
/*09f0*/ IMAD.MOV.U32 R0, RZ, RZ, R1 ; /* 0x000000ffff007224 */
/* 0x000fc600078e0001 */
/*0a00*/ SHF.R.U32.HI R16, RZ, 0x5, R14 ; /* 0x00000005ff107819 */
/* 0x000fe4000001160e */
/*0a10*/ MOV R4, UR8 ; /* 0x0000000800047c02 */
/* 0x000fe20008000f00 */
/*0a20*/ IMAD.U32 R5, RZ, RZ, UR9 ; /* 0x00000009ff057e24 */
/* 0x000fca000f8e00ff */
/*0a30*/ LDG.E.CONSTANT R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea2000c1e9900 */
/*0a40*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0a50*/ UIADD3 UR8, UP0, UR8, 0x4, URZ ; /* 0x0000000408087890 */
/* 0x000fc6000ff1e03f */
/*0a60*/ ISETP.NE.AND P0, PT, R7, 0x6, PT ; /* 0x000000060700780c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe200087fe43f */
/*0a80*/ IMAD.WIDE.U32 R2, R2, R19, RZ ; /* 0x0000001302027225 */
/* 0x004fca00078e00ff */
/*0a90*/ IADD3 R15, P1, R2, R6, RZ ; /* 0x00000006020f7210 */
/* 0x000fc80007f3e0ff */
/*0aa0*/ IADD3.X R6, R3, UR4, RZ, P1, !PT ; /* 0x0000000403067c10 */
/* 0x000fe20008ffe4ff */
/*0ab0*/ STL [R0], R15 ; /* 0x0000000f00007387 */
/* 0x0001e40000100800 */
/*0ac0*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x001fe20007ffe0ff */
/*0ad0*/ @P0 BRA 0xa10 ; /* 0xffffff3000000947 */
/* 0x000fea000383ffff */
/*0ae0*/ LOP3.LUT P0, R14, R14, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f0e0e7812 */
/* 0x000fe2000780c0ff */
/*0af0*/ STL [R1+0x18], R6 ; /* 0x0000180601007387 */
/* 0x0001e20000100800 */
/*0b00*/ IADD3 R0, -R16.reuse, 0x4, RZ ; /* 0x0000000410007810 */
/* 0x040fe40007ffe1ff */
/*0b10*/ IADD3 R16, -R16, 0x6, RZ ; /* 0x0000000610107810 */
/* 0x000fca0007ffe1ff */
/*0b20*/ IMAD R16, R16, 0x4, R1 ; /* 0x0000000410107824 */
/* 0x000fc800078e0201 */
/*0b30*/ @P0 IMAD R15, R0, 0x4, R1 ; /* 0x00000004000f0824 */
/* 0x000fe200078e0201 */
/*0b40*/ LDL R3, [R16+-0x4] ; /* 0xfffffc0010037983 */
/* 0x000ea80000100800 */
/*0b50*/ @P0 LDL R2, [R15] ; /* 0x000000000f020983 */
/* 0x000ee80000100800 */
/*0b60*/ LDL R0, [R16] ; /* 0x0000000010007983 */
/* 0x000f220000100800 */
/*0b70*/ @P0 IADD3 R7, -R14, 0x20, RZ ; /* 0x000000200e070810 */
/* 0x000fc40007ffe1ff */
/*0b80*/ LOP3.LUT P1, R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fe4000782c0ff */
/*0b90*/ @P0 SHF.R.U32.HI R4, RZ, R7.reuse, R2 ; /* 0x00000007ff040219 */
/* 0x088fe40000011602 */
/*0ba0*/ @P0 SHF.R.U32.HI R2, RZ, R7, R3 ; /* 0x00000007ff020219 */
/* 0x004fe40000011603 */
/*0bb0*/ @P0 SHF.L.U32 R5, R0, R14.reuse, RZ ; /* 0x0000000e00050219 */
/* 0x090fe400000006ff */
/*0bc0*/ @P0 SHF.L.U32 R7, R3, R14, RZ ; /* 0x0000000e03070219 */
/* 0x000fc600000006ff */
/*0bd0*/ @P0 IMAD.IADD R0, R2, 0x1, R5 ; /* 0x0000000102000824 */
/* 0x000fe400078e0205 */
/*0be0*/ @P0 IMAD.IADD R3, R4, 0x1, R7 ; /* 0x0000000104030824 */
/* 0x000fca00078e0207 */
/*0bf0*/ SHF.L.U32.HI R5, R3, 0x2, R0 ; /* 0x0000000203057819 */
/* 0x000fc80000010600 */
/*0c00*/ SHF.R.U32.HI R15, RZ, 0x1f, R5 ; /* 0x0000001fff0f7819 */
/* 0x000fc80000011605 */
/*0c10*/ ISETP.NE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe20003f05270 */
/*0c20*/ IMAD.SHL.U32 R4, R3, 0x4, RZ ; /* 0x0000000403047824 */
/* 0x000fd800078e00ff */
/*0c30*/ @P0 LOP3.LUT R5, RZ, R5, RZ, 0x33, !PT ; /* 0x00000005ff050212 */
/* 0x000fe400078e33ff */
/*0c40*/ @P0 LOP3.LUT R4, RZ, R4, RZ, 0x33, !PT ; /* 0x00000004ff040212 */
/* 0x000fc800078e33ff */
/*0c50*/ I2F.F64.S64 R2, R4 ; /* 0x0000000400027312 */
/* 0x000e640000301c00 */
/*0c60*/ DMUL R2, R2, c[0x2][0x8] ; /* 0x0080020002027a28 */
/* 0x002e620000000000 */
/*0c70*/ LEA.HI R15, R0, R15, RZ, 0x2 ; /* 0x0000000f000f7211 */
/* 0x000fd200078f10ff */
/*0c80*/ F2F.F32.F64 R2, R2 ; /* 0x0000000200027310 */
/* 0x002e620000301000 */
/*0c90*/ @P0 LOP3.LUT R9, R9, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000009090812 */
/* 0x000fe400078e3cff */
/*0ca0*/ IADD3 R0, -R15, RZ, RZ ; /* 0x000000ff0f007210 */
/* 0x000fe40007ffe1ff */
/*0cb0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc60003f05270 */
/*0cc0*/ @P1 IMAD.MOV.U32 R15, RZ, RZ, R0 ; /* 0x000000ffff0f1224 */
/* 0x000fe200078e0000 */
/*0cd0*/ FSEL R14, R2, -R2, !P0 ; /* 0x80000002020e7208 */
/* 0x002fe20004000000 */
/*0ce0*/ BRA 0xd10 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0cf0*/ FMUL R14, RZ, R9 ; /* 0x00000009ff0e7220 */
/* 0x000fe40000400000 */
/*0d00*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e00ff */
/*0d10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0d20*/ IADD3 R15, R15, 0x1, RZ ; /* 0x000000010f0f7810 */
/* 0x000fe20007ffe0ff */
/*0d30*/ FMUL R2, R14, R14 ; /* 0x0000000e0e027220 */
/* 0x000fe20000400000 */
/*0d40*/ SHF.L.U64.HI R8, R11, 0x2, R8 ; /* 0x000000020b087819 */
/* 0x000fe20000010208 */
/*0d50*/ IMAD.MOV.U32 R0, RZ, RZ, -0x46b2bead ; /* 0xb94d4153ff007424 */
/* 0x000fe200078e00ff */
/*0d60*/ LOP3.LUT P1, RZ, R15, 0x1, RZ, 0xc0, !PT ; /* 0x000000010fff7812 */
/* 0x000fe2000782c0ff */
/*0d70*/ IMAD.SHL.U32 R4, R11, 0x4, RZ ; /* 0x000000040b047824 */
/* 0x000fe200078e00ff */
/*0d80*/ LOP3.LUT P0, RZ, R15, 0x2, RZ, 0xc0, !PT ; /* 0x000000020fff7812 */
/* 0x000fe2000780c0ff */
/*0d90*/ FMUL R17, R17, R10 ; /* 0x0000000a11117220 */
/* 0x000fe20000400000 */
/*0da0*/ FSEL R3, R12, 0.041666727513074874878, !P1 ; /* 0x3d2aaabb0c037808 */
/* 0x000fc40004800000 */
/*0db0*/ FSEL R7, R14, 1, !P1 ; /* 0x3f8000000e077808 */
/* 0x000fe40004800000 */
/*0dc0*/ FSEL R13, -R13, -0.4999999701976776123, !P1 ; /* 0xbeffffff0d0d7808 */
/* 0x000fca0004800100 */
/*0dd0*/ @P1 IMAD.MOV.U32 R5, RZ, RZ, 0x37cbac00 ; /* 0x37cbac00ff051424 */
/* 0x000fc800078e00ff */
/*0de0*/ @P1 FFMA R0, R2, R5, -0.0013887860113754868507 ; /* 0xbab607ed02001423 */
/* 0x000fc80000000005 */
/*0df0*/ FFMA R0, R2.reuse, R0, R3 ; /* 0x0000000002007223 */
/* 0x040fe40000000003 */
/*0e00*/ FFMA R3, R7, R2, RZ ; /* 0x0000000207037223 */
/* 0x000fe400000000ff */
/*0e10*/ FFMA R0, R2, R0, R13 ; /* 0x0000000002007223 */
/* 0x000fe2000000000d */
/*0e20*/ IADD3 R2, P1, R4.reuse, c[0x0][0x170], RZ ; /* 0x00005c0004027a10 */
/* 0x040fe40007f3e0ff */
/*0e30*/ IADD3 R4, P2, R4, c[0x0][0x178], RZ ; /* 0x00005e0004047a10 */
/* 0x000fe20007f5e0ff */
/*0e40*/ FFMA R7, R0, R3, R7 ; /* 0x0000000300077223 */
/* 0x000fe20000000007 */
/*0e50*/ IADD3.X R3, R8.reuse, c[0x0][0x174], RZ, P1, !PT ; /* 0x00005d0008037a10 */
/* 0x040fe40000ffe4ff */
/*0e60*/ IADD3.X R5, R8, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f0008057a10 */
/* 0x000fe200017fe4ff */
/*0e70*/ @P0 FFMA R7, R7, -1, RZ ; /* 0xbf80000007070823 */
/* 0x000fc400000000ff */
/*0e80*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x000fe4000c101906 */
/*0e90*/ FMUL R7, R7, R10 ; /* 0x0000000a07077220 */
/* 0x000fca0000400000 */
/*0ea0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*0eb0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ec0*/ LOP3.LUT P1, RZ, R10, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0aff7812 */
/* 0x000fda000782c0ff */
/*0ed0*/ @!P1 MOV R3, R10 ; /* 0x0000000a00039202 */
/* 0x000fe20000000f00 */
/*0ee0*/ @!P1 BRA 0xff0 ; /* 0x0000010000009947 */
/* 0x000fea0003800000 */
/*0ef0*/ FSETP.GEU.FTZ.AND P1, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fda0003f3e000 */
/*0f00*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, 0x7fffffff ; /* 0x7fffffffff039424 */
/* 0x000fe200078e00ff */
/*0f10*/ @!P1 BRA 0xff0 ; /* 0x000000d000009947 */
/* 0x000fea0003800000 */
/*0f20*/ FSETP.GTU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f3c200 */
/*0f30*/ @P1 FADD.FTZ R3, R10, 1 ; /* 0x3f8000000a031421 */
/* 0x000fe20000010000 */
/*0f40*/ @P1 BRA 0xff0 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0f50*/ FSETP.NEU.FTZ.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fda0003f3d200 */
/*0f60*/ @P1 FFMA R4, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a041823 */
/* 0x000fc800000000ff */
/*0f70*/ @P1 MUFU.RSQ R3, R4 ; /* 0x0000000400031308 */
/* 0x000e240000001400 */
/*0f80*/ @P1 FMUL.FTZ R5, R4, R3 ; /* 0x0000000304051220 */
/* 0x001fe40000410000 */
/*0f90*/ @P1 FMUL.FTZ R7, R3, 0.5 ; /* 0x3f00000003071820 */
/* 0x000fe40000410000 */
/*0fa0*/ @P1 FADD.FTZ R6, -R5.reuse, -RZ ; /* 0x800000ff05061221 */
/* 0x040fe40000010100 */
/*0fb0*/ @!P1 IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff039224 */
/* 0x000fe400078e000a */
/*0fc0*/ @P1 FFMA R6, R5, R6, R4 ; /* 0x0000000605061223 */
/* 0x000fc80000000004 */
/*0fd0*/ @P1 FFMA R6, R6, R7, R5 ; /* 0x0000000706061223 */
/* 0x000fc80000000005 */
/*0fe0*/ @P1 FMUL.FTZ R3, R6, 2.3283064365386962891e-10 ; /* 0x2f80000006031820 */
/* 0x000fe40000410000 */
/*0ff0*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe400078e000c */
/*1000*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*1010*/ RET.REL.NODEC R4 0x0 ; /* 0xffffefe004007950 */
/* 0x000fea0003c3ffff */
/*1020*/ BRA 0x1020; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*10f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <cuda_runtime.h>
#define PI 3.14159265358979323846
#define N 100000
#define BLOCK_SIZE 1024
__device__ void BoxMuller(float u1, float u2, float *n1, float *n2)
{
float r = sqrtf(-2*logf(u1));
float theta = 2*PI*(u2);
*n1 = r*sinf(theta);
*n2 = r*cosf(theta);
}
__global__ void norm_transform(float *dev_u1, float *dev_u2,
float *dev_n1, float *dev_n2, int size)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < size)
{
float res1;
float res2;
BoxMuller(dev_u1[tid], dev_u2[tid], &res1, &res2);
dev_n1[tid] = res1;
dev_n2[tid] = res2;
}
}
int main()
{
int dev_count;
cudaGetDeviceCount(&dev_count);
printf("Number of CUDA-capable devices: %d.\n", dev_count);
cudaDeviceProp dev_prop;
for (int j=0; j<dev_count; j++)
{
cudaGetDeviceProperties(&dev_prop, j);
printf("Device number %d has max %d threads per block.\n", j, dev_prop.maxThreadsPerBlock);
printf("Device number %d has %d multiprocessors.\n", j, dev_prop.multiProcessorCount);
}
int i;
curandGenerator_t gen1, gen2;
float *dev_u1, *dev_u2, *host_u1, *host_u2;
float *dev_n1, *dev_n2, *host_n1, *host_n2;
// allocate memory on the host
//host_u1 = (float*)calloc(N, sizeof(float));
//host_u2 = (float*)calloc(N, sizeof(float));
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
host_n1 = (float*)calloc(N, sizeof(float));
host_n2 = (float*)calloc(N, sizeof(float));
// allocate memory on the device
cudaMalloc((void**)&dev_u1, N * sizeof(float));
cudaMalloc((void**)&dev_u2, N * sizeof(float));
cudaMalloc((void**)&dev_n1, N * sizeof(float));
cudaMalloc((void**)&dev_n2, N * sizeof(float));
// create a mersenne twister
curandCreateGenerator(&gen1, CURAND_RNG_PSEUDO_MTGP32);
curandCreateGenerator(&gen2, CURAND_RNG_PSEUDO_MTGP32);
// set seed
curandGenerateUniform(gen1, dev_u1, N);
curandGenerateUniform(gen2, dev_u2, N);
int numBlocks = ceil(float(N) / BLOCK_SIZE);
// box muller transform
norm_transform<<<numBlocks, BLOCK_SIZE>>>(dev_u1, dev_u2, dev_n1, dev_n2, N);
// copy device memory to host
cudaMemcpy(host_n1, dev_n1, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(host_n2, dev_n2, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("Time elapsed to generate 2 x %d normal variables: %f seconds.\n", N, elapsedTime/1000.0);
printf("Random normal draws: \n");
for (i = 0; i < 10; i++)
{
printf(" %1.4f %1.4f\n", host_n1[i], host_n2[i]);
}
printf("\n");
curandDestroyGenerator(gen1);
curandDestroyGenerator(gen2);
cudaDeviceReset();
free(host_n1);
free(host_n2);
return 0;
}
|
.file "tmpxft_001459b8_00000000-6_monte_carlo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9BoxMullerffPfS_
.type _Z9BoxMullerffPfS_, @function
_Z9BoxMullerffPfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9BoxMullerffPfS_, .-_Z9BoxMullerffPfS_
.globl _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
.type _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i, @function
_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14norm_transformPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i, .-_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
.globl _Z14norm_transformPfS_S_S_i
.type _Z14norm_transformPfS_S_S_i, @function
_Z14norm_transformPfS_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14norm_transformPfS_S_S_i, .-_Z14norm_transformPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Number of CUDA-capable devices: %d.\n"
.align 8
.LC1:
.string "Device number %d has max %d threads per block.\n"
.align 8
.LC2:
.string "Device number %d has %d multiprocessors.\n"
.align 8
.LC4:
.string "Time elapsed to generate 2 x %d normal variables: %f seconds.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Random normal draws: \n"
.LC6:
.string " %1.4f %1.4f\n"
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1144, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L14
movl $0, %ebx
leaq 96(%rsp), %r13
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %rbp
.L15:
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 484(%rsp), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L15
.L14:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, %esi
movl $100000, %edi
call calloc@PLT
movq %rax, %r12
movl $4, %esi
movl $100000, %edi
call calloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $141, %esi
call curandCreateGenerator@PLT
leaq 16(%rsp), %rdi
movl $141, %esi
call curandCreateGenerator@PLT
movl $100000, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniform@PLT
movl $100000, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call curandGenerateUniform@PLT
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $98, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movl $2, %ecx
movl $400000, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $400000, %edx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 84(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 84(%rsp), %xmm0
divsd .LC3(%rip), %xmm0
movl $100000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC6(%rip), %r13
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%rbx), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L17
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call curandDestroyGenerator@PLT
movq 16(%rsp), %rdi
call curandDestroyGenerator@PLT
call cudaDeviceReset@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl $100000, %r8d
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z14norm_transformPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z14norm_transformPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#include <curand.h>
#include <cuda_runtime.h>
#define PI 3.14159265358979323846
#define N 100000
#define BLOCK_SIZE 1024
__device__ void BoxMuller(float u1, float u2, float *n1, float *n2)
{
float r = sqrtf(-2*logf(u1));
float theta = 2*PI*(u2);
*n1 = r*sinf(theta);
*n2 = r*cosf(theta);
}
__global__ void norm_transform(float *dev_u1, float *dev_u2,
float *dev_n1, float *dev_n2, int size)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < size)
{
float res1;
float res2;
BoxMuller(dev_u1[tid], dev_u2[tid], &res1, &res2);
dev_n1[tid] = res1;
dev_n2[tid] = res2;
}
}
int main()
{
int dev_count;
cudaGetDeviceCount(&dev_count);
printf("Number of CUDA-capable devices: %d.\n", dev_count);
cudaDeviceProp dev_prop;
for (int j=0; j<dev_count; j++)
{
cudaGetDeviceProperties(&dev_prop, j);
printf("Device number %d has max %d threads per block.\n", j, dev_prop.maxThreadsPerBlock);
printf("Device number %d has %d multiprocessors.\n", j, dev_prop.multiProcessorCount);
}
int i;
curandGenerator_t gen1, gen2;
float *dev_u1, *dev_u2, *host_u1, *host_u2;
float *dev_n1, *dev_n2, *host_n1, *host_n2;
// allocate memory on the host
//host_u1 = (float*)calloc(N, sizeof(float));
//host_u2 = (float*)calloc(N, sizeof(float));
float elapsedTime;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
host_n1 = (float*)calloc(N, sizeof(float));
host_n2 = (float*)calloc(N, sizeof(float));
// allocate memory on the device
cudaMalloc((void**)&dev_u1, N * sizeof(float));
cudaMalloc((void**)&dev_u2, N * sizeof(float));
cudaMalloc((void**)&dev_n1, N * sizeof(float));
cudaMalloc((void**)&dev_n2, N * sizeof(float));
// create a mersenne twister
curandCreateGenerator(&gen1, CURAND_RNG_PSEUDO_MTGP32);
curandCreateGenerator(&gen2, CURAND_RNG_PSEUDO_MTGP32);
// set seed
curandGenerateUniform(gen1, dev_u1, N);
curandGenerateUniform(gen2, dev_u2, N);
int numBlocks = ceil(float(N) / BLOCK_SIZE);
// box muller transform
norm_transform<<<numBlocks, BLOCK_SIZE>>>(dev_u1, dev_u2, dev_n1, dev_n2, N);
// copy device memory to host
cudaMemcpy(host_n1, dev_n1, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(host_n2, dev_n2, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
printf("Time elapsed to generate 2 x %d normal variables: %f seconds.\n", N, elapsedTime/1000.0);
printf("Random normal draws: \n");
for (i = 0; i < 10; i++)
{
printf(" %1.4f %1.4f\n", host_n1[i], host_n2[i]);
}
printf("\n");
curandDestroyGenerator(gen1);
curandDestroyGenerator(gen2);
cudaDeviceReset();
free(host_n1);
free(host_n2);
return 0;
}
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#define PI 3.14159265358979323846
#define N 100000
#define BLOCK_SIZE 1024
__device__ void BoxMuller(float u1, float u2, float *n1, float *n2)
{
float r = sqrtf(-2*logf(u1));
float theta = 2*PI*(u2);
*n1 = r*sinf(theta);
*n2 = r*cosf(theta);
}
__global__ void norm_transform(float *dev_u1, float *dev_u2,
float *dev_n1, float *dev_n2, int size)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < size)
{
float res1;
float res2;
BoxMuller(dev_u1[tid], dev_u2[tid], &res1, &res2);
dev_n1[tid] = res1;
dev_n2[tid] = res2;
}
}
int main()
{
int dev_count;
hipGetDeviceCount(&dev_count);
printf("Number of CUDA-capable devices: %d.\n", dev_count);
hipDeviceProp_t dev_prop;
for (int j=0; j<dev_count; j++)
{
hipGetDeviceProperties(&dev_prop, j);
printf("Device number %d has max %d threads per block.\n", j, dev_prop.maxThreadsPerBlock);
printf("Device number %d has %d multiprocessors.\n", j, dev_prop.multiProcessorCount);
}
int i;
hiprandGenerator_t gen1, gen2;
float *dev_u1, *dev_u2, *host_u1, *host_u2;
float *dev_n1, *dev_n2, *host_n1, *host_n2;
// allocate memory on the host
//host_u1 = (float*)calloc(N, sizeof(float));
//host_u2 = (float*)calloc(N, sizeof(float));
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
host_n1 = (float*)calloc(N, sizeof(float));
host_n2 = (float*)calloc(N, sizeof(float));
// allocate memory on the device
hipMalloc((void**)&dev_u1, N * sizeof(float));
hipMalloc((void**)&dev_u2, N * sizeof(float));
hipMalloc((void**)&dev_n1, N * sizeof(float));
hipMalloc((void**)&dev_n2, N * sizeof(float));
// create a mersenne twister
hiprandCreateGenerator(&gen1, HIPRAND_RNG_PSEUDO_MTGP32);
hiprandCreateGenerator(&gen2, HIPRAND_RNG_PSEUDO_MTGP32);
// set seed
hiprandGenerateUniform(gen1, dev_u1, N);
hiprandGenerateUniform(gen2, dev_u2, N);
int numBlocks = ceil(float(N) / BLOCK_SIZE);
// box muller transform
norm_transform<<<numBlocks, BLOCK_SIZE>>>(dev_u1, dev_u2, dev_n1, dev_n2, N);
// copy device memory to host
hipMemcpy(host_n1, dev_n1, N * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(host_n2, dev_n2, N * sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("Time elapsed to generate 2 x %d normal variables: %f seconds.\n", N, elapsedTime/1000.0);
printf("Random normal draws: \n");
for (i = 0; i < 10; i++)
{
printf(" %1.4f %1.4f\n", host_n1[i], host_n2[i]);
}
printf("\n");
hiprandDestroyGenerator(gen1);
hiprandDestroyGenerator(gen2);
hipDeviceReset();
free(host_n1);
free(host_n2);
return 0;
}
|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#define PI 3.14159265358979323846
#define N 100000
#define BLOCK_SIZE 1024
__device__ void BoxMuller(float u1, float u2, float *n1, float *n2)
{
float r = sqrtf(-2*logf(u1));
float theta = 2*PI*(u2);
*n1 = r*sinf(theta);
*n2 = r*cosf(theta);
}
__global__ void norm_transform(float *dev_u1, float *dev_u2,
float *dev_n1, float *dev_n2, int size)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < size)
{
float res1;
float res2;
BoxMuller(dev_u1[tid], dev_u2[tid], &res1, &res2);
dev_n1[tid] = res1;
dev_n2[tid] = res2;
}
}
int main()
{
int dev_count;
hipGetDeviceCount(&dev_count);
printf("Number of CUDA-capable devices: %d.\n", dev_count);
hipDeviceProp_t dev_prop;
for (int j=0; j<dev_count; j++)
{
hipGetDeviceProperties(&dev_prop, j);
printf("Device number %d has max %d threads per block.\n", j, dev_prop.maxThreadsPerBlock);
printf("Device number %d has %d multiprocessors.\n", j, dev_prop.multiProcessorCount);
}
int i;
hiprandGenerator_t gen1, gen2;
float *dev_u1, *dev_u2, *host_u1, *host_u2;
float *dev_n1, *dev_n2, *host_n1, *host_n2;
// allocate memory on the host
//host_u1 = (float*)calloc(N, sizeof(float));
//host_u2 = (float*)calloc(N, sizeof(float));
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
host_n1 = (float*)calloc(N, sizeof(float));
host_n2 = (float*)calloc(N, sizeof(float));
// allocate memory on the device
hipMalloc((void**)&dev_u1, N * sizeof(float));
hipMalloc((void**)&dev_u2, N * sizeof(float));
hipMalloc((void**)&dev_n1, N * sizeof(float));
hipMalloc((void**)&dev_n2, N * sizeof(float));
// create a mersenne twister
hiprandCreateGenerator(&gen1, HIPRAND_RNG_PSEUDO_MTGP32);
hiprandCreateGenerator(&gen2, HIPRAND_RNG_PSEUDO_MTGP32);
// set seed
hiprandGenerateUniform(gen1, dev_u1, N);
hiprandGenerateUniform(gen2, dev_u2, N);
int numBlocks = ceil(float(N) / BLOCK_SIZE);
// box muller transform
norm_transform<<<numBlocks, BLOCK_SIZE>>>(dev_u1, dev_u2, dev_n1, dev_n2, N);
// copy device memory to host
hipMemcpy(host_n1, dev_n1, N * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(host_n2, dev_n2, N * sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("Time elapsed to generate 2 x %d normal variables: %f seconds.\n", N, elapsedTime/1000.0);
printf("Random normal draws: \n");
for (i = 0; i < 10; i++)
{
printf(" %1.4f %1.4f\n", host_n1[i], host_n2[i]);
}
printf("\n");
hiprandDestroyGenerator(gen1);
hiprandDestroyGenerator(gen2);
hipDeviceReset();
free(host_n1);
free(host_n2);
return 0;
}
|
.text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14norm_transformPfS_S_S_i
.globl _Z14norm_transformPfS_S_S_i
.p2align 8
.type _Z14norm_transformPfS_S_S_i,@function
_Z14norm_transformPfS_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_10
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s3, 0x401921fb
s_mov_b32 s2, 0x54442d18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v4, v[3:4], off
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e32 v[5:6], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[5:6], v[5:6], s[2:3]
v_cvt_f32_f64_e32 v0, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v3, 0x7fffffff, v0
v_cmp_ngt_f32_e64 s4, 0x48000000, |v0|
s_and_saveexec_b32 s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s5, exec_lo, s2
s_cbranch_execz .LBB0_3
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v7, 0
v_and_or_b32 v15, v3, s2, 0x800000
v_lshrrev_b32_e32 v12, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[5:6], null, v15, 0xfe5163ab, 0
v_add_nc_u32_e32 v13, 0xffffff88, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v13
v_mad_u64_u32 v[8:9], null, v15, 0x3c439041, v[6:7]
v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v6, v9
v_add_nc_u32_e32 v14, v14, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[9:10], null, v15, 0xdb629599, v[6:7]
v_cmp_lt_u32_e64 s2, 31, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v16, 0, 0xffffffe0, s2
v_dual_mov_b32 v6, v10 :: v_dual_cndmask_b32 v5, v9, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v16, v16, v14
v_mad_u64_u32 v[10:11], null, v15, 0xf534ddc0, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v16
v_mov_b32_e32 v6, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v8, v10, v8, vcc_lo
v_mad_u64_u32 v[11:12], null, v15, 0xfc2757d1, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v8, v5, s2
v_mov_b32_e32 v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[12:13], null, v15, 0x4e441529, v[6:7]
v_mov_b32_e32 v6, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[13:14], null, v15, 0xa2f9836e, v[6:7]
v_cndmask_b32_e64 v6, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v7, v12, v10 :: v_dual_add_nc_u32 v6, v6, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v13, v13, v11 :: v_dual_cndmask_b32 v12, v14, v12
v_cndmask_b32_e32 v11, v11, v9, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v10, v13, v7, s2
v_cndmask_b32_e64 v12, v12, v13, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v7, v7, v11, s2
v_sub_nc_u32_e32 v13, 32, v6
v_cndmask_b32_e64 v11, v11, v8, s2
v_cndmask_b32_e64 v12, v12, v10, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v10, v10, v7, s3
v_cndmask_b32_e64 v7, v7, v11, s3
v_cndmask_b32_e64 v5, v11, v5, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v14, v12, v10, v13
v_alignbit_b32 v9, v10, v7, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v6, v14, v12, vcc_lo
v_alignbit_b32 v12, v7, v5, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v8, v9, v10, vcc_lo
v_bfe_u32 v9, v6, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v12, v7, vcc_lo
v_alignbit_b32 v10, v6, v8, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v11, 0, v9
v_alignbit_b32 v8, v8, v7, 30
v_alignbit_b32 v5, v7, v5, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v10, v10, v11
v_xor_b32_e32 v7, v8, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v5, v5, v11
v_clz_i32_u32_e32 v12, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v12, 32, v12
v_sub_nc_u32_e32 v8, 31, v12
v_lshlrev_b32_e32 v14, 23, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v10, v10, v7, v8
v_alignbit_b32 v5, v7, v5, v8
v_lshrrev_b32_e32 v8, 29, v6
v_alignbit_b32 v7, v10, v5, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v8, 31, v8
v_lshrrev_b32_e32 v10, 9, v10
v_clz_i32_u32_e32 v11, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v13, 0.5, v8
v_min_u32_e32 v11, 32, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v13, v13, v14
v_sub_nc_u32_e32 v15, 31, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v5, v7, v5, v15
v_or_b32_e32 v7, v10, v13
v_add_lshl_u32 v10, v11, v12, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v5, 9, v5
v_mul_f32_e32 v11, 0x3fc90fda, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v5, v5, v10
v_fma_f32 v10, v7, 0x3fc90fda, -v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 0x33000000, v5
v_fmamk_f32 v7, v7, 0x33a22168, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v5, v5, v8
v_fmac_f32_e32 v7, 0x3fc90fda, v5
v_lshrrev_b32_e32 v6, 30, v6
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v5, v11, v7 :: v_dual_add_nc_u32 v6, v9, v6
.LBB0_3:
s_and_not1_saveexec_b32 s2, s5
v_mul_f32_e64 v5, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v6, v5
v_fma_f32 v5, v6, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v5, v6, 0xb3a22168, v5
v_fmamk_f32 v5, v6, 0xa7c234c4, v5
v_cvt_i32_f32_e32 v6, v6
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s4, exec_lo, s2
s_cbranch_execz .LBB0_7
s_mov_b32 s2, 0x7fffff
v_mov_b32_e32 v9, 0
v_and_or_b32 v17, v3, s2, 0x800000
v_lshrrev_b32_e32 v14, 23, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[7:8], null, v17, 0xfe5163ab, 0
v_add_nc_u32_e32 v15, 0xffffff88, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_u32_e32 vcc_lo, 63, v15
v_mad_u64_u32 v[10:11], null, v17, 0x3c439041, v[8:9]
v_cndmask_b32_e64 v16, 0, 0xffffffc0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v8, v11
v_add_nc_u32_e32 v16, v16, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[11:12], null, v17, 0xdb629599, v[8:9]
v_cmp_lt_u32_e64 s2, 31, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v18, 0, 0xffffffe0, s2
v_dual_mov_b32 v8, v12 :: v_dual_cndmask_b32 v7, v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v18, v18, v16
v_mad_u64_u32 v[12:13], null, v17, 0xf534ddc0, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_lt_u32_e64 s3, 31, v18
v_mov_b32_e32 v8, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v10, v12, v10, vcc_lo
v_mad_u64_u32 v[13:14], null, v17, 0xfc2757d1, v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, v10, v7, s2
v_mov_b32_e32 v8, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[14:15], null, v17, 0x4e441529, v[8:9]
v_mov_b32_e32 v8, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[15:16], null, v17, 0xa2f9836e, v[8:9]
v_cndmask_b32_e64 v8, 0, 0xffffffe0, s3
v_dual_cndmask_b32 v9, v14, v12 :: v_dual_add_nc_u32 v8, v8, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v15, v15, v13 :: v_dual_cndmask_b32 v14, v16, v14
v_cndmask_b32_e32 v13, v13, v11, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, v15, v9, s2
v_cndmask_b32_e64 v14, v14, v15, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, v9, v13, s2
v_sub_nc_u32_e32 v15, 32, v8
v_cndmask_b32_e64 v13, v13, v10, s2
v_cndmask_b32_e64 v14, v14, v12, s3
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, v12, v9, s3
v_cndmask_b32_e64 v9, v9, v13, s3
v_cndmask_b32_e64 v7, v13, v7, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v16, v14, v12, v15
v_alignbit_b32 v11, v12, v9, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v8, v16, v14, vcc_lo
v_alignbit_b32 v14, v9, v7, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v10, v11, v12, vcc_lo
v_bfe_u32 v11, v8, 29, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v14, v9, vcc_lo
v_alignbit_b32 v12, v8, v10, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v13, 0, v11
v_alignbit_b32 v10, v10, v9, 30
v_alignbit_b32 v7, v9, v7, 30
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v12, v12, v13
v_xor_b32_e32 v9, v10, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_xor_b32_e32 v7, v7, v13
v_clz_i32_u32_e32 v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v14, 32, v14
v_sub_nc_u32_e32 v10, 31, v14
v_lshlrev_b32_e32 v16, 23, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_alignbit_b32 v12, v12, v9, v10
v_alignbit_b32 v7, v9, v7, v10
v_lshrrev_b32_e32 v10, 29, v8
v_alignbit_b32 v9, v12, v7, 9
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b32_e32 v10, 31, v10
v_lshrrev_b32_e32 v12, 9, v12
v_clz_i32_u32_e32 v13, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v15, 0.5, v10
v_min_u32_e32 v13, 32, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v15, v15, v16
v_sub_nc_u32_e32 v17, 31, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_alignbit_b32 v7, v9, v7, v17
v_or_b32_e32 v9, v12, v15
v_add_lshl_u32 v12, v13, v14, 23
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v7, 9, v7
v_mul_f32_e32 v13, 0x3fc90fda, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v7, v7, v12
v_fma_f32 v12, v9, 0x3fc90fda, -v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, 0x33000000, v7
v_fmamk_f32 v9, v9, 0x33a22168, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_or_b32_e32 v7, v7, v10
v_fmac_f32_e32 v9, 0x3fc90fda, v7
v_lshrrev_b32_e32 v8, 30, v8
s_delay_alu instid0(VALU_DEP_1)
v_dual_add_f32 v7, v13, v9 :: v_dual_add_nc_u32 v8, v11, v8
.LBB0_7:
s_and_not1_saveexec_b32 s2, s4
v_mul_f32_e64 v7, 0x3f22f983, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v8, v7
v_fma_f32 v7, v8, 0xbfc90fda, |v0|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v7, v8, 0xb3a22168, v7
v_fmamk_f32 v7, v8, 0xa7c234c4, v7
v_cvt_i32_f32_e32 v8, v8
s_or_b32 exec_lo, exec_lo, s2
s_waitcnt vmcnt(0)
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v4
s_mov_b32 s2, 0xb94c1982
s_mov_b32 s3, 0x37d75334
s_load_b128 s[4:7], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_cndmask_b32_e64 v9, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v4, v4, v9 :: v_dual_and_b32 v11, 1, v6
v_log_f32_e32 v4, v4
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v9, 0x3f317217, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v10, v4, 0x3f317217, -v9
v_fmamk_f32 v10, v4, 0x3377d1cf, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v9, v10
v_cndmask_b32_e64 v10, 0, 0x41b17218, vcc_lo
v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v4|
v_cndmask_b32_e32 v4, v4, v9, vcc_lo
v_dual_mul_f32 v9, v5, v5 :: v_dual_lshlrev_b32 v6, 30, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v4, v4, v10 :: v_dual_fmaak_f32 v15, s3, v9, 0xbab64f3b
v_dual_fmaak_f32 v13, s2, v9, 0x3c0881c4 :: v_dual_and_b32 v12, 1, v8
v_dual_mul_f32 v4, -2.0, v4 :: v_dual_fmaak_f32 v15, v9, v15, 0x3d2aabf7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmaak_f32 v13, v9, v13, 0xbe2aaa9d
v_mul_f32_e32 v10, 0x4f800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v13, v9, v13 :: v_dual_and_b32 v6, 0x80000000, v6
v_dual_cndmask_b32 v10, v4, v10 :: v_dual_fmac_f32 v5, v5, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v6, v6, v0
v_sqrt_f32_e32 v14, v10
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v4, v7, v7 :: v_dual_add_nc_u32 v19, 1, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_dual_fmaak_f32 v17, s3, v4, 0xbab64f3b :: v_dual_add_nc_u32 v18, -1, v14
v_fmaak_f32 v16, s2, v4, 0x3c0881c4
v_lshlrev_b32_e32 v8, 30, v8
v_fma_f32 v13, -v19, v14, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_fmaak_f32 v17, v4, v17, 0x3d2aabf7
v_fma_f32 v20, -v18, v14, v10
v_fmaak_f32 v16, v4, v16, 0xbe2aaa9d
v_fmaak_f32 v15, v9, v15, 0xbf000004
v_and_b32_e32 v8, 0x80000000, v8
v_cmp_ge_f32_e64 s0, 0, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_f32_e32 v16, v4, v16
v_fma_f32 v9, v9, v15, 1.0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v14, v14, v18, s0
v_cmp_lt_f32_e64 s0, 0, v13
v_fmac_f32_e32 v7, v7, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v13, v14, v19, s0
v_fmaak_f32 v17, v4, v17, 0xbf000004
v_cmp_eq_u32_e64 s0, 0, v11
v_fma_f32 v4, v4, v17, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, v9, v5, s0
v_cmp_eq_u32_e64 s0, 0, v12
v_xor3_b32 v5, v6, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v4, -v7, v4, s0
v_mul_f32_e32 v7, 0x37800000, v13
v_cmp_class_f32_e64 s0, v0, 0x1f8
v_xor_b32_e32 v0, v8, v4
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v6, v13, v7, vcc_lo
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v10, 0x260
v_cndmask_b32_e64 v5, 0x7fc00000, v5, s0
v_cndmask_b32_e64 v7, 0x7fc00000, v0, s0
v_cndmask_b32_e32 v6, v6, v10, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_mul_f32_e32 v2, v6, v5
v_mul_f32_e32 v5, v6, v7
global_store_b32 v[3:4], v2, off
global_store_b32 v[0:1], v5, off
.LBB0_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14norm_transformPfS_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14norm_transformPfS_S_S_i, .Lfunc_end0-_Z14norm_transformPfS_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14norm_transformPfS_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14norm_transformPfS_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata
|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly.
|
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#define PI 3.14159265358979323846
#define N 100000
#define BLOCK_SIZE 1024
__device__ void BoxMuller(float u1, float u2, float *n1, float *n2)
{
float r = sqrtf(-2*logf(u1));
float theta = 2*PI*(u2);
*n1 = r*sinf(theta);
*n2 = r*cosf(theta);
}
__global__ void norm_transform(float *dev_u1, float *dev_u2,
float *dev_n1, float *dev_n2, int size)
{
int tid = threadIdx.x + blockIdx.x*blockDim.x;
if (tid < size)
{
float res1;
float res2;
BoxMuller(dev_u1[tid], dev_u2[tid], &res1, &res2);
dev_n1[tid] = res1;
dev_n2[tid] = res2;
}
}
int main()
{
int dev_count;
hipGetDeviceCount(&dev_count);
printf("Number of CUDA-capable devices: %d.\n", dev_count);
hipDeviceProp_t dev_prop;
for (int j=0; j<dev_count; j++)
{
hipGetDeviceProperties(&dev_prop, j);
printf("Device number %d has max %d threads per block.\n", j, dev_prop.maxThreadsPerBlock);
printf("Device number %d has %d multiprocessors.\n", j, dev_prop.multiProcessorCount);
}
int i;
hiprandGenerator_t gen1, gen2;
float *dev_u1, *dev_u2, *host_u1, *host_u2;
float *dev_n1, *dev_n2, *host_n1, *host_n2;
// allocate memory on the host
//host_u1 = (float*)calloc(N, sizeof(float));
//host_u2 = (float*)calloc(N, sizeof(float));
float elapsedTime;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
host_n1 = (float*)calloc(N, sizeof(float));
host_n2 = (float*)calloc(N, sizeof(float));
// allocate memory on the device
hipMalloc((void**)&dev_u1, N * sizeof(float));
hipMalloc((void**)&dev_u2, N * sizeof(float));
hipMalloc((void**)&dev_n1, N * sizeof(float));
hipMalloc((void**)&dev_n2, N * sizeof(float));
// create a mersenne twister
hiprandCreateGenerator(&gen1, HIPRAND_RNG_PSEUDO_MTGP32);
hiprandCreateGenerator(&gen2, HIPRAND_RNG_PSEUDO_MTGP32);
// set seed
hiprandGenerateUniform(gen1, dev_u1, N);
hiprandGenerateUniform(gen2, dev_u2, N);
int numBlocks = ceil(float(N) / BLOCK_SIZE);
// box muller transform
norm_transform<<<numBlocks, BLOCK_SIZE>>>(dev_u1, dev_u2, dev_n1, dev_n2, N);
// copy device memory to host
hipMemcpy(host_n1, dev_n1, N * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(host_n2, dev_n2, N * sizeof(float), hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
printf("Time elapsed to generate 2 x %d normal variables: %f seconds.\n", N, elapsedTime/1000.0);
printf("Random normal draws: \n");
for (i = 0; i < 10; i++)
{
printf(" %1.4f %1.4f\n", host_n1[i], host_n2[i]);
}
printf("\n");
hiprandDestroyGenerator(gen1);
hiprandDestroyGenerator(gen2);
hipDeviceReset();
free(host_n1);
free(host_n2);
return 0;
}
|
.text
.file "monte_carlo.hip"
.globl _Z29__device_stub__norm_transformPfS_S_S_i # -- Begin function _Z29__device_stub__norm_transformPfS_S_S_i
.p2align 4, 0x90
.type _Z29__device_stub__norm_transformPfS_S_S_i,@function
_Z29__device_stub__norm_transformPfS_S_S_i: # @_Z29__device_stub__norm_transformPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14norm_transformPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z29__device_stub__norm_transformPfS_S_S_i, .Lfunc_end0-_Z29__device_stub__norm_transformPfS_S_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 1712
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph
leaq 200(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 520(%rsp), %edx
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 588(%rsp), %edx
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100000, %edi # imm = 0x186A0
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $100000, %edi # imm = 0x186A0
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 56(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 48(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 40(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 32(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 72(%rsp), %rdi
movl $403, %esi # imm = 0x193
callq hiprandCreateGenerator
leaq 64(%rsp), %rdi
movl $403, %esi # imm = 0x193
callq hiprandCreateGenerator
movq 72(%rsp), %rdi
movq 56(%rsp), %rsi
movl $100000, %edx # imm = 0x186A0
callq hiprandGenerateUniform
movq 64(%rsp), %rdi
movq 48(%rsp), %rsi
movl $100000, %edx # imm = 0x186A0
callq hiprandGenerateUniform
movabsq $4294967394, %rdi # imm = 0x100000062
leaq 926(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rsi, 128(%rsp)
movl $100000, 28(%rsp) # imm = 0x186A0
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z14norm_transformPfS_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 40(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.3, %edi
movl $100000, %esi # imm = 0x186A0
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.5, %edi
movb $2, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_6
# %bb.7:
movl $10, %edi
callq putchar@PLT
movq 72(%rsp), %rdi
callq hiprandDestroyGenerator
movq 64(%rsp), %rdi
callq hiprandDestroyGenerator
callq hipDeviceReset
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14norm_transformPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14norm_transformPfS_S_S_i,@object # @_Z14norm_transformPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z14norm_transformPfS_S_S_i
.p2align 3, 0x0
_Z14norm_transformPfS_S_S_i:
.quad _Z29__device_stub__norm_transformPfS_S_S_i
.size _Z14norm_transformPfS_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of CUDA-capable devices: %d.\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Device number %d has max %d threads per block.\n"
.size .L.str.1, 48
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device number %d has %d multiprocessors.\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time elapsed to generate 2 x %d normal variables: %f seconds.\n"
.size .L.str.3, 63
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " %1.4f %1.4f\n"
.size .L.str.5, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14norm_transformPfS_S_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Random normal draws: "
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__norm_transformPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14norm_transformPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly.
|
.file "tmpxft_001459b8_00000000-6_monte_carlo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9BoxMullerffPfS_
.type _Z9BoxMullerffPfS_, @function
_Z9BoxMullerffPfS_:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z9BoxMullerffPfS_, .-_Z9BoxMullerffPfS_
.globl _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
.type _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i, @function
_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14norm_transformPfS_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i, .-_Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
.globl _Z14norm_transformPfS_S_S_i
.type _Z14norm_transformPfS_S_S_i, @function
_Z14norm_transformPfS_S_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z14norm_transformPfS_S_S_i, .-_Z14norm_transformPfS_S_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Number of CUDA-capable devices: %d.\n"
.align 8
.LC1:
.string "Device number %d has max %d threads per block.\n"
.align 8
.LC2:
.string "Device number %d has %d multiprocessors.\n"
.align 8
.LC4:
.string "Time elapsed to generate 2 x %d normal variables: %f seconds.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "Random normal draws: \n"
.LC6:
.string " %1.4f %1.4f\n"
.LC7:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $1144, %rsp
.cfi_def_cfa_offset 1184
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L14
movl $0, %ebx
leaq 96(%rsp), %r13
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %rbp
.L15:
movl %ebx, %esi
movq %r13, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 416(%rsp), %ecx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 484(%rsp), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 4(%rsp)
jg .L15
.L14:
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movl $4, %esi
movl $100000, %edi
call calloc@PLT
movq %rax, %r12
movl $4, %esi
movl $100000, %edi
call calloc@PLT
movq %rax, %rbp
leaq 24(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $400000, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $141, %esi
call curandCreateGenerator@PLT
leaq 16(%rsp), %rdi
movl $141, %esi
call curandCreateGenerator@PLT
movl $100000, %edx
movq 24(%rsp), %rsi
movq 8(%rsp), %rdi
call curandGenerateUniform@PLT
movl $100000, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call curandGenerateUniform@PLT
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $98, 72(%rsp)
movl $1, 76(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L22
.L16:
movl $2, %ecx
movl $400000, %edx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $400000, %edx
movq 48(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 84(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 56(%rsp), %rdi
call cudaEventDestroy@PLT
movq 64(%rsp), %rdi
call cudaEventDestroy@PLT
pxor %xmm0, %xmm0
cvtss2sd 84(%rsp), %xmm0
divsd .LC3(%rip), %xmm0
movl $100000, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
leaq .LC6(%rip), %r13
.L17:
pxor %xmm0, %xmm0
cvtss2sd (%r12,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 0(%rbp,%rbx), %xmm1
movq %r13, %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L17
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call curandDestroyGenerator@PLT
movq 16(%rsp), %rdi
call curandDestroyGenerator@PLT
call cudaDeviceReset@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L23
movl $0, %eax
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L22:
.cfi_restore_state
movl $100000, %r8d
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z41__device_stub__Z14norm_transformPfS_S_S_iPfS_S_S_i
jmp .L16
.L23:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z14norm_transformPfS_S_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z14norm_transformPfS_S_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4:
|
.text
.file "monte_carlo.hip"
.globl _Z29__device_stub__norm_transformPfS_S_S_i # -- Begin function _Z29__device_stub__norm_transformPfS_S_S_i
.p2align 4, 0x90
.type _Z29__device_stub__norm_transformPfS_S_S_i,@function
_Z29__device_stub__norm_transformPfS_S_S_i: # @_Z29__device_stub__norm_transformPfS_S_S_i
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14norm_transformPfS_S_S_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z29__device_stub__norm_transformPfS_S_S_i, .Lfunc_end0-_Z29__device_stub__norm_transformPfS_S_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 1712
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rdi
callq hipGetDeviceCount
movl 4(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB1_3
# %bb.1: # %.lr.ph
leaq 200(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB1_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 520(%rsp), %edx
movl $.L.str.1, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
movl 588(%rsp), %edx
movl $.L.str.2, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
incl %ebp
cmpl 4(%rsp), %ebp
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movl $100000, %edi # imm = 0x186A0
movl $4, %esi
callq calloc
movq %rax, %rbx
movl $100000, %edi # imm = 0x186A0
movl $4, %esi
callq calloc
movq %rax, %r14
leaq 56(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 48(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 40(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 32(%rsp), %rdi
movl $400000, %esi # imm = 0x61A80
callq hipMalloc
leaq 72(%rsp), %rdi
movl $403, %esi # imm = 0x193
callq hiprandCreateGenerator
leaq 64(%rsp), %rdi
movl $403, %esi # imm = 0x193
callq hiprandCreateGenerator
movq 72(%rsp), %rdi
movq 56(%rsp), %rsi
movl $100000, %edx # imm = 0x186A0
callq hiprandGenerateUniform
movq 64(%rsp), %rdi
movq 48(%rsp), %rsi
movl $100000, %edx # imm = 0x186A0
callq hiprandGenerateUniform
movabsq $4294967394, %rdi # imm = 0x100000062
leaq 926(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq %rax, 152(%rsp)
movq %rcx, 144(%rsp)
movq %rdx, 136(%rsp)
movq %rsi, 128(%rsp)
movl $100000, 28(%rsp) # imm = 0x186A0
leaq 152(%rsp), %rax
movq %rax, 160(%rsp)
leaq 144(%rsp), %rax
movq %rax, 168(%rsp)
leaq 136(%rsp), %rax
movq %rax, 176(%rsp)
leaq 128(%rsp), %rax
movq %rax, 184(%rsp)
leaq 28(%rsp), %rax
movq %rax, 192(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z14norm_transformPfS_S_S_i, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 40(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movl $400000, %edx # imm = 0x61A80
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.3, %edi
movl $100000, %esi # imm = 0x186A0
movb $1, %al
callq printf
movl $.Lstr, %edi
callq puts@PLT
.p2align 4, 0x90
.LBB1_6: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movss (%r14,%r15,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movl $.L.str.5, %edi
movb $2, %al
callq printf
incq %r15
cmpq $10, %r15
jne .LBB1_6
# %bb.7:
movl $10, %edi
callq putchar@PLT
movq 72(%rsp), %rdi
callq hiprandDestroyGenerator
movq 64(%rsp), %rdi
callq hiprandDestroyGenerator
callq hipDeviceReset
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $1672, %rsp # imm = 0x688
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14norm_transformPfS_S_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14norm_transformPfS_S_S_i,@object # @_Z14norm_transformPfS_S_S_i
.section .rodata,"a",@progbits
.globl _Z14norm_transformPfS_S_S_i
.p2align 3, 0x0
_Z14norm_transformPfS_S_S_i:
.quad _Z29__device_stub__norm_transformPfS_S_S_i
.size _Z14norm_transformPfS_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Number of CUDA-capable devices: %d.\n"
.size .L.str, 37
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Device number %d has max %d threads per block.\n"
.size .L.str.1, 48
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device number %d has %d multiprocessors.\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time elapsed to generate 2 x %d normal variables: %f seconds.\n"
.size .L.str.3, 63
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " %1.4f %1.4f\n"
.size .L.str.5, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14norm_transformPfS_S_S_i"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Random normal draws: "
.size .Lstr, 22
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__norm_transformPfS_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14norm_transformPfS_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_
|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code.
|
/*
* Solves the Panfilov model using an explicit numerical scheme.
* Based on code orginally provided by Xing Cai, Simula Research Laboratory
* and reimplementation by Scott B. Baden, UCSD
*
* Modified and restructured by Didem Unat, Koc University
*
* Refer to "Detailed Numerical Analyses of the Aliev-Panfilov Model on GPGPU"
* https://www.simula.no/publications/detailed-numerical-analyses-aliev-panfilov-model-gpgpu
* by Xing Cai, Didem Unat and Scott Baden
*
*/
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <iostream>
#include <iomanip>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <getopt.h>
using namespace std;
#define TILE_DIM 32
#define kk 8.0
#define a 0.1
#define epsilon 0.01
#define M1 0.07
#define M2 0.3
#define b 0.1
#define d 5e-5
// For Command Line Args
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads);
// Timer: Make successive calls and take a difference to get the elapsed time.
double getTime();
// Allocate a 2D array
double **alloc2D(int m, int n);
// Mirror Ghost Boundries
void mirrorBoundries(double *E_prev_1D, const int n, const int m, const int WIDTH);
void mirrorBoundries(double *E_prev_1D, double* d_E_prev_1D, const int n, const int m, const int WIDTH);
/*
Reports statistics about the computation
These values should not vary (except to within roundoff)
when we use different numbers of processes to solve the problem
*/
double stats(double **E, int m, int n, double *_mx);
double stats1D(double *E, int m, int n, double *_mx, int WIDTH);
// ============================== Kernels ===========================
__global__ void mirrorkernel(double *E_prev_1D, const int n, const int m, const int WIDTH);
void simV1(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
void simV2(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
void simV3(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
void simV4(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
void simV5(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
// ============================= Exp 1= ===============
// Main Refined -- Versioin 4 Refined --
// Main program
int main(int argc, char **argv)
{
/*
* Solution arrays
* E is the "Excitation" variable, a voltage
* R is the "Recovery" variable
* E_prev is the Excitation variable for the previous timestep,
* and is used in time integration
*/
// For Serial Version
double **E, **R, **E_prev;
// For Host and GPU
double *E_1D, *R_1D, *E_prev_1D;
double *d_E_1D, *d_E_prev_1D, *d_R_1D;
// Various constants - these definitions shouldn't change
double T = 1000.0;
int m = 200, n = 200;
int plot_freq = 0;
int px = 1, py = 1;
int no_comm = 0;
int version = 4;
int WIDTH;
double time_elapsed = 0.0;
// int version = 4;
cmdLine(argc, argv, T, n, px, py, plot_freq, no_comm, version);
m = n;
// Allocate contiguous memory for solution arrays
// The computational box is defined on [1:m+1,1:n+1]
// We pad the arrays in order to facilitate differencing on the
// boundaries of the computation box
int Total_Bytes = (m + 2) * (n + 2) * sizeof(double);
WIDTH = m + 2;
E = alloc2D(m + 2, n + 2);
E_prev = alloc2D(m + 2, n + 2);
R = alloc2D(m + 2, n + 2);
// Allocate space on the host (PINNED Memory)
cudaError_t status = cudaMallocHost(&E_1D, Total_Bytes);
status = cudaMallocHost(&E_prev_1D, Total_Bytes);
status = cudaMallocHost(&R_1D, Total_Bytes);
if (status != cudaSuccess) {
printf("Error allocating pinned host memory\n");
}
// Allocate space on the GPU
cudaMalloc(&d_E_1D, Total_Bytes);
cudaMalloc(&d_E_prev_1D, Total_Bytes);
cudaMalloc(&d_R_1D, Total_Bytes);
int col, row;
// Initialization
for (row = 1; row <= m; row++)
{
for (col = 1; col <= n; col++)
{
E_prev[row][col] = 0;
R[row][col] = 0;
E_prev_1D[row * WIDTH + col] = 0;
R_1D[row * WIDTH + col] = 0;
}
}
for (row = 1; row <= m; row++)
{
for (col = n / 2 + 1; col <= n; col++)
{
E_prev[row][col] = 1.0;
E_prev_1D[row * WIDTH + col] = 1.0;
}
}
for (row = m / 2 + 1; row <= m; row++)
{
for (col = 1; col <= n; col++)
{
R[row][col] = 1.0;
R_1D[row * WIDTH + col] = 1.0;
}
}
double dx = 1.0 / n;
// For time integration, these values shouldn't change
double rp = kk * (b + 1) * (b + 1) / 4;
double dte = (dx * dx) / (d * 4 + ((dx * dx)) * (rp + kk));
double dtr = 1 / (epsilon + ((M1 / M2) * rp));
double dt = (dte < dtr) ? 0.95 * dte : 0.95 * dtr;
double alpha = d * dt / (dx * dx);
int devId = 0;
cudaDeviceProp prop;
cudaGetDeviceProperties(&prop, devId);
printf("\n ******** Device : %s **********\n", prop.name);
cout << "Simulation Version : " << version<<endl;
cout << "Block Size :"<< TILE_DIM <<endl;
cout << "Grid Size : " << n << endl;
cout << "Duration of Sim : " << T << endl;
cout << "Time step dt : " << dt << endl;
cout << "Process geometry: " << px << " x " << py << endl;
if (no_comm)
{
cout << "Communication : DISABLED" << endl;
}
cout << endl;
// Start the timer
//double t0 = getTime();
// Simulated time is different from the integer timestep number
// Simulated time
double t = 0.0;
// Integer timestep number
int niter = 0;
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
cudaMemcpy(d_R_1D, R_1D, Total_Bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, cudaMemcpyHostToDevice);
// very well done
//simV5(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
while (t < T)
{
t += dt;
niter++;
//mirrorBoundries(E_prev_1D, n, m, WIDTH);
//mirrorBoundries(E_prev_1D, d_E_prev_1D,n, m, WIDTH);
mirrorkernel<<<num_blocks, block_size>>>(d_E_prev_1D, n, m ,WIDTH);
cudaStreamSynchronize(0);
//cudaMemcpy(E_prev_1D, d_E_prev_1D, Total_Bytes, cudaMemcpyDeviceToHost);
switch (version){
case 1:
simV1(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
break;
case 2:
simV2(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
break;
case 3:
simV3(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
break;
case 4:
simV4(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
break;
// case 5:
// break;
case 0:
cout<<"\n Implement the Serial Version"<<endl;
break;
default:
cout<<"\nPlease Enter the Correct version"<<endl;
return 0;
}
//cudaMemcpy(d_E_prev_1D, d_E_1D, Total_Bytes, cudaMemcpyDeviceToDevice);
//swap current E with previous E
double **tmp = E;
E = E_prev;
E_prev = tmp;
double *tmp2 = d_E_1D;
d_E_1D = d_E_prev_1D;
d_E_prev_1D = tmp2;
} //end of while loop
cudaMemcpy(E_prev_1D, d_E_prev_1D, Total_Bytes, cudaMemcpyDeviceToHost);
//double time_elapsed = getTime() - t0;
double Gflops = (double)(niter * (1E-9 * n * n) * 28.0) / time_elapsed;
double BW = (double)(niter * 1E-9 * (n * n * sizeof(double) * 4.0)) / time_elapsed;
cout << "Number of Iterations : " << niter << endl;
cout << "Elapsed Time (sec) : " << time_elapsed << endl;
cout << "Sustained Gflops Rate : " << Gflops << endl;
cout << "Sustained Bandwidth (GB/sec): " << BW << endl<< endl;
double mx;
double l2norm = stats(E_prev, m, n, &mx);
cout << "Max: " << mx << " L2norm: " << l2norm << endl;
l2norm = stats1D(E_prev_1D, m, n, &mx, WIDTH);
cout << "Max: " << mx << " L2norm: " << l2norm << " (1D or GPU)" <<endl;
free(E);
free(E_prev);
free(R);
cudaFreeHost(E_1D);
cudaFreeHost(E_prev_1D);
cudaFreeHost(R_1D);
cudaFree(d_E_1D);
cudaFree(d_E_prev_1D);
cudaFree(d_R_1D);
return 0;
}
// ************************************************ Kernels Start ***************************************
__global__ void mirrorkernel(double *E_prev_1D, const int n, const int m, const int WIDTH){
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
//int col, row;
size_t row = blockIdx.y * blockDim.y + threadIdx.y + 1;
size_t col = blockIdx.x * blockDim.x + threadIdx.x + 1;
if (row <= m) {
E_prev_1D[row * WIDTH + 0] = E_prev_1D[row * WIDTH + 2];
E_prev_1D[row * WIDTH + (n + 1)] = E_prev_1D[row * WIDTH + (n - 1)];
}
if (col <= n) {
E_prev_1D[0 * WIDTH + col] = E_prev_1D[2 * WIDTH + col];
E_prev_1D[(m + 1) * WIDTH + col] = E_prev_1D[(m - 1) * WIDTH + col];
}
}
__global__ void simulate_version1_PDE(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
E_1D[row * WIDTH + col] = E_prev_1D[row * WIDTH + col] + alpha * (E_prev_1D[row * WIDTH + (col + 1)] + E_prev_1D[row * WIDTH + (col - 1)] - 4 * E_prev_1D[row * WIDTH + col] + E_prev_1D[(row + 1) * WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
__global__ void simulate_version1_ODE(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
int index = row * WIDTH + col;
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
// checkpoint 2
__global__ void simulate_version2(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
int index = row * WIDTH + col;
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
// PDE
E_1D[row * WIDTH + col] = E_prev_1D[row * WIDTH + col] + alpha * (E_prev_1D[row * WIDTH + (col + 1)] + E_prev_1D[row * WIDTH + (col - 1)] - 4 * E_prev_1D[row * WIDTH + col] + E_prev_1D[(row + 1) * WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
//ODE
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
// checkpoint 1
__global__ void simulate_version3(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
//int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + 1;
int col = blockIdx.x * blockDim.x + threadIdx.x + 1;
int index = row * WIDTH + col;
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
double e_temp; //= E_1D[index];
double r_temp = R_1D[index];
double e_prev_temp = E_prev_1D[index];
// PDE
e_temp = e_prev_temp + alpha * (E_prev_1D[row * WIDTH + (col + 1)] + E_prev_1D[row * WIDTH + (col - 1)] - 4 * e_prev_temp + E_prev_1D[(row + 1) * WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
//ODE
e_temp = e_temp - dt * (kk * e_temp * (e_temp - a) * (e_temp - 1) + e_temp * r_temp);
r_temp = r_temp + dt * (epsilon + M1 * r_temp / (e_temp + M2)) * (-r_temp - kk * e_temp * (e_temp - b - 1));
E_1D[index] = e_temp;
R_1D[index] = r_temp;
}
}
__global__ void simulate_version4(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
// __shared__ double tempR[(TILE_DIM + 2)*(TILE_DIM + 2)];
__shared__ double tempE_prev[(TILE_DIM + 2)*(TILE_DIM + 2)];
size_t LocalWidth = TILE_DIM + 2;
// Global Indexing
size_t row = blockIdx.y * blockDim.y + threadIdx.y + 1;
size_t col = blockIdx.x * blockDim.x + threadIdx.x + 1;
size_t index = row * WIDTH + col;
size_t local_index = (threadIdx.y + 1)* LocalWidth + threadIdx.x + 1;
// copy all
if (row >= 1 && row <= m && col >= 1 && col <= n ){
tempE_prev[local_index] = E_prev_1D[index];
}
// copy Right & Left
if (threadIdx.x + 1 == TILE_DIM){
tempE_prev[local_index+1] = E_prev_1D[index+1];
tempE_prev[local_index-TILE_DIM] = E_prev_1D[index-TILE_DIM];
}
// copy Up & Down
if (threadIdx.y + 1== TILE_DIM){
tempE_prev[local_index + LocalWidth] = E_prev_1D[index + WIDTH];
tempE_prev[local_index - TILE_DIM*LocalWidth] = E_prev_1D[index - TILE_DIM*WIDTH];
}
// Make sure all threads get to this point before proceeding!
__syncthreads(); // This will syncronize threads in a block
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
double e_temp;
double r_temp = R_1D[index];
// PDE
e_temp = tempE_prev[local_index] + alpha * (tempE_prev[local_index + 1] + tempE_prev[local_index- 1] - 4 * tempE_prev[local_index] + tempE_prev[local_index + LocalWidth] + tempE_prev[local_index- LocalWidth]);
//ODE
e_temp = e_temp - dt * (kk * e_temp * (e_temp - a) * (e_temp - 1) + e_temp * r_temp);
r_temp = r_temp + dt * (epsilon + M1 * r_temp / (e_temp + M2)) * (-r_temp - kk * e_temp * (e_temp - b - 1));
E_1D[index] = e_temp;
R_1D[index] = r_temp;
}
}
void simV1(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version1_PDE<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
simulate_version1_ODE<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
cudaStreamSynchronize(0);
// end timer
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
void simV2(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version2<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
cudaStreamSynchronize(0);
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
void simV3(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version3<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
cudaStreamSynchronize(0);
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
void simV4(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version4<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
cudaStreamSynchronize(0);
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
//************************************************* Kernels End *****************************************
// --------------------------------------------- Optimaztion Start-------------------------------------------------
__global__ void simulate_version5(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
int index = row * WIDTH + col;
double t = 0.0;
int niter = 0;
double T = 1000.0;
while (t < T) {
t += dt;
niter++;
if (row <= m) {
E_prev_1D[row * WIDTH + 0] = E_prev_1D[row * WIDTH + 2];
E_prev_1D[row * WIDTH + (n + 1)] = E_prev_1D[row * WIDTH + (n - 1)];
}
if (col <= n) {
E_prev_1D[0 * WIDTH + col] = E_prev_1D[2 * WIDTH + col];
E_prev_1D[(m + 1) * WIDTH + col] = E_prev_1D[(m - 1) * WIDTH + col];
}
__syncthreads();
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
// PDE
E_1D[row * WIDTH + col] = E_prev_1D[row * WIDTH + col] + alpha * (E_prev_1D[row * WIDTH + (col + 1)] + E_prev_1D[row * WIDTH + (col - 1)] - 4 * E_prev_1D[row * WIDTH + col] + E_prev_1D[(row + 1) * WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
//ODE
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
// double *tmp2 = E_1D;
// E_1D = E_prev_1D;
// E_prev_1D = tmp2;
E_prev_1D[index] = E_1D[index];
}
//E_prev_1D[index] = E_1D[index];
//if (row == 1 && col == 1) {
//double *tmp2 = E_1D;
//E_1D = E_prev_1D;
//E_prev_1D = tmp2;
//}
__syncthreads();
}
}
void simV5(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version5<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
cudaStreamSynchronize(0);
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
// --------------------------------------------- Optimation End -------------------------------------------------
//================================================== Utilities =========================================
// Mirror Ghost Boundries
void mirrorBoundries(double *E_prev_1D, double* d_E_prev_1D, const int n, const int m, const int WIDTH){
// ==================================================
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
int Total_Bytes = WIDTH * WIDTH * sizeof(double);
// Copy to GPU
cudaMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, cudaMemcpyHostToDevice);
mirrorkernel<<<num_blocks, block_size>>>(d_E_prev_1D, n, m ,WIDTH);
cudaMemcpy(E_prev_1D, d_E_prev_1D, Total_Bytes, cudaMemcpyDeviceToHost);
}
// Mirror Ghost Boundries
void mirrorBoundries(double *E_prev_1D, const int n, const int m, const int WIDTH)
{
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
int col, row;
for (row = 1; row <= m; row++)
{
//E_prev[row][0] = E_prev[row][2];
E_prev_1D[row * WIDTH + 0] = E_prev_1D[row * WIDTH + 2];
}
for (row = 1; row <= m; row++)
{
//E_prev[row][n + 1] = E_prev[row][n - 1];
E_prev_1D[row * WIDTH + (n + 1)] = E_prev_1D[row * WIDTH + (n - 1)];
}
for (col = 1; col <= n; col++)
{
//E_prev[0][col] = E_prev[2][col];
E_prev_1D[0 * WIDTH + col] = E_prev_1D[2 * WIDTH + col];
}
for (col = 1; col <= n; col++)
{
//E_prev[m + 1][col] = E_prev[m - 1][col];
E_prev_1D[(m + 1) * WIDTH + col] = E_prev_1D[(m - 1) * WIDTH + col];
}
}
// Allocate a 2D array
double **alloc2D(int m, int n)
{
double **E;
int nx = n, ny = m;
E = (double **)malloc(sizeof(double *) * ny + sizeof(double) * nx * ny);
assert(E);
int row;
for (row = 0; row < ny; row++)
E[row] = (double *)(E + ny) + row * nx;
return (E);
}
/* Reports statistics about the computation
These values should not vary (except to within roundoff)
when we use different numbers of processes to solve the problem
*/
double stats(double **E, int m, int n, double *_mx)
{
double mx = -1;
double l2norm = 0;
int col, row;
for (row = 1; row <= m; row++)
for (col = 1; col <= n; col++)
{
l2norm += E[row][col] * E[row][col];
if (E[row][col] > mx)
mx = E[row][col];
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
double stats1D(double *E, int m, int n, double *_mx, int WIDTH)
{
double mx = -1;
double l2norm = 0;
int col, row;
int index = -1;
for (row = 1; row <= m; row++)
{
for (col = 1; col <= n; col++)
{
index = row * WIDTH + col;
l2norm += E[index] * E[index];
if (E[index] > mx)
{
mx = E[index];
}
}
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
// Timer
// Make successive calls and take a difference to get the elapsed time.
static const double kMicro = 1.0e-6;
double getTime()
{
struct timeval TV;
struct timezone TZ;
const int RC = gettimeofday(&TV, &TZ);
if (RC == -1)
{
cerr << "ERROR: Bad call to gettimeofday" << endl;
return (-1);
}
return (((double)TV.tv_sec) + kMicro * ((double)TV.tv_usec));
}
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads)
{
/// Command line arguments
// Default value of the domain sizes
static struct option long_options[] = {
{"n", required_argument, 0, 'n'},
{"px", required_argument, 0, 'x'},
{"py", required_argument, 0, 'y'},
{"tfinal", required_argument, 0, 't'},
{"plot", required_argument, 0, 'p'},
{"nocomm", no_argument, 0, 'k'},
{"numthreads", required_argument, 0, 'o'},
};
// Process command line arguments
int ac;
for (ac = 1; ac < argc; ac++)
{
int c;
while ((c = getopt_long(argc, argv, "n:x:y:t:kp:o:", long_options, NULL)) != -1)
{
switch (c)
{
// Size of the computational box
case 'n':
n = atoi(optarg);
break;
// X processor geometry
case 'x':
px = atoi(optarg);
// Y processor geometry
case 'y':
py = atoi(optarg);
// Length of simulation, in simulated time units
case 't':
T = atof(optarg);
break;
// Turn off communication
case 'k':
no_comm = 1;
break;
// Plot the excitation variable
case 'p':
plot_freq = atoi(optarg);
break;
// Plot the excitation variable
case 'o':
num_threads = atoi(optarg);
break;
// Error
default:
printf("Usage: a.out [-n <domain size>] [-t <final time >]\n\t [-p <plot frequency>]\n\t[-px <x processor geometry> [-py <y proc. geometry] [-k turn off communication] [-o <Number of OpenMP threads>]\n");
exit(-1);
}
}
}
}
|
/*
* Solves the Panfilov model using an explicit numerical scheme.
* Based on code orginally provided by Xing Cai, Simula Research Laboratory
* and reimplementation by Scott B. Baden, UCSD
*
* Modified and restructured by Didem Unat, Koc University
*
* Refer to "Detailed Numerical Analyses of the Aliev-Panfilov Model on GPGPU"
* https://www.simula.no/publications/detailed-numerical-analyses-aliev-panfilov-model-gpgpu
* by Xing Cai, Didem Unat and Scott Baden
*
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <stdlib.h>
#include <iostream>
#include <iomanip>
#include <string.h>
#include <math.h>
#include <sys/time.h>
#include <getopt.h>
using namespace std;
#define TILE_DIM 32
#define kk 8.0
#define a 0.1
#define epsilon 0.01
#define M1 0.07
#define M2 0.3
#define b 0.1
#define d 5e-5
// For Command Line Args
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads);
// Timer: Make successive calls and take a difference to get the elapsed time.
double getTime();
// Allocate a 2D array
double **alloc2D(int m, int n);
// Mirror Ghost Boundries
void mirrorBoundries(double *E_prev_1D, const int n, const int m, const int WIDTH);
void mirrorBoundries(double *E_prev_1D, double* d_E_prev_1D, const int n, const int m, const int WIDTH);
/*
Reports statistics about the computation
These values should not vary (except to within roundoff)
when we use different numbers of processes to solve the problem
*/
double stats(double **E, int m, int n, double *_mx);
double stats1D(double *E, int m, int n, double *_mx, int WIDTH);
// ============================== Kernels ===========================
__global__ void mirrorkernel(double *E_prev_1D, const int n, const int m, const int WIDTH);
void simV1(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
void simV2(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
void simV3(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
void simV4(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
void simV5(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D);
// ============================= Exp 1= ===============
// Main Refined -- Versioin 4 Refined --
// Main program
int main(int argc, char **argv)
{
/*
* Solution arrays
* E is the "Excitation" variable, a voltage
* R is the "Recovery" variable
* E_prev is the Excitation variable for the previous timestep,
* and is used in time integration
*/
// For Serial Version
double **E, **R, **E_prev;
// For Host and GPU
double *E_1D, *R_1D, *E_prev_1D;
double *d_E_1D, *d_E_prev_1D, *d_R_1D;
// Various constants - these definitions shouldn't change
double T = 1000.0;
int m = 200, n = 200;
int plot_freq = 0;
int px = 1, py = 1;
int no_comm = 0;
int version = 4;
int WIDTH;
double time_elapsed = 0.0;
// int version = 4;
cmdLine(argc, argv, T, n, px, py, plot_freq, no_comm, version);
m = n;
// Allocate contiguous memory for solution arrays
// The computational box is defined on [1:m+1,1:n+1]
// We pad the arrays in order to facilitate differencing on the
// boundaries of the computation box
int Total_Bytes = (m + 2) * (n + 2) * sizeof(double);
WIDTH = m + 2;
E = alloc2D(m + 2, n + 2);
E_prev = alloc2D(m + 2, n + 2);
R = alloc2D(m + 2, n + 2);
// Allocate space on the host (PINNED Memory)
hipError_t status = hipHostMalloc(&E_1D, Total_Bytes, hipHostMallocDefault);
status = hipHostMalloc(&E_prev_1D, Total_Bytes, hipHostMallocDefault);
status = hipHostMalloc(&R_1D, Total_Bytes, hipHostMallocDefault);
if (status != hipSuccess) {
printf("Error allocating pinned host memory\n");
}
// Allocate space on the GPU
hipMalloc(&d_E_1D, Total_Bytes);
hipMalloc(&d_E_prev_1D, Total_Bytes);
hipMalloc(&d_R_1D, Total_Bytes);
int col, row;
// Initialization
for (row = 1; row <= m; row++)
{
for (col = 1; col <= n; col++)
{
E_prev[row][col] = 0;
R[row][col] = 0;
E_prev_1D[row * WIDTH + col] = 0;
R_1D[row * WIDTH + col] = 0;
}
}
for (row = 1; row <= m; row++)
{
for (col = n / 2 + 1; col <= n; col++)
{
E_prev[row][col] = 1.0;
E_prev_1D[row * WIDTH + col] = 1.0;
}
}
for (row = m / 2 + 1; row <= m; row++)
{
for (col = 1; col <= n; col++)
{
R[row][col] = 1.0;
R_1D[row * WIDTH + col] = 1.0;
}
}
double dx = 1.0 / n;
// For time integration, these values shouldn't change
double rp = kk * (b + 1) * (b + 1) / 4;
double dte = (dx * dx) / (d * 4 + ((dx * dx)) * (rp + kk));
double dtr = 1 / (epsilon + ((M1 / M2) * rp));
double dt = (dte < dtr) ? 0.95 * dte : 0.95 * dtr;
double alpha = d * dt / (dx * dx);
int devId = 0;
hipDeviceProp_t prop;
hipGetDeviceProperties(&prop, devId);
printf("\n ******** Device : %s **********\n", prop.name);
cout << "Simulation Version : " << version<<endl;
cout << "Block Size :"<< TILE_DIM <<endl;
cout << "Grid Size : " << n << endl;
cout << "Duration of Sim : " << T << endl;
cout << "Time step dt : " << dt << endl;
cout << "Process geometry: " << px << " x " << py << endl;
if (no_comm)
{
cout << "Communication : DISABLED" << endl;
}
cout << endl;
// Start the timer
//double t0 = getTime();
// Simulated time is different from the integer timestep number
// Simulated time
double t = 0.0;
// Integer timestep number
int niter = 0;
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
hipMemcpy(d_R_1D, R_1D, Total_Bytes, hipMemcpyHostToDevice);
hipMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, hipMemcpyHostToDevice);
// very well done
//simV5(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
while (t < T)
{
t += dt;
niter++;
//mirrorBoundries(E_prev_1D, n, m, WIDTH);
//mirrorBoundries(E_prev_1D, d_E_prev_1D,n, m, WIDTH);
mirrorkernel<<<num_blocks, block_size>>>(d_E_prev_1D, n, m ,WIDTH);
hipStreamSynchronize(0);
//cudaMemcpy(E_prev_1D, d_E_prev_1D, Total_Bytes, cudaMemcpyDeviceToHost);
switch (version){
case 1:
simV1(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
break;
case 2:
simV2(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
break;
case 3:
simV3(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
break;
case 4:
simV4(alpha, n, m, dt, WIDTH, &time_elapsed, d_E_1D, d_E_prev_1D, d_R_1D);
break;
// case 5:
// break;
case 0:
cout<<"\n Implement the Serial Version"<<endl;
break;
default:
cout<<"\nPlease Enter the Correct version"<<endl;
return 0;
}
//cudaMemcpy(d_E_prev_1D, d_E_1D, Total_Bytes, cudaMemcpyDeviceToDevice);
//swap current E with previous E
double **tmp = E;
E = E_prev;
E_prev = tmp;
double *tmp2 = d_E_1D;
d_E_1D = d_E_prev_1D;
d_E_prev_1D = tmp2;
} //end of while loop
hipMemcpy(E_prev_1D, d_E_prev_1D, Total_Bytes, hipMemcpyDeviceToHost);
//double time_elapsed = getTime() - t0;
double Gflops = (double)(niter * (1E-9 * n * n) * 28.0) / time_elapsed;
double BW = (double)(niter * 1E-9 * (n * n * sizeof(double) * 4.0)) / time_elapsed;
cout << "Number of Iterations : " << niter << endl;
cout << "Elapsed Time (sec) : " << time_elapsed << endl;
cout << "Sustained Gflops Rate : " << Gflops << endl;
cout << "Sustained Bandwidth (GB/sec): " << BW << endl<< endl;
double mx;
double l2norm = stats(E_prev, m, n, &mx);
cout << "Max: " << mx << " L2norm: " << l2norm << endl;
l2norm = stats1D(E_prev_1D, m, n, &mx, WIDTH);
cout << "Max: " << mx << " L2norm: " << l2norm << " (1D or GPU)" <<endl;
free(E);
free(E_prev);
free(R);
hipHostFree(E_1D);
hipHostFree(E_prev_1D);
hipHostFree(R_1D);
hipFree(d_E_1D);
hipFree(d_E_prev_1D);
hipFree(d_R_1D);
return 0;
}
// ************************************************ Kernels Start ***************************************
__global__ void mirrorkernel(double *E_prev_1D, const int n, const int m, const int WIDTH){
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
//int col, row;
size_t row = blockIdx.y * blockDim.y + threadIdx.y + 1;
size_t col = blockIdx.x * blockDim.x + threadIdx.x + 1;
if (row <= m) {
E_prev_1D[row * WIDTH + 0] = E_prev_1D[row * WIDTH + 2];
E_prev_1D[row * WIDTH + (n + 1)] = E_prev_1D[row * WIDTH + (n - 1)];
}
if (col <= n) {
E_prev_1D[0 * WIDTH + col] = E_prev_1D[2 * WIDTH + col];
E_prev_1D[(m + 1) * WIDTH + col] = E_prev_1D[(m - 1) * WIDTH + col];
}
}
__global__ void simulate_version1_PDE(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
E_1D[row * WIDTH + col] = E_prev_1D[row * WIDTH + col] + alpha * (E_prev_1D[row * WIDTH + (col + 1)] + E_prev_1D[row * WIDTH + (col - 1)] - 4 * E_prev_1D[row * WIDTH + col] + E_prev_1D[(row + 1) * WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
}
}
__global__ void simulate_version1_ODE(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
int index = row * WIDTH + col;
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
// checkpoint 2
__global__ void simulate_version2(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
int index = row * WIDTH + col;
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
// PDE
E_1D[row * WIDTH + col] = E_prev_1D[row * WIDTH + col] + alpha * (E_prev_1D[row * WIDTH + (col + 1)] + E_prev_1D[row * WIDTH + (col - 1)] - 4 * E_prev_1D[row * WIDTH + col] + E_prev_1D[(row + 1) * WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
//ODE
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
}
}
// checkpoint 1
__global__ void simulate_version3(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
//int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + 1;
int col = blockIdx.x * blockDim.x + threadIdx.x + 1;
int index = row * WIDTH + col;
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
double e_temp; //= E_1D[index];
double r_temp = R_1D[index];
double e_prev_temp = E_prev_1D[index];
// PDE
e_temp = e_prev_temp + alpha * (E_prev_1D[row * WIDTH + (col + 1)] + E_prev_1D[row * WIDTH + (col - 1)] - 4 * e_prev_temp + E_prev_1D[(row + 1) * WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
//ODE
e_temp = e_temp - dt * (kk * e_temp * (e_temp - a) * (e_temp - 1) + e_temp * r_temp);
r_temp = r_temp + dt * (epsilon + M1 * r_temp / (e_temp + M2)) * (-r_temp - kk * e_temp * (e_temp - b - 1));
E_1D[index] = e_temp;
R_1D[index] = r_temp;
}
}
__global__ void simulate_version4(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
// __shared__ double tempR[(TILE_DIM + 2)*(TILE_DIM + 2)];
__shared__ double tempE_prev[(TILE_DIM + 2)*(TILE_DIM + 2)];
size_t LocalWidth = TILE_DIM + 2;
// Global Indexing
size_t row = blockIdx.y * blockDim.y + threadIdx.y + 1;
size_t col = blockIdx.x * blockDim.x + threadIdx.x + 1;
size_t index = row * WIDTH + col;
size_t local_index = (threadIdx.y + 1)* LocalWidth + threadIdx.x + 1;
// copy all
if (row >= 1 && row <= m && col >= 1 && col <= n ){
tempE_prev[local_index] = E_prev_1D[index];
}
// copy Right & Left
if (threadIdx.x + 1 == TILE_DIM){
tempE_prev[local_index+1] = E_prev_1D[index+1];
tempE_prev[local_index-TILE_DIM] = E_prev_1D[index-TILE_DIM];
}
// copy Up & Down
if (threadIdx.y + 1== TILE_DIM){
tempE_prev[local_index + LocalWidth] = E_prev_1D[index + WIDTH];
tempE_prev[local_index - TILE_DIM*LocalWidth] = E_prev_1D[index - TILE_DIM*WIDTH];
}
// Make sure all threads get to this point before proceeding!
__syncthreads(); // This will syncronize threads in a block
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
double e_temp;
double r_temp = R_1D[index];
// PDE
e_temp = tempE_prev[local_index] + alpha * (tempE_prev[local_index + 1] + tempE_prev[local_index- 1] - 4 * tempE_prev[local_index] + tempE_prev[local_index + LocalWidth] + tempE_prev[local_index- LocalWidth]);
//ODE
e_temp = e_temp - dt * (kk * e_temp * (e_temp - a) * (e_temp - 1) + e_temp * r_temp);
r_temp = r_temp + dt * (epsilon + M1 * r_temp / (e_temp + M2)) * (-r_temp - kk * e_temp * (e_temp - b - 1));
E_1D[index] = e_temp;
R_1D[index] = r_temp;
}
}
void simV1(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version1_PDE<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
simulate_version1_ODE<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
hipStreamSynchronize(0);
// end timer
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
void simV2(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version2<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
hipStreamSynchronize(0);
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
void simV3(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version3<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
hipStreamSynchronize(0);
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
void simV4(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version4<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
hipStreamSynchronize(0);
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
//************************************************* Kernels End *****************************************
// --------------------------------------------- Optimaztion Start-------------------------------------------------
__global__ void simulate_version5(const double alpha, const int n, const int m, const double dt, double *E_1D, double *E_prev_1D, double *R_1D, const int WIDTH)
{
int RADIUS = 1;
int row = blockIdx.y * blockDim.y + threadIdx.y + RADIUS;
int col = blockIdx.x * blockDim.x + threadIdx.x + RADIUS;
int index = row * WIDTH + col;
double t = 0.0;
int niter = 0;
double T = 1000.0;
while (t < T) {
t += dt;
niter++;
if (row <= m) {
E_prev_1D[row * WIDTH + 0] = E_prev_1D[row * WIDTH + 2];
E_prev_1D[row * WIDTH + (n + 1)] = E_prev_1D[row * WIDTH + (n - 1)];
}
if (col <= n) {
E_prev_1D[0 * WIDTH + col] = E_prev_1D[2 * WIDTH + col];
E_prev_1D[(m + 1) * WIDTH + col] = E_prev_1D[(m - 1) * WIDTH + col];
}
__syncthreads();
if (row >= 1 && row <= m && col >= 1 && col <= n)
{
// PDE
E_1D[row * WIDTH + col] = E_prev_1D[row * WIDTH + col] + alpha * (E_prev_1D[row * WIDTH + (col + 1)] + E_prev_1D[row * WIDTH + (col - 1)] - 4 * E_prev_1D[row * WIDTH + col] + E_prev_1D[(row + 1) * WIDTH + col] + E_prev_1D[(row - 1) * WIDTH + col]);
//ODE
E_1D[index] = E_1D[index] - dt * (kk * E_1D[index] * (E_1D[index] - a) * (E_1D[index] - 1) + E_1D[index] * R_1D[index]);
R_1D[index] = R_1D[index] + dt * (epsilon + M1 * R_1D[index] / (E_1D[index] + M2)) * (-R_1D[index] - kk * E_1D[index] * (E_1D[index] - b - 1));
// double *tmp2 = E_1D;
// E_1D = E_prev_1D;
// E_prev_1D = tmp2;
E_prev_1D[index] = E_1D[index];
}
//E_prev_1D[index] = E_1D[index];
//if (row == 1 && col == 1) {
//double *tmp2 = E_1D;
//E_1D = E_prev_1D;
//E_prev_1D = tmp2;
//}
__syncthreads();
}
}
void simV5(const double alpha, const int n, const int m, const double dt, int WIDTH, double* time, double *d_E_1D, double *d_E_prev_1D, double *d_R_1D)
{
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
// Start the timer
double t0 = getTime();
simulate_version5<<<num_blocks, block_size>>>(alpha, n, m, dt, d_E_1D, d_E_prev_1D, d_R_1D, WIDTH);
hipStreamSynchronize(0);
double time_elapsed = getTime() - t0;
*time += time_elapsed;
}
// --------------------------------------------- Optimation End -------------------------------------------------
//================================================== Utilities =========================================
// Mirror Ghost Boundries
void mirrorBoundries(double *E_prev_1D, double* d_E_prev_1D, const int n, const int m, const int WIDTH){
// ==================================================
const dim3 block_size(TILE_DIM, TILE_DIM);
const dim3 num_blocks(WIDTH / block_size.x, WIDTH / block_size.y);
int Total_Bytes = WIDTH * WIDTH * sizeof(double);
// Copy to GPU
hipMemcpy(d_E_prev_1D, E_prev_1D, Total_Bytes, hipMemcpyHostToDevice);
mirrorkernel<<<num_blocks, block_size>>>(d_E_prev_1D, n, m ,WIDTH);
hipMemcpy(E_prev_1D, d_E_prev_1D, Total_Bytes, hipMemcpyDeviceToHost);
}
// Mirror Ghost Boundries
void mirrorBoundries(double *E_prev_1D, const int n, const int m, const int WIDTH)
{
/*
* Copy data from boundary of the computational box
* to the padding region, set up for differencing
* on the boundary of the computational box
* Using mirror boundaries
*/
int col, row;
for (row = 1; row <= m; row++)
{
//E_prev[row][0] = E_prev[row][2];
E_prev_1D[row * WIDTH + 0] = E_prev_1D[row * WIDTH + 2];
}
for (row = 1; row <= m; row++)
{
//E_prev[row][n + 1] = E_prev[row][n - 1];
E_prev_1D[row * WIDTH + (n + 1)] = E_prev_1D[row * WIDTH + (n - 1)];
}
for (col = 1; col <= n; col++)
{
//E_prev[0][col] = E_prev[2][col];
E_prev_1D[0 * WIDTH + col] = E_prev_1D[2 * WIDTH + col];
}
for (col = 1; col <= n; col++)
{
//E_prev[m + 1][col] = E_prev[m - 1][col];
E_prev_1D[(m + 1) * WIDTH + col] = E_prev_1D[(m - 1) * WIDTH + col];
}
}
// Allocate a 2D array
double **alloc2D(int m, int n)
{
double **E;
int nx = n, ny = m;
E = (double **)malloc(sizeof(double *) * ny + sizeof(double) * nx * ny);
assert(E);
int row;
for (row = 0; row < ny; row++)
E[row] = (double *)(E + ny) + row * nx;
return (E);
}
/* Reports statistics about the computation
These values should not vary (except to within roundoff)
when we use different numbers of processes to solve the problem
*/
double stats(double **E, int m, int n, double *_mx)
{
double mx = -1;
double l2norm = 0;
int col, row;
for (row = 1; row <= m; row++)
for (col = 1; col <= n; col++)
{
l2norm += E[row][col] * E[row][col];
if (E[row][col] > mx)
mx = E[row][col];
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
double stats1D(double *E, int m, int n, double *_mx, int WIDTH)
{
double mx = -1;
double l2norm = 0;
int col, row;
int index = -1;
for (row = 1; row <= m; row++)
{
for (col = 1; col <= n; col++)
{
index = row * WIDTH + col;
l2norm += E[index] * E[index];
if (E[index] > mx)
{
mx = E[index];
}
}
}
*_mx = mx;
l2norm /= (double)((m) * (n));
l2norm = sqrt(l2norm);
return l2norm;
}
// Timer
// Make successive calls and take a difference to get the elapsed time.
static const double kMicro = 1.0e-6;
double getTime()
{
struct timeval TV;
struct timezone TZ;
const int RC = gettimeofday(&TV, &TZ);
if (RC == -1)
{
cerr << "ERROR: Bad call to gettimeofday" << endl;
return (-1);
}
return (((double)TV.tv_sec) + kMicro * ((double)TV.tv_usec));
}
void cmdLine(int argc, char *argv[], double &T, int &n, int &px, int &py, int &plot_freq, int &no_comm, int &num_threads)
{
/// Command line arguments
// Default value of the domain sizes
static struct option long_options[] = {
{"n", required_argument, 0, 'n'},
{"px", required_argument, 0, 'x'},
{"py", required_argument, 0, 'y'},
{"tfinal", required_argument, 0, 't'},
{"plot", required_argument, 0, 'p'},
{"nocomm", no_argument, 0, 'k'},
{"numthreads", required_argument, 0, 'o'},
};
// Process command line arguments
int ac;
for (ac = 1; ac < argc; ac++)
{
int c;
while ((c = getopt_long(argc, argv, "n:x:y:t:kp:o:", long_options, NULL)) != -1)
{
switch (c)
{
// Size of the computational box
case 'n':
n = atoi(optarg);
break;
// X processor geometry
case 'x':
px = atoi(optarg);
// Y processor geometry
case 'y':
py = atoi(optarg);
// Length of simulation, in simulated time units
case 't':
T = atof(optarg);
break;
// Turn off communication
case 'k':
no_comm = 1;
break;
// Plot the excitation variable
case 'p':
plot_freq = atoi(optarg);
break;
// Plot the excitation variable
case 'o':
num_threads = atoi(optarg);
break;
// Error
default:
printf("Usage: a.out [-n <domain size>] [-t <final time >]\n\t [-p <plot frequency>]\n\t[-px <x processor geometry> [-py <y proc. geometry] [-k turn off communication] [-o <Number of OpenMP threads>]\n");
exit(-1);
}
}
}
}
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